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38
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1 /**
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2 ******************************************************************************
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3 * @file stm32f4xx_hal_nor.c
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4 * @author MCD Application Team
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5 * @version V1.2.0
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6 * @date 26-December-2014
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7 * @brief NOR HAL module driver.
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8 * This file provides a generic firmware to drive NOR memories mounted
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9 * as external device.
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10 *
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11 @verbatim
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12 ==============================================================================
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13 ##### How to use this driver #####
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14 ==============================================================================
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15 [..]
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16 This driver is a generic layered driver which contains a set of APIs used to
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17 control NOR flash memories. It uses the FMC/FSMC layer functions to interface
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18 with NOR devices. This driver is used as follows:
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19
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20 (+) NOR flash memory configuration sequence using the function HAL_NOR_Init()
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21 with control and timing parameters for both normal and extended mode.
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22
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23 (+) Read NOR flash memory manufacturer code and device IDs using the function
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24 HAL_NOR_Read_ID(). The read information is stored in the NOR_ID_TypeDef
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25 structure declared by the function caller.
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26
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27 (+) Access NOR flash memory by read/write data unit operations using the functions
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28 HAL_NOR_Read(), HAL_NOR_Program().
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29
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30 (+) Perform NOR flash erase block/chip operations using the functions
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31 HAL_NOR_Erase_Block() and HAL_NOR_Erase_Chip().
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32
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33 (+) Read the NOR flash CFI (common flash interface) IDs using the function
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34 HAL_NOR_Read_CFI(). The read information is stored in the NOR_CFI_TypeDef
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35 structure declared by the function caller.
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36
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37 (+) You can also control the NOR device by calling the control APIs HAL_NOR_WriteOperation_Enable()/
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38 HAL_NOR_WriteOperation_Disable() to respectively enable/disable the NOR write operation
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39
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40 (+) You can monitor the NOR device HAL state by calling the function
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41 HAL_NOR_GetState()
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42 [..]
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43 (@) This driver is a set of generic APIs which handle standard NOR flash operations.
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44 If a NOR flash device contains different operations and/or implementations,
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45 it should be implemented separately.
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46
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47 *** NOR HAL driver macros list ***
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48 =============================================
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49 [..]
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50 Below the list of most used macros in NOR HAL driver.
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51
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52 (+) NOR_WRITE : NOR memory write data to specified address
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53
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54 @endverbatim
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55 ******************************************************************************
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56 * @attention
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57 *
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58 * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
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59 *
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60 * Redistribution and use in source and binary forms, with or without modification,
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61 * are permitted provided that the following conditions are met:
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62 * 1. Redistributions of source code must retain the above copyright notice,
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63 * this list of conditions and the following disclaimer.
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64 * 2. Redistributions in binary form must reproduce the above copyright notice,
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65 * this list of conditions and the following disclaimer in the documentation
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66 * and/or other materials provided with the distribution.
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67 * 3. Neither the name of STMicroelectronics nor the names of its contributors
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68 * may be used to endorse or promote products derived from this software
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69 * without specific prior written permission.
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70 *
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71 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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72 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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73 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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74 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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75 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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76 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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77 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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78 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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79 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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80 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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81 *
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82 ******************************************************************************
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83 */
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84
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85 /* Includes ------------------------------------------------------------------*/
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86 #include "stm32f4xx_hal.h"
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87
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88 /** @addtogroup STM32F4xx_HAL_Driver
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89 * @{
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90 */
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91
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92 /** @defgroup NOR NOR
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93 * @brief NOR driver modules
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94 * @{
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95 */
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96 #ifdef HAL_NOR_MODULE_ENABLED
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97 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
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98
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99 /* Private typedef -----------------------------------------------------------*/
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100 /* Private define ------------------------------------------------------------*/
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101 /* Private macro -------------------------------------------------------------*/
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102 /* Private variables ---------------------------------------------------------*/
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103 /* Private functions ---------------------------------------------------------*/
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104 /* Exported functions --------------------------------------------------------*/
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105 /** @defgroup NOR_Exported_Functions NOR Exported Functions
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106 * @{
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107 */
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108
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109 /** @defgroup NOR_Exported_Functions_Group1 Initialization and de-initialization functions
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110 * @brief Initialization and Configuration functions
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111 *
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112 @verbatim
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113 ==============================================================================
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114 ##### NOR Initialization and de_initialization functions #####
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115 ==============================================================================
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116 [..]
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117 This section provides functions allowing to initialize/de-initialize
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118 the NOR memory
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119
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120 @endverbatim
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121 * @{
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122 */
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123
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124 /**
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125 * @brief Perform the NOR memory Initialization sequence
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126 * @param hnor: pointer to the NOR handle
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127 * @param Timing: pointer to NOR control timing structure
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128 * @param ExtTiming: pointer to NOR extended mode timing structure
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129 * @retval HAL status
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130 */
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131 HAL_StatusTypeDef HAL_NOR_Init(NOR_HandleTypeDef *hnor, FMC_NORSRAM_TimingTypeDef *Timing, FMC_NORSRAM_TimingTypeDef *ExtTiming)
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132 {
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133 /* Check the NOR handle parameter */
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134 if(hnor == NULL)
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135 {
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136 return HAL_ERROR;
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137 }
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138
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139 if(hnor->State == HAL_NOR_STATE_RESET)
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140 {
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141 /* Initialize the low level hardware (MSP) */
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142 HAL_NOR_MspInit(hnor);
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143 }
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144
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145 /* Initialize NOR control Interface */
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146 FMC_NORSRAM_Init(hnor->Instance, &(hnor->Init));
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147
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148 /* Initialize NOR timing Interface */
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149 FMC_NORSRAM_Timing_Init(hnor->Instance, Timing, hnor->Init.NSBank);
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150
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151 /* Initialize NOR extended mode timing Interface */
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152 FMC_NORSRAM_Extended_Timing_Init(hnor->Extended, ExtTiming, hnor->Init.NSBank, hnor->Init.ExtendedMode);
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153
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154 /* Enable the NORSRAM device */
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155 __FMC_NORSRAM_ENABLE(hnor->Instance, hnor->Init.NSBank);
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156
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157 /* Check the NOR controller state */
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158 hnor->State = HAL_NOR_STATE_READY;
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159
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160 return HAL_OK;
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161 }
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162
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163 /**
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164 * @brief Perform NOR memory De-Initialization sequence
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165 * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
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166 * the configuration information for NOR module.
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167 * @retval HAL status
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168 */
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169 HAL_StatusTypeDef HAL_NOR_DeInit(NOR_HandleTypeDef *hnor)
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170 {
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171 /* De-Initialize the low level hardware (MSP) */
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172 HAL_NOR_MspDeInit(hnor);
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173
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174 /* Configure the NOR registers with their reset values */
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175 FMC_NORSRAM_DeInit(hnor->Instance, hnor->Extended, hnor->Init.NSBank);
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176
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177 /* Update the NOR controller state */
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178 hnor->State = HAL_NOR_STATE_RESET;
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179
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180 /* Release Lock */
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181 __HAL_UNLOCK(hnor);
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182
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183 return HAL_OK;
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184 }
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185
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186 /**
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187 * @brief NOR MSP Init
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188 * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
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189 * the configuration information for NOR module.
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190 * @retval None
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191 */
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192 __weak void HAL_NOR_MspInit(NOR_HandleTypeDef *hnor)
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193 {
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194 /* NOTE : This function Should not be modified, when the callback is needed,
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195 the HAL_NOR_MspInit could be implemented in the user file
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196 */
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197 }
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198
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199 /**
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200 * @brief NOR MSP DeInit
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201 * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
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202 * the configuration information for NOR module.
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203 * @retval None
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204 */
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205 __weak void HAL_NOR_MspDeInit(NOR_HandleTypeDef *hnor)
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206 {
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207 /* NOTE : This function Should not be modified, when the callback is needed,
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208 the HAL_NOR_MspDeInit could be implemented in the user file
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209 */
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210 }
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211
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212 /**
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213 * @brief NOR BSP Wait for Ready/Busy signal
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214 * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
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215 * the configuration information for NOR module.
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216 * @param Timeout: Maximum timeout value
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217 * @retval None
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218 */
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219 __weak void HAL_NOR_MspWait(NOR_HandleTypeDef *hnor, uint32_t Timeout)
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220 {
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221 /* NOTE : This function Should not be modified, when the callback is needed,
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222 the HAL_NOR_BspWait could be implemented in the user file
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223 */
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224 }
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225
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226 /**
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227 * @}
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228 */
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229
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230 /** @defgroup NOR_Exported_Functions_Group2 Input and Output functions
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231 * @brief Input Output and memory control functions
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232 *
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233 @verbatim
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234 ==============================================================================
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235 ##### NOR Input and Output functions #####
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236 ==============================================================================
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237 [..]
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238 This section provides functions allowing to use and control the NOR memory
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239
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240 @endverbatim
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241 * @{
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242 */
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243
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244 /**
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245 * @brief Read NOR flash IDs
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246 * @param hnor: pointer to the NOR handle
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247 * @param pNOR_ID : pointer to NOR ID structure
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248 * @retval HAL status
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249 */
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250 HAL_StatusTypeDef HAL_NOR_Read_ID(NOR_HandleTypeDef *hnor, NOR_IDTypeDef *pNOR_ID)
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251 {
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252 uint32_t deviceAddress = 0;
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253
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254 /* Process Locked */
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255 __HAL_LOCK(hnor);
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256
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257 /* Check the NOR controller state */
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258 if(hnor->State == HAL_NOR_STATE_BUSY)
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259 {
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260 return HAL_BUSY;
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261 }
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262
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263 /* Select the NOR device address */
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264 if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
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265 {
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266 deviceAddress = NOR_MEMORY_ADRESS1;
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267 }
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268 else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
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269 {
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270 deviceAddress = NOR_MEMORY_ADRESS2;
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271 }
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272 else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
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273 {
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274 deviceAddress = NOR_MEMORY_ADRESS3;
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275 }
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276 else /* FMC_NORSRAM_BANK4 */
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277 {
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278 deviceAddress = NOR_MEMORY_ADRESS4;
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279 }
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280
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281 /* Update the NOR controller state */
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282 hnor->State = HAL_NOR_STATE_BUSY;
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283
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284 /* Send read ID command */
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285 NOR_WRITE(NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, 0x0555), 0x00AA);
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286 NOR_WRITE(NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, 0x02AA), 0x0055);
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287 NOR_WRITE(NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, 0x0555), 0x0090);
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288
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289 /* Read the NOR IDs */
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290 pNOR_ID->Manufacturer_Code = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, MC_ADDRESS);
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291 pNOR_ID->Device_Code1 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, DEVICE_CODE1_ADDR);
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292 pNOR_ID->Device_Code2 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, DEVICE_CODE2_ADDR);
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293 pNOR_ID->Device_Code3 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, DEVICE_CODE3_ADDR);
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294
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295 /* Check the NOR controller state */
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296 hnor->State = HAL_NOR_STATE_READY;
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297
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298 /* Process unlocked */
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299 __HAL_UNLOCK(hnor);
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300
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301 return HAL_OK;
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302 }
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303
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304 /**
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305 * @brief Returns the NOR memory to Read mode.
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306 * @param hnor: pointer to the NOR handle
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307 * @retval HAL status
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308 */
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309 HAL_StatusTypeDef HAL_NOR_ReturnToReadMode(NOR_HandleTypeDef *hnor)
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310 {
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311 uint32_t deviceAddress = 0;
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312
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313 /* Process Locked */
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314 __HAL_LOCK(hnor);
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315
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316 /* Check the NOR controller state */
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317 if(hnor->State == HAL_NOR_STATE_BUSY)
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318 {
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319 return HAL_BUSY;
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320 }
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321
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322 /* Select the NOR device address */
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323 if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
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324 {
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325 deviceAddress = NOR_MEMORY_ADRESS1;
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326 }
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327 else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
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328 {
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329 deviceAddress = NOR_MEMORY_ADRESS2;
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330 }
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331 else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
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332 {
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333 deviceAddress = NOR_MEMORY_ADRESS3;
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334 }
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335 else /* FMC_NORSRAM_BANK4 */
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336 {
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337 deviceAddress = NOR_MEMORY_ADRESS4;
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338 }
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339
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340 NOR_WRITE(deviceAddress, 0x00F0);
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341
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342 /* Check the NOR controller state */
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343 hnor->State = HAL_NOR_STATE_READY;
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344
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345 /* Process unlocked */
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346 __HAL_UNLOCK(hnor);
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347
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348 return HAL_OK;
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349 }
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350
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351 /**
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352 * @brief Read data from NOR memory
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353 * @param hnor: pointer to the NOR handle
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354 * @param pAddress: pointer to Device address
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355 * @param pData : pointer to read data
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356 * @retval HAL status
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357 */
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358 HAL_StatusTypeDef HAL_NOR_Read(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData)
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359 {
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360 uint32_t deviceAddress = 0;
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361
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362 /* Process Locked */
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363 __HAL_LOCK(hnor);
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364
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365 /* Check the NOR controller state */
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366 if(hnor->State == HAL_NOR_STATE_BUSY)
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367 {
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368 return HAL_BUSY;
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369 }
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370
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371 /* Select the NOR device address */
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372 if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
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373 {
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374 deviceAddress = NOR_MEMORY_ADRESS1;
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375 }
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376 else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
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377 {
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378 deviceAddress = NOR_MEMORY_ADRESS2;
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379 }
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380 else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
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381 {
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382 deviceAddress = NOR_MEMORY_ADRESS3;
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383 }
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384 else /* FMC_NORSRAM_BANK4 */
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385 {
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386 deviceAddress = NOR_MEMORY_ADRESS4;
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387 }
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388
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389 /* Update the NOR controller state */
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390 hnor->State = HAL_NOR_STATE_BUSY;
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391
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392 /* Send read data command */
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393 NOR_WRITE(NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, 0x00555), 0x00AA);
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394 NOR_WRITE(NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, 0x002AA), 0x0055);
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395 NOR_WRITE(pAddress, 0x00F0);
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396
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397 /* Read the data */
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398 *pData = *(__IO uint32_t *)pAddress;
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399
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400 /* Check the NOR controller state */
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401 hnor->State = HAL_NOR_STATE_READY;
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402
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403 /* Process unlocked */
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404 __HAL_UNLOCK(hnor);
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405
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406 return HAL_OK;
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407 }
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408
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409 /**
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410 * @brief Program data to NOR memory
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411 * @param hnor: pointer to the NOR handle
|
|
|
412 * @param pAddress: Device address
|
|
|
413 * @param pData : pointer to the data to write
|
|
|
414 * @retval HAL status
|
|
|
415 */
|
|
|
416 HAL_StatusTypeDef HAL_NOR_Program(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData)
|
|
|
417 {
|
|
|
418 uint32_t deviceAddress = 0;
|
|
|
419
|
|
|
420 /* Process Locked */
|
|
|
421 __HAL_LOCK(hnor);
|
|
|
422
|
|
|
423 /* Check the NOR controller state */
|
|
|
424 if(hnor->State == HAL_NOR_STATE_BUSY)
|
|
|
425 {
|
|
|
426 return HAL_BUSY;
|
|
|
427 }
|
|
|
428
|
|
|
429 /* Select the NOR device address */
|
|
|
430 if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
|
|
|
431 {
|
|
|
432 deviceAddress = NOR_MEMORY_ADRESS1;
|
|
|
433 }
|
|
|
434 else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
|
|
|
435 {
|
|
|
436 deviceAddress = NOR_MEMORY_ADRESS2;
|
|
|
437 }
|
|
|
438 else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
|
|
|
439 {
|
|
|
440 deviceAddress = NOR_MEMORY_ADRESS3;
|
|
|
441 }
|
|
|
442 else /* FMC_NORSRAM_BANK4 */
|
|
|
443 {
|
|
|
444 deviceAddress = NOR_MEMORY_ADRESS4;
|
|
|
445 }
|
|
|
446
|
|
|
447 /* Update the NOR controller state */
|
|
|
448 hnor->State = HAL_NOR_STATE_BUSY;
|
|
|
449
|
|
|
450 /* Send program data command */
|
|
|
451 NOR_WRITE(NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, 0x0555), 0x00AA);
|
|
|
452 NOR_WRITE(NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, 0x02AA), 0x0055);
|
|
|
453 NOR_WRITE(NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, 0x0555), 0x00A0);
|
|
|
454
|
|
|
455 /* Write the data */
|
|
|
456 NOR_WRITE(pAddress, *pData);
|
|
|
457
|
|
|
458 /* Check the NOR controller state */
|
|
|
459 hnor->State = HAL_NOR_STATE_READY;
|
|
|
460
|
|
|
461 /* Process unlocked */
|
|
|
462 __HAL_UNLOCK(hnor);
|
|
|
463
|
|
|
464 return HAL_OK;
|
|
|
465 }
|
|
|
466
|
|
|
467 /**
|
|
|
468 * @brief Reads a half-word buffer from the NOR memory.
|
|
|
469 * @param hnor: pointer to the NOR handle
|
|
|
470 * @param uwAddress: NOR memory internal address to read from.
|
|
|
471 * @param pData: pointer to the buffer that receives the data read from the
|
|
|
472 * NOR memory.
|
|
|
473 * @param uwBufferSize : number of Half word to read.
|
|
|
474 * @retval HAL status
|
|
|
475 */
|
|
|
476 HAL_StatusTypeDef HAL_NOR_ReadBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize)
|
|
|
477 {
|
|
|
478 uint32_t deviceAddress = 0;
|
|
|
479
|
|
|
480 /* Process Locked */
|
|
|
481 __HAL_LOCK(hnor);
|
|
|
482
|
|
|
483 /* Check the NOR controller state */
|
|
|
484 if(hnor->State == HAL_NOR_STATE_BUSY)
|
|
|
485 {
|
|
|
486 return HAL_BUSY;
|
|
|
487 }
|
|
|
488
|
|
|
489 /* Select the NOR device address */
|
|
|
490 if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
|
|
|
491 {
|
|
|
492 deviceAddress = NOR_MEMORY_ADRESS1;
|
|
|
493 }
|
|
|
494 else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
|
|
|
495 {
|
|
|
496 deviceAddress = NOR_MEMORY_ADRESS2;
|
|
|
497 }
|
|
|
498 else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
|
|
|
499 {
|
|
|
500 deviceAddress = NOR_MEMORY_ADRESS3;
|
|
|
501 }
|
|
|
502 else /* FMC_NORSRAM_BANK4 */
|
|
|
503 {
|
|
|
504 deviceAddress = NOR_MEMORY_ADRESS4;
|
|
|
505 }
|
|
|
506
|
|
|
507 /* Update the NOR controller state */
|
|
|
508 hnor->State = HAL_NOR_STATE_BUSY;
|
|
|
509
|
|
|
510 /* Send read data command */
|
|
|
511 NOR_WRITE(NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, 0x00555), 0x00AA);
|
|
|
512 NOR_WRITE(NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, 0x002AA), 0x0055);
|
|
|
513 NOR_WRITE(uwAddress, 0x00F0);
|
|
|
514
|
|
|
515 /* Read buffer */
|
|
|
516 while( uwBufferSize > 0)
|
|
|
517 {
|
|
|
518 *pData++ = *(__IO uint16_t *)uwAddress;
|
|
|
519 uwAddress += 2;
|
|
|
520 uwBufferSize--;
|
|
|
521 }
|
|
|
522
|
|
|
523 /* Check the NOR controller state */
|
|
|
524 hnor->State = HAL_NOR_STATE_READY;
|
|
|
525
|
|
|
526 /* Process unlocked */
|
|
|
527 __HAL_UNLOCK(hnor);
|
|
|
528
|
|
|
529 return HAL_OK;
|
|
|
530 }
|
|
|
531
|
|
|
532 /**
|
|
|
533 * @brief Writes a half-word buffer to the NOR memory. This function must be used
|
|
|
534 only with S29GL128P NOR memory.
|
|
|
535 * @param hnor: pointer to the NOR handle
|
|
|
536 * @param uwAddress: NOR memory internal start write address
|
|
|
537 * @param pData: pointer to source data buffer.
|
|
|
538 * @param uwBufferSize: Size of the buffer to write
|
|
|
539 * @retval HAL status
|
|
|
540 */
|
|
|
541 HAL_StatusTypeDef HAL_NOR_ProgramBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize)
|
|
|
542 {
|
|
|
543 uint32_t lastloadedaddress = 0;
|
|
|
544 uint32_t currentaddress = 0;
|
|
|
545 uint32_t endaddress = 0;
|
|
|
546 uint32_t deviceAddress = 0;
|
|
|
547
|
|
|
548 /* Process Locked */
|
|
|
549 __HAL_LOCK(hnor);
|
|
|
550
|
|
|
551 /* Check the NOR controller state */
|
|
|
552 if(hnor->State == HAL_NOR_STATE_BUSY)
|
|
|
553 {
|
|
|
554 return HAL_BUSY;
|
|
|
555 }
|
|
|
556
|
|
|
557 /* Select the NOR device address */
|
|
|
558 if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
|
|
|
559 {
|
|
|
560 deviceAddress = NOR_MEMORY_ADRESS1;
|
|
|
561 }
|
|
|
562 else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
|
|
|
563 {
|
|
|
564 deviceAddress = NOR_MEMORY_ADRESS2;
|
|
|
565 }
|
|
|
566 else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
|
|
|
567 {
|
|
|
568 deviceAddress = NOR_MEMORY_ADRESS3;
|
|
|
569 }
|
|
|
570 else /* FMC_NORSRAM_BANK4 */
|
|
|
571 {
|
|
|
572 deviceAddress = NOR_MEMORY_ADRESS4;
|
|
|
573 }
|
|
|
574
|
|
|
575 /* Update the NOR controller state */
|
|
|
576 hnor->State = HAL_NOR_STATE_BUSY;
|
|
|
577
|
|
|
578 /* Initialize variables */
|
|
|
579 currentaddress = uwAddress;
|
|
|
580 endaddress = uwAddress + uwBufferSize - 1;
|
|
|
581 lastloadedaddress = uwAddress;
|
|
|
582
|
|
|
583 /* Issue unlock command sequence */
|
|
|
584 NOR_WRITE(NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, 0x0555), 0x00AA);
|
|
|
585 NOR_WRITE(NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, 0x02AA), 0x0055);
|
|
|
586
|
|
|
587 /* Write Buffer Load Command */
|
|
|
588 NOR_WRITE(NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, uwAddress), 0x25);
|
|
|
589 NOR_WRITE(NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, uwAddress), (uwBufferSize - 1));
|
|
|
590
|
|
|
591 /* Load Data into NOR Buffer */
|
|
|
592 while(currentaddress <= endaddress)
|
|
|
593 {
|
|
|
594 /* Store last loaded address & data value (for polling) */
|
|
|
595 lastloadedaddress = currentaddress;
|
|
|
596
|
|
|
597 NOR_WRITE(NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, currentaddress), *pData++);
|
|
|
598
|
|
|
599 currentaddress += 1;
|
|
|
600 }
|
|
|
601
|
|
|
602 NOR_WRITE(NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, lastloadedaddress), 0x29);
|
|
|
603
|
|
|
604 /* Check the NOR controller state */
|
|
|
605 hnor->State = HAL_NOR_STATE_READY;
|
|
|
606
|
|
|
607 /* Process unlocked */
|
|
|
608 __HAL_UNLOCK(hnor);
|
|
|
609
|
|
|
610 return HAL_OK;
|
|
|
611
|
|
|
612 }
|
|
|
613
|
|
|
614 /**
|
|
|
615 * @brief Erase the specified block of the NOR memory
|
|
|
616 * @param hnor: pointer to the NOR handle
|
|
|
617 * @param BlockAddress : Block to erase address
|
|
|
618 * @param Address: Device address
|
|
|
619 * @retval HAL status
|
|
|
620 */
|
|
|
621 HAL_StatusTypeDef HAL_NOR_Erase_Block(NOR_HandleTypeDef *hnor, uint32_t BlockAddress, uint32_t Address)
|
|
|
622 {
|
|
|
623 uint32_t deviceAddress = 0;
|
|
|
624
|
|
|
625 /* Process Locked */
|
|
|
626 __HAL_LOCK(hnor);
|
|
|
627
|
|
|
628 /* Check the NOR controller state */
|
|
|
629 if(hnor->State == HAL_NOR_STATE_BUSY)
|
|
|
630 {
|
|
|
631 return HAL_BUSY;
|
|
|
632 }
|
|
|
633
|
|
|
634 /* Select the NOR device address */
|
|
|
635 if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
|
|
|
636 {
|
|
|
637 deviceAddress = NOR_MEMORY_ADRESS1;
|
|
|
638 }
|
|
|
639 else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
|
|
|
640 {
|
|
|
641 deviceAddress = NOR_MEMORY_ADRESS2;
|
|
|
642 }
|
|
|
643 else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
|
|
|
644 {
|
|
|
645 deviceAddress = NOR_MEMORY_ADRESS3;
|
|
|
646 }
|
|
|
647 else /* FMC_NORSRAM_BANK4 */
|
|
|
648 {
|
|
|
649 deviceAddress = NOR_MEMORY_ADRESS4;
|
|
|
650 }
|
|
|
651
|
|
|
652 /* Update the NOR controller state */
|
|
|
653 hnor->State = HAL_NOR_STATE_BUSY;
|
|
|
654
|
|
|
655 /* Send block erase command sequence */
|
|
|
656 NOR_WRITE(NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, 0x0555), 0x00AA);
|
|
|
657 NOR_WRITE(NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, 0x02AA), 0x0055);
|
|
|
658 NOR_WRITE(NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, 0x0555), 0x0080);
|
|
|
659 NOR_WRITE(NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, 0x0555), 0x00AA);
|
|
|
660 NOR_WRITE(NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, 0x02AA), 0x0055);
|
|
|
661 NOR_WRITE((uint32_t)(BlockAddress + Address), 0x30);
|
|
|
662
|
|
|
663 /* Check the NOR memory status and update the controller state */
|
|
|
664 hnor->State = HAL_NOR_STATE_READY;
|
|
|
665
|
|
|
666 /* Process unlocked */
|
|
|
667 __HAL_UNLOCK(hnor);
|
|
|
668
|
|
|
669 return HAL_OK;
|
|
|
670
|
|
|
671 }
|
|
|
672
|
|
|
673 /**
|
|
|
674 * @brief Erase the entire NOR chip.
|
|
|
675 * @param hnor: pointer to the NOR handle
|
|
|
676 * @param Address : Device address
|
|
|
677 * @retval HAL status
|
|
|
678 */
|
|
|
679 HAL_StatusTypeDef HAL_NOR_Erase_Chip(NOR_HandleTypeDef *hnor, uint32_t Address)
|
|
|
680 {
|
|
|
681 uint32_t deviceAddress = 0;
|
|
|
682
|
|
|
683 /* Process Locked */
|
|
|
684 __HAL_LOCK(hnor);
|
|
|
685
|
|
|
686 /* Check the NOR controller state */
|
|
|
687 if(hnor->State == HAL_NOR_STATE_BUSY)
|
|
|
688 {
|
|
|
689 return HAL_BUSY;
|
|
|
690 }
|
|
|
691
|
|
|
692 /* Select the NOR device address */
|
|
|
693 if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
|
|
|
694 {
|
|
|
695 deviceAddress = NOR_MEMORY_ADRESS1;
|
|
|
696 }
|
|
|
697 else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
|
|
|
698 {
|
|
|
699 deviceAddress = NOR_MEMORY_ADRESS2;
|
|
|
700 }
|
|
|
701 else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
|
|
|
702 {
|
|
|
703 deviceAddress = NOR_MEMORY_ADRESS3;
|
|
|
704 }
|
|
|
705 else /* FMC_NORSRAM_BANK4 */
|
|
|
706 {
|
|
|
707 deviceAddress = NOR_MEMORY_ADRESS4;
|
|
|
708 }
|
|
|
709
|
|
|
710 /* Update the NOR controller state */
|
|
|
711 hnor->State = HAL_NOR_STATE_BUSY;
|
|
|
712
|
|
|
713 /* Send NOR chip erase command sequence */
|
|
|
714 NOR_WRITE(NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, 0x0555), 0x00AA);
|
|
|
715 NOR_WRITE(NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, 0x02AA), 0x0055);
|
|
|
716 NOR_WRITE(NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, 0x0555), 0x0080);
|
|
|
717 NOR_WRITE(NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, 0x0555), 0x00AA);
|
|
|
718 NOR_WRITE(NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, 0x02AA), 0x0055);
|
|
|
719 NOR_WRITE(NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, 0x0555), 0x0010);
|
|
|
720
|
|
|
721 /* Check the NOR memory status and update the controller state */
|
|
|
722 hnor->State = HAL_NOR_STATE_READY;
|
|
|
723
|
|
|
724 /* Process unlocked */
|
|
|
725 __HAL_UNLOCK(hnor);
|
|
|
726
|
|
|
727 return HAL_OK;
|
|
|
728 }
|
|
|
729
|
|
|
730 /**
|
|
|
731 * @brief Read NOR flash CFI IDs
|
|
|
732 * @param hnor: pointer to the NOR handle
|
|
|
733 * @param pNOR_CFI : pointer to NOR CFI IDs structure
|
|
|
734 * @retval HAL status
|
|
|
735 */
|
|
|
736 HAL_StatusTypeDef HAL_NOR_Read_CFI(NOR_HandleTypeDef *hnor, NOR_CFITypeDef *pNOR_CFI)
|
|
|
737 {
|
|
|
738 uint32_t deviceAddress = 0;
|
|
|
739
|
|
|
740 /* Process Locked */
|
|
|
741 __HAL_LOCK(hnor);
|
|
|
742
|
|
|
743 /* Check the NOR controller state */
|
|
|
744 if(hnor->State == HAL_NOR_STATE_BUSY)
|
|
|
745 {
|
|
|
746 return HAL_BUSY;
|
|
|
747 }
|
|
|
748
|
|
|
749 /* Select the NOR device address */
|
|
|
750 if (hnor->Init.NSBank == FMC_NORSRAM_BANK1)
|
|
|
751 {
|
|
|
752 deviceAddress = NOR_MEMORY_ADRESS1;
|
|
|
753 }
|
|
|
754 else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2)
|
|
|
755 {
|
|
|
756 deviceAddress = NOR_MEMORY_ADRESS2;
|
|
|
757 }
|
|
|
758 else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3)
|
|
|
759 {
|
|
|
760 deviceAddress = NOR_MEMORY_ADRESS3;
|
|
|
761 }
|
|
|
762 else /* FMC_NORSRAM_BANK4 */
|
|
|
763 {
|
|
|
764 deviceAddress = NOR_MEMORY_ADRESS4;
|
|
|
765 }
|
|
|
766
|
|
|
767 /* Update the NOR controller state */
|
|
|
768 hnor->State = HAL_NOR_STATE_BUSY;
|
|
|
769
|
|
|
770 /* Send read CFI query command */
|
|
|
771 NOR_WRITE(NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, 0x0055), 0x0098);
|
|
|
772
|
|
|
773 /* read the NOR CFI information */
|
|
|
774 pNOR_CFI->CFI_1 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, CFI1_ADDRESS);
|
|
|
775 pNOR_CFI->CFI_2 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, CFI2_ADDRESS);
|
|
|
776 pNOR_CFI->CFI_3 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, CFI3_ADDRESS);
|
|
|
777 pNOR_CFI->CFI_4 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, CFI4_ADDRESS);
|
|
|
778
|
|
|
779 /* Check the NOR controller state */
|
|
|
780 hnor->State = HAL_NOR_STATE_READY;
|
|
|
781
|
|
|
782 /* Process unlocked */
|
|
|
783 __HAL_UNLOCK(hnor);
|
|
|
784
|
|
|
785 return HAL_OK;
|
|
|
786 }
|
|
|
787
|
|
|
788 /**
|
|
|
789 * @}
|
|
|
790 */
|
|
|
791
|
|
|
792 /** @defgroup NOR_Exported_Functions_Group3 Control functions
|
|
|
793 * @brief management functions
|
|
|
794 *
|
|
|
795 @verbatim
|
|
|
796 ==============================================================================
|
|
|
797 ##### NOR Control functions #####
|
|
|
798 ==============================================================================
|
|
|
799 [..]
|
|
|
800 This subsection provides a set of functions allowing to control dynamically
|
|
|
801 the NOR interface.
|
|
|
802
|
|
|
803 @endverbatim
|
|
|
804 * @{
|
|
|
805 */
|
|
|
806
|
|
|
807 /**
|
|
|
808 * @brief Enables dynamically NOR write operation.
|
|
|
809 * @param hnor: pointer to the NOR handle
|
|
|
810 * @retval HAL status
|
|
|
811 */
|
|
|
812 HAL_StatusTypeDef HAL_NOR_WriteOperation_Enable(NOR_HandleTypeDef *hnor)
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813 {
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814 /* Process Locked */
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815 __HAL_LOCK(hnor);
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816
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817 /* Enable write operation */
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818 FMC_NORSRAM_WriteOperation_Enable(hnor->Instance, hnor->Init.NSBank);
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819
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820 /* Update the NOR controller state */
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821 hnor->State = HAL_NOR_STATE_READY;
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822
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823 /* Process unlocked */
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824 __HAL_UNLOCK(hnor);
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825
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826 return HAL_OK;
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827 }
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828
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829 /**
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830 * @brief Disables dynamically NOR write operation.
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831 * @param hnor: pointer to the NOR handle
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832 * @retval HAL status
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833 */
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834 HAL_StatusTypeDef HAL_NOR_WriteOperation_Disable(NOR_HandleTypeDef *hnor)
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835 {
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836 /* Process Locked */
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837 __HAL_LOCK(hnor);
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|
|
838
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839 /* Update the SRAM controller state */
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840 hnor->State = HAL_NOR_STATE_BUSY;
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841
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842 /* Disable write operation */
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843 FMC_NORSRAM_WriteOperation_Disable(hnor->Instance, hnor->Init.NSBank);
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|
|
844
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845 /* Update the NOR controller state */
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846 hnor->State = HAL_NOR_STATE_PROTECTED;
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847
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848 /* Process unlocked */
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849 __HAL_UNLOCK(hnor);
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850
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851 return HAL_OK;
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852 }
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853
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854 /**
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855 * @}
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856 */
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857
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858 /** @defgroup NOR_Exported_Functions_Group4 State functions
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859 * @brief Peripheral State functions
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|
860 *
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861 @verbatim
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|
862 ==============================================================================
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863 ##### NOR State functions #####
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|
864 ==============================================================================
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|
865 [..]
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|
866 This subsection permits to get in run-time the status of the NOR controller
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|
|
867 and the data flow.
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|
|
868
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869 @endverbatim
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|
870 * @{
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|
871 */
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|
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872
|
|
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873 /**
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874 * @brief return the NOR controller state
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|
|
875 * @param hnor: pointer to the NOR handle
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|
|
876 * @retval NOR controller state
|
|
|
877 */
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878 HAL_NOR_StateTypeDef HAL_NOR_GetState(NOR_HandleTypeDef *hnor)
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879 {
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880 return hnor->State;
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|
|
881 }
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|
|
882
|
|
|
883 /**
|
|
|
884 * @brief Returns the NOR operation status.
|
|
|
885 * @param hnor: pointer to the NOR handle
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|
|
886 * @param Address: Device address
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|
|
887 * @param Timeout: NOR programming Timeout
|
|
|
888 * @retval NOR_Status: The returned value can be: HAL_NOR_STATUS_SUCCESS, HAL_NOR_STATUS_ERROR
|
|
|
889 * or HAL_NOR_STATUS_TIMEOUT
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|
|
890 */
|
|
|
891 HAL_NOR_StatusTypeDef HAL_NOR_GetStatus(NOR_HandleTypeDef *hnor, uint32_t Address, uint32_t Timeout)
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|
892 {
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|
|
893 HAL_NOR_StatusTypeDef status = HAL_NOR_STATUS_ONGOING;
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|
|
894 uint16_t tmpSR1 = 0, tmpSR2 = 0;
|
|
|
895 uint32_t tickstart = 0;
|
|
|
896
|
|
|
897 /* Poll on NOR memory Ready/Busy signal ------------------------------------*/
|
|
|
898 HAL_NOR_MspWait(hnor, Timeout);
|
|
|
899
|
|
|
900 /* Get the NOR memory operation status -------------------------------------*/
|
|
|
901
|
|
|
902 /* Get tick */
|
|
|
903 tickstart = HAL_GetTick();
|
|
|
904 while((status != HAL_NOR_STATUS_SUCCESS ) && (status != HAL_NOR_STATUS_TIMEOUT))
|
|
|
905 {
|
|
|
906 /* Check for the Timeout */
|
|
|
907 if(Timeout != HAL_MAX_DELAY)
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|
|
908 {
|
|
|
909 if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
|
|
|
910 {
|
|
|
911 status = HAL_NOR_STATUS_TIMEOUT;
|
|
|
912 }
|
|
|
913 }
|
|
|
914
|
|
|
915 /* Read NOR status register (DQ6 and DQ5) */
|
|
|
916 tmpSR1 = *(__IO uint16_t *)Address;
|
|
|
917 tmpSR2 = *(__IO uint16_t *)Address;
|
|
|
918
|
|
|
919 /* If DQ6 did not toggle between the two reads then return HAL_NOR_STATUS_SUCCESS */
|
|
|
920 if((tmpSR1 & 0x0040) == (tmpSR2 & 0x0040))
|
|
|
921 {
|
|
|
922 return HAL_NOR_STATUS_SUCCESS ;
|
|
|
923 }
|
|
|
924
|
|
|
925 if((tmpSR1 & 0x0020) == 0x0020)
|
|
|
926 {
|
|
|
927 status = HAL_NOR_STATUS_ONGOING;
|
|
|
928 }
|
|
|
929
|
|
|
930 tmpSR1 = *(__IO uint16_t *)Address;
|
|
|
931 tmpSR2 = *(__IO uint16_t *)Address;
|
|
|
932
|
|
|
933 /* If DQ6 did not toggle between the two reads then return HAL_NOR_STATUS_SUCCESS */
|
|
|
934 if((tmpSR1 & 0x0040) == (tmpSR2 & 0x0040))
|
|
|
935 {
|
|
|
936 return HAL_NOR_STATUS_SUCCESS;
|
|
|
937 }
|
|
|
938 if((tmpSR1 & 0x0020) == 0x0020)
|
|
|
939 {
|
|
|
940 return HAL_NOR_STATUS_ERROR;
|
|
|
941 }
|
|
|
942 }
|
|
|
943
|
|
|
944 /* Return the operation status */
|
|
|
945 return status;
|
|
|
946 }
|
|
|
947
|
|
|
948 /**
|
|
|
949 * @}
|
|
|
950 */
|
|
|
951
|
|
|
952
|
|
|
953 /**
|
|
|
954 * @}
|
|
|
955 */
|
|
|
956 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
|
|
|
957 #endif /* HAL_NOR_MODULE_ENABLED */
|
|
|
958 /**
|
|
|
959 * @}
|
|
|
960 */
|
|
|
961
|
|
|
962 /**
|
|
|
963 * @}
|
|
|
964 */
|
|
|
965
|
|
|
966 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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