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comparison Common/Drivers/STM32F4xx_HAL_DRIVER_v120/Src/stm32f4xx_hal_nor.c @ 38:5f11787b4f42
include in ostc4 repository
author | heinrichsweikamp |
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date | Sat, 28 Apr 2018 11:52:34 +0200 |
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1 /** | |
2 ****************************************************************************** | |
3 * @file stm32f4xx_hal_nor.c | |
4 * @author MCD Application Team | |
5 * @version V1.2.0 | |
6 * @date 26-December-2014 | |
7 * @brief NOR HAL module driver. | |
8 * This file provides a generic firmware to drive NOR memories mounted | |
9 * as external device. | |
10 * | |
11 @verbatim | |
12 ============================================================================== | |
13 ##### How to use this driver ##### | |
14 ============================================================================== | |
15 [..] | |
16 This driver is a generic layered driver which contains a set of APIs used to | |
17 control NOR flash memories. It uses the FMC/FSMC layer functions to interface | |
18 with NOR devices. This driver is used as follows: | |
19 | |
20 (+) NOR flash memory configuration sequence using the function HAL_NOR_Init() | |
21 with control and timing parameters for both normal and extended mode. | |
22 | |
23 (+) Read NOR flash memory manufacturer code and device IDs using the function | |
24 HAL_NOR_Read_ID(). The read information is stored in the NOR_ID_TypeDef | |
25 structure declared by the function caller. | |
26 | |
27 (+) Access NOR flash memory by read/write data unit operations using the functions | |
28 HAL_NOR_Read(), HAL_NOR_Program(). | |
29 | |
30 (+) Perform NOR flash erase block/chip operations using the functions | |
31 HAL_NOR_Erase_Block() and HAL_NOR_Erase_Chip(). | |
32 | |
33 (+) Read the NOR flash CFI (common flash interface) IDs using the function | |
34 HAL_NOR_Read_CFI(). The read information is stored in the NOR_CFI_TypeDef | |
35 structure declared by the function caller. | |
36 | |
37 (+) You can also control the NOR device by calling the control APIs HAL_NOR_WriteOperation_Enable()/ | |
38 HAL_NOR_WriteOperation_Disable() to respectively enable/disable the NOR write operation | |
39 | |
40 (+) You can monitor the NOR device HAL state by calling the function | |
41 HAL_NOR_GetState() | |
42 [..] | |
43 (@) This driver is a set of generic APIs which handle standard NOR flash operations. | |
44 If a NOR flash device contains different operations and/or implementations, | |
45 it should be implemented separately. | |
46 | |
47 *** NOR HAL driver macros list *** | |
48 ============================================= | |
49 [..] | |
50 Below the list of most used macros in NOR HAL driver. | |
51 | |
52 (+) NOR_WRITE : NOR memory write data to specified address | |
53 | |
54 @endverbatim | |
55 ****************************************************************************** | |
56 * @attention | |
57 * | |
58 * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2> | |
59 * | |
60 * Redistribution and use in source and binary forms, with or without modification, | |
61 * are permitted provided that the following conditions are met: | |
62 * 1. Redistributions of source code must retain the above copyright notice, | |
63 * this list of conditions and the following disclaimer. | |
64 * 2. Redistributions in binary form must reproduce the above copyright notice, | |
65 * this list of conditions and the following disclaimer in the documentation | |
66 * and/or other materials provided with the distribution. | |
67 * 3. Neither the name of STMicroelectronics nor the names of its contributors | |
68 * may be used to endorse or promote products derived from this software | |
69 * without specific prior written permission. | |
70 * | |
71 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" | |
72 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE | |
73 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE | |
74 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE | |
75 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL | |
76 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR | |
77 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER | |
78 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, | |
79 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE | |
80 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | |
81 * | |
82 ****************************************************************************** | |
83 */ | |
84 | |
85 /* Includes ------------------------------------------------------------------*/ | |
86 #include "stm32f4xx_hal.h" | |
87 | |
88 /** @addtogroup STM32F4xx_HAL_Driver | |
89 * @{ | |
90 */ | |
91 | |
92 /** @defgroup NOR NOR | |
93 * @brief NOR driver modules | |
94 * @{ | |
95 */ | |
96 #ifdef HAL_NOR_MODULE_ENABLED | |
97 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) | |
98 | |
99 /* Private typedef -----------------------------------------------------------*/ | |
100 /* Private define ------------------------------------------------------------*/ | |
101 /* Private macro -------------------------------------------------------------*/ | |
102 /* Private variables ---------------------------------------------------------*/ | |
103 /* Private functions ---------------------------------------------------------*/ | |
104 /* Exported functions --------------------------------------------------------*/ | |
105 /** @defgroup NOR_Exported_Functions NOR Exported Functions | |
106 * @{ | |
107 */ | |
108 | |
109 /** @defgroup NOR_Exported_Functions_Group1 Initialization and de-initialization functions | |
110 * @brief Initialization and Configuration functions | |
111 * | |
112 @verbatim | |
113 ============================================================================== | |
114 ##### NOR Initialization and de_initialization functions ##### | |
115 ============================================================================== | |
116 [..] | |
117 This section provides functions allowing to initialize/de-initialize | |
118 the NOR memory | |
119 | |
120 @endverbatim | |
121 * @{ | |
122 */ | |
123 | |
124 /** | |
125 * @brief Perform the NOR memory Initialization sequence | |
126 * @param hnor: pointer to the NOR handle | |
127 * @param Timing: pointer to NOR control timing structure | |
128 * @param ExtTiming: pointer to NOR extended mode timing structure | |
129 * @retval HAL status | |
130 */ | |
131 HAL_StatusTypeDef HAL_NOR_Init(NOR_HandleTypeDef *hnor, FMC_NORSRAM_TimingTypeDef *Timing, FMC_NORSRAM_TimingTypeDef *ExtTiming) | |
132 { | |
133 /* Check the NOR handle parameter */ | |
134 if(hnor == NULL) | |
135 { | |
136 return HAL_ERROR; | |
137 } | |
138 | |
139 if(hnor->State == HAL_NOR_STATE_RESET) | |
140 { | |
141 /* Initialize the low level hardware (MSP) */ | |
142 HAL_NOR_MspInit(hnor); | |
143 } | |
144 | |
145 /* Initialize NOR control Interface */ | |
146 FMC_NORSRAM_Init(hnor->Instance, &(hnor->Init)); | |
147 | |
148 /* Initialize NOR timing Interface */ | |
149 FMC_NORSRAM_Timing_Init(hnor->Instance, Timing, hnor->Init.NSBank); | |
150 | |
151 /* Initialize NOR extended mode timing Interface */ | |
152 FMC_NORSRAM_Extended_Timing_Init(hnor->Extended, ExtTiming, hnor->Init.NSBank, hnor->Init.ExtendedMode); | |
153 | |
154 /* Enable the NORSRAM device */ | |
155 __FMC_NORSRAM_ENABLE(hnor->Instance, hnor->Init.NSBank); | |
156 | |
157 /* Check the NOR controller state */ | |
158 hnor->State = HAL_NOR_STATE_READY; | |
159 | |
160 return HAL_OK; | |
161 } | |
162 | |
163 /** | |
164 * @brief Perform NOR memory De-Initialization sequence | |
165 * @param hnor: pointer to a NOR_HandleTypeDef structure that contains | |
166 * the configuration information for NOR module. | |
167 * @retval HAL status | |
168 */ | |
169 HAL_StatusTypeDef HAL_NOR_DeInit(NOR_HandleTypeDef *hnor) | |
170 { | |
171 /* De-Initialize the low level hardware (MSP) */ | |
172 HAL_NOR_MspDeInit(hnor); | |
173 | |
174 /* Configure the NOR registers with their reset values */ | |
175 FMC_NORSRAM_DeInit(hnor->Instance, hnor->Extended, hnor->Init.NSBank); | |
176 | |
177 /* Update the NOR controller state */ | |
178 hnor->State = HAL_NOR_STATE_RESET; | |
179 | |
180 /* Release Lock */ | |
181 __HAL_UNLOCK(hnor); | |
182 | |
183 return HAL_OK; | |
184 } | |
185 | |
186 /** | |
187 * @brief NOR MSP Init | |
188 * @param hnor: pointer to a NOR_HandleTypeDef structure that contains | |
189 * the configuration information for NOR module. | |
190 * @retval None | |
191 */ | |
192 __weak void HAL_NOR_MspInit(NOR_HandleTypeDef *hnor) | |
193 { | |
194 /* NOTE : This function Should not be modified, when the callback is needed, | |
195 the HAL_NOR_MspInit could be implemented in the user file | |
196 */ | |
197 } | |
198 | |
199 /** | |
200 * @brief NOR MSP DeInit | |
201 * @param hnor: pointer to a NOR_HandleTypeDef structure that contains | |
202 * the configuration information for NOR module. | |
203 * @retval None | |
204 */ | |
205 __weak void HAL_NOR_MspDeInit(NOR_HandleTypeDef *hnor) | |
206 { | |
207 /* NOTE : This function Should not be modified, when the callback is needed, | |
208 the HAL_NOR_MspDeInit could be implemented in the user file | |
209 */ | |
210 } | |
211 | |
212 /** | |
213 * @brief NOR BSP Wait for Ready/Busy signal | |
214 * @param hnor: pointer to a NOR_HandleTypeDef structure that contains | |
215 * the configuration information for NOR module. | |
216 * @param Timeout: Maximum timeout value | |
217 * @retval None | |
218 */ | |
219 __weak void HAL_NOR_MspWait(NOR_HandleTypeDef *hnor, uint32_t Timeout) | |
220 { | |
221 /* NOTE : This function Should not be modified, when the callback is needed, | |
222 the HAL_NOR_BspWait could be implemented in the user file | |
223 */ | |
224 } | |
225 | |
226 /** | |
227 * @} | |
228 */ | |
229 | |
230 /** @defgroup NOR_Exported_Functions_Group2 Input and Output functions | |
231 * @brief Input Output and memory control functions | |
232 * | |
233 @verbatim | |
234 ============================================================================== | |
235 ##### NOR Input and Output functions ##### | |
236 ============================================================================== | |
237 [..] | |
238 This section provides functions allowing to use and control the NOR memory | |
239 | |
240 @endverbatim | |
241 * @{ | |
242 */ | |
243 | |
244 /** | |
245 * @brief Read NOR flash IDs | |
246 * @param hnor: pointer to the NOR handle | |
247 * @param pNOR_ID : pointer to NOR ID structure | |
248 * @retval HAL status | |
249 */ | |
250 HAL_StatusTypeDef HAL_NOR_Read_ID(NOR_HandleTypeDef *hnor, NOR_IDTypeDef *pNOR_ID) | |
251 { | |
252 uint32_t deviceAddress = 0; | |
253 | |
254 /* Process Locked */ | |
255 __HAL_LOCK(hnor); | |
256 | |
257 /* Check the NOR controller state */ | |
258 if(hnor->State == HAL_NOR_STATE_BUSY) | |
259 { | |
260 return HAL_BUSY; | |
261 } | |
262 | |
263 /* Select the NOR device address */ | |
264 if (hnor->Init.NSBank == FMC_NORSRAM_BANK1) | |
265 { | |
266 deviceAddress = NOR_MEMORY_ADRESS1; | |
267 } | |
268 else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2) | |
269 { | |
270 deviceAddress = NOR_MEMORY_ADRESS2; | |
271 } | |
272 else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3) | |
273 { | |
274 deviceAddress = NOR_MEMORY_ADRESS3; | |
275 } | |
276 else /* FMC_NORSRAM_BANK4 */ | |
277 { | |
278 deviceAddress = NOR_MEMORY_ADRESS4; | |
279 } | |
280 | |
281 /* Update the NOR controller state */ | |
282 hnor->State = HAL_NOR_STATE_BUSY; | |
283 | |
284 /* Send read ID command */ | |
285 NOR_WRITE(NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, 0x0555), 0x00AA); | |
286 NOR_WRITE(NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, 0x02AA), 0x0055); | |
287 NOR_WRITE(NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, 0x0555), 0x0090); | |
288 | |
289 /* Read the NOR IDs */ | |
290 pNOR_ID->Manufacturer_Code = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, MC_ADDRESS); | |
291 pNOR_ID->Device_Code1 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, DEVICE_CODE1_ADDR); | |
292 pNOR_ID->Device_Code2 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, DEVICE_CODE2_ADDR); | |
293 pNOR_ID->Device_Code3 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, DEVICE_CODE3_ADDR); | |
294 | |
295 /* Check the NOR controller state */ | |
296 hnor->State = HAL_NOR_STATE_READY; | |
297 | |
298 /* Process unlocked */ | |
299 __HAL_UNLOCK(hnor); | |
300 | |
301 return HAL_OK; | |
302 } | |
303 | |
304 /** | |
305 * @brief Returns the NOR memory to Read mode. | |
306 * @param hnor: pointer to the NOR handle | |
307 * @retval HAL status | |
308 */ | |
309 HAL_StatusTypeDef HAL_NOR_ReturnToReadMode(NOR_HandleTypeDef *hnor) | |
310 { | |
311 uint32_t deviceAddress = 0; | |
312 | |
313 /* Process Locked */ | |
314 __HAL_LOCK(hnor); | |
315 | |
316 /* Check the NOR controller state */ | |
317 if(hnor->State == HAL_NOR_STATE_BUSY) | |
318 { | |
319 return HAL_BUSY; | |
320 } | |
321 | |
322 /* Select the NOR device address */ | |
323 if (hnor->Init.NSBank == FMC_NORSRAM_BANK1) | |
324 { | |
325 deviceAddress = NOR_MEMORY_ADRESS1; | |
326 } | |
327 else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2) | |
328 { | |
329 deviceAddress = NOR_MEMORY_ADRESS2; | |
330 } | |
331 else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3) | |
332 { | |
333 deviceAddress = NOR_MEMORY_ADRESS3; | |
334 } | |
335 else /* FMC_NORSRAM_BANK4 */ | |
336 { | |
337 deviceAddress = NOR_MEMORY_ADRESS4; | |
338 } | |
339 | |
340 NOR_WRITE(deviceAddress, 0x00F0); | |
341 | |
342 /* Check the NOR controller state */ | |
343 hnor->State = HAL_NOR_STATE_READY; | |
344 | |
345 /* Process unlocked */ | |
346 __HAL_UNLOCK(hnor); | |
347 | |
348 return HAL_OK; | |
349 } | |
350 | |
351 /** | |
352 * @brief Read data from NOR memory | |
353 * @param hnor: pointer to the NOR handle | |
354 * @param pAddress: pointer to Device address | |
355 * @param pData : pointer to read data | |
356 * @retval HAL status | |
357 */ | |
358 HAL_StatusTypeDef HAL_NOR_Read(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData) | |
359 { | |
360 uint32_t deviceAddress = 0; | |
361 | |
362 /* Process Locked */ | |
363 __HAL_LOCK(hnor); | |
364 | |
365 /* Check the NOR controller state */ | |
366 if(hnor->State == HAL_NOR_STATE_BUSY) | |
367 { | |
368 return HAL_BUSY; | |
369 } | |
370 | |
371 /* Select the NOR device address */ | |
372 if (hnor->Init.NSBank == FMC_NORSRAM_BANK1) | |
373 { | |
374 deviceAddress = NOR_MEMORY_ADRESS1; | |
375 } | |
376 else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2) | |
377 { | |
378 deviceAddress = NOR_MEMORY_ADRESS2; | |
379 } | |
380 else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3) | |
381 { | |
382 deviceAddress = NOR_MEMORY_ADRESS3; | |
383 } | |
384 else /* FMC_NORSRAM_BANK4 */ | |
385 { | |
386 deviceAddress = NOR_MEMORY_ADRESS4; | |
387 } | |
388 | |
389 /* Update the NOR controller state */ | |
390 hnor->State = HAL_NOR_STATE_BUSY; | |
391 | |
392 /* Send read data command */ | |
393 NOR_WRITE(NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, 0x00555), 0x00AA); | |
394 NOR_WRITE(NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, 0x002AA), 0x0055); | |
395 NOR_WRITE(pAddress, 0x00F0); | |
396 | |
397 /* Read the data */ | |
398 *pData = *(__IO uint32_t *)pAddress; | |
399 | |
400 /* Check the NOR controller state */ | |
401 hnor->State = HAL_NOR_STATE_READY; | |
402 | |
403 /* Process unlocked */ | |
404 __HAL_UNLOCK(hnor); | |
405 | |
406 return HAL_OK; | |
407 } | |
408 | |
409 /** | |
410 * @brief Program data to NOR memory | |
411 * @param hnor: pointer to the NOR handle | |
412 * @param pAddress: Device address | |
413 * @param pData : pointer to the data to write | |
414 * @retval HAL status | |
415 */ | |
416 HAL_StatusTypeDef HAL_NOR_Program(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData) | |
417 { | |
418 uint32_t deviceAddress = 0; | |
419 | |
420 /* Process Locked */ | |
421 __HAL_LOCK(hnor); | |
422 | |
423 /* Check the NOR controller state */ | |
424 if(hnor->State == HAL_NOR_STATE_BUSY) | |
425 { | |
426 return HAL_BUSY; | |
427 } | |
428 | |
429 /* Select the NOR device address */ | |
430 if (hnor->Init.NSBank == FMC_NORSRAM_BANK1) | |
431 { | |
432 deviceAddress = NOR_MEMORY_ADRESS1; | |
433 } | |
434 else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2) | |
435 { | |
436 deviceAddress = NOR_MEMORY_ADRESS2; | |
437 } | |
438 else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3) | |
439 { | |
440 deviceAddress = NOR_MEMORY_ADRESS3; | |
441 } | |
442 else /* FMC_NORSRAM_BANK4 */ | |
443 { | |
444 deviceAddress = NOR_MEMORY_ADRESS4; | |
445 } | |
446 | |
447 /* Update the NOR controller state */ | |
448 hnor->State = HAL_NOR_STATE_BUSY; | |
449 | |
450 /* Send program data command */ | |
451 NOR_WRITE(NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, 0x0555), 0x00AA); | |
452 NOR_WRITE(NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, 0x02AA), 0x0055); | |
453 NOR_WRITE(NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, 0x0555), 0x00A0); | |
454 | |
455 /* Write the data */ | |
456 NOR_WRITE(pAddress, *pData); | |
457 | |
458 /* Check the NOR controller state */ | |
459 hnor->State = HAL_NOR_STATE_READY; | |
460 | |
461 /* Process unlocked */ | |
462 __HAL_UNLOCK(hnor); | |
463 | |
464 return HAL_OK; | |
465 } | |
466 | |
467 /** | |
468 * @brief Reads a half-word buffer from the NOR memory. | |
469 * @param hnor: pointer to the NOR handle | |
470 * @param uwAddress: NOR memory internal address to read from. | |
471 * @param pData: pointer to the buffer that receives the data read from the | |
472 * NOR memory. | |
473 * @param uwBufferSize : number of Half word to read. | |
474 * @retval HAL status | |
475 */ | |
476 HAL_StatusTypeDef HAL_NOR_ReadBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize) | |
477 { | |
478 uint32_t deviceAddress = 0; | |
479 | |
480 /* Process Locked */ | |
481 __HAL_LOCK(hnor); | |
482 | |
483 /* Check the NOR controller state */ | |
484 if(hnor->State == HAL_NOR_STATE_BUSY) | |
485 { | |
486 return HAL_BUSY; | |
487 } | |
488 | |
489 /* Select the NOR device address */ | |
490 if (hnor->Init.NSBank == FMC_NORSRAM_BANK1) | |
491 { | |
492 deviceAddress = NOR_MEMORY_ADRESS1; | |
493 } | |
494 else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2) | |
495 { | |
496 deviceAddress = NOR_MEMORY_ADRESS2; | |
497 } | |
498 else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3) | |
499 { | |
500 deviceAddress = NOR_MEMORY_ADRESS3; | |
501 } | |
502 else /* FMC_NORSRAM_BANK4 */ | |
503 { | |
504 deviceAddress = NOR_MEMORY_ADRESS4; | |
505 } | |
506 | |
507 /* Update the NOR controller state */ | |
508 hnor->State = HAL_NOR_STATE_BUSY; | |
509 | |
510 /* Send read data command */ | |
511 NOR_WRITE(NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, 0x00555), 0x00AA); | |
512 NOR_WRITE(NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, 0x002AA), 0x0055); | |
513 NOR_WRITE(uwAddress, 0x00F0); | |
514 | |
515 /* Read buffer */ | |
516 while( uwBufferSize > 0) | |
517 { | |
518 *pData++ = *(__IO uint16_t *)uwAddress; | |
519 uwAddress += 2; | |
520 uwBufferSize--; | |
521 } | |
522 | |
523 /* Check the NOR controller state */ | |
524 hnor->State = HAL_NOR_STATE_READY; | |
525 | |
526 /* Process unlocked */ | |
527 __HAL_UNLOCK(hnor); | |
528 | |
529 return HAL_OK; | |
530 } | |
531 | |
532 /** | |
533 * @brief Writes a half-word buffer to the NOR memory. This function must be used | |
534 only with S29GL128P NOR memory. | |
535 * @param hnor: pointer to the NOR handle | |
536 * @param uwAddress: NOR memory internal start write address | |
537 * @param pData: pointer to source data buffer. | |
538 * @param uwBufferSize: Size of the buffer to write | |
539 * @retval HAL status | |
540 */ | |
541 HAL_StatusTypeDef HAL_NOR_ProgramBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize) | |
542 { | |
543 uint32_t lastloadedaddress = 0; | |
544 uint32_t currentaddress = 0; | |
545 uint32_t endaddress = 0; | |
546 uint32_t deviceAddress = 0; | |
547 | |
548 /* Process Locked */ | |
549 __HAL_LOCK(hnor); | |
550 | |
551 /* Check the NOR controller state */ | |
552 if(hnor->State == HAL_NOR_STATE_BUSY) | |
553 { | |
554 return HAL_BUSY; | |
555 } | |
556 | |
557 /* Select the NOR device address */ | |
558 if (hnor->Init.NSBank == FMC_NORSRAM_BANK1) | |
559 { | |
560 deviceAddress = NOR_MEMORY_ADRESS1; | |
561 } | |
562 else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2) | |
563 { | |
564 deviceAddress = NOR_MEMORY_ADRESS2; | |
565 } | |
566 else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3) | |
567 { | |
568 deviceAddress = NOR_MEMORY_ADRESS3; | |
569 } | |
570 else /* FMC_NORSRAM_BANK4 */ | |
571 { | |
572 deviceAddress = NOR_MEMORY_ADRESS4; | |
573 } | |
574 | |
575 /* Update the NOR controller state */ | |
576 hnor->State = HAL_NOR_STATE_BUSY; | |
577 | |
578 /* Initialize variables */ | |
579 currentaddress = uwAddress; | |
580 endaddress = uwAddress + uwBufferSize - 1; | |
581 lastloadedaddress = uwAddress; | |
582 | |
583 /* Issue unlock command sequence */ | |
584 NOR_WRITE(NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, 0x0555), 0x00AA); | |
585 NOR_WRITE(NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, 0x02AA), 0x0055); | |
586 | |
587 /* Write Buffer Load Command */ | |
588 NOR_WRITE(NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, uwAddress), 0x25); | |
589 NOR_WRITE(NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, uwAddress), (uwBufferSize - 1)); | |
590 | |
591 /* Load Data into NOR Buffer */ | |
592 while(currentaddress <= endaddress) | |
593 { | |
594 /* Store last loaded address & data value (for polling) */ | |
595 lastloadedaddress = currentaddress; | |
596 | |
597 NOR_WRITE(NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, currentaddress), *pData++); | |
598 | |
599 currentaddress += 1; | |
600 } | |
601 | |
602 NOR_WRITE(NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, lastloadedaddress), 0x29); | |
603 | |
604 /* Check the NOR controller state */ | |
605 hnor->State = HAL_NOR_STATE_READY; | |
606 | |
607 /* Process unlocked */ | |
608 __HAL_UNLOCK(hnor); | |
609 | |
610 return HAL_OK; | |
611 | |
612 } | |
613 | |
614 /** | |
615 * @brief Erase the specified block of the NOR memory | |
616 * @param hnor: pointer to the NOR handle | |
617 * @param BlockAddress : Block to erase address | |
618 * @param Address: Device address | |
619 * @retval HAL status | |
620 */ | |
621 HAL_StatusTypeDef HAL_NOR_Erase_Block(NOR_HandleTypeDef *hnor, uint32_t BlockAddress, uint32_t Address) | |
622 { | |
623 uint32_t deviceAddress = 0; | |
624 | |
625 /* Process Locked */ | |
626 __HAL_LOCK(hnor); | |
627 | |
628 /* Check the NOR controller state */ | |
629 if(hnor->State == HAL_NOR_STATE_BUSY) | |
630 { | |
631 return HAL_BUSY; | |
632 } | |
633 | |
634 /* Select the NOR device address */ | |
635 if (hnor->Init.NSBank == FMC_NORSRAM_BANK1) | |
636 { | |
637 deviceAddress = NOR_MEMORY_ADRESS1; | |
638 } | |
639 else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2) | |
640 { | |
641 deviceAddress = NOR_MEMORY_ADRESS2; | |
642 } | |
643 else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3) | |
644 { | |
645 deviceAddress = NOR_MEMORY_ADRESS3; | |
646 } | |
647 else /* FMC_NORSRAM_BANK4 */ | |
648 { | |
649 deviceAddress = NOR_MEMORY_ADRESS4; | |
650 } | |
651 | |
652 /* Update the NOR controller state */ | |
653 hnor->State = HAL_NOR_STATE_BUSY; | |
654 | |
655 /* Send block erase command sequence */ | |
656 NOR_WRITE(NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, 0x0555), 0x00AA); | |
657 NOR_WRITE(NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, 0x02AA), 0x0055); | |
658 NOR_WRITE(NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, 0x0555), 0x0080); | |
659 NOR_WRITE(NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, 0x0555), 0x00AA); | |
660 NOR_WRITE(NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, 0x02AA), 0x0055); | |
661 NOR_WRITE((uint32_t)(BlockAddress + Address), 0x30); | |
662 | |
663 /* Check the NOR memory status and update the controller state */ | |
664 hnor->State = HAL_NOR_STATE_READY; | |
665 | |
666 /* Process unlocked */ | |
667 __HAL_UNLOCK(hnor); | |
668 | |
669 return HAL_OK; | |
670 | |
671 } | |
672 | |
673 /** | |
674 * @brief Erase the entire NOR chip. | |
675 * @param hnor: pointer to the NOR handle | |
676 * @param Address : Device address | |
677 * @retval HAL status | |
678 */ | |
679 HAL_StatusTypeDef HAL_NOR_Erase_Chip(NOR_HandleTypeDef *hnor, uint32_t Address) | |
680 { | |
681 uint32_t deviceAddress = 0; | |
682 | |
683 /* Process Locked */ | |
684 __HAL_LOCK(hnor); | |
685 | |
686 /* Check the NOR controller state */ | |
687 if(hnor->State == HAL_NOR_STATE_BUSY) | |
688 { | |
689 return HAL_BUSY; | |
690 } | |
691 | |
692 /* Select the NOR device address */ | |
693 if (hnor->Init.NSBank == FMC_NORSRAM_BANK1) | |
694 { | |
695 deviceAddress = NOR_MEMORY_ADRESS1; | |
696 } | |
697 else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2) | |
698 { | |
699 deviceAddress = NOR_MEMORY_ADRESS2; | |
700 } | |
701 else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3) | |
702 { | |
703 deviceAddress = NOR_MEMORY_ADRESS3; | |
704 } | |
705 else /* FMC_NORSRAM_BANK4 */ | |
706 { | |
707 deviceAddress = NOR_MEMORY_ADRESS4; | |
708 } | |
709 | |
710 /* Update the NOR controller state */ | |
711 hnor->State = HAL_NOR_STATE_BUSY; | |
712 | |
713 /* Send NOR chip erase command sequence */ | |
714 NOR_WRITE(NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, 0x0555), 0x00AA); | |
715 NOR_WRITE(NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, 0x02AA), 0x0055); | |
716 NOR_WRITE(NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, 0x0555), 0x0080); | |
717 NOR_WRITE(NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, 0x0555), 0x00AA); | |
718 NOR_WRITE(NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, 0x02AA), 0x0055); | |
719 NOR_WRITE(NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, 0x0555), 0x0010); | |
720 | |
721 /* Check the NOR memory status and update the controller state */ | |
722 hnor->State = HAL_NOR_STATE_READY; | |
723 | |
724 /* Process unlocked */ | |
725 __HAL_UNLOCK(hnor); | |
726 | |
727 return HAL_OK; | |
728 } | |
729 | |
730 /** | |
731 * @brief Read NOR flash CFI IDs | |
732 * @param hnor: pointer to the NOR handle | |
733 * @param pNOR_CFI : pointer to NOR CFI IDs structure | |
734 * @retval HAL status | |
735 */ | |
736 HAL_StatusTypeDef HAL_NOR_Read_CFI(NOR_HandleTypeDef *hnor, NOR_CFITypeDef *pNOR_CFI) | |
737 { | |
738 uint32_t deviceAddress = 0; | |
739 | |
740 /* Process Locked */ | |
741 __HAL_LOCK(hnor); | |
742 | |
743 /* Check the NOR controller state */ | |
744 if(hnor->State == HAL_NOR_STATE_BUSY) | |
745 { | |
746 return HAL_BUSY; | |
747 } | |
748 | |
749 /* Select the NOR device address */ | |
750 if (hnor->Init.NSBank == FMC_NORSRAM_BANK1) | |
751 { | |
752 deviceAddress = NOR_MEMORY_ADRESS1; | |
753 } | |
754 else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2) | |
755 { | |
756 deviceAddress = NOR_MEMORY_ADRESS2; | |
757 } | |
758 else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3) | |
759 { | |
760 deviceAddress = NOR_MEMORY_ADRESS3; | |
761 } | |
762 else /* FMC_NORSRAM_BANK4 */ | |
763 { | |
764 deviceAddress = NOR_MEMORY_ADRESS4; | |
765 } | |
766 | |
767 /* Update the NOR controller state */ | |
768 hnor->State = HAL_NOR_STATE_BUSY; | |
769 | |
770 /* Send read CFI query command */ | |
771 NOR_WRITE(NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, 0x0055), 0x0098); | |
772 | |
773 /* read the NOR CFI information */ | |
774 pNOR_CFI->CFI_1 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, CFI1_ADDRESS); | |
775 pNOR_CFI->CFI_2 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, CFI2_ADDRESS); | |
776 pNOR_CFI->CFI_3 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, CFI3_ADDRESS); | |
777 pNOR_CFI->CFI_4 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceAddress, NOR_MEMORY_8B, CFI4_ADDRESS); | |
778 | |
779 /* Check the NOR controller state */ | |
780 hnor->State = HAL_NOR_STATE_READY; | |
781 | |
782 /* Process unlocked */ | |
783 __HAL_UNLOCK(hnor); | |
784 | |
785 return HAL_OK; | |
786 } | |
787 | |
788 /** | |
789 * @} | |
790 */ | |
791 | |
792 /** @defgroup NOR_Exported_Functions_Group3 Control functions | |
793 * @brief management functions | |
794 * | |
795 @verbatim | |
796 ============================================================================== | |
797 ##### NOR Control functions ##### | |
798 ============================================================================== | |
799 [..] | |
800 This subsection provides a set of functions allowing to control dynamically | |
801 the NOR interface. | |
802 | |
803 @endverbatim | |
804 * @{ | |
805 */ | |
806 | |
807 /** | |
808 * @brief Enables dynamically NOR write operation. | |
809 * @param hnor: pointer to the NOR handle | |
810 * @retval HAL status | |
811 */ | |
812 HAL_StatusTypeDef HAL_NOR_WriteOperation_Enable(NOR_HandleTypeDef *hnor) | |
813 { | |
814 /* Process Locked */ | |
815 __HAL_LOCK(hnor); | |
816 | |
817 /* Enable write operation */ | |
818 FMC_NORSRAM_WriteOperation_Enable(hnor->Instance, hnor->Init.NSBank); | |
819 | |
820 /* Update the NOR controller state */ | |
821 hnor->State = HAL_NOR_STATE_READY; | |
822 | |
823 /* Process unlocked */ | |
824 __HAL_UNLOCK(hnor); | |
825 | |
826 return HAL_OK; | |
827 } | |
828 | |
829 /** | |
830 * @brief Disables dynamically NOR write operation. | |
831 * @param hnor: pointer to the NOR handle | |
832 * @retval HAL status | |
833 */ | |
834 HAL_StatusTypeDef HAL_NOR_WriteOperation_Disable(NOR_HandleTypeDef *hnor) | |
835 { | |
836 /* Process Locked */ | |
837 __HAL_LOCK(hnor); | |
838 | |
839 /* Update the SRAM controller state */ | |
840 hnor->State = HAL_NOR_STATE_BUSY; | |
841 | |
842 /* Disable write operation */ | |
843 FMC_NORSRAM_WriteOperation_Disable(hnor->Instance, hnor->Init.NSBank); | |
844 | |
845 /* Update the NOR controller state */ | |
846 hnor->State = HAL_NOR_STATE_PROTECTED; | |
847 | |
848 /* Process unlocked */ | |
849 __HAL_UNLOCK(hnor); | |
850 | |
851 return HAL_OK; | |
852 } | |
853 | |
854 /** | |
855 * @} | |
856 */ | |
857 | |
858 /** @defgroup NOR_Exported_Functions_Group4 State functions | |
859 * @brief Peripheral State functions | |
860 * | |
861 @verbatim | |
862 ============================================================================== | |
863 ##### NOR State functions ##### | |
864 ============================================================================== | |
865 [..] | |
866 This subsection permits to get in run-time the status of the NOR controller | |
867 and the data flow. | |
868 | |
869 @endverbatim | |
870 * @{ | |
871 */ | |
872 | |
873 /** | |
874 * @brief return the NOR controller state | |
875 * @param hnor: pointer to the NOR handle | |
876 * @retval NOR controller state | |
877 */ | |
878 HAL_NOR_StateTypeDef HAL_NOR_GetState(NOR_HandleTypeDef *hnor) | |
879 { | |
880 return hnor->State; | |
881 } | |
882 | |
883 /** | |
884 * @brief Returns the NOR operation status. | |
885 * @param hnor: pointer to the NOR handle | |
886 * @param Address: Device address | |
887 * @param Timeout: NOR programming Timeout | |
888 * @retval NOR_Status: The returned value can be: HAL_NOR_STATUS_SUCCESS, HAL_NOR_STATUS_ERROR | |
889 * or HAL_NOR_STATUS_TIMEOUT | |
890 */ | |
891 HAL_NOR_StatusTypeDef HAL_NOR_GetStatus(NOR_HandleTypeDef *hnor, uint32_t Address, uint32_t Timeout) | |
892 { | |
893 HAL_NOR_StatusTypeDef status = HAL_NOR_STATUS_ONGOING; | |
894 uint16_t tmpSR1 = 0, tmpSR2 = 0; | |
895 uint32_t tickstart = 0; | |
896 | |
897 /* Poll on NOR memory Ready/Busy signal ------------------------------------*/ | |
898 HAL_NOR_MspWait(hnor, Timeout); | |
899 | |
900 /* Get the NOR memory operation status -------------------------------------*/ | |
901 | |
902 /* Get tick */ | |
903 tickstart = HAL_GetTick(); | |
904 while((status != HAL_NOR_STATUS_SUCCESS ) && (status != HAL_NOR_STATUS_TIMEOUT)) | |
905 { | |
906 /* Check for the Timeout */ | |
907 if(Timeout != HAL_MAX_DELAY) | |
908 { | |
909 if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) | |
910 { | |
911 status = HAL_NOR_STATUS_TIMEOUT; | |
912 } | |
913 } | |
914 | |
915 /* Read NOR status register (DQ6 and DQ5) */ | |
916 tmpSR1 = *(__IO uint16_t *)Address; | |
917 tmpSR2 = *(__IO uint16_t *)Address; | |
918 | |
919 /* If DQ6 did not toggle between the two reads then return HAL_NOR_STATUS_SUCCESS */ | |
920 if((tmpSR1 & 0x0040) == (tmpSR2 & 0x0040)) | |
921 { | |
922 return HAL_NOR_STATUS_SUCCESS ; | |
923 } | |
924 | |
925 if((tmpSR1 & 0x0020) == 0x0020) | |
926 { | |
927 status = HAL_NOR_STATUS_ONGOING; | |
928 } | |
929 | |
930 tmpSR1 = *(__IO uint16_t *)Address; | |
931 tmpSR2 = *(__IO uint16_t *)Address; | |
932 | |
933 /* If DQ6 did not toggle between the two reads then return HAL_NOR_STATUS_SUCCESS */ | |
934 if((tmpSR1 & 0x0040) == (tmpSR2 & 0x0040)) | |
935 { | |
936 return HAL_NOR_STATUS_SUCCESS; | |
937 } | |
938 if((tmpSR1 & 0x0020) == 0x0020) | |
939 { | |
940 return HAL_NOR_STATUS_ERROR; | |
941 } | |
942 } | |
943 | |
944 /* Return the operation status */ | |
945 return status; | |
946 } | |
947 | |
948 /** | |
949 * @} | |
950 */ | |
951 | |
952 | |
953 /** | |
954 * @} | |
955 */ | |
956 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */ | |
957 #endif /* HAL_NOR_MODULE_ENABLED */ | |
958 /** | |
959 * @} | |
960 */ | |
961 | |
962 /** | |
963 * @} | |
964 */ | |
965 | |
966 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |