--- a/src/hwos.asm	Thu Mar 05 15:06:14 2020 +0100
+++ b/src/hwos.asm	Tue Apr 28 17:34:31 2020 +0200
@@ -1,6 +1,6 @@
 ;=============================================================================
 ;
-;   File hwos.asm                             combined next generation V3.08.8
+;   File hwos.asm                           * combined next generation V3.09.4e
 ;
 ;   Definition of the hwOS dive computer platform.
 ;
@@ -12,30 +12,32 @@
 
 ;=============================================================================
 
-#DEFINE ACCESS_RAM_VARS			; the access RAM variables are declared in this file
+#DEFINE INSIDE_HWOS_ASM
 
 #include "hwos.inc"
 #include "eeprom_rs232.inc"
 
-;----------------------------- CONFIG ----------------------------------------
-	CONFIG	RETEN   = OFF		; disabled - controlled by SRETEN bit
-	CONFIG	SOSCSEL = HIGH		; High Power SOSC circuit selected
-	CONFIG	XINST   = OFF		; code won't execute in extended mode
+;----------------------------- PIC Configuration -----------------------------
+;
+	CONFIG	RETEN   = OFF		; regulator power while in sleep mode controlled by SRETEN bit
+	CONFIG	SOSCSEL = HIGH		; high power SOSC circuit selected
+	CONFIG	XINST   = OFF		; extended instruction set disabled
 	CONFIG	FOSC    = INTIO2	; internal RC oscillator, no clock-out
-	CONFIG	PLLCFG  = OFF		;
-	CONFIG	IESO    = OFF		; disabled
-	CONFIG	PWRTEN  = OFF		; disabled, because incompatible with ICD3 (Ri-400)
-	CONFIG	BOREN   = ON		; controlled with SBOREN bit
-	CONFIG	BORV    = 2			; 2.0V
-	CONFIG	BORPWR  = MEDIUM	; BORMV set to medium power level
-	CONFIG	WDTEN   = ON		; WDT controlled by SWDTEN bit setting
-	CONFIG	WDTPS   = 128		; 1:128
-	CONFIG	RTCOSC  = SOSCREF	; RTCC uses SOSC
-	CONFIG	MCLRE   = ON		; MCLR Enabled, RG5 Disabled
-	CONFIG	CCP2MX  = PORTBE	; RE7 micro-controller mode/RB3-all other modes
+	CONFIG	PLLCFG  = OFF		; oscillator used directly
+	CONFIG	IESO    = OFF		; two-speed start-up disabled
+	CONFIG	PWRTEN  = OFF		; power-up timer disabled, because incompatible with ICD3 (Ri-400)
+	CONFIG	BOREN   = ON		; brown-out reset controlled with SBOREN bit
+	CONFIG	BORV    = 2			; brown-out reset voltage 2.0V
+	CONFIG	BORPWR  = MEDIUM	; brown-out monitoring set to medium power level
+	CONFIG	WDTEN   = ON		; watchdog timer enabled, controlled by SWDTEN bit
+	CONFIG	WDTPS   = 128		; watchdog timer post-scaler 1:128
+	CONFIG	RTCOSC  = SOSCREF	; RTCC uses SOSC as ref clock
+	CONFIG	MCLRE   = ON		; MCLR enabled, RG5 disabled
+	CONFIG	CCP2MX  = PORTBE	; ECCP2 muxed with RE7 (micro-controller mode) /RB3 (other modes)
 
 
 ;---------------------------- Bank0 ACCESS RAM -------------------------------
+;
 ac_ram		equ			0x000
 ac_ram		udata_acs	ac_ram				; access RAM data
 
@@ -94,12 +96,22 @@
 hud_status_byte					res 1		; HUD status byte, see definition of flags   | Attention: keep relative position
 hud_battery_mv					res 2		; hud/ppo2 monitor battery voltage in mV     | between these two variables!
 
+;---- Battery Management
+battery_capacity_internal		res 2		; for internal battery gauging
+battery_capacity				res 2		; for battery gauge IC
+battery_offset					res 2		; for battery gauge IC
+battery_type					res 1		; =0:1.5V, =1:3.6V Saft, =2:LiIon 3.7V/0.8Ah, =3:LiIon 3.7V/3.1Ah, =4: LiIon 3.7V/2.3Ah
+battery_accumulated_charge		res 2		; raw values in battery gauge IC
+battery_temperature				res 2		; battery temperature in 0.1 Kelvin
+gauge_status_byte				res 1		; gauge IC status byte
 
-; 28 byte user data
+
+
+; 40 byte user data
 ; 32 byte tmp  data placed by C compiler
 ; 20 byte variables placed by math library
 ; ==
-; 80 byte used, 16 byte free (96 byte total available)
+; 92 byte used, 4 byte free (96 byte total available)
 
 
 	global	HW_descriptor
@@ -129,24 +141,33 @@
 	global	simulatormode_depth
 	global	hud_status_byte
 	global	hud_battery_mv
+	global	battery_capacity_internal
+	global	battery_capacity
+	global	battery_offset
+	global	battery_type
+	global	battery_accumulated_charge
+	global	battery_temperature
+	global	gauge_status_byte
+
+
+;=============================================================================
+hwos1	CODE
+;=============================================================================
 
 ;-----------------------------------------------------------------------------
-
-hwos	CODE
-
-;=============================================================================
-
+; Master Initialization of Hardware Resources
+;
 	global	init_ostc
 init_ostc:
 
 ; Oscillator
 	banksel	common				; select bank common
-	movlw	b'01110010'
-	movwf	OSCCON				; 16 MHz INTOSC
-	movlw	b'00001000'
-	movwf	OSCCON2				; secondary oscillator running
-	movlw	b'00000000'
-	movwf	OSCTUNE				; 4x PLL disable (Bit 6) - only works with 8 or 16MHz (=32 or 64MHz)
+	movlw	b'01110010'			; select 16 MHz INTOSC
+	movwf	OSCCON				; ...
+	movlw	b'00001000'			; secondary oscillator running
+	movwf	OSCCON2				; ...
+	movlw	b'00000000'			; 4x PLL disable (Bit 6) - only works with 8 or 16MHz (=32 or 64MHz)
+	movwf	OSCTUNE				; ...
 
 	movlw	coding_speed_normal	; coding for normal CPU speed
 	movwf	cpu_speed_request	; store CPU shall run with normal speed
@@ -156,72 +177,74 @@
 	bcf		RCON,IPEN			; priority interrupts off
 
 	banksel	WDTCON
-	movlw	b'10000000'
-	movwf	WDTCON				; setup watchdog
+	movlw	b'10000000'			; setup watchdog
+	movwf	WDTCON				; ...
 
 
 ; I/O Ports
-	banksel	0xF16				; addresses, F16h through F5Fh, are also used by SFRs, but are not part of the access RAM
+	banksel	0xF16				; addresses F16h ... F5Fh are not part of the access RAM
+
 	clrf	REFOCON				; no reference oscillator active on REFO pin
 	clrf	ODCON1				; disable open drain capability
 	clrf	ODCON2				; disable open drain capability
 	clrf	ODCON3				; disable open drain capability
-	clrf	CM1CON				; disable
-	clrf	CM2CON				; disable
-	clrf	CM3CON				; disable
+	clrf	CM1CON				; disable comparator 1
+	clrf	CM2CON				; disable comparator 2
+	clrf	CM3CON				; disable comparator 3
 
-	movlw	b'11000000'			; ANSEL, AN7 and AN6 -> Analog inputs, PORTA is digital
-	movwf	ANCON0
-	movlw	b'00000111'			; ANSEL, AN8, AN9, AN10 -> Analog input
-	movwf	ANCON1
-	movlw	b'00000010'			; ANSEL, AN17 -> Analog input
-	movwf	ANCON2
-	banksel	common
+	movlw	b'11000000'			; ANSEL0: AN7, AN6       -> analog inputs, PORTA is digital
+	movwf	ANCON0				; ...
+	movlw	b'00000111'			; ANSEL1: AN8, AN9, AN10 -> analog input
+	movwf	ANCON1				; ...
+	movlw	b'00000010'			; ANSEL2: AN17           -> analog input
+	movwf	ANCON2				; ...
+
+	banksel	common				; back to bank common
 
 ;	movlw	b'00000000'			; 1= input -> Data TFT_high
-	clrf	TRISA
+	clrf	TRISA				; ...
 ;	movlw	b'00000000'			; init port
-	clrf	PORTA
+	clrf	PORTA				; ...
 
 	movlw	b'00000011'			; 1= input, (RB0, RB1) -> switches, RB2 -> Power_MCP, RB3 -> s8_npower, RB4 -> LED_green/rx_nreset, RB5 -> /TFT_POWER
-	movwf	TRISB
+	movwf	TRISB				; ...
 	movlw	b'00111000'			; init port, rx_nreset=1 -> hard reset RX
-	movwf	PORTB
+	movwf	PORTB				; ...
 
 	movlw	b'10011010'			; 1= input, (RC0, RC1) -> SOSC, RC2 -> TFT_LED_PWM, (RC3,RC4) -> I²C, RC5 -> MOSI_MS5541, (RC6, RC7) -> UART1
-	movwf	TRISC
+	movwf	TRISC				; ...
 ;	movlw	b'00000000'			; init port
-	clrf	PORTC
+	clrf	PORTC				; ...
 
 	movlw	b'00100000'			; 1= input, RD0 -> TFT_NCS, RD1 -> TFT_RS, RD2 -> TFT_NWR, RD3 -> TFT_RD, RD4 -> MOSI_Flash, RD5 -> MISO_Flash, RD6 -> CLK_Flash, RD7 -> TFT_NRESET
-	movwf	TRISD
+	movwf	TRISD				; ...
 ;	movlw	b'00000000'			; init port
-	clrf	PORTD
+	clrf	PORTD				; ...
 
 	movlw	b'00100000'			; 1= input, RE0 -> not_Power_BLE, RE1 -> Power_IR, RE2 -> CS_MCP, RE3 -> LED_blue, RE4 -> power_sw1, RE5 -> leave as input
-	movwf	TRISE
+	movwf	TRISE				; ...
 	movlw	b'00010001'			; init port
-	movwf	PORTE
+	movwf	PORTE				; ...
 
 	movlw	b'01111110'			; 1= input, (RF1, RF2, RF3, RF4, RF5) -> Analog
-	movwf	TRISF
+	movwf	TRISF				; ...
 ;	movlw	b'00000000'			; init port
-	clrf	PORTF
+	clrf	PORTF				; ...
 
 	movlw	b'00001110'			; 1= input, <7:6> not implemented, RG0 -> TX3_PIEZO_CFG, , RG1 -> TX2, RG2 -> RX2, RG3 -> AN17_RSSI, RG4 -> SOSC_OUT, RG5 -> /RESET
-	movwf	TRISG
+	movwf	TRISG				; ...
 	movlw	b'00000001'			; init port
-	movwf	PORTG
+	movwf	PORTG				; ...
 
 ;	movlw	b'00000000'			; 1= input -> Data TFT_low
-	clrf	TRISH
+	clrf	TRISH				; ...
 ;	movlw	b'00000000'			; init port
-	clrf	PORTH
+	clrf	PORTH				; ...
 
 	movlw	b'10011011'			; 1= input, RJ4 -> vusb_in, RJ5 -> power_sw2, RJ6 -> CLK_MS5541, RJ7 -> MISO_MS5541
-	movwf	TRISJ
+	movwf	TRISJ				; ...
 	movlw	b'00100000'			; init port
-	movwf	PORTJ
+	movwf	PORTJ				; ...
 
 
 ; disable Charger by default
@@ -229,51 +252,74 @@
 	bcf		charge_enable		; activate charging-inhibit signal
 
 
-; Timer 0
-	movlw	b'00000001'			; timer0 with 1:4 prescaler
-	movwf	T0CON
+; Timer 7 for 62.5 ms Interrupt (Sensor States)
+	banksel	0xF16				; addresses F16h...F5Fh are not part of the access RAM
+	clrf	T7GCON				; clear timer 7 gate control register
+	movlw	b'10001101'			; bit 7-6: 10 = clock source SOSC/SCLKI (with bit   3 = 1)
+								; bit 5-4: 00 = 1:1 prescaler
+								; bit   3:  1 = clock source SOSC/SCLKI (with bit 7-6 = 10)
+								; bit   2:  1 = DO NOT synchronize external clock input (else OSTC won't wake up from sleep!)
+								; bit   1:  0 = 2x 8 bit operation
+								; bit   0:  1 = timer enabled
+								; 32768 Hz clock source, 1:1 prescaler -> timer counts at 30.51757813 µs/bit
+	movwf	T7CON				; ...
+	movlw	.248				; load timer 7, high byte (8x256 ticks -> 62.5 ms)
+	movwf	TMR7H				; ...
+	clrf	TMR7L				; load timer 7, low  byte
 
 
-; Timer 1 - Button hold-down timer
-	movlw	b'10001100'			; 32768 Hz clock source, 1:1 prescaler -> ; 30.51757813 µs/bit in TMR1L:TMR1H
-	movwf	T1CON
+; Timer 0 - not used
+	movlw	b'00000001'			; timer0 stopped (1:4 prescaler)
+	movwf	T0CON				; ...
+
+
+; Timer 1 - Button hold-down Timer
+;	movlw	b'10001100'			; old setting
+	movlw	b'10001010'			; bit 7-6: 10 = clock source SOSC/SCLKI (with bit   3 = 1)
+								; bit 5-4: 00 = 1:1 prescaler
+								; bit   3:  1 = clock source SOSC/SCLKI (with bit 7-6 = 10)
+								; bit   2:  0 = synchronize external clock input
+								; bit   1:  1 = 16 bit operation
+								; bit   0:  0 = timer stopped
+								; 32768 Hz clock source, 1:1 prescaler -> timer counts at 30.51757813 µs/bit
+	movwf	T1CON				; ...
 
 
 ; RTCC
 	banksel	0xF16				; addresses, F16h through F5Fh, are also used by SFRs, but are not part of the access RAM
-	movlw	0x55
-	movwf	EECON2
-	movlw	0xAA
-	movwf	EECON2
-	bsf 	RTCCFG,RTCWREN		; unlock sequence for RTCWREN
-	bsf		RTCCFG,RTCPTR1
-	bsf		RTCCFG,RTCPTR0
+	movlw	0x55				; unlock sequence for RTCWREN
+	movwf	EECON2				; ...
+	movlw	0xAA				; ...
+	movwf	EECON2				; ...
+	bsf 	RTCCFG,RTCWREN		; unlock access to RTC
+	bsf		RTCCFG,RTCPTR1		; set pointer register to b'11'
+	bsf		RTCCFG,RTCPTR0		; ..
 	bsf		RTCCFG,RTCEN		; module enable
 	bsf		RTCCFG,RTCOE		; output enable
 	movlw	b'00000100'			; 32768 Hz SOCS on RTCC pin (PORTG,4) Bit7-5: pull-ups for Port D, E and J
-	movwf	PADCFG1
-	movlw	b'11000000'
-	movwf	ALRMCFG				; 1/2 second alarm
-	movlw	d'1'
-	movwf	ALRMRPT				; alarm repeat counter
-	movlw	0x55
-	movwf	EECON2
-	movlw	0xAA
-	movwf	EECON2
-	bcf		RTCCFG,RTCWREN		; lock sequence for RTCWREN
-	banksel	common
+	movwf	PADCFG1				; ...
+	movlw	b'11000000'			; 1/2 second alarm
+	movwf	ALRMCFG				; ...
+	movlw	d'1'				; select alarm repeat counter to 1
+	movwf	ALRMRPT				; ...
+	movlw	0x55				; unlock sequence for RTCWREN
+	movwf	EECON2				; ...
+	movlw	0xAA				; ...
+	movwf	EECON2				; ...
+	bcf		RTCCFG,RTCWREN		; lock access to RTC
+	banksel	common				; back to bank common
 
 
 ; A/D Converter
 	movlw	b'00011000'			; power off ADC, select AN6
-	movwf	ADCON0
+	movwf	ADCON0				; ...
 	movlw	b'00100000'			; 2.048V Vref+
-	movwf	ADCON1
+	movwf	ADCON1				; ...
 	movlw	b'10111010'			; right aligned, 20 x T_AD acquisition time, FOSC/32 -> max. 40 MHz device clock speed
-	movwf	ADCON2
+	movwf	ADCON2				; ...
 
 
-; serial Port 1 (TRISC6/7)
+; Serial Port 1 (TRISC6/7)
 	movlw	b'00001000'			; switch baud generator to 16 bit mode (BRG16=1)
 	movwf	BAUDCON1			; ...
 								; SPBRGH:SPBRG =  .34 : 114285 BAUD @ 16MHz (+0.79% error at 115200 baud)
@@ -287,131 +333,148 @@
 	bcf		PORTC,6				; tie TX output hard to GND
 
 
-; serial Port 2 (TRISG2) for IR/S8 digital interface
+; Serial Port 2 (TRISG2) for IR/S8 digital Interface
 ;
 ; - will be initialized by enable_ir_s8 (eeprom_rs232.asm) in case IR/S8 shall be available
 
 
 ; Timer 3 for IR-RX Timeout
  IFDEF _external_sensor
-	clrf	T3GCON				; reset Timer3 gate control register
-	movlw	b'10001101'			; not synced, 1:1 prescaler -> 2 seconds till overrun @ 32768 Hz,
-								;                          incrementing by 1 bit each 30.51757813 µs
-	movwf	T3CON
+	clrf	T3GCON				; clear Timer3 gate control register
+;	movlw	b'10001101'			; old value
+	movlw	b'10001011'			; bit 7-6: 10 = clock source SOSC/SCLKI (with bit   3 = 1)
+								; bit 5-4: 00 = 1:1 prescaler
+								; bit   3:  1 = clock source SOSC/SCLKI (with bit 7-6 = 10)
+								; bit   2:  0 = synchronize external clock input
+								; bit   1:  1 = 16 bit operation
+								; bit   0:  1 = timer enabled
+								; 32768 Hz clock source, 1:1 prescaler -> timer counts at 30.51757813 µs/bit
+	movwf	T3CON				; ...
  ENDIF
 
 
 ; SPI Module(s)
 ; SPI2: External Flash
-	movlw	b'00110000'
-	movwf	SSP2CON1
-;	movlw	b'00000000'
-	clrf	SSP2STAT
-								; -> 0.25 MHz Bit clock @  1 MHz mode (Eco)
-								; ->    4 MHz Bit clock @ 16 MHz mode (Normal)
-								; ->   16 MHz Bit clock @ 64 MHz mode (Fastest)
+	movlw	b'00110000'			; set up SPI module
+	movwf	SSP2CON1			; ...
+	clrf	SSP2STAT			; ...
+								; resulting bit clocks:  0.25 MHz @  1 MHz CPU clock (Eco)
+								;                        4.00 MHz @ 16 MHz CPU clock (Normal)
+								;                       16.00 MHz @ 64 MHz CPU clock (Fastest)
 
 
 ; MSSP1 Module: I2C Master
-	movlw	b'00101000'			; I2C master mode
-	movwf	SSP1CON1
-;	movlw	b'00000000'
-	clrf	SSP1CON2
-	movlw	0x9C
-	movwf	SSP1ADD				; 100kHz @ 64MHz Fosc
+	movlw	b'00101000'			; set up I2C to master mode
+	movwf	SSP1CON1			; ...
+	clrf	SSP1CON2			; ...
+	movlw	0x9C				; select speed 100kHz @ 64MHz Fosc
+	movwf	SSP1ADD				; ...
 
 
 ; PWM Module(s)
 ; PWM 1 for LED dimming
-	movlw	b'00001100'
-	movwf	CCP1CON
-	movlw	b'00000001'
-	movwf	PSTR1CON			; pulse steering disabled
-	movlw	d'254'
-	movwf	PR2					; period
+	movlw	b'00001100'			; set up PWM module
+	movwf	CCP1CON				; ...
+	movlw	b'00000001'			; pulse steering disabled
+	movwf	PSTR1CON			; ...
+	movlw	d'254'				; select period
+	movwf	PR2					; ...
 	; 255 is max brightness (300 mW)
-	clrf	CCPR1L				; duty cycle
-	clrf	CCPR1H				; duty cycle
-	movlw	T2CON_NORMAL
-	movwf	T2CON
-
-
-; Timer 5 for ISR-independent wait routines
-	clrf	T5GCON				; reset Timer5 gate control register
-	movlw	b'10001111'			; not synced, 16 bit mode, 1:1 prescaler -> 2 seconds till overrun @ 32768 Hz,
-	movwf	T5CON				;                                       incrementing by 1 bit each 30.51757813 µs
+	clrf	CCPR1L				; duty cycle, low  byte
+	clrf	CCPR1H				; duty cycle, high byte
+	movlw	T2CON_NORMAL		; set timer for normal dimming
+	movwf	T2CON				; ...
 
 
-	banksel	0xF16				; addresses F16h through F5Fh are also used by SFRs, but are not part of the access RAM
-
-; Timer 7 for 62.5 ms Interrupt (sensor states)
-	clrf	T7GCON				; reset Timer7 gate control register
-	movlw	b'10001101'			; 1:1 prescaler -> 2 seconds @ 32768 Hz, not synced
-	movwf	T7CON
-	clrf	TMR7L
-	movlw	.248
-	movwf	TMR7H				; -> rollover after 2048 cycles -> 62.5 ms
+; Timer 5 for ISR-independent Wait/Timeout
+	clrf	T5GCON				; clear Timer5 gate control register
+;	movlw	b'10001111'			; old value
+	movlw	b'10001011'			; bit 7-6: 10 = clock source SOSC/SCLKI (with bit   3 = 1)
+								; bit 5-4: 00 = 1:1 prescaler
+								; bit   3:  1 = clock source SOSC/SCLKI (with bit 7-6 = 10)
+								; bit   2:  0 = synchronize external clock input
+								; bit   1:  1 = 16 bit operation
+								; bit   0:  1 = timer enabled
+								; 32768 Hz clock source, 1:1 prescaler -> timer counts at 30.51757813 µs/bit
+	movwf	T5CON				; ...
 
 
-; turn off unused timers
-	movlw	b'11000000'
-	movwf	PMD0
+; turn off unused Timers
+	;banksel 0xF16				; addresses F16h...F5Fh are not part of the access RAM
+	movlw	b'11000000'			; disable ECCP3 and ECCP2
+	movwf	PMD0				; ...
  IFDEF _external_sensor
-	movlw	b'11010001'
+	movlw	b'11010001'			; disable PSP, CTMU, Timer 4 and EMB
  ELSE
-	movlw	b'11011001'			; includes turning off timer 3
+	movlw	b'11011001'			; disable PSP, CTMU, Timer 4, Timer 3 and EMB
  ENDIF
-	movwf	PMD1
-	movlw	b'11010111'
-	movwf	PMD2
-	movlw	b'11111111'
-	movwf	PMD3
+	movwf	PMD1				; ...
+	movlw	b'11010111'			; disable timer 10, timer 8, timer 6 and comparators 1-3
+	movwf	PMD2				; ...
+	movlw	b'11111111'			; disable CCP 4-10 and timer 12
+	movwf	PMD3				; ...
 
 
 ; turn off unused CTMU
-	clrf	CTMUCONH
-	clrf	CTMUCONL
-	clrf	CTMUICON
+	;banksel 0xF16				; addresses F16h...F5Fh are not part of the access RAM
+	clrf	CTMUCONH			; disable CTMU
+	clrf	CTMUCONL			; ...
+	clrf	CTMUICON			; ...
+
 
 	banksel	common
 
 
 ; Interrupts
-	movlw	b'11010000'
-	movwf	INTCON
-	movlw	b'00001000'			; Bit7=1: pull-up for PORTB disabled
-	movwf	INTCON2
-	movlw	b'00000000'
-	movwf	INTCON3
-	movlw	b'00000001'			; Bit0: TMR1
-	movwf	PIE1
-	movlw	b'00000010'			; Bit1: TMR3
-	movwf	PIE2
-	movlw	b'00000000'			; Bit1: TMR5
-	movwf	PIE5
-	movlw	b'00000001'			; Bit0: RTCC, Bit5: UART2 (Default OFF)
-	movwf	PIE3
-	movlw	b'00001000'			; Bit3: TMR7
-	movwf	PIE5
+	bcf		PIR5,TMR7IF			; if applicable clear timer 7 IRQ flag
 
-	bcf		active_reset_ostc_rx	; release RESET from RX circuitry
+	movlw	b'11010000'			; enable global IRQ, peripheral IRQ and external IRQ 0
+	movwf	INTCON				; ...
+	movlw	b'00001000'			; external IRQ 0 on falling edge, pull-up of PORTB by TRIS register
+	movwf	INTCON2				; ...
+	movlw	b'00000000'			; disable external IRQs 1,2,3
+	movwf	INTCON3				; ...
+	movlw	b'00000001'			; enable timer 1 IRQ
+	movwf	PIE1				; ...
+	movlw	b'00000010'			; enable timer 3 IRQ
+	movwf	PIE2				; ...
+	movlw	b'00000000'			; enable timer 5 IRQ
+	movwf	PIE5				; ...
+	movlw	b'00000001'			; enable RTCC IRQ
+	movwf	PIE3				; ...
+	movlw	b'00001000'			; enable timer 7 IRQ
+	movwf	PIE5				; ...
+
+; Release RESET from RX Circuitry
+	bcf		active_reset_ostc_rx
+
+; Power-up the Switches
 	;bra	power_up_switches
 
 
+;-----------------------------------------------------------------------------
+; Power-up the Switches
+;
 	global	power_up_switches
 power_up_switches:
 	bsf		power_sw1			; switch on power supply for switch 1
 	btfss	power_sw1			; power established?
 	bra		$-4					; NO - wait
+
 	bsf		power_sw2			; switch on power supply for switch 2
 	btfss	power_sw2			; power established?
 	bra		$-4					; NO - wait
 
-	return
+	return						; done
+
 
 ;=============================================================================
-; CPU speed change request functions
+hwos2	CODE
+;=============================================================================
 
+;-----------------------------------------------------------------------------
+; CPU Speed Change Requests
+;
 	global	request_speed_eco
 request_speed_eco:
 	movlw	coding_speed_eco		; load coding for eco speed
@@ -430,14 +493,19 @@
 	movwf	cpu_speed_request		; request ISR to change the CPU speed
 	return							; done
 
+
 ;=============================================================================
-; Backup the first 128 bytes from program memory to EEPROM
+hwos3	CODE
+;=============================================================================
+
+;-----------------------------------------------------------------------------
+; Backup the first 128 bytes from program FLASH to EEPROM
 ;
 	global	backup_flash_page
 backup_flash_page:
 	banksel	common
 
-	; set start address in internal program memory
+	; set start address in internal program FLASH
 	movlw	0x00					; set 0x000000
 	movwf	TBLPTRL					; ...
 	movwf	TBLPTRH					; ...
@@ -450,22 +518,27 @@
 	movlw	.128					; copy 1 block = 128 byte
 	movwf	eeprom_loop				; initialize loop counter
 backup_flash_loop:
-	tblrd+*							; read one byte from program memory (with pre-increment)
-	movff	TABLAT,EEDATA			; transfer byte from program memory read to EEPROM write
+	tblrd+*							; read one byte from program FLASH (with pre-increment)
+	movff	TABLAT,EEDATA			; transfer byte from program FLASH read to EEPROM write
 	call	write_eeprom			; execute   EEPROM write
 	incf	EEADR,F					; increment EEPROM address
 	decfsz	eeprom_loop,F			; all 128 byte done?
 	bra		backup_flash_loop		; NO  - loop
 	return							; YES - done
 
+
 ;=============================================================================
-; Restore the first 128 bytes from EEPROM to program memory
+hwos4	CODE
+;=============================================================================
+
+;-----------------------------------------------------------------------------
+; Restore the first 128 bytes from EEPROM to program FLASH
 ;
 	global	restore_flash
 restore_flash:
 	banksel	common
 
-	;set start address in internal program memory
+	;set start address in internal program FLASH
 	movlw	0x00					; set 0x000000
 	movwf	TBLPTRL					; ...
 	movwf	TBLPTRH					; ...
@@ -483,8 +556,8 @@
 restore_flash_loop:
 	call	read_eeprom				; execute   EEPROM read
 	incf	EEADR,F					; increment EEPROM address
-	movff	EEDATA,TABLAT			; transfer byte from EEPROM read to program memory write
-	tblwt+*							; execute program memory write (with pre-increment)
+	movff	EEDATA,TABLAT			; transfer byte from EEPROM read to program FLASH write
+	tblwt+*							; execute program FLASH write (with pre-increment)
 	decfsz	eeprom_loop,F			; all 128 bytes done?
 	bra		restore_flash_loop		; NO  - loop
 	movlw	b'10000100'				; YES - setup   block write
@@ -502,8 +575,13 @@
 	nop								; ...
 	return							; done
 
+
 ;=============================================================================
-; Memory clear and move functions, to be used through macros
+hwos5	CODE
+;=============================================================================
+
+;-----------------------------------------------------------------------------
+; Memory clear and move Functions, to be used via Macros
 ;
 	global	memory_clear
 memory_clear:
@@ -519,4 +597,27 @@
 	bra		memory_move				; NO  - loop
 	return							; YES - done
 
-	END
\ No newline at end of file
+
+;=============================================================================
+hwos6	CODE
+;=============================================================================
+
+;-----------------------------------------------------------------------------
+; Read CPU Silicon Version
+;
+	global	get_cpu_version
+get_cpu_version:
+	movlw	0xFE					; select address 0x3FFFFE
+	movwf	TBLPTRL					; ...
+	movlw	0xFF					; ...
+	movwf	TBLPTRH					; ...
+	movlw	0x3F					; ...
+	movwf	TBLPTRU					; ...
+	TBLRD*+							; read DEVID1 byte
+	movlw	b'00011111'				; load mask for silicon version
+	andwf	TABLAT,W				; apply mask and store result in WREG 
+	return							; done
+
+;-----------------------------------------------------------------------------
+
+	END