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3.10 stable release
author heinrichsweikamp
date Tue, 28 Apr 2020 17:34:31 +0200
parents 185ba2f91f59
children 8c1f1f334275
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633:690c48db7b5b 634:4050675965ea
1 ;============================================================================= 1 ;=============================================================================
2 ; 2 ;
3 ; File hwos.asm combined next generation V3.08.8 3 ; File hwos.asm * combined next generation V3.09.4e
4 ; 4 ;
5 ; Definition of the hwOS dive computer platform. 5 ; Definition of the hwOS dive computer platform.
6 ; 6 ;
7 ; Copyright (c) 2011, JD Gascuel, HeinrichsWeikamp, all right reserved. 7 ; Copyright (c) 2011, JD Gascuel, HeinrichsWeikamp, all right reserved.
8 ;============================================================================= 8 ;=============================================================================
10 ; 2011-05-24 : [jDG] Cleanups from initial Matthias code 10 ; 2011-05-24 : [jDG] Cleanups from initial Matthias code
11 ; 2011-06-24 : [MH] Added clock speeds 11 ; 2011-06-24 : [MH] Added clock speeds
12 12
13 ;============================================================================= 13 ;=============================================================================
14 14
15 #DEFINE ACCESS_RAM_VARS ; the access RAM variables are declared in this file 15 #DEFINE INSIDE_HWOS_ASM
16 16
17 #include "hwos.inc" 17 #include "hwos.inc"
18 #include "eeprom_rs232.inc" 18 #include "eeprom_rs232.inc"
19 19
20 ;----------------------------- CONFIG ---------------------------------------- 20 ;----------------------------- PIC Configuration -----------------------------
21 CONFIG RETEN = OFF ; disabled - controlled by SRETEN bit 21 ;
22 CONFIG SOSCSEL = HIGH ; High Power SOSC circuit selected 22 CONFIG RETEN = OFF ; regulator power while in sleep mode controlled by SRETEN bit
23 CONFIG XINST = OFF ; code won't execute in extended mode 23 CONFIG SOSCSEL = HIGH ; high power SOSC circuit selected
24 CONFIG XINST = OFF ; extended instruction set disabled
24 CONFIG FOSC = INTIO2 ; internal RC oscillator, no clock-out 25 CONFIG FOSC = INTIO2 ; internal RC oscillator, no clock-out
25 CONFIG PLLCFG = OFF ; 26 CONFIG PLLCFG = OFF ; oscillator used directly
26 CONFIG IESO = OFF ; disabled 27 CONFIG IESO = OFF ; two-speed start-up disabled
27 CONFIG PWRTEN = OFF ; disabled, because incompatible with ICD3 (Ri-400) 28 CONFIG PWRTEN = OFF ; power-up timer disabled, because incompatible with ICD3 (Ri-400)
28 CONFIG BOREN = ON ; controlled with SBOREN bit 29 CONFIG BOREN = ON ; brown-out reset controlled with SBOREN bit
29 CONFIG BORV = 2 ; 2.0V 30 CONFIG BORV = 2 ; brown-out reset voltage 2.0V
30 CONFIG BORPWR = MEDIUM ; BORMV set to medium power level 31 CONFIG BORPWR = MEDIUM ; brown-out monitoring set to medium power level
31 CONFIG WDTEN = ON ; WDT controlled by SWDTEN bit setting 32 CONFIG WDTEN = ON ; watchdog timer enabled, controlled by SWDTEN bit
32 CONFIG WDTPS = 128 ; 1:128 33 CONFIG WDTPS = 128 ; watchdog timer post-scaler 1:128
33 CONFIG RTCOSC = SOSCREF ; RTCC uses SOSC 34 CONFIG RTCOSC = SOSCREF ; RTCC uses SOSC as ref clock
34 CONFIG MCLRE = ON ; MCLR Enabled, RG5 Disabled 35 CONFIG MCLRE = ON ; MCLR enabled, RG5 disabled
35 CONFIG CCP2MX = PORTBE ; RE7 micro-controller mode/RB3-all other modes 36 CONFIG CCP2MX = PORTBE ; ECCP2 muxed with RE7 (micro-controller mode) /RB3 (other modes)
36 37
37 38
38 ;---------------------------- Bank0 ACCESS RAM ------------------------------- 39 ;---------------------------- Bank0 ACCESS RAM -------------------------------
40 ;
39 ac_ram equ 0x000 41 ac_ram equ 0x000
40 ac_ram udata_acs ac_ram ; access RAM data 42 ac_ram udata_acs ac_ram ; access RAM data
41 43
42 44
43 ;---- Flags - Hardware Descriptors 45 ;---- Flags - Hardware Descriptors
92 94
93 ;---- HUD / Sensor Data 95 ;---- HUD / Sensor Data
94 hud_status_byte res 1 ; HUD status byte, see definition of flags | Attention: keep relative position 96 hud_status_byte res 1 ; HUD status byte, see definition of flags | Attention: keep relative position
95 hud_battery_mv res 2 ; hud/ppo2 monitor battery voltage in mV | between these two variables! 97 hud_battery_mv res 2 ; hud/ppo2 monitor battery voltage in mV | between these two variables!
96 98
97 99 ;---- Battery Management
98 ; 28 byte user data 100 battery_capacity_internal res 2 ; for internal battery gauging
101 battery_capacity res 2 ; for battery gauge IC
102 battery_offset res 2 ; for battery gauge IC
103 battery_type res 1 ; =0:1.5V, =1:3.6V Saft, =2:LiIon 3.7V/0.8Ah, =3:LiIon 3.7V/3.1Ah, =4: LiIon 3.7V/2.3Ah
104 battery_accumulated_charge res 2 ; raw values in battery gauge IC
105 battery_temperature res 2 ; battery temperature in 0.1 Kelvin
106 gauge_status_byte res 1 ; gauge IC status byte
107
108
109
110 ; 40 byte user data
99 ; 32 byte tmp data placed by C compiler 111 ; 32 byte tmp data placed by C compiler
100 ; 20 byte variables placed by math library 112 ; 20 byte variables placed by math library
101 ; == 113 ; ==
102 ; 80 byte used, 16 byte free (96 byte total available) 114 ; 92 byte used, 4 byte free (96 byte total available)
103 115
104 116
105 global HW_descriptor 117 global HW_descriptor
106 global HW_variants 118 global HW_variants
107 global HW_flags_state1 119 global HW_flags_state1
127 global sampling_rate 139 global sampling_rate
128 global sampling_timer 140 global sampling_timer
129 global simulatormode_depth 141 global simulatormode_depth
130 global hud_status_byte 142 global hud_status_byte
131 global hud_battery_mv 143 global hud_battery_mv
132 144 global battery_capacity_internal
133 ;----------------------------------------------------------------------------- 145 global battery_capacity
134 146 global battery_offset
135 hwos CODE 147 global battery_type
136 148 global battery_accumulated_charge
137 ;============================================================================= 149 global battery_temperature
138 150 global gauge_status_byte
151
152
153 ;=============================================================================
154 hwos1 CODE
155 ;=============================================================================
156
157 ;-----------------------------------------------------------------------------
158 ; Master Initialization of Hardware Resources
159 ;
139 global init_ostc 160 global init_ostc
140 init_ostc: 161 init_ostc:
141 162
142 ; Oscillator 163 ; Oscillator
143 banksel common ; select bank common 164 banksel common ; select bank common
144 movlw b'01110010' 165 movlw b'01110010' ; select 16 MHz INTOSC
145 movwf OSCCON ; 16 MHz INTOSC 166 movwf OSCCON ; ...
146 movlw b'00001000' 167 movlw b'00001000' ; secondary oscillator running
147 movwf OSCCON2 ; secondary oscillator running 168 movwf OSCCON2 ; ...
148 movlw b'00000000' 169 movlw b'00000000' ; 4x PLL disable (Bit 6) - only works with 8 or 16MHz (=32 or 64MHz)
149 movwf OSCTUNE ; 4x PLL disable (Bit 6) - only works with 8 or 16MHz (=32 or 64MHz) 170 movwf OSCTUNE ; ...
150 171
151 movlw coding_speed_normal ; coding for normal CPU speed 172 movlw coding_speed_normal ; coding for normal CPU speed
152 movwf cpu_speed_request ; store CPU shall run with normal speed 173 movwf cpu_speed_request ; store CPU shall run with normal speed
153 movwf cpu_speed_state ; store CPU does run with normal speed 174 movwf cpu_speed_state ; store CPU does run with normal speed
154 175
155 ;bcf RCON,SBOREN ; brown-out off (not needed here, is handled in bootloader) 176 ;bcf RCON,SBOREN ; brown-out off (not needed here, is handled in bootloader)
156 bcf RCON,IPEN ; priority interrupts off 177 bcf RCON,IPEN ; priority interrupts off
157 178
158 banksel WDTCON 179 banksel WDTCON
159 movlw b'10000000' 180 movlw b'10000000' ; setup watchdog
160 movwf WDTCON ; setup watchdog 181 movwf WDTCON ; ...
161 182
162 183
163 ; I/O Ports 184 ; I/O Ports
164 banksel 0xF16 ; addresses, F16h through F5Fh, are also used by SFRs, but are not part of the access RAM 185 banksel 0xF16 ; addresses F16h ... F5Fh are not part of the access RAM
186
165 clrf REFOCON ; no reference oscillator active on REFO pin 187 clrf REFOCON ; no reference oscillator active on REFO pin
166 clrf ODCON1 ; disable open drain capability 188 clrf ODCON1 ; disable open drain capability
167 clrf ODCON2 ; disable open drain capability 189 clrf ODCON2 ; disable open drain capability
168 clrf ODCON3 ; disable open drain capability 190 clrf ODCON3 ; disable open drain capability
169 clrf CM1CON ; disable 191 clrf CM1CON ; disable comparator 1
170 clrf CM2CON ; disable 192 clrf CM2CON ; disable comparator 2
171 clrf CM3CON ; disable 193 clrf CM3CON ; disable comparator 3
172 194
173 movlw b'11000000' ; ANSEL, AN7 and AN6 -> Analog inputs, PORTA is digital 195 movlw b'11000000' ; ANSEL0: AN7, AN6 -> analog inputs, PORTA is digital
174 movwf ANCON0 196 movwf ANCON0 ; ...
175 movlw b'00000111' ; ANSEL, AN8, AN9, AN10 -> Analog input 197 movlw b'00000111' ; ANSEL1: AN8, AN9, AN10 -> analog input
176 movwf ANCON1 198 movwf ANCON1 ; ...
177 movlw b'00000010' ; ANSEL, AN17 -> Analog input 199 movlw b'00000010' ; ANSEL2: AN17 -> analog input
178 movwf ANCON2 200 movwf ANCON2 ; ...
179 banksel common 201
202 banksel common ; back to bank common
180 203
181 ; movlw b'00000000' ; 1= input -> Data TFT_high 204 ; movlw b'00000000' ; 1= input -> Data TFT_high
182 clrf TRISA 205 clrf TRISA ; ...
183 ; movlw b'00000000' ; init port 206 ; movlw b'00000000' ; init port
184 clrf PORTA 207 clrf PORTA ; ...
185 208
186 movlw b'00000011' ; 1= input, (RB0, RB1) -> switches, RB2 -> Power_MCP, RB3 -> s8_npower, RB4 -> LED_green/rx_nreset, RB5 -> /TFT_POWER 209 movlw b'00000011' ; 1= input, (RB0, RB1) -> switches, RB2 -> Power_MCP, RB3 -> s8_npower, RB4 -> LED_green/rx_nreset, RB5 -> /TFT_POWER
187 movwf TRISB 210 movwf TRISB ; ...
188 movlw b'00111000' ; init port, rx_nreset=1 -> hard reset RX 211 movlw b'00111000' ; init port, rx_nreset=1 -> hard reset RX
189 movwf PORTB 212 movwf PORTB ; ...
190 213
191 movlw b'10011010' ; 1= input, (RC0, RC1) -> SOSC, RC2 -> TFT_LED_PWM, (RC3,RC4) -> I²C, RC5 -> MOSI_MS5541, (RC6, RC7) -> UART1 214 movlw b'10011010' ; 1= input, (RC0, RC1) -> SOSC, RC2 -> TFT_LED_PWM, (RC3,RC4) -> I²C, RC5 -> MOSI_MS5541, (RC6, RC7) -> UART1
192 movwf TRISC 215 movwf TRISC ; ...
193 ; movlw b'00000000' ; init port 216 ; movlw b'00000000' ; init port
194 clrf PORTC 217 clrf PORTC ; ...
195 218
196 movlw b'00100000' ; 1= input, RD0 -> TFT_NCS, RD1 -> TFT_RS, RD2 -> TFT_NWR, RD3 -> TFT_RD, RD4 -> MOSI_Flash, RD5 -> MISO_Flash, RD6 -> CLK_Flash, RD7 -> TFT_NRESET 219 movlw b'00100000' ; 1= input, RD0 -> TFT_NCS, RD1 -> TFT_RS, RD2 -> TFT_NWR, RD3 -> TFT_RD, RD4 -> MOSI_Flash, RD5 -> MISO_Flash, RD6 -> CLK_Flash, RD7 -> TFT_NRESET
197 movwf TRISD 220 movwf TRISD ; ...
198 ; movlw b'00000000' ; init port 221 ; movlw b'00000000' ; init port
199 clrf PORTD 222 clrf PORTD ; ...
200 223
201 movlw b'00100000' ; 1= input, RE0 -> not_Power_BLE, RE1 -> Power_IR, RE2 -> CS_MCP, RE3 -> LED_blue, RE4 -> power_sw1, RE5 -> leave as input 224 movlw b'00100000' ; 1= input, RE0 -> not_Power_BLE, RE1 -> Power_IR, RE2 -> CS_MCP, RE3 -> LED_blue, RE4 -> power_sw1, RE5 -> leave as input
202 movwf TRISE 225 movwf TRISE ; ...
203 movlw b'00010001' ; init port 226 movlw b'00010001' ; init port
204 movwf PORTE 227 movwf PORTE ; ...
205 228
206 movlw b'01111110' ; 1= input, (RF1, RF2, RF3, RF4, RF5) -> Analog 229 movlw b'01111110' ; 1= input, (RF1, RF2, RF3, RF4, RF5) -> Analog
207 movwf TRISF 230 movwf TRISF ; ...
208 ; movlw b'00000000' ; init port 231 ; movlw b'00000000' ; init port
209 clrf PORTF 232 clrf PORTF ; ...
210 233
211 movlw b'00001110' ; 1= input, <7:6> not implemented, RG0 -> TX3_PIEZO_CFG, , RG1 -> TX2, RG2 -> RX2, RG3 -> AN17_RSSI, RG4 -> SOSC_OUT, RG5 -> /RESET 234 movlw b'00001110' ; 1= input, <7:6> not implemented, RG0 -> TX3_PIEZO_CFG, , RG1 -> TX2, RG2 -> RX2, RG3 -> AN17_RSSI, RG4 -> SOSC_OUT, RG5 -> /RESET
212 movwf TRISG 235 movwf TRISG ; ...
213 movlw b'00000001' ; init port 236 movlw b'00000001' ; init port
214 movwf PORTG 237 movwf PORTG ; ...
215 238
216 ; movlw b'00000000' ; 1= input -> Data TFT_low 239 ; movlw b'00000000' ; 1= input -> Data TFT_low
217 clrf TRISH 240 clrf TRISH ; ...
218 ; movlw b'00000000' ; init port 241 ; movlw b'00000000' ; init port
219 clrf PORTH 242 clrf PORTH ; ...
220 243
221 movlw b'10011011' ; 1= input, RJ4 -> vusb_in, RJ5 -> power_sw2, RJ6 -> CLK_MS5541, RJ7 -> MISO_MS5541 244 movlw b'10011011' ; 1= input, RJ4 -> vusb_in, RJ5 -> power_sw2, RJ6 -> CLK_MS5541, RJ7 -> MISO_MS5541
222 movwf TRISJ 245 movwf TRISJ ; ...
223 movlw b'00100000' ; init port 246 movlw b'00100000' ; init port
224 movwf PORTJ 247 movwf PORTJ ; ...
225 248
226 249
227 ; disable Charger by default 250 ; disable Charger by default
228 bsf charge_disable ; set charging-inhibit signal 251 bsf charge_disable ; set charging-inhibit signal
229 bcf charge_enable ; activate charging-inhibit signal 252 bcf charge_enable ; activate charging-inhibit signal
230 253
231 254
232 ; Timer 0 255 ; Timer 7 for 62.5 ms Interrupt (Sensor States)
233 movlw b'00000001' ; timer0 with 1:4 prescaler 256 banksel 0xF16 ; addresses F16h...F5Fh are not part of the access RAM
234 movwf T0CON 257 clrf T7GCON ; clear timer 7 gate control register
235 258 movlw b'10001101' ; bit 7-6: 10 = clock source SOSC/SCLKI (with bit 3 = 1)
236 259 ; bit 5-4: 00 = 1:1 prescaler
237 ; Timer 1 - Button hold-down timer 260 ; bit 3: 1 = clock source SOSC/SCLKI (with bit 7-6 = 10)
238 movlw b'10001100' ; 32768 Hz clock source, 1:1 prescaler -> ; 30.51757813 µs/bit in TMR1L:TMR1H 261 ; bit 2: 1 = DO NOT synchronize external clock input (else OSTC won't wake up from sleep!)
239 movwf T1CON 262 ; bit 1: 0 = 2x 8 bit operation
263 ; bit 0: 1 = timer enabled
264 ; 32768 Hz clock source, 1:1 prescaler -> timer counts at 30.51757813 µs/bit
265 movwf T7CON ; ...
266 movlw .248 ; load timer 7, high byte (8x256 ticks -> 62.5 ms)
267 movwf TMR7H ; ...
268 clrf TMR7L ; load timer 7, low byte
269
270
271 ; Timer 0 - not used
272 movlw b'00000001' ; timer0 stopped (1:4 prescaler)
273 movwf T0CON ; ...
274
275
276 ; Timer 1 - Button hold-down Timer
277 ; movlw b'10001100' ; old setting
278 movlw b'10001010' ; bit 7-6: 10 = clock source SOSC/SCLKI (with bit 3 = 1)
279 ; bit 5-4: 00 = 1:1 prescaler
280 ; bit 3: 1 = clock source SOSC/SCLKI (with bit 7-6 = 10)
281 ; bit 2: 0 = synchronize external clock input
282 ; bit 1: 1 = 16 bit operation
283 ; bit 0: 0 = timer stopped
284 ; 32768 Hz clock source, 1:1 prescaler -> timer counts at 30.51757813 µs/bit
285 movwf T1CON ; ...
240 286
241 287
242 ; RTCC 288 ; RTCC
243 banksel 0xF16 ; addresses, F16h through F5Fh, are also used by SFRs, but are not part of the access RAM 289 banksel 0xF16 ; addresses, F16h through F5Fh, are also used by SFRs, but are not part of the access RAM
244 movlw 0x55 290 movlw 0x55 ; unlock sequence for RTCWREN
245 movwf EECON2 291 movwf EECON2 ; ...
246 movlw 0xAA 292 movlw 0xAA ; ...
247 movwf EECON2 293 movwf EECON2 ; ...
248 bsf RTCCFG,RTCWREN ; unlock sequence for RTCWREN 294 bsf RTCCFG,RTCWREN ; unlock access to RTC
249 bsf RTCCFG,RTCPTR1 295 bsf RTCCFG,RTCPTR1 ; set pointer register to b'11'
250 bsf RTCCFG,RTCPTR0 296 bsf RTCCFG,RTCPTR0 ; ..
251 bsf RTCCFG,RTCEN ; module enable 297 bsf RTCCFG,RTCEN ; module enable
252 bsf RTCCFG,RTCOE ; output enable 298 bsf RTCCFG,RTCOE ; output enable
253 movlw b'00000100' ; 32768 Hz SOCS on RTCC pin (PORTG,4) Bit7-5: pull-ups for Port D, E and J 299 movlw b'00000100' ; 32768 Hz SOCS on RTCC pin (PORTG,4) Bit7-5: pull-ups for Port D, E and J
254 movwf PADCFG1 300 movwf PADCFG1 ; ...
255 movlw b'11000000' 301 movlw b'11000000' ; 1/2 second alarm
256 movwf ALRMCFG ; 1/2 second alarm 302 movwf ALRMCFG ; ...
257 movlw d'1' 303 movlw d'1' ; select alarm repeat counter to 1
258 movwf ALRMRPT ; alarm repeat counter 304 movwf ALRMRPT ; ...
259 movlw 0x55 305 movlw 0x55 ; unlock sequence for RTCWREN
260 movwf EECON2 306 movwf EECON2 ; ...
261 movlw 0xAA 307 movlw 0xAA ; ...
262 movwf EECON2 308 movwf EECON2 ; ...
263 bcf RTCCFG,RTCWREN ; lock sequence for RTCWREN 309 bcf RTCCFG,RTCWREN ; lock access to RTC
264 banksel common 310 banksel common ; back to bank common
265 311
266 312
267 ; A/D Converter 313 ; A/D Converter
268 movlw b'00011000' ; power off ADC, select AN6 314 movlw b'00011000' ; power off ADC, select AN6
269 movwf ADCON0 315 movwf ADCON0 ; ...
270 movlw b'00100000' ; 2.048V Vref+ 316 movlw b'00100000' ; 2.048V Vref+
271 movwf ADCON1 317 movwf ADCON1 ; ...
272 movlw b'10111010' ; right aligned, 20 x T_AD acquisition time, FOSC/32 -> max. 40 MHz device clock speed 318 movlw b'10111010' ; right aligned, 20 x T_AD acquisition time, FOSC/32 -> max. 40 MHz device clock speed
273 movwf ADCON2 319 movwf ADCON2 ; ...
274 320
275 321
276 ; serial Port 1 (TRISC6/7) 322 ; Serial Port 1 (TRISC6/7)
277 movlw b'00001000' ; switch baud generator to 16 bit mode (BRG16=1) 323 movlw b'00001000' ; switch baud generator to 16 bit mode (BRG16=1)
278 movwf BAUDCON1 ; ... 324 movwf BAUDCON1 ; ...
279 ; SPBRGH:SPBRG = .34 : 114285 BAUD @ 16MHz (+0.79% error at 115200 baud) 325 ; SPBRGH:SPBRG = .34 : 114285 BAUD @ 16MHz (+0.79% error at 115200 baud)
280 ; SPBRGH:SPBRG = .207 : 19230 BAUD @ 16MHz (-0.16% error at 19200 baud) 326 ; SPBRGH:SPBRG = .207 : 19230 BAUD @ 16MHz (-0.16% error at 19200 baud)
281 movlw .34 ; select 114285 baud (low byte) 327 movlw .34 ; select 114285 baud (low byte)
285 clrf RCSTA1 ; disable UART RX 331 clrf RCSTA1 ; disable UART RX
286 clrf TXSTA1 ; disable UART TX 332 clrf TXSTA1 ; disable UART TX
287 bcf PORTC,6 ; tie TX output hard to GND 333 bcf PORTC,6 ; tie TX output hard to GND
288 334
289 335
290 ; serial Port 2 (TRISG2) for IR/S8 digital interface 336 ; Serial Port 2 (TRISG2) for IR/S8 digital Interface
291 ; 337 ;
292 ; - will be initialized by enable_ir_s8 (eeprom_rs232.asm) in case IR/S8 shall be available 338 ; - will be initialized by enable_ir_s8 (eeprom_rs232.asm) in case IR/S8 shall be available
293 339
294 340
295 ; Timer 3 for IR-RX Timeout 341 ; Timer 3 for IR-RX Timeout
296 IFDEF _external_sensor 342 IFDEF _external_sensor
297 clrf T3GCON ; reset Timer3 gate control register 343 clrf T3GCON ; clear Timer3 gate control register
298 movlw b'10001101' ; not synced, 1:1 prescaler -> 2 seconds till overrun @ 32768 Hz, 344 ; movlw b'10001101' ; old value
299 ; incrementing by 1 bit each 30.51757813 µs 345 movlw b'10001011' ; bit 7-6: 10 = clock source SOSC/SCLKI (with bit 3 = 1)
300 movwf T3CON 346 ; bit 5-4: 00 = 1:1 prescaler
347 ; bit 3: 1 = clock source SOSC/SCLKI (with bit 7-6 = 10)
348 ; bit 2: 0 = synchronize external clock input
349 ; bit 1: 1 = 16 bit operation
350 ; bit 0: 1 = timer enabled
351 ; 32768 Hz clock source, 1:1 prescaler -> timer counts at 30.51757813 µs/bit
352 movwf T3CON ; ...
301 ENDIF 353 ENDIF
302 354
303 355
304 ; SPI Module(s) 356 ; SPI Module(s)
305 ; SPI2: External Flash 357 ; SPI2: External Flash
306 movlw b'00110000' 358 movlw b'00110000' ; set up SPI module
307 movwf SSP2CON1 359 movwf SSP2CON1 ; ...
308 ; movlw b'00000000' 360 clrf SSP2STAT ; ...
309 clrf SSP2STAT 361 ; resulting bit clocks: 0.25 MHz @ 1 MHz CPU clock (Eco)
310 ; -> 0.25 MHz Bit clock @ 1 MHz mode (Eco) 362 ; 4.00 MHz @ 16 MHz CPU clock (Normal)
311 ; -> 4 MHz Bit clock @ 16 MHz mode (Normal) 363 ; 16.00 MHz @ 64 MHz CPU clock (Fastest)
312 ; -> 16 MHz Bit clock @ 64 MHz mode (Fastest)
313 364
314 365
315 ; MSSP1 Module: I2C Master 366 ; MSSP1 Module: I2C Master
316 movlw b'00101000' ; I2C master mode 367 movlw b'00101000' ; set up I2C to master mode
317 movwf SSP1CON1 368 movwf SSP1CON1 ; ...
318 ; movlw b'00000000' 369 clrf SSP1CON2 ; ...
319 clrf SSP1CON2 370 movlw 0x9C ; select speed 100kHz @ 64MHz Fosc
320 movlw 0x9C 371 movwf SSP1ADD ; ...
321 movwf SSP1ADD ; 100kHz @ 64MHz Fosc
322 372
323 373
324 ; PWM Module(s) 374 ; PWM Module(s)
325 ; PWM 1 for LED dimming 375 ; PWM 1 for LED dimming
326 movlw b'00001100' 376 movlw b'00001100' ; set up PWM module
327 movwf CCP1CON 377 movwf CCP1CON ; ...
328 movlw b'00000001' 378 movlw b'00000001' ; pulse steering disabled
329 movwf PSTR1CON ; pulse steering disabled 379 movwf PSTR1CON ; ...
330 movlw d'254' 380 movlw d'254' ; select period
331 movwf PR2 ; period 381 movwf PR2 ; ...
332 ; 255 is max brightness (300 mW) 382 ; 255 is max brightness (300 mW)
333 clrf CCPR1L ; duty cycle 383 clrf CCPR1L ; duty cycle, low byte
334 clrf CCPR1H ; duty cycle 384 clrf CCPR1H ; duty cycle, high byte
335 movlw T2CON_NORMAL 385 movlw T2CON_NORMAL ; set timer for normal dimming
336 movwf T2CON 386 movwf T2CON ; ...
337 387
338 388
339 ; Timer 5 for ISR-independent wait routines 389 ; Timer 5 for ISR-independent Wait/Timeout
340 clrf T5GCON ; reset Timer5 gate control register 390 clrf T5GCON ; clear Timer5 gate control register
341 movlw b'10001111' ; not synced, 16 bit mode, 1:1 prescaler -> 2 seconds till overrun @ 32768 Hz, 391 ; movlw b'10001111' ; old value
342 movwf T5CON ; incrementing by 1 bit each 30.51757813 µs 392 movlw b'10001011' ; bit 7-6: 10 = clock source SOSC/SCLKI (with bit 3 = 1)
343 393 ; bit 5-4: 00 = 1:1 prescaler
344 394 ; bit 3: 1 = clock source SOSC/SCLKI (with bit 7-6 = 10)
345 banksel 0xF16 ; addresses F16h through F5Fh are also used by SFRs, but are not part of the access RAM 395 ; bit 2: 0 = synchronize external clock input
346 396 ; bit 1: 1 = 16 bit operation
347 ; Timer 7 for 62.5 ms Interrupt (sensor states) 397 ; bit 0: 1 = timer enabled
348 clrf T7GCON ; reset Timer7 gate control register 398 ; 32768 Hz clock source, 1:1 prescaler -> timer counts at 30.51757813 µs/bit
349 movlw b'10001101' ; 1:1 prescaler -> 2 seconds @ 32768 Hz, not synced 399 movwf T5CON ; ...
350 movwf T7CON 400
351 clrf TMR7L 401
352 movlw .248 402 ; turn off unused Timers
353 movwf TMR7H ; -> rollover after 2048 cycles -> 62.5 ms 403 ;banksel 0xF16 ; addresses F16h...F5Fh are not part of the access RAM
354 404 movlw b'11000000' ; disable ECCP3 and ECCP2
355 405 movwf PMD0 ; ...
356 ; turn off unused timers
357 movlw b'11000000'
358 movwf PMD0
359 IFDEF _external_sensor 406 IFDEF _external_sensor
360 movlw b'11010001' 407 movlw b'11010001' ; disable PSP, CTMU, Timer 4 and EMB
361 ELSE 408 ELSE
362 movlw b'11011001' ; includes turning off timer 3 409 movlw b'11011001' ; disable PSP, CTMU, Timer 4, Timer 3 and EMB
363 ENDIF 410 ENDIF
364 movwf PMD1 411 movwf PMD1 ; ...
365 movlw b'11010111' 412 movlw b'11010111' ; disable timer 10, timer 8, timer 6 and comparators 1-3
366 movwf PMD2 413 movwf PMD2 ; ...
367 movlw b'11111111' 414 movlw b'11111111' ; disable CCP 4-10 and timer 12
368 movwf PMD3 415 movwf PMD3 ; ...
369 416
370 417
371 ; turn off unused CTMU 418 ; turn off unused CTMU
372 clrf CTMUCONH 419 ;banksel 0xF16 ; addresses F16h...F5Fh are not part of the access RAM
373 clrf CTMUCONL 420 clrf CTMUCONH ; disable CTMU
374 clrf CTMUICON 421 clrf CTMUCONL ; ...
422 clrf CTMUICON ; ...
423
375 424
376 banksel common 425 banksel common
377 426
378 427
379 ; Interrupts 428 ; Interrupts
380 movlw b'11010000' 429 bcf PIR5,TMR7IF ; if applicable clear timer 7 IRQ flag
381 movwf INTCON 430
382 movlw b'00001000' ; Bit7=1: pull-up for PORTB disabled 431 movlw b'11010000' ; enable global IRQ, peripheral IRQ and external IRQ 0
383 movwf INTCON2 432 movwf INTCON ; ...
384 movlw b'00000000' 433 movlw b'00001000' ; external IRQ 0 on falling edge, pull-up of PORTB by TRIS register
385 movwf INTCON3 434 movwf INTCON2 ; ...
386 movlw b'00000001' ; Bit0: TMR1 435 movlw b'00000000' ; disable external IRQs 1,2,3
387 movwf PIE1 436 movwf INTCON3 ; ...
388 movlw b'00000010' ; Bit1: TMR3 437 movlw b'00000001' ; enable timer 1 IRQ
389 movwf PIE2 438 movwf PIE1 ; ...
390 movlw b'00000000' ; Bit1: TMR5 439 movlw b'00000010' ; enable timer 3 IRQ
391 movwf PIE5 440 movwf PIE2 ; ...
392 movlw b'00000001' ; Bit0: RTCC, Bit5: UART2 (Default OFF) 441 movlw b'00000000' ; enable timer 5 IRQ
393 movwf PIE3 442 movwf PIE5 ; ...
394 movlw b'00001000' ; Bit3: TMR7 443 movlw b'00000001' ; enable RTCC IRQ
395 movwf PIE5 444 movwf PIE3 ; ...
396 445 movlw b'00001000' ; enable timer 7 IRQ
397 bcf active_reset_ostc_rx ; release RESET from RX circuitry 446 movwf PIE5 ; ...
447
448 ; Release RESET from RX Circuitry
449 bcf active_reset_ostc_rx
450
451 ; Power-up the Switches
398 ;bra power_up_switches 452 ;bra power_up_switches
399 453
400 454
455 ;-----------------------------------------------------------------------------
456 ; Power-up the Switches
457 ;
401 global power_up_switches 458 global power_up_switches
402 power_up_switches: 459 power_up_switches:
403 bsf power_sw1 ; switch on power supply for switch 1 460 bsf power_sw1 ; switch on power supply for switch 1
404 btfss power_sw1 ; power established? 461 btfss power_sw1 ; power established?
405 bra $-4 ; NO - wait 462 bra $-4 ; NO - wait
463
406 bsf power_sw2 ; switch on power supply for switch 2 464 bsf power_sw2 ; switch on power supply for switch 2
407 btfss power_sw2 ; power established? 465 btfss power_sw2 ; power established?
408 bra $-4 ; NO - wait 466 bra $-4 ; NO - wait
409 467
410 return 468 return ; done
411 469
412 ;============================================================================= 470
413 ; CPU speed change request functions 471 ;=============================================================================
414 472 hwos2 CODE
473 ;=============================================================================
474
475 ;-----------------------------------------------------------------------------
476 ; CPU Speed Change Requests
477 ;
415 global request_speed_eco 478 global request_speed_eco
416 request_speed_eco: 479 request_speed_eco:
417 movlw coding_speed_eco ; load coding for eco speed 480 movlw coding_speed_eco ; load coding for eco speed
418 movwf cpu_speed_request ; request ISR to change the CPU speed 481 movwf cpu_speed_request ; request ISR to change the CPU speed
419 return ; done 482 return ; done
428 request_speed_fastest: 491 request_speed_fastest:
429 movlw coding_speed_fastest ; load coding for fastest speed 492 movlw coding_speed_fastest ; load coding for fastest speed
430 movwf cpu_speed_request ; request ISR to change the CPU speed 493 movwf cpu_speed_request ; request ISR to change the CPU speed
431 return ; done 494 return ; done
432 495
433 ;============================================================================= 496
434 ; Backup the first 128 bytes from program memory to EEPROM 497 ;=============================================================================
498 hwos3 CODE
499 ;=============================================================================
500
501 ;-----------------------------------------------------------------------------
502 ; Backup the first 128 bytes from program FLASH to EEPROM
435 ; 503 ;
436 global backup_flash_page 504 global backup_flash_page
437 backup_flash_page: 505 backup_flash_page:
438 banksel common 506 banksel common
439 507
440 ; set start address in internal program memory 508 ; set start address in internal program FLASH
441 movlw 0x00 ; set 0x000000 509 movlw 0x00 ; set 0x000000
442 movwf TBLPTRL ; ... 510 movwf TBLPTRL ; ...
443 movwf TBLPTRH ; ... 511 movwf TBLPTRH ; ...
444 movwf TBLPTRU ; ... 512 movwf TBLPTRU ; ...
445 TBLRD*- ; dummy read to be in 128 byte block 513 TBLRD*- ; dummy read to be in 128 byte block
448 EEPROM_SET_ADDRESS eeprom_prog_page0_backup 516 EEPROM_SET_ADDRESS eeprom_prog_page0_backup
449 517
450 movlw .128 ; copy 1 block = 128 byte 518 movlw .128 ; copy 1 block = 128 byte
451 movwf eeprom_loop ; initialize loop counter 519 movwf eeprom_loop ; initialize loop counter
452 backup_flash_loop: 520 backup_flash_loop:
453 tblrd+* ; read one byte from program memory (with pre-increment) 521 tblrd+* ; read one byte from program FLASH (with pre-increment)
454 movff TABLAT,EEDATA ; transfer byte from program memory read to EEPROM write 522 movff TABLAT,EEDATA ; transfer byte from program FLASH read to EEPROM write
455 call write_eeprom ; execute EEPROM write 523 call write_eeprom ; execute EEPROM write
456 incf EEADR,F ; increment EEPROM address 524 incf EEADR,F ; increment EEPROM address
457 decfsz eeprom_loop,F ; all 128 byte done? 525 decfsz eeprom_loop,F ; all 128 byte done?
458 bra backup_flash_loop ; NO - loop 526 bra backup_flash_loop ; NO - loop
459 return ; YES - done 527 return ; YES - done
460 528
461 ;============================================================================= 529
462 ; Restore the first 128 bytes from EEPROM to program memory 530 ;=============================================================================
531 hwos4 CODE
532 ;=============================================================================
533
534 ;-----------------------------------------------------------------------------
535 ; Restore the first 128 bytes from EEPROM to program FLASH
463 ; 536 ;
464 global restore_flash 537 global restore_flash
465 restore_flash: 538 restore_flash:
466 banksel common 539 banksel common
467 540
468 ;set start address in internal program memory 541 ;set start address in internal program FLASH
469 movlw 0x00 ; set 0x000000 542 movlw 0x00 ; set 0x000000
470 movwf TBLPTRL ; ... 543 movwf TBLPTRL ; ...
471 movwf TBLPTRH ; ... 544 movwf TBLPTRH ; ...
472 movwf TBLPTRU ; ... 545 movwf TBLPTRU ; ...
473 TBLRD*- ; dummy read to be in 128 byte block 546 TBLRD*- ; dummy read to be in 128 byte block
481 movlw .128 ; copy 1 block = 128 byte 554 movlw .128 ; copy 1 block = 128 byte
482 movwf eeprom_loop ; initialize loop counter 555 movwf eeprom_loop ; initialize loop counter
483 restore_flash_loop: 556 restore_flash_loop:
484 call read_eeprom ; execute EEPROM read 557 call read_eeprom ; execute EEPROM read
485 incf EEADR,F ; increment EEPROM address 558 incf EEADR,F ; increment EEPROM address
486 movff EEDATA,TABLAT ; transfer byte from EEPROM read to program memory write 559 movff EEDATA,TABLAT ; transfer byte from EEPROM read to program FLASH write
487 tblwt+* ; execute program memory write (with pre-increment) 560 tblwt+* ; execute program FLASH write (with pre-increment)
488 decfsz eeprom_loop,F ; all 128 bytes done? 561 decfsz eeprom_loop,F ; all 128 bytes done?
489 bra restore_flash_loop ; NO - loop 562 bra restore_flash_loop ; NO - loop
490 movlw b'10000100' ; YES - setup block write 563 movlw b'10000100' ; YES - setup block write
491 rcall restore_write ; - execute block write 564 rcall restore_write ; - execute block write
492 reset ; - done, reset CPU 565 reset ; - done, reset CPU
500 bsf EECON1,WR ; execute operation 573 bsf EECON1,WR ; execute operation
501 nop ; wait for operation to complete 574 nop ; wait for operation to complete
502 nop ; ... 575 nop ; ...
503 return ; done 576 return ; done
504 577
505 ;============================================================================= 578
506 ; Memory clear and move functions, to be used through macros 579 ;=============================================================================
580 hwos5 CODE
581 ;=============================================================================
582
583 ;-----------------------------------------------------------------------------
584 ; Memory clear and move Functions, to be used via Macros
507 ; 585 ;
508 global memory_clear 586 global memory_clear
509 memory_clear: 587 memory_clear:
510 clrf POSTINC1 ; clear address 588 clrf POSTINC1 ; clear address
511 decfsz WREG ; decrement loop counter, became zero? 589 decfsz WREG ; decrement loop counter, became zero?
517 movff POSTINC1,POSTINC2 ; copy from-to 595 movff POSTINC1,POSTINC2 ; copy from-to
518 decfsz WREG ; decrement loop counter, became zero? 596 decfsz WREG ; decrement loop counter, became zero?
519 bra memory_move ; NO - loop 597 bra memory_move ; NO - loop
520 return ; YES - done 598 return ; YES - done
521 599
600
601 ;=============================================================================
602 hwos6 CODE
603 ;=============================================================================
604
605 ;-----------------------------------------------------------------------------
606 ; Read CPU Silicon Version
607 ;
608 global get_cpu_version
609 get_cpu_version:
610 movlw 0xFE ; select address 0x3FFFFE
611 movwf TBLPTRL ; ...
612 movlw 0xFF ; ...
613 movwf TBLPTRH ; ...
614 movlw 0x3F ; ...
615 movwf TBLPTRU ; ...
616 TBLRD*+ ; read DEVID1 byte
617 movlw b'00011111' ; load mask for silicon version
618 andwf TABLAT,W ; apply mask and store result in WREG
619 return ; done
620
621 ;-----------------------------------------------------------------------------
622
522 END 623 END