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1 ;=============================================================================
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2 ;
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634
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3 ; File hwos.asm * combined next generation V3.09.4e
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4 ;
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275
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5 ; Definition of the hwOS dive computer platform.
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6 ;
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7 ; Copyright (c) 2011, JD Gascuel, HeinrichsWeikamp, all right reserved.
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8 ;=============================================================================
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9 ; HISTORY
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10 ; 2011-05-24 : [jDG] Cleanups from initial Matthias code
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11 ; 2011-06-24 : [MH] Added clock speeds
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12
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13 ;=============================================================================
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14
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634
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15 #DEFINE INSIDE_HWOS_ASM
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16
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275
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17 #include "hwos.inc"
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18 #include "eeprom_rs232.inc"
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19
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20 ;----------------------------- PIC Configuration -----------------------------
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21 ;
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22 CONFIG RETEN = OFF ; regulator power while in sleep mode controlled by SRETEN bit
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23 CONFIG SOSCSEL = HIGH ; high power SOSC circuit selected
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24 CONFIG XINST = OFF ; extended instruction set disabled
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25 CONFIG FOSC = INTIO2 ; internal RC oscillator, no clock-out
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26 CONFIG PLLCFG = OFF ; oscillator used directly
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27 CONFIG IESO = OFF ; two-speed start-up disabled
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28 CONFIG PWRTEN = OFF ; power-up timer disabled, because incompatible with ICD3 (Ri-400)
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29 CONFIG BOREN = ON ; brown-out reset controlled with SBOREN bit
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30 CONFIG BORV = 2 ; brown-out reset voltage 2.0V
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31 CONFIG BORPWR = MEDIUM ; brown-out monitoring set to medium power level
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32 CONFIG WDTEN = ON ; watchdog timer enabled, controlled by SWDTEN bit
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33 CONFIG WDTPS = 128 ; watchdog timer post-scaler 1:128
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34 CONFIG RTCOSC = SOSCREF ; RTCC uses SOSC as ref clock
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35 CONFIG MCLRE = ON ; MCLR enabled, RG5 disabled
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36 CONFIG CCP2MX = PORTBE ; ECCP2 muxed with RE7 (micro-controller mode) /RB3 (other modes)
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37
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38
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39 ;---------------------------- Bank0 ACCESS RAM -------------------------------
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40 ;
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41 ac_ram equ 0x000
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42 ac_ram udata_acs ac_ram ; access RAM data
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43
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44
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45 ;---- Flags - Hardware Descriptors
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46 HW_descriptor res 1 ; OSTC - model descriptor (cleared & rebuilt in restart)
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47 HW_variants res 1 ; OSTC - model variants (NOT cleared in restart)
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48
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49 ;---- Flags - Hardware States
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50 HW_flags_state1 res 1 ; hardware - states 1
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51 HW_flags_state2 res 1 ; hardware - states 2
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52
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53 ;--- Flags - Operating System
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54 OS_flags_persist res 1 ; system - persistent settings (NOT cleared in restart)
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55 OS_flags_ISR1 res 1 ; system - ISR control 1
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56 OS_flags_ISR2 res 1 ; system - ISR control 2
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57
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58 ;---- Flags - Operating Modes
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59 OM_flags_mode res 1 ; operating modes
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60
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61 ;---- Flags - Dive Modes
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62 DM_flags_deco res 1 ; dive mode - main dive & deco mode
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63
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64 ;---- CPU Speed
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65 cpu_speed_request res 1 ; requested CPU speed: =1: eco, =2: normal, =3: fastest
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66 cpu_speed_state res 1 ; current CPU speed: =1: eco, =2: normal, =3: fastest
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67
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68 ;---- Timebase & Eventbase
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69 timebase res 1 ; timed trigger flags and running timebase
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70 eventbase res 1 ; event trigger flags
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71
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72 ;---- Timeout-Timer Service
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73 isr_timeout_timer res 1 ; timeout timer
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74 isr_timeout_reload res 1 ; timeout reload value
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75
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76 ;---- Dive Times
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77 total_divetime_secs res 2 ; total dive time, seconds
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78 counted_divetime_mins res 2 ; counted dive time, minutes | Attention: do not change the position of
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79 counted_divetime_secs res 1 ; counted dive time, seconds | these 2 Variables relative to each other!
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80
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81 ;---- Dive Times / Apnoe
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82 apnoe_surface_mins res 1 ; surface time minutes | Attention: do not change the position of
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83 apnoe_surface_secs res 1 ; surface time seconds | these 2 Variables relative to each other!
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84
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85 apnoe_dive_mins res 1 ; dive time minutes | Attention: do not change the position of
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86 apnoe_dive_secs res 1 ; dive time seconds | these 2 Variables relative to each other!
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87
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88 ;---- Profile Recording
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89 sampling_rate res 1 ; configured sampling rate
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90 sampling_timer res 1 ; sampling timer
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91
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92 ;---- Simulator Mode
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93 simulatormode_depth res 1 ; depth in simulator mode
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94
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95 ;---- HUD / Sensor Data
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96 hud_status_byte res 1 ; HUD status byte, see definition of flags | Attention: keep relative position
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97 hud_battery_mv res 2 ; hud/ppo2 monitor battery voltage in mV | between these two variables!
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98
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99 ;---- Battery Management
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100 battery_capacity_internal res 2 ; for internal battery gauging
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101 battery_capacity res 2 ; for battery gauge IC
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102 battery_offset res 2 ; for battery gauge IC
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103 battery_type res 1 ; =0:1.5V, =1:3.6V Saft, =2:LiIon 3.7V/0.8Ah, =3:LiIon 3.7V/3.1Ah, =4: LiIon 3.7V/2.3Ah
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104 battery_accumulated_charge res 2 ; raw values in battery gauge IC
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105 battery_temperature res 2 ; battery temperature in 0.1 Kelvin
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106 gauge_status_byte res 1 ; gauge IC status byte
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107
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108
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109
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110 ; 40 byte user data
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111 ; 32 byte tmp data placed by C compiler
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112 ; 20 byte variables placed by math library
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113 ; ==
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114 ; 92 byte used, 4 byte free (96 byte total available)
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115
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116
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117 global HW_descriptor
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118 global HW_variants
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119 global HW_flags_state1
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120 global HW_flags_state2
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121 global OS_flags_persist
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122 global OS_flags_ISR1
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123 global OS_flags_ISR2
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124 global OM_flags_mode
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125 global DM_flags_deco
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126 global cpu_speed_request
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127 global cpu_speed_state
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128 global timebase
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129 global eventbase
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130 global isr_timeout_timer
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131 global isr_timeout_reload
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132 global total_divetime_secs
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133 global counted_divetime_mins
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134 global counted_divetime_secs
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135 global apnoe_surface_secs
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136 global apnoe_surface_mins
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137 global apnoe_dive_secs
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138 global apnoe_dive_mins
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139 global sampling_rate
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140 global sampling_timer
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141 global simulatormode_depth
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142 global hud_status_byte
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143 global hud_battery_mv
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144 global battery_capacity_internal
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145 global battery_capacity
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146 global battery_offset
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147 global battery_type
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148 global battery_accumulated_charge
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149 global battery_temperature
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150 global gauge_status_byte
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151
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152
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153 ;=============================================================================
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154 hwos1 CODE
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155 ;=============================================================================
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156
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157 ;-----------------------------------------------------------------------------
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158 ; Master Initialization of Hardware Resources
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159 ;
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160 global init_ostc
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161 init_ostc:
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162
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163 ; Oscillator
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164 banksel common ; select bank common
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165 movlw b'01110010' ; select 16 MHz INTOSC
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166 movwf OSCCON ; ...
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167 movlw b'00001000' ; secondary oscillator running
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168 movwf OSCCON2 ; ...
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169 movlw b'00000000' ; 4x PLL disable (Bit 6) - only works with 8 or 16MHz (=32 or 64MHz)
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170 movwf OSCTUNE ; ...
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171
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172 movlw coding_speed_normal ; coding for normal CPU speed
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173 movwf cpu_speed_request ; store CPU shall run with normal speed
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174 movwf cpu_speed_state ; store CPU does run with normal speed
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175
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176 ;bcf RCON,SBOREN ; brown-out off (not needed here, is handled in bootloader)
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177 bcf RCON,IPEN ; priority interrupts off
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178
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179 banksel WDTCON
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180 movlw b'10000000' ; setup watchdog
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181 movwf WDTCON ; ...
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182
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183
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184 ; I/O Ports
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185 banksel 0xF16 ; addresses F16h ... F5Fh are not part of the access RAM
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186
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187 clrf REFOCON ; no reference oscillator active on REFO pin
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188 clrf ODCON1 ; disable open drain capability
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189 clrf ODCON2 ; disable open drain capability
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190 clrf ODCON3 ; disable open drain capability
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191 clrf CM1CON ; disable comparator 1
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192 clrf CM2CON ; disable comparator 2
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193 clrf CM3CON ; disable comparator 3
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194
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195 movlw b'11000000' ; ANSEL0: AN7, AN6 -> analog inputs, PORTA is digital
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196 movwf ANCON0 ; ...
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197 movlw b'00000111' ; ANSEL1: AN8, AN9, AN10 -> analog input
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198 movwf ANCON1 ; ...
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199 movlw b'00000010' ; ANSEL2: AN17 -> analog input
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200 movwf ANCON2 ; ...
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201
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202 banksel common ; back to bank common
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203
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204 ; movlw b'00000000' ; 1= input -> Data TFT_high
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205 clrf TRISA ; ...
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206 ; movlw b'00000000' ; init port
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207 clrf PORTA ; ...
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208
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209 movlw b'00000011' ; 1= input, (RB0, RB1) -> switches, RB2 -> Power_MCP, RB3 -> s8_npower, RB4 -> LED_green/rx_nreset, RB5 -> /TFT_POWER
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210 movwf TRISB ; ...
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211 movlw b'00111000' ; init port, rx_nreset=1 -> hard reset RX
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212 movwf PORTB ; ...
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213
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214 movlw b'10011010' ; 1= input, (RC0, RC1) -> SOSC, RC2 -> TFT_LED_PWM, (RC3,RC4) -> I²C, RC5 -> MOSI_MS5541, (RC6, RC7) -> UART1
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215 movwf TRISC ; ...
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216 ; movlw b'00000000' ; init port
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217 clrf PORTC ; ...
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218
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219 movlw b'00100000' ; 1= input, RD0 -> TFT_NCS, RD1 -> TFT_RS, RD2 -> TFT_NWR, RD3 -> TFT_RD, RD4 -> MOSI_Flash, RD5 -> MISO_Flash, RD6 -> CLK_Flash, RD7 -> TFT_NRESET
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220 movwf TRISD ; ...
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221 ; movlw b'00000000' ; init port
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222 clrf PORTD ; ...
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223
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224 movlw b'00100000' ; 1= input, RE0 -> not_Power_BLE, RE1 -> Power_IR, RE2 -> CS_MCP, RE3 -> LED_blue, RE4 -> power_sw1, RE5 -> leave as input
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225 movwf TRISE ; ...
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226 movlw b'00010001' ; init port
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227 movwf PORTE ; ...
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228
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229 movlw b'01111110' ; 1= input, (RF1, RF2, RF3, RF4, RF5) -> Analog
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230 movwf TRISF ; ...
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231 ; movlw b'00000000' ; init port
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232 clrf PORTF ; ...
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233
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234 movlw b'00001110' ; 1= input, <7:6> not implemented, RG0 -> TX3_PIEZO_CFG, , RG1 -> TX2, RG2 -> RX2, RG3 -> AN17_RSSI, RG4 -> SOSC_OUT, RG5 -> /RESET
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235 movwf TRISG ; ...
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236 movlw b'00000001' ; init port
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237 movwf PORTG ; ...
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238
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239 ; movlw b'00000000' ; 1= input -> Data TFT_low
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240 clrf TRISH ; ...
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241 ; movlw b'00000000' ; init port
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242 clrf PORTH ; ...
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243
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244 movlw b'10011011' ; 1= input, RJ4 -> vusb_in, RJ5 -> power_sw2, RJ6 -> CLK_MS5541, RJ7 -> MISO_MS5541
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245 movwf TRISJ ; ...
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246 movlw b'00100000' ; init port
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247 movwf PORTJ ; ...
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248
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249
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250 ; disable Charger by default
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251 bsf charge_disable ; set charging-inhibit signal
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252 bcf charge_enable ; activate charging-inhibit signal
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253
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254
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255 ; Timer 7 for 62.5 ms Interrupt (Sensor States)
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256 banksel 0xF16 ; addresses F16h...F5Fh are not part of the access RAM
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257 clrf T7GCON ; clear timer 7 gate control register
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258 movlw b'10001101' ; bit 7-6: 10 = clock source SOSC/SCLKI (with bit 3 = 1)
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259 ; bit 5-4: 00 = 1:1 prescaler
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260 ; bit 3: 1 = clock source SOSC/SCLKI (with bit 7-6 = 10)
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261 ; bit 2: 1 = DO NOT synchronize external clock input (else OSTC won't wake up from sleep!)
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262 ; bit 1: 0 = 2x 8 bit operation
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263 ; bit 0: 1 = timer enabled
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264 ; 32768 Hz clock source, 1:1 prescaler -> timer counts at 30.51757813 µs/bit
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265 movwf T7CON ; ...
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266 movlw .248 ; load timer 7, high byte (8x256 ticks -> 62.5 ms)
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267 movwf TMR7H ; ...
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268 clrf TMR7L ; load timer 7, low byte
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269
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270
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271 ; Timer 0 - not used
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272 movlw b'00000001' ; timer0 stopped (1:4 prescaler)
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273 movwf T0CON ; ...
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274
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275
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276 ; Timer 1 - Button hold-down Timer
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277 ; movlw b'10001100' ; old setting
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278 movlw b'10001010' ; bit 7-6: 10 = clock source SOSC/SCLKI (with bit 3 = 1)
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279 ; bit 5-4: 00 = 1:1 prescaler
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280 ; bit 3: 1 = clock source SOSC/SCLKI (with bit 7-6 = 10)
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281 ; bit 2: 0 = synchronize external clock input
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282 ; bit 1: 1 = 16 bit operation
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283 ; bit 0: 0 = timer stopped
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284 ; 32768 Hz clock source, 1:1 prescaler -> timer counts at 30.51757813 µs/bit
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285 movwf T1CON ; ...
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0
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286
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287
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0
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288 ; RTCC
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289 banksel 0xF16 ; addresses, F16h through F5Fh, are also used by SFRs, but are not part of the access RAM
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290 movlw 0x55 ; unlock sequence for RTCWREN
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291 movwf EECON2 ; ...
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292 movlw 0xAA ; ...
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293 movwf EECON2 ; ...
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294 bsf RTCCFG,RTCWREN ; unlock access to RTC
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295 bsf RTCCFG,RTCPTR1 ; set pointer register to b'11'
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296 bsf RTCCFG,RTCPTR0 ; ..
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297 bsf RTCCFG,RTCEN ; module enable
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298 bsf RTCCFG,RTCOE ; output enable
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299 movlw b'00000100' ; 32768 Hz SOCS on RTCC pin (PORTG,4) Bit7-5: pull-ups for Port D, E and J
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300 movwf PADCFG1 ; ...
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301 movlw b'11000000' ; 1/2 second alarm
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302 movwf ALRMCFG ; ...
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303 movlw d'1' ; select alarm repeat counter to 1
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304 movwf ALRMRPT ; ...
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305 movlw 0x55 ; unlock sequence for RTCWREN
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306 movwf EECON2 ; ...
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307 movlw 0xAA ; ...
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308 movwf EECON2 ; ...
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309 bcf RTCCFG,RTCWREN ; lock access to RTC
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310 banksel common ; back to bank common
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311
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614
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312
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0
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313 ; A/D Converter
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314 movlw b'00011000' ; power off ADC, select AN6
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315 movwf ADCON0 ; ...
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0
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316 movlw b'00100000' ; 2.048V Vref+
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317 movwf ADCON1 ; ...
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318 movlw b'10111010' ; right aligned, 20 x T_AD acquisition time, FOSC/32 -> max. 40 MHz device clock speed
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319 movwf ADCON2 ; ...
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320
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321
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322 ; Serial Port 1 (TRISC6/7)
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323 movlw b'00001000' ; switch baud generator to 16 bit mode (BRG16=1)
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324 movwf BAUDCON1 ; ...
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325 ; SPBRGH:SPBRG = .34 : 114285 BAUD @ 16MHz (+0.79% error at 115200 baud)
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326 ; SPBRGH:SPBRG = .207 : 19230 BAUD @ 16MHz (-0.16% error at 19200 baud)
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327 movlw .34 ; select 114285 baud (low byte)
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328 movwf SPBRG1 ; ...
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329 clrf SPBRGH1 ; ... (high byte)
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204
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330
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331 clrf RCSTA1 ; disable UART RX
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332 clrf TXSTA1 ; disable UART TX
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333 bcf PORTC,6 ; tie TX output hard to GND
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0
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334
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623
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335
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634
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336 ; Serial Port 2 (TRISG2) for IR/S8 digital Interface
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623
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337 ;
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338 ; - will be initialized by enable_ir_s8 (eeprom_rs232.asm) in case IR/S8 shall be available
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339
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0
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340
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623
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341 ; Timer 3 for IR-RX Timeout
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342 IFDEF _external_sensor
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634
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343 clrf T3GCON ; clear Timer3 gate control register
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344 ; movlw b'10001101' ; old value
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345 movlw b'10001011' ; bit 7-6: 10 = clock source SOSC/SCLKI (with bit 3 = 1)
|
|
|
346 ; bit 5-4: 00 = 1:1 prescaler
|
|
|
347 ; bit 3: 1 = clock source SOSC/SCLKI (with bit 7-6 = 10)
|
|
|
348 ; bit 2: 0 = synchronize external clock input
|
|
|
349 ; bit 1: 1 = 16 bit operation
|
|
|
350 ; bit 0: 1 = timer enabled
|
|
|
351 ; 32768 Hz clock source, 1:1 prescaler -> timer counts at 30.51757813 µs/bit
|
|
|
352 movwf T3CON ; ...
|
|
623
|
353 ENDIF
|
|
|
354
|
|
0
|
355
|
|
|
356 ; SPI Module(s)
|
|
|
357 ; SPI2: External Flash
|
|
634
|
358 movlw b'00110000' ; set up SPI module
|
|
|
359 movwf SSP2CON1 ; ...
|
|
|
360 clrf SSP2STAT ; ...
|
|
|
361 ; resulting bit clocks: 0.25 MHz @ 1 MHz CPU clock (Eco)
|
|
|
362 ; 4.00 MHz @ 16 MHz CPU clock (Normal)
|
|
|
363 ; 16.00 MHz @ 64 MHz CPU clock (Fastest)
|
|
623
|
364
|
|
0
|
365
|
|
|
366 ; MSSP1 Module: I2C Master
|
|
634
|
367 movlw b'00101000' ; set up I2C to master mode
|
|
|
368 movwf SSP1CON1 ; ...
|
|
|
369 clrf SSP1CON2 ; ...
|
|
|
370 movlw 0x9C ; select speed 100kHz @ 64MHz Fosc
|
|
|
371 movwf SSP1ADD ; ...
|
|
0
|
372
|
|
623
|
373
|
|
0
|
374 ; PWM Module(s)
|
|
623
|
375 ; PWM 1 for LED dimming
|
|
634
|
376 movlw b'00001100' ; set up PWM module
|
|
|
377 movwf CCP1CON ; ...
|
|
|
378 movlw b'00000001' ; pulse steering disabled
|
|
|
379 movwf PSTR1CON ; ...
|
|
|
380 movlw d'254' ; select period
|
|
|
381 movwf PR2 ; ...
|
|
604
|
382 ; 255 is max brightness (300 mW)
|
|
634
|
383 clrf CCPR1L ; duty cycle, low byte
|
|
|
384 clrf CCPR1H ; duty cycle, high byte
|
|
|
385 movlw T2CON_NORMAL ; set timer for normal dimming
|
|
|
386 movwf T2CON ; ...
|
|
623
|
387
|
|
0
|
388
|
|
634
|
389 ; Timer 5 for ISR-independent Wait/Timeout
|
|
|
390 clrf T5GCON ; clear Timer5 gate control register
|
|
|
391 ; movlw b'10001111' ; old value
|
|
|
392 movlw b'10001011' ; bit 7-6: 10 = clock source SOSC/SCLKI (with bit 3 = 1)
|
|
|
393 ; bit 5-4: 00 = 1:1 prescaler
|
|
|
394 ; bit 3: 1 = clock source SOSC/SCLKI (with bit 7-6 = 10)
|
|
|
395 ; bit 2: 0 = synchronize external clock input
|
|
|
396 ; bit 1: 1 = 16 bit operation
|
|
|
397 ; bit 0: 1 = timer enabled
|
|
|
398 ; 32768 Hz clock source, 1:1 prescaler -> timer counts at 30.51757813 µs/bit
|
|
|
399 movwf T5CON ; ...
|
|
0
|
400
|
|
623
|
401
|
|
634
|
402 ; turn off unused Timers
|
|
|
403 ;banksel 0xF16 ; addresses F16h...F5Fh are not part of the access RAM
|
|
|
404 movlw b'11000000' ; disable ECCP3 and ECCP2
|
|
|
405 movwf PMD0 ; ...
|
|
623
|
406 IFDEF _external_sensor
|
|
634
|
407 movlw b'11010001' ; disable PSP, CTMU, Timer 4 and EMB
|
|
623
|
408 ELSE
|
|
634
|
409 movlw b'11011001' ; disable PSP, CTMU, Timer 4, Timer 3 and EMB
|
|
623
|
410 ENDIF
|
|
634
|
411 movwf PMD1 ; ...
|
|
|
412 movlw b'11010111' ; disable timer 10, timer 8, timer 6 and comparators 1-3
|
|
|
413 movwf PMD2 ; ...
|
|
|
414 movlw b'11111111' ; disable CCP 4-10 and timer 12
|
|
|
415 movwf PMD3 ; ...
|
|
608
|
416
|
|
623
|
417
|
|
|
418 ; turn off unused CTMU
|
|
634
|
419 ;banksel 0xF16 ; addresses F16h...F5Fh are not part of the access RAM
|
|
|
420 clrf CTMUCONH ; disable CTMU
|
|
|
421 clrf CTMUCONL ; ...
|
|
|
422 clrf CTMUICON ; ...
|
|
|
423
|
|
623
|
424
|
|
604
|
425 banksel common
|
|
608
|
426
|
|
623
|
427
|
|
0
|
428 ; Interrupts
|
|
634
|
429 bcf PIR5,TMR7IF ; if applicable clear timer 7 IRQ flag
|
|
0
|
430
|
|
634
|
431 movlw b'11010000' ; enable global IRQ, peripheral IRQ and external IRQ 0
|
|
|
432 movwf INTCON ; ...
|
|
|
433 movlw b'00001000' ; external IRQ 0 on falling edge, pull-up of PORTB by TRIS register
|
|
|
434 movwf INTCON2 ; ...
|
|
|
435 movlw b'00000000' ; disable external IRQs 1,2,3
|
|
|
436 movwf INTCON3 ; ...
|
|
|
437 movlw b'00000001' ; enable timer 1 IRQ
|
|
|
438 movwf PIE1 ; ...
|
|
|
439 movlw b'00000010' ; enable timer 3 IRQ
|
|
|
440 movwf PIE2 ; ...
|
|
|
441 movlw b'00000000' ; enable timer 5 IRQ
|
|
|
442 movwf PIE5 ; ...
|
|
|
443 movlw b'00000001' ; enable RTCC IRQ
|
|
|
444 movwf PIE3 ; ...
|
|
|
445 movlw b'00001000' ; enable timer 7 IRQ
|
|
|
446 movwf PIE5 ; ...
|
|
|
447
|
|
|
448 ; Release RESET from RX Circuitry
|
|
|
449 bcf active_reset_ostc_rx
|
|
|
450
|
|
|
451 ; Power-up the Switches
|
|
623
|
452 ;bra power_up_switches
|
|
|
453
|
|
0
|
454
|
|
634
|
455 ;-----------------------------------------------------------------------------
|
|
|
456 ; Power-up the Switches
|
|
|
457 ;
|
|
623
|
458 global power_up_switches
|
|
|
459 power_up_switches:
|
|
|
460 bsf power_sw1 ; switch on power supply for switch 1
|
|
|
461 btfss power_sw1 ; power established?
|
|
|
462 bra $-4 ; NO - wait
|
|
634
|
463
|
|
623
|
464 bsf power_sw2 ; switch on power supply for switch 2
|
|
|
465 btfss power_sw2 ; power established?
|
|
|
466 bra $-4 ; NO - wait
|
|
204
|
467
|
|
634
|
468 return ; done
|
|
|
469
|
|
0
|
470
|
|
|
471 ;=============================================================================
|
|
634
|
472 hwos2 CODE
|
|
|
473 ;=============================================================================
|
|
623
|
474
|
|
634
|
475 ;-----------------------------------------------------------------------------
|
|
|
476 ; CPU Speed Change Requests
|
|
|
477 ;
|
|
623
|
478 global request_speed_eco
|
|
|
479 request_speed_eco:
|
|
|
480 movlw coding_speed_eco ; load coding for eco speed
|
|
|
481 movwf cpu_speed_request ; request ISR to change the CPU speed
|
|
|
482 return ; done
|
|
|
483
|
|
|
484 global request_speed_normal
|
|
|
485 request_speed_normal:
|
|
|
486 movlw coding_speed_normal ; load coding for normal speed
|
|
|
487 movwf cpu_speed_request ; request ISR to change the CPU speed
|
|
|
488 return ; done
|
|
|
489
|
|
|
490 global request_speed_fastest
|
|
|
491 request_speed_fastest:
|
|
|
492 movlw coding_speed_fastest ; load coding for fastest speed
|
|
|
493 movwf cpu_speed_request ; request ISR to change the CPU speed
|
|
|
494 return ; done
|
|
|
495
|
|
634
|
496
|
|
0
|
497 ;=============================================================================
|
|
634
|
498 hwos3 CODE
|
|
|
499 ;=============================================================================
|
|
|
500
|
|
|
501 ;-----------------------------------------------------------------------------
|
|
|
502 ; Backup the first 128 bytes from program FLASH to EEPROM
|
|
623
|
503 ;
|
|
|
504 global backup_flash_page
|
|
|
505 backup_flash_page:
|
|
|
506 banksel common
|
|
631
|
507
|
|
634
|
508 ; set start address in internal program FLASH
|
|
631
|
509 movlw 0x00 ; set 0x000000
|
|
|
510 movwf TBLPTRL ; ...
|
|
|
511 movwf TBLPTRH ; ...
|
|
|
512 movwf TBLPTRU ; ...
|
|
|
513 TBLRD*- ; dummy read to be in 128 byte block
|
|
|
514
|
|
|
515 ; set start address in EEPROM
|
|
|
516 EEPROM_SET_ADDRESS eeprom_prog_page0_backup
|
|
623
|
517
|
|
|
518 movlw .128 ; copy 1 block = 128 byte
|
|
631
|
519 movwf eeprom_loop ; initialize loop counter
|
|
623
|
520 backup_flash_loop:
|
|
634
|
521 tblrd+* ; read one byte from program FLASH (with pre-increment)
|
|
|
522 movff TABLAT,EEDATA ; transfer byte from program FLASH read to EEPROM write
|
|
631
|
523 call write_eeprom ; execute EEPROM write
|
|
623
|
524 incf EEADR,F ; increment EEPROM address
|
|
631
|
525 decfsz eeprom_loop,F ; all 128 byte done?
|
|
623
|
526 bra backup_flash_loop ; NO - loop
|
|
631
|
527 return ; YES - done
|
|
623
|
528
|
|
634
|
529
|
|
0
|
530 ;=============================================================================
|
|
634
|
531 hwos4 CODE
|
|
|
532 ;=============================================================================
|
|
|
533
|
|
|
534 ;-----------------------------------------------------------------------------
|
|
|
535 ; Restore the first 128 bytes from EEPROM to program FLASH
|
|
623
|
536 ;
|
|
|
537 global restore_flash
|
|
|
538 restore_flash:
|
|
|
539 banksel common
|
|
631
|
540
|
|
634
|
541 ;set start address in internal program FLASH
|
|
631
|
542 movlw 0x00 ; set 0x000000
|
|
|
543 movwf TBLPTRL ; ...
|
|
|
544 movwf TBLPTRH ; ...
|
|
|
545 movwf TBLPTRU ; ...
|
|
|
546 TBLRD*- ; dummy read to be in 128 byte block
|
|
623
|
547
|
|
|
548 movlw b'10010100' ; setup block erase
|
|
|
549 rcall restore_write ; execute block erase
|
|
|
550
|
|
631
|
551 ; set start address in EEPROM
|
|
|
552 EEPROM_SET_ADDRESS eeprom_prog_page0_backup
|
|
623
|
553
|
|
631
|
554 movlw .128 ; copy 1 block = 128 byte
|
|
|
555 movwf eeprom_loop ; initialize loop counter
|
|
623
|
556 restore_flash_loop:
|
|
631
|
557 call read_eeprom ; execute EEPROM read
|
|
623
|
558 incf EEADR,F ; increment EEPROM address
|
|
634
|
559 movff EEDATA,TABLAT ; transfer byte from EEPROM read to program FLASH write
|
|
|
560 tblwt+* ; execute program FLASH write (with pre-increment)
|
|
631
|
561 decfsz eeprom_loop,F ; all 128 bytes done?
|
|
|
562 bra restore_flash_loop ; NO - loop
|
|
623
|
563 movlw b'10000100' ; YES - setup block write
|
|
|
564 rcall restore_write ; - execute block write
|
|
|
565 reset ; - done, reset CPU
|
|
|
566
|
|
|
567 restore_write:
|
|
631
|
568 movwf EECON1 ; configure operation
|
|
|
569 movlw 0x55 ; unlock sequence
|
|
|
570 movwf EECON2 ; ...
|
|
|
571 movlw 0xAA ; ...
|
|
|
572 movwf EECON2 ; ...
|
|
|
573 bsf EECON1,WR ; execute operation
|
|
|
574 nop ; wait for operation to complete
|
|
|
575 nop ; ...
|
|
|
576 return ; done
|
|
|
577
|
|
634
|
578
|
|
631
|
579 ;=============================================================================
|
|
634
|
580 hwos5 CODE
|
|
|
581 ;=============================================================================
|
|
|
582
|
|
|
583 ;-----------------------------------------------------------------------------
|
|
|
584 ; Memory clear and move Functions, to be used via Macros
|
|
631
|
585 ;
|
|
|
586 global memory_clear
|
|
|
587 memory_clear:
|
|
|
588 clrf POSTINC1 ; clear address
|
|
|
589 decfsz WREG ; decrement loop counter, became zero?
|
|
|
590 bra memory_clear ; NO - loop
|
|
|
591 return ; YES - done
|
|
|
592
|
|
|
593 global memory_move
|
|
|
594 memory_move:
|
|
|
595 movff POSTINC1,POSTINC2 ; copy from-to
|
|
|
596 decfsz WREG ; decrement loop counter, became zero?
|
|
|
597 bra memory_move ; NO - loop
|
|
|
598 return ; YES - done
|
|
0
|
599
|
|
634
|
600
|
|
|
601 ;=============================================================================
|
|
|
602 hwos6 CODE
|
|
|
603 ;=============================================================================
|
|
|
604
|
|
|
605 ;-----------------------------------------------------------------------------
|
|
|
606 ; Read CPU Silicon Version
|
|
|
607 ;
|
|
|
608 global get_cpu_version
|
|
|
609 get_cpu_version:
|
|
|
610 movlw 0xFE ; select address 0x3FFFFE
|
|
|
611 movwf TBLPTRL ; ...
|
|
|
612 movlw 0xFF ; ...
|
|
|
613 movwf TBLPTRH ; ...
|
|
|
614 movlw 0x3F ; ...
|
|
|
615 movwf TBLPTRU ; ...
|
|
|
616 TBLRD*+ ; read DEVID1 byte
|
|
|
617 movlw b'00011111' ; load mask for silicon version
|
|
|
618 andwf TABLAT,W ; apply mask and store result in WREG
|
|
|
619 return ; done
|
|
|
620
|
|
|
621 ;-----------------------------------------------------------------------------
|
|
|
622
|
|
|
623 END
|
