Bugfix simulator/planer: For deco calculation two structures are used. The calculation structure and the input structure. During simulation fast forward (+5min) the input structure is manipulated. Especially for vpm calculation it could happen that the input structure was manipulated and then overwritten by the calculation structure => deco and tts may have wrong values. To avoid this thedeco calculation status is now checked before doing the FF manupulation. Based an calculation state deco or input structures are manipulated. Surface time stamp in planer view: The planer used its own (buggy) implementation for calculation of tts. The timestamp for the surface arrival did not match the bottom time + TTS. The new implementation uses the tts calculated by the deco loop for generation of surface time stamp.

#! openocd -f
# Define the prob used:
source [find interface/stlink-v2.cfg]
set WORKAREASIZE 0x8000
transport select hla_swd

# Reset options
set ENABLE_LOW_POWER 1
set STOP_WATCHDOG 1
reset_config srst_only srst_nogate connect_assert_srst

# Seelct the right chip
set CHIPNAME stm32f411RETx
set CONNECT_UNDER_RESET 1
source [find target/stm32f4x.cfg]

# Allow to continue execution after a connection:
init_reset run

#puts "Flash banks:"
#flash banks

#puts "Reading..."
#flash dump_image CPU2-RTE-dump.hex 0x00000000 0x8000

#puts "Done."
#exit