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view Documentations/dump-rte.cfg @ 277:580822b5d3d1 IPC_Sync_Improvment_3

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Rework SPI error handling. SPI_Start_single_TxRx_with_Master evaluated the incoming data for a condition to send device instead of life data. In case of invalid input data this may cause unintended transmission of device data => now lifedata is send if incoming data is expected to be invalid The SPI timeout monitoring was done at the beginning of the mode loop. A timeout may have been detected even if meanwhile valid data was received (this is evaluated at x20ms) => Moved the timeout monitoring after the handling of incoming data
author ideenmodellierer
date Sun, 28 Apr 2019 10:16:38 +0200
parents 01cc5959f199
children
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#! openocd -f
# Define the prob used:
source [find interface/stlink-v2.cfg]
set WORKAREASIZE 0x8000
transport select hla_swd

# Reset options
set ENABLE_LOW_POWER 1
set STOP_WATCHDOG 1
reset_config srst_only srst_nogate connect_assert_srst

# Seelct the right chip
set CHIPNAME stm32f411RETx
set CONNECT_UNDER_RESET 1
source [find target/stm32f4x.cfg]

# Allow to continue execution after a connection:
init_reset run

#puts "Flash banks:"
#flash banks

#puts "Reading..."
#flash dump_image CPU2-RTE-dump.hex 0x00000000 0x8000

#puts "Done."
#exit