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view Documentations/dump-rte.cfg @ 303:90e65971f15d cleanup-4
bugfix, cleanup: simplify stopwatch logic and fix fallout
The previous 2 commits (making the depth switch between surface
and diving consistent) increased the time difference (in the
simulator) to about 4 seconds. This commit fixes this again, and
we are back at 1 sec. difference between the 2 timers (notice:
in the simulator). Still not the wanted 0 sec. difference, but
the old stopwatch logic logic was rather convoluted. Resetting to
1 second (instead of 0), and second-1 logic. Basically, this feels
like a bug fixed with a second bug on top to mask it. The code
is now much more logic and consistent (despite the fact that the
real reason for the 1 sec. difference is not yet found).
Signed-off-by: Jan Mulder <jlmulder@xs4all.nl>
author | Jan Mulder <jlmulder@xs4all.nl> |
---|---|
date | Mon, 20 May 2019 12:57:31 +0200 |
parents | 01cc5959f199 |
children |
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#! openocd -f # Define the prob used: source [find interface/stlink-v2.cfg] set WORKAREASIZE 0x8000 transport select hla_swd # Reset options set ENABLE_LOW_POWER 1 set STOP_WATCHDOG 1 reset_config srst_only srst_nogate connect_assert_srst # Seelct the right chip set CHIPNAME stm32f411RETx set CONNECT_UNDER_RESET 1 source [find target/stm32f4x.cfg] # Allow to continue execution after a connection: init_reset run #puts "Flash banks:" #flash banks #puts "Reading..." #flash dump_image CPU2-RTE-dump.hex 0x00000000 0x8000 #puts "Done." #exit