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comparison Common/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc.c @ 160:e3ca52b8e7fa
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author | heinrichsweikamp |
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date | Thu, 07 Mar 2019 15:06:43 +0100 |
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1 /** | |
2 ****************************************************************************** | |
3 * @file stm32f4xx_hal_adc.c | |
4 * @author MCD Application Team | |
5 * @brief This file provides firmware functions to manage the following | |
6 * functionalities of the Analog to Digital Convertor (ADC) peripheral: | |
7 * + Initialization and de-initialization functions | |
8 * + IO operation functions | |
9 * + State and errors functions | |
10 * | |
11 @verbatim | |
12 ============================================================================== | |
13 ##### ADC Peripheral features ##### | |
14 ============================================================================== | |
15 [..] | |
16 (#) 12-bit, 10-bit, 8-bit or 6-bit configurable resolution. | |
17 (#) Interrupt generation at the end of conversion, end of injected conversion, | |
18 and in case of analog watchdog or overrun events | |
19 (#) Single and continuous conversion modes. | |
20 (#) Scan mode for automatic conversion of channel 0 to channel x. | |
21 (#) Data alignment with in-built data coherency. | |
22 (#) Channel-wise programmable sampling time. | |
23 (#) External trigger option with configurable polarity for both regular and | |
24 injected conversion. | |
25 (#) Dual/Triple mode (on devices with 2 ADCs or more). | |
26 (#) Configurable DMA data storage in Dual/Triple ADC mode. | |
27 (#) Configurable delay between conversions in Dual/Triple interleaved mode. | |
28 (#) ADC conversion type (refer to the datasheets). | |
29 (#) ADC supply requirements: 2.4 V to 3.6 V at full speed and down to 1.8 V at | |
30 slower speed. | |
31 (#) ADC input range: VREF(minus) = VIN = VREF(plus). | |
32 (#) DMA request generation during regular channel conversion. | |
33 | |
34 | |
35 ##### How to use this driver ##### | |
36 ============================================================================== | |
37 [..] | |
38 (#)Initialize the ADC low level resources by implementing the HAL_ADC_MspInit(): | |
39 (##) Enable the ADC interface clock using __HAL_RCC_ADC_CLK_ENABLE() | |
40 (##) ADC pins configuration | |
41 (+++) Enable the clock for the ADC GPIOs using the following function: | |
42 __HAL_RCC_GPIOx_CLK_ENABLE() | |
43 (+++) Configure these ADC pins in analog mode using HAL_GPIO_Init() | |
44 (##) In case of using interrupts (e.g. HAL_ADC_Start_IT()) | |
45 (+++) Configure the ADC interrupt priority using HAL_NVIC_SetPriority() | |
46 (+++) Enable the ADC IRQ handler using HAL_NVIC_EnableIRQ() | |
47 (+++) In ADC IRQ handler, call HAL_ADC_IRQHandler() | |
48 (##) In case of using DMA to control data transfer (e.g. HAL_ADC_Start_DMA()) | |
49 (+++) Enable the DMAx interface clock using __HAL_RCC_DMAx_CLK_ENABLE() | |
50 (+++) Configure and enable two DMA streams stream for managing data | |
51 transfer from peripheral to memory (output stream) | |
52 (+++) Associate the initialized DMA handle to the CRYP DMA handle | |
53 using __HAL_LINKDMA() | |
54 (+++) Configure the priority and enable the NVIC for the transfer complete | |
55 interrupt on the two DMA Streams. The output stream should have higher | |
56 priority than the input stream. | |
57 | |
58 *** Configuration of ADC, groups regular/injected, channels parameters *** | |
59 ============================================================================== | |
60 [..] | |
61 (#) Configure the ADC parameters (resolution, data alignment, ...) | |
62 and regular group parameters (conversion trigger, sequencer, ...) | |
63 using function HAL_ADC_Init(). | |
64 | |
65 (#) Configure the channels for regular group parameters (channel number, | |
66 channel rank into sequencer, ..., into regular group) | |
67 using function HAL_ADC_ConfigChannel(). | |
68 | |
69 (#) Optionally, configure the injected group parameters (conversion trigger, | |
70 sequencer, ..., of injected group) | |
71 and the channels for injected group parameters (channel number, | |
72 channel rank into sequencer, ..., into injected group) | |
73 using function HAL_ADCEx_InjectedConfigChannel(). | |
74 | |
75 (#) Optionally, configure the analog watchdog parameters (channels | |
76 monitored, thresholds, ...) using function HAL_ADC_AnalogWDGConfig(). | |
77 | |
78 (#) Optionally, for devices with several ADC instances: configure the | |
79 multimode parameters using function HAL_ADCEx_MultiModeConfigChannel(). | |
80 | |
81 *** Execution of ADC conversions *** | |
82 ============================================================================== | |
83 [..] | |
84 (#) ADC driver can be used among three modes: polling, interruption, | |
85 transfer by DMA. | |
86 | |
87 *** Polling mode IO operation *** | |
88 ================================= | |
89 [..] | |
90 (+) Start the ADC peripheral using HAL_ADC_Start() | |
91 (+) Wait for end of conversion using HAL_ADC_PollForConversion(), at this stage | |
92 user can specify the value of timeout according to his end application | |
93 (+) To read the ADC converted values, use the HAL_ADC_GetValue() function. | |
94 (+) Stop the ADC peripheral using HAL_ADC_Stop() | |
95 | |
96 *** Interrupt mode IO operation *** | |
97 =================================== | |
98 [..] | |
99 (+) Start the ADC peripheral using HAL_ADC_Start_IT() | |
100 (+) Use HAL_ADC_IRQHandler() called under ADC_IRQHandler() Interrupt subroutine | |
101 (+) At ADC end of conversion HAL_ADC_ConvCpltCallback() function is executed and user can | |
102 add his own code by customization of function pointer HAL_ADC_ConvCpltCallback | |
103 (+) In case of ADC Error, HAL_ADC_ErrorCallback() function is executed and user can | |
104 add his own code by customization of function pointer HAL_ADC_ErrorCallback | |
105 (+) Stop the ADC peripheral using HAL_ADC_Stop_IT() | |
106 | |
107 *** DMA mode IO operation *** | |
108 ============================== | |
109 [..] | |
110 (+) Start the ADC peripheral using HAL_ADC_Start_DMA(), at this stage the user specify the length | |
111 of data to be transferred at each end of conversion | |
112 (+) At The end of data transfer by HAL_ADC_ConvCpltCallback() function is executed and user can | |
113 add his own code by customization of function pointer HAL_ADC_ConvCpltCallback | |
114 (+) In case of transfer Error, HAL_ADC_ErrorCallback() function is executed and user can | |
115 add his own code by customization of function pointer HAL_ADC_ErrorCallback | |
116 (+) Stop the ADC peripheral using HAL_ADC_Stop_DMA() | |
117 | |
118 *** ADC HAL driver macros list *** | |
119 ============================================= | |
120 [..] | |
121 Below the list of most used macros in ADC HAL driver. | |
122 | |
123 (+) __HAL_ADC_ENABLE : Enable the ADC peripheral | |
124 (+) __HAL_ADC_DISABLE : Disable the ADC peripheral | |
125 (+) __HAL_ADC_ENABLE_IT: Enable the ADC end of conversion interrupt | |
126 (+) __HAL_ADC_DISABLE_IT: Disable the ADC end of conversion interrupt | |
127 (+) __HAL_ADC_GET_IT_SOURCE: Check if the specified ADC interrupt source is enabled or disabled | |
128 (+) __HAL_ADC_CLEAR_FLAG: Clear the ADC's pending flags | |
129 (+) __HAL_ADC_GET_FLAG: Get the selected ADC's flag status | |
130 (+) ADC_GET_RESOLUTION: Return resolution bits in CR1 register | |
131 | |
132 [..] | |
133 (@) You can refer to the ADC HAL driver header file for more useful macros | |
134 | |
135 *** Deinitialization of ADC *** | |
136 ============================================================================== | |
137 [..] | |
138 (#) Disable the ADC interface | |
139 (++) ADC clock can be hard reset and disabled at RCC top level. | |
140 (++) Hard reset of ADC peripherals | |
141 using macro __HAL_RCC_ADC_FORCE_RESET(), __HAL_RCC_ADC_RELEASE_RESET(). | |
142 (++) ADC clock disable using the equivalent macro/functions as configuration step. | |
143 (+++) Example: | |
144 Into HAL_ADC_MspDeInit() (recommended code location) or with | |
145 other device clock parameters configuration: | |
146 (+++) HAL_RCC_GetOscConfig(&RCC_OscInitStructure); | |
147 (+++) RCC_OscInitStructure.OscillatorType = RCC_OSCILLATORTYPE_HSI; | |
148 (+++) RCC_OscInitStructure.HSIState = RCC_HSI_OFF; (if not used for system clock) | |
149 (+++) HAL_RCC_OscConfig(&RCC_OscInitStructure); | |
150 | |
151 (#) ADC pins configuration | |
152 (++) Disable the clock for the ADC GPIOs using macro __HAL_RCC_GPIOx_CLK_DISABLE() | |
153 | |
154 (#) Optionally, in case of usage of ADC with interruptions: | |
155 (++) Disable the NVIC for ADC using function HAL_NVIC_DisableIRQ(ADCx_IRQn) | |
156 | |
157 (#) Optionally, in case of usage of DMA: | |
158 (++) Deinitialize the DMA using function HAL_DMA_DeInit(). | |
159 (++) Disable the NVIC for DMA using function HAL_NVIC_DisableIRQ(DMAx_Channelx_IRQn) | |
160 | |
161 @endverbatim | |
162 ****************************************************************************** | |
163 * @attention | |
164 * | |
165 * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2> | |
166 * | |
167 * Redistribution and use in source and binary forms, with or without modification, | |
168 * are permitted provided that the following conditions are met: | |
169 * 1. Redistributions of source code must retain the above copyright notice, | |
170 * this list of conditions and the following disclaimer. | |
171 * 2. Redistributions in binary form must reproduce the above copyright notice, | |
172 * this list of conditions and the following disclaimer in the documentation | |
173 * and/or other materials provided with the distribution. | |
174 * 3. Neither the name of STMicroelectronics nor the names of its contributors | |
175 * may be used to endorse or promote products derived from this software | |
176 * without specific prior written permission. | |
177 * | |
178 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" | |
179 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE | |
180 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE | |
181 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE | |
182 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL | |
183 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR | |
184 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER | |
185 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, | |
186 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE | |
187 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | |
188 * | |
189 ****************************************************************************** | |
190 */ | |
191 | |
192 /* Includes ------------------------------------------------------------------*/ | |
193 #include "stm32f4xx_hal.h" | |
194 | |
195 /** @addtogroup STM32F4xx_HAL_Driver | |
196 * @{ | |
197 */ | |
198 | |
199 /** @defgroup ADC ADC | |
200 * @brief ADC driver modules | |
201 * @{ | |
202 */ | |
203 | |
204 #ifdef HAL_ADC_MODULE_ENABLED | |
205 | |
206 /* Private typedef -----------------------------------------------------------*/ | |
207 /* Private define ------------------------------------------------------------*/ | |
208 /* Private macro -------------------------------------------------------------*/ | |
209 /* Private variables ---------------------------------------------------------*/ | |
210 /** @addtogroup ADC_Private_Functions | |
211 * @{ | |
212 */ | |
213 /* Private function prototypes -----------------------------------------------*/ | |
214 static void ADC_Init(ADC_HandleTypeDef* hadc); | |
215 static void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma); | |
216 static void ADC_DMAError(DMA_HandleTypeDef *hdma); | |
217 static void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma); | |
218 /** | |
219 * @} | |
220 */ | |
221 /* Exported functions --------------------------------------------------------*/ | |
222 /** @defgroup ADC_Exported_Functions ADC Exported Functions | |
223 * @{ | |
224 */ | |
225 | |
226 /** @defgroup ADC_Exported_Functions_Group1 Initialization and de-initialization functions | |
227 * @brief Initialization and Configuration functions | |
228 * | |
229 @verbatim | |
230 =============================================================================== | |
231 ##### Initialization and de-initialization functions ##### | |
232 =============================================================================== | |
233 [..] This section provides functions allowing to: | |
234 (+) Initialize and configure the ADC. | |
235 (+) De-initialize the ADC. | |
236 | |
237 @endverbatim | |
238 * @{ | |
239 */ | |
240 | |
241 /** | |
242 * @brief Initializes the ADCx peripheral according to the specified parameters | |
243 * in the ADC_InitStruct and initializes the ADC MSP. | |
244 * | |
245 * @note This function is used to configure the global features of the ADC ( | |
246 * ClockPrescaler, Resolution, Data Alignment and number of conversion), however, | |
247 * the rest of the configuration parameters are specific to the regular | |
248 * channels group (scan mode activation, continuous mode activation, | |
249 * External trigger source and edge, DMA continuous request after the | |
250 * last transfer and End of conversion selection). | |
251 * | |
252 * @param hadc pointer to a ADC_HandleTypeDef structure that contains | |
253 * the configuration information for the specified ADC. | |
254 * @retval HAL status | |
255 */ | |
256 HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc) | |
257 { | |
258 HAL_StatusTypeDef tmp_hal_status = HAL_OK; | |
259 | |
260 /* Check ADC handle */ | |
261 if(hadc == NULL) | |
262 { | |
263 return HAL_ERROR; | |
264 } | |
265 | |
266 /* Check the parameters */ | |
267 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); | |
268 assert_param(IS_ADC_CLOCKPRESCALER(hadc->Init.ClockPrescaler)); | |
269 assert_param(IS_ADC_RESOLUTION(hadc->Init.Resolution)); | |
270 assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ScanConvMode)); | |
271 assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode)); | |
272 assert_param(IS_ADC_EXT_TRIG(hadc->Init.ExternalTrigConv)); | |
273 assert_param(IS_ADC_DATA_ALIGN(hadc->Init.DataAlign)); | |
274 assert_param(IS_ADC_REGULAR_LENGTH(hadc->Init.NbrOfConversion)); | |
275 assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DMAContinuousRequests)); | |
276 assert_param(IS_ADC_EOCSelection(hadc->Init.EOCSelection)); | |
277 assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DiscontinuousConvMode)); | |
278 | |
279 if(hadc->Init.ExternalTrigConv != ADC_SOFTWARE_START) | |
280 { | |
281 assert_param(IS_ADC_EXT_TRIG_EDGE(hadc->Init.ExternalTrigConvEdge)); | |
282 } | |
283 | |
284 if(hadc->State == HAL_ADC_STATE_RESET) | |
285 { | |
286 /* Initialize ADC error code */ | |
287 ADC_CLEAR_ERRORCODE(hadc); | |
288 | |
289 /* Allocate lock resource and initialize it */ | |
290 hadc->Lock = HAL_UNLOCKED; | |
291 | |
292 /* Init the low level hardware */ | |
293 HAL_ADC_MspInit(hadc); | |
294 } | |
295 | |
296 /* Configuration of ADC parameters if previous preliminary actions are */ | |
297 /* correctly completed. */ | |
298 if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL)) | |
299 { | |
300 /* Set ADC state */ | |
301 ADC_STATE_CLR_SET(hadc->State, | |
302 HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY, | |
303 HAL_ADC_STATE_BUSY_INTERNAL); | |
304 | |
305 /* Set ADC parameters */ | |
306 ADC_Init(hadc); | |
307 | |
308 /* Set ADC error code to none */ | |
309 ADC_CLEAR_ERRORCODE(hadc); | |
310 | |
311 /* Set the ADC state */ | |
312 ADC_STATE_CLR_SET(hadc->State, | |
313 HAL_ADC_STATE_BUSY_INTERNAL, | |
314 HAL_ADC_STATE_READY); | |
315 } | |
316 else | |
317 { | |
318 tmp_hal_status = HAL_ERROR; | |
319 } | |
320 | |
321 /* Release Lock */ | |
322 __HAL_UNLOCK(hadc); | |
323 | |
324 /* Return function status */ | |
325 return tmp_hal_status; | |
326 } | |
327 | |
328 /** | |
329 * @brief Deinitializes the ADCx peripheral registers to their default reset values. | |
330 * @param hadc pointer to a ADC_HandleTypeDef structure that contains | |
331 * the configuration information for the specified ADC. | |
332 * @retval HAL status | |
333 */ | |
334 HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef* hadc) | |
335 { | |
336 HAL_StatusTypeDef tmp_hal_status = HAL_OK; | |
337 | |
338 /* Check ADC handle */ | |
339 if(hadc == NULL) | |
340 { | |
341 return HAL_ERROR; | |
342 } | |
343 | |
344 /* Check the parameters */ | |
345 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); | |
346 | |
347 /* Set ADC state */ | |
348 SET_BIT(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL); | |
349 | |
350 /* Stop potential conversion on going, on regular and injected groups */ | |
351 /* Disable ADC peripheral */ | |
352 __HAL_ADC_DISABLE(hadc); | |
353 | |
354 /* Configuration of ADC parameters if previous preliminary actions are */ | |
355 /* correctly completed. */ | |
356 if(HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_ADON)) | |
357 { | |
358 /* DeInit the low level hardware */ | |
359 HAL_ADC_MspDeInit(hadc); | |
360 | |
361 /* Set ADC error code to none */ | |
362 ADC_CLEAR_ERRORCODE(hadc); | |
363 | |
364 /* Set ADC state */ | |
365 hadc->State = HAL_ADC_STATE_RESET; | |
366 } | |
367 | |
368 /* Process unlocked */ | |
369 __HAL_UNLOCK(hadc); | |
370 | |
371 /* Return function status */ | |
372 return tmp_hal_status; | |
373 } | |
374 | |
375 /** | |
376 * @brief Initializes the ADC MSP. | |
377 * @param hadc pointer to a ADC_HandleTypeDef structure that contains | |
378 * the configuration information for the specified ADC. | |
379 * @retval None | |
380 */ | |
381 __weak void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc) | |
382 { | |
383 /* Prevent unused argument(s) compilation warning */ | |
384 UNUSED(hadc); | |
385 /* NOTE : This function Should not be modified, when the callback is needed, | |
386 the HAL_ADC_MspInit could be implemented in the user file | |
387 */ | |
388 } | |
389 | |
390 /** | |
391 * @brief DeInitializes the ADC MSP. | |
392 * @param hadc pointer to a ADC_HandleTypeDef structure that contains | |
393 * the configuration information for the specified ADC. | |
394 * @retval None | |
395 */ | |
396 __weak void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc) | |
397 { | |
398 /* Prevent unused argument(s) compilation warning */ | |
399 UNUSED(hadc); | |
400 /* NOTE : This function Should not be modified, when the callback is needed, | |
401 the HAL_ADC_MspDeInit could be implemented in the user file | |
402 */ | |
403 } | |
404 | |
405 /** | |
406 * @} | |
407 */ | |
408 | |
409 /** @defgroup ADC_Exported_Functions_Group2 IO operation functions | |
410 * @brief IO operation functions | |
411 * | |
412 @verbatim | |
413 =============================================================================== | |
414 ##### IO operation functions ##### | |
415 =============================================================================== | |
416 [..] This section provides functions allowing to: | |
417 (+) Start conversion of regular channel. | |
418 (+) Stop conversion of regular channel. | |
419 (+) Start conversion of regular channel and enable interrupt. | |
420 (+) Stop conversion of regular channel and disable interrupt. | |
421 (+) Start conversion of regular channel and enable DMA transfer. | |
422 (+) Stop conversion of regular channel and disable DMA transfer. | |
423 (+) Handle ADC interrupt request. | |
424 | |
425 @endverbatim | |
426 * @{ | |
427 */ | |
428 | |
429 /** | |
430 * @brief Enables ADC and starts conversion of the regular channels. | |
431 * @param hadc pointer to a ADC_HandleTypeDef structure that contains | |
432 * the configuration information for the specified ADC. | |
433 * @retval HAL status | |
434 */ | |
435 HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc) | |
436 { | |
437 __IO uint32_t counter = 0U; | |
438 ADC_Common_TypeDef *tmpADC_Common; | |
439 | |
440 /* Check the parameters */ | |
441 assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode)); | |
442 assert_param(IS_ADC_EXT_TRIG_EDGE(hadc->Init.ExternalTrigConvEdge)); | |
443 | |
444 /* Process locked */ | |
445 __HAL_LOCK(hadc); | |
446 | |
447 /* Enable the ADC peripheral */ | |
448 /* Check if ADC peripheral is disabled in order to enable it and wait during | |
449 Tstab time the ADC's stabilization */ | |
450 if((hadc->Instance->CR2 & ADC_CR2_ADON) != ADC_CR2_ADON) | |
451 { | |
452 /* Enable the Peripheral */ | |
453 __HAL_ADC_ENABLE(hadc); | |
454 | |
455 /* Delay for ADC stabilization time */ | |
456 /* Compute number of CPU cycles to wait for */ | |
457 counter = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000U)); | |
458 while(counter != 0U) | |
459 { | |
460 counter--; | |
461 } | |
462 } | |
463 | |
464 /* Start conversion if ADC is effectively enabled */ | |
465 if(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_ADON)) | |
466 { | |
467 /* Set ADC state */ | |
468 /* - Clear state bitfield related to regular group conversion results */ | |
469 /* - Set state bitfield related to regular group operation */ | |
470 ADC_STATE_CLR_SET(hadc->State, | |
471 HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR, | |
472 HAL_ADC_STATE_REG_BUSY); | |
473 | |
474 /* If conversions on group regular are also triggering group injected, */ | |
475 /* update ADC state. */ | |
476 if (READ_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO) != RESET) | |
477 { | |
478 ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY); | |
479 } | |
480 | |
481 /* State machine update: Check if an injected conversion is ongoing */ | |
482 if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY)) | |
483 { | |
484 /* Reset ADC error code fields related to conversions on group regular */ | |
485 CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA)); | |
486 } | |
487 else | |
488 { | |
489 /* Reset ADC all error code fields */ | |
490 ADC_CLEAR_ERRORCODE(hadc); | |
491 } | |
492 | |
493 /* Process unlocked */ | |
494 /* Unlock before starting ADC conversions: in case of potential */ | |
495 /* interruption, to let the process to ADC IRQ Handler. */ | |
496 __HAL_UNLOCK(hadc); | |
497 | |
498 /* Pointer to the common control register to which is belonging hadc */ | |
499 /* (Depending on STM32F4 product, there may be up to 3 ADCs and 1 common */ | |
500 /* control register) */ | |
501 tmpADC_Common = ADC_COMMON_REGISTER(hadc); | |
502 | |
503 /* Clear regular group conversion flag and overrun flag */ | |
504 /* (To ensure of no unknown state from potential previous ADC operations) */ | |
505 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC | ADC_FLAG_OVR); | |
506 | |
507 /* Check if Multimode enabled */ | |
508 if(HAL_IS_BIT_CLR(tmpADC_Common->CCR, ADC_CCR_MULTI)) | |
509 { | |
510 /* if no external trigger present enable software conversion of regular channels */ | |
511 if((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET) | |
512 { | |
513 /* Enable the selected ADC software conversion for regular group */ | |
514 hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART; | |
515 } | |
516 } | |
517 else | |
518 { | |
519 /* if instance of handle correspond to ADC1 and no external trigger present enable software conversion of regular channels */ | |
520 if((hadc->Instance == ADC1) && ((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET)) | |
521 { | |
522 /* Enable the selected ADC software conversion for regular group */ | |
523 hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART; | |
524 } | |
525 } | |
526 } | |
527 | |
528 /* Return function status */ | |
529 return HAL_OK; | |
530 } | |
531 | |
532 /** | |
533 * @brief Disables ADC and stop conversion of regular channels. | |
534 * | |
535 * @note Caution: This function will stop also injected channels. | |
536 * | |
537 * @param hadc pointer to a ADC_HandleTypeDef structure that contains | |
538 * the configuration information for the specified ADC. | |
539 * | |
540 * @retval HAL status. | |
541 */ | |
542 HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc) | |
543 { | |
544 /* Check the parameters */ | |
545 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); | |
546 | |
547 /* Process locked */ | |
548 __HAL_LOCK(hadc); | |
549 | |
550 /* Stop potential conversion on going, on regular and injected groups */ | |
551 /* Disable ADC peripheral */ | |
552 __HAL_ADC_DISABLE(hadc); | |
553 | |
554 /* Check if ADC is effectively disabled */ | |
555 if(HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_ADON)) | |
556 { | |
557 /* Set ADC state */ | |
558 ADC_STATE_CLR_SET(hadc->State, | |
559 HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY, | |
560 HAL_ADC_STATE_READY); | |
561 } | |
562 | |
563 /* Process unlocked */ | |
564 __HAL_UNLOCK(hadc); | |
565 | |
566 /* Return function status */ | |
567 return HAL_OK; | |
568 } | |
569 | |
570 /** | |
571 * @brief Poll for regular conversion complete | |
572 * @note ADC conversion flags EOS (end of sequence) and EOC (end of | |
573 * conversion) are cleared by this function. | |
574 * @note This function cannot be used in a particular setup: ADC configured | |
575 * in DMA mode and polling for end of each conversion (ADC init | |
576 * parameter "EOCSelection" set to ADC_EOC_SINGLE_CONV). | |
577 * In this case, DMA resets the flag EOC and polling cannot be | |
578 * performed on each conversion. Nevertheless, polling can still | |
579 * be performed on the complete sequence. | |
580 * @param hadc pointer to a ADC_HandleTypeDef structure that contains | |
581 * the configuration information for the specified ADC. | |
582 * @param Timeout Timeout value in millisecond. | |
583 * @retval HAL status | |
584 */ | |
585 HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout) | |
586 { | |
587 uint32_t tickstart = 0U; | |
588 | |
589 /* Verification that ADC configuration is compliant with polling for */ | |
590 /* each conversion: */ | |
591 /* Particular case is ADC configured in DMA mode and ADC sequencer with */ | |
592 /* several ranks and polling for end of each conversion. */ | |
593 /* For code simplicity sake, this particular case is generalized to */ | |
594 /* ADC configured in DMA mode and polling for end of each conversion. */ | |
595 if (HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_EOCS) && | |
596 HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_DMA) ) | |
597 { | |
598 /* Update ADC state machine to error */ | |
599 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); | |
600 | |
601 /* Process unlocked */ | |
602 __HAL_UNLOCK(hadc); | |
603 | |
604 return HAL_ERROR; | |
605 } | |
606 | |
607 /* Get tick */ | |
608 tickstart = HAL_GetTick(); | |
609 | |
610 /* Check End of conversion flag */ | |
611 while(!(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOC))) | |
612 { | |
613 /* Check if timeout is disabled (set to infinite wait) */ | |
614 if(Timeout != HAL_MAX_DELAY) | |
615 { | |
616 if((Timeout == 0U) || ((HAL_GetTick() - tickstart ) > Timeout)) | |
617 { | |
618 /* Update ADC state machine to timeout */ | |
619 SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT); | |
620 | |
621 /* Process unlocked */ | |
622 __HAL_UNLOCK(hadc); | |
623 | |
624 return HAL_TIMEOUT; | |
625 } | |
626 } | |
627 } | |
628 | |
629 /* Clear regular group conversion flag */ | |
630 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_STRT | ADC_FLAG_EOC); | |
631 | |
632 /* Update ADC state machine */ | |
633 SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC); | |
634 | |
635 /* Determine whether any further conversion upcoming on group regular */ | |
636 /* by external trigger, continuous mode or scan sequence on going. */ | |
637 /* Note: On STM32F4, there is no independent flag of end of sequence. */ | |
638 /* The test of scan sequence on going is done either with scan */ | |
639 /* sequence disabled or with end of conversion flag set to */ | |
640 /* of end of sequence. */ | |
641 if(ADC_IS_SOFTWARE_START_REGULAR(hadc) && | |
642 (hadc->Init.ContinuousConvMode == DISABLE) && | |
643 (HAL_IS_BIT_CLR(hadc->Instance->SQR1, ADC_SQR1_L) || | |
644 HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_EOCS) ) ) | |
645 { | |
646 /* Set ADC state */ | |
647 CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY); | |
648 | |
649 if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY)) | |
650 { | |
651 SET_BIT(hadc->State, HAL_ADC_STATE_READY); | |
652 } | |
653 } | |
654 | |
655 /* Return ADC state */ | |
656 return HAL_OK; | |
657 } | |
658 | |
659 /** | |
660 * @brief Poll for conversion event | |
661 * @param hadc pointer to a ADC_HandleTypeDef structure that contains | |
662 * the configuration information for the specified ADC. | |
663 * @param EventType the ADC event type. | |
664 * This parameter can be one of the following values: | |
665 * @arg ADC_AWD_EVENT: ADC Analog watch Dog event. | |
666 * @arg ADC_OVR_EVENT: ADC Overrun event. | |
667 * @param Timeout Timeout value in millisecond. | |
668 * @retval HAL status | |
669 */ | |
670 HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventType, uint32_t Timeout) | |
671 { | |
672 uint32_t tickstart = 0U; | |
673 | |
674 /* Check the parameters */ | |
675 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); | |
676 assert_param(IS_ADC_EVENT_TYPE(EventType)); | |
677 | |
678 /* Get tick */ | |
679 tickstart = HAL_GetTick(); | |
680 | |
681 /* Check selected event flag */ | |
682 while(!(__HAL_ADC_GET_FLAG(hadc,EventType))) | |
683 { | |
684 /* Check for the Timeout */ | |
685 if(Timeout != HAL_MAX_DELAY) | |
686 { | |
687 if((Timeout == 0U) || ((HAL_GetTick() - tickstart ) > Timeout)) | |
688 { | |
689 /* Update ADC state machine to timeout */ | |
690 SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT); | |
691 | |
692 /* Process unlocked */ | |
693 __HAL_UNLOCK(hadc); | |
694 | |
695 return HAL_TIMEOUT; | |
696 } | |
697 } | |
698 } | |
699 | |
700 /* Analog watchdog (level out of window) event */ | |
701 if(EventType == ADC_AWD_EVENT) | |
702 { | |
703 /* Set ADC state */ | |
704 SET_BIT(hadc->State, HAL_ADC_STATE_AWD1); | |
705 | |
706 /* Clear ADC analog watchdog flag */ | |
707 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD); | |
708 } | |
709 /* Overrun event */ | |
710 else | |
711 { | |
712 /* Set ADC state */ | |
713 SET_BIT(hadc->State, HAL_ADC_STATE_REG_OVR); | |
714 /* Set ADC error code to overrun */ | |
715 SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_OVR); | |
716 | |
717 /* Clear ADC overrun flag */ | |
718 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR); | |
719 } | |
720 | |
721 /* Return ADC state */ | |
722 return HAL_OK; | |
723 } | |
724 | |
725 | |
726 /** | |
727 * @brief Enables the interrupt and starts ADC conversion of regular channels. | |
728 * @param hadc pointer to a ADC_HandleTypeDef structure that contains | |
729 * the configuration information for the specified ADC. | |
730 * @retval HAL status. | |
731 */ | |
732 HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc) | |
733 { | |
734 __IO uint32_t counter = 0U; | |
735 ADC_Common_TypeDef *tmpADC_Common; | |
736 | |
737 /* Check the parameters */ | |
738 assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode)); | |
739 assert_param(IS_ADC_EXT_TRIG_EDGE(hadc->Init.ExternalTrigConvEdge)); | |
740 | |
741 /* Process locked */ | |
742 __HAL_LOCK(hadc); | |
743 | |
744 /* Enable the ADC peripheral */ | |
745 /* Check if ADC peripheral is disabled in order to enable it and wait during | |
746 Tstab time the ADC's stabilization */ | |
747 if((hadc->Instance->CR2 & ADC_CR2_ADON) != ADC_CR2_ADON) | |
748 { | |
749 /* Enable the Peripheral */ | |
750 __HAL_ADC_ENABLE(hadc); | |
751 | |
752 /* Delay for ADC stabilization time */ | |
753 /* Compute number of CPU cycles to wait for */ | |
754 counter = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000U)); | |
755 while(counter != 0U) | |
756 { | |
757 counter--; | |
758 } | |
759 } | |
760 | |
761 /* Start conversion if ADC is effectively enabled */ | |
762 if(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_ADON)) | |
763 { | |
764 /* Set ADC state */ | |
765 /* - Clear state bitfield related to regular group conversion results */ | |
766 /* - Set state bitfield related to regular group operation */ | |
767 ADC_STATE_CLR_SET(hadc->State, | |
768 HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR, | |
769 HAL_ADC_STATE_REG_BUSY); | |
770 | |
771 /* If conversions on group regular are also triggering group injected, */ | |
772 /* update ADC state. */ | |
773 if (READ_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO) != RESET) | |
774 { | |
775 ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY); | |
776 } | |
777 | |
778 /* State machine update: Check if an injected conversion is ongoing */ | |
779 if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY)) | |
780 { | |
781 /* Reset ADC error code fields related to conversions on group regular */ | |
782 CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA)); | |
783 } | |
784 else | |
785 { | |
786 /* Reset ADC all error code fields */ | |
787 ADC_CLEAR_ERRORCODE(hadc); | |
788 } | |
789 | |
790 /* Process unlocked */ | |
791 /* Unlock before starting ADC conversions: in case of potential */ | |
792 /* interruption, to let the process to ADC IRQ Handler. */ | |
793 __HAL_UNLOCK(hadc); | |
794 | |
795 /* Pointer to the common control register to which is belonging hadc */ | |
796 /* (Depending on STM32F4 product, there may be up to 3 ADCs and 1 common */ | |
797 /* control register) */ | |
798 tmpADC_Common = ADC_COMMON_REGISTER(hadc); | |
799 | |
800 /* Clear regular group conversion flag and overrun flag */ | |
801 /* (To ensure of no unknown state from potential previous ADC operations) */ | |
802 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC | ADC_FLAG_OVR); | |
803 | |
804 /* Enable end of conversion interrupt for regular group */ | |
805 __HAL_ADC_ENABLE_IT(hadc, (ADC_IT_EOC | ADC_IT_OVR)); | |
806 | |
807 /* Check if Multimode enabled */ | |
808 if(HAL_IS_BIT_CLR(tmpADC_Common->CCR, ADC_CCR_MULTI)) | |
809 { | |
810 /* if no external trigger present enable software conversion of regular channels */ | |
811 if((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET) | |
812 { | |
813 /* Enable the selected ADC software conversion for regular group */ | |
814 hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART; | |
815 } | |
816 } | |
817 else | |
818 { | |
819 /* if instance of handle correspond to ADC1 and no external trigger present enable software conversion of regular channels */ | |
820 if((hadc->Instance == ADC1) && ((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET)) | |
821 { | |
822 /* Enable the selected ADC software conversion for regular group */ | |
823 hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART; | |
824 } | |
825 } | |
826 } | |
827 | |
828 /* Return function status */ | |
829 return HAL_OK; | |
830 } | |
831 | |
832 /** | |
833 * @brief Disables the interrupt and stop ADC conversion of regular channels. | |
834 * | |
835 * @note Caution: This function will stop also injected channels. | |
836 * | |
837 * @param hadc pointer to a ADC_HandleTypeDef structure that contains | |
838 * the configuration information for the specified ADC. | |
839 * @retval HAL status. | |
840 */ | |
841 HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc) | |
842 { | |
843 /* Check the parameters */ | |
844 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); | |
845 | |
846 /* Process locked */ | |
847 __HAL_LOCK(hadc); | |
848 | |
849 /* Stop potential conversion on going, on regular and injected groups */ | |
850 /* Disable ADC peripheral */ | |
851 __HAL_ADC_DISABLE(hadc); | |
852 | |
853 /* Check if ADC is effectively disabled */ | |
854 if(HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_ADON)) | |
855 { | |
856 /* Disable ADC end of conversion interrupt for regular group */ | |
857 __HAL_ADC_DISABLE_IT(hadc, (ADC_IT_EOC | ADC_IT_OVR)); | |
858 | |
859 /* Set ADC state */ | |
860 ADC_STATE_CLR_SET(hadc->State, | |
861 HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY, | |
862 HAL_ADC_STATE_READY); | |
863 } | |
864 | |
865 /* Process unlocked */ | |
866 __HAL_UNLOCK(hadc); | |
867 | |
868 /* Return function status */ | |
869 return HAL_OK; | |
870 } | |
871 | |
872 /** | |
873 * @brief Handles ADC interrupt request | |
874 * @param hadc pointer to a ADC_HandleTypeDef structure that contains | |
875 * the configuration information for the specified ADC. | |
876 * @retval None | |
877 */ | |
878 void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc) | |
879 { | |
880 uint32_t tmp1 = 0U, tmp2 = 0U; | |
881 | |
882 /* Check the parameters */ | |
883 assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode)); | |
884 assert_param(IS_ADC_REGULAR_LENGTH(hadc->Init.NbrOfConversion)); | |
885 assert_param(IS_ADC_EOCSelection(hadc->Init.EOCSelection)); | |
886 | |
887 tmp1 = __HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOC); | |
888 tmp2 = __HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_EOC); | |
889 /* Check End of conversion flag for regular channels */ | |
890 if(tmp1 && tmp2) | |
891 { | |
892 /* Update state machine on conversion status if not in error state */ | |
893 if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL)) | |
894 { | |
895 /* Set ADC state */ | |
896 SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC); | |
897 } | |
898 | |
899 /* Determine whether any further conversion upcoming on group regular */ | |
900 /* by external trigger, continuous mode or scan sequence on going. */ | |
901 /* Note: On STM32F4, there is no independent flag of end of sequence. */ | |
902 /* The test of scan sequence on going is done either with scan */ | |
903 /* sequence disabled or with end of conversion flag set to */ | |
904 /* of end of sequence. */ | |
905 if(ADC_IS_SOFTWARE_START_REGULAR(hadc) && | |
906 (hadc->Init.ContinuousConvMode == DISABLE) && | |
907 (HAL_IS_BIT_CLR(hadc->Instance->SQR1, ADC_SQR1_L) || | |
908 HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_EOCS) ) ) | |
909 { | |
910 /* Disable ADC end of single conversion interrupt on group regular */ | |
911 /* Note: Overrun interrupt was enabled with EOC interrupt in */ | |
912 /* HAL_ADC_Start_IT(), but is not disabled here because can be used */ | |
913 /* by overrun IRQ process below. */ | |
914 __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC); | |
915 | |
916 /* Set ADC state */ | |
917 CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY); | |
918 | |
919 if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY)) | |
920 { | |
921 SET_BIT(hadc->State, HAL_ADC_STATE_READY); | |
922 } | |
923 } | |
924 | |
925 /* Conversion complete callback */ | |
926 HAL_ADC_ConvCpltCallback(hadc); | |
927 | |
928 /* Clear regular group conversion flag */ | |
929 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_STRT | ADC_FLAG_EOC); | |
930 } | |
931 | |
932 tmp1 = __HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOC); | |
933 tmp2 = __HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_JEOC); | |
934 /* Check End of conversion flag for injected channels */ | |
935 if(tmp1 && tmp2) | |
936 { | |
937 /* Update state machine on conversion status if not in error state */ | |
938 if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL)) | |
939 { | |
940 /* Set ADC state */ | |
941 SET_BIT(hadc->State, HAL_ADC_STATE_INJ_EOC); | |
942 } | |
943 | |
944 /* Determine whether any further conversion upcoming on group injected */ | |
945 /* by external trigger, scan sequence on going or by automatic injected */ | |
946 /* conversion from group regular (same conditions as group regular */ | |
947 /* interruption disabling above). */ | |
948 if(ADC_IS_SOFTWARE_START_INJECTED(hadc) && | |
949 (HAL_IS_BIT_CLR(hadc->Instance->JSQR, ADC_JSQR_JL) || | |
950 HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_EOCS) ) && | |
951 (HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO) && | |
952 (ADC_IS_SOFTWARE_START_REGULAR(hadc) && | |
953 (hadc->Init.ContinuousConvMode == DISABLE) ) ) ) | |
954 { | |
955 /* Disable ADC end of single conversion interrupt on group injected */ | |
956 __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC); | |
957 | |
958 /* Set ADC state */ | |
959 CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY); | |
960 | |
961 if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_REG_BUSY)) | |
962 { | |
963 SET_BIT(hadc->State, HAL_ADC_STATE_READY); | |
964 } | |
965 } | |
966 | |
967 /* Conversion complete callback */ | |
968 HAL_ADCEx_InjectedConvCpltCallback(hadc); | |
969 | |
970 /* Clear injected group conversion flag */ | |
971 __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_JSTRT | ADC_FLAG_JEOC)); | |
972 } | |
973 | |
974 tmp1 = __HAL_ADC_GET_FLAG(hadc, ADC_FLAG_AWD); | |
975 tmp2 = __HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_AWD); | |
976 /* Check Analog watchdog flag */ | |
977 if(tmp1 && tmp2) | |
978 { | |
979 if(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_AWD)) | |
980 { | |
981 /* Set ADC state */ | |
982 SET_BIT(hadc->State, HAL_ADC_STATE_AWD1); | |
983 | |
984 /* Level out of window callback */ | |
985 HAL_ADC_LevelOutOfWindowCallback(hadc); | |
986 | |
987 /* Clear the ADC analog watchdog flag */ | |
988 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD); | |
989 } | |
990 } | |
991 | |
992 tmp1 = __HAL_ADC_GET_FLAG(hadc, ADC_FLAG_OVR); | |
993 tmp2 = __HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_OVR); | |
994 /* Check Overrun flag */ | |
995 if(tmp1 && tmp2) | |
996 { | |
997 /* Note: On STM32F4, ADC overrun can be set through other parameters */ | |
998 /* refer to description of parameter "EOCSelection" for more */ | |
999 /* details. */ | |
1000 | |
1001 /* Set ADC error code to overrun */ | |
1002 SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_OVR); | |
1003 | |
1004 /* Clear ADC overrun flag */ | |
1005 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR); | |
1006 | |
1007 /* Error callback */ | |
1008 HAL_ADC_ErrorCallback(hadc); | |
1009 | |
1010 /* Clear the Overrun flag */ | |
1011 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR); | |
1012 } | |
1013 } | |
1014 | |
1015 /** | |
1016 * @brief Enables ADC DMA request after last transfer (Single-ADC mode) and enables ADC peripheral | |
1017 * @param hadc pointer to a ADC_HandleTypeDef structure that contains | |
1018 * the configuration information for the specified ADC. | |
1019 * @param pData The destination Buffer address. | |
1020 * @param Length The length of data to be transferred from ADC peripheral to memory. | |
1021 * @retval HAL status | |
1022 */ | |
1023 HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length) | |
1024 { | |
1025 __IO uint32_t counter = 0U; | |
1026 ADC_Common_TypeDef *tmpADC_Common; | |
1027 | |
1028 /* Check the parameters */ | |
1029 assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode)); | |
1030 assert_param(IS_ADC_EXT_TRIG_EDGE(hadc->Init.ExternalTrigConvEdge)); | |
1031 | |
1032 /* Process locked */ | |
1033 __HAL_LOCK(hadc); | |
1034 | |
1035 /* Enable the ADC peripheral */ | |
1036 /* Check if ADC peripheral is disabled in order to enable it and wait during | |
1037 Tstab time the ADC's stabilization */ | |
1038 if((hadc->Instance->CR2 & ADC_CR2_ADON) != ADC_CR2_ADON) | |
1039 { | |
1040 /* Enable the Peripheral */ | |
1041 __HAL_ADC_ENABLE(hadc); | |
1042 | |
1043 /* Delay for ADC stabilization time */ | |
1044 /* Compute number of CPU cycles to wait for */ | |
1045 counter = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000U)); | |
1046 while(counter != 0U) | |
1047 { | |
1048 counter--; | |
1049 } | |
1050 } | |
1051 | |
1052 /* Start conversion if ADC is effectively enabled */ | |
1053 if(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_ADON)) | |
1054 { | |
1055 /* Set ADC state */ | |
1056 /* - Clear state bitfield related to regular group conversion results */ | |
1057 /* - Set state bitfield related to regular group operation */ | |
1058 ADC_STATE_CLR_SET(hadc->State, | |
1059 HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR, | |
1060 HAL_ADC_STATE_REG_BUSY); | |
1061 | |
1062 /* If conversions on group regular are also triggering group injected, */ | |
1063 /* update ADC state. */ | |
1064 if (READ_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO) != RESET) | |
1065 { | |
1066 ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY); | |
1067 } | |
1068 | |
1069 /* State machine update: Check if an injected conversion is ongoing */ | |
1070 if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY)) | |
1071 { | |
1072 /* Reset ADC error code fields related to conversions on group regular */ | |
1073 CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA)); | |
1074 } | |
1075 else | |
1076 { | |
1077 /* Reset ADC all error code fields */ | |
1078 ADC_CLEAR_ERRORCODE(hadc); | |
1079 } | |
1080 | |
1081 /* Process unlocked */ | |
1082 /* Unlock before starting ADC conversions: in case of potential */ | |
1083 /* interruption, to let the process to ADC IRQ Handler. */ | |
1084 __HAL_UNLOCK(hadc); | |
1085 | |
1086 /* Pointer to the common control register to which is belonging hadc */ | |
1087 /* (Depending on STM32F4 product, there may be up to 3 ADCs and 1 common */ | |
1088 /* control register) */ | |
1089 tmpADC_Common = ADC_COMMON_REGISTER(hadc); | |
1090 | |
1091 /* Set the DMA transfer complete callback */ | |
1092 hadc->DMA_Handle->XferCpltCallback = ADC_DMAConvCplt; | |
1093 | |
1094 /* Set the DMA half transfer complete callback */ | |
1095 hadc->DMA_Handle->XferHalfCpltCallback = ADC_DMAHalfConvCplt; | |
1096 | |
1097 /* Set the DMA error callback */ | |
1098 hadc->DMA_Handle->XferErrorCallback = ADC_DMAError; | |
1099 | |
1100 | |
1101 /* Manage ADC and DMA start: ADC overrun interruption, DMA start, ADC */ | |
1102 /* start (in case of SW start): */ | |
1103 | |
1104 /* Clear regular group conversion flag and overrun flag */ | |
1105 /* (To ensure of no unknown state from potential previous ADC operations) */ | |
1106 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC | ADC_FLAG_OVR); | |
1107 | |
1108 /* Enable ADC overrun interrupt */ | |
1109 __HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR); | |
1110 | |
1111 /* Enable ADC DMA mode */ | |
1112 hadc->Instance->CR2 |= ADC_CR2_DMA; | |
1113 | |
1114 /* Start the DMA channel */ | |
1115 HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&hadc->Instance->DR, (uint32_t)pData, Length); | |
1116 | |
1117 /* Check if Multimode enabled */ | |
1118 if(HAL_IS_BIT_CLR(tmpADC_Common->CCR, ADC_CCR_MULTI)) | |
1119 { | |
1120 /* if no external trigger present enable software conversion of regular channels */ | |
1121 if((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET) | |
1122 { | |
1123 /* Enable the selected ADC software conversion for regular group */ | |
1124 hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART; | |
1125 } | |
1126 } | |
1127 else | |
1128 { | |
1129 /* if instance of handle correspond to ADC1 and no external trigger present enable software conversion of regular channels */ | |
1130 if((hadc->Instance == ADC1) && ((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET)) | |
1131 { | |
1132 /* Enable the selected ADC software conversion for regular group */ | |
1133 hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART; | |
1134 } | |
1135 } | |
1136 } | |
1137 | |
1138 /* Return function status */ | |
1139 return HAL_OK; | |
1140 } | |
1141 | |
1142 /** | |
1143 * @brief Disables ADC DMA (Single-ADC mode) and disables ADC peripheral | |
1144 * @param hadc pointer to a ADC_HandleTypeDef structure that contains | |
1145 * the configuration information for the specified ADC. | |
1146 * @retval HAL status | |
1147 */ | |
1148 HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc) | |
1149 { | |
1150 HAL_StatusTypeDef tmp_hal_status = HAL_OK; | |
1151 | |
1152 /* Check the parameters */ | |
1153 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); | |
1154 | |
1155 /* Process locked */ | |
1156 __HAL_LOCK(hadc); | |
1157 | |
1158 /* Stop potential conversion on going, on regular and injected groups */ | |
1159 /* Disable ADC peripheral */ | |
1160 __HAL_ADC_DISABLE(hadc); | |
1161 | |
1162 /* Check if ADC is effectively disabled */ | |
1163 if(HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_ADON)) | |
1164 { | |
1165 /* Disable the selected ADC DMA mode */ | |
1166 hadc->Instance->CR2 &= ~ADC_CR2_DMA; | |
1167 | |
1168 /* Disable the DMA channel (in case of DMA in circular mode or stop while */ | |
1169 /* DMA transfer is on going) */ | |
1170 tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle); | |
1171 | |
1172 /* Disable ADC overrun interrupt */ | |
1173 __HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR); | |
1174 | |
1175 /* Set ADC state */ | |
1176 ADC_STATE_CLR_SET(hadc->State, | |
1177 HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY, | |
1178 HAL_ADC_STATE_READY); | |
1179 } | |
1180 | |
1181 /* Process unlocked */ | |
1182 __HAL_UNLOCK(hadc); | |
1183 | |
1184 /* Return function status */ | |
1185 return tmp_hal_status; | |
1186 } | |
1187 | |
1188 /** | |
1189 * @brief Gets the converted value from data register of regular channel. | |
1190 * @param hadc pointer to a ADC_HandleTypeDef structure that contains | |
1191 * the configuration information for the specified ADC. | |
1192 * @retval Converted value | |
1193 */ | |
1194 uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef* hadc) | |
1195 { | |
1196 /* Return the selected ADC converted value */ | |
1197 return hadc->Instance->DR; | |
1198 } | |
1199 | |
1200 /** | |
1201 * @brief Regular conversion complete callback in non blocking mode | |
1202 * @param hadc pointer to a ADC_HandleTypeDef structure that contains | |
1203 * the configuration information for the specified ADC. | |
1204 * @retval None | |
1205 */ | |
1206 __weak void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc) | |
1207 { | |
1208 /* Prevent unused argument(s) compilation warning */ | |
1209 UNUSED(hadc); | |
1210 /* NOTE : This function Should not be modified, when the callback is needed, | |
1211 the HAL_ADC_ConvCpltCallback could be implemented in the user file | |
1212 */ | |
1213 } | |
1214 | |
1215 /** | |
1216 * @brief Regular conversion half DMA transfer callback in non blocking mode | |
1217 * @param hadc pointer to a ADC_HandleTypeDef structure that contains | |
1218 * the configuration information for the specified ADC. | |
1219 * @retval None | |
1220 */ | |
1221 __weak void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef* hadc) | |
1222 { | |
1223 /* Prevent unused argument(s) compilation warning */ | |
1224 UNUSED(hadc); | |
1225 /* NOTE : This function Should not be modified, when the callback is needed, | |
1226 the HAL_ADC_ConvHalfCpltCallback could be implemented in the user file | |
1227 */ | |
1228 } | |
1229 | |
1230 /** | |
1231 * @brief Analog watchdog callback in non blocking mode | |
1232 * @param hadc pointer to a ADC_HandleTypeDef structure that contains | |
1233 * the configuration information for the specified ADC. | |
1234 * @retval None | |
1235 */ | |
1236 __weak void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef* hadc) | |
1237 { | |
1238 /* Prevent unused argument(s) compilation warning */ | |
1239 UNUSED(hadc); | |
1240 /* NOTE : This function Should not be modified, when the callback is needed, | |
1241 the HAL_ADC_LevelOoutOfWindowCallback could be implemented in the user file | |
1242 */ | |
1243 } | |
1244 | |
1245 /** | |
1246 * @brief Error ADC callback. | |
1247 * @note In case of error due to overrun when using ADC with DMA transfer | |
1248 * (HAL ADC handle paramater "ErrorCode" to state "HAL_ADC_ERROR_OVR"): | |
1249 * - Reinitialize the DMA using function "HAL_ADC_Stop_DMA()". | |
1250 * - If needed, restart a new ADC conversion using function | |
1251 * "HAL_ADC_Start_DMA()" | |
1252 * (this function is also clearing overrun flag) | |
1253 * @param hadc pointer to a ADC_HandleTypeDef structure that contains | |
1254 * the configuration information for the specified ADC. | |
1255 * @retval None | |
1256 */ | |
1257 __weak void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc) | |
1258 { | |
1259 /* Prevent unused argument(s) compilation warning */ | |
1260 UNUSED(hadc); | |
1261 /* NOTE : This function Should not be modified, when the callback is needed, | |
1262 the HAL_ADC_ErrorCallback could be implemented in the user file | |
1263 */ | |
1264 } | |
1265 | |
1266 /** | |
1267 * @} | |
1268 */ | |
1269 | |
1270 /** @defgroup ADC_Exported_Functions_Group3 Peripheral Control functions | |
1271 * @brief Peripheral Control functions | |
1272 * | |
1273 @verbatim | |
1274 =============================================================================== | |
1275 ##### Peripheral Control functions ##### | |
1276 =============================================================================== | |
1277 [..] This section provides functions allowing to: | |
1278 (+) Configure regular channels. | |
1279 (+) Configure injected channels. | |
1280 (+) Configure multimode. | |
1281 (+) Configure the analog watch dog. | |
1282 | |
1283 @endverbatim | |
1284 * @{ | |
1285 */ | |
1286 | |
1287 /** | |
1288 * @brief Configures for the selected ADC regular channel its corresponding | |
1289 * rank in the sequencer and its sample time. | |
1290 * @param hadc pointer to a ADC_HandleTypeDef structure that contains | |
1291 * the configuration information for the specified ADC. | |
1292 * @param sConfig ADC configuration structure. | |
1293 * @retval HAL status | |
1294 */ | |
1295 HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig) | |
1296 { | |
1297 __IO uint32_t counter = 0U; | |
1298 ADC_Common_TypeDef *tmpADC_Common; | |
1299 | |
1300 /* Check the parameters */ | |
1301 assert_param(IS_ADC_CHANNEL(sConfig->Channel)); | |
1302 assert_param(IS_ADC_REGULAR_RANK(sConfig->Rank)); | |
1303 assert_param(IS_ADC_SAMPLE_TIME(sConfig->SamplingTime)); | |
1304 | |
1305 /* Process locked */ | |
1306 __HAL_LOCK(hadc); | |
1307 | |
1308 /* if ADC_Channel_10 ... ADC_Channel_18 is selected */ | |
1309 if (sConfig->Channel > ADC_CHANNEL_9) | |
1310 { | |
1311 /* Clear the old sample time */ | |
1312 hadc->Instance->SMPR1 &= ~ADC_SMPR1(ADC_SMPR1_SMP10, sConfig->Channel); | |
1313 | |
1314 /* Set the new sample time */ | |
1315 hadc->Instance->SMPR1 |= ADC_SMPR1(sConfig->SamplingTime, sConfig->Channel); | |
1316 } | |
1317 else /* ADC_Channel include in ADC_Channel_[0..9] */ | |
1318 { | |
1319 /* Clear the old sample time */ | |
1320 hadc->Instance->SMPR2 &= ~ADC_SMPR2(ADC_SMPR2_SMP0, sConfig->Channel); | |
1321 | |
1322 /* Set the new sample time */ | |
1323 hadc->Instance->SMPR2 |= ADC_SMPR2(sConfig->SamplingTime, sConfig->Channel); | |
1324 } | |
1325 | |
1326 /* For Rank 1 to 6 */ | |
1327 if (sConfig->Rank < 7U) | |
1328 { | |
1329 /* Clear the old SQx bits for the selected rank */ | |
1330 hadc->Instance->SQR3 &= ~ADC_SQR3_RK(ADC_SQR3_SQ1, sConfig->Rank); | |
1331 | |
1332 /* Set the SQx bits for the selected rank */ | |
1333 hadc->Instance->SQR3 |= ADC_SQR3_RK(sConfig->Channel, sConfig->Rank); | |
1334 } | |
1335 /* For Rank 7 to 12 */ | |
1336 else if (sConfig->Rank < 13U) | |
1337 { | |
1338 /* Clear the old SQx bits for the selected rank */ | |
1339 hadc->Instance->SQR2 &= ~ADC_SQR2_RK(ADC_SQR2_SQ7, sConfig->Rank); | |
1340 | |
1341 /* Set the SQx bits for the selected rank */ | |
1342 hadc->Instance->SQR2 |= ADC_SQR2_RK(sConfig->Channel, sConfig->Rank); | |
1343 } | |
1344 /* For Rank 13 to 16 */ | |
1345 else | |
1346 { | |
1347 /* Clear the old SQx bits for the selected rank */ | |
1348 hadc->Instance->SQR1 &= ~ADC_SQR1_RK(ADC_SQR1_SQ13, sConfig->Rank); | |
1349 | |
1350 /* Set the SQx bits for the selected rank */ | |
1351 hadc->Instance->SQR1 |= ADC_SQR1_RK(sConfig->Channel, sConfig->Rank); | |
1352 } | |
1353 | |
1354 /* Pointer to the common control register to which is belonging hadc */ | |
1355 /* (Depending on STM32F4 product, there may be up to 3 ADCs and 1 common */ | |
1356 /* control register) */ | |
1357 tmpADC_Common = ADC_COMMON_REGISTER(hadc); | |
1358 | |
1359 /* if ADC1 Channel_18 is selected enable VBAT Channel */ | |
1360 if ((hadc->Instance == ADC1) && (sConfig->Channel == ADC_CHANNEL_VBAT)) | |
1361 { | |
1362 /* Enable the VBAT channel*/ | |
1363 tmpADC_Common->CCR |= ADC_CCR_VBATE; | |
1364 } | |
1365 | |
1366 /* if ADC1 Channel_16 or Channel_17 is selected enable TSVREFE Channel(Temperature sensor and VREFINT) */ | |
1367 if ((hadc->Instance == ADC1) && ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) || (sConfig->Channel == ADC_CHANNEL_VREFINT))) | |
1368 { | |
1369 /* Enable the TSVREFE channel*/ | |
1370 tmpADC_Common->CCR |= ADC_CCR_TSVREFE; | |
1371 | |
1372 if((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR)) | |
1373 { | |
1374 /* Delay for temperature sensor stabilization time */ | |
1375 /* Compute number of CPU cycles to wait for */ | |
1376 counter = (ADC_TEMPSENSOR_DELAY_US * (SystemCoreClock / 1000000U)); | |
1377 while(counter != 0U) | |
1378 { | |
1379 counter--; | |
1380 } | |
1381 } | |
1382 } | |
1383 | |
1384 /* Process unlocked */ | |
1385 __HAL_UNLOCK(hadc); | |
1386 | |
1387 /* Return function status */ | |
1388 return HAL_OK; | |
1389 } | |
1390 | |
1391 /** | |
1392 * @brief Configures the analog watchdog. | |
1393 * @note Analog watchdog thresholds can be modified while ADC conversion | |
1394 * is on going. | |
1395 * In this case, some constraints must be taken into account: | |
1396 * The programmed threshold values are effective from the next | |
1397 * ADC EOC (end of unitary conversion). | |
1398 * Considering that registers write delay may happen due to | |
1399 * bus activity, this might cause an uncertainty on the | |
1400 * effective timing of the new programmed threshold values. | |
1401 * @param hadc pointer to a ADC_HandleTypeDef structure that contains | |
1402 * the configuration information for the specified ADC. | |
1403 * @param AnalogWDGConfig pointer to an ADC_AnalogWDGConfTypeDef structure | |
1404 * that contains the configuration information of ADC analog watchdog. | |
1405 * @retval HAL status | |
1406 */ | |
1407 HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDGConfTypeDef* AnalogWDGConfig) | |
1408 { | |
1409 #ifdef USE_FULL_ASSERT | |
1410 uint32_t tmp = 0U; | |
1411 #endif /* USE_FULL_ASSERT */ | |
1412 | |
1413 /* Check the parameters */ | |
1414 assert_param(IS_ADC_ANALOG_WATCHDOG(AnalogWDGConfig->WatchdogMode)); | |
1415 assert_param(IS_ADC_CHANNEL(AnalogWDGConfig->Channel)); | |
1416 assert_param(IS_FUNCTIONAL_STATE(AnalogWDGConfig->ITMode)); | |
1417 | |
1418 #ifdef USE_FULL_ASSERT | |
1419 tmp = ADC_GET_RESOLUTION(hadc); | |
1420 assert_param(IS_ADC_RANGE(tmp, AnalogWDGConfig->HighThreshold)); | |
1421 assert_param(IS_ADC_RANGE(tmp, AnalogWDGConfig->LowThreshold)); | |
1422 #endif /* USE_FULL_ASSERT */ | |
1423 | |
1424 /* Process locked */ | |
1425 __HAL_LOCK(hadc); | |
1426 | |
1427 if(AnalogWDGConfig->ITMode == ENABLE) | |
1428 { | |
1429 /* Enable the ADC Analog watchdog interrupt */ | |
1430 __HAL_ADC_ENABLE_IT(hadc, ADC_IT_AWD); | |
1431 } | |
1432 else | |
1433 { | |
1434 /* Disable the ADC Analog watchdog interrupt */ | |
1435 __HAL_ADC_DISABLE_IT(hadc, ADC_IT_AWD); | |
1436 } | |
1437 | |
1438 /* Clear AWDEN, JAWDEN and AWDSGL bits */ | |
1439 hadc->Instance->CR1 &= ~(ADC_CR1_AWDSGL | ADC_CR1_JAWDEN | ADC_CR1_AWDEN); | |
1440 | |
1441 /* Set the analog watchdog enable mode */ | |
1442 hadc->Instance->CR1 |= AnalogWDGConfig->WatchdogMode; | |
1443 | |
1444 /* Set the high threshold */ | |
1445 hadc->Instance->HTR = AnalogWDGConfig->HighThreshold; | |
1446 | |
1447 /* Set the low threshold */ | |
1448 hadc->Instance->LTR = AnalogWDGConfig->LowThreshold; | |
1449 | |
1450 /* Clear the Analog watchdog channel select bits */ | |
1451 hadc->Instance->CR1 &= ~ADC_CR1_AWDCH; | |
1452 | |
1453 /* Set the Analog watchdog channel */ | |
1454 hadc->Instance->CR1 |= (uint32_t)((uint16_t)(AnalogWDGConfig->Channel)); | |
1455 | |
1456 /* Process unlocked */ | |
1457 __HAL_UNLOCK(hadc); | |
1458 | |
1459 /* Return function status */ | |
1460 return HAL_OK; | |
1461 } | |
1462 | |
1463 /** | |
1464 * @} | |
1465 */ | |
1466 | |
1467 /** @defgroup ADC_Exported_Functions_Group4 ADC Peripheral State functions | |
1468 * @brief ADC Peripheral State functions | |
1469 * | |
1470 @verbatim | |
1471 =============================================================================== | |
1472 ##### Peripheral State and errors functions ##### | |
1473 =============================================================================== | |
1474 [..] | |
1475 This subsection provides functions allowing to | |
1476 (+) Check the ADC state | |
1477 (+) Check the ADC Error | |
1478 | |
1479 @endverbatim | |
1480 * @{ | |
1481 */ | |
1482 | |
1483 /** | |
1484 * @brief return the ADC state | |
1485 * @param hadc pointer to a ADC_HandleTypeDef structure that contains | |
1486 * the configuration information for the specified ADC. | |
1487 * @retval HAL state | |
1488 */ | |
1489 uint32_t HAL_ADC_GetState(ADC_HandleTypeDef* hadc) | |
1490 { | |
1491 /* Return ADC state */ | |
1492 return hadc->State; | |
1493 } | |
1494 | |
1495 /** | |
1496 * @brief Return the ADC error code | |
1497 * @param hadc pointer to a ADC_HandleTypeDef structure that contains | |
1498 * the configuration information for the specified ADC. | |
1499 * @retval ADC Error Code | |
1500 */ | |
1501 uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc) | |
1502 { | |
1503 return hadc->ErrorCode; | |
1504 } | |
1505 | |
1506 /** | |
1507 * @} | |
1508 */ | |
1509 | |
1510 /** @addtogroup ADC_Private_Functions | |
1511 * @{ | |
1512 */ | |
1513 | |
1514 /** | |
1515 * @brief Initializes the ADCx peripheral according to the specified parameters | |
1516 * in the ADC_InitStruct without initializing the ADC MSP. | |
1517 * @param hadc pointer to a ADC_HandleTypeDef structure that contains | |
1518 * the configuration information for the specified ADC. | |
1519 * @retval None | |
1520 */ | |
1521 static void ADC_Init(ADC_HandleTypeDef* hadc) | |
1522 { | |
1523 ADC_Common_TypeDef *tmpADC_Common; | |
1524 | |
1525 /* Set ADC parameters */ | |
1526 /* Pointer to the common control register to which is belonging hadc */ | |
1527 /* (Depending on STM32F4 product, there may be up to 3 ADCs and 1 common */ | |
1528 /* control register) */ | |
1529 tmpADC_Common = ADC_COMMON_REGISTER(hadc); | |
1530 | |
1531 /* Set the ADC clock prescaler */ | |
1532 tmpADC_Common->CCR &= ~(ADC_CCR_ADCPRE); | |
1533 tmpADC_Common->CCR |= hadc->Init.ClockPrescaler; | |
1534 | |
1535 /* Set ADC scan mode */ | |
1536 hadc->Instance->CR1 &= ~(ADC_CR1_SCAN); | |
1537 hadc->Instance->CR1 |= ADC_CR1_SCANCONV(hadc->Init.ScanConvMode); | |
1538 | |
1539 /* Set ADC resolution */ | |
1540 hadc->Instance->CR1 &= ~(ADC_CR1_RES); | |
1541 hadc->Instance->CR1 |= hadc->Init.Resolution; | |
1542 | |
1543 /* Set ADC data alignment */ | |
1544 hadc->Instance->CR2 &= ~(ADC_CR2_ALIGN); | |
1545 hadc->Instance->CR2 |= hadc->Init.DataAlign; | |
1546 | |
1547 /* Enable external trigger if trigger selection is different of software */ | |
1548 /* start. */ | |
1549 /* Note: This configuration keeps the hardware feature of parameter */ | |
1550 /* ExternalTrigConvEdge "trigger edge none" equivalent to */ | |
1551 /* software start. */ | |
1552 if(hadc->Init.ExternalTrigConv != ADC_SOFTWARE_START) | |
1553 { | |
1554 /* Select external trigger to start conversion */ | |
1555 hadc->Instance->CR2 &= ~(ADC_CR2_EXTSEL); | |
1556 hadc->Instance->CR2 |= hadc->Init.ExternalTrigConv; | |
1557 | |
1558 /* Select external trigger polarity */ | |
1559 hadc->Instance->CR2 &= ~(ADC_CR2_EXTEN); | |
1560 hadc->Instance->CR2 |= hadc->Init.ExternalTrigConvEdge; | |
1561 } | |
1562 else | |
1563 { | |
1564 /* Reset the external trigger */ | |
1565 hadc->Instance->CR2 &= ~(ADC_CR2_EXTSEL); | |
1566 hadc->Instance->CR2 &= ~(ADC_CR2_EXTEN); | |
1567 } | |
1568 | |
1569 /* Enable or disable ADC continuous conversion mode */ | |
1570 hadc->Instance->CR2 &= ~(ADC_CR2_CONT); | |
1571 hadc->Instance->CR2 |= ADC_CR2_CONTINUOUS(hadc->Init.ContinuousConvMode); | |
1572 | |
1573 if(hadc->Init.DiscontinuousConvMode != DISABLE) | |
1574 { | |
1575 assert_param(IS_ADC_REGULAR_DISC_NUMBER(hadc->Init.NbrOfDiscConversion)); | |
1576 | |
1577 /* Enable the selected ADC regular discontinuous mode */ | |
1578 hadc->Instance->CR1 |= (uint32_t)ADC_CR1_DISCEN; | |
1579 | |
1580 /* Set the number of channels to be converted in discontinuous mode */ | |
1581 hadc->Instance->CR1 &= ~(ADC_CR1_DISCNUM); | |
1582 hadc->Instance->CR1 |= ADC_CR1_DISCONTINUOUS(hadc->Init.NbrOfDiscConversion); | |
1583 } | |
1584 else | |
1585 { | |
1586 /* Disable the selected ADC regular discontinuous mode */ | |
1587 hadc->Instance->CR1 &= ~(ADC_CR1_DISCEN); | |
1588 } | |
1589 | |
1590 /* Set ADC number of conversion */ | |
1591 hadc->Instance->SQR1 &= ~(ADC_SQR1_L); | |
1592 hadc->Instance->SQR1 |= ADC_SQR1(hadc->Init.NbrOfConversion); | |
1593 | |
1594 /* Enable or disable ADC DMA continuous request */ | |
1595 hadc->Instance->CR2 &= ~(ADC_CR2_DDS); | |
1596 hadc->Instance->CR2 |= ADC_CR2_DMAContReq(hadc->Init.DMAContinuousRequests); | |
1597 | |
1598 /* Enable or disable ADC end of conversion selection */ | |
1599 hadc->Instance->CR2 &= ~(ADC_CR2_EOCS); | |
1600 hadc->Instance->CR2 |= ADC_CR2_EOCSelection(hadc->Init.EOCSelection); | |
1601 } | |
1602 | |
1603 /** | |
1604 * @brief DMA transfer complete callback. | |
1605 * @param hdma pointer to a DMA_HandleTypeDef structure that contains | |
1606 * the configuration information for the specified DMA module. | |
1607 * @retval None | |
1608 */ | |
1609 static void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma) | |
1610 { | |
1611 /* Retrieve ADC handle corresponding to current DMA handle */ | |
1612 ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; | |
1613 | |
1614 /* Update state machine on conversion status if not in error state */ | |
1615 if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL | HAL_ADC_STATE_ERROR_DMA)) | |
1616 { | |
1617 /* Update ADC state machine */ | |
1618 SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC); | |
1619 | |
1620 /* Determine whether any further conversion upcoming on group regular */ | |
1621 /* by external trigger, continuous mode or scan sequence on going. */ | |
1622 /* Note: On STM32F4, there is no independent flag of end of sequence. */ | |
1623 /* The test of scan sequence on going is done either with scan */ | |
1624 /* sequence disabled or with end of conversion flag set to */ | |
1625 /* of end of sequence. */ | |
1626 if(ADC_IS_SOFTWARE_START_REGULAR(hadc) && | |
1627 (hadc->Init.ContinuousConvMode == DISABLE) && | |
1628 (HAL_IS_BIT_CLR(hadc->Instance->SQR1, ADC_SQR1_L) || | |
1629 HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_EOCS) ) ) | |
1630 { | |
1631 /* Disable ADC end of single conversion interrupt on group regular */ | |
1632 /* Note: Overrun interrupt was enabled with EOC interrupt in */ | |
1633 /* HAL_ADC_Start_IT(), but is not disabled here because can be used */ | |
1634 /* by overrun IRQ process below. */ | |
1635 __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC); | |
1636 | |
1637 /* Set ADC state */ | |
1638 CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY); | |
1639 | |
1640 if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY)) | |
1641 { | |
1642 SET_BIT(hadc->State, HAL_ADC_STATE_READY); | |
1643 } | |
1644 } | |
1645 | |
1646 /* Conversion complete callback */ | |
1647 HAL_ADC_ConvCpltCallback(hadc); | |
1648 } | |
1649 else | |
1650 { | |
1651 /* Call DMA error callback */ | |
1652 hadc->DMA_Handle->XferErrorCallback(hdma); | |
1653 } | |
1654 } | |
1655 | |
1656 /** | |
1657 * @brief DMA half transfer complete callback. | |
1658 * @param hdma pointer to a DMA_HandleTypeDef structure that contains | |
1659 * the configuration information for the specified DMA module. | |
1660 * @retval None | |
1661 */ | |
1662 static void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma) | |
1663 { | |
1664 ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; | |
1665 /* Conversion complete callback */ | |
1666 HAL_ADC_ConvHalfCpltCallback(hadc); | |
1667 } | |
1668 | |
1669 /** | |
1670 * @brief DMA error callback | |
1671 * @param hdma pointer to a DMA_HandleTypeDef structure that contains | |
1672 * the configuration information for the specified DMA module. | |
1673 * @retval None | |
1674 */ | |
1675 static void ADC_DMAError(DMA_HandleTypeDef *hdma) | |
1676 { | |
1677 ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; | |
1678 hadc->State= HAL_ADC_STATE_ERROR_DMA; | |
1679 /* Set ADC error code to DMA error */ | |
1680 hadc->ErrorCode |= HAL_ADC_ERROR_DMA; | |
1681 HAL_ADC_ErrorCallback(hadc); | |
1682 } | |
1683 | |
1684 /** | |
1685 * @} | |
1686 */ | |
1687 | |
1688 /** | |
1689 * @} | |
1690 */ | |
1691 | |
1692 #endif /* HAL_ADC_MODULE_ENABLED */ | |
1693 /** | |
1694 * @} | |
1695 */ | |
1696 | |
1697 /** | |
1698 * @} | |
1699 */ | |
1700 | |
1701 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |