Mercurial > public > ostc4

comparison Common/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dfsdm.c @ 128:c78bcbd5deda FlipDisplay

Find changesets by keywords (author, files, the commit message), revision number or hash, or revset expression.
Added current STM32 standandard libraries in version independend folder structure
author Ideenmodellierer
date Sun, 17 Feb 2019 21:12:22 +0100
parents
children
comparison
equal deleted inserted replaced
127:1369f8660eaa 128:c78bcbd5deda
1 /**
2 ******************************************************************************
3 * @file stm32f4xx_hal_dfsdm.c
4 * @author MCD Application Team
5 * @brief This file provides firmware functions to manage the following
6 * functionalities of the Digital Filter for Sigma-Delta Modulators
7 * (DFSDM) peripherals:
8 * + Initialization and configuration of channels and filters
9 * + Regular channels configuration
10 * + Injected channels configuration
11 * + Regular/Injected Channels DMA Configuration
12 * + Interrupts and flags management
13 * + Analog watchdog feature
14 * + Short-circuit detector feature
15 * + Extremes detector feature
16 * + Clock absence detector feature
17 * + Break generation on analog watchdog or short-circuit event
18 *
19 @verbatim
20 ==============================================================================
21 ##### How to use this driver #####
22 ==============================================================================
23 [..]
24 *** Channel initialization ***
25 ==============================
26 [..]
27 (#) User has first to initialize channels (before filters initialization).
28 (#) As prerequisite, fill in the HAL_DFSDM_ChannelMspInit() :
29 (++) Enable DFSDMz clock interface with __HAL_RCC_DFSDMz_CLK_ENABLE().
30 (++) Enable the clocks for the DFSDMz GPIOS with __HAL_RCC_GPIOx_CLK_ENABLE().
31 (++) Configure these DFSDMz pins in alternate mode using HAL_GPIO_Init().
32 (++) If interrupt mode is used, enable and configure DFSDMz_FLT0 global
33 interrupt with HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ().
34 (#) Configure the output clock, input, serial interface, analog watchdog,
35 offset and data right bit shift parameters for this channel using the
36 HAL_DFSDM_ChannelInit() function.
37
38 *** Channel clock absence detector ***
39 ======================================
40 [..]
41 (#) Start clock absence detector using HAL_DFSDM_ChannelCkabStart() or
42 HAL_DFSDM_ChannelCkabStart_IT().
43 (#) In polling mode, use HAL_DFSDM_ChannelPollForCkab() to detect the clock
44 absence.
45 (#) In interrupt mode, HAL_DFSDM_ChannelCkabCallback() will be called if
46 clock absence is detected.
47 (#) Stop clock absence detector using HAL_DFSDM_ChannelCkabStop() or
48 HAL_DFSDM_ChannelCkabStop_IT().
49 (#) Please note that the same mode (polling or interrupt) has to be used
50 for all channels because the channels are sharing the same interrupt.
51 (#) Please note also that in interrupt mode, if clock absence detector is
52 stopped for one channel, interrupt will be disabled for all channels.
53
54 *** Channel short circuit detector ***
55 ======================================
56 [..]
57 (#) Start short circuit detector using HAL_DFSDM_ChannelScdStart() or
58 or HAL_DFSDM_ChannelScdStart_IT().
59 (#) In polling mode, use HAL_DFSDM_ChannelPollForScd() to detect short
60 circuit.
61 (#) In interrupt mode, HAL_DFSDM_ChannelScdCallback() will be called if
62 short circuit is detected.
63 (#) Stop short circuit detector using HAL_DFSDM_ChannelScdStop() or
64 or HAL_DFSDM_ChannelScdStop_IT().
65 (#) Please note that the same mode (polling or interrupt) has to be used
66 for all channels because the channels are sharing the same interrupt.
67 (#) Please note also that in interrupt mode, if short circuit detector is
68 stopped for one channel, interrupt will be disabled for all channels.
69
70 *** Channel analog watchdog value ***
71 =====================================
72 [..]
73 (#) Get analog watchdog filter value of a channel using
74 HAL_DFSDM_ChannelGetAwdValue().
75
76 *** Channel offset value ***
77 =====================================
78 [..]
79 (#) Modify offset value of a channel using HAL_DFSDM_ChannelModifyOffset().
80
81 *** Filter initialization ***
82 =============================
83 [..]
84 (#) After channel initialization, user has to init filters.
85 (#) As prerequisite, fill in the HAL_DFSDM_FilterMspInit() :
86 (++) If interrupt mode is used , enable and configure DFSDMz_FLTx global
87 interrupt with HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ().
88 Please note that DFSDMz_FLT0 global interrupt could be already
89 enabled if interrupt is used for channel.
90 (++) If DMA mode is used, configure DMA with HAL_DMA_Init() and link it
91 with DFSDMz filter handle using __HAL_LINKDMA().
92 (#) Configure the regular conversion, injected conversion and filter
93 parameters for this filter using the HAL_DFSDM_FilterInit() function.
94
95 *** Filter regular channel conversion ***
96 =========================================
97 [..]
98 (#) Select regular channel and enable/disable continuous mode using
99 HAL_DFSDM_FilterConfigRegChannel().
100 (#) Start regular conversion using HAL_DFSDM_FilterRegularStart(),
101 HAL_DFSDM_FilterRegularStart_IT(), HAL_DFSDM_FilterRegularStart_DMA() or
102 HAL_DFSDM_FilterRegularMsbStart_DMA().
103 (#) In polling mode, use HAL_DFSDM_FilterPollForRegConversion() to detect
104 the end of regular conversion.
105 (#) In interrupt mode, HAL_DFSDM_FilterRegConvCpltCallback() will be called
106 at the end of regular conversion.
107 (#) Get value of regular conversion and corresponding channel using
108 HAL_DFSDM_FilterGetRegularValue().
109 (#) In DMA mode, HAL_DFSDM_FilterRegConvHalfCpltCallback() and
110 HAL_DFSDM_FilterRegConvCpltCallback() will be called respectively at the
111 half transfer and at the transfer complete. Please note that
112 HAL_DFSDM_FilterRegConvHalfCpltCallback() will be called only in DMA
113 circular mode.
114 (#) Stop regular conversion using HAL_DFSDM_FilterRegularStop(),
115 HAL_DFSDM_FilterRegularStop_IT() or HAL_DFSDM_FilterRegularStop_DMA().
116
117 *** Filter injected channels conversion ***
118 ===========================================
119 [..]
120 (#) Select injected channels using HAL_DFSDM_FilterConfigInjChannel().
121 (#) Start injected conversion using HAL_DFSDM_FilterInjectedStart(),
122 HAL_DFSDM_FilterInjectedStart_IT(), HAL_DFSDM_FilterInjectedStart_DMA() or
123 HAL_DFSDM_FilterInjectedMsbStart_DMA().
124 (#) In polling mode, use HAL_DFSDM_FilterPollForInjConversion() to detect
125 the end of injected conversion.
126 (#) In interrupt mode, HAL_DFSDM_FilterInjConvCpltCallback() will be called
127 at the end of injected conversion.
128 (#) Get value of injected conversion and corresponding channel using
129 HAL_DFSDM_FilterGetInjectedValue().
130 (#) In DMA mode, HAL_DFSDM_FilterInjConvHalfCpltCallback() and
131 HAL_DFSDM_FilterInjConvCpltCallback() will be called respectively at the
132 half transfer and at the transfer complete. Please note that
133 HAL_DFSDM_FilterInjConvCpltCallback() will be called only in DMA
134 circular mode.
135 (#) Stop injected conversion using HAL_DFSDM_FilterInjectedStop(),
136 HAL_DFSDM_FilterInjectedStop_IT() or HAL_DFSDM_FilterInjectedStop_DMA().
137
138 *** Filter analog watchdog ***
139 ==============================
140 [..]
141 (#) Start filter analog watchdog using HAL_DFSDM_FilterAwdStart_IT().
142 (#) HAL_DFSDM_FilterAwdCallback() will be called if analog watchdog occurs.
143 (#) Stop filter analog watchdog using HAL_DFSDM_FilterAwdStop_IT().
144
145 *** Filter extreme detector ***
146 ===============================
147 [..]
148 (#) Start filter extreme detector using HAL_DFSDM_FilterExdStart().
149 (#) Get extreme detector maximum value using HAL_DFSDM_FilterGetExdMaxValue().
150 (#) Get extreme detector minimum value using HAL_DFSDM_FilterGetExdMinValue().
151 (#) Start filter extreme detector using HAL_DFSDM_FilterExdStop().
152
153 *** Filter conversion time ***
154 ==============================
155 [..]
156 (#) Get conversion time value using HAL_DFSDM_FilterGetConvTimeValue().
157
158 @endverbatim
159 ******************************************************************************
160 * @attention
161 *
162 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
163 *
164 * Redistribution and use in source and binary forms, with or without modification,
165 * are permitted provided that the following conditions are met:
166 * 1. Redistributions of source code must retain the above copyright notice,
167 * this list of conditions and the following disclaimer.
168 * 2. Redistributions in binary form must reproduce the above copyright notice,
169 * this list of conditions and the following disclaimer in the documentation
170 * and/or other materials provided with the distribution.
171 * 3. Neither the name of STMicroelectronics nor the names of its contributors
172 * may be used to endorse or promote products derived from this software
173 * without specific prior written permission.
174 *
175 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
176 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
177 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
178 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
179 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
180 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
181 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
182 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
183 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
184 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
185 *
186 ******************************************************************************
187 */
188
189 /* Includes ------------------------------------------------------------------*/
190 #include "stm32f4xx_hal.h"
191
192 /** @addtogroup STM32F4xx_HAL_Driver
193 * @{
194 */
195 #ifdef HAL_DFSDM_MODULE_ENABLED
196 #if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)
197 /** @defgroup DFSDM DFSDM
198 * @brief DFSDM HAL driver module
199 * @{
200 */
201
202 /* Private typedef -----------------------------------------------------------*/
203 /* Private define ------------------------------------------------------------*/
204 /** @defgroup DFSDM_Private_Define DFSDM Private Define
205 * @{
206 */
207
208 #define DFSDM_FLTCR1_MSB_RCH_OFFSET 8U
209
210 #define DFSDM_MSB_MASK 0xFFFF0000U
211 #define DFSDM_LSB_MASK 0x0000FFFFU
212 #define DFSDM_CKAB_TIMEOUT 5000U
213 #define DFSDM1_CHANNEL_NUMBER 4U
214 #if defined (DFSDM2_Channel0)
215 #define DFSDM2_CHANNEL_NUMBER 8U
216 #endif /* DFSDM2_Channel0 */
217
218 /**
219 * @}
220 */
221 /** @addtogroup DFSDM_Private_Macros
222 * @{
223 */
224
225 /**
226 * @}
227 */
228 /* Private macro -------------------------------------------------------------*/
229 /* Private variables ---------------------------------------------------------*/
230 /** @defgroup DFSDM_Private_Variables DFSDM Private Variables
231 * @{
232 */
233 __IO uint32_t v_dfsdm1ChannelCounter = 0U;
234 DFSDM_Channel_HandleTypeDef* a_dfsdm1ChannelHandle[DFSDM1_CHANNEL_NUMBER] = {NULL};
235
236 #if defined (DFSDM2_Channel0)
237 __IO uint32_t v_dfsdm2ChannelCounter = 0U;
238 DFSDM_Channel_HandleTypeDef* a_dfsdm2ChannelHandle[DFSDM2_CHANNEL_NUMBER] = {NULL};
239 #endif /* DFSDM2_Channel0 */
240 /**
241 * @}
242 */
243
244 /* Private function prototypes -----------------------------------------------*/
245 /** @defgroup DFSDM_Private_Functions DFSDM Private Functions
246 * @{
247 */
248 static uint32_t DFSDM_GetInjChannelsNbr(uint32_t Channels);
249 static uint32_t DFSDM_GetChannelFromInstance(DFSDM_Channel_TypeDef* Instance);
250 static void DFSDM_RegConvStart(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
251 static void DFSDM_RegConvStop(DFSDM_Filter_HandleTypeDef* hdfsdm_filter);
252 static void DFSDM_InjConvStart(DFSDM_Filter_HandleTypeDef* hdfsdm_filter);
253 static void DFSDM_InjConvStop(DFSDM_Filter_HandleTypeDef* hdfsdm_filter);
254 static void DFSDM_DMARegularHalfConvCplt(DMA_HandleTypeDef *hdma);
255 static void DFSDM_DMARegularConvCplt(DMA_HandleTypeDef *hdma);
256 static void DFSDM_DMAInjectedHalfConvCplt(DMA_HandleTypeDef *hdma);
257 static void DFSDM_DMAInjectedConvCplt(DMA_HandleTypeDef *hdma);
258 static void DFSDM_DMAError(DMA_HandleTypeDef *hdma);
259
260 /**
261 * @}
262 */
263
264 /* Exported functions --------------------------------------------------------*/
265 /** @defgroup DFSDM_Exported_Functions DFSDM Exported Functions
266 * @{
267 */
268
269 /** @defgroup DFSDM_Exported_Functions_Group1_Channel Channel initialization and de-initialization functions
270 * @brief Channel initialization and de-initialization functions
271 *
272 @verbatim
273 ==============================================================================
274 ##### Channel initialization and de-initialization functions #####
275 ==============================================================================
276 [..] This section provides functions allowing to:
277 (+) Initialize the DFSDM channel.
278 (+) De-initialize the DFSDM channel.
279 @endverbatim
280 * @{
281 */
282
283 /**
284 * @brief Initialize the DFSDM channel according to the specified parameters
285 * in the DFSDM_ChannelInitTypeDef structure and initialize the associated handle.
286 * @param hdfsdm_channel DFSDM channel handle.
287 * @retval HAL status.
288 */
289 HAL_StatusTypeDef HAL_DFSDM_ChannelInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
290 {
291 #if defined(DFSDM2_Channel0)
292 __IO uint32_t* channelCounterPtr;
293 DFSDM_Channel_HandleTypeDef **channelHandleTable;
294 DFSDM_Channel_TypeDef* channel0Instance;
295 #endif /* defined(DFSDM2_Channel0) */
296
297 /* Check DFSDM Channel handle */
298 if(hdfsdm_channel == NULL)
299 {
300 return HAL_ERROR;
301 }
302
303 /* Check parameters */
304 assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance));
305 assert_param(IS_FUNCTIONAL_STATE(hdfsdm_channel->Init.OutputClock.Activation));
306 assert_param(IS_DFSDM_CHANNEL_INPUT(hdfsdm_channel->Init.Input.Multiplexer));
307 assert_param(IS_DFSDM_CHANNEL_DATA_PACKING(hdfsdm_channel->Init.Input.DataPacking));
308 assert_param(IS_DFSDM_CHANNEL_INPUT_PINS(hdfsdm_channel->Init.Input.Pins));
309 assert_param(IS_DFSDM_CHANNEL_SERIAL_INTERFACE_TYPE(hdfsdm_channel->Init.SerialInterface.Type));
310 assert_param(IS_DFSDM_CHANNEL_SPI_CLOCK(hdfsdm_channel->Init.SerialInterface.SpiClock));
311 assert_param(IS_DFSDM_CHANNEL_FILTER_ORDER(hdfsdm_channel->Init.Awd.FilterOrder));
312 assert_param(IS_DFSDM_CHANNEL_FILTER_OVS_RATIO(hdfsdm_channel->Init.Awd.Oversampling));
313 assert_param(IS_DFSDM_CHANNEL_OFFSET(hdfsdm_channel->Init.Offset));
314 assert_param(IS_DFSDM_CHANNEL_RIGHT_BIT_SHIFT(hdfsdm_channel->Init.RightBitShift));
315
316 #if defined(DFSDM2_Channel0)
317 /* Get channel counter, channel handle table and channel 0 instance */
318 if(IS_DFSDM1_CHANNEL_INSTANCE(hdfsdm_channel->Instance))
319 {
320 channelCounterPtr = &v_dfsdm1ChannelCounter;
321 channelHandleTable = a_dfsdm1ChannelHandle;
322 channel0Instance = DFSDM1_Channel0;
323 }
324 else
325 {
326 channelCounterPtr = &v_dfsdm2ChannelCounter;
327 channelHandleTable = a_dfsdm2ChannelHandle;
328 channel0Instance = DFSDM2_Channel0;
329 }
330
331 /* Check that channel has not been already initialized */
332 if(channelHandleTable[DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance)] != NULL)
333 {
334 return HAL_ERROR;
335 }
336
337 /* Call MSP init function */
338 HAL_DFSDM_ChannelMspInit(hdfsdm_channel);
339
340 /* Update the channel counter */
341 (*channelCounterPtr)++;
342
343 /* Configure output serial clock and enable global DFSDM interface only for first channel */
344 if(*channelCounterPtr == 1U)
345 {
346 assert_param(IS_DFSDM_CHANNEL_OUTPUT_CLOCK(hdfsdm_channel->Init.OutputClock.Selection));
347 /* Set the output serial clock source */
348 channel0Instance->CHCFGR1 &= ~(DFSDM_CHCFGR1_CKOUTSRC);
349 channel0Instance->CHCFGR1 |= hdfsdm_channel->Init.OutputClock.Selection;
350
351 /* Reset clock divider */
352 channel0Instance->CHCFGR1 &= ~(DFSDM_CHCFGR1_CKOUTDIV);
353 if(hdfsdm_channel->Init.OutputClock.Activation == ENABLE)
354 {
355 assert_param(IS_DFSDM_CHANNEL_OUTPUT_CLOCK_DIVIDER(hdfsdm_channel->Init.OutputClock.Divider));
356 /* Set the output clock divider */
357 channel0Instance->CHCFGR1 |= (uint32_t) ((hdfsdm_channel->Init.OutputClock.Divider - 1U) <<
358 DFSDM_CHCFGR1_CKOUTDIV_Pos);
359 }
360
361 /* enable the DFSDM global interface */
362 channel0Instance->CHCFGR1 |= DFSDM_CHCFGR1_DFSDMEN;
363 }
364
365 /* Set channel input parameters */
366 hdfsdm_channel->Instance->CHCFGR1 &= ~(DFSDM_CHCFGR1_DATPACK | DFSDM_CHCFGR1_DATMPX |
367 DFSDM_CHCFGR1_CHINSEL);
368 hdfsdm_channel->Instance->CHCFGR1 |= (hdfsdm_channel->Init.Input.Multiplexer |
369 hdfsdm_channel->Init.Input.DataPacking |
370 hdfsdm_channel->Init.Input.Pins);
371
372 /* Set serial interface parameters */
373 hdfsdm_channel->Instance->CHCFGR1 &= ~(DFSDM_CHCFGR1_SITP | DFSDM_CHCFGR1_SPICKSEL);
374 hdfsdm_channel->Instance->CHCFGR1 |= (hdfsdm_channel->Init.SerialInterface.Type |
375 hdfsdm_channel->Init.SerialInterface.SpiClock);
376
377 /* Set analog watchdog parameters */
378 hdfsdm_channel->Instance->CHAWSCDR &= ~(DFSDM_CHAWSCDR_AWFORD | DFSDM_CHAWSCDR_AWFOSR);
379 hdfsdm_channel->Instance->CHAWSCDR |= (hdfsdm_channel->Init.Awd.FilterOrder |
380 ((hdfsdm_channel->Init.Awd.Oversampling - 1U) << DFSDM_CHAWSCDR_AWFOSR_Pos));
381
382 /* Set channel offset and right bit shift */
383 hdfsdm_channel->Instance->CHCFGR2 &= ~(DFSDM_CHCFGR2_OFFSET | DFSDM_CHCFGR2_DTRBS);
384 hdfsdm_channel->Instance->CHCFGR2 |= (((uint32_t) hdfsdm_channel->Init.Offset << DFSDM_CHCFGR2_OFFSET_Pos) |
385 (hdfsdm_channel->Init.RightBitShift << DFSDM_CHCFGR2_DTRBS_Pos));
386
387 /* Enable DFSDM channel */
388 hdfsdm_channel->Instance->CHCFGR1 |= DFSDM_CHCFGR1_CHEN;
389
390 /* Set DFSDM Channel to ready state */
391 hdfsdm_channel->State = HAL_DFSDM_CHANNEL_STATE_READY;
392
393 /* Store channel handle in DFSDM channel handle table */
394 channelHandleTable[DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance)] = hdfsdm_channel;
395
396 #else
397 /* Check that channel has not been already initialized */
398 if(a_dfsdm1ChannelHandle[DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance)] != NULL)
399 {
400 return HAL_ERROR;
401 }
402
403 /* Call MSP init function */
404 HAL_DFSDM_ChannelMspInit(hdfsdm_channel);
405
406 /* Update the channel counter */
407 v_dfsdm1ChannelCounter++;
408
409 /* Configure output serial clock and enable global DFSDM interface only for first channel */
410 if(v_dfsdm1ChannelCounter == 1U)
411 {
412 assert_param(IS_DFSDM_CHANNEL_OUTPUT_CLOCK(hdfsdm_channel->Init.OutputClock.Selection));
413 /* Set the output serial clock source */
414 DFSDM1_Channel0->CHCFGR1 &= ~(DFSDM_CHCFGR1_CKOUTSRC);
415 DFSDM1_Channel0->CHCFGR1 |= hdfsdm_channel->Init.OutputClock.Selection;
416
417 /* Reset clock divider */
418 DFSDM1_Channel0->CHCFGR1 &= ~(DFSDM_CHCFGR1_CKOUTDIV);
419 if(hdfsdm_channel->Init.OutputClock.Activation == ENABLE)
420 {
421 assert_param(IS_DFSDM_CHANNEL_OUTPUT_CLOCK_DIVIDER(hdfsdm_channel->Init.OutputClock.Divider));
422 /* Set the output clock divider */
423 DFSDM1_Channel0->CHCFGR1 |= (uint32_t) ((hdfsdm_channel->Init.OutputClock.Divider - 1U) <<
424 DFSDM_CHCFGR1_CKOUTDIV_Pos);
425 }
426
427 /* enable the DFSDM global interface */
428 DFSDM1_Channel0->CHCFGR1 |= DFSDM_CHCFGR1_DFSDMEN;
429 }
430
431 /* Set channel input parameters */
432 hdfsdm_channel->Instance->CHCFGR1 &= ~(DFSDM_CHCFGR1_DATPACK | DFSDM_CHCFGR1_DATMPX |
433 DFSDM_CHCFGR1_CHINSEL);
434 hdfsdm_channel->Instance->CHCFGR1 |= (hdfsdm_channel->Init.Input.Multiplexer |
435 hdfsdm_channel->Init.Input.DataPacking |
436 hdfsdm_channel->Init.Input.Pins);
437
438 /* Set serial interface parameters */
439 hdfsdm_channel->Instance->CHCFGR1 &= ~(DFSDM_CHCFGR1_SITP | DFSDM_CHCFGR1_SPICKSEL);
440 hdfsdm_channel->Instance->CHCFGR1 |= (hdfsdm_channel->Init.SerialInterface.Type |
441 hdfsdm_channel->Init.SerialInterface.SpiClock);
442
443 /* Set analog watchdog parameters */
444 hdfsdm_channel->Instance->CHAWSCDR &= ~(DFSDM_CHAWSCDR_AWFORD | DFSDM_CHAWSCDR_AWFOSR);
445 hdfsdm_channel->Instance->CHAWSCDR |= (hdfsdm_channel->Init.Awd.FilterOrder |
446 ((hdfsdm_channel->Init.Awd.Oversampling - 1U) << DFSDM_CHAWSCDR_AWFOSR_Pos));
447
448 /* Set channel offset and right bit shift */
449 hdfsdm_channel->Instance->CHCFGR2 &= ~(DFSDM_CHCFGR2_OFFSET | DFSDM_CHCFGR2_DTRBS);
450 hdfsdm_channel->Instance->CHCFGR2 |= (((uint32_t) hdfsdm_channel->Init.Offset << DFSDM_CHCFGR2_OFFSET_Pos) |
451 (hdfsdm_channel->Init.RightBitShift << DFSDM_CHCFGR2_DTRBS_Pos));
452
453 /* Enable DFSDM channel */
454 hdfsdm_channel->Instance->CHCFGR1 |= DFSDM_CHCFGR1_CHEN;
455
456 /* Set DFSDM Channel to ready state */
457 hdfsdm_channel->State = HAL_DFSDM_CHANNEL_STATE_READY;
458
459 /* Store channel handle in DFSDM channel handle table */
460 a_dfsdm1ChannelHandle[DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance)] = hdfsdm_channel;
461 #endif /* DFSDM2_Channel0 */
462
463 return HAL_OK;
464 }
465
466 /**
467 * @brief De-initialize the DFSDM channel.
468 * @param hdfsdm_channel DFSDM channel handle.
469 * @retval HAL status.
470 */
471 HAL_StatusTypeDef HAL_DFSDM_ChannelDeInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
472 {
473 #if defined(DFSDM2_Channel0)
474 __IO uint32_t* channelCounterPtr;
475 DFSDM_Channel_HandleTypeDef **channelHandleTable;
476 DFSDM_Channel_TypeDef* channel0Instance;
477 #endif /* defined(DFSDM2_Channel0) */
478
479 /* Check DFSDM Channel handle */
480 if(hdfsdm_channel == NULL)
481 {
482 return HAL_ERROR;
483 }
484
485 /* Check parameters */
486 assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance));
487
488 #if defined(DFSDM2_Channel0)
489 /* Get channel counter, channel handle table and channel 0 instance */
490 if(IS_DFSDM1_CHANNEL_INSTANCE(hdfsdm_channel->Instance))
491 {
492 channelCounterPtr = &v_dfsdm1ChannelCounter;
493 channelHandleTable = a_dfsdm1ChannelHandle;
494 channel0Instance = DFSDM1_Channel0;
495 }
496 else
497 {
498 channelCounterPtr = &v_dfsdm2ChannelCounter;
499 channelHandleTable = a_dfsdm2ChannelHandle;
500 channel0Instance = DFSDM2_Channel0;
501 }
502
503 /* Check that channel has not been already deinitialized */
504 if(channelHandleTable[DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance)] == NULL)
505 {
506 return HAL_ERROR;
507 }
508
509 /* Disable the DFSDM channel */
510 hdfsdm_channel->Instance->CHCFGR1 &= ~(DFSDM_CHCFGR1_CHEN);
511
512 /* Update the channel counter */
513 (*channelCounterPtr)--;
514
515 /* Disable global DFSDM at deinit of last channel */
516 if(*channelCounterPtr == 0U)
517 {
518 channel0Instance->CHCFGR1 &= ~(DFSDM_CHCFGR1_DFSDMEN);
519 }
520
521 /* Call MSP deinit function */
522 HAL_DFSDM_ChannelMspDeInit(hdfsdm_channel);
523
524 /* Set DFSDM Channel in reset state */
525 hdfsdm_channel->State = HAL_DFSDM_CHANNEL_STATE_RESET;
526
527 /* Reset channel handle in DFSDM channel handle table */
528 channelHandleTable[DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance)] = NULL;
529 #else
530 /* Check that channel has not been already deinitialized */
531 if(a_dfsdm1ChannelHandle[DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance)] == NULL)
532 {
533 return HAL_ERROR;
534 }
535
536 /* Disable the DFSDM channel */
537 hdfsdm_channel->Instance->CHCFGR1 &= ~(DFSDM_CHCFGR1_CHEN);
538
539 /* Update the channel counter */
540 v_dfsdm1ChannelCounter--;
541
542 /* Disable global DFSDM at deinit of last channel */
543 if(v_dfsdm1ChannelCounter == 0U)
544 {
545 DFSDM1_Channel0->CHCFGR1 &= ~(DFSDM_CHCFGR1_DFSDMEN);
546 }
547
548 /* Call MSP deinit function */
549 HAL_DFSDM_ChannelMspDeInit(hdfsdm_channel);
550
551 /* Set DFSDM Channel in reset state */
552 hdfsdm_channel->State = HAL_DFSDM_CHANNEL_STATE_RESET;
553
554 /* Reset channel handle in DFSDM channel handle table */
555 a_dfsdm1ChannelHandle[DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance)] = (DFSDM_Channel_HandleTypeDef *) NULL;
556 #endif /* defined(DFSDM2_Channel0) */
557
558 return HAL_OK;
559 }
560
561 /**
562 * @brief Initialize the DFSDM channel MSP.
563 * @param hdfsdm_channel DFSDM channel handle.
564 * @retval None
565 */
566 __weak void HAL_DFSDM_ChannelMspInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
567 {
568 /* Prevent unused argument(s) compilation warning */
569 UNUSED(hdfsdm_channel);
570 /* NOTE : This function should not be modified, when the function is needed,
571 the HAL_DFSDM_ChannelMspInit could be implemented in the user file.
572 */
573 }
574
575 /**
576 * @brief De-initialize the DFSDM channel MSP.
577 * @param hdfsdm_channel DFSDM channel handle.
578 * @retval None
579 */
580 __weak void HAL_DFSDM_ChannelMspDeInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
581 {
582 /* Prevent unused argument(s) compilation warning */
583 UNUSED(hdfsdm_channel);
584 /* NOTE : This function should not be modified, when the function is needed,
585 the HAL_DFSDM_ChannelMspDeInit could be implemented in the user file.
586 */
587 }
588
589 /**
590 * @}
591 */
592
593 /** @defgroup DFSDM_Exported_Functions_Group2_Channel Channel operation functions
594 * @brief Channel operation functions
595 *
596 @verbatim
597 ==============================================================================
598 ##### Channel operation functions #####
599 ==============================================================================
600 [..] This section provides functions allowing to:
601 (+) Manage clock absence detector feature.
602 (+) Manage short circuit detector feature.
603 (+) Get analog watchdog value.
604 (+) Modify offset value.
605 @endverbatim
606 * @{
607 */
608
609 /**
610 * @brief This function allows to start clock absence detection in polling mode.
611 * @note Same mode has to be used for all channels.
612 * @note If clock is not available on this channel during 5 seconds,
613 * clock absence detection will not be activated and function
614 * will return HAL_TIMEOUT error.
615 * @param hdfsdm_channel DFSDM channel handle.
616 * @retval HAL status
617 */
618 HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStart(DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
619 {
620 HAL_StatusTypeDef status = HAL_OK;
621 uint32_t tickstart;
622 uint32_t channel;
623
624 #if defined(DFSDM2_Channel0)
625 DFSDM_Filter_TypeDef* filter0Instance;
626 #endif /* defined(DFSDM2_Channel0) */
627
628 /* Check parameters */
629 assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance));
630
631 /* Check DFSDM channel state */
632 if(hdfsdm_channel->State != HAL_DFSDM_CHANNEL_STATE_READY)
633 {
634 /* Return error status */
635 status = HAL_ERROR;
636 }
637 else
638 {
639 #if defined (DFSDM2_Channel0)
640 /* Get channel counter, channel handle table and channel 0 instance */
641 if(IS_DFSDM1_CHANNEL_INSTANCE(hdfsdm_channel->Instance))
642 {
643 filter0Instance = DFSDM1_Filter0;
644 }
645 else
646 {
647 filter0Instance = DFSDM2_Filter0;
648 }
649 /* Get channel number from channel instance */
650 channel = DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance);
651
652 /* Get timeout */
653 tickstart = HAL_GetTick();
654
655 /* Clear clock absence flag */
656 while((((filter0Instance->FLTISR & DFSDM_FLTISR_CKABF) >> (DFSDM_FLTISR_CKABF_Pos + channel)) & 1U) != 0U)
657 {
658 filter0Instance->FLTICR = (1U << (DFSDM_FLTICR_CLRCKABF_Pos + channel));
659
660 /* Check the Timeout */
661 if((HAL_GetTick()-tickstart) > DFSDM_CKAB_TIMEOUT)
662 {
663 /* Set timeout status */
664 status = HAL_TIMEOUT;
665 break;
666 }
667 }
668 #else
669 /* Get channel number from channel instance */
670 channel = DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance);
671
672 /* Get timeout */
673 tickstart = HAL_GetTick();
674
675 /* Clear clock absence flag */
676 while((((DFSDM1_Filter0->FLTISR & DFSDM_FLTISR_CKABF) >> (DFSDM_FLTISR_CKABF_Pos + channel)) & 1U) != 0U)
677 {
678 DFSDM1_Filter0->FLTICR = (1U << (DFSDM_FLTICR_CLRCKABF_Pos + channel));
679
680 /* Check the Timeout */
681 if((HAL_GetTick()-tickstart) > DFSDM_CKAB_TIMEOUT)
682 {
683 /* Set timeout status */
684 status = HAL_TIMEOUT;
685 break;
686 }
687 }
688 #endif /* DFSDM2_Channel0 */
689
690 if(status == HAL_OK)
691 {
692 /* Start clock absence detection */
693 hdfsdm_channel->Instance->CHCFGR1 |= DFSDM_CHCFGR1_CKABEN;
694 }
695 }
696 /* Return function status */
697 return status;
698 }
699
700 /**
701 * @brief This function allows to poll for the clock absence detection.
702 * @param hdfsdm_channel DFSDM channel handle.
703 * @param Timeout Timeout value in milliseconds.
704 * @retval HAL status
705 */
706 HAL_StatusTypeDef HAL_DFSDM_ChannelPollForCkab(DFSDM_Channel_HandleTypeDef *hdfsdm_channel,
707 uint32_t Timeout)
708 {
709 uint32_t tickstart;
710 uint32_t channel;
711 #if defined(DFSDM2_Channel0)
712 DFSDM_Filter_TypeDef* filter0Instance;
713 #endif /* defined(DFSDM2_Channel0) */
714
715 /* Check parameters */
716 assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance));
717
718 /* Check DFSDM channel state */
719 if(hdfsdm_channel->State != HAL_DFSDM_CHANNEL_STATE_READY)
720 {
721 /* Return error status */
722 return HAL_ERROR;
723 }
724 else
725 {
726 #if defined(DFSDM2_Channel0)
727
728 /* Get channel counter, channel handle table and channel 0 instance */
729 if(IS_DFSDM1_CHANNEL_INSTANCE(hdfsdm_channel->Instance))
730 {
731 filter0Instance = DFSDM1_Filter0;
732 }
733 else
734 {
735 filter0Instance = DFSDM2_Filter0;
736 }
737
738 /* Get channel number from channel instance */
739 channel = DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance);
740
741 /* Get timeout */
742 tickstart = HAL_GetTick();
743
744 /* Wait clock absence detection */
745 while((((filter0Instance->FLTISR & DFSDM_FLTISR_CKABF) >> (DFSDM_FLTISR_CKABF_Pos + channel)) & 1U) == 0U)
746 {
747 /* Check the Timeout */
748 if(Timeout != HAL_MAX_DELAY)
749 {
750 if((Timeout == 0U) || ((HAL_GetTick()-tickstart) > Timeout))
751 {
752 /* Return timeout status */
753 return HAL_TIMEOUT;
754 }
755 }
756 }
757
758 /* Clear clock absence detection flag */
759 filter0Instance->FLTICR = (1U << (DFSDM_FLTICR_CLRCKABF_Pos + channel));
760 #else
761 /* Get channel number from channel instance */
762 channel = DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance);
763
764 /* Get timeout */
765 tickstart = HAL_GetTick();
766
767 /* Wait clock absence detection */
768 while((((DFSDM1_Filter0->FLTISR & DFSDM_FLTISR_CKABF) >> (DFSDM_FLTISR_CKABF_Pos + channel)) & 1U) == 0U)
769 {
770 /* Check the Timeout */
771 if(Timeout != HAL_MAX_DELAY)
772 {
773 if((Timeout == 0U) || ((HAL_GetTick()-tickstart) > Timeout))
774 {
775 /* Return timeout status */
776 return HAL_TIMEOUT;
777 }
778 }
779 }
780
781 /* Clear clock absence detection flag */
782 DFSDM1_Filter0->FLTICR = (1U << (DFSDM_FLTICR_CLRCKABF_Pos + channel));
783 #endif /* defined(DFSDM2_Channel0) */
784 /* Return function status */
785 return HAL_OK;
786 }
787 }
788
789 /**
790 * @brief This function allows to stop clock absence detection in polling mode.
791 * @param hdfsdm_channel DFSDM channel handle.
792 * @retval HAL status
793 */
794 HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStop(DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
795 {
796 HAL_StatusTypeDef status = HAL_OK;
797 uint32_t channel;
798 #if defined(DFSDM2_Channel0)
799 DFSDM_Filter_TypeDef* filter0Instance;
800 #endif /* defined(DFSDM2_Channel0) */
801
802 /* Check parameters */
803 assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance));
804
805 /* Check DFSDM channel state */
806 if(hdfsdm_channel->State != HAL_DFSDM_CHANNEL_STATE_READY)
807 {
808 /* Return error status */
809 status = HAL_ERROR;
810 }
811 else
812 {
813 #if defined(DFSDM2_Channel0)
814
815 /* Get channel counter, channel handle table and channel 0 instance */
816 if(IS_DFSDM1_CHANNEL_INSTANCE(hdfsdm_channel->Instance))
817 {
818 filter0Instance = DFSDM1_Filter0;
819 }
820 else
821 {
822 filter0Instance = DFSDM2_Filter0;
823 }
824
825 /* Stop clock absence detection */
826 hdfsdm_channel->Instance->CHCFGR1 &= ~(DFSDM_CHCFGR1_CKABEN);
827
828 /* Clear clock absence flag */
829 channel = DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance);
830 filter0Instance->FLTICR = (1U << (DFSDM_FLTICR_CLRCKABF_Pos + channel));
831
832 #else
833 /* Stop clock absence detection */
834 hdfsdm_channel->Instance->CHCFGR1 &= ~(DFSDM_CHCFGR1_CKABEN);
835
836 /* Clear clock absence flag */
837 channel = DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance);
838 DFSDM1_Filter0->FLTICR = (1U << (DFSDM_FLTICR_CLRCKABF_Pos + channel));
839 #endif /* DFSDM2_Channel0 */
840 }
841 /* Return function status */
842 return status;
843 }
844
845 /**
846 * @brief This function allows to start clock absence detection in interrupt mode.
847 * @note Same mode has to be used for all channels.
848 * @note If clock is not available on this channel during 5 seconds,
849 * clock absence detection will not be activated and function
850 * will return HAL_TIMEOUT error.
851 * @param hdfsdm_channel DFSDM channel handle.
852 * @retval HAL status
853 */
854 HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStart_IT(DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
855 {
856 HAL_StatusTypeDef status = HAL_OK;
857 uint32_t channel;
858 uint32_t tickstart;
859 #if defined(DFSDM2_Channel0)
860 DFSDM_Filter_TypeDef* filter0Instance;
861 #endif /* defined(DFSDM2_Channel0) */
862
863 /* Check parameters */
864 assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance));
865
866 /* Check DFSDM channel state */
867 if(hdfsdm_channel->State != HAL_DFSDM_CHANNEL_STATE_READY)
868 {
869 /* Return error status */
870 status = HAL_ERROR;
871 }
872 else
873 {
874 #if defined(DFSDM2_Channel0)
875
876 /* Get channel counter, channel handle table and channel 0 instance */
877 if(IS_DFSDM1_CHANNEL_INSTANCE(hdfsdm_channel->Instance))
878 {
879 filter0Instance = DFSDM1_Filter0;
880 }
881 else
882 {
883 filter0Instance = DFSDM2_Filter0;
884 }
885
886 /* Get channel number from channel instance */
887 channel = DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance);
888
889 /* Get timeout */
890 tickstart = HAL_GetTick();
891
892 /* Clear clock absence flag */
893 while((((filter0Instance->FLTISR & DFSDM_FLTISR_CKABF) >> (DFSDM_FLTISR_CKABF_Pos + channel)) & 1U) != 0U)
894 {
895 filter0Instance->FLTICR = (1U << (DFSDM_FLTICR_CLRCKABF_Pos + channel));
896
897 /* Check the Timeout */
898 if((HAL_GetTick()-tickstart) > DFSDM_CKAB_TIMEOUT)
899 {
900 /* Set timeout status */
901 status = HAL_TIMEOUT;
902 break;
903 }
904 }
905
906 if(status == HAL_OK)
907 {
908 /* Activate clock absence detection interrupt */
909 filter0Instance->FLTCR2 |= DFSDM_FLTCR2_CKABIE;
910
911 /* Start clock absence detection */
912 hdfsdm_channel->Instance->CHCFGR1 |= DFSDM_CHCFGR1_CKABEN;
913 }
914 #else
915 /* Get channel number from channel instance */
916 channel = DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance);
917
918 /* Get timeout */
919 tickstart = HAL_GetTick();
920
921 /* Clear clock absence flag */
922 while((((DFSDM1_Filter0->FLTISR & DFSDM_FLTISR_CKABF) >> (DFSDM_FLTISR_CKABF_Pos + channel)) & 1U) != 0U)
923 {
924 DFSDM1_Filter0->FLTICR = (1U << (DFSDM_FLTICR_CLRCKABF_Pos + channel));
925
926 /* Check the Timeout */
927 if((HAL_GetTick()-tickstart) > DFSDM_CKAB_TIMEOUT)
928 {
929 /* Set timeout status */
930 status = HAL_TIMEOUT;
931 break;
932 }
933 }
934
935 if(status == HAL_OK)
936 {
937 /* Activate clock absence detection interrupt */
938 DFSDM1_Filter0->FLTCR2 |= DFSDM_FLTCR2_CKABIE;
939
940 /* Start clock absence detection */
941 hdfsdm_channel->Instance->CHCFGR1 |= DFSDM_CHCFGR1_CKABEN;
942 }
943
944 #endif /* defined(DFSDM2_Channel0) */
945 }
946 /* Return function status */
947 return status;
948 }
949
950 /**
951 * @brief Clock absence detection callback.
952 * @param hdfsdm_channel DFSDM channel handle.
953 * @retval None
954 */
955 __weak void HAL_DFSDM_ChannelCkabCallback(DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
956 {
957 /* Prevent unused argument(s) compilation warning */
958 UNUSED(hdfsdm_channel);
959 /* NOTE : This function should not be modified, when the callback is needed,
960 the HAL_DFSDM_ChannelCkabCallback could be implemented in the user file
961 */
962 }
963
964 /**
965 * @brief This function allows to stop clock absence detection in interrupt mode.
966 * @note Interrupt will be disabled for all channels
967 * @param hdfsdm_channel DFSDM channel handle.
968 * @retval HAL status
969 */
970 HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStop_IT(DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
971 {
972 HAL_StatusTypeDef status = HAL_OK;
973 uint32_t channel;
974 #if defined(DFSDM2_Channel0)
975 DFSDM_Filter_TypeDef* filter0Instance;
976 #endif /* defined(DFSDM2_Channel0) */
977
978 /* Check parameters */
979 assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance));
980
981 /* Check DFSDM channel state */
982 if(hdfsdm_channel->State != HAL_DFSDM_CHANNEL_STATE_READY)
983 {
984 /* Return error status */
985 status = HAL_ERROR;
986 }
987 else
988 {
989 #if defined(DFSDM2_Channel0)
990
991 /* Get channel counter, channel handle table and channel 0 instance */
992 if(IS_DFSDM1_CHANNEL_INSTANCE(hdfsdm_channel->Instance))
993 {
994 filter0Instance = DFSDM1_Filter0;
995 }
996 else
997 {
998 filter0Instance = DFSDM2_Filter0;
999 }
1000
1001 /* Stop clock absence detection */
1002 hdfsdm_channel->Instance->CHCFGR1 &= ~(DFSDM_CHCFGR1_CKABEN);
1003
1004 /* Clear clock absence flag */
1005 channel = DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance);
1006 filter0Instance->FLTICR = (1U << (DFSDM_FLTICR_CLRCKABF_Pos + channel));
1007
1008 /* Disable clock absence detection interrupt */
1009 filter0Instance->FLTCR2 &= ~(DFSDM_FLTCR2_CKABIE);
1010 #else
1011
1012 /* Stop clock absence detection */
1013 hdfsdm_channel->Instance->CHCFGR1 &= ~(DFSDM_CHCFGR1_CKABEN);
1014
1015 /* Clear clock absence flag */
1016 channel = DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance);
1017 DFSDM1_Filter0->FLTICR = (1U << (DFSDM_FLTICR_CLRCKABF_Pos + channel));
1018
1019 /* Disable clock absence detection interrupt */
1020 DFSDM1_Filter0->FLTCR2 &= ~(DFSDM_FLTCR2_CKABIE);
1021 #endif /* DFSDM2_Channel0 */
1022 }
1023
1024 /* Return function status */
1025 return status;
1026 }
1027
1028 /**
1029 * @brief This function allows to start short circuit detection in polling mode.
1030 * @note Same mode has to be used for all channels
1031 * @param hdfsdm_channel DFSDM channel handle.
1032 * @param Threshold Short circuit detector threshold.
1033 * This parameter must be a number between Min_Data = 0 and Max_Data = 255.
1034 * @param BreakSignal Break signals assigned to short circuit event.
1035 * This parameter can be a values combination of @ref DFSDM_BreakSignals.
1036 * @retval HAL status
1037 */
1038 HAL_StatusTypeDef HAL_DFSDM_ChannelScdStart(DFSDM_Channel_HandleTypeDef *hdfsdm_channel,
1039 uint32_t Threshold,
1040 uint32_t BreakSignal)
1041 {
1042 HAL_StatusTypeDef status = HAL_OK;
1043
1044 /* Check parameters */
1045 assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance));
1046 assert_param(IS_DFSDM_CHANNEL_SCD_THRESHOLD(Threshold));
1047 assert_param(IS_DFSDM_BREAK_SIGNALS(BreakSignal));
1048
1049 /* Check DFSDM channel state */
1050 if(hdfsdm_channel->State != HAL_DFSDM_CHANNEL_STATE_READY)
1051 {
1052 /* Return error status */
1053 status = HAL_ERROR;
1054 }
1055 else
1056 {
1057 /* Configure threshold and break signals */
1058 hdfsdm_channel->Instance->CHAWSCDR &= ~(DFSDM_CHAWSCDR_BKSCD | DFSDM_CHAWSCDR_SCDT);
1059 hdfsdm_channel->Instance->CHAWSCDR |= ((BreakSignal << DFSDM_CHAWSCDR_BKSCD_Pos) | \
1060 Threshold);
1061
1062 /* Start short circuit detection */
1063 hdfsdm_channel->Instance->CHCFGR1 |= DFSDM_CHCFGR1_SCDEN;
1064 }
1065 /* Return function status */
1066 return status;
1067 }
1068
1069 /**
1070 * @brief This function allows to poll for the short circuit detection.
1071 * @param hdfsdm_channel DFSDM channel handle.
1072 * @param Timeout Timeout value in milliseconds.
1073 * @retval HAL status
1074 */
1075 HAL_StatusTypeDef HAL_DFSDM_ChannelPollForScd(DFSDM_Channel_HandleTypeDef *hdfsdm_channel,
1076 uint32_t Timeout)
1077 {
1078 uint32_t tickstart;
1079 uint32_t channel;
1080 #if defined(DFSDM2_Channel0)
1081 DFSDM_Filter_TypeDef* filter0Instance;
1082 #endif /* defined(DFSDM2_Channel0) */
1083
1084 /* Check parameters */
1085 assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance));
1086
1087 /* Check DFSDM channel state */
1088 if(hdfsdm_channel->State != HAL_DFSDM_CHANNEL_STATE_READY)
1089 {
1090 /* Return error status */
1091 return HAL_ERROR;
1092 }
1093 else
1094 {
1095 /* Get channel number from channel instance */
1096 channel = DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance);
1097
1098 #if defined(DFSDM2_Channel0)
1099 /* Get channel counter, channel handle table and channel 0 instance */
1100 if(IS_DFSDM1_CHANNEL_INSTANCE(hdfsdm_channel->Instance))
1101 {
1102 filter0Instance = DFSDM1_Filter0;
1103 }
1104 else
1105 {
1106 filter0Instance = DFSDM2_Filter0;
1107 }
1108
1109 /* Get timeout */
1110 tickstart = HAL_GetTick();
1111
1112 /* Wait short circuit detection */
1113 while(((filter0Instance->FLTISR & DFSDM_FLTISR_SCDF) >> (DFSDM_FLTISR_SCDF_Pos + channel)) == 0U)
1114 {
1115 /* Check the Timeout */
1116 if(Timeout != HAL_MAX_DELAY)
1117 {
1118 if((Timeout == 0U) || ((HAL_GetTick()-tickstart) > Timeout))
1119 {
1120 /* Return timeout status */
1121 return HAL_TIMEOUT;
1122 }
1123 }
1124 }
1125
1126 /* Clear short circuit detection flag */
1127 filter0Instance->FLTICR = (1U << (DFSDM_FLTICR_CLRSCSDF_Pos + channel));
1128
1129 #else
1130 /* Get timeout */
1131 tickstart = HAL_GetTick();
1132
1133 /* Wait short circuit detection */
1134 while(((DFSDM1_Filter0->FLTISR & DFSDM_FLTISR_SCDF) >> (DFSDM_FLTISR_SCDF_Pos + channel)) == 0U)
1135 {
1136 /* Check the Timeout */
1137 if(Timeout != HAL_MAX_DELAY)
1138 {
1139 if((Timeout == 0U) || ((HAL_GetTick()-tickstart) > Timeout))
1140 {
1141 /* Return timeout status */
1142 return HAL_TIMEOUT;
1143 }
1144 }
1145 }
1146
1147 /* Clear short circuit detection flag */
1148 DFSDM1_Filter0->FLTICR = (1U << (DFSDM_FLTICR_CLRSCSDF_Pos + channel));
1149 #endif /* DFSDM2_Channel0 */
1150
1151 /* Return function status */
1152 return HAL_OK;
1153 }
1154 }
1155
1156 /**
1157 * @brief This function allows to stop short circuit detection in polling mode.
1158 * @param hdfsdm_channel DFSDM channel handle.
1159 * @retval HAL status
1160 */
1161 HAL_StatusTypeDef HAL_DFSDM_ChannelScdStop(DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
1162 {
1163 HAL_StatusTypeDef status = HAL_OK;
1164 uint32_t channel;
1165 #if defined(DFSDM2_Channel0)
1166 DFSDM_Filter_TypeDef* filter0Instance;
1167 #endif /* defined(DFSDM2_Channel0) */
1168
1169 /* Check parameters */
1170 assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance));
1171
1172 /* Check DFSDM channel state */
1173 if(hdfsdm_channel->State != HAL_DFSDM_CHANNEL_STATE_READY)
1174 {
1175 /* Return error status */
1176 status = HAL_ERROR;
1177 }
1178 else
1179 {
1180 /* Stop short circuit detection */
1181 hdfsdm_channel->Instance->CHCFGR1 &= ~(DFSDM_CHCFGR1_SCDEN);
1182
1183 /* Clear short circuit detection flag */
1184 channel = DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance);
1185
1186 #if defined(DFSDM2_Channel0)
1187 /* Get channel counter, channel handle table and channel 0 instance */
1188 if(IS_DFSDM1_CHANNEL_INSTANCE(hdfsdm_channel->Instance))
1189 {
1190 filter0Instance = DFSDM1_Filter0;
1191 }
1192 else
1193 {
1194 filter0Instance = DFSDM2_Filter0;
1195 }
1196
1197 filter0Instance->FLTICR = (1U << (DFSDM_FLTICR_CLRSCSDF_Pos + channel));
1198 #else
1199 DFSDM1_Filter0->FLTICR = (1U << (DFSDM_FLTICR_CLRSCSDF_Pos + channel));
1200 #endif /* DFSDM2_Channel0*/
1201 }
1202 /* Return function status */
1203 return status;
1204 }
1205
1206 /**
1207 * @brief This function allows to start short circuit detection in interrupt mode.
1208 * @note Same mode has to be used for all channels
1209 * @param hdfsdm_channel DFSDM channel handle.
1210 * @param Threshold Short circuit detector threshold.
1211 * This parameter must be a number between Min_Data = 0 and Max_Data = 255.
1212 * @param BreakSignal Break signals assigned to short circuit event.
1213 * This parameter can be a values combination of @ref DFSDM_BreakSignals.
1214 * @retval HAL status
1215 */
1216 HAL_StatusTypeDef HAL_DFSDM_ChannelScdStart_IT(DFSDM_Channel_HandleTypeDef *hdfsdm_channel,
1217 uint32_t Threshold,
1218 uint32_t BreakSignal)
1219 {
1220 HAL_StatusTypeDef status = HAL_OK;
1221 #if defined(DFSDM2_Channel0)
1222 DFSDM_Filter_TypeDef* filter0Instance;
1223 #endif /* defined(DFSDM2_Channel0) */
1224
1225 /* Check parameters */
1226 assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance));
1227 assert_param(IS_DFSDM_CHANNEL_SCD_THRESHOLD(Threshold));
1228 assert_param(IS_DFSDM_BREAK_SIGNALS(BreakSignal));
1229
1230 /* Check DFSDM channel state */
1231 if(hdfsdm_channel->State != HAL_DFSDM_CHANNEL_STATE_READY)
1232 {
1233 /* Return error status */
1234 status = HAL_ERROR;
1235 }
1236 else
1237 {
1238 #if defined(DFSDM2_Channel0)
1239 /* Get channel counter, channel handle table and channel 0 instance */
1240 if(IS_DFSDM1_CHANNEL_INSTANCE(hdfsdm_channel->Instance))
1241 {
1242 filter0Instance = DFSDM1_Filter0;
1243 }
1244 else
1245 {
1246 filter0Instance = DFSDM2_Filter0;
1247 }
1248 /* Activate short circuit detection interrupt */
1249 filter0Instance->FLTCR2 |= DFSDM_FLTCR2_SCDIE;
1250 #else
1251 /* Activate short circuit detection interrupt */
1252 DFSDM1_Filter0->FLTCR2 |= DFSDM_FLTCR2_SCDIE;
1253 #endif /* DFSDM2_Channel0 */
1254
1255 /* Configure threshold and break signals */
1256 hdfsdm_channel->Instance->CHAWSCDR &= ~(DFSDM_CHAWSCDR_BKSCD | DFSDM_CHAWSCDR_SCDT);
1257 hdfsdm_channel->Instance->CHAWSCDR |= ((BreakSignal << DFSDM_CHAWSCDR_BKSCD_Pos) | \
1258 Threshold);
1259
1260 /* Start short circuit detection */
1261 hdfsdm_channel->Instance->CHCFGR1 |= DFSDM_CHCFGR1_SCDEN;
1262 }
1263 /* Return function status */
1264 return status;
1265 }
1266
1267 /**
1268 * @brief Short circuit detection callback.
1269 * @param hdfsdm_channel DFSDM channel handle.
1270 * @retval None
1271 */
1272 __weak void HAL_DFSDM_ChannelScdCallback(DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
1273 {
1274 /* Prevent unused argument(s) compilation warning */
1275 UNUSED(hdfsdm_channel);
1276 /* NOTE : This function should not be modified, when the callback is needed,
1277 the HAL_DFSDM_ChannelScdCallback could be implemented in the user file
1278 */
1279 }
1280
1281 /**
1282 * @brief This function allows to stop short circuit detection in interrupt mode.
1283 * @note Interrupt will be disabled for all channels
1284 * @param hdfsdm_channel DFSDM channel handle.
1285 * @retval HAL status
1286 */
1287 HAL_StatusTypeDef HAL_DFSDM_ChannelScdStop_IT(DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
1288 {
1289 HAL_StatusTypeDef status = HAL_OK;
1290 uint32_t channel;
1291 #if defined(DFSDM2_Channel0)
1292 DFSDM_Filter_TypeDef* filter0Instance;
1293 #endif /* defined(DFSDM2_Channel0) */
1294
1295 /* Check parameters */
1296 assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance));
1297
1298 /* Check DFSDM channel state */
1299 if(hdfsdm_channel->State != HAL_DFSDM_CHANNEL_STATE_READY)
1300 {
1301 /* Return error status */
1302 status = HAL_ERROR;
1303 }
1304 else
1305 {
1306 /* Stop short circuit detection */
1307 hdfsdm_channel->Instance->CHCFGR1 &= ~(DFSDM_CHCFGR1_SCDEN);
1308
1309 /* Clear short circuit detection flag */
1310 channel = DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance);
1311 #if defined(DFSDM2_Channel0)
1312 /* Get channel counter, channel handle table and channel 0 instance */
1313 if(IS_DFSDM1_CHANNEL_INSTANCE(hdfsdm_channel->Instance))
1314 {
1315 filter0Instance = DFSDM1_Filter0;
1316 }
1317 else
1318 {
1319 filter0Instance = DFSDM2_Filter0;
1320 }
1321
1322 filter0Instance->FLTICR = (1U << (DFSDM_FLTICR_CLRSCSDF_Pos + channel));
1323
1324 /* Disable short circuit detection interrupt */
1325 filter0Instance->FLTCR2 &= ~(DFSDM_FLTCR2_SCDIE);
1326 #else
1327 DFSDM1_Filter0->FLTICR = (1U << (DFSDM_FLTICR_CLRSCSDF_Pos + channel));
1328
1329 /* Disable short circuit detection interrupt */
1330 DFSDM1_Filter0->FLTCR2 &= ~(DFSDM_FLTCR2_SCDIE);
1331 #endif /* DFSDM2_Channel0 */
1332 }
1333 /* Return function status */
1334 return status;
1335 }
1336
1337 /**
1338 * @brief This function allows to get channel analog watchdog value.
1339 * @param hdfsdm_channel DFSDM channel handle.
1340 * @retval Channel analog watchdog value.
1341 */
1342 int16_t HAL_DFSDM_ChannelGetAwdValue(DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
1343 {
1344 return (int16_t) hdfsdm_channel->Instance->CHWDATAR;
1345 }
1346
1347 /**
1348 * @brief This function allows to modify channel offset value.
1349 * @param hdfsdm_channel DFSDM channel handle.
1350 * @param Offset DFSDM channel offset.
1351 * This parameter must be a number between Min_Data = -8388608 and Max_Data = 8388607.
1352 * @retval HAL status.
1353 */
1354 HAL_StatusTypeDef HAL_DFSDM_ChannelModifyOffset(DFSDM_Channel_HandleTypeDef *hdfsdm_channel,
1355 int32_t Offset)
1356 {
1357 HAL_StatusTypeDef status = HAL_OK;
1358
1359 /* Check parameters */
1360 assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance));
1361 assert_param(IS_DFSDM_CHANNEL_OFFSET(Offset));
1362
1363 /* Check DFSDM channel state */
1364 if(hdfsdm_channel->State != HAL_DFSDM_CHANNEL_STATE_READY)
1365 {
1366 /* Return error status */
1367 status = HAL_ERROR;
1368 }
1369 else
1370 {
1371 /* Modify channel offset */
1372 hdfsdm_channel->Instance->CHCFGR2 &= ~(DFSDM_CHCFGR2_OFFSET);
1373 hdfsdm_channel->Instance->CHCFGR2 |= ((uint32_t) Offset << DFSDM_CHCFGR2_OFFSET_Pos);
1374 }
1375 /* Return function status */
1376 return status;
1377 }
1378
1379 /**
1380 * @}
1381 */
1382
1383 /** @defgroup DFSDM_Exported_Functions_Group3_Channel Channel state function
1384 * @brief Channel state function
1385 *
1386 @verbatim
1387 ==============================================================================
1388 ##### Channel state function #####
1389 ==============================================================================
1390 [..] This section provides function allowing to:
1391 (+) Get channel handle state.
1392 @endverbatim
1393 * @{
1394 */
1395
1396 /**
1397 * @brief This function allows to get the current DFSDM channel handle state.
1398 * @param hdfsdm_channel DFSDM channel handle.
1399 * @retval DFSDM channel state.
1400 */
1401 HAL_DFSDM_Channel_StateTypeDef HAL_DFSDM_ChannelGetState(DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
1402 {
1403 /* Return DFSDM channel handle state */
1404 return hdfsdm_channel->State;
1405 }
1406
1407 /**
1408 * @}
1409 */
1410
1411 /** @defgroup DFSDM_Exported_Functions_Group1_Filter Filter initialization and de-initialization functions
1412 * @brief Filter initialization and de-initialization functions
1413 *
1414 @verbatim
1415 ==============================================================================
1416 ##### Filter initialization and de-initialization functions #####
1417 ==============================================================================
1418 [..] This section provides functions allowing to:
1419 (+) Initialize the DFSDM filter.
1420 (+) De-initialize the DFSDM filter.
1421 @endverbatim
1422 * @{
1423 */
1424
1425 /**
1426 * @brief Initialize the DFSDM filter according to the specified parameters
1427 * in the DFSDM_FilterInitTypeDef structure and initialize the associated handle.
1428 * @param hdfsdm_filter DFSDM filter handle.
1429 * @retval HAL status.
1430 */
1431 HAL_StatusTypeDef HAL_DFSDM_FilterInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
1432 {
1433 /* Check DFSDM Channel handle */
1434 if(hdfsdm_filter == NULL)
1435 {
1436 return HAL_ERROR;
1437 }
1438
1439 /* Check parameters */
1440 assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
1441 assert_param(IS_DFSDM_FILTER_REG_TRIGGER(hdfsdm_filter->Init.RegularParam.Trigger));
1442 assert_param(IS_FUNCTIONAL_STATE(hdfsdm_filter->Init.RegularParam.FastMode));
1443 assert_param(IS_FUNCTIONAL_STATE(hdfsdm_filter->Init.RegularParam.DmaMode));
1444 assert_param(IS_DFSDM_FILTER_INJ_TRIGGER(hdfsdm_filter->Init.InjectedParam.Trigger));
1445 assert_param(IS_FUNCTIONAL_STATE(hdfsdm_filter->Init.InjectedParam.ScanMode));
1446 assert_param(IS_FUNCTIONAL_STATE(hdfsdm_filter->Init.InjectedParam.DmaMode));
1447 assert_param(IS_DFSDM_FILTER_SINC_ORDER(hdfsdm_filter->Init.FilterParam.SincOrder));
1448 assert_param(IS_DFSDM_FILTER_OVS_RATIO(hdfsdm_filter->Init.FilterParam.Oversampling));
1449 assert_param(IS_DFSDM_FILTER_INTEGRATOR_OVS_RATIO(hdfsdm_filter->Init.FilterParam.IntOversampling));
1450
1451 /* Check parameters compatibility */
1452 if((hdfsdm_filter->Instance == DFSDM1_Filter0) &&
1453 ((hdfsdm_filter->Init.RegularParam.Trigger == DFSDM_FILTER_SYNC_TRIGGER) ||
1454 (hdfsdm_filter->Init.InjectedParam.Trigger == DFSDM_FILTER_SYNC_TRIGGER)))
1455 {
1456 return HAL_ERROR;
1457 }
1458 #if defined (DFSDM2_Channel0)
1459 if((hdfsdm_filter->Instance == DFSDM2_Filter0) &&
1460 ((hdfsdm_filter->Init.RegularParam.Trigger == DFSDM_FILTER_SYNC_TRIGGER) ||
1461 (hdfsdm_filter->Init.InjectedParam.Trigger == DFSDM_FILTER_SYNC_TRIGGER)))
1462 {
1463 return HAL_ERROR;
1464 }
1465 #endif /* DFSDM2_Channel0 */
1466
1467 /* Initialize DFSDM filter variables with default values */
1468 hdfsdm_filter->RegularContMode = DFSDM_CONTINUOUS_CONV_OFF;
1469 hdfsdm_filter->InjectedChannelsNbr = 1U;
1470 hdfsdm_filter->InjConvRemaining = 1U;
1471 hdfsdm_filter->ErrorCode = DFSDM_FILTER_ERROR_NONE;
1472
1473 /* Call MSP init function */
1474 HAL_DFSDM_FilterMspInit(hdfsdm_filter);
1475
1476 /* Set regular parameters */
1477 hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_RSYNC);
1478 if(hdfsdm_filter->Init.RegularParam.FastMode == ENABLE)
1479 {
1480 hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_FAST;
1481 }
1482 else
1483 {
1484 hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_FAST);
1485 }
1486
1487 if(hdfsdm_filter->Init.RegularParam.DmaMode == ENABLE)
1488 {
1489 hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_RDMAEN;
1490 }
1491 else
1492 {
1493 hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_RDMAEN);
1494 }
1495
1496 /* Set injected parameters */
1497 hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_JSYNC | DFSDM_FLTCR1_JEXTEN | DFSDM_FLTCR1_JEXTSEL);
1498 if(hdfsdm_filter->Init.InjectedParam.Trigger == DFSDM_FILTER_EXT_TRIGGER)
1499 {
1500 assert_param(IS_DFSDM_FILTER_EXT_TRIG(hdfsdm_filter->Init.InjectedParam.ExtTrigger));
1501 assert_param(IS_DFSDM_FILTER_EXT_TRIG_EDGE(hdfsdm_filter->Init.InjectedParam.ExtTriggerEdge));
1502 hdfsdm_filter->Instance->FLTCR1 |= (hdfsdm_filter->Init.InjectedParam.ExtTrigger);
1503 }
1504
1505 if(hdfsdm_filter->Init.InjectedParam.ScanMode == ENABLE)
1506 {
1507 hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_JSCAN;
1508 }
1509 else
1510 {
1511 hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_JSCAN);
1512 }
1513
1514 if(hdfsdm_filter->Init.InjectedParam.DmaMode == ENABLE)
1515 {
1516 hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_JDMAEN;
1517 }
1518 else
1519 {
1520 hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_JDMAEN);
1521 }
1522
1523 /* Set filter parameters */
1524 hdfsdm_filter->Instance->FLTFCR &= ~(DFSDM_FLTFCR_FORD | DFSDM_FLTFCR_FOSR | DFSDM_FLTFCR_IOSR);
1525 hdfsdm_filter->Instance->FLTFCR |= (hdfsdm_filter->Init.FilterParam.SincOrder |
1526 ((hdfsdm_filter->Init.FilterParam.Oversampling - 1U) << DFSDM_FLTFCR_FOSR_Pos) |
1527 (hdfsdm_filter->Init.FilterParam.IntOversampling - 1U));
1528
1529 /* Store regular and injected triggers and injected scan mode*/
1530 hdfsdm_filter->RegularTrigger = hdfsdm_filter->Init.RegularParam.Trigger;
1531 hdfsdm_filter->InjectedTrigger = hdfsdm_filter->Init.InjectedParam.Trigger;
1532 hdfsdm_filter->ExtTriggerEdge = hdfsdm_filter->Init.InjectedParam.ExtTriggerEdge;
1533 hdfsdm_filter->InjectedScanMode = hdfsdm_filter->Init.InjectedParam.ScanMode;
1534
1535 /* Enable DFSDM filter */
1536 hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_DFEN;
1537
1538 /* Set DFSDM filter to ready state */
1539 hdfsdm_filter->State = HAL_DFSDM_FILTER_STATE_READY;
1540
1541 return HAL_OK;
1542 }
1543
1544 /**
1545 * @brief De-initializes the DFSDM filter.
1546 * @param hdfsdm_filter DFSDM filter handle.
1547 * @retval HAL status.
1548 */
1549 HAL_StatusTypeDef HAL_DFSDM_FilterDeInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
1550 {
1551 /* Check DFSDM filter handle */
1552 if(hdfsdm_filter == NULL)
1553 {
1554 return HAL_ERROR;
1555 }
1556
1557 /* Check parameters */
1558 assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
1559
1560 /* Disable the DFSDM filter */
1561 hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_DFEN);
1562
1563 /* Call MSP deinit function */
1564 HAL_DFSDM_FilterMspDeInit(hdfsdm_filter);
1565
1566 /* Set DFSDM filter in reset state */
1567 hdfsdm_filter->State = HAL_DFSDM_FILTER_STATE_RESET;
1568
1569 return HAL_OK;
1570 }
1571
1572 /**
1573 * @brief Initializes the DFSDM filter MSP.
1574 * @param hdfsdm_filter DFSDM filter handle.
1575 * @retval None
1576 */
1577 __weak void HAL_DFSDM_FilterMspInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
1578 {
1579 /* Prevent unused argument(s) compilation warning */
1580 UNUSED(hdfsdm_filter);
1581 /* NOTE : This function should not be modified, when the function is needed,
1582 the HAL_DFSDM_FilterMspInit could be implemented in the user file.
1583 */
1584 }
1585
1586 /**
1587 * @brief De-initializes the DFSDM filter MSP.
1588 * @param hdfsdm_filter DFSDM filter handle.
1589 * @retval None
1590 */
1591 __weak void HAL_DFSDM_FilterMspDeInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
1592 {
1593 /* Prevent unused argument(s) compilation warning */
1594 UNUSED(hdfsdm_filter);
1595 /* NOTE : This function should not be modified, when the function is needed,
1596 the HAL_DFSDM_FilterMspDeInit could be implemented in the user file.
1597 */
1598 }
1599
1600 /**
1601 * @}
1602 */
1603
1604 /** @defgroup DFSDM_Exported_Functions_Group2_Filter Filter control functions
1605 * @brief Filter control functions
1606 *
1607 @verbatim
1608 ==============================================================================
1609 ##### Filter control functions #####
1610 ==============================================================================
1611 [..] This section provides functions allowing to:
1612 (+) Select channel and enable/disable continuous mode for regular conversion.
1613 (+) Select channels for injected conversion.
1614 @endverbatim
1615 * @{
1616 */
1617
1618 /**
1619 * @brief This function allows to select channel and to enable/disable
1620 * continuous mode for regular conversion.
1621 * @param hdfsdm_filter DFSDM filter handle.
1622 * @param Channel Channel for regular conversion.
1623 * This parameter can be a value of @ref DFSDM_Channel_Selection.
1624 * @param ContinuousMode Enable/disable continuous mode for regular conversion.
1625 * This parameter can be a value of @ref DFSDM_ContinuousMode.
1626 * @retval HAL status
1627 */
1628 HAL_StatusTypeDef HAL_DFSDM_FilterConfigRegChannel(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
1629 uint32_t Channel,
1630 uint32_t ContinuousMode)
1631 {
1632 HAL_StatusTypeDef status = HAL_OK;
1633
1634 /* Check parameters */
1635 assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
1636 assert_param(IS_DFSDM_REGULAR_CHANNEL(Channel));
1637 assert_param(IS_DFSDM_CONTINUOUS_MODE(ContinuousMode));
1638
1639 /* Check DFSDM filter state */
1640 if((hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_RESET) &&
1641 (hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_ERROR))
1642 {
1643 /* Configure channel and continuous mode for regular conversion */
1644 hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_RCH | DFSDM_FLTCR1_RCONT);
1645 if(ContinuousMode == DFSDM_CONTINUOUS_CONV_ON)
1646 {
1647 hdfsdm_filter->Instance->FLTCR1 |= (uint32_t) (((Channel & DFSDM_MSB_MASK) << DFSDM_FLTCR1_MSB_RCH_OFFSET) |
1648 DFSDM_FLTCR1_RCONT);
1649 }
1650 else
1651 {
1652 hdfsdm_filter->Instance->FLTCR1 |= (uint32_t) ((Channel & DFSDM_MSB_MASK) << DFSDM_FLTCR1_MSB_RCH_OFFSET);
1653 }
1654 /* Store continuous mode information */
1655 hdfsdm_filter->RegularContMode = ContinuousMode;
1656 }
1657 else
1658 {
1659 status = HAL_ERROR;
1660 }
1661
1662 /* Return function status */
1663 return status;
1664 }
1665
1666 /**
1667 * @brief This function allows to select channels for injected conversion.
1668 * @param hdfsdm_filter DFSDM filter handle.
1669 * @param Channel Channels for injected conversion.
1670 * This parameter can be a values combination of @ref DFSDM_Channel_Selection.
1671 * @retval HAL status
1672 */
1673 HAL_StatusTypeDef HAL_DFSDM_FilterConfigInjChannel(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
1674 uint32_t Channel)
1675 {
1676 HAL_StatusTypeDef status = HAL_OK;
1677
1678 /* Check parameters */
1679 assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
1680 assert_param(IS_DFSDM_INJECTED_CHANNEL(Channel));
1681
1682 /* Check DFSDM filter state */
1683 if((hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_RESET) &&
1684 (hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_ERROR))
1685 {
1686 /* Configure channel for injected conversion */
1687 hdfsdm_filter->Instance->FLTJCHGR = (uint32_t) (Channel & DFSDM_LSB_MASK);
1688 /* Store number of injected channels */
1689 hdfsdm_filter->InjectedChannelsNbr = DFSDM_GetInjChannelsNbr(Channel);
1690 /* Update number of injected channels remaining */
1691 hdfsdm_filter->InjConvRemaining = (hdfsdm_filter->InjectedScanMode == ENABLE) ? \
1692 hdfsdm_filter->InjectedChannelsNbr : 1U;
1693 }
1694 else
1695 {
1696 status = HAL_ERROR;
1697 }
1698 /* Return function status */
1699 return status;
1700 }
1701
1702 /**
1703 * @}
1704 */
1705
1706 /** @defgroup DFSDM_Exported_Functions_Group3_Filter Filter operation functions
1707 * @brief Filter operation functions
1708 *
1709 @verbatim
1710 ==============================================================================
1711 ##### Filter operation functions #####
1712 ==============================================================================
1713 [..] This section provides functions allowing to:
1714 (+) Start conversion of regular/injected channel.
1715 (+) Poll for the end of regular/injected conversion.
1716 (+) Stop conversion of regular/injected channel.
1717 (+) Start conversion of regular/injected channel and enable interrupt.
1718 (+) Call the callback functions at the end of regular/injected conversions.
1719 (+) Stop conversion of regular/injected channel and disable interrupt.
1720 (+) Start conversion of regular/injected channel and enable DMA transfer.
1721 (+) Stop conversion of regular/injected channel and disable DMA transfer.
1722 (+) Start analog watchdog and enable interrupt.
1723 (+) Call the callback function when analog watchdog occurs.
1724 (+) Stop analog watchdog and disable interrupt.
1725 (+) Start extreme detector.
1726 (+) Stop extreme detector.
1727 (+) Get result of regular channel conversion.
1728 (+) Get result of injected channel conversion.
1729 (+) Get extreme detector maximum and minimum values.
1730 (+) Get conversion time.
1731 (+) Handle DFSDM interrupt request.
1732 @endverbatim
1733 * @{
1734 */
1735
1736 /**
1737 * @brief This function allows to start regular conversion in polling mode.
1738 * @note This function should be called only when DFSDM filter instance is
1739 * in idle state or if injected conversion is ongoing.
1740 * @param hdfsdm_filter DFSDM filter handle.
1741 * @retval HAL status
1742 */
1743 HAL_StatusTypeDef HAL_DFSDM_FilterRegularStart(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
1744 {
1745 HAL_StatusTypeDef status = HAL_OK;
1746
1747 /* Check parameters */
1748 assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
1749
1750 /* Check DFSDM filter state */
1751 if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_READY) || \
1752 (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_INJ))
1753 {
1754 /* Start regular conversion */
1755 DFSDM_RegConvStart(hdfsdm_filter);
1756 }
1757 else
1758 {
1759 status = HAL_ERROR;
1760 }
1761 /* Return function status */
1762 return status;
1763 }
1764
1765 /**
1766 * @brief This function allows to poll for the end of regular conversion.
1767 * @note This function should be called only if regular conversion is ongoing.
1768 * @param hdfsdm_filter DFSDM filter handle.
1769 * @param Timeout Timeout value in milliseconds.
1770 * @retval HAL status
1771 */
1772 HAL_StatusTypeDef HAL_DFSDM_FilterPollForRegConversion(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
1773 uint32_t Timeout)
1774 {
1775 uint32_t tickstart;
1776
1777 /* Check parameters */
1778 assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
1779
1780 /* Check DFSDM filter state */
1781 if((hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG) && \
1782 (hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG_INJ))
1783 {
1784 /* Return error status */
1785 return HAL_ERROR;
1786 }
1787 else
1788 {
1789 /* Get timeout */
1790 tickstart = HAL_GetTick();
1791
1792 /* Wait end of regular conversion */
1793 while((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_REOCF) != DFSDM_FLTISR_REOCF)
1794 {
1795 /* Check the Timeout */
1796 if(Timeout != HAL_MAX_DELAY)
1797 {
1798 if((Timeout == 0U) || ((HAL_GetTick()-tickstart) > Timeout))
1799 {
1800 /* Return timeout status */
1801 return HAL_TIMEOUT;
1802 }
1803 }
1804 }
1805 /* Check if overrun occurs */
1806 if((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_ROVRF) == DFSDM_FLTISR_ROVRF)
1807 {
1808 /* Update error code and call error callback */
1809 hdfsdm_filter->ErrorCode = DFSDM_FILTER_ERROR_REGULAR_OVERRUN;
1810 HAL_DFSDM_FilterErrorCallback(hdfsdm_filter);
1811
1812 /* Clear regular overrun flag */
1813 hdfsdm_filter->Instance->FLTICR = DFSDM_FLTICR_CLRROVRF;
1814 }
1815 /* Update DFSDM filter state only if not continuous conversion and SW trigger */
1816 if((hdfsdm_filter->RegularContMode == DFSDM_CONTINUOUS_CONV_OFF) && \
1817 (hdfsdm_filter->RegularTrigger == DFSDM_FILTER_SW_TRIGGER))
1818 {
1819 hdfsdm_filter->State = (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_REG) ? \
1820 HAL_DFSDM_FILTER_STATE_READY : HAL_DFSDM_FILTER_STATE_INJ;
1821 }
1822 /* Return function status */
1823 return HAL_OK;
1824 }
1825 }
1826
1827 /**
1828 * @brief This function allows to stop regular conversion in polling mode.
1829 * @note This function should be called only if regular conversion is ongoing.
1830 * @param hdfsdm_filter DFSDM filter handle.
1831 * @retval HAL status
1832 */
1833 HAL_StatusTypeDef HAL_DFSDM_FilterRegularStop(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
1834 {
1835 HAL_StatusTypeDef status = HAL_OK;
1836
1837 /* Check parameters */
1838 assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
1839
1840 /* Check DFSDM filter state */
1841 if((hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG) && \
1842 (hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG_INJ))
1843 {
1844 /* Return error status */
1845 status = HAL_ERROR;
1846 }
1847 else
1848 {
1849 /* Stop regular conversion */
1850 DFSDM_RegConvStop(hdfsdm_filter);
1851 }
1852 /* Return function status */
1853 return status;
1854 }
1855
1856 /**
1857 * @brief This function allows to start regular conversion in interrupt mode.
1858 * @note This function should be called only when DFSDM filter instance is
1859 * in idle state or if injected conversion is ongoing.
1860 * @param hdfsdm_filter DFSDM filter handle.
1861 * @retval HAL status
1862 */
1863 HAL_StatusTypeDef HAL_DFSDM_FilterRegularStart_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
1864 {
1865 HAL_StatusTypeDef status = HAL_OK;
1866
1867 /* Check parameters */
1868 assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
1869
1870 /* Check DFSDM filter state */
1871 if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_READY) || \
1872 (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_INJ))
1873 {
1874 /* Enable interrupts for regular conversions */
1875 hdfsdm_filter->Instance->FLTCR2 |= (DFSDM_FLTCR2_REOCIE | DFSDM_FLTCR2_ROVRIE);
1876
1877 /* Start regular conversion */
1878 DFSDM_RegConvStart(hdfsdm_filter);
1879 }
1880 else
1881 {
1882 status = HAL_ERROR;
1883 }
1884 /* Return function status */
1885 return status;
1886 }
1887
1888 /**
1889 * @brief This function allows to stop regular conversion in interrupt mode.
1890 * @note This function should be called only if regular conversion is ongoing.
1891 * @param hdfsdm_filter DFSDM filter handle.
1892 * @retval HAL status
1893 */
1894 HAL_StatusTypeDef HAL_DFSDM_FilterRegularStop_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
1895 {
1896 HAL_StatusTypeDef status = HAL_OK;
1897
1898 /* Check parameters */
1899 assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
1900
1901 /* Check DFSDM filter state */
1902 if((hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG) && \
1903 (hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG_INJ))
1904 {
1905 /* Return error status */
1906 status = HAL_ERROR;
1907 }
1908 else
1909 {
1910 /* Disable interrupts for regular conversions */
1911 hdfsdm_filter->Instance->FLTCR2 &= ~(DFSDM_FLTCR2_REOCIE | DFSDM_FLTCR2_ROVRIE);
1912
1913 /* Stop regular conversion */
1914 DFSDM_RegConvStop(hdfsdm_filter);
1915 }
1916 /* Return function status */
1917 return status;
1918 }
1919
1920 /**
1921 * @brief This function allows to start regular conversion in DMA mode.
1922 * @note This function should be called only when DFSDM filter instance is
1923 * in idle state or if injected conversion is ongoing.
1924 * Please note that data on buffer will contain signed regular conversion
1925 * value on 24 most significant bits and corresponding channel on 3 least
1926 * significant bits.
1927 * @param hdfsdm_filter DFSDM filter handle.
1928 * @param pData The destination buffer address.
1929 * @param Length The length of data to be transferred from DFSDM filter to memory.
1930 * @retval HAL status
1931 */
1932 HAL_StatusTypeDef HAL_DFSDM_FilterRegularStart_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
1933 int32_t *pData,
1934 uint32_t Length)
1935 {
1936 HAL_StatusTypeDef status = HAL_OK;
1937
1938 /* Check parameters */
1939 assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
1940
1941 /* Check destination address and length */
1942 if((pData == NULL) || (Length == 0U))
1943 {
1944 status = HAL_ERROR;
1945 }
1946 /* Check that DMA is enabled for regular conversion */
1947 else if((hdfsdm_filter->Instance->FLTCR1 & DFSDM_FLTCR1_RDMAEN) != DFSDM_FLTCR1_RDMAEN)
1948 {
1949 status = HAL_ERROR;
1950 }
1951 /* Check parameters compatibility */
1952 else if((hdfsdm_filter->RegularTrigger == DFSDM_FILTER_SW_TRIGGER) && \
1953 (hdfsdm_filter->RegularContMode == DFSDM_CONTINUOUS_CONV_OFF) && \
1954 (hdfsdm_filter->hdmaReg->Init.Mode == DMA_NORMAL) && \
1955 (Length != 1U))
1956 {
1957 status = HAL_ERROR;
1958 }
1959 else if((hdfsdm_filter->RegularTrigger == DFSDM_FILTER_SW_TRIGGER) && \
1960 (hdfsdm_filter->RegularContMode == DFSDM_CONTINUOUS_CONV_OFF) && \
1961 (hdfsdm_filter->hdmaReg->Init.Mode == DMA_CIRCULAR))
1962 {
1963 status = HAL_ERROR;
1964 }
1965 /* Check DFSDM filter state */
1966 else if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_READY) || \
1967 (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_INJ))
1968 {
1969 /* Set callbacks on DMA handler */
1970 hdfsdm_filter->hdmaReg->XferCpltCallback = DFSDM_DMARegularConvCplt;
1971 hdfsdm_filter->hdmaReg->XferErrorCallback = DFSDM_DMAError;
1972 hdfsdm_filter->hdmaReg->XferHalfCpltCallback = (hdfsdm_filter->hdmaReg->Init.Mode == DMA_CIRCULAR) ?\
1973 DFSDM_DMARegularHalfConvCplt : NULL;
1974
1975 /* Start DMA in interrupt mode */
1976 if(HAL_DMA_Start_IT(hdfsdm_filter->hdmaReg, (uint32_t)&hdfsdm_filter->Instance->FLTRDATAR, \
1977 (uint32_t) pData, Length) != HAL_OK)
1978 {
1979 /* Set DFSDM filter in error state */
1980 hdfsdm_filter->State = HAL_DFSDM_FILTER_STATE_ERROR;
1981 status = HAL_ERROR;
1982 }
1983 else
1984 {
1985 /* Start regular conversion */
1986 DFSDM_RegConvStart(hdfsdm_filter);
1987 }
1988 }
1989 else
1990 {
1991 status = HAL_ERROR;
1992 }
1993 /* Return function status */
1994 return status;
1995 }
1996
1997 /**
1998 * @brief This function allows to start regular conversion in DMA mode and to get
1999 * only the 16 most significant bits of conversion.
2000 * @note This function should be called only when DFSDM filter instance is
2001 * in idle state or if injected conversion is ongoing.
2002 * Please note that data on buffer will contain signed 16 most significant
2003 * bits of regular conversion.
2004 * @param hdfsdm_filter DFSDM filter handle.
2005 * @param pData The destination buffer address.
2006 * @param Length The length of data to be transferred from DFSDM filter to memory.
2007 * @retval HAL status
2008 */
2009 HAL_StatusTypeDef HAL_DFSDM_FilterRegularMsbStart_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
2010 int16_t *pData,
2011 uint32_t Length)
2012 {
2013 HAL_StatusTypeDef status = HAL_OK;
2014
2015 /* Check parameters */
2016 assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
2017
2018 /* Check destination address and length */
2019 if((pData == NULL) || (Length == 0U))
2020 {
2021 status = HAL_ERROR;
2022 }
2023 /* Check that DMA is enabled for regular conversion */
2024 else if((hdfsdm_filter->Instance->FLTCR1 & DFSDM_FLTCR1_RDMAEN) != DFSDM_FLTCR1_RDMAEN)
2025 {
2026 status = HAL_ERROR;
2027 }
2028 /* Check parameters compatibility */
2029 else if((hdfsdm_filter->RegularTrigger == DFSDM_FILTER_SW_TRIGGER) && \
2030 (hdfsdm_filter->RegularContMode == DFSDM_CONTINUOUS_CONV_OFF) && \
2031 (hdfsdm_filter->hdmaReg->Init.Mode == DMA_NORMAL) && \
2032 (Length != 1U))
2033 {
2034 status = HAL_ERROR;
2035 }
2036 else if((hdfsdm_filter->RegularTrigger == DFSDM_FILTER_SW_TRIGGER) && \
2037 (hdfsdm_filter->RegularContMode == DFSDM_CONTINUOUS_CONV_OFF) && \
2038 (hdfsdm_filter->hdmaReg->Init.Mode == DMA_CIRCULAR))
2039 {
2040 status = HAL_ERROR;
2041 }
2042 /* Check DFSDM filter state */
2043 else if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_READY) || \
2044 (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_INJ))
2045 {
2046 /* Set callbacks on DMA handler */
2047 hdfsdm_filter->hdmaReg->XferCpltCallback = DFSDM_DMARegularConvCplt;
2048 hdfsdm_filter->hdmaReg->XferErrorCallback = DFSDM_DMAError;
2049 hdfsdm_filter->hdmaReg->XferHalfCpltCallback = (hdfsdm_filter->hdmaReg->Init.Mode == DMA_CIRCULAR) ?\
2050 DFSDM_DMARegularHalfConvCplt : NULL;
2051
2052 /* Start DMA in interrupt mode */
2053 if(HAL_DMA_Start_IT(hdfsdm_filter->hdmaReg, (uint32_t)(&hdfsdm_filter->Instance->FLTRDATAR) + 2U, \
2054 (uint32_t) pData, Length) != HAL_OK)
2055 {
2056 /* Set DFSDM filter in error state */
2057 hdfsdm_filter->State = HAL_DFSDM_FILTER_STATE_ERROR;
2058 status = HAL_ERROR;
2059 }
2060 else
2061 {
2062 /* Start regular conversion */
2063 DFSDM_RegConvStart(hdfsdm_filter);
2064 }
2065 }
2066 else
2067 {
2068 status = HAL_ERROR;
2069 }
2070 /* Return function status */
2071 return status;
2072 }
2073
2074 /**
2075 * @brief This function allows to stop regular conversion in DMA mode.
2076 * @note This function should be called only if regular conversion is ongoing.
2077 * @param hdfsdm_filter DFSDM filter handle.
2078 * @retval HAL status
2079 */
2080 HAL_StatusTypeDef HAL_DFSDM_FilterRegularStop_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
2081 {
2082 HAL_StatusTypeDef status = HAL_OK;
2083
2084 /* Check parameters */
2085 assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
2086
2087 /* Check DFSDM filter state */
2088 if((hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG) && \
2089 (hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG_INJ))
2090 {
2091 /* Return error status */
2092 status = HAL_ERROR;
2093 }
2094 else
2095 {
2096 /* Stop current DMA transfer */
2097 if(HAL_DMA_Abort(hdfsdm_filter->hdmaReg) != HAL_OK)
2098 {
2099 /* Set DFSDM filter in error state */
2100 hdfsdm_filter->State = HAL_DFSDM_FILTER_STATE_ERROR;
2101 status = HAL_ERROR;
2102 }
2103 else
2104 {
2105 /* Stop regular conversion */
2106 DFSDM_RegConvStop(hdfsdm_filter);
2107 }
2108 }
2109 /* Return function status */
2110 return status;
2111 }
2112
2113 /**
2114 * @brief This function allows to get regular conversion value.
2115 * @param hdfsdm_filter DFSDM filter handle.
2116 * @param Channel Corresponding channel of regular conversion.
2117 * @retval Regular conversion value
2118 */
2119 int32_t HAL_DFSDM_FilterGetRegularValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
2120 uint32_t *Channel)
2121 {
2122 uint32_t reg = 0U;
2123 int32_t value = 0;
2124
2125 /* Check parameters */
2126 assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
2127 assert_param(Channel != NULL);
2128
2129 /* Get value of data register for regular channel */
2130 reg = hdfsdm_filter->Instance->FLTRDATAR;
2131
2132 /* Extract channel and regular conversion value */
2133 *Channel = (reg & DFSDM_FLTRDATAR_RDATACH);
2134 value = ((int32_t)(reg & DFSDM_FLTRDATAR_RDATA) >> DFSDM_FLTRDATAR_RDATA_Pos);
2135
2136 /* return regular conversion value */
2137 return value;
2138 }
2139
2140 /**
2141 * @brief This function allows to start injected conversion in polling mode.
2142 * @note This function should be called only when DFSDM filter instance is
2143 * in idle state or if regular conversion is ongoing.
2144 * @param hdfsdm_filter DFSDM filter handle.
2145 * @retval HAL status
2146 */
2147 HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStart(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
2148 {
2149 HAL_StatusTypeDef status = HAL_OK;
2150
2151 /* Check parameters */
2152 assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
2153
2154 /* Check DFSDM filter state */
2155 if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_READY) || \
2156 (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_REG))
2157 {
2158 /* Start injected conversion */
2159 DFSDM_InjConvStart(hdfsdm_filter);
2160 }
2161 else
2162 {
2163 status = HAL_ERROR;
2164 }
2165 /* Return function status */
2166 return status;
2167 }
2168
2169 /**
2170 * @brief This function allows to poll for the end of injected conversion.
2171 * @note This function should be called only if injected conversion is ongoing.
2172 * @param hdfsdm_filter DFSDM filter handle.
2173 * @param Timeout Timeout value in milliseconds.
2174 * @retval HAL status
2175 */
2176 HAL_StatusTypeDef HAL_DFSDM_FilterPollForInjConversion(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
2177 uint32_t Timeout)
2178 {
2179 uint32_t tickstart;
2180
2181 /* Check parameters */
2182 assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
2183
2184 /* Check DFSDM filter state */
2185 if((hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_INJ) && \
2186 (hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG_INJ))
2187 {
2188 /* Return error status */
2189 return HAL_ERROR;
2190 }
2191 else
2192 {
2193 /* Get timeout */
2194 tickstart = HAL_GetTick();
2195
2196 /* Wait end of injected conversions */
2197 while((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_JEOCF) != DFSDM_FLTISR_JEOCF)
2198 {
2199 /* Check the Timeout */
2200 if(Timeout != HAL_MAX_DELAY)
2201 {
2202 if((Timeout == 0U) || ((HAL_GetTick()-tickstart) > Timeout))
2203 {
2204 /* Return timeout status */
2205 return HAL_TIMEOUT;
2206 }
2207 }
2208 }
2209 /* Check if overrun occurs */
2210 if((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_JOVRF) == DFSDM_FLTISR_JOVRF)
2211 {
2212 /* Update error code and call error callback */
2213 hdfsdm_filter->ErrorCode = DFSDM_FILTER_ERROR_INJECTED_OVERRUN;
2214 HAL_DFSDM_FilterErrorCallback(hdfsdm_filter);
2215
2216 /* Clear injected overrun flag */
2217 hdfsdm_filter->Instance->FLTICR = DFSDM_FLTICR_CLRJOVRF;
2218 }
2219
2220 /* Update remaining injected conversions */
2221 hdfsdm_filter->InjConvRemaining--;
2222 if(hdfsdm_filter->InjConvRemaining == 0U)
2223 {
2224 /* Update DFSDM filter state only if trigger is software */
2225 if(hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_SW_TRIGGER)
2226 {
2227 hdfsdm_filter->State = (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_INJ) ? \
2228 HAL_DFSDM_FILTER_STATE_READY : HAL_DFSDM_FILTER_STATE_REG;
2229 }
2230
2231 /* end of injected sequence, reset the value */
2232 hdfsdm_filter->InjConvRemaining = (hdfsdm_filter->InjectedScanMode == ENABLE) ? \
2233 hdfsdm_filter->InjectedChannelsNbr : 1U;
2234 }
2235
2236 /* Return function status */
2237 return HAL_OK;
2238 }
2239 }
2240
2241 /**
2242 * @brief This function allows to stop injected conversion in polling mode.
2243 * @note This function should be called only if injected conversion is ongoing.
2244 * @param hdfsdm_filter DFSDM filter handle.
2245 * @retval HAL status
2246 */
2247 HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
2248 {
2249 HAL_StatusTypeDef status = HAL_OK;
2250
2251 /* Check parameters */
2252 assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
2253
2254 /* Check DFSDM filter state */
2255 if((hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_INJ) && \
2256 (hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG_INJ))
2257 {
2258 /* Return error status */
2259 status = HAL_ERROR;
2260 }
2261 else
2262 {
2263 /* Stop injected conversion */
2264 DFSDM_InjConvStop(hdfsdm_filter);
2265 }
2266 /* Return function status */
2267 return status;
2268 }
2269
2270 /**
2271 * @brief This function allows to start injected conversion in interrupt mode.
2272 * @note This function should be called only when DFSDM filter instance is
2273 * in idle state or if regular conversion is ongoing.
2274 * @param hdfsdm_filter DFSDM filter handle.
2275 * @retval HAL status
2276 */
2277 HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStart_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
2278 {
2279 HAL_StatusTypeDef status = HAL_OK;
2280
2281 /* Check parameters */
2282 assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
2283
2284 /* Check DFSDM filter state */
2285 if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_READY) || \
2286 (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_REG))
2287 {
2288 /* Enable interrupts for injected conversions */
2289 hdfsdm_filter->Instance->FLTCR2 |= (DFSDM_FLTCR2_JEOCIE | DFSDM_FLTCR2_JOVRIE);
2290
2291 /* Start injected conversion */
2292 DFSDM_InjConvStart(hdfsdm_filter);
2293 }
2294 else
2295 {
2296 status = HAL_ERROR;
2297 }
2298 /* Return function status */
2299 return status;
2300 }
2301
2302 /**
2303 * @brief This function allows to stop injected conversion in interrupt mode.
2304 * @note This function should be called only if injected conversion is ongoing.
2305 * @param hdfsdm_filter DFSDM filter handle.
2306 * @retval HAL status
2307 */
2308 HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
2309 {
2310 HAL_StatusTypeDef status = HAL_OK;
2311
2312 /* Check parameters */
2313 assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
2314
2315 /* Check DFSDM filter state */
2316 if((hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_INJ) && \
2317 (hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG_INJ))
2318 {
2319 /* Return error status */
2320 status = HAL_ERROR;
2321 }
2322 else
2323 {
2324 /* Disable interrupts for injected conversions */
2325 hdfsdm_filter->Instance->FLTCR2 &= ~(DFSDM_FLTCR2_JEOCIE | DFSDM_FLTCR2_JOVRIE);
2326
2327 /* Stop injected conversion */
2328 DFSDM_InjConvStop(hdfsdm_filter);
2329 }
2330 /* Return function status */
2331 return status;
2332 }
2333
2334 /**
2335 * @brief This function allows to start injected conversion in DMA mode.
2336 * @note This function should be called only when DFSDM filter instance is
2337 * in idle state or if regular conversion is ongoing.
2338 * Please note that data on buffer will contain signed injected conversion
2339 * value on 24 most significant bits and corresponding channel on 3 least
2340 * significant bits.
2341 * @param hdfsdm_filter DFSDM filter handle.
2342 * @param pData The destination buffer address.
2343 * @param Length The length of data to be transferred from DFSDM filter to memory.
2344 * @retval HAL status
2345 */
2346 HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStart_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
2347 int32_t *pData,
2348 uint32_t Length)
2349 {
2350 HAL_StatusTypeDef status = HAL_OK;
2351
2352 /* Check parameters */
2353 assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
2354
2355 /* Check destination address and length */
2356 if((pData == NULL) || (Length == 0U))
2357 {
2358 status = HAL_ERROR;
2359 }
2360 /* Check that DMA is enabled for injected conversion */
2361 else if((hdfsdm_filter->Instance->FLTCR1 & DFSDM_FLTCR1_JDMAEN) != DFSDM_FLTCR1_JDMAEN)
2362 {
2363 status = HAL_ERROR;
2364 }
2365 /* Check parameters compatibility */
2366 else if((hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_SW_TRIGGER) && \
2367 (hdfsdm_filter->hdmaInj->Init.Mode == DMA_NORMAL) && \
2368 (Length > hdfsdm_filter->InjConvRemaining))
2369 {
2370 status = HAL_ERROR;
2371 }
2372 else if((hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_SW_TRIGGER) && \
2373 (hdfsdm_filter->hdmaInj->Init.Mode == DMA_CIRCULAR))
2374 {
2375 status = HAL_ERROR;
2376 }
2377 /* Check DFSDM filter state */
2378 else if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_READY) || \
2379 (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_REG))
2380 {
2381 /* Set callbacks on DMA handler */
2382 hdfsdm_filter->hdmaInj->XferCpltCallback = DFSDM_DMAInjectedConvCplt;
2383 hdfsdm_filter->hdmaInj->XferErrorCallback = DFSDM_DMAError;
2384 hdfsdm_filter->hdmaInj->XferHalfCpltCallback = (hdfsdm_filter->hdmaInj->Init.Mode == DMA_CIRCULAR) ?\
2385 DFSDM_DMAInjectedHalfConvCplt : NULL;
2386
2387 /* Start DMA in interrupt mode */
2388 if(HAL_DMA_Start_IT(hdfsdm_filter->hdmaInj, (uint32_t)&hdfsdm_filter->Instance->FLTJDATAR, \
2389 (uint32_t) pData, Length) != HAL_OK)
2390 {
2391 /* Set DFSDM filter in error state */
2392 hdfsdm_filter->State = HAL_DFSDM_FILTER_STATE_ERROR;
2393 status = HAL_ERROR;
2394 }
2395 else
2396 {
2397 /* Start injected conversion */
2398 DFSDM_InjConvStart(hdfsdm_filter);
2399 }
2400 }
2401 else
2402 {
2403 status = HAL_ERROR;
2404 }
2405 /* Return function status */
2406 return status;
2407 }
2408
2409 /**
2410 * @brief This function allows to start injected conversion in DMA mode and to get
2411 * only the 16 most significant bits of conversion.
2412 * @note This function should be called only when DFSDM filter instance is
2413 * in idle state or if regular conversion is ongoing.
2414 * Please note that data on buffer will contain signed 16 most significant
2415 * bits of injected conversion.
2416 * @param hdfsdm_filter DFSDM filter handle.
2417 * @param pData The destination buffer address.
2418 * @param Length The length of data to be transferred from DFSDM filter to memory.
2419 * @retval HAL status
2420 */
2421 HAL_StatusTypeDef HAL_DFSDM_FilterInjectedMsbStart_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
2422 int16_t *pData,
2423 uint32_t Length)
2424 {
2425 HAL_StatusTypeDef status = HAL_OK;
2426
2427 /* Check parameters */
2428 assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
2429
2430 /* Check destination address and length */
2431 if((pData == NULL) || (Length == 0U))
2432 {
2433 status = HAL_ERROR;
2434 }
2435 /* Check that DMA is enabled for injected conversion */
2436 else if((hdfsdm_filter->Instance->FLTCR1 & DFSDM_FLTCR1_JDMAEN) != DFSDM_FLTCR1_JDMAEN)
2437 {
2438 status = HAL_ERROR;
2439 }
2440 /* Check parameters compatibility */
2441 else if((hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_SW_TRIGGER) && \
2442 (hdfsdm_filter->hdmaInj->Init.Mode == DMA_NORMAL) && \
2443 (Length > hdfsdm_filter->InjConvRemaining))
2444 {
2445 status = HAL_ERROR;
2446 }
2447 else if((hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_SW_TRIGGER) && \
2448 (hdfsdm_filter->hdmaInj->Init.Mode == DMA_CIRCULAR))
2449 {
2450 status = HAL_ERROR;
2451 }
2452 /* Check DFSDM filter state */
2453 else if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_READY) || \
2454 (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_REG))
2455 {
2456 /* Set callbacks on DMA handler */
2457 hdfsdm_filter->hdmaInj->XferCpltCallback = DFSDM_DMAInjectedConvCplt;
2458 hdfsdm_filter->hdmaInj->XferErrorCallback = DFSDM_DMAError;
2459 hdfsdm_filter->hdmaInj->XferHalfCpltCallback = (hdfsdm_filter->hdmaInj->Init.Mode == DMA_CIRCULAR) ?\
2460 DFSDM_DMAInjectedHalfConvCplt : NULL;
2461
2462 /* Start DMA in interrupt mode */
2463 if(HAL_DMA_Start_IT(hdfsdm_filter->hdmaInj, (uint32_t)(&hdfsdm_filter->Instance->FLTJDATAR) + 2U, \
2464 (uint32_t) pData, Length) != HAL_OK)
2465 {
2466 /* Set DFSDM filter in error state */
2467 hdfsdm_filter->State = HAL_DFSDM_FILTER_STATE_ERROR;
2468 status = HAL_ERROR;
2469 }
2470 else
2471 {
2472 /* Start injected conversion */
2473 DFSDM_InjConvStart(hdfsdm_filter);
2474 }
2475 }
2476 else
2477 {
2478 status = HAL_ERROR;
2479 }
2480 /* Return function status */
2481 return status;
2482 }
2483
2484 /**
2485 * @brief This function allows to stop injected conversion in DMA mode.
2486 * @note This function should be called only if injected conversion is ongoing.
2487 * @param hdfsdm_filter DFSDM filter handle.
2488 * @retval HAL status
2489 */
2490 HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
2491 {
2492 HAL_StatusTypeDef status = HAL_OK;
2493
2494 /* Check parameters */
2495 assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
2496
2497 /* Check DFSDM filter state */
2498 if((hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_INJ) && \
2499 (hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_REG_INJ))
2500 {
2501 /* Return error status */
2502 status = HAL_ERROR;
2503 }
2504 else
2505 {
2506 /* Stop current DMA transfer */
2507 if(HAL_DMA_Abort(hdfsdm_filter->hdmaInj) != HAL_OK)
2508 {
2509 /* Set DFSDM filter in error state */
2510 hdfsdm_filter->State = HAL_DFSDM_FILTER_STATE_ERROR;
2511 status = HAL_ERROR;
2512 }
2513 else
2514 {
2515 /* Stop regular conversion */
2516 DFSDM_InjConvStop(hdfsdm_filter);
2517 }
2518 }
2519 /* Return function status */
2520 return status;
2521 }
2522
2523 /**
2524 * @brief This function allows to get injected conversion value.
2525 * @param hdfsdm_filter DFSDM filter handle.
2526 * @param Channel Corresponding channel of injected conversion.
2527 * @retval Injected conversion value
2528 */
2529 int32_t HAL_DFSDM_FilterGetInjectedValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
2530 uint32_t *Channel)
2531 {
2532 uint32_t reg = 0U;
2533 int32_t value = 0;
2534
2535 /* Check parameters */
2536 assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
2537 assert_param(Channel != NULL);
2538
2539 /* Get value of data register for injected channel */
2540 reg = hdfsdm_filter->Instance->FLTJDATAR;
2541
2542 /* Extract channel and injected conversion value */
2543 *Channel = (reg & DFSDM_FLTJDATAR_JDATACH);
2544 value = ((int32_t)(reg & DFSDM_FLTJDATAR_JDATA) >> DFSDM_FLTJDATAR_JDATA_Pos);
2545
2546 /* return regular conversion value */
2547 return value;
2548 }
2549
2550 /**
2551 * @brief This function allows to start filter analog watchdog in interrupt mode.
2552 * @param hdfsdm_filter DFSDM filter handle.
2553 * @param awdParam DFSDM filter analog watchdog parameters.
2554 * @retval HAL status
2555 */
2556 HAL_StatusTypeDef HAL_DFSDM_FilterAwdStart_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
2557 DFSDM_Filter_AwdParamTypeDef *awdParam)
2558 {
2559 HAL_StatusTypeDef status = HAL_OK;
2560
2561 /* Check parameters */
2562 assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
2563 assert_param(IS_DFSDM_FILTER_AWD_DATA_SOURCE(awdParam->DataSource));
2564 assert_param(IS_DFSDM_INJECTED_CHANNEL(awdParam->Channel));
2565 assert_param(IS_DFSDM_FILTER_AWD_THRESHOLD(awdParam->HighThreshold));
2566 assert_param(IS_DFSDM_FILTER_AWD_THRESHOLD(awdParam->LowThreshold));
2567 assert_param(IS_DFSDM_BREAK_SIGNALS(awdParam->HighBreakSignal));
2568 assert_param(IS_DFSDM_BREAK_SIGNALS(awdParam->LowBreakSignal));
2569
2570 /* Check DFSDM filter state */
2571 if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_RESET) || \
2572 (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_ERROR))
2573 {
2574 /* Return error status */
2575 status = HAL_ERROR;
2576 }
2577 else
2578 {
2579 /* Set analog watchdog data source */
2580 hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_AWFSEL);
2581 hdfsdm_filter->Instance->FLTCR1 |= awdParam->DataSource;
2582
2583 /* Set thresholds and break signals */
2584 hdfsdm_filter->Instance->FLTAWHTR &= ~(DFSDM_FLTAWHTR_AWHT | DFSDM_FLTAWHTR_BKAWH);
2585 hdfsdm_filter->Instance->FLTAWHTR |= (((uint32_t) awdParam->HighThreshold << DFSDM_FLTAWHTR_AWHT_Pos) | \
2586 awdParam->HighBreakSignal);
2587 hdfsdm_filter->Instance->FLTAWLTR &= ~(DFSDM_FLTAWLTR_AWLT | DFSDM_FLTAWLTR_BKAWL);
2588 hdfsdm_filter->Instance->FLTAWLTR |= (((uint32_t) awdParam->LowThreshold << DFSDM_FLTAWLTR_AWLT_Pos) | \
2589 awdParam->LowBreakSignal);
2590
2591 /* Set channels and interrupt for analog watchdog */
2592 hdfsdm_filter->Instance->FLTCR2 &= ~(DFSDM_FLTCR2_AWDCH);
2593 hdfsdm_filter->Instance->FLTCR2 |= (((awdParam->Channel & DFSDM_LSB_MASK) << DFSDM_FLTCR2_AWDCH_Pos) | \
2594 DFSDM_FLTCR2_AWDIE);
2595 }
2596 /* Return function status */
2597 return status;
2598 }
2599
2600 /**
2601 * @brief This function allows to stop filter analog watchdog in interrupt mode.
2602 * @param hdfsdm_filter DFSDM filter handle.
2603 * @retval HAL status
2604 */
2605 HAL_StatusTypeDef HAL_DFSDM_FilterAwdStop_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
2606 {
2607 HAL_StatusTypeDef status = HAL_OK;
2608
2609 /* Check parameters */
2610 assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
2611
2612 /* Check DFSDM filter state */
2613 if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_RESET) || \
2614 (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_ERROR))
2615 {
2616 /* Return error status */
2617 status = HAL_ERROR;
2618 }
2619 else
2620 {
2621 /* Reset channels for analog watchdog and deactivate interrupt */
2622 hdfsdm_filter->Instance->FLTCR2 &= ~(DFSDM_FLTCR2_AWDCH | DFSDM_FLTCR2_AWDIE);
2623
2624 /* Clear all analog watchdog flags */
2625 hdfsdm_filter->Instance->FLTAWCFR = (DFSDM_FLTAWCFR_CLRAWHTF | DFSDM_FLTAWCFR_CLRAWLTF);
2626
2627 /* Reset thresholds and break signals */
2628 hdfsdm_filter->Instance->FLTAWHTR &= ~(DFSDM_FLTAWHTR_AWHT | DFSDM_FLTAWHTR_BKAWH);
2629 hdfsdm_filter->Instance->FLTAWLTR &= ~(DFSDM_FLTAWLTR_AWLT | DFSDM_FLTAWLTR_BKAWL);
2630
2631 /* Reset analog watchdog data source */
2632 hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_AWFSEL);
2633 }
2634 /* Return function status */
2635 return status;
2636 }
2637
2638 /**
2639 * @brief This function allows to start extreme detector feature.
2640 * @param hdfsdm_filter DFSDM filter handle.
2641 * @param Channel Channels where extreme detector is enabled.
2642 * This parameter can be a values combination of @ref DFSDM_Channel_Selection.
2643 * @retval HAL status
2644 */
2645 HAL_StatusTypeDef HAL_DFSDM_FilterExdStart(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
2646 uint32_t Channel)
2647 {
2648 HAL_StatusTypeDef status = HAL_OK;
2649
2650 /* Check parameters */
2651 assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
2652 assert_param(IS_DFSDM_INJECTED_CHANNEL(Channel));
2653
2654 /* Check DFSDM filter state */
2655 if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_RESET) || \
2656 (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_ERROR))
2657 {
2658 /* Return error status */
2659 status = HAL_ERROR;
2660 }
2661 else
2662 {
2663 /* Set channels for extreme detector */
2664 hdfsdm_filter->Instance->FLTCR2 &= ~(DFSDM_FLTCR2_EXCH);
2665 hdfsdm_filter->Instance->FLTCR2 |= ((Channel & DFSDM_LSB_MASK) << DFSDM_FLTCR2_EXCH_Pos);
2666 }
2667 /* Return function status */
2668 return status;
2669 }
2670
2671 /**
2672 * @brief This function allows to stop extreme detector feature.
2673 * @param hdfsdm_filter DFSDM filter handle.
2674 * @retval HAL status
2675 */
2676 HAL_StatusTypeDef HAL_DFSDM_FilterExdStop(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
2677 {
2678 HAL_StatusTypeDef status = HAL_OK;
2679 __IO uint32_t reg1;
2680 __IO uint32_t reg2;
2681
2682 /* Check parameters */
2683 assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
2684
2685 /* Check DFSDM filter state */
2686 if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_RESET) || \
2687 (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_ERROR))
2688 {
2689 /* Return error status */
2690 status = HAL_ERROR;
2691 }
2692 else
2693 {
2694 /* Reset channels for extreme detector */
2695 hdfsdm_filter->Instance->FLTCR2 &= ~(DFSDM_FLTCR2_EXCH);
2696
2697 /* Clear extreme detector values */
2698 reg1 = hdfsdm_filter->Instance->FLTEXMAX;
2699 reg2 = hdfsdm_filter->Instance->FLTEXMIN;
2700 UNUSED(reg1); /* To avoid GCC warning */
2701 UNUSED(reg2); /* To avoid GCC warning */
2702 }
2703 /* Return function status */
2704 return status;
2705 }
2706
2707 /**
2708 * @brief This function allows to get extreme detector maximum value.
2709 * @param hdfsdm_filter DFSDM filter handle.
2710 * @param Channel Corresponding channel.
2711 * @retval Extreme detector maximum value
2712 * This value is between Min_Data = -8388608 and Max_Data = 8388607.
2713 */
2714 int32_t HAL_DFSDM_FilterGetExdMaxValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
2715 uint32_t *Channel)
2716 {
2717 uint32_t reg = 0U;
2718 int32_t value = 0;
2719
2720 /* Check parameters */
2721 assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
2722 assert_param(Channel != NULL);
2723
2724 /* Get value of extreme detector maximum register */
2725 reg = hdfsdm_filter->Instance->FLTEXMAX;
2726
2727 /* Extract channel and extreme detector maximum value */
2728 *Channel = (reg & DFSDM_FLTEXMAX_EXMAXCH);
2729 value = ((int32_t)(reg & DFSDM_FLTEXMAX_EXMAX) >> DFSDM_FLTEXMAX_EXMAX_Pos);
2730
2731 /* return extreme detector maximum value */
2732 return value;
2733 }
2734
2735 /**
2736 * @brief This function allows to get extreme detector minimum value.
2737 * @param hdfsdm_filter DFSDM filter handle.
2738 * @param Channel Corresponding channel.
2739 * @retval Extreme detector minimum value
2740 * This value is between Min_Data = -8388608 and Max_Data = 8388607.
2741 */
2742 int32_t HAL_DFSDM_FilterGetExdMinValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
2743 uint32_t *Channel)
2744 {
2745 uint32_t reg = 0U;
2746 int32_t value = 0;
2747
2748 /* Check parameters */
2749 assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
2750 assert_param(Channel != NULL);
2751
2752 /* Get value of extreme detector minimum register */
2753 reg = hdfsdm_filter->Instance->FLTEXMIN;
2754
2755 /* Extract channel and extreme detector minimum value */
2756 *Channel = (reg & DFSDM_FLTEXMIN_EXMINCH);
2757 value = ((int32_t)(reg & DFSDM_FLTEXMIN_EXMIN) >> DFSDM_FLTEXMIN_EXMIN_Pos);
2758
2759 /* return extreme detector minimum value */
2760 return value;
2761 }
2762
2763 /**
2764 * @brief This function allows to get conversion time value.
2765 * @param hdfsdm_filter DFSDM filter handle.
2766 * @retval Conversion time value
2767 * @note To get time in second, this value has to be divided by DFSDM clock frequency.
2768 */
2769 uint32_t HAL_DFSDM_FilterGetConvTimeValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
2770 {
2771 uint32_t reg = 0U;
2772 uint32_t value = 0U;
2773
2774 /* Check parameters */
2775 assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance));
2776
2777 /* Get value of conversion timer register */
2778 reg = hdfsdm_filter->Instance->FLTCNVTIMR;
2779
2780 /* Extract conversion time value */
2781 value = ((reg & DFSDM_FLTCNVTIMR_CNVCNT) >> DFSDM_FLTCNVTIMR_CNVCNT_Pos);
2782
2783 /* return extreme detector minimum value */
2784 return value;
2785 }
2786
2787 /**
2788 * @brief This function handles the DFSDM interrupts.
2789 * @param hdfsdm_filter DFSDM filter handle.
2790 * @retval None
2791 */
2792 void HAL_DFSDM_IRQHandler(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
2793 {
2794 /* Check if overrun occurs during regular conversion */
2795 if(((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_ROVRF) != 0U) && \
2796 ((hdfsdm_filter->Instance->FLTCR2 & DFSDM_FLTCR2_ROVRIE) != 0U))
2797 {
2798 /* Clear regular overrun flag */
2799 hdfsdm_filter->Instance->FLTICR = DFSDM_FLTICR_CLRROVRF;
2800
2801 /* Update error code */
2802 hdfsdm_filter->ErrorCode = DFSDM_FILTER_ERROR_REGULAR_OVERRUN;
2803
2804 /* Call error callback */
2805 HAL_DFSDM_FilterErrorCallback(hdfsdm_filter);
2806 }
2807 /* Check if overrun occurs during injected conversion */
2808 else if(((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_JOVRF) != 0U) && \
2809 ((hdfsdm_filter->Instance->FLTCR2 & DFSDM_FLTCR2_JOVRIE) != 0U))
2810 {
2811 /* Clear injected overrun flag */
2812 hdfsdm_filter->Instance->FLTICR = DFSDM_FLTICR_CLRJOVRF;
2813
2814 /* Update error code */
2815 hdfsdm_filter->ErrorCode = DFSDM_FILTER_ERROR_INJECTED_OVERRUN;
2816
2817 /* Call error callback */
2818 HAL_DFSDM_FilterErrorCallback(hdfsdm_filter);
2819 }
2820 /* Check if end of regular conversion */
2821 else if(((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_REOCF) != 0U) && \
2822 ((hdfsdm_filter->Instance->FLTCR2 & DFSDM_FLTCR2_REOCIE) != 0U))
2823 {
2824 /* Call regular conversion complete callback */
2825 HAL_DFSDM_FilterRegConvCpltCallback(hdfsdm_filter);
2826
2827 /* End of conversion if mode is not continuous and software trigger */
2828 if((hdfsdm_filter->RegularContMode == DFSDM_CONTINUOUS_CONV_OFF) && \
2829 (hdfsdm_filter->RegularTrigger == DFSDM_FILTER_SW_TRIGGER))
2830 {
2831 /* Disable interrupts for regular conversions */
2832 hdfsdm_filter->Instance->FLTCR2 &= ~(DFSDM_FLTCR2_REOCIE);
2833
2834 /* Update DFSDM filter state */
2835 hdfsdm_filter->State = (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_REG) ? \
2836 HAL_DFSDM_FILTER_STATE_READY : HAL_DFSDM_FILTER_STATE_INJ;
2837 }
2838 }
2839 /* Check if end of injected conversion */
2840 else if(((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_JEOCF) != 0U) && \
2841 ((hdfsdm_filter->Instance->FLTCR2 & DFSDM_FLTCR2_JEOCIE) != 0U))
2842 {
2843 /* Call injected conversion complete callback */
2844 HAL_DFSDM_FilterInjConvCpltCallback(hdfsdm_filter);
2845
2846 /* Update remaining injected conversions */
2847 hdfsdm_filter->InjConvRemaining--;
2848 if(hdfsdm_filter->InjConvRemaining == 0U)
2849 {
2850 /* End of conversion if trigger is software */
2851 if(hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_SW_TRIGGER)
2852 {
2853 /* Disable interrupts for injected conversions */
2854 hdfsdm_filter->Instance->FLTCR2 &= ~(DFSDM_FLTCR2_JEOCIE);
2855
2856 /* Update DFSDM filter state */
2857 hdfsdm_filter->State = (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_INJ) ? \
2858 HAL_DFSDM_FILTER_STATE_READY : HAL_DFSDM_FILTER_STATE_REG;
2859 }
2860 /* end of injected sequence, reset the value */
2861 hdfsdm_filter->InjConvRemaining = (hdfsdm_filter->InjectedScanMode == ENABLE) ? \
2862 hdfsdm_filter->InjectedChannelsNbr : 1U;
2863 }
2864 }
2865 /* Check if analog watchdog occurs */
2866 else if(((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_AWDF) != 0U) && \
2867 ((hdfsdm_filter->Instance->FLTCR2 & DFSDM_FLTCR2_AWDIE) != 0U))
2868 {
2869 uint32_t reg = 0U;
2870 uint32_t threshold = 0U;
2871 uint32_t channel = 0U;
2872
2873 /* Get channel and threshold */
2874 reg = hdfsdm_filter->Instance->FLTAWSR;
2875 threshold = ((reg & DFSDM_FLTAWSR_AWLTF) != 0U) ? DFSDM_AWD_LOW_THRESHOLD : DFSDM_AWD_HIGH_THRESHOLD;
2876 if(threshold == DFSDM_AWD_HIGH_THRESHOLD)
2877 {
2878 reg = reg >> DFSDM_FLTAWSR_AWHTF_Pos;
2879 }
2880 while((reg & 1U) == 0U)
2881 {
2882 channel++;
2883 reg = reg >> 1U;
2884 }
2885 /* Clear analog watchdog flag */
2886 hdfsdm_filter->Instance->FLTAWCFR = (threshold == DFSDM_AWD_HIGH_THRESHOLD) ? \
2887 (1U << (DFSDM_FLTAWSR_AWHTF_Pos + channel)) : \
2888 (1U << channel);
2889
2890 /* Call analog watchdog callback */
2891 HAL_DFSDM_FilterAwdCallback(hdfsdm_filter, channel, threshold);
2892 }
2893 /* Check if clock absence occurs */
2894 else if((hdfsdm_filter->Instance == DFSDM1_Filter0) && \
2895 ((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_CKABF) != 0U) && \
2896 ((hdfsdm_filter->Instance->FLTCR2 & DFSDM_FLTCR2_CKABIE) != 0U))
2897 {
2898 uint32_t reg = 0U;
2899 uint32_t channel = 0U;
2900
2901 reg = ((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_CKABF) >> DFSDM_FLTISR_CKABF_Pos);
2902
2903 while(channel < DFSDM1_CHANNEL_NUMBER)
2904 {
2905 /* Check if flag is set and corresponding channel is enabled */
2906 if(((reg & 1U) != 0U) && (a_dfsdm1ChannelHandle[channel] != NULL))
2907 {
2908 /* Check clock absence has been enabled for this channel */
2909 if((a_dfsdm1ChannelHandle[channel]->Instance->CHCFGR1 & DFSDM_CHCFGR1_CKABEN) != 0U)
2910 {
2911 /* Clear clock absence flag */
2912 hdfsdm_filter->Instance->FLTICR = (1U << (DFSDM_FLTICR_CLRCKABF_Pos + channel));
2913
2914 /* Call clock absence callback */
2915 HAL_DFSDM_ChannelCkabCallback(a_dfsdm1ChannelHandle[channel]);
2916 }
2917 }
2918 channel++;
2919 reg = reg >> 1U;
2920 }
2921 }
2922 #if defined (DFSDM2_Channel0)
2923 /* Check if clock absence occurs */
2924 else if((hdfsdm_filter->Instance == DFSDM2_Filter0) && \
2925 ((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_CKABF) != 0U) && \
2926 ((hdfsdm_filter->Instance->FLTCR2 & DFSDM_FLTCR2_CKABIE) != 0U))
2927 {
2928 uint32_t reg = 0U;
2929 uint32_t channel = 0U;
2930
2931 reg = ((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_CKABF) >> DFSDM_FLTISR_CKABF_Pos);
2932
2933 while(channel < DFSDM2_CHANNEL_NUMBER)
2934 {
2935 /* Check if flag is set and corresponding channel is enabled */
2936 if(((reg & 1U) != 0U) && (a_dfsdm2ChannelHandle[channel] != NULL))
2937 {
2938 /* Check clock absence has been enabled for this channel */
2939 if((a_dfsdm2ChannelHandle[channel]->Instance->CHCFGR1 & DFSDM_CHCFGR1_CKABEN) != 0U)
2940 {
2941 /* Clear clock absence flag */
2942 hdfsdm_filter->Instance->FLTICR = (1U << (DFSDM_FLTICR_CLRCKABF_Pos + channel));
2943
2944 /* Call clock absence callback */
2945 HAL_DFSDM_ChannelCkabCallback(a_dfsdm2ChannelHandle[channel]);
2946 }
2947 }
2948 channel++;
2949 reg = reg >> 1U;
2950 }
2951 }
2952 #endif /* DFSDM2_Channel0 */
2953 /* Check if short circuit detection occurs */
2954 else if((hdfsdm_filter->Instance == DFSDM1_Filter0) && \
2955 ((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_SCDF) != 0U) && \
2956 ((hdfsdm_filter->Instance->FLTCR2 & DFSDM_FLTCR2_SCDIE) != 0U))
2957 {
2958 uint32_t reg = 0U;
2959 uint32_t channel = 0U;
2960
2961 /* Get channel */
2962 reg = ((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_SCDF) >> DFSDM_FLTISR_SCDF_Pos);
2963 while((reg & 1U) == 0U)
2964 {
2965 channel++;
2966 reg = reg >> 1U;
2967 }
2968
2969 /* Clear short circuit detection flag */
2970 hdfsdm_filter->Instance->FLTICR = (1U << (DFSDM_FLTICR_CLRSCSDF_Pos + channel));
2971
2972 /* Call short circuit detection callback */
2973 HAL_DFSDM_ChannelScdCallback(a_dfsdm1ChannelHandle[channel]);
2974 }
2975 #if defined (DFSDM2_Channel0)
2976 /* Check if short circuit detection occurs */
2977 else if((hdfsdm_filter->Instance == DFSDM2_Filter0) && \
2978 ((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_SCDF) != 0U) && \
2979 ((hdfsdm_filter->Instance->FLTCR2 & DFSDM_FLTCR2_SCDIE) != 0U))
2980 {
2981 uint32_t reg = 0U;
2982 uint32_t channel = 0U;
2983
2984 /* Get channel */
2985 reg = ((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_SCDF) >> DFSDM_FLTISR_SCDF_Pos);
2986 while((reg & 1U) == 0U)
2987 {
2988 channel++;
2989 reg = reg >> 1U;
2990 }
2991
2992 /* Clear short circuit detection flag */
2993 hdfsdm_filter->Instance->FLTICR = (1U << (DFSDM_FLTICR_CLRSCSDF_Pos + channel));
2994
2995 /* Call short circuit detection callback */
2996 HAL_DFSDM_ChannelScdCallback(a_dfsdm2ChannelHandle[channel]);
2997 }
2998 #endif /* DFSDM2_Channel0 */
2999 }
3000
3001 /**
3002 * @brief Regular conversion complete callback.
3003 * @note In interrupt mode, user has to read conversion value in this function
3004 * using HAL_DFSDM_FilterGetRegularValue.
3005 * @param hdfsdm_filter DFSDM filter handle.
3006 * @retval None
3007 */
3008 __weak void HAL_DFSDM_FilterRegConvCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
3009 {
3010 /* Prevent unused argument(s) compilation warning */
3011 UNUSED(hdfsdm_filter);
3012 /* NOTE : This function should not be modified, when the callback is needed,
3013 the HAL_DFSDM_FilterRegConvCpltCallback could be implemented in the user file.
3014 */
3015 }
3016
3017 /**
3018 * @brief Half regular conversion complete callback.
3019 * @param hdfsdm_filter DFSDM filter handle.
3020 * @retval None
3021 */
3022 __weak void HAL_DFSDM_FilterRegConvHalfCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
3023 {
3024 /* Prevent unused argument(s) compilation warning */
3025 UNUSED(hdfsdm_filter);
3026 /* NOTE : This function should not be modified, when the callback is needed,
3027 the HAL_DFSDM_FilterRegConvHalfCpltCallback could be implemented in the user file.
3028 */
3029 }
3030
3031 /**
3032 * @brief Injected conversion complete callback.
3033 * @note In interrupt mode, user has to read conversion value in this function
3034 * using HAL_DFSDM_FilterGetInjectedValue.
3035 * @param hdfsdm_filter DFSDM filter handle.
3036 * @retval None
3037 */
3038 __weak void HAL_DFSDM_FilterInjConvCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
3039 {
3040 /* Prevent unused argument(s) compilation warning */
3041 UNUSED(hdfsdm_filter);
3042 /* NOTE : This function should not be modified, when the callback is needed,
3043 the HAL_DFSDM_FilterInjConvCpltCallback could be implemented in the user file.
3044 */
3045 }
3046
3047 /**
3048 * @brief Half injected conversion complete callback.
3049 * @param hdfsdm_filter DFSDM filter handle.
3050 * @retval None
3051 */
3052 __weak void HAL_DFSDM_FilterInjConvHalfCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
3053 {
3054 /* Prevent unused argument(s) compilation warning */
3055 UNUSED(hdfsdm_filter);
3056 /* NOTE : This function should not be modified, when the callback is needed,
3057 the HAL_DFSDM_FilterInjConvHalfCpltCallback could be implemented in the user file.
3058 */
3059 }
3060
3061 /**
3062 * @brief Filter analog watchdog callback.
3063 * @param hdfsdm_filter DFSDM filter handle.
3064 * @param Channel Corresponding channel.
3065 * @param Threshold Low or high threshold has been reached.
3066 * @retval None
3067 */
3068 __weak void HAL_DFSDM_FilterAwdCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
3069 uint32_t Channel, uint32_t Threshold)
3070 {
3071 /* Prevent unused argument(s) compilation warning */
3072 UNUSED(hdfsdm_filter);
3073 UNUSED(Channel);
3074 UNUSED(Threshold);
3075
3076 /* NOTE : This function should not be modified, when the callback is needed,
3077 the HAL_DFSDM_FilterAwdCallback could be implemented in the user file.
3078 */
3079 }
3080
3081 /**
3082 * @brief Error callback.
3083 * @param hdfsdm_filter DFSDM filter handle.
3084 * @retval None
3085 */
3086 __weak void HAL_DFSDM_FilterErrorCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
3087 {
3088 /* Prevent unused argument(s) compilation warning */
3089 UNUSED(hdfsdm_filter);
3090 /* NOTE : This function should not be modified, when the callback is needed,
3091 the HAL_DFSDM_FilterErrorCallback could be implemented in the user file.
3092 */
3093 }
3094
3095 /**
3096 * @}
3097 */
3098
3099 /** @defgroup DFSDM_Exported_Functions_Group4_Filter Filter state functions
3100 * @brief Filter state functions
3101 *
3102 @verbatim
3103 ==============================================================================
3104 ##### Filter state functions #####
3105 ==============================================================================
3106 [..] This section provides functions allowing to:
3107 (+) Get the DFSDM filter state.
3108 (+) Get the DFSDM filter error.
3109 @endverbatim
3110 * @{
3111 */
3112
3113 /**
3114 * @brief This function allows to get the current DFSDM filter handle state.
3115 * @param hdfsdm_filter DFSDM filter handle.
3116 * @retval DFSDM filter state.
3117 */
3118 HAL_DFSDM_Filter_StateTypeDef HAL_DFSDM_FilterGetState(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
3119 {
3120 /* Return DFSDM filter handle state */
3121 return hdfsdm_filter->State;
3122 }
3123
3124 /**
3125 * @brief This function allows to get the current DFSDM filter error.
3126 * @param hdfsdm_filter DFSDM filter handle.
3127 * @retval DFSDM filter error code.
3128 */
3129 uint32_t HAL_DFSDM_FilterGetError(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
3130 {
3131 return hdfsdm_filter->ErrorCode;
3132 }
3133
3134 /**
3135 * @}
3136 */
3137
3138 /** @defgroup DFSDM_Exported_Functions_Group5_Filter MultiChannel operation functions
3139 * @brief Filter state functions
3140 *
3141 @verbatim
3142 ==============================================================================
3143 ##### Filter MultiChannel operation functions #####
3144 ==============================================================================
3145 [..] This section provides functions allowing to:
3146 (+) Control the DFSDM Multi channel delay block
3147 @endverbatim
3148 * @{
3149 */
3150 #if defined(SYSCFG_MCHDLYCR_BSCKSEL)
3151 /**
3152 * @brief Select the DFSDM2 as clock source for the bitstream clock.
3153 * @note The SYSCFG clock marco __HAL_RCC_SYSCFG_CLK_ENABLE() must be called
3154 * before HAL_DFSDM_BitstreamClock_Start()
3155 */
3156 void HAL_DFSDM_BitstreamClock_Start(void)
3157 {
3158 uint32_t tmp = 0;
3159
3160 tmp = SYSCFG->MCHDLYCR;
3161 tmp = (tmp &(~SYSCFG_MCHDLYCR_BSCKSEL));
3162
3163 SYSCFG->MCHDLYCR = (tmp|SYSCFG_MCHDLYCR_BSCKSEL);
3164 }
3165
3166 /**
3167 * @brief Stop the DFSDM2 as clock source for the bitstream clock.
3168 * @note The SYSCFG clock marco __HAL_RCC_SYSCFG_CLK_ENABLE() must be called
3169 * before HAL_DFSDM_BitstreamClock_Stop()
3170 * @retval None
3171 */
3172 void HAL_DFSDM_BitstreamClock_Stop(void)
3173 {
3174 uint32_t tmp = 0U;
3175
3176 tmp = SYSCFG->MCHDLYCR;
3177 tmp = (tmp &(~SYSCFG_MCHDLYCR_BSCKSEL));
3178
3179 SYSCFG->MCHDLYCR = tmp;
3180 }
3181
3182 /**
3183 * @brief Disable Delay Clock for DFSDM1/2.
3184 * @param MCHDLY HAL_MCHDLY_CLOCK_DFSDM2.
3185 * HAL_MCHDLY_CLOCK_DFSDM1.
3186 * @note The SYSCFG clock marco __HAL_RCC_SYSCFG_CLK_ENABLE() must be called
3187 * before HAL_DFSDM_DisableDelayClock()
3188 * @retval None
3189 */
3190 void HAL_DFSDM_DisableDelayClock(uint32_t MCHDLY)
3191 {
3192 uint32_t tmp = 0U;
3193
3194 assert_param(IS_DFSDM_DELAY_CLOCK(MCHDLY));
3195
3196 tmp = SYSCFG->MCHDLYCR;
3197 if(MCHDLY == HAL_MCHDLY_CLOCK_DFSDM2)
3198 {
3199 tmp = tmp &(~SYSCFG_MCHDLYCR_MCHDLY2EN);
3200 }
3201 else
3202 {
3203 tmp = tmp &(~SYSCFG_MCHDLYCR_MCHDLY1EN);
3204 }
3205
3206 SYSCFG->MCHDLYCR = tmp;
3207 }
3208
3209 /**
3210 * @brief Enable Delay Clock for DFSDM1/2.
3211 * @param MCHDLY HAL_MCHDLY_CLOCK_DFSDM2.
3212 * HAL_MCHDLY_CLOCK_DFSDM1.
3213 * @note The SYSCFG clock marco __HAL_RCC_SYSCFG_CLK_ENABLE() must be called
3214 * before HAL_DFSDM_EnableDelayClock()
3215 * @retval None
3216 */
3217 void HAL_DFSDM_EnableDelayClock(uint32_t MCHDLY)
3218 {
3219 uint32_t tmp = 0U;
3220
3221 assert_param(IS_DFSDM_DELAY_CLOCK(MCHDLY));
3222
3223 tmp = SYSCFG->MCHDLYCR;
3224 tmp = tmp & ~MCHDLY;
3225
3226 SYSCFG->MCHDLYCR = (tmp|MCHDLY);
3227 }
3228
3229 /**
3230 * @brief Select the source for CKin signals for DFSDM1/2.
3231 * @param source DFSDM2_CKIN_PAD.
3232 * DFSDM2_CKIN_DM.
3233 * DFSDM1_CKIN_PAD.
3234 * DFSDM1_CKIN_DM.
3235 * @retval None
3236 */
3237 void HAL_DFSDM_ClockIn_SourceSelection(uint32_t source)
3238 {
3239 uint32_t tmp = 0U;
3240
3241 assert_param(IS_DFSDM_CLOCKIN_SELECTION(source));
3242
3243 tmp = SYSCFG->MCHDLYCR;
3244
3245 if((source == HAL_DFSDM2_CKIN_PAD) || (source == HAL_DFSDM2_CKIN_DM))
3246 {
3247 tmp = (tmp & ~SYSCFG_MCHDLYCR_DFSDM2CFG);
3248
3249 if(source == HAL_DFSDM2_CKIN_PAD)
3250 {
3251 source = 0x000000U;
3252 }
3253 }
3254 else
3255 {
3256 tmp = (tmp & ~SYSCFG_MCHDLYCR_DFSDM1CFG);
3257 }
3258
3259 SYSCFG->MCHDLYCR = (source|tmp);
3260 }
3261
3262 /**
3263 * @brief Select the source for CKOut signals for DFSDM1/2.
3264 * @param source: DFSDM2_CKOUT_DFSDM2.
3265 * DFSDM2_CKOUT_M27.
3266 * DFSDM1_CKOUT_DFSDM1.
3267 * DFSDM1_CKOUT_M27.
3268 * @retval None
3269 */
3270 void HAL_DFSDM_ClockOut_SourceSelection(uint32_t source)
3271 {
3272 uint32_t tmp = 0U;
3273
3274 assert_param(IS_DFSDM_CLOCKOUT_SELECTION(source));
3275
3276 tmp = SYSCFG->MCHDLYCR;
3277
3278 if((source == HAL_DFSDM2_CKOUT_DFSDM2) || (source == HAL_DFSDM2_CKOUT_M27))
3279 {
3280 tmp = (tmp & ~SYSCFG_MCHDLYCR_DFSDM2CKOSEL);
3281
3282 if(source == HAL_DFSDM2_CKOUT_DFSDM2)
3283 {
3284 source = 0x000U;
3285 }
3286 }
3287 else
3288 {
3289 tmp = (tmp & ~SYSCFG_MCHDLYCR_DFSDM1CKOSEL);
3290 }
3291
3292 SYSCFG->MCHDLYCR = (source|tmp);
3293 }
3294
3295 /**
3296 * @brief Select the source for DataIn0 signals for DFSDM1/2.
3297 * @param source DATAIN0_DFSDM2_PAD.
3298 * DATAIN0_DFSDM2_DATAIN1.
3299 * DATAIN0_DFSDM1_PAD.
3300 * DATAIN0_DFSDM1_DATAIN1.
3301 * @retval None
3302 */
3303 void HAL_DFSDM_DataIn0_SourceSelection(uint32_t source)
3304 {
3305 uint32_t tmp = 0U;
3306
3307 assert_param(IS_DFSDM_DATAIN0_SRC_SELECTION(source));
3308
3309 tmp = SYSCFG->MCHDLYCR;
3310
3311 if((source == HAL_DATAIN0_DFSDM2_PAD)|| (source == HAL_DATAIN0_DFSDM2_DATAIN1))
3312 {
3313 tmp = (tmp & ~SYSCFG_MCHDLYCR_DFSDM2D0SEL);
3314 if(source == HAL_DATAIN0_DFSDM2_PAD)
3315 {
3316 source = 0x00000U;
3317 }
3318 }
3319 else
3320 {
3321 tmp = (tmp & ~SYSCFG_MCHDLYCR_DFSDM1D0SEL);
3322 }
3323 SYSCFG->MCHDLYCR = (source|tmp);
3324 }
3325
3326 /**
3327 * @brief Select the source for DataIn2 signals for DFSDM1/2.
3328 * @param source DATAIN2_DFSDM2_PAD.
3329 * DATAIN2_DFSDM2_DATAIN3.
3330 * DATAIN2_DFSDM1_PAD.
3331 * DATAIN2_DFSDM1_DATAIN3.
3332 * @retval None
3333 */
3334 void HAL_DFSDM_DataIn2_SourceSelection(uint32_t source)
3335 {
3336 uint32_t tmp = 0U;
3337
3338 assert_param(IS_DFSDM_DATAIN2_SRC_SELECTION(source));
3339
3340 tmp = SYSCFG->MCHDLYCR;
3341
3342 if((source == HAL_DATAIN2_DFSDM2_PAD)|| (source == HAL_DATAIN2_DFSDM2_DATAIN3))
3343 {
3344 tmp = (tmp & ~SYSCFG_MCHDLYCR_DFSDM2D2SEL);
3345 if (source == HAL_DATAIN2_DFSDM2_PAD)
3346 {
3347 source = 0x0000U;
3348 }
3349 }
3350 else
3351 {
3352 tmp = (tmp & ~SYSCFG_MCHDLYCR_DFSDM1D2SEL);
3353 }
3354 SYSCFG->MCHDLYCR = (source|tmp);
3355 }
3356
3357 /**
3358 * @brief Select the source for DataIn4 signals for DFSDM2.
3359 * @param source DATAIN4_DFSDM2_PAD.
3360 * DATAIN4_DFSDM2_DATAIN5
3361 * @retval None
3362 */
3363 void HAL_DFSDM_DataIn4_SourceSelection(uint32_t source)
3364 {
3365 uint32_t tmp = 0U;
3366
3367 assert_param(IS_DFSDM_DATAIN4_SRC_SELECTION(source));
3368
3369 tmp = SYSCFG->MCHDLYCR;
3370 tmp = (tmp & ~SYSCFG_MCHDLYCR_DFSDM2D4SEL);
3371
3372 SYSCFG->MCHDLYCR = (source|tmp);
3373 }
3374
3375 /**
3376 * @brief Select the source for DataIn6 signals for DFSDM2.
3377 * @param source DATAIN6_DFSDM2_PAD.
3378 * DATAIN6_DFSDM2_DATAIN7.
3379 * @retval None
3380 */
3381 void HAL_DFSDM_DataIn6_SourceSelection(uint32_t source)
3382 {
3383 uint32_t tmp = 0U;
3384
3385 assert_param(IS_DFSDM_DATAIN6_SRC_SELECTION(source));
3386
3387 tmp = SYSCFG->MCHDLYCR;
3388
3389 tmp = (tmp & ~SYSCFG_MCHDLYCR_DFSDM2D6SEL);
3390
3391 SYSCFG->MCHDLYCR = (source|tmp);
3392 }
3393
3394 /**
3395 * @brief Configure the distribution of the bitstream clock gated from TIM4_OC
3396 * for DFSDM1 or TIM3_OC for DFSDM2
3397 * @param source DFSDM1_CLKIN0_TIM4OC2
3398 * DFSDM1_CLKIN2_TIM4OC2
3399 * DFSDM1_CLKIN1_TIM4OC1
3400 * DFSDM1_CLKIN3_TIM4OC1
3401 * DFSDM2_CLKIN0_TIM3OC4
3402 * DFSDM2_CLKIN4_TIM3OC4
3403 * DFSDM2_CLKIN1_TIM3OC3
3404 * DFSDM2_CLKIN5_TIM3OC3
3405 * DFSDM2_CLKIN2_TIM3OC2
3406 * DFSDM2_CLKIN6_TIM3OC2
3407 * DFSDM2_CLKIN3_TIM3OC1
3408 * DFSDM2_CLKIN7_TIM3OC1
3409 * @retval None
3410 */
3411 void HAL_DFSDM_BitStreamClkDistribution_Config(uint32_t source)
3412 {
3413 uint32_t tmp = 0U;
3414
3415 assert_param(IS_DFSDM_BITSTREM_CLK_DISTRIBUTION(source));
3416
3417 tmp = SYSCFG->MCHDLYCR;
3418
3419 if ((source == HAL_DFSDM1_CLKIN0_TIM4OC2) || (source == HAL_DFSDM1_CLKIN2_TIM4OC2))
3420 {
3421 tmp = (tmp & ~SYSCFG_MCHDLYCR_DFSDM1CK02SEL);
3422 }
3423 else if ((source == HAL_DFSDM1_CLKIN1_TIM4OC1) || (source == HAL_DFSDM1_CLKIN3_TIM4OC1))
3424 {
3425 tmp = (tmp & ~SYSCFG_MCHDLYCR_DFSDM1CK13SEL);
3426 }
3427 else if ((source == HAL_DFSDM2_CLKIN0_TIM3OC4) || (source == HAL_DFSDM2_CLKIN4_TIM3OC4))
3428 {
3429 tmp = (tmp & ~SYSCFG_MCHDLYCR_DFSDM2CK04SEL);
3430 }
3431 else if ((source == HAL_DFSDM2_CLKIN1_TIM3OC3) || (source == HAL_DFSDM2_CLKIN5_TIM3OC3))
3432 {
3433 tmp = (tmp & ~SYSCFG_MCHDLYCR_DFSDM2CK15SEL);
3434
3435 }else if ((source == HAL_DFSDM2_CLKIN2_TIM3OC2) || (source == HAL_DFSDM2_CLKIN6_TIM3OC2))
3436 {
3437 tmp = (tmp & ~SYSCFG_MCHDLYCR_DFSDM2CK26SEL);
3438 }
3439 else
3440 {
3441 tmp = (tmp & ~SYSCFG_MCHDLYCR_DFSDM2CK37SEL);
3442 }
3443
3444 if((source == HAL_DFSDM1_CLKIN0_TIM4OC2) ||(source == HAL_DFSDM1_CLKIN1_TIM4OC1)||
3445 (source == HAL_DFSDM2_CLKIN0_TIM3OC4) ||(source == HAL_DFSDM2_CLKIN1_TIM3OC3)||
3446 (source == HAL_DFSDM2_CLKIN2_TIM3OC2) ||(source == HAL_DFSDM2_CLKIN3_TIM3OC1))
3447 {
3448 source = 0x0000U;
3449 }
3450
3451 SYSCFG->MCHDLYCR = (source|tmp);
3452 }
3453
3454 /**
3455 * @brief Configure multi channel delay block: Use DFSDM2 audio clock source as input
3456 * clock for DFSDM1 and DFSDM2 filters to Synchronize DFSDMx filters.
3457 * Set the path of the DFSDM2 clock output (dfsdm2_ckout) to the
3458 * DFSDM1/2 CkInx and data inputs channels by configuring following MCHDLY muxes
3459 * or demuxes: M1, M2, M3, M4, M5, M6, M7, M8, DM1, DM2, DM3, DM4, DM5, DM6,
3460 * M9, M10, M11, M12, M13, M14, M15, M16, M17, M18, M19, M20 based on the
3461 * contains of the DFSDM_MultiChannelConfigTypeDef structure
3462 * @param mchdlystruct Structure of multi channel configuration
3463 * @retval None
3464 * @note The SYSCFG clock marco __HAL_RCC_SYSCFG_CLK_ENABLE() must be called
3465 * before HAL_DFSDM_ConfigMultiChannelDelay()
3466 * @note The HAL_DFSDM_ConfigMultiChannelDelay() function clears the SYSCFG-MCHDLYCR
3467 * register before setting the new configuration.
3468 */
3469 void HAL_DFSDM_ConfigMultiChannelDelay(DFSDM_MultiChannelConfigTypeDef* mchdlystruct)
3470 {
3471 uint32_t mchdlyreg = 0U;
3472
3473 assert_param(IS_DFSDM_DFSDM1_CLKOUT(mchdlystruct->DFSDM1ClockOut));
3474 assert_param(IS_DFSDM_DFSDM2_CLKOUT(mchdlystruct->DFSDM2ClockOut));
3475 assert_param(IS_DFSDM_DFSDM1_CLKIN(mchdlystruct->DFSDM1ClockIn));
3476 assert_param(IS_DFSDM_DFSDM2_CLKIN(mchdlystruct->DFSDM2ClockIn));
3477 assert_param(IS_DFSDM_DFSDM1_BIT_CLK((mchdlystruct->DFSDM1BitClkDistribution)));
3478 assert_param(IS_DFSDM_DFSDM2_BIT_CLK(mchdlystruct->DFSDM2BitClkDistribution));
3479 assert_param(IS_DFSDM_DFSDM1_DATA_DISTRIBUTION(mchdlystruct->DFSDM1DataDistribution));
3480 assert_param(IS_DFSDM_DFSDM2_DATA_DISTRIBUTION(mchdlystruct->DFSDM2DataDistribution));
3481
3482 mchdlyreg = (SYSCFG->MCHDLYCR & 0x80103U);
3483
3484 SYSCFG->MCHDLYCR = (mchdlyreg |(mchdlystruct->DFSDM1ClockOut)|(mchdlystruct->DFSDM2ClockOut)|
3485 (mchdlystruct->DFSDM1ClockIn)|(mchdlystruct->DFSDM2ClockIn)|
3486 (mchdlystruct->DFSDM1BitClkDistribution)| (mchdlystruct->DFSDM2BitClkDistribution)|
3487 (mchdlystruct->DFSDM1DataDistribution)| (mchdlystruct->DFSDM2DataDistribution));
3488
3489 }
3490 #endif /* SYSCFG_MCHDLYCR_BSCKSEL */
3491 /**
3492 * @}
3493 */
3494 /**
3495 * @}
3496 */
3497 /* End of exported functions -------------------------------------------------*/
3498
3499 /* Private functions ---------------------------------------------------------*/
3500 /** @addtogroup DFSDM_Private_Functions DFSDM Private Functions
3501 * @{
3502 */
3503
3504 /**
3505 * @brief DMA half transfer complete callback for regular conversion.
3506 * @param hdma DMA handle.
3507 * @retval None
3508 */
3509 static void DFSDM_DMARegularHalfConvCplt(DMA_HandleTypeDef *hdma)
3510 {
3511 /* Get DFSDM filter handle */
3512 DFSDM_Filter_HandleTypeDef* hdfsdm_filter = (DFSDM_Filter_HandleTypeDef*) ((DMA_HandleTypeDef*)hdma)->Parent;
3513
3514 /* Call regular half conversion complete callback */
3515 HAL_DFSDM_FilterRegConvHalfCpltCallback(hdfsdm_filter);
3516 }
3517
3518 /**
3519 * @brief DMA transfer complete callback for regular conversion.
3520 * @param hdma DMA handle.
3521 * @retval None
3522 */
3523 static void DFSDM_DMARegularConvCplt(DMA_HandleTypeDef *hdma)
3524 {
3525 /* Get DFSDM filter handle */
3526 DFSDM_Filter_HandleTypeDef* hdfsdm_filter = (DFSDM_Filter_HandleTypeDef*) ((DMA_HandleTypeDef*)hdma)->Parent;
3527
3528 /* Call regular conversion complete callback */
3529 HAL_DFSDM_FilterRegConvCpltCallback(hdfsdm_filter);
3530 }
3531
3532 /**
3533 * @brief DMA half transfer complete callback for injected conversion.
3534 * @param hdma DMA handle.
3535 * @retval None
3536 */
3537 static void DFSDM_DMAInjectedHalfConvCplt(DMA_HandleTypeDef *hdma)
3538 {
3539 /* Get DFSDM filter handle */
3540 DFSDM_Filter_HandleTypeDef* hdfsdm_filter = (DFSDM_Filter_HandleTypeDef*) ((DMA_HandleTypeDef*)hdma)->Parent;
3541
3542 /* Call injected half conversion complete callback */
3543 HAL_DFSDM_FilterInjConvHalfCpltCallback(hdfsdm_filter);
3544 }
3545
3546 /**
3547 * @brief DMA transfer complete callback for injected conversion.
3548 * @param hdma DMA handle.
3549 * @retval None
3550 */
3551 static void DFSDM_DMAInjectedConvCplt(DMA_HandleTypeDef *hdma)
3552 {
3553 /* Get DFSDM filter handle */
3554 DFSDM_Filter_HandleTypeDef* hdfsdm_filter = (DFSDM_Filter_HandleTypeDef*) ((DMA_HandleTypeDef*)hdma)->Parent;
3555
3556 /* Call injected conversion complete callback */
3557 HAL_DFSDM_FilterInjConvCpltCallback(hdfsdm_filter);
3558 }
3559
3560 /**
3561 * @brief DMA error callback.
3562 * @param hdma DMA handle.
3563 * @retval None
3564 */
3565 static void DFSDM_DMAError(DMA_HandleTypeDef *hdma)
3566 {
3567 /* Get DFSDM filter handle */
3568 DFSDM_Filter_HandleTypeDef* hdfsdm_filter = (DFSDM_Filter_HandleTypeDef*) ((DMA_HandleTypeDef*)hdma)->Parent;
3569
3570 /* Update error code */
3571 hdfsdm_filter->ErrorCode = DFSDM_FILTER_ERROR_DMA;
3572
3573 /* Call error callback */
3574 HAL_DFSDM_FilterErrorCallback(hdfsdm_filter);
3575 }
3576
3577 /**
3578 * @brief This function allows to get the number of injected channels.
3579 * @param Channels bitfield of injected channels.
3580 * @retval Number of injected channels.
3581 */
3582 static uint32_t DFSDM_GetInjChannelsNbr(uint32_t Channels)
3583 {
3584 uint32_t nbChannels = 0U;
3585 uint32_t tmp;
3586
3587 /* Get the number of channels from bitfield */
3588 tmp = (uint32_t) (Channels & DFSDM_LSB_MASK);
3589 while(tmp != 0U)
3590 {
3591 if((tmp & 1U) != 0U)
3592 {
3593 nbChannels++;
3594 }
3595 tmp = (uint32_t) (tmp >> 1U);
3596 }
3597 return nbChannels;
3598 }
3599
3600 /**
3601 * @brief This function allows to get the channel number from channel instance.
3602 * @param Instance DFSDM channel instance.
3603 * @retval Channel number.
3604 */
3605 static uint32_t DFSDM_GetChannelFromInstance(DFSDM_Channel_TypeDef* Instance)
3606 {
3607 uint32_t channel = 0xFFU;
3608
3609 /* Get channel from instance */
3610 #if defined(DFSDM2_Channel0)
3611 if((Instance == DFSDM1_Channel0) || (Instance == DFSDM2_Channel0))
3612 {
3613 channel = 0U;
3614 }
3615 else if((Instance == DFSDM1_Channel1) || (Instance == DFSDM2_Channel1))
3616 {
3617 channel = 1U;
3618 }
3619 else if((Instance == DFSDM1_Channel2) || (Instance == DFSDM2_Channel2))
3620 {
3621 channel = 2U;
3622 }
3623 else if((Instance == DFSDM1_Channel3) || (Instance == DFSDM2_Channel3))
3624 {
3625 channel = 3U;
3626 }
3627 else if(Instance == DFSDM2_Channel4)
3628 {
3629 channel = 4U;
3630 }
3631 else if(Instance == DFSDM2_Channel5)
3632 {
3633 channel = 5U;
3634 }
3635 else if(Instance == DFSDM2_Channel6)
3636 {
3637 channel = 6U;
3638 }
3639 else if(Instance == DFSDM2_Channel7)
3640 {
3641 channel = 7U;
3642 }
3643 #else
3644 if(Instance == DFSDM1_Channel0)
3645 {
3646 channel = 0U;
3647 }
3648 else if(Instance == DFSDM1_Channel1)
3649 {
3650 channel = 1U;
3651 }
3652 else if(Instance == DFSDM1_Channel2)
3653 {
3654 channel = 2U;
3655 }
3656 else if(Instance == DFSDM1_Channel3)
3657 {
3658 channel = 3U;
3659 }
3660 #endif /* defined(DFSDM2_Channel0) */
3661
3662 return channel;
3663 }
3664
3665 /**
3666 * @brief This function allows to really start regular conversion.
3667 * @param hdfsdm_filter DFSDM filter handle.
3668 * @retval None
3669 */
3670 static void DFSDM_RegConvStart(DFSDM_Filter_HandleTypeDef* hdfsdm_filter)
3671 {
3672 /* Check regular trigger */
3673 if(hdfsdm_filter->RegularTrigger == DFSDM_FILTER_SW_TRIGGER)
3674 {
3675 /* Software start of regular conversion */
3676 hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_RSWSTART;
3677 }
3678 else /* synchronous trigger */
3679 {
3680 /* Disable DFSDM filter */
3681 hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_DFEN);
3682
3683 /* Set RSYNC bit in DFSDM_FLTCR1 register */
3684 hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_RSYNC;
3685
3686 /* Enable DFSDM filter */
3687 hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_DFEN;
3688
3689 /* If injected conversion was in progress, restart it */
3690 if(hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_INJ)
3691 {
3692 if(hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_SW_TRIGGER)
3693 {
3694 hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_JSWSTART;
3695 }
3696 /* Update remaining injected conversions */
3697 hdfsdm_filter->InjConvRemaining = (hdfsdm_filter->InjectedScanMode == ENABLE) ? \
3698 hdfsdm_filter->InjectedChannelsNbr : 1U;
3699 }
3700 }
3701 /* Update DFSDM filter state */
3702 hdfsdm_filter->State = (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_READY) ? \
3703 HAL_DFSDM_FILTER_STATE_REG : HAL_DFSDM_FILTER_STATE_REG_INJ;
3704 }
3705
3706 /**
3707 * @brief This function allows to really stop regular conversion.
3708 * @param hdfsdm_filter DFSDM filter handle.
3709 * @retval None
3710 */
3711 static void DFSDM_RegConvStop(DFSDM_Filter_HandleTypeDef* hdfsdm_filter)
3712 {
3713 /* Disable DFSDM filter */
3714 hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_DFEN);
3715
3716 /* If regular trigger was synchronous, reset RSYNC bit in DFSDM_FLTCR1 register */
3717 if(hdfsdm_filter->RegularTrigger == DFSDM_FILTER_SYNC_TRIGGER)
3718 {
3719 hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_RSYNC);
3720 }
3721
3722 /* Enable DFSDM filter */
3723 hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_DFEN;
3724
3725 /* If injected conversion was in progress, restart it */
3726 if(hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_REG_INJ)
3727 {
3728 if(hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_SW_TRIGGER)
3729 {
3730 hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_JSWSTART;
3731 }
3732 /* Update remaining injected conversions */
3733 hdfsdm_filter->InjConvRemaining = (hdfsdm_filter->InjectedScanMode == ENABLE) ? \
3734 hdfsdm_filter->InjectedChannelsNbr : 1U;
3735 }
3736
3737 /* Update DFSDM filter state */
3738 hdfsdm_filter->State = (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_REG) ? \
3739 HAL_DFSDM_FILTER_STATE_READY : HAL_DFSDM_FILTER_STATE_INJ;
3740 }
3741
3742 /**
3743 * @brief This function allows to really start injected conversion.
3744 * @param hdfsdm_filter DFSDM filter handle.
3745 * @retval None
3746 */
3747 static void DFSDM_InjConvStart(DFSDM_Filter_HandleTypeDef* hdfsdm_filter)
3748 {
3749 /* Check injected trigger */
3750 if(hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_SW_TRIGGER)
3751 {
3752 /* Software start of injected conversion */
3753 hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_JSWSTART;
3754 }
3755 else /* external or synchronous trigger */
3756 {
3757 /* Disable DFSDM filter */
3758 hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_DFEN);
3759
3760 if(hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_SYNC_TRIGGER)
3761 {
3762 /* Set JSYNC bit in DFSDM_FLTCR1 register */
3763 hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_JSYNC;
3764 }
3765 else /* external trigger */
3766 {
3767 /* Set JEXTEN[1:0] bits in DFSDM_FLTCR1 register */
3768 hdfsdm_filter->Instance->FLTCR1 |= hdfsdm_filter->ExtTriggerEdge;
3769 }
3770
3771 /* Enable DFSDM filter */
3772 hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_DFEN;
3773
3774 /* If regular conversion was in progress, restart it */
3775 if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_REG) && \
3776 (hdfsdm_filter->RegularTrigger == DFSDM_FILTER_SW_TRIGGER))
3777 {
3778 hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_RSWSTART;
3779 }
3780 }
3781 /* Update DFSDM filter state */
3782 hdfsdm_filter->State = (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_READY) ? \
3783 HAL_DFSDM_FILTER_STATE_INJ : HAL_DFSDM_FILTER_STATE_REG_INJ;
3784 }
3785
3786 /**
3787 * @brief This function allows to really stop injected conversion.
3788 * @param hdfsdm_filter DFSDM filter handle.
3789 * @retval None
3790 */
3791 static void DFSDM_InjConvStop(DFSDM_Filter_HandleTypeDef* hdfsdm_filter)
3792 {
3793 /* Disable DFSDM filter */
3794 hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_DFEN);
3795
3796 /* If injected trigger was synchronous, reset JSYNC bit in DFSDM_FLTCR1 register */
3797 if(hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_SYNC_TRIGGER)
3798 {
3799 hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_JSYNC);
3800 }
3801 else if(hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_EXT_TRIGGER)
3802 {
3803 /* Reset JEXTEN[1:0] bits in DFSDM_FLTCR1 register */
3804 hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_JEXTEN);
3805 }
3806
3807 /* Enable DFSDM filter */
3808 hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_DFEN;
3809
3810 /* If regular conversion was in progress, restart it */
3811 if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_REG_INJ) && \
3812 (hdfsdm_filter->RegularTrigger == DFSDM_FILTER_SW_TRIGGER))
3813 {
3814 hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_RSWSTART;
3815 }
3816
3817 /* Update remaining injected conversions */
3818 hdfsdm_filter->InjConvRemaining = (hdfsdm_filter->InjectedScanMode == ENABLE) ? \
3819 hdfsdm_filter->InjectedChannelsNbr : 1U;
3820
3821 /* Update DFSDM filter state */
3822 hdfsdm_filter->State = (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_INJ) ? \
3823 HAL_DFSDM_FILTER_STATE_READY : HAL_DFSDM_FILTER_STATE_REG;
3824 }
3825 /**
3826 * @}
3827 */
3828 /* End of private functions --------------------------------------------------*/
3829
3830 /**
3831 * @}
3832 */
3833 #endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */
3834 #endif /* HAL_DFSDM_MODULE_ENABLED */
3835 /**
3836 * @}
3837 */
3838
3839 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/