Mercurial > public > ostc4
annotate Small_CPU/Src/startup_stm32f4xx.S @ 859:d32901746950 Evo_2_23
Improvment battery charger visualization:
In the previous version the green flash (charge complete) was shown even battery had not reached 100% charge. Root cause was that the pin signaling the end of charge could be raised for other reasons then a full battery. The new version will show the green flash only in case the battery is rated as full.
In addition the graph visualization has been updated to continously progress. In the previous version it only progressed in case the charge value changed. Especially at charging start the charger is doing some battery evaluation which does not increase the charge state. In such a case the graph seemed to be frozen.
| author | Ideenmodellierer |
|---|---|
| date | Tue, 07 May 2024 21:20:33 +0200 |
| parents | 22864a24973b |
| children |
| rev | line source |
|---|---|
| 38 | 1 /* File: startup_ARMCM4.S |
| 2 * Purpose: startup file for Cortex-M4 devices. Should use with | |
| 3 * GCC for ARM Embedded Processors | |
| 4 * Version: V1.3 | |
| 5 * Date: 08 Feb 2012 | |
| 6 * | |
| 7 * Copyright (c) 2012, ARM Limited | |
| 8 * All rights reserved. | |
| 9 * | |
| 10 * Redistribution and use in source and binary forms, with or without | |
| 11 * modification, are permitted provided that the following conditions are met: | |
| 12 * Redistributions of source code must retain the above copyright | |
| 13 notice, this list of conditions and the following disclaimer. | |
| 14 * Redistributions in binary form must reproduce the above copyright | |
| 15 notice, this list of conditions and the following disclaimer in the | |
| 16 documentation and/or other materials provided with the distribution. | |
| 17 * Neither the name of the ARM Limited nor the | |
| 18 names of its contributors may be used to endorse or promote products | |
| 19 derived from this software without specific prior written permission. | |
| 20 * | |
| 21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND | |
| 22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED | |
| 23 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE | |
| 24 * DISCLAIMED. IN NO EVENT SHALL ARM LIMITED BE LIABLE FOR ANY | |
| 25 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES | |
| 26 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; | |
| 27 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND | |
| 28 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | |
| 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS | |
| 30 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | |
| 31 */ | |
| 32 .syntax unified | |
| 33 .arch armv7-m | |
| 34 | |
| 35 .section .stack | |
| 36 .align 3 | |
| 37 #ifdef __STACK_SIZE | |
| 38 .equ Stack_Size, __STACK_SIZE | |
| 39 #else | |
| 40 .equ Stack_Size, 0x400 | |
| 41 #endif | |
| 42 .globl __StackTop | |
| 43 .globl __StackLimit | |
| 44 __StackLimit: | |
| 45 .space Stack_Size | |
| 46 .size __StackLimit, . - __StackLimit | |
| 47 __StackTop: | |
| 48 .size __StackTop, . - __StackTop | |
| 49 | |
| 50 .section .heap | |
| 51 .align 3 | |
| 52 #ifdef __HEAP_SIZE | |
| 53 .equ Heap_Size, __HEAP_SIZE | |
| 54 #else | |
| 55 .equ Heap_Size, 0xC00 | |
| 56 #endif | |
| 57 .globl __HeapBase | |
| 58 .globl __HeapLimit | |
| 59 __HeapBase: | |
| 60 .if Heap_Size | |
| 61 .space Heap_Size | |
| 62 .endif | |
| 63 .size __HeapBase, . - __HeapBase | |
| 64 __HeapLimit: | |
| 65 .size __HeapLimit, . - __HeapLimit | |
| 66 | |
| 67 .section .isr_vector | |
| 68 .align 2 | |
| 69 .globl __isr_vector | |
| 70 __isr_vector: | |
| 71 .long __StackTop /* Top of Stack */ | |
| 72 .long Reset_Handler /* Reset Handler */ | |
| 73 .long NMI_Handler /* NMI Handler */ | |
| 74 .long HardFault_Handler /* Hard Fault Handler */ | |
| 75 .long MemManage_Handler /* MPU Fault Handler */ | |
| 76 .long BusFault_Handler /* Bus Fault Handler */ | |
| 77 .long UsageFault_Handler /* Usage Fault Handler */ | |
| 78 .long 0 /* Reserved */ | |
| 79 .long 0 /* Reserved */ | |
| 80 .long 0 /* Reserved */ | |
| 81 .long 0 /* Reserved */ | |
| 82 .long SVC_Handler /* SVCall Handler */ | |
| 83 .long DebugMon_Handler /* Debug Monitor Handler */ | |
| 84 .long 0 /* Reserved */ | |
| 85 .long PendSV_Handler /* PendSV Handler */ | |
| 86 .long SysTick_Handler /* SysTick Handler */ | |
| 87 | |
| 88 // External Interrupts | |
| 89 .long WWDG_IRQHandler // Window WatchDog | |
| 90 .long PVD_IRQHandler // PVD through EXTI Line detection | |
| 91 .long TAMP_STAMP_IRQHandler // Tamper and TimeStamps through the EXTI line | |
| 92 .long RTC_WKUP_IRQHandler // RTC Wakeup through the EXTI line | |
| 93 .long FLASH_IRQHandler // FLASH | |
| 94 .long RCC_IRQHandler // RCC | |
| 95 .long EXTI0_IRQHandler // EXTI Line0 | |
| 96 .long EXTI1_IRQHandler // EXTI Line1 | |
| 97 .long EXTI2_IRQHandler // EXTI Line2 | |
| 98 .long EXTI3_IRQHandler // EXTI Line3 | |
| 99 .long EXTI4_IRQHandler // EXTI Line4 | |
| 100 .long DMA1_Stream0_IRQHandler // DMA1 Stream 0 | |
| 101 .long DMA1_Stream1_IRQHandler // DMA1 Stream 1 | |
| 102 .long DMA1_Stream2_IRQHandler // DMA1 Stream 2 | |
| 103 .long DMA1_Stream3_IRQHandler // DMA1 Stream 3 | |
| 104 .long DMA1_Stream4_IRQHandler // DMA1 Stream 4 | |
| 105 .long DMA1_Stream5_IRQHandler // DMA1 Stream 5 | |
| 106 .long DMA1_Stream6_IRQHandler // DMA1 Stream 6 | |
| 107 .long ADC_IRQHandler // ADC1, ADC2 and ADC3s | |
| 108 .long CAN1_TX_IRQHandler // CAN1 TX | |
| 109 .long CAN1_RX0_IRQHandler // CAN1 RX0 | |
| 110 .long CAN1_RX1_IRQHandler // CAN1 RX1 | |
| 111 .long CAN1_SCE_IRQHandler // CAN1 SCE | |
| 112 .long EXTI9_5_IRQHandler // External Line[9:5]s | |
| 113 .long TIM1_BRK_TIM9_IRQHandler // TIM1 Break and TIM9 | |
| 114 .long TIM1_UP_TIM10_IRQHandler // TIM1 Update and TIM10 | |
| 115 .long TIM1_TRG_COM_TIM11_IRQHandler // TIM1 Trigger and Commutation and TIM11 | |
| 116 .long TIM1_CC_IRQHandler // TIM1 Capture Compare | |
| 117 .long TIM2_IRQHandler // TIM2 | |
| 118 .long TIM3_IRQHandler // TIM3 | |
| 119 .long TIM4_IRQHandler // TIM4 | |
| 120 .long I2C1_EV_IRQHandler // I2C1 Event | |
| 121 .long I2C1_ER_IRQHandler // I2C1 Error | |
| 122 .long I2C2_EV_IRQHandler // I2C2 Event | |
| 123 .long I2C2_ER_IRQHandler // I2C2 Error | |
| 124 .long SPI1_IRQHandler // SPI1 | |
| 125 .long SPI2_IRQHandler // SPI2 | |
| 126 .long USART1_IRQHandler // USART1 | |
| 127 .long USART2_IRQHandler // USART2 | |
| 128 .long USART3_IRQHandler // USART3 | |
| 129 .long EXTI15_10_IRQHandler // External Line[15:10]s | |
| 130 .long RTC_Alarm_IRQHandler // RTC Alarm (A and B) through EXTI Line | |
| 131 .long OTG_FS_WKUP_IRQHandler // USB OTG FS Wakeup through EXTI line | |
| 132 .long TIM8_BRK_TIM12_IRQHandler // TIM8 Break and TIM12 | |
| 133 .long TIM8_UP_TIM13_IRQHandler // TIM8 Update and TIM13 | |
| 134 .long TIM8_TRG_COM_TIM14_IRQHandler // TIM8 Trigger and Commutation and TIM14 | |
| 135 .long TIM8_CC_IRQHandler // TIM8 Capture Compare | |
| 136 .long DMA1_Stream7_IRQHandler // DMA1 Stream7 | |
| 137 .long FSMC_IRQHandler // FSMC | |
| 138 .long SDIO_IRQHandler // SDIO | |
| 139 .long TIM5_IRQHandler // TIM5 | |
| 140 .long SPI3_IRQHandler // SPI3 | |
| 141 .long UART4_IRQHandler // UART4 | |
| 142 .long UART5_IRQHandler // UART5 | |
| 143 .long TIM6_DAC_IRQHandler // TIM6 and DAC1&2 underrun errors | |
| 144 .long TIM7_IRQHandler // TIM7 | |
| 145 .long DMA2_Stream0_IRQHandler // DMA2 Stream 0 | |
| 146 .long DMA2_Stream1_IRQHandler // DMA2 Stream 1 | |
| 147 .long DMA2_Stream2_IRQHandler // DMA2 Stream 2 | |
| 148 .long DMA2_Stream3_IRQHandler // DMA2 Stream 3 | |
| 149 .long DMA2_Stream4_IRQHandler // DMA2 Stream 4 | |
| 150 .long ETH_IRQHandler // Ethernet | |
| 151 .long ETH_WKUP_IRQHandler // Ethernet Wakeup through EXTI line | |
| 152 .long CAN2_TX_IRQHandler // CAN2 TX | |
| 153 .long CAN2_RX0_IRQHandler // CAN2 RX0 | |
| 154 .long CAN2_RX1_IRQHandler // CAN2 RX1 | |
| 155 .long CAN2_SCE_IRQHandler // CAN2 SCE | |
| 156 .long OTG_FS_IRQHandler // USB OTG FS | |
| 157 .long DMA2_Stream5_IRQHandler // DMA2 Stream 5 | |
| 158 .long DMA2_Stream6_IRQHandler // DMA2 Stream 6 | |
| 159 .long DMA2_Stream7_IRQHandler // DMA2 Stream 7 | |
| 160 .long USART6_IRQHandler // USART6 | |
| 161 .long I2C3_EV_IRQHandler // I2C3 event | |
| 162 .long I2C3_ER_IRQHandler // I2C3 error | |
| 163 .long OTG_HS_EP1_OUT_IRQHandler // USB OTG HS End Point 1 Out | |
| 164 .long OTG_HS_EP1_IN_IRQHandler // USB OTG HS End Point 1 In | |
| 165 .long OTG_HS_WKUP_IRQHandler // USB OTG HS Wakeup through EXTI | |
| 166 .long OTG_HS_IRQHandler // USB OTG HS | |
| 167 .long DCMI_IRQHandler // DCMI | |
| 168 .long CRYP_IRQHandler // CRYP crypto | |
| 169 .long HASH_RNG_IRQHandler // Hash and Rng | |
| 170 .long FPU_IRQHandler // FPU | |
| 171 | |
| 172 .size __isr_vector, . - __isr_vector | |
| 173 | |
| 174 .text | |
| 175 .thumb | |
| 176 .thumb_func | |
| 177 .align 2 | |
| 178 .globl Reset_Handler | |
| 179 .type Reset_Handler, %function | |
| 180 Reset_Handler: | |
| 181 /* Loop to copy data from read only memory to RAM. The ranges | |
| 182 * of copy from/to are specified by following symbols evaluated in | |
| 183 * linker script. | |
| 184 * __etext: End of code section, i.e., begin of data sections to copy from. | |
| 185 * __data_start__/__data_end__: RAM address range that data should be | |
| 186 * copied to. Both must be aligned to 4 bytes boundary. */ | |
| 187 | |
|
41
22864a24973b
Non functional change just to use same symbols as CPU1
Ideenmodellierer
parents:
38
diff
changeset
|
188 ldr r1, =_sidata /*__etext*/ |
| 38 | 189 ldr r2, =__data_start__ |
| 190 ldr r3, =__data_end__ | |
| 191 | |
| 192 #if 1 | |
| 193 /* Here are two copies of loop implemenations. First one favors code size | |
| 194 * and the second one favors performance. Default uses the first one. | |
| 195 * Change to "#if 0" to use the second one */ | |
| 196 .flash_to_ram_loop: | |
| 197 cmp r2, r3 | |
| 198 ittt lt | |
| 199 ldrlt r0, [r1], #4 | |
| 200 strlt r0, [r2], #4 | |
| 201 blt .flash_to_ram_loop | |
| 202 #else | |
| 203 subs r3, r2 | |
| 204 ble .flash_to_ram_loop_end | |
| 205 .flash_to_ram_loop: | |
| 206 subs r3, #4 | |
| 207 ldr r0, [r1, r3] | |
| 208 str r0, [r2, r3] | |
| 209 bgt .flash_to_ram_loop | |
| 210 .flash_to_ram_loop_end: | |
| 211 #endif | |
| 212 | |
| 213 #ifndef __NO_SYSTEM_INIT | |
| 214 ldr r0, =SystemInit | |
| 215 blx r0 | |
| 216 #endif | |
| 217 | |
| 218 ldr r0, =_start | |
| 219 bx r0 | |
| 220 .pool | |
| 221 .size Reset_Handler, . - Reset_Handler | |
| 222 | |
| 223 /* Our weak _start alternative if we don't use the library _start | |
| 224 * The zero init section must be cleared, otherwise the librtary is | |
| 225 * doing that */ | |
| 226 .align 1 | |
| 227 .thumb_func | |
| 228 .weak _start | |
| 229 .type _start, %function | |
| 230 _start: | |
| 231 | |
| 232 /* Zero fill the bss segment. */ | |
| 233 ldr r1, = __bss_start__ | |
| 234 ldr r2, = __bss_end__ | |
| 235 movs r3, #0 | |
| 236 b .fill_zero_bss | |
| 237 .loop_zero_bss: | |
| 238 str r3, [r1], #4 | |
| 239 | |
| 240 .fill_zero_bss: | |
| 241 cmp r1, r2 | |
| 242 bcc .loop_zero_bss | |
| 243 | |
| 244 /* Jump to our main */ | |
| 245 bl main | |
| 246 b . | |
| 247 .size _start, . - _start | |
| 248 | |
| 249 /* Macro to define default handlers. Default handler | |
| 250 * will be weak symbol and just dead loops. They can be | |
| 251 * overwritten by other handlers */ | |
| 252 .macro def_irq_handler handler_name | |
| 253 .align 1 | |
| 254 .thumb_func | |
| 255 .weak \handler_name | |
| 256 .type \handler_name, %function | |
| 257 \handler_name : | |
| 258 b . | |
| 259 .size \handler_name, . - \handler_name | |
| 260 .endm | |
| 261 | |
| 262 def_irq_handler NMI_Handler | |
| 263 def_irq_handler HardFault_Handler | |
| 264 def_irq_handler MemManage_Handler | |
| 265 def_irq_handler BusFault_Handler | |
| 266 def_irq_handler UsageFault_Handler | |
| 267 def_irq_handler SVC_Handler | |
| 268 def_irq_handler DebugMon_Handler | |
| 269 def_irq_handler PendSV_Handler | |
| 270 def_irq_handler SysTick_Handler | |
| 271 def_irq_handler Default_Handler | |
| 272 | |
| 273 // External Interrupts | |
| 274 def_irq_handler WWDG_IRQHandler // Window WatchDog | |
| 275 def_irq_handler PVD_IRQHandler // PVD through EXTI Line detection | |
| 276 def_irq_handler TAMP_STAMP_IRQHandler // Tamper and TimeStamps through the EXTI line | |
| 277 def_irq_handler RTC_WKUP_IRQHandler // RTC Wakeup through the EXTI line | |
| 278 def_irq_handler FLASH_IRQHandler // FLASH | |
| 279 def_irq_handler RCC_IRQHandler // RCC | |
| 280 def_irq_handler EXTI0_IRQHandler // EXTI Line0 | |
| 281 def_irq_handler EXTI1_IRQHandler // EXTI Line1 | |
| 282 def_irq_handler EXTI2_IRQHandler // EXTI Line2 | |
| 283 def_irq_handler EXTI3_IRQHandler // EXTI Line3 | |
| 284 def_irq_handler EXTI4_IRQHandler // EXTI Line4 | |
| 285 def_irq_handler DMA1_Stream0_IRQHandler // DMA1 Stream 0 | |
| 286 def_irq_handler DMA1_Stream1_IRQHandler // DMA1 Stream 1 | |
| 287 def_irq_handler DMA1_Stream2_IRQHandler // DMA1 Stream 2 | |
| 288 def_irq_handler DMA1_Stream3_IRQHandler // DMA1 Stream 3 | |
| 289 def_irq_handler DMA1_Stream4_IRQHandler // DMA1 Stream 4 | |
| 290 def_irq_handler DMA1_Stream5_IRQHandler // DMA1 Stream 5 | |
| 291 def_irq_handler DMA1_Stream6_IRQHandler // DMA1 Stream 6 | |
| 292 def_irq_handler ADC_IRQHandler // ADC1, ADC2 and ADC3s | |
| 293 def_irq_handler CAN1_TX_IRQHandler // CAN1 TX | |
| 294 def_irq_handler CAN1_RX0_IRQHandler // CAN1 RX0 | |
| 295 def_irq_handler CAN1_RX1_IRQHandler // CAN1 RX1 | |
| 296 def_irq_handler CAN1_SCE_IRQHandler // CAN1 SCE | |
| 297 def_irq_handler EXTI9_5_IRQHandler // External Line[9:5]s | |
| 298 def_irq_handler TIM1_BRK_TIM9_IRQHandler // TIM1 Break and TIM9 | |
| 299 def_irq_handler TIM1_UP_TIM10_IRQHandler // TIM1 Update and TIM10 | |
| 300 def_irq_handler TIM1_TRG_COM_TIM11_IRQHandler // TIM1 Trigger and Commutation and TIM11 | |
| 301 def_irq_handler TIM1_CC_IRQHandler // TIM1 Capture Compare | |
| 302 def_irq_handler TIM2_IRQHandler // TIM2 | |
| 303 def_irq_handler TIM3_IRQHandler // TIM3 | |
| 304 def_irq_handler TIM4_IRQHandler // TIM4 | |
| 305 def_irq_handler I2C1_EV_IRQHandler // I2C1 Event | |
| 306 def_irq_handler I2C1_ER_IRQHandler // I2C1 Error | |
| 307 def_irq_handler I2C2_EV_IRQHandler // I2C2 Event | |
| 308 def_irq_handler I2C2_ER_IRQHandler // I2C2 Error | |
| 309 def_irq_handler SPI1_IRQHandler // SPI1 | |
| 310 def_irq_handler SPI2_IRQHandler // SPI2 | |
| 311 def_irq_handler USART1_IRQHandler // USART1 | |
| 312 def_irq_handler USART2_IRQHandler // USART2 | |
| 313 def_irq_handler USART3_IRQHandler // USART3 | |
| 314 def_irq_handler EXTI15_10_IRQHandler // External Line[15:10]s | |
| 315 def_irq_handler RTC_Alarm_IRQHandler // RTC Alarm (A and B) through EXTI Line | |
| 316 def_irq_handler OTG_FS_WKUP_IRQHandler // USB OTG FS Wakeup through EXTI line | |
| 317 def_irq_handler TIM8_BRK_TIM12_IRQHandler // TIM8 Break and TIM12 | |
| 318 def_irq_handler TIM8_UP_TIM13_IRQHandler // TIM8 Update and TIM13 | |
| 319 def_irq_handler TIM8_TRG_COM_TIM14_IRQHandler // TIM8 Trigger and Commutation and TIM14 | |
| 320 def_irq_handler TIM8_CC_IRQHandler // TIM8 Capture Compare | |
| 321 def_irq_handler DMA1_Stream7_IRQHandler // DMA1 Stream7 | |
| 322 def_irq_handler FSMC_IRQHandler // FSMC | |
| 323 def_irq_handler SDIO_IRQHandler // SDIO | |
| 324 def_irq_handler TIM5_IRQHandler // TIM5 | |
| 325 def_irq_handler SPI3_IRQHandler // SPI3 | |
| 326 def_irq_handler UART4_IRQHandler // UART4 | |
| 327 def_irq_handler UART5_IRQHandler // UART5 | |
| 328 def_irq_handler TIM6_DAC_IRQHandler // TIM6 and DAC1&2 underrun errors | |
| 329 def_irq_handler TIM7_IRQHandler // TIM7 | |
| 330 def_irq_handler DMA2_Stream0_IRQHandler // DMA2 Stream 0 | |
| 331 def_irq_handler DMA2_Stream1_IRQHandler // DMA2 Stream 1 | |
| 332 def_irq_handler DMA2_Stream2_IRQHandler // DMA2 Stream 2 | |
| 333 def_irq_handler DMA2_Stream3_IRQHandler // DMA2 Stream 3 | |
| 334 def_irq_handler DMA2_Stream4_IRQHandler // DMA2 Stream 4 | |
| 335 def_irq_handler ETH_IRQHandler // Ethernet | |
| 336 def_irq_handler ETH_WKUP_IRQHandler // Ethernet Wakeup through EXTI line | |
| 337 def_irq_handler CAN2_TX_IRQHandler // CAN2 TX | |
| 338 def_irq_handler CAN2_RX0_IRQHandler // CAN2 RX0 | |
| 339 def_irq_handler CAN2_RX1_IRQHandler // CAN2 RX1 | |
| 340 def_irq_handler CAN2_SCE_IRQHandler // CAN2 SCE | |
| 341 def_irq_handler OTG_FS_IRQHandler // USB OTG FS | |
| 342 def_irq_handler DMA2_Stream5_IRQHandler // DMA2 Stream 5 | |
| 343 def_irq_handler DMA2_Stream6_IRQHandler // DMA2 Stream 6 | |
| 344 def_irq_handler DMA2_Stream7_IRQHandler // DMA2 Stream 7 | |
| 345 def_irq_handler USART6_IRQHandler // USART6 | |
| 346 def_irq_handler I2C3_EV_IRQHandler // I2C3 event | |
| 347 def_irq_handler I2C3_ER_IRQHandler // I2C3 error | |
| 348 def_irq_handler OTG_HS_EP1_OUT_IRQHandler // USB OTG HS End Point 1 Out | |
| 349 def_irq_handler OTG_HS_EP1_IN_IRQHandler // USB OTG HS End Point 1 In | |
| 350 def_irq_handler OTG_HS_WKUP_IRQHandler // USB OTG HS Wakeup through EXTI | |
| 351 def_irq_handler OTG_HS_IRQHandler // USB OTG HS | |
| 352 def_irq_handler DCMI_IRQHandler // DCMI | |
| 353 def_irq_handler CRYP_IRQHandler // CRYP crypto | |
| 354 def_irq_handler HASH_RNG_IRQHandler // Hash and Rng | |
| 355 def_irq_handler FPU_IRQHandler // FPU | |
| 356 | |
| 357 .end |