Mercurial > public > ostc4
annotate Small_CPU/Src/uart.c @ 919:c0553dd70608 Evo_2_23
GNSS support for external UART interface:
An ubox gps module may now be connected to the external UART. Per default the functionality is disabled using the compile switch ENABLE_GNSS_SUPPORT
author | Ideenmodellierer |
---|---|
date | Sun, 03 Nov 2024 15:43:04 +0100 |
parents | f72613a152dd |
children | eb4109d7d1e9 |
rev | line source |
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38 | 1 /** |
2 ****************************************************************************** | |
3 * @file uart.c | |
4 * @author heinrichs weikamp gmbh | |
5 * @version V0.0.1 | |
6 * @date 27-March-2014 | |
7 * @brief button control | |
8 * | |
9 @verbatim | |
10 ============================================================================== | |
11 ##### How to use ##### | |
12 ============================================================================== | |
13 @endverbatim | |
14 ****************************************************************************** | |
15 * @attention | |
16 * | |
17 * <h2><center>© COPYRIGHT(c) 2015 heinrichs weikamp</center></h2> | |
18 * | |
19 ****************************************************************************** | |
20 */ | |
21 /* Includes ------------------------------------------------------------------*/ | |
22 #include "uart.h" | |
794 | 23 #include "uartProtocol_O2.h" |
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24 #include "uartProtocol_Co2.h" |
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25 #include "uartProtocol_Sentinel.h" |
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26 #include "uartProtocol_GNSS.h" |
662 | 27 #include "externalInterface.h" |
28 #include "data_exchange.h" | |
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29 #include <string.h> /* memset */ |
38 | 30 |
889 | 31 |
38 | 32 /* Private variables ---------------------------------------------------------*/ |
33 | |
794 | 34 |
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35 #define TX_BUF_SIZE (40u) /* max length for commands */ |
781 | 36 #define CHUNK_SIZE (25u) /* the DMA will handle chunk size transfers */ |
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37 #define CHUNKS_PER_BUFFER (6u) |
794 | 38 |
889 | 39 |
662 | 40 |
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41 DMA_HandleTypeDef hdma_usart1_rx, hdma_usart1_tx, hdma_usart6_rx, hdma_usart6_tx; |
38 | 42 |
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43 uint8_t rxBuffer[CHUNK_SIZE * CHUNKS_PER_BUFFER]; /* The complete buffer has a X * chunk size to allow variations in buffer read time */ |
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44 uint8_t txBuffer[CHUNK_SIZE]; /* tx uses less bytes */ |
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45 uint8_t txBufferQue[TX_BUF_SIZE]; /* In MUX mode command may be send shortly after each other => allow q 1 entry que */ |
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46 uint8_t txBufferQueLen; |
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47 |
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48 uint8_t rxBufferUart6[CHUNK_SIZE * CHUNKS_PER_BUFFER]; /* The complete buffer has a X * chunk size to allow variations in buffer read time */ |
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49 uint8_t txBufferUart6[CHUNK_SIZE * CHUNKS_PER_BUFFER]; /* The complete buffer has a X * chunk size to allow variations in buffer read time */ |
889 | 50 |
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51 static uint8_t rxWriteIndex; /* Index of the data item which is analysed */ |
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52 static uint8_t rxReadIndex; /* Index at which new data is stared */ |
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53 static uint8_t lastCmdIndex; /* Index of last command which has not been completely received */ |
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54 static uint8_t dmaRxActive; /* Indicator if DMA reception needs to be started */ |
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55 static uint8_t dmaTxActive; /* Indicator if DMA reception needs to be started */ |
794 | 56 |
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57 |
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58 static uint8_t isEndIndication(uint8_t index); |
889 | 59 |
38 | 60 /* Exported functions --------------------------------------------------------*/ |
61 | |
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62 void UART_clearRxBuffer(void) |
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63 { |
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64 uint16_t index = 0; |
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65 do |
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66 { |
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67 rxBuffer[index++] = BUFFER_NODATA_LOW; |
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68 rxBuffer[index++] = BUFFER_NODATA_HIGH; |
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69 } while (index < sizeof(rxBuffer)); |
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70 |
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71 rxReadIndex = 0; |
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72 rxWriteIndex = 0; |
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73 } |
794 | 74 |
662 | 75 void MX_USART1_UART_Init(void) |
38 | 76 { |
662 | 77 /* regular init */ |
78 huart1.Instance = USART1; | |
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79 huart1.Init.BaudRate = 19200; |
662 | 80 huart1.Init.WordLength = UART_WORDLENGTH_8B; |
81 huart1.Init.StopBits = UART_STOPBITS_1; | |
82 huart1.Init.Parity = UART_PARITY_NONE; | |
83 huart1.Init.Mode = UART_MODE_TX_RX; | |
84 huart1.Init.HwFlowCtl = UART_HWCONTROL_NONE; | |
85 huart1.Init.OverSampling = UART_OVERSAMPLING_16; | |
86 | |
87 HAL_UART_Init(&huart1); | |
88 | |
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89 MX_USART1_DMA_Init(); |
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90 |
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91 UART_clearRxBuffer(); |
662 | 92 rxReadIndex = 0; |
93 lastCmdIndex = 0; | |
94 rxWriteIndex = 0; | |
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95 dmaRxActive = 0; |
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96 dmaTxActive = 0; |
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97 txBufferQueLen = 0; |
662 | 98 } |
38 | 99 |
889 | 100 |
101 | |
662 | 102 void MX_USART1_UART_DeInit(void) |
103 { | |
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104 HAL_DMA_Abort(&hdma_usart1_rx); |
662 | 105 HAL_DMA_DeInit(&hdma_usart1_rx); |
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106 HAL_DMA_Abort(&hdma_usart1_tx); |
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107 HAL_DMA_DeInit(&hdma_usart1_tx); |
662 | 108 HAL_UART_DeInit(&huart1); |
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109 dmaRxActive = 0; |
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110 dmaTxActive = 0; |
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111 txBufferQueLen = 0; |
662 | 112 } |
113 | |
114 void MX_USART1_DMA_Init() | |
115 { | |
116 /* DMA controller clock enable */ | |
117 __DMA2_CLK_ENABLE(); | |
118 | |
119 /* Peripheral DMA init*/ | |
120 hdma_usart1_rx.Instance = DMA2_Stream5; | |
121 hdma_usart1_rx.Init.Channel = DMA_CHANNEL_4; | |
122 hdma_usart1_rx.Init.Direction = DMA_PERIPH_TO_MEMORY; //DMA_MEMORY_TO_PERIPH; | |
123 hdma_usart1_rx.Init.PeriphInc = DMA_PINC_DISABLE; | |
124 hdma_usart1_rx.Init.MemInc = DMA_MINC_ENABLE; | |
125 hdma_usart1_rx.Init.PeriphDataAlignment = DMA_MDATAALIGN_BYTE; | |
126 hdma_usart1_rx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE; | |
127 hdma_usart1_rx.Init.Mode = DMA_NORMAL; | |
128 hdma_usart1_rx.Init.Priority = DMA_PRIORITY_LOW; | |
129 hdma_usart1_rx.Init.FIFOMode = DMA_FIFOMODE_DISABLE; | |
130 HAL_DMA_Init(&hdma_usart1_rx); | |
131 | |
132 __HAL_LINKDMA(&huart1,hdmarx,hdma_usart1_rx); | |
133 | |
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134 hdma_usart1_tx.Instance = DMA2_Stream7; |
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135 hdma_usart1_tx.Init.Channel = DMA_CHANNEL_4; |
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136 hdma_usart1_tx.Init.Direction = DMA_MEMORY_TO_PERIPH; |
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137 hdma_usart1_tx.Init.PeriphInc = DMA_PINC_DISABLE; |
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138 hdma_usart1_tx.Init.MemInc = DMA_MINC_ENABLE; |
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139 hdma_usart1_tx.Init.PeriphDataAlignment = DMA_MDATAALIGN_BYTE; |
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140 hdma_usart1_tx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE; |
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141 hdma_usart1_tx.Init.Mode = DMA_NORMAL; |
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142 hdma_usart1_tx.Init.Priority = DMA_PRIORITY_LOW; |
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143 hdma_usart1_tx.Init.FIFOMode = DMA_FIFOMODE_DISABLE; |
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144 HAL_DMA_Init(&hdma_usart1_tx); |
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145 |
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146 __HAL_LINKDMA(&huart1,hdmatx,hdma_usart1_tx); |
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147 |
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148 |
662 | 149 /* DMA interrupt init */ |
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150 HAL_NVIC_SetPriority(DMA2_Stream5_IRQn, 2, 2); |
662 | 151 HAL_NVIC_EnableIRQ(DMA2_Stream5_IRQn); |
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152 HAL_NVIC_SetPriority(DMA2_Stream7_IRQn, 2, 1); |
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153 HAL_NVIC_EnableIRQ(DMA2_Stream7_IRQn); |
38 | 154 } |
155 | |
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156 |
889 | 157 void GNSS_IO_init() { |
158 | |
159 GPIO_InitTypeDef GPIO_InitStruct = { 0 }; | |
160 /* Peripheral clock enable */ | |
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161 __HAL_RCC_USART6_CLK_ENABLE() |
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162 ; |
889 | 163 |
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164 __HAL_RCC_GPIOA_CLK_ENABLE() |
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165 ; |
889 | 166 /**USART6 GPIO Configuration |
167 PA11 ------> USART6_TX | |
168 PA12 ------> USART6_RX | |
169 */ | |
170 GPIO_InitStruct.Pin = GPIO_PIN_11 | GPIO_PIN_12; | |
171 GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; | |
172 GPIO_InitStruct.Pull = GPIO_NOPULL; | |
894 | 173 GPIO_InitStruct.Speed = GPIO_SPEED_FAST; |
889 | 174 GPIO_InitStruct.Alternate = GPIO_AF8_USART6; |
175 HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); | |
176 | |
177 /* USART6 DMA Init */ | |
178 /* USART6_RX Init */ | |
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179 hdma_usart6_rx.Instance = DMA2_Stream1; |
889 | 180 hdma_usart6_rx.Init.Channel = DMA_CHANNEL_5; |
181 hdma_usart6_rx.Init.Direction = DMA_PERIPH_TO_MEMORY; | |
182 hdma_usart6_rx.Init.PeriphInc = DMA_PINC_DISABLE; | |
183 hdma_usart6_rx.Init.MemInc = DMA_MINC_ENABLE; | |
894 | 184 hdma_usart6_rx.Init.PeriphDataAlignment = DMA_MDATAALIGN_BYTE; |
889 | 185 hdma_usart6_rx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE; |
186 hdma_usart6_rx.Init.Mode = DMA_NORMAL; | |
187 hdma_usart6_rx.Init.Priority = DMA_PRIORITY_LOW; | |
188 hdma_usart6_rx.Init.FIFOMode = DMA_FIFOMODE_DISABLE; | |
189 HAL_DMA_Init(&hdma_usart6_rx); | |
190 | |
191 __HAL_LINKDMA(&huart6, hdmarx, hdma_usart6_rx); | |
192 | |
193 /* USART6_TX Init */ | |
194 hdma_usart6_tx.Instance = DMA2_Stream6; | |
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195 hdma_usart6_tx.Init.Channel = DMA_CHANNEL_6; |
889 | 196 hdma_usart6_tx.Init.Direction = DMA_MEMORY_TO_PERIPH; |
197 hdma_usart6_tx.Init.PeriphInc = DMA_PINC_DISABLE; | |
198 hdma_usart6_tx.Init.MemInc = DMA_MINC_ENABLE; | |
894 | 199 hdma_usart6_tx.Init.PeriphDataAlignment = DMA_MDATAALIGN_BYTE; |
889 | 200 hdma_usart6_tx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE; |
201 hdma_usart6_tx.Init.Mode = DMA_NORMAL; | |
202 hdma_usart6_tx.Init.Priority = DMA_PRIORITY_LOW; | |
203 hdma_usart6_tx.Init.FIFOMode = DMA_FIFOMODE_DISABLE; | |
204 HAL_DMA_Init(&hdma_usart6_tx); | |
205 | |
206 __HAL_LINKDMA(&huart6, hdmatx, hdma_usart6_tx); | |
207 | |
208 /* USART6 interrupt Init */ | |
209 HAL_NVIC_SetPriority(USART6_IRQn, 0, 0); | |
210 HAL_NVIC_EnableIRQ(USART6_IRQn); | |
211 | |
212 MX_USART6_DMA_Init(); | |
213 | |
214 } | |
215 | |
216 void MX_USART6_DMA_Init() { | |
217 /* DMA controller clock enable */ | |
218 __HAL_RCC_DMA2_CLK_ENABLE(); | |
219 | |
220 /* DMA interrupt init */ | |
221 /* DMA2_Stream2_IRQn interrupt configuration */ | |
222 HAL_NVIC_SetPriority(DMA2_Stream2_IRQn, 0, 0); | |
223 HAL_NVIC_EnableIRQ(DMA2_Stream2_IRQn); | |
224 /* DMA2_Stream6_IRQn interrupt configuration */ | |
225 HAL_NVIC_SetPriority(DMA2_Stream6_IRQn, 0, 0); | |
226 HAL_NVIC_EnableIRQ(DMA2_Stream6_IRQn); | |
227 } | |
228 | |
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229 |
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230 void MX_USART6_UART_DeInit(void) |
889 | 231 { |
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232 HAL_DMA_Abort(&hdma_usart6_rx); |
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233 HAL_DMA_DeInit(&hdma_usart6_rx); |
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234 HAL_DMA_Abort(&hdma_usart6_tx); |
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235 HAL_DMA_DeInit(&hdma_usart6_tx); |
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236 HAL_UART_DeInit(&huart6); |
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237 HAL_UART_DeInit(&huart6); |
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238 } |
889 | 239 |
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240 void MX_USART6_UART_Init(void) { |
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241 huart6.Instance = USART6; |
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242 huart6.Init.BaudRate = 9600; |
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243 huart6.Init.WordLength = UART_WORDLENGTH_8B; |
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244 huart6.Init.StopBits = UART_STOPBITS_1; |
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245 huart6.Init.Parity = UART_PARITY_NONE; |
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246 huart6.Init.Mode = UART_MODE_TX_RX; |
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247 huart6.Init.HwFlowCtl = UART_HWCONTROL_NONE; |
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248 huart6.Init.OverSampling = UART_OVERSAMPLING_16; |
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249 HAL_UART_Init(&huart6); |
889 | 250 } |
251 | |
794 | 252 void UART_MUX_SelectAddress(uint8_t muxAddress) |
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253 { |
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254 uint8_t indexstr[4]; |
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255 |
794 | 256 if(muxAddress <= MAX_MUX_CHANNEL) |
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257 { |
794 | 258 indexstr[0] = '~'; |
259 indexstr[1] = muxAddress; | |
260 indexstr[2] = 0x0D; | |
261 indexstr[3] = 0x0A; | |
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262 if(!dmaTxActive) |
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263 { |
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264 memcpy(txBuffer, indexstr, 4); |
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265 dmaTxActive = 0; |
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266 if(HAL_OK == HAL_UART_Transmit_DMA(&huart1,txBuffer,4)) |
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267 { |
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268 dmaTxActive = 1; |
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269 while(dmaTxActive) |
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270 { |
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271 HAL_Delay(1); |
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272 } |
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273 } |
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274 } |
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275 else |
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276 { |
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277 memcpy(txBufferQue, indexstr, 4); |
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278 txBufferQueLen = 4; |
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279 } |
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280 } |
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281 } |
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282 |
794 | 283 |
284 void UART_SendCmdString(uint8_t *cmdString) | |
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285 { |
794 | 286 uint8_t cmdLength = strlen((char*)cmdString); |
287 | |
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288 if(dmaTxActive == 0) |
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289 { |
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290 if(cmdLength < TX_BUF_SIZE) /* A longer string is an indication for a missing 0 termination */ |
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291 { |
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292 if(dmaRxActive == 0) |
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293 { |
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294 UART_StartDMA_Receiption(); |
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295 } |
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296 memcpy(txBuffer, cmdString, cmdLength); |
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297 if(HAL_OK == HAL_UART_Transmit_DMA(&huart1,txBuffer,cmdLength)) |
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298 { |
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299 dmaTxActive = 1; |
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300 } |
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301 } |
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302 } |
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303 else |
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304 { |
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305 memcpy(txBufferQue, cmdString, cmdLength); |
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306 txBufferQueLen = cmdLength; |
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307 } |
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308 } |
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309 |
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310 void UART_SendCmdUbx(uint8_t *cmd, uint8_t len) |
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311 { |
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312 if(len < TX_BUF_SIZE) /* A longer string is an indication for a missing 0 termination */ |
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313 { |
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314 if(dmaRxActive == 0) |
794 | 315 { |
316 UART_StartDMA_Receiption(); | |
317 } | |
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318 memcpy(txBuffer, cmd, len); |
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319 if(HAL_OK == HAL_UART_Transmit_DMA(&huart1,txBuffer,len)) |
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320 { |
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321 dmaTxActive = 1; |
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322 } |
794 | 323 } |
324 } | |
325 | |
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326 |
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327 void StringToInt(char *pstr, uint32_t *puInt32) |
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328 { |
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329 uint8_t index = 0; |
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330 uint32_t result = 0; |
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331 while((pstr[index] >= '0') && (pstr[index] <= '9')) |
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332 { |
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333 result *=10; |
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334 result += pstr[index] - '0'; |
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335 index++; |
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336 } |
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337 *puInt32 = result; |
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338 } |
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339 |
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340 void StringToUInt64(char *pstr, uint64_t *puint64) |
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341 { |
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342 uint8_t index = 0; |
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343 uint64_t result = 0; |
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344 while((pstr[index] >= '0') && (pstr[index] <= '9')) |
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345 { |
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346 result *=10; |
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347 result += pstr[index] - '0'; |
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348 index++; |
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349 } |
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350 *puint64 = result; |
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351 } |
662 | 352 |
742 | 353 void UART_StartDMA_Receiption() |
354 { | |
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355 if(dmaRxActive == 0) |
742 | 356 { |
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357 if(((rxWriteIndex / CHUNK_SIZE) != (rxReadIndex / CHUNK_SIZE)) || ((isEndIndication(rxWriteIndex)) && (isEndIndication(rxWriteIndex + 1)))) /* start next transfer if we did not catch up with read index */ |
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358 { |
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359 if(HAL_OK == HAL_UART_Receive_DMA (&huart1, &rxBuffer[rxWriteIndex], CHUNK_SIZE)) |
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360 { |
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361 dmaRxActive = 1; |
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362 } |
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363 } |
742 | 364 } |
365 } | |
690 | 366 |
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367 void UART_ChangeBaudrate(uint32_t newBaudrate) |
38 | 368 { |
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369 MX_USART1_UART_DeInit(); |
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370 huart1.Init.BaudRate = newBaudrate; |
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371 HAL_UART_Init(&huart1); |
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372 MX_USART1_DMA_Init(); |
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373 HAL_NVIC_SetPriority(USART1_IRQn, 1, 3); |
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374 HAL_NVIC_EnableIRQ(USART1_IRQn); |
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375 |
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376 UART_clearRxBuffer(); |
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377 rxReadIndex = 0; |
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378 rxWriteIndex = 0; |
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379 dmaRxActive = 0; |
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380 txBufferQueLen = 0; |
38 | 381 } |
690 | 382 |
662 | 383 void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart) |
38 | 384 { |
662 | 385 if(huart == &huart1) |
386 { | |
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387 dmaRxActive = 0; |
662 | 388 rxWriteIndex+=CHUNK_SIZE; |
389 if(rxWriteIndex >= CHUNK_SIZE * CHUNKS_PER_BUFFER) | |
390 { | |
391 rxWriteIndex = 0; | |
392 } | |
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393 UART_StartDMA_Receiption(); |
662 | 394 } |
38 | 395 } |
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396 void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart) |
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397 { |
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398 if(huart == &huart1) |
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399 { |
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400 dmaTxActive = 0; |
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401 UART_WriteData(); |
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402 if(txBufferQueLen) |
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403 { |
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404 memcpy(txBuffer, txBufferQue, txBufferQueLen); |
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405 HAL_UART_Transmit_DMA(&huart1,txBuffer,txBufferQueLen); |
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406 dmaTxActive = 1; |
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407 txBufferQueLen = 0; |
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408 } |
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409 } |
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410 } |
38 | 411 |
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412 uint8_t isEndIndication(uint8_t index) |
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413 { |
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414 uint8_t ret = 0; |
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415 if(index % 2) |
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416 { |
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417 if(rxBuffer[index] == BUFFER_NODATA_HIGH) |
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418 { |
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419 ret = 1; |
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420 } |
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421 } |
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422 else |
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423 { |
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424 if(rxBuffer[index] == BUFFER_NODATA_LOW) |
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425 { |
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426 ret = 1; |
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427 } |
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428 } |
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429 |
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430 return ret; |
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431 } |
794 | 432 void UART_ReadData(uint8_t sensorType) |
433 { | |
434 uint8_t localRX = rxReadIndex; | |
916
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435 uint8_t futureIndex = rxReadIndex + 1; |
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436 uint8_t moreData = 0; |
38 | 437 |
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438 if(futureIndex >= CHUNK_SIZE * CHUNKS_PER_BUFFER) |
794 | 439 { |
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440 futureIndex = 0; |
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441 } |
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442 |
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443 if((!isEndIndication(localRX)) || (!isEndIndication(futureIndex))) do |
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444 { |
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445 while((!isEndIndication(localRX)) || (moreData)) |
794 | 446 { |
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447 moreData = 0; |
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448 switch (sensorType) |
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449 { |
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450 case SENSOR_MUX: |
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451 case SENSOR_DIGO2: uartO2_ProcessData(rxBuffer[localRX]); |
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452 break; |
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453 #ifdef ENABLE_CO2_SUPPORT |
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454 case SENSOR_CO2: uartCo2_ProcessData(rxBuffer[localRX]); |
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455 break; |
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456 #endif |
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457 #ifdef ENABLE_GNSS_SUPPORT |
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458 case SENSOR_GNSS: uartGnss_ProcessData(rxBuffer[localRX]); |
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459 break; |
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460 #endif |
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461 #ifdef ENABLE_SENTINEL_MODE |
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462 case SENSOR_SENTINEL: uartSentinel_ProcessData(rxBuffer[localRX]); |
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463 break; |
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464 #endif |
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465 default: |
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466 break; |
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467 } |
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468 if(localRX % 2) |
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469 { |
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470 rxBuffer[localRX] = BUFFER_NODATA_HIGH; |
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471 } |
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472 else |
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473 { |
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474 rxBuffer[localRX] = BUFFER_NODATA_LOW; |
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475 } |
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476 |
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477 localRX++; |
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478 rxReadIndex++; |
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479 if(rxReadIndex >= CHUNK_SIZE * CHUNKS_PER_BUFFER) |
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480 { |
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481 localRX = 0; |
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482 rxReadIndex = 0; |
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483 } |
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484 futureIndex++; |
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485 if(futureIndex >= CHUNK_SIZE * CHUNKS_PER_BUFFER) |
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486 { |
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487 futureIndex = 0; |
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488 } |
794 | 489 } |
916
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490 if(!isEndIndication(futureIndex)) |
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491 { |
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492 moreData = 1; |
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493 } |
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494 } while(moreData); |
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495 } |
794 | 496 |
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497 void UART_WriteData(void) |
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498 { |
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499 if(huart1.hdmatx->State == HAL_DMA_STATE_READY) |
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500 { |
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501 huart1.gState = HAL_UART_STATE_READY; |
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502 dmaTxActive = 0; |
794 | 503 } |
918
f72613a152dd
Switch external interface tx communication to DMA:
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diff
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504 if(huart1.hdmarx->State == HAL_DMA_STATE_READY) |
f72613a152dd
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|
505 { |
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Switch external interface tx communication to DMA:
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506 huart1.RxState = HAL_UART_STATE_READY; |
f72613a152dd
Switch external interface tx communication to DMA:
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507 dmaRxActive = 0; |
f72613a152dd
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508 } |
794 | 509 } |
510 | |
511 void UART_FlushRxBuffer(void) | |
512 { | |
916
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513 uint8_t futureIndex = rxReadIndex + 1; |
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514 |
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515 if(futureIndex >= CHUNK_SIZE * CHUNKS_PER_BUFFER) |
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516 { |
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517 futureIndex = 0; |
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|
518 } |
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519 while((rxBuffer[rxReadIndex] != BUFFER_NODATA_LOW) && (rxBuffer[futureIndex] != BUFFER_NODATA_HIGH)) |
794 | 520 { |
916
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521 if(rxReadIndex % 2) |
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|
522 { |
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523 rxBuffer[rxReadIndex++] = BUFFER_NODATA_HIGH; |
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524 } |
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|
525 else |
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|
526 { |
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527 rxBuffer[rxReadIndex++] = BUFFER_NODATA_LOW; |
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528 } |
794 | 529 if(rxReadIndex >= CHUNK_SIZE * CHUNKS_PER_BUFFER) |
530 { | |
531 rxReadIndex = 0; | |
532 } | |
916
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533 futureIndex++; |
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|
534 if(futureIndex >= CHUNK_SIZE * CHUNKS_PER_BUFFER) |
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diff
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|
535 { |
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|
536 futureIndex = 0; |
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537 } |
794 | 538 } |
539 } | |
662 | 540 |
861 | 541 uint8_t UART_isComActive(uint8_t sensorId) |
542 { | |
543 uint8_t active = 1; | |
809 | 544 |
861 | 545 uint8_t ComState = externalInterface_GetSensorState(sensorId + EXT_INTERFACE_MUX_OFFSET); |
546 | |
916
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547 if((ComState == UART_COMMON_INIT) || (ComState == UART_COMMON_IDLE) || (ComState == UART_COMMON_ERROR) || (ComState == COMMON_SENSOR_STATE_INVALID)) |
861 | 548 { |
549 active = 0; | |
550 } | |
551 return active; | |
552 } | |
809 | 553 |
38 | 554 /************************ (C) COPYRIGHT heinrichs weikamp *****END OF FILE****/ |