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38
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1 /**
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2 ******************************************************************************
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3 * @file stm32f4xx_hal_i2s_ex.c
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4 * @author MCD Application Team
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5 * @version V1.2.0
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6 * @date 26-December-2014
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7 * @brief I2S HAL module driver.
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8 * This file provides firmware functions to manage the following
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9 * functionalities of I2S extension peripheral:
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10 * + Extension features Functions
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11 *
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12 @verbatim
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13 ==============================================================================
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14 ##### I2S Extension features #####
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15 ==============================================================================
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16 [..]
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17 (#) In I2S full duplex mode, each SPI peripheral is able to manage sending and receiving
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18 data simultaneously using two data lines. Each SPI peripheral has an extended block
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19 called I2Sxext (i.e I2S2ext for SPI2 and I2S3ext for SPI3).
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20 (#) The extension block is not a full SPI IP, it is used only as I2S slave to
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21 implement full duplex mode. The extension block uses the same clock sources
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22 as its master.
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23
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24 (#) Both I2Sx and I2Sx_ext can be configured as transmitters or receivers.
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25
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26 [..]
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27 (@) Only I2Sx can deliver SCK and WS to I2Sx_ext in full duplex mode, where
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28 I2Sx can be I2S2 or I2S3.
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29
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30 ##### How to use this driver #####
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31 ===============================================================================
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32 [..]
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33 Three operation modes are available within this driver :
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34
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35 *** Polling mode IO operation ***
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36 =================================
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37 [..]
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38 (+) Send and receive in the same time an amount of data in blocking mode using HAL_I2S_TransmitReceive()
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39
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40 *** Interrupt mode IO operation ***
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41 ===================================
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42 [..]
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43 (+) Send and receive in the same time an amount of data in non blocking mode using HAL_I2S_TransmitReceive_IT()
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44 (+) At transmission end of half transfer HAL_I2S_TxHalfCpltCallback is executed and user can
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45 add his own code by customization of function pointer HAL_I2S_TxHalfCpltCallback
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46 (+) At transmission end of transfer HAL_I2S_TxCpltCallback is executed and user can
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47 add his own code by customization of function pointer HAL_I2S_TxCpltCallback
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48 (+) At reception end of half transfer HAL_I2S_RxHalfCpltCallback is executed and user can
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49 add his own code by customization of function pointer HAL_I2S_RxHalfCpltCallback
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50 (+) At reception end of transfer HAL_I2S_RxCpltCallback is executed and user can
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51 add his own code by customization of function pointer HAL_I2S_RxCpltCallback
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52 (+) In case of transfer Error, HAL_I2S_ErrorCallback() function is executed and user can
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53 add his own code by customization of function pointer HAL_I2S_ErrorCallback
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54
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55 *** DMA mode IO operation ***
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56 ==============================
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57 [..]
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58 (+) Send and receive an amount of data in non blocking mode (DMA) using HAL_I2S_TransmitReceive_DMA()
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59 (+) At transmission end of half transfer HAL_I2S_TxHalfCpltCallback is executed and user can
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60 add his own code by customization of function pointer HAL_I2S_TxHalfCpltCallback
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61 (+) At transmission end of transfer HAL_I2S_TxCpltCallback is executed and user can
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62 add his own code by customization of function pointer HAL_I2S_TxCpltCallback
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63 (+) At reception end of half transfer HAL_I2S_RxHalfCpltCallback is executed and user can
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64 add his own code by customization of function pointer HAL_I2S_RxHalfCpltCallback
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65 (+) At reception end of transfer HAL_I2S_RxCpltCallback is executed and user can
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66 add his own code by customization of function pointer HAL_I2S_RxCpltCallback
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67 (+) In case of transfer Error, HAL_I2S_ErrorCallback() function is executed and user can
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68 add his own code by customization of function pointer HAL_I2S_ErrorCallback
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69 (+) Pause the DMA Transfer using HAL_I2S_DMAPause()
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70 (+) Resume the DMA Transfer using HAL_I2S_DMAResume()
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71 (+) Stop the DMA Transfer using HAL_I2S_DMAStop()
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72
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73 @endverbatim
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74 ******************************************************************************
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75 * @attention
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76 *
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77 * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
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78 *
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79 * Redistribution and use in source and binary forms, with or without modification,
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80 * are permitted provided that the following conditions are met:
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81 * 1. Redistributions of source code must retain the above copyright notice,
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82 * this list of conditions and the following disclaimer.
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83 * 2. Redistributions in binary form must reproduce the above copyright notice,
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84 * this list of conditions and the following disclaimer in the documentation
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85 * and/or other materials provided with the distribution.
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86 * 3. Neither the name of STMicroelectronics nor the names of its contributors
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87 * may be used to endorse or promote products derived from this software
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88 * without specific prior written permission.
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89 *
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90 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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91 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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92 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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93 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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94 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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95 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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96 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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97 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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98 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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99 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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100 *
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101 ******************************************************************************
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102 */
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103
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104 /* Includes ------------------------------------------------------------------*/
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105 #include "stm32f4xx_hal.h"
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106
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107 /** @addtogroup STM32F4xx_HAL_Driver
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108 * @{
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109 */
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110
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111 /** @defgroup I2SEx I2SEx
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112 * @brief I2S HAL module driver
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113 * @{
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114 */
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115
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116 #ifdef HAL_I2S_MODULE_ENABLED
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117
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118 /* Private typedef -----------------------------------------------------------*/
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119 /* Private define ------------------------------------------------------------*/
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120 /* Private macro -------------------------------------------------------------*/
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121 /* Private variables ---------------------------------------------------------*/
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122 /* Private function prototypes -----------------------------------------------*/
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123 /* Private functions ---------------------------------------------------------*/
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124 /** @addtogroup I2SEx_Private_Functions
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125 * @{
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126 */
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127 /**
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128 * @}
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129 */
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130
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131 /* Exported functions --------------------------------------------------------*/
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132 /** @defgroup I2SEx_Exported_Functions I2S Exported Functions
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133 * @{
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134 */
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135
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136 /** @defgroup I2SEx_Group1 Extension features functions
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137 * @brief Extension features functions
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138 *
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139 @verbatim
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140 ===============================================================================
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141 ##### Extension features Functions #####
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142 ===============================================================================
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143 [..]
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144 This subsection provides a set of functions allowing to manage the I2S data
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145 transfers.
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146
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147 (#) There are two modes of transfer:
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148 (++) Blocking mode : The communication is performed in the polling mode.
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149 The status of all data processing is returned by the same function
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150 after finishing transfer.
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151 (++) No-Blocking mode : The communication is performed using Interrupts
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152 or DMA. These functions return the status of the transfer startup.
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153 The end of the data processing will be indicated through the
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154 dedicated I2S IRQ when using Interrupt mode or the DMA IRQ when
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155 using DMA mode.
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156
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157 (#) Blocking mode functions are :
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158 (++) HAL_I2S_TransmitReceive()
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159
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160 (#) No-Blocking mode functions with Interrupt are :
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161 (++) HAL_I2S_TransmitReceive_IT()
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162
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163 (#) No-Blocking mode functions with DMA are :
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164 (++) HAL_I2S_TransmitReceive_DMA()
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165
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166 (#) A set of Transfer Complete Callbacks are provided in non Blocking mode:
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167 (++) HAL_I2S_TxCpltCallback()
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168 (++) HAL_I2S_RxCpltCallback()
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169 (++) HAL_I2S_ErrorCallback()
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170
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171 @endverbatim
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172 * @{
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173 */
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174
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175 /**
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176 * @brief Full-Duplex Transmit/Receive data in blocking mode.
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177 * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
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178 * the configuration information for I2S module
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179 * @param pTxData: a 16-bit pointer to the Transmit data buffer.
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180 * @param pRxData: a 16-bit pointer to the Receive data buffer.
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181 * @param Size: number of data sample to be sent:
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182 * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
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183 * configuration phase, the Size parameter means the number of 16-bit data length
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184 * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
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185 * the Size parameter means the number of 16-bit data length.
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186 * @param Timeout: Timeout duration
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187 * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
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188 * between Master and Slave(example: audio streaming).
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189 * @retval HAL status
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190 */
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191 HAL_StatusTypeDef HAL_I2SEx_TransmitReceive(I2S_HandleTypeDef *hi2s, uint16_t *pTxData, uint16_t *pRxData, uint16_t Size, uint32_t Timeout)
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192 {
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193 uint32_t tickstart = 0;
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194 uint32_t tmp1 = 0, tmp2 = 0;
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195
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196 if((pTxData == NULL ) || (pRxData == NULL ) || (Size == 0))
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197 {
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198 return HAL_ERROR;
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199 }
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200
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201 /* Check the I2S State */
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202 if(hi2s->State == HAL_I2S_STATE_READY)
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203 {
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204 tmp1 = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);
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205 tmp2 = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);
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206 /* Check the Data format: When a 16-bit data frame or a 16-bit data frame extended
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207 is selected during the I2S configuration phase, the Size parameter means the number
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208 of 16-bit data length in the transaction and when a 24-bit data frame or a 32-bit data
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209 frame is selected the Size parameter means the number of 16-bit data length. */
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210 if((tmp1 == I2S_DATAFORMAT_24B)|| \
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211 (tmp2 == I2S_DATAFORMAT_32B))
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212 {
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213 hi2s->TxXferSize = Size*2;
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214 hi2s->TxXferCount = Size*2;
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215 hi2s->RxXferSize = Size*2;
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216 hi2s->RxXferCount = Size*2;
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217 }
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218 else
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219 {
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220 hi2s->TxXferSize = Size;
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221 hi2s->TxXferCount = Size;
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222 hi2s->RxXferSize = Size;
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223 hi2s->RxXferCount = Size;
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224 }
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225
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226 /* Process Locked */
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227 __HAL_LOCK(hi2s);
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228
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229 /* Set the I2S State busy TX/RX */
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230 hi2s->State = HAL_I2S_STATE_BUSY_TX_RX;
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231
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232 tmp1 = hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG;
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233 tmp2 = hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG;
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234 /* Check if the I2S_MODE_MASTER_TX or I2S_MODE_SLAVE_TX Mode is selected */
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235 if((tmp1 == I2S_MODE_MASTER_TX) || (tmp2 == I2S_MODE_SLAVE_TX))
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236 {
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237 /* Check if the I2S is already enabled: The I2S is kept enabled at the end of transaction
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238 to avoid the clock de-synchronization between Master and Slave. */
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239 if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
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240 {
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241 /* Enable I2Sext(receiver) before enabling I2Sx peripheral */
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242 I2SxEXT(hi2s->Instance)->I2SCFGR |= SPI_I2SCFGR_I2SE;
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243
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244 /* Enable I2Sx peripheral */
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245 __HAL_I2S_ENABLE(hi2s);
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246 }
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247
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248 while(hi2s->TxXferCount > 0)
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249 {
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250 /* Wait until TXE flag is set */
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251 if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_TXE, RESET, Timeout) != HAL_OK)
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252 {
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253 return HAL_TIMEOUT;
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254 }
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255 hi2s->Instance->DR = (*pTxData++);
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256
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257 /* Get tick */
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258 tickstart = HAL_GetTick();
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259
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260 /* Wait until RXNE flag is set */
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261 while((I2SxEXT(hi2s->Instance)->SR & SPI_SR_RXNE) != SPI_SR_RXNE)
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262 {
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263 if(Timeout != HAL_MAX_DELAY)
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264 {
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265 if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
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266 {
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267 /* Process Unlocked */
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268 __HAL_UNLOCK(hi2s);
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269
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270 return HAL_TIMEOUT;
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271 }
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272 }
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273 }
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274 (*pRxData++) = I2SxEXT(hi2s->Instance)->DR;
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275
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276 hi2s->TxXferCount--;
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277 hi2s->RxXferCount--;
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278 }
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279 }
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280 /* The I2S_MODE_MASTER_RX or I2S_MODE_SLAVE_RX Mode is selected */
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281 else
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282 {
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283 /* Check if the I2S is already enabled */
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284 if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
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285 {
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286 /* Enable I2S peripheral before the I2Sext*/
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287 __HAL_I2S_ENABLE(hi2s);
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288
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289 /* Enable I2Sext(transmitter) after enabling I2Sx peripheral */
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290 I2SxEXT(hi2s->Instance)->I2SCFGR |= SPI_I2SCFGR_I2SE;
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291 }
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292 else
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293 {
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294 /* Check if Master Receiver mode is selected */
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295 if((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_MASTER_RX)
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296 {
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297 /* Clear the Overrun Flag by a read operation on the SPI_DR register followed by a read
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298 access to the SPI_SR register. */
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299 __HAL_I2S_CLEAR_OVRFLAG(hi2s);
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300 }
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301 }
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302 while(hi2s->TxXferCount > 0)
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303 {
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304 /* Get tick */
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305 tickstart = HAL_GetTick();
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306
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307 /* Wait until TXE flag is set */
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308 while((I2SxEXT(hi2s->Instance)->SR & SPI_SR_TXE) != SPI_SR_TXE)
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309 {
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310 if(Timeout != HAL_MAX_DELAY)
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311 {
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312 if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
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313 {
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314 /* Process Unlocked */
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315 __HAL_UNLOCK(hi2s);
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316
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317 return HAL_TIMEOUT;
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318 }
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319 }
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320 }
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321 I2SxEXT(hi2s->Instance)->DR = (*pTxData++);
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322
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323 /* Wait until RXNE flag is set */
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324 if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_RXNE, RESET, Timeout) != HAL_OK)
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325 {
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326 return HAL_TIMEOUT;
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327 }
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328 (*pRxData++) = hi2s->Instance->DR;
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329
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330 hi2s->TxXferCount--;
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331 hi2s->RxXferCount--;
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332 }
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333 }
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334
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335 /* Set the I2S State ready */
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336 hi2s->State = HAL_I2S_STATE_READY;
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337
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338 /* Process Unlocked */
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339 __HAL_UNLOCK(hi2s);
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340
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341 return HAL_OK;
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342 }
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343 else
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344 {
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345 return HAL_BUSY;
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346 }
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347 }
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348
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349 /**
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350 * @brief Full-Duplex Transmit/Receive data in non-blocking mode using Interrupt
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351 * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
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352 * the configuration information for I2S module
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353 * @param pTxData: a 16-bit pointer to the Transmit data buffer.
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354 * @param pRxData: a 16-bit pointer to the Receive data buffer.
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355 * @param Size: number of data sample to be sent:
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356 * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
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357 * configuration phase, the Size parameter means the number of 16-bit data length
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358 * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
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359 * the Size parameter means the number of 16-bit data length.
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360 * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
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361 * between Master and Slave(example: audio streaming).
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362 * @retval HAL status
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363 */
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364 HAL_StatusTypeDef HAL_I2SEx_TransmitReceive_IT(I2S_HandleTypeDef *hi2s, uint16_t *pTxData, uint16_t *pRxData, uint16_t Size)
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365 {
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366 uint32_t tmp1 = 0, tmp2 = 0;
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367
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368 if(hi2s->State == HAL_I2S_STATE_READY)
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369 {
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370 if((pTxData == NULL ) || (pRxData == NULL ) || (Size == 0))
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|
371 {
|
|
|
372 return HAL_ERROR;
|
|
|
373 }
|
|
|
374
|
|
|
375 hi2s->pTxBuffPtr = pTxData;
|
|
|
376 hi2s->pRxBuffPtr = pRxData;
|
|
|
377
|
|
|
378 tmp1 = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);
|
|
|
379 tmp2 = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);
|
|
|
380 /* Check the Data format: When a 16-bit data frame or a 16-bit data frame extended
|
|
|
381 is selected during the I2S configuration phase, the Size parameter means the number
|
|
|
382 of 16-bit data length in the transaction and when a 24-bit data frame or a 32-bit data
|
|
|
383 frame is selected the Size parameter means the number of 16-bit data length. */
|
|
|
384 if((tmp1 == I2S_DATAFORMAT_24B)||\
|
|
|
385 (tmp2 == I2S_DATAFORMAT_32B))
|
|
|
386 {
|
|
|
387 hi2s->TxXferSize = Size*2;
|
|
|
388 hi2s->TxXferCount = Size*2;
|
|
|
389 hi2s->RxXferSize = Size*2;
|
|
|
390 hi2s->RxXferCount = Size*2;
|
|
|
391 }
|
|
|
392 else
|
|
|
393 {
|
|
|
394 hi2s->TxXferSize = Size;
|
|
|
395 hi2s->TxXferCount = Size;
|
|
|
396 hi2s->RxXferSize = Size;
|
|
|
397 hi2s->RxXferCount = Size;
|
|
|
398 }
|
|
|
399
|
|
|
400 /* Process Locked */
|
|
|
401 __HAL_LOCK(hi2s);
|
|
|
402
|
|
|
403 hi2s->State = HAL_I2S_STATE_BUSY_TX_RX;
|
|
|
404 hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
|
|
|
405
|
|
|
406 tmp1 = hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG;
|
|
|
407 tmp2 = hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG;
|
|
|
408 /* Check if the I2S_MODE_MASTER_TX or I2S_MODE_SLAVE_TX Mode is selected */
|
|
|
409 if((tmp1 == I2S_MODE_MASTER_TX) || (tmp2 == I2S_MODE_SLAVE_TX))
|
|
|
410 {
|
|
|
411 /* Enable I2Sext RXNE and ERR interrupts */
|
|
|
412 I2SxEXT(hi2s->Instance)->CR2 |= (I2S_IT_RXNE | I2S_IT_ERR);
|
|
|
413
|
|
|
414 /* Enable I2Sx TXE and ERR interrupts */
|
|
|
415 __HAL_I2S_ENABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR));
|
|
|
416
|
|
|
417 /* Check if the I2S is already enabled */
|
|
|
418 if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
|
|
|
419 {
|
|
|
420 /* Enable I2Sext(receiver) before enabling I2Sx peripheral */
|
|
|
421 I2SxEXT(hi2s->Instance)->I2SCFGR |= SPI_I2SCFGR_I2SE;
|
|
|
422
|
|
|
423 /* Enable I2Sx peripheral */
|
|
|
424 __HAL_I2S_ENABLE(hi2s);
|
|
|
425 }
|
|
|
426 }
|
|
|
427 /* The I2S_MODE_MASTER_RX or I2S_MODE_SLAVE_RX Mode is selected */
|
|
|
428 else
|
|
|
429 {
|
|
|
430 /* Enable I2Sext TXE and ERR interrupts */
|
|
|
431 I2SxEXT(hi2s->Instance)->CR2 |= (I2S_IT_TXE |I2S_IT_ERR);
|
|
|
432
|
|
|
433 /* Enable I2Sext RXNE and ERR interrupts */
|
|
|
434 __HAL_I2S_ENABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR));
|
|
|
435
|
|
|
436 /* Check if the I2S is already enabled */
|
|
|
437 if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
|
|
|
438 {
|
|
|
439 /* Check if the I2S_MODE_MASTER_RX is selected */
|
|
|
440 if((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_MASTER_RX)
|
|
|
441 {
|
|
|
442 /* Prepare the First Data before enabling the I2S */
|
|
|
443 if(hi2s->TxXferCount != 0)
|
|
|
444 {
|
|
|
445 /* Transmit First data */
|
|
|
446 I2SxEXT(hi2s->Instance)->DR = (*hi2s->pTxBuffPtr++);
|
|
|
447 hi2s->TxXferCount--;
|
|
|
448
|
|
|
449 if(hi2s->TxXferCount == 0)
|
|
|
450 {
|
|
|
451 /* Disable I2Sext TXE interrupt */
|
|
|
452 I2SxEXT(hi2s->Instance)->CR2 &= ~I2S_IT_TXE;
|
|
|
453 }
|
|
|
454 }
|
|
|
455 }
|
|
|
456 /* Enable I2S peripheral */
|
|
|
457 __HAL_I2S_ENABLE(hi2s);
|
|
|
458
|
|
|
459 /* Enable I2Sext(transmitter) after enabling I2Sx peripheral */
|
|
|
460 I2SxEXT(hi2s->Instance)->I2SCFGR |= SPI_I2SCFGR_I2SE;
|
|
|
461 }
|
|
|
462 }
|
|
|
463 /* Process Unlocked */
|
|
|
464 __HAL_UNLOCK(hi2s);
|
|
|
465
|
|
|
466 return HAL_OK;
|
|
|
467 }
|
|
|
468 else
|
|
|
469 {
|
|
|
470 return HAL_BUSY;
|
|
|
471 }
|
|
|
472 }
|
|
|
473
|
|
|
474 /**
|
|
|
475 * @brief Full-Duplex Transmit/Receive data in non-blocking mode using DMA
|
|
|
476 * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
|
|
|
477 * the configuration information for I2S module
|
|
|
478 * @param pTxData: a 16-bit pointer to the Transmit data buffer.
|
|
|
479 * @param pRxData: a 16-bit pointer to the Receive data buffer.
|
|
|
480 * @param Size: number of data sample to be sent:
|
|
|
481 * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
|
|
|
482 * configuration phase, the Size parameter means the number of 16-bit data length
|
|
|
483 * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
|
|
|
484 * the Size parameter means the number of 16-bit data length.
|
|
|
485 * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
|
|
|
486 * between Master and Slave(example: audio streaming).
|
|
|
487 * @retval HAL status
|
|
|
488 */
|
|
|
489 HAL_StatusTypeDef HAL_I2SEx_TransmitReceive_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pTxData, uint16_t *pRxData, uint16_t Size)
|
|
|
490 {
|
|
|
491 uint32_t *tmp;
|
|
|
492 uint32_t tmp1 = 0, tmp2 = 0;
|
|
|
493
|
|
|
494 if((pTxData == NULL ) || (pRxData == NULL ) || (Size == 0))
|
|
|
495 {
|
|
|
496 return HAL_ERROR;
|
|
|
497 }
|
|
|
498
|
|
|
499 if(hi2s->State == HAL_I2S_STATE_READY)
|
|
|
500 {
|
|
|
501 hi2s->pTxBuffPtr = pTxData;
|
|
|
502 hi2s->pRxBuffPtr = pRxData;
|
|
|
503
|
|
|
504 tmp1 = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);
|
|
|
505 tmp2 = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN);
|
|
|
506 /* Check the Data format: When a 16-bit data frame or a 16-bit data frame extended
|
|
|
507 is selected during the I2S configuration phase, the Size parameter means the number
|
|
|
508 of 16-bit data length in the transaction and when a 24-bit data frame or a 32-bit data
|
|
|
509 frame is selected the Size parameter means the number of 16-bit data length. */
|
|
|
510 if((tmp1 == I2S_DATAFORMAT_24B)||\
|
|
|
511 (tmp2 == I2S_DATAFORMAT_32B))
|
|
|
512 {
|
|
|
513 hi2s->TxXferSize = Size*2;
|
|
|
514 hi2s->TxXferCount = Size*2;
|
|
|
515 hi2s->RxXferSize = Size*2;
|
|
|
516 hi2s->RxXferCount = Size*2;
|
|
|
517 }
|
|
|
518 else
|
|
|
519 {
|
|
|
520 hi2s->TxXferSize = Size;
|
|
|
521 hi2s->TxXferCount = Size;
|
|
|
522 hi2s->RxXferSize = Size;
|
|
|
523 hi2s->RxXferCount = Size;
|
|
|
524 }
|
|
|
525
|
|
|
526 /* Process Locked */
|
|
|
527 __HAL_LOCK(hi2s);
|
|
|
528
|
|
|
529 hi2s->State = HAL_I2S_STATE_BUSY_TX_RX;
|
|
|
530 hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
|
|
|
531
|
|
|
532 /* Set the I2S Rx DMA Half transfer complete callback */
|
|
|
533 hi2s->hdmarx->XferHalfCpltCallback = I2S_DMARxHalfCplt;
|
|
|
534
|
|
|
535 /* Set the I2S Rx DMA transfer complete callback */
|
|
|
536 hi2s->hdmarx->XferCpltCallback = I2S_DMARxCplt;
|
|
|
537
|
|
|
538 /* Set the I2S Rx DMA error callback */
|
|
|
539 hi2s->hdmarx->XferErrorCallback = I2S_DMAError;
|
|
|
540
|
|
|
541 /* Set the I2S Tx DMA Half transfer complete callback */
|
|
|
542 hi2s->hdmatx->XferHalfCpltCallback = I2S_DMATxHalfCplt;
|
|
|
543
|
|
|
544 /* Set the I2S Tx DMA transfer complete callback */
|
|
|
545 hi2s->hdmatx->XferCpltCallback = I2S_DMATxCplt;
|
|
|
546
|
|
|
547 /* Set the I2S Tx DMA error callback */
|
|
|
548 hi2s->hdmatx->XferErrorCallback = I2S_DMAError;
|
|
|
549
|
|
|
550 tmp1 = hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG;
|
|
|
551 tmp2 = hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG;
|
|
|
552 /* Check if the I2S_MODE_MASTER_TX or I2S_MODE_SLAVE_TX Mode is selected */
|
|
|
553 if((tmp1 == I2S_MODE_MASTER_TX) || (tmp2 == I2S_MODE_SLAVE_TX))
|
|
|
554 {
|
|
|
555 /* Enable the Rx DMA Stream */
|
|
|
556 tmp = (uint32_t*)&pRxData;
|
|
|
557 HAL_DMA_Start_IT(hi2s->hdmarx, (uint32_t)&I2SxEXT(hi2s->Instance)->DR, *(uint32_t*)tmp, hi2s->RxXferSize);
|
|
|
558
|
|
|
559 /* Enable Rx DMA Request */
|
|
|
560 I2SxEXT(hi2s->Instance)->CR2 |= SPI_CR2_RXDMAEN;
|
|
|
561
|
|
|
562 /* Enable the Tx DMA Stream */
|
|
|
563 tmp = (uint32_t*)&pTxData;
|
|
|
564 HAL_DMA_Start_IT(hi2s->hdmatx, *(uint32_t*)tmp, (uint32_t)&hi2s->Instance->DR, hi2s->TxXferSize);
|
|
|
565
|
|
|
566 /* Enable Tx DMA Request */
|
|
|
567 hi2s->Instance->CR2 |= SPI_CR2_TXDMAEN;
|
|
|
568
|
|
|
569 /* Check if the I2S is already enabled */
|
|
|
570 if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
|
|
|
571 {
|
|
|
572 /* Enable I2Sext(receiver) before enabling I2Sx peripheral */
|
|
|
573 I2SxEXT(hi2s->Instance)->I2SCFGR |= SPI_I2SCFGR_I2SE;
|
|
|
574
|
|
|
575 /* Enable I2S peripheral after the I2Sext */
|
|
|
576 __HAL_I2S_ENABLE(hi2s);
|
|
|
577 }
|
|
|
578 }
|
|
|
579 else
|
|
|
580 {
|
|
|
581 /* Enable the Tx DMA Stream */
|
|
|
582 tmp = (uint32_t*)&pTxData;
|
|
|
583 HAL_DMA_Start_IT(hi2s->hdmatx, *(uint32_t*)tmp, (uint32_t)&I2SxEXT(hi2s->Instance)->DR, hi2s->TxXferSize);
|
|
|
584
|
|
|
585 /* Enable Tx DMA Request */
|
|
|
586 I2SxEXT(hi2s->Instance)->CR2 |= SPI_CR2_TXDMAEN;
|
|
|
587
|
|
|
588 /* Enable the Rx DMA Stream */
|
|
|
589 tmp = (uint32_t*)&pRxData;
|
|
|
590 HAL_DMA_Start_IT(hi2s->hdmarx, (uint32_t)&hi2s->Instance->DR, *(uint32_t*)tmp, hi2s->RxXferSize);
|
|
|
591
|
|
|
592 /* Enable Rx DMA Request */
|
|
|
593 hi2s->Instance->CR2 |= SPI_CR2_RXDMAEN;
|
|
|
594
|
|
|
595 /* Check if the I2S is already enabled */
|
|
|
596 if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
|
|
|
597 {
|
|
|
598 /* Enable I2S peripheral before the I2Sext */
|
|
|
599 __HAL_I2S_ENABLE(hi2s);
|
|
|
600
|
|
|
601 /* Enable I2Sext(transmitter) after enabling I2Sx peripheral */
|
|
|
602 I2SxEXT(hi2s->Instance)->I2SCFGR |= SPI_I2SCFGR_I2SE;
|
|
|
603 }
|
|
|
604 else
|
|
|
605 {
|
|
|
606 /* Check if Master Receiver mode is selected */
|
|
|
607 if((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_MASTER_RX)
|
|
|
608 {
|
|
|
609 /* Clear the Overrun Flag by a read operation on the SPI_DR register followed by a read
|
|
|
610 access to the SPI_SR register. */
|
|
|
611 __HAL_I2S_CLEAR_OVRFLAG(hi2s);
|
|
|
612 }
|
|
|
613 }
|
|
|
614 }
|
|
|
615
|
|
|
616 /* Process Unlocked */
|
|
|
617 __HAL_UNLOCK(hi2s);
|
|
|
618
|
|
|
619 return HAL_OK;
|
|
|
620 }
|
|
|
621 else
|
|
|
622 {
|
|
|
623 return HAL_BUSY;
|
|
|
624 }
|
|
|
625 }
|
|
|
626
|
|
|
627 /**
|
|
|
628 * @}
|
|
|
629 */
|
|
|
630
|
|
|
631
|
|
|
632 /**
|
|
|
633 * @brief Full-Duplex Transmit/Receive data in non-blocking mode using Interrupt
|
|
|
634 * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
|
|
|
635 * the configuration information for I2S module
|
|
|
636 * @retval HAL status
|
|
|
637 */
|
|
|
638 HAL_StatusTypeDef I2SEx_TransmitReceive_IT(I2S_HandleTypeDef *hi2s)
|
|
|
639 {
|
|
|
640 uint32_t tmp1 = 0, tmp2 = 0;
|
|
|
641
|
|
|
642 if(hi2s->State == HAL_I2S_STATE_BUSY_TX_RX)
|
|
|
643 {
|
|
|
644 /* Process Locked */
|
|
|
645 __HAL_LOCK(hi2s);
|
|
|
646
|
|
|
647 tmp1 = hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG;
|
|
|
648 tmp2 = hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG;
|
|
|
649 /* Check if the I2S_MODE_MASTER_TX or I2S_MODE_SLAVE_TX Mode is selected */
|
|
|
650 if((tmp1 == I2S_MODE_MASTER_TX) || (tmp2 == I2S_MODE_SLAVE_TX))
|
|
|
651 {
|
|
|
652 if(hi2s->TxXferCount != 0)
|
|
|
653 {
|
|
|
654 if(__HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_TXE) != RESET)
|
|
|
655 {
|
|
|
656 /* Transmit data */
|
|
|
657 hi2s->Instance->DR = (*hi2s->pTxBuffPtr++);
|
|
|
658 hi2s->TxXferCount--;
|
|
|
659
|
|
|
660 if(hi2s->TxXferCount == 0)
|
|
|
661 {
|
|
|
662 /* Disable TXE interrupt */
|
|
|
663 __HAL_I2S_DISABLE_IT(hi2s, I2S_IT_TXE);
|
|
|
664 }
|
|
|
665 }
|
|
|
666 }
|
|
|
667
|
|
|
668 if(hi2s->RxXferCount != 0)
|
|
|
669 {
|
|
|
670 if((I2SxEXT(hi2s->Instance)->SR & SPI_SR_RXNE) == SPI_SR_RXNE)
|
|
|
671 {
|
|
|
672 /* Receive data */
|
|
|
673 (*hi2s->pRxBuffPtr++) = I2SxEXT(hi2s->Instance)->DR;
|
|
|
674 hi2s->RxXferCount--;
|
|
|
675
|
|
|
676 if(hi2s->RxXferCount == 0)
|
|
|
677 {
|
|
|
678 /* Disable I2Sext RXNE interrupt */
|
|
|
679 I2SxEXT(hi2s->Instance)->CR2 &= ~I2S_IT_RXNE;
|
|
|
680 }
|
|
|
681 }
|
|
|
682 }
|
|
|
683 }
|
|
|
684 /* The I2S_MODE_MASTER_RX or I2S_MODE_SLAVE_RX Mode is selected */
|
|
|
685 else
|
|
|
686 {
|
|
|
687 if(hi2s->TxXferCount != 0)
|
|
|
688 {
|
|
|
689 if((I2SxEXT(hi2s->Instance)->SR & SPI_SR_TXE) == SPI_SR_TXE)
|
|
|
690 {
|
|
|
691 /* Transmit data */
|
|
|
692 I2SxEXT(hi2s->Instance)->DR = (*hi2s->pTxBuffPtr++);
|
|
|
693 hi2s->TxXferCount--;
|
|
|
694
|
|
|
695 if(hi2s->TxXferCount == 0)
|
|
|
696 {
|
|
|
697 /* Disable I2Sext TXE interrupt */
|
|
|
698 I2SxEXT(hi2s->Instance)->CR2 &= ~I2S_IT_TXE;
|
|
|
699
|
|
|
700 HAL_I2S_TxCpltCallback(hi2s);
|
|
|
701 }
|
|
|
702 }
|
|
|
703 }
|
|
|
704 if(hi2s->RxXferCount != 0)
|
|
|
705 {
|
|
|
706 if(__HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_RXNE) != RESET)
|
|
|
707 {
|
|
|
708 /* Receive data */
|
|
|
709 (*hi2s->pRxBuffPtr++) = hi2s->Instance->DR;
|
|
|
710 hi2s->RxXferCount--;
|
|
|
711
|
|
|
712 if(hi2s->RxXferCount == 0)
|
|
|
713 {
|
|
|
714 /* Disable RXNE interrupt */
|
|
|
715 __HAL_I2S_DISABLE_IT(hi2s, I2S_IT_RXNE);
|
|
|
716
|
|
|
717 HAL_I2S_RxCpltCallback(hi2s);
|
|
|
718 }
|
|
|
719 }
|
|
|
720 }
|
|
|
721 }
|
|
|
722
|
|
|
723 tmp1 = hi2s->RxXferCount;
|
|
|
724 tmp2 = hi2s->TxXferCount;
|
|
|
725 if((tmp1 == 0) && (tmp2 == 0))
|
|
|
726 {
|
|
|
727 /* Disable I2Sx ERR interrupt */
|
|
|
728 __HAL_I2S_DISABLE_IT(hi2s, I2S_IT_ERR);
|
|
|
729 /* Disable I2Sext ERR interrupt */
|
|
|
730 I2SxEXT(hi2s->Instance)->CR2 &= ~I2S_IT_ERR;
|
|
|
731
|
|
|
732 hi2s->State = HAL_I2S_STATE_READY;
|
|
|
733 }
|
|
|
734
|
|
|
735 /* Process Unlocked */
|
|
|
736 __HAL_UNLOCK(hi2s);
|
|
|
737
|
|
|
738 return HAL_OK;
|
|
|
739 }
|
|
|
740 else
|
|
|
741 {
|
|
|
742 return HAL_BUSY;
|
|
|
743 }
|
|
|
744 }
|
|
|
745
|
|
|
746 /**
|
|
|
747 * @}
|
|
|
748 */
|
|
|
749
|
|
|
750 #endif /* HAL_I2S_MODULE_ENABLED */
|
|
|
751 /**
|
|
|
752 * @}
|
|
|
753 */
|
|
|
754
|
|
|
755 /**
|
|
|
756 * @}
|
|
|
757 */
|
|
|
758
|
|
|
759 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
