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comparison src/hwos.asm @ 640:8c1f1f334275

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3.13 release
author heinrichsweikamp
date Thu, 29 Oct 2020 09:29:15 +0100
parents 4050675965ea
children a9a0188091e4
comparison
equal deleted inserted replaced
639:0ff82370991d 640:8c1f1f334275
171 171
172 movlw coding_speed_normal ; coding for normal CPU speed 172 movlw coding_speed_normal ; coding for normal CPU speed
173 movwf cpu_speed_request ; store CPU shall run with normal speed 173 movwf cpu_speed_request ; store CPU shall run with normal speed
174 movwf cpu_speed_state ; store CPU does run with normal speed 174 movwf cpu_speed_state ; store CPU does run with normal speed
175 175
176 ;bcf RCON,SBOREN ; brown-out off (not needed here, is handled in bootloader) 176 bcf RCON,SBOREN ; brown-out off (not needed here, is handled in bootloader)
177 bcf RCON,IPEN ; priority interrupts off 177 bcf RCON,IPEN ; priority interrupts off
178 178
179 banksel WDTCON 179 banksel WDTCON
180 movlw b'10000000' ; setup watchdog 180 movlw b'10000000' ; setup watchdog
181 movwf WDTCON ; ... 181 movwf WDTCON ; ...
194 194
195 movlw b'11000000' ; ANSEL0: AN7, AN6 -> analog inputs, PORTA is digital 195 movlw b'11000000' ; ANSEL0: AN7, AN6 -> analog inputs, PORTA is digital
196 movwf ANCON0 ; ... 196 movwf ANCON0 ; ...
197 movlw b'00000111' ; ANSEL1: AN8, AN9, AN10 -> analog input 197 movlw b'00000111' ; ANSEL1: AN8, AN9, AN10 -> analog input
198 movwf ANCON1 ; ... 198 movwf ANCON1 ; ...
199 movlw b'00000010' ; ANSEL2: AN17 -> analog input 199 clrf ANCON2
200 movwf ANCON2 ; ...
201 200
202 banksel common ; back to bank common 201 banksel common ; back to bank common
203 202
204 ; movlw b'00000000' ; 1= input -> Data TFT_high 203 ; movlw b'00000000' ; 1= input -> Data TFT_high
205 clrf TRISA ; ... 204 clrf TRISA ; ...
229 movlw b'01111110' ; 1= input, (RF1, RF2, RF3, RF4, RF5) -> Analog 228 movlw b'01111110' ; 1= input, (RF1, RF2, RF3, RF4, RF5) -> Analog
230 movwf TRISF ; ... 229 movwf TRISF ; ...
231 ; movlw b'00000000' ; init port 230 ; movlw b'00000000' ; init port
232 clrf PORTF ; ... 231 clrf PORTF ; ...
233 232
234 movlw b'00001110' ; 1= input, <7:6> not implemented, RG0 -> TX3_PIEZO_CFG, , RG1 -> TX2, RG2 -> RX2, RG3 -> AN17_RSSI, RG4 -> SOSC_OUT, RG5 -> /RESET 233 movlw b'00000110' ; 1= input, <7:6> not implemented, RG0 -> TX3_PIEZO_CFG, , RG1 -> TX2, RG2 -> RX2, RG3 -> AN17_RSSI, RG4 -> SOSC_OUT, RG5 -> /RESET
235 movwf TRISG ; ... 234 movwf TRISG ; ...
236 movlw b'00000001' ; init port 235 movlw b'00000001' ; init port
237 movwf PORTG ; ... 236 movwf PORTG ; ...
238 237
239 ; movlw b'00000000' ; 1= input -> Data TFT_low 238 ; movlw b'00000000' ; 1= input -> Data TFT_low
313 ; A/D Converter 312 ; A/D Converter
314 movlw b'00011000' ; power off ADC, select AN6 313 movlw b'00011000' ; power off ADC, select AN6
315 movwf ADCON0 ; ... 314 movwf ADCON0 ; ...
316 movlw b'00100000' ; 2.048V Vref+ 315 movlw b'00100000' ; 2.048V Vref+
317 movwf ADCON1 ; ... 316 movwf ADCON1 ; ...
318 movlw b'10111010' ; right aligned, 20 x T_AD acquisition time, FOSC/32 -> max. 40 MHz device clock speed 317 movlw b'10001111' ; right aligned, 2 x T_AD acquisition time, clock derived from A/D RC oscillator (To be CPU-clock independent)
319 movwf ADCON2 ; ... 318 movwf ADCON2 ; ...
320 319
321 320
322 ; Serial Port 1 (TRISC6/7) 321 ; Serial Port 1 (TRISC6/7)
323 movlw b'00001000' ; switch baud generator to 16 bit mode (BRG16=1) 322 movlw b'00001000' ; switch baud generator to 16 bit mode (BRG16=1)
396 ; bit 1: 1 = 16 bit operation 395 ; bit 1: 1 = 16 bit operation
397 ; bit 0: 1 = timer enabled 396 ; bit 0: 1 = timer enabled
398 ; 32768 Hz clock source, 1:1 prescaler -> timer counts at 30.51757813 µs/bit 397 ; 32768 Hz clock source, 1:1 prescaler -> timer counts at 30.51757813 µs/bit
399 movwf T5CON ; ... 398 movwf T5CON ; ...
400 399
401 400 ; Timer 4 for debounce of new digital piezo circuity
401 movlw b'01111011' ; 1:8 Postscale, Prescale = 1, Timer 4 OFF
402 movwf T4CON
403 setf PR4
404
402 ; turn off unused Timers 405 ; turn off unused Timers
403 ;banksel 0xF16 ; addresses F16h...F5Fh are not part of the access RAM 406 banksel 0xF16 ; addresses F16h...F5Fh are not part of the access RAM
404 movlw b'11000000' ; disable ECCP3 and ECCP2 407 movlw b'11000000' ; disable ECCP3 and ECCP2
405 movwf PMD0 ; ... 408 movwf PMD0 ; ...
406 IFDEF _external_sensor 409 IFDEF _external_sensor
407 movlw b'11010001' ; disable PSP, CTMU, Timer 4 and EMB 410 movlw b'11000001' ; disable PSP, CTMU and EMB
408 ELSE 411 ELSE
409 movlw b'11011001' ; disable PSP, CTMU, Timer 4, Timer 3 and EMB 412 movlw b'11001001' ; disable PSP, CTMU, Timer 3 and EMB
410 ENDIF 413 ENDIF
411 movwf PMD1 ; ... 414 movwf PMD1 ; ...
412 movlw b'11010111' ; disable timer 10, timer 8, timer 6 and comparators 1-3 415 movlw b'11010111' ; disable timer 10, timer 8, timer 6 and comparators 1-3
413 movwf PMD2 ; ... 416 movwf PMD2 ; ...
414 movlw b'11111111' ; disable CCP 4-10 and timer 12 417 movlw b'11111111' ; disable CCP 4-10 and timer 12
440 movwf PIE2 ; ... 443 movwf PIE2 ; ...
441 movlw b'00000000' ; enable timer 5 IRQ 444 movlw b'00000000' ; enable timer 5 IRQ
442 movwf PIE5 ; ... 445 movwf PIE5 ; ...
443 movlw b'00000001' ; enable RTCC IRQ 446 movlw b'00000001' ; enable RTCC IRQ
444 movwf PIE3 ; ... 447 movwf PIE3 ; ...
445 movlw b'00001000' ; enable timer 7 IRQ 448 movlw b'00001001' ; enable timer 7 and timer 4 IRQ
446 movwf PIE5 ; ... 449 movwf PIE5 ; ...
447 450
448 ; Release RESET from RX Circuitry 451 ; Release RESET from RX Circuitry
449 bcf active_reset_ostc_rx 452 bcf active_reset_ostc_rx
450 453