Mercurial > public > hwos_code
annotate src/hwos.asm @ 623:c40025d8e750
3.03 beta released
| author | heinrichsweikamp |
|---|---|
| date | Mon, 03 Jun 2019 14:01:48 +0200 |
| parents | 7b3903536213 |
| children | 7bdcc591196c |
| rev | line source |
|---|---|
| 0 | 1 ;============================================================================= |
| 2 ; | |
| 623 | 3 ; File hwos.asm combined next generation V3.03.4 |
| 0 | 4 ; |
| 275 | 5 ; Definition of the hwOS dive computer platform. |
| 0 | 6 ; |
| 7 ; Copyright (c) 2011, JD Gascuel, HeinrichsWeikamp, all right reserved. | |
| 8 ;============================================================================= | |
| 9 ; HISTORY | |
| 604 | 10 ; 2011-05-24 : [jDG] Cleanups from initial Matthias code |
| 11 ; 2011-06-24 : [MH] Added clock speeds | |
| 12 | |
| 623 | 13 ;============================================================================= |
| 14 | |
| 15 #DEFINE ACCESS_RAM_VARS ; the access RAM variables are declared in this file | |
| 604 | 16 |
| 275 | 17 #include "hwos.inc" |
| 623 | 18 #include "eeprom_rs232.inc" |
| 0 | 19 |
| 623 | 20 ;----------------------------- CONFIG ---------------------------------------- |
| 21 CONFIG RETEN = OFF ; disabled - controlled by SRETEN bit | |
| 604 | 22 CONFIG SOSCSEL = HIGH ; High Power SOSC circuit selected |
| 623 | 23 CONFIG XINST = OFF ; code won't execute in extended mode |
| 24 CONFIG FOSC = INTIO2 ; internal RC oscillator, no clock-out | |
| 25 CONFIG PLLCFG = OFF ; | |
| 26 CONFIG IESO = OFF ; disabled | |
| 27 CONFIG PWRTEN = OFF ; disabled, because incompatible with ICD3 (Ri-400) | |
| 28 CONFIG BOREN = ON ; controlled with SBOREN bit | |
| 29 CONFIG BORV = 2 ; 2.0V | |
| 30 CONFIG BORPWR = MEDIUM ; BORMV set to medium power level | |
| 31 CONFIG WDTEN = ON ; WDT controlled by SWDTEN bit setting | |
| 32 CONFIG WDTPS = 128 ; 1:128 | |
| 33 CONFIG RTCOSC = SOSCREF ; RTCC uses SOSC | |
| 34 CONFIG MCLRE = ON ; MCLR Enabled, RG5 Disabled | |
| 35 CONFIG CCP2MX = PORTBE ; RE7 micro-controller mode/RB3-all other modes | |
| 36 | |
| 37 | |
| 38 ;---------------------------- Bank0 ACCESS RAM ------------------------------- | |
| 39 ac_ram equ 0x000 | |
| 40 ac_ram udata_acs ac_ram ; access RAM data | |
| 41 | |
| 42 | |
| 43 ;---- Flags - Hardware Descriptors | |
| 44 HW_descriptor res 1 ; OSTC - model descriptor (cleared & rebuilt in restart) | |
| 45 HW_variants res 1 ; OSTC - model variants (NOT cleared in restart) | |
| 46 | |
| 47 ;---- Flags - Hardware States | |
| 48 HW_flags_state res 1 ; hardware - states | |
| 49 | |
| 50 ;--- Flags - Operating System | |
| 51 OS_flags_persist res 1 ; system - persistent settings (NOT cleared in restart) | |
| 52 OS_flags_ISR1 res 1 ; system - ISR control 1 | |
| 53 OS_flags_ISR2 res 1 ; system - ISR control 2 | |
| 54 | |
| 55 ;---- Flags - Operating Modes | |
| 56 OM_flags_mode res 1 ; operating modes | |
| 57 | |
| 58 ;---- Flags - Dive Modes | |
| 59 DM_flags_deco res 1 ; dive mode - main dive & deco mode | |
| 60 | |
| 61 ;---- CPU Speed | |
| 62 cpu_speed_request res 1 ; requested CPU speed: =1: eco, =2: normal, =3: fastest | |
| 63 cpu_speed_state res 1 ; current CPU speed: =1: eco, =2: normal, =3: fastest | |
| 64 | |
| 65 ;---- Timebase & Eventbase | |
| 66 timebase res 1 ; timed trigger flags and running timebase | |
| 67 eventbase res 1 ; event trigger flags | |
| 68 | |
| 69 ;---- Timeout-Timer Service | |
| 70 isr_timeout_timer res 1 ; timeout timer | |
| 71 isr_timeout_reload res 1 ; timeout reload value | |
| 72 | |
| 73 ;---- Dive Times | |
| 74 total_divetime_secs res 2 ; total dive time, seconds | |
| 75 counted_divetime_mins res 2 ; counted dive time, minutes | Attention: do not change the position of | |
| 76 counted_divetime_secs res 1 ; counted dive time, seconds | these 2 Variables relative to each other! | |
| 604 | 77 |
| 623 | 78 ;---- Dive Times / Apnoe |
| 79 apnoe_surface_mins res 1 ; surface time minutes | Attention: do not change the position of | |
| 80 apnoe_surface_secs res 1 ; surface time seconds | these 2 Variables relative to each other! | |
| 81 | |
| 82 apnoe_dive_mins res 1 ; dive time minutes | Attention: do not change the position of | |
| 83 apnoe_dive_secs res 1 ; dive time seconds | these 2 Variables relative to each other! | |
| 84 | |
| 85 | |
| 86 ;---- Profile Recording | |
| 87 sampling_rate res 1 ; configured sampling rate | |
| 88 sampling_timer res 1 ; sampling timer | |
| 89 | |
| 90 ;---- Simulator Mode | |
| 91 simulatormode_depth res 1 ; depth in simulator mode | |
| 92 | |
| 93 ;---- HUD / Sensor Data | |
| 94 hud_status_byte res 1 ; HUD status byte, see definition of flags | Attention: keep relative position | |
| 95 hud_battery_mv res 2 ; hud/ppo2 monitor battery voltage in mV | between these two variables! | |
| 96 | |
| 97 | |
| 98 ; 28 byte user data | |
| 99 ; 32 byte tmp data placed by C compiler | |
| 100 ; 20 byte variables placed by math library | |
| 101 ; == | |
| 102 ; 80 byte used, 16 byte free (96 byte total available) | |
| 103 | |
| 104 global HW_descriptor | |
| 105 global HW_variants | |
| 106 global HW_flags_state | |
| 107 global OS_flags_persist | |
| 108 global OS_flags_ISR1 | |
| 109 global OS_flags_ISR2 | |
| 110 global OM_flags_mode | |
| 111 global DM_flags_deco | |
| 112 global cpu_speed_request | |
| 113 global cpu_speed_state | |
| 114 global timebase | |
| 115 global eventbase | |
| 116 global isr_timeout_timer | |
| 117 global isr_timeout_reload | |
| 118 global total_divetime_secs | |
| 119 global counted_divetime_mins | |
| 120 global counted_divetime_secs | |
| 121 global apnoe_surface_secs | |
| 122 global apnoe_surface_mins | |
| 123 global apnoe_dive_secs | |
| 124 global apnoe_dive_mins | |
| 125 global sampling_rate | |
| 126 global sampling_timer | |
| 127 global simulatormode_depth | |
| 128 global hud_status_byte | |
| 129 global hud_battery_mv | |
| 130 | |
| 131 ;----------------------------------------------------------------------------- | |
| 132 | |
| 133 hwos CODE | |
| 604 | 134 |
| 0 | 135 ;============================================================================= |
| 136 | |
| 604 | 137 global init_ostc |
| 275 | 138 init_ostc: |
| 623 | 139 |
| 140 ; Oscillator | |
| 141 banksel common ; select bank common | |
| 0 | 142 movlw b'01110010' |
| 604 | 143 movwf OSCCON ; 16 MHz INTOSC |
| 0 | 144 movlw b'00001000' |
| 604 | 145 movwf OSCCON2 ; secondary oscillator running |
| 0 | 146 movlw b'00000000' |
| 604 | 147 movwf OSCTUNE ; 4x PLL disable (Bit 6) - only works with 8 or 16MHz (=32 or 64MHz) |
| 608 | 148 |
| 623 | 149 movlw coding_speed_normal ; coding for normal CPU speed |
| 150 movwf cpu_speed_request ; store CPU shall run with normal speed | |
| 151 movwf cpu_speed_state ; store CPU does run with normal speed | |
| 608 | 152 |
| 623 | 153 ;bcf RCON,SBOREN ; brown-out off (not needed here, is handled in bootloader) |
| 604 | 154 bcf RCON,IPEN ; priority interrupts off |
| 608 | 155 |
| 604 | 156 banksel WDTCON |
| 157 movlw b'10000000' | |
| 158 movwf WDTCON ; setup watchdog | |
| 0 | 159 |
| 608 | 160 |
| 0 | 161 ; I/O Ports |
| 604 | 162 banksel 0xF16 ; addresses, F16h through F5Fh, are also used by SFRs, but are not part of the access RAM |
| 163 clrf REFOCON ; no reference oscillator active on REFO pin | |
| 164 clrf ODCON1 ; disable open drain capability | |
| 165 clrf ODCON2 ; disable open drain capability | |
| 166 clrf ODCON3 ; disable open drain capability | |
| 608 | 167 clrf CM1CON ; disable |
| 604 | 168 clrf CM2CON ; disable |
| 169 clrf CM3CON ; disable | |
| 0 | 170 |
| 604 | 171 movlw b'11000000' ; ANSEL, AN7 and AN6 -> Analog inputs, PORTA is digital |
| 0 | 172 movwf ANCON0 |
| 604 | 173 movlw b'00000111' ; ANSEL, AN8, AN9, AN10 -> Analog input |
| 0 | 174 movwf ANCON1 |
| 175 movlw b'00000010' ; ANSEL, AN17 -> Analog input | |
| 176 movwf ANCON2 | |
| 604 | 177 banksel common |
| 0 | 178 |
| 604 | 179 ; movlw b'00000000' ; 1= input -> Data TFT_high |
| 448 | 180 clrf TRISA |
| 604 | 181 ; movlw b'00000000' ; init port |
| 448 | 182 clrf PORTA |
| 0 | 183 |
| 604 | 184 movlw b'00000011' ; 1= input, (RB0, RB1) -> switches, RB2 -> Power_MCP, RB3 -> s8_npower, RB4 -> LED_green/rx_nreset, RB5 -> /TFT_POWER |
| 0 | 185 movwf TRISB |
| 604 | 186 movlw b'00111000' ; init port, rx_nreset=1 -> hard reset RX |
| 0 | 187 movwf PORTB |
| 188 | |
| 604 | 189 movlw b'10011010' ; 1= input, (RC0, RC1) -> SOSC, RC2 -> TFT_LED_PWM, (RC3,RC4) -> I²C, RC5 -> MOSI_MS5541, (RC6, RC7) -> UART1 |
| 0 | 190 movwf TRISC |
| 604 | 191 ; movlw b'00000000' ; init port |
| 448 | 192 clrf PORTC |
| 0 | 193 |
| 604 | 194 movlw b'00100000' ; 1= input, RD0 -> TFT_NCS, RD1 -> TFT_RS, RD2 -> TFT_NWR, RD3 -> TFT_RD, RD4 -> MOSI_Flash, RD5 -> MISO_Flash, RD6 -> CLK_Flash, RD7 -> TFT_NRESET |
| 0 | 195 movwf TRISD |
| 604 | 196 ; movlw b'00000000' ; init port |
| 448 | 197 clrf PORTD |
| 0 | 198 |
| 623 | 199 ; movlw b'00000000' ; 1= input, RE1 -> Power_IR, RE2 -> CS_MCP, RE3 -> LED_blue, RE4 -> power_sw1, RE5 -> set to 1 for cR hardware |
| 448 | 200 clrf TRISE |
| 604 | 201 movlw b'00110001' ; init port |
| 0 | 202 movwf PORTE |
| 203 | |
| 604 | 204 movlw b'01111110' ; 1= input, (RF1, RF2, RF3, RF4, RF5) -> Analog |
| 0 | 205 movwf TRISF |
| 604 | 206 ; movlw b'00000000' ; init port |
| 448 | 207 clrf PORTF |
| 0 | 208 |
| 604 | 209 movlw b'00001110' ; 1= input, <7:6> not implemented, RG0 -> TX3_PIEZO_CFG, RG2 -> RX2, RG3 -> AN17_RSSI, RG4 -> SOSC_OUT, RG5 -> /RESET |
| 0 | 210 movwf TRISG |
| 604 | 211 movlw b'00000001' ; init port |
| 0 | 212 movwf PORTG |
| 213 | |
| 604 | 214 ; movlw b'00000000' ; 1= input -> Data TFT_low |
| 448 | 215 clrf TRISH |
| 604 | 216 ; movlw b'00000000' ; init port |
| 448 | 217 clrf PORTH |
| 0 | 218 |
| 623 | 219 movlw b'10011011' ; 1= input, RJ4 -> vusb_in, RJ5 -> power_sw2, RJ6 -> CLK_MS5541, RJ7 -> MISO_MS5541 |
| 0 | 220 movwf TRISJ |
| 604 | 221 movlw b'00100000' ; init port |
| 0 | 222 movwf PORTJ |
| 223 | |
| 623 | 224 |
| 618 | 225 ; disable Charger by default |
| 623 | 226 bsf charge_disable ; set charging-inhibit signal |
| 227 bcf charge_enable ; activate charging-inhibit signal | |
| 228 | |
| 229 | |
| 0 | 230 ; Timer 0 |
| 604 | 231 movlw b'00000001' ; timer0 with 1:4 prescaler |
| 0 | 232 movwf T0CON |
| 233 | |
| 623 | 234 |
| 0 | 235 ; Timer 1 - Button hold-down timer |
| 623 | 236 movlw b'10001100' ; 32768 Hz clock source, 1:1 prescaler -> ; 30.51757813 µs/bit in TMR1L:TMR1H |
| 0 | 237 movwf T1CON |
| 238 | |
| 623 | 239 |
| 0 | 240 ; RTCC |
| 623 | 241 banksel 0xF16 ; addresses, F16h through F5Fh, are also used by SFRs, but are not part of the access RAM |
| 242 movlw 0x55 | |
| 243 movwf EECON2 | |
| 244 movlw 0xAA | |
| 245 movwf EECON2 | |
| 246 bsf RTCCFG,RTCWREN ; unlock sequence for RTCWREN | |
| 0 | 247 bsf RTCCFG,RTCPTR1 |
| 248 bsf RTCCFG,RTCPTR0 | |
| 623 | 249 bsf RTCCFG,RTCEN ; module enable |
| 250 bsf RTCCFG,RTCOE ; output enable | |
| 251 movlw b'00000100' ; 32768 Hz SOCS on RTCC pin (PORTG,4) Bit7-5: pull-ups for Port D, E and J | |
| 0 | 252 movwf PADCFG1 |
| 623 | 253 movlw b'11000000' |
| 254 movwf ALRMCFG ; 1/2 second alarm | |
| 0 | 255 movlw d'1' |
| 623 | 256 movwf ALRMRPT ; alarm repeat counter |
| 257 movlw 0x55 | |
| 258 movwf EECON2 | |
| 259 movlw 0xAA | |
| 260 movwf EECON2 | |
| 261 bcf RTCCFG,RTCWREN ; lock sequence for RTCWREN | |
| 262 banksel common | |
| 263 | |
| 614 | 264 |
| 0 | 265 ; A/D Converter |
| 266 movlw b'00011000' ; power off ADC, select AN6 | |
| 267 movwf ADCON0 | |
| 268 movlw b'00100000' ; 2.048V Vref+ | |
| 269 movwf ADCON1 | |
| 604 | 270 movlw b'10001101' ; right aligned |
| 0 | 271 movwf ADCON2 |
| 272 | |
| 623 | 273 |
| 274 ; serial Port 1 (TRISC6/7) | |
| 0 | 275 movlw b'00001000' ; BRG16=1 |
| 276 movwf BAUDCON1 | |
| 623 | 277 movlw .34 ; SPBRGH:SPBRG = .34 : 114285 BAUD @ 16MHz (+0.79% Error at 115200 BAUD) |
| 278 movwf SPBRG1 ; SPBRGH:SPBRG = .207 : 19230 BAUD @ 16MHz (-0.16% Error at 19200 BAUD) | |
| 0 | 279 clrf SPBRGH1 ; |
| 204 | 280 |
| 281 clrf RCSTA1 | |
| 604 | 282 clrf TXSTA1 ; UART disable |
| 283 bcf PORTC,6 ; TX hard to GND | |
| 0 | 284 |
| 623 | 285 |
| 286 ; serial Port 2 (TRISG2) for IR/S8 digital interface | |
| 287 ; | |
| 288 ; - will be initialized by enable_ir_s8 (eeprom_rs232.asm) in case IR/S8 shall be available | |
| 289 | |
| 0 | 290 |
| 623 | 291 ; Timer 3 for IR-RX Timeout |
| 292 IFDEF _external_sensor | |
| 604 | 293 clrf T3GCON ; reset Timer3 gate control register |
| 623 | 294 movlw b'10001001' ; synced, 1:1 prescaler -> 2 seconds till overrun @ 32768 Hz, |
| 295 ; incrementing by 1 bit each 30.51757813 µs | |
| 0 | 296 movwf T3CON |
| 623 | 297 ENDIF |
| 298 | |
| 0 | 299 |
| 300 ; SPI Module(s) | |
| 301 ; SPI2: External Flash | |
| 302 movlw b'00110000' | |
| 303 movwf SSP2CON1 | |
| 448 | 304 ; movlw b'00000000' |
| 305 clrf SSP2STAT | |
| 623 | 306 ; -> 0.25 MHz Bit clock @ 1 MHz mode (Eco) |
| 307 ; -> 4 MHz Bit clock @ 16 MHz mode (Normal) | |
| 308 ; -> 16 MHz Bit clock @ 64 MHz mode (Fastest) | |
| 309 | |
| 0 | 310 |
| 311 ; MSSP1 Module: I2C Master | |
| 604 | 312 movlw b'00101000' ; I2C master mode |
| 0 | 313 movwf SSP1CON1 |
| 448 | 314 ; movlw b'00000000' |
| 315 clrf SSP1CON2 | |
| 0 | 316 movlw 0x27 |
| 604 | 317 movwf SSP1ADD ; 100kHz @ 16MHz Fosc |
| 0 | 318 |
| 623 | 319 |
| 0 | 320 ; PWM Module(s) |
| 623 | 321 ; PWM 1 for LED dimming |
| 0 | 322 movlw b'00001100' |
| 323 movwf CCP1CON | |
| 324 movlw b'00000001' | |
| 604 | 325 movwf PSTR1CON ; pulse steering disabled |
| 0 | 326 movlw d'255' |
| 604 | 327 movwf PR2 ; period |
| 328 ; 255 is max brightness (300 mW) | |
| 329 clrf CCPR1L ; duty cycle | |
| 330 clrf CCPR1H ; duty cycle | |
| 0 | 331 movlw T2CON_NORMAL |
| 332 movwf T2CON | |
| 333 | |
| 623 | 334 |
| 335 ; Timer 5 for ISR-independent wait routines | |
| 604 | 336 clrf T5GCON ; reset Timer5 gate control register |
| 623 | 337 movlw b'10001011' ; synced, 16 bit mode, 1:1 prescaler -> 2 seconds till overrun @ 32768 Hz, |
| 338 movwf T5CON ; incrementing by 1 bit each 30.51757813 µs | |
| 339 | |
| 0 | 340 |
| 623 | 341 banksel 0xF16 ; addresses F16h through F5Fh are also used by SFRs, but are not part of the access RAM |
| 342 | |
| 343 ; Timer 7 for 62.5 ms Interrupt (sensor states) | |
| 604 | 344 clrf T7GCON ; reset Timer7 gate control register |
| 623 | 345 movlw b'10001001' ; 1:1 prescaler -> 2 seconds @ 32768 Hz, synced |
| 0 | 346 movwf T7CON |
| 347 clrf TMR7L | |
| 348 movlw .248 | |
| 623 | 349 movwf TMR7H ; -> rollover after 2048 cycles -> 62.5 ms |
| 0 | 350 |
| 623 | 351 |
| 352 ; turn off unused timers | |
| 608 | 353 movlw b'11000000' |
| 354 movwf PMD0 | |
| 623 | 355 IFDEF _external_sensor |
| 608 | 356 movlw b'11010001' |
| 623 | 357 ELSE |
| 358 movlw b'11011001' ; includes turning off timer 3 | |
| 359 ENDIF | |
| 608 | 360 movwf PMD1 |
| 361 movlw b'11010111' | |
| 362 movwf PMD2 | |
| 363 movlw b'11111111' | |
| 364 movwf PMD3 | |
| 365 | |
| 623 | 366 |
| 367 ; turn off unused CTMU | |
| 608 | 368 clrf CTMUCONH |
| 369 clrf CTMUCONL | |
| 370 clrf CTMUICON | |
| 623 | 371 |
| 604 | 372 banksel common |
| 608 | 373 |
| 623 | 374 |
| 0 | 375 ; Interrupts |
| 50 | 376 movlw b'11010000' |
| 0 | 377 movwf INTCON |
| 623 | 378 movlw b'00001000' ; Bit7=1: pull-up for PORTB disabled |
| 0 | 379 movwf INTCON2 |
|
77
131e6dd9e201
BUGFIX: Potential bug to freeze the OSTC3 after battery change or update
heinrichsweikamp
parents:
58
diff
changeset
|
380 movlw b'00000000' |
| 0 | 381 movwf INTCON3 |
| 382 movlw b'00000001' ; Bit0: TMR1 | |
| 383 movwf PIE1 | |
| 384 movlw b'00000010' ; Bit1: TMR3 | |
| 604 | 385 movwf PIE2 |
| 0 | 386 movlw b'00000000' ; Bit1: TMR5 |
| 387 movwf PIE5 | |
| 388 movlw b'00100001' ; Bit0: RTCC, Bit5: UART2 | |
| 389 movwf PIE3 | |
| 390 movlw b'00001000' ; Bit3: TMR7 | |
| 391 movwf PIE5 | |
| 392 | |
| 623 | 393 bcf active_reset_ostc_rx ; release RESET from RX circuitry |
| 394 ;bra power_up_switches | |
| 395 | |
| 0 | 396 |
| 623 | 397 global power_up_switches |
| 398 power_up_switches: | |
| 399 bsf power_sw1 ; switch on power supply for switch 1 | |
| 400 btfss power_sw1 ; power established? | |
| 401 bra $-4 ; NO - wait | |
| 402 bsf power_sw2 ; switch on power supply for switch 2 | |
| 403 btfss power_sw2 ; power established? | |
| 404 bra $-4 ; NO - wait | |
| 204 | 405 |
| 0 | 406 return |
| 407 | |
| 408 ;============================================================================= | |
| 623 | 409 ; CPU speed change request functions |
| 410 | |
| 411 global request_speed_eco | |
| 412 request_speed_eco: | |
| 413 movlw coding_speed_eco ; load coding for eco speed | |
| 414 movwf cpu_speed_request ; request ISR to change the CPU speed | |
| 415 return ; done | |
| 416 | |
| 417 global request_speed_normal | |
| 418 request_speed_normal: | |
| 419 movlw coding_speed_normal ; load coding for normal speed | |
| 420 movwf cpu_speed_request ; request ISR to change the CPU speed | |
| 421 return ; done | |
| 422 | |
| 423 global request_speed_fastest | |
| 424 request_speed_fastest: | |
| 425 movlw coding_speed_fastest ; load coding for fastest speed | |
| 426 movwf cpu_speed_request ; request ISR to change the CPU speed | |
| 427 return ; done | |
| 428 | |
| 0 | 429 ;============================================================================= |
| 623 | 430 ; Backup the first 128 bytes from program memory to EEPROM |
| 431 ; | |
| 432 global backup_flash_page | |
| 433 backup_flash_page: | |
| 434 banksel common | |
| 435 movlw 0x00 ; start address in internal program memory | |
| 436 movwf TBLPTRL | |
| 437 movwf TBLPTRH | |
| 438 movwf TBLPTRU | |
| 439 | |
| 440 movlw .128 ; copy 1 block = 128 byte | |
| 441 movwf lo ; byte counter | |
| 442 | |
| 443 clrf EEADR ; start address in EEPROM, low | |
| 444 movlw .3 ; start address in EEPROM, high | |
| 445 movwf EEADRH | |
| 446 | |
| 447 TBLRD*- ; dummy read to be in 128 byte block | |
| 448 backup_flash_loop: | |
| 449 tblrd+* ; read one byte from program memory (with pre-increment) | |
| 450 movff TABLAT,EEDATA ; transfer byte from program memory read to EEPROM write | |
| 451 call write_eeprom ; execute EEPROM write | |
| 452 incf EEADR,F ; increment EEPROM address | |
| 453 decfsz lo,F ; 128 byte done? | |
| 454 bra backup_flash_loop ; NO - loop | |
| 455 clrf EEADRH ; YES - reset EEPROM high address | |
| 456 return ; - done | |
| 457 | |
| 0 | 458 ;============================================================================= |
| 623 | 459 ; Restore the first 128 bytes from EEPROM to program memory |
| 460 ; | |
| 461 global restore_flash | |
| 462 restore_flash: | |
| 463 banksel common | |
| 464 movlw 0x00 ; start address in internal program memory | |
| 465 movwf TBLPTRL | |
| 466 movwf TBLPTRH | |
| 467 movwf TBLPTRU | |
| 468 | |
| 469 movlw b'10010100' ; setup block erase | |
| 470 rcall restore_write ; execute block erase | |
| 471 | |
| 472 movlw .128 ; copy 1 block = 128 byte | |
| 473 movwf lo ; byte counter | |
| 474 | |
| 475 clrf EEADR ; start address in EEPROM, low | |
| 476 movlw .3 ; start address in EEPROM, high | |
| 477 movwf EEADRH | |
| 478 | |
| 479 TBLRD*- ; dummy read to be in 128 byte block | |
| 480 restore_flash_loop: | |
| 481 call read_eeprom ; read one byte from EEPROM | |
| 482 incf EEADR,F ; increment EEPROM address | |
| 483 movff EEDATA,TABLAT ; transfer byte from EEPROM read to program memory write | |
| 484 tblwt+* ; execute program memory write (with pre-increment) | |
| 485 decfsz lo,F ; 128 bytes done? | |
| 486 bra restore_flash_loop ; NO - loop | |
| 487 movlw b'10000100' ; YES - setup block write | |
| 488 rcall restore_write ; - execute block write | |
| 489 reset ; - done, reset CPU | |
| 490 | |
| 491 restore_write: | |
| 492 movwf EECON1 ; type of memory to write in | |
| 493 movlw 0x55 | |
| 494 movwf EECON2 | |
| 495 movlw 0xAA | |
| 496 movwf EECON2 | |
| 497 bsf EECON1,WR ; execute write | |
| 498 nop | |
| 499 nop | |
| 0 | 500 return |
| 501 | |
| 604 | 502 END |