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3.03 beta released
author heinrichsweikamp
date Mon, 03 Jun 2019 14:01:48 +0200
parents 7b3903536213
children 7bdcc591196c
comparison
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622:02d1386429a6 623:c40025d8e750
1 ;============================================================================= 1 ;=============================================================================
2 ; 2 ;
3 ; File hwos.asm V2.99g 3 ; File hwos.asm combined next generation V3.03.4
4 ; 4 ;
5 ; Definition of the hwOS dive computer platform. 5 ; Definition of the hwOS dive computer platform.
6 ; 6 ;
7 ; Copyright (c) 2011, JD Gascuel, HeinrichsWeikamp, all right reserved. 7 ; Copyright (c) 2011, JD Gascuel, HeinrichsWeikamp, all right reserved.
8 ;============================================================================= 8 ;=============================================================================
9 ; HISTORY 9 ; HISTORY
10 ; 2011-05-24 : [jDG] Cleanups from initial Matthias code 10 ; 2011-05-24 : [jDG] Cleanups from initial Matthias code
11 ; 2011-06-24 : [MH] Added clock speeds 11 ; 2011-06-24 : [MH] Added clock speeds
12 12
13 ;=============================================================================
14
15 #DEFINE ACCESS_RAM_VARS ; the access RAM variables are declared in this file
13 16
14 #include "hwos.inc" 17 #include "hwos.inc"
15 18 #include "eeprom_rs232.inc"
16 ;============================================================================= 19
17 ;----------------------------- CONFIG --------------------------------- 20 ;----------------------------- CONFIG ----------------------------------------
18 CONFIG RETEN = OFF ; disabled - controlled by SRETEN bit 21 CONFIG RETEN = OFF ; disabled - controlled by SRETEN bit
19 CONFIG SOSCSEL = HIGH ; High Power SOSC circuit selected 22 CONFIG SOSCSEL = HIGH ; High Power SOSC circuit selected
20 CONFIG XINST = OFF ; code won't execute in extended mode 23 CONFIG XINST = OFF ; code won't execute in extended mode
21 CONFIG FOSC = INTIO2 ; internal RC oscillator, no clock-out 24 CONFIG FOSC = INTIO2 ; internal RC oscillator, no clock-out
22 CONFIG PLLCFG = OFF 25 CONFIG PLLCFG = OFF ;
23 CONFIG IESO = OFF ; disabled 26 CONFIG IESO = OFF ; disabled
24 CONFIG PWRTEN = OFF ; disabled, because incompatible with ICD3 (Ri-400) 27 CONFIG PWRTEN = OFF ; disabled, because incompatible with ICD3 (Ri-400)
25 CONFIG BOREN = ON ; controlled with SBOREN bit 28 CONFIG BOREN = ON ; controlled with SBOREN bit
26 CONFIG BORV = 2 ; 2.0V 29 CONFIG BORV = 2 ; 2.0V
27 CONFIG BORPWR = MEDIUM ; BORMV set to medium power level 30 CONFIG BORPWR = MEDIUM ; BORMV set to medium power level
28 CONFIG WDTEN = ON ; WDT controlled by SWDTEN bit setting 31 CONFIG WDTEN = ON ; WDT controlled by SWDTEN bit setting
29 CONFIG WDTPS = 128 ; 1:128 32 CONFIG WDTPS = 128 ; 1:128
30 CONFIG RTCOSC = SOSCREF ; RTCC uses SOSC 33 CONFIG RTCOSC = SOSCREF ; RTCC uses SOSC
31 CONFIG MCLRE = ON ; MCLR Enabled, RG5 Disabled 34 CONFIG MCLRE = ON ; MCLR Enabled, RG5 Disabled
32 CONFIG CCP2MX = PORTBE ; RE7-microcontroller mode/RB3-all other modes 35 CONFIG CCP2MX = PORTBE ; RE7 micro-controller mode/RB3-all other modes
33 36
34 hwos CODE 37
38 ;---------------------------- Bank0 ACCESS RAM -------------------------------
39 ac_ram equ 0x000
40 ac_ram udata_acs ac_ram ; access RAM data
41
42
43 ;---- Flags - Hardware Descriptors
44 HW_descriptor res 1 ; OSTC - model descriptor (cleared & rebuilt in restart)
45 HW_variants res 1 ; OSTC - model variants (NOT cleared in restart)
46
47 ;---- Flags - Hardware States
48 HW_flags_state res 1 ; hardware - states
49
50 ;--- Flags - Operating System
51 OS_flags_persist res 1 ; system - persistent settings (NOT cleared in restart)
52 OS_flags_ISR1 res 1 ; system - ISR control 1
53 OS_flags_ISR2 res 1 ; system - ISR control 2
54
55 ;---- Flags - Operating Modes
56 OM_flags_mode res 1 ; operating modes
57
58 ;---- Flags - Dive Modes
59 DM_flags_deco res 1 ; dive mode - main dive & deco mode
60
61 ;---- CPU Speed
62 cpu_speed_request res 1 ; requested CPU speed: =1: eco, =2: normal, =3: fastest
63 cpu_speed_state res 1 ; current CPU speed: =1: eco, =2: normal, =3: fastest
64
65 ;---- Timebase & Eventbase
66 timebase res 1 ; timed trigger flags and running timebase
67 eventbase res 1 ; event trigger flags
68
69 ;---- Timeout-Timer Service
70 isr_timeout_timer res 1 ; timeout timer
71 isr_timeout_reload res 1 ; timeout reload value
72
73 ;---- Dive Times
74 total_divetime_secs res 2 ; total dive time, seconds
75 counted_divetime_mins res 2 ; counted dive time, minutes | Attention: do not change the position of
76 counted_divetime_secs res 1 ; counted dive time, seconds | these 2 Variables relative to each other!
77
78 ;---- Dive Times / Apnoe
79 apnoe_surface_mins res 1 ; surface time minutes | Attention: do not change the position of
80 apnoe_surface_secs res 1 ; surface time seconds | these 2 Variables relative to each other!
81
82 apnoe_dive_mins res 1 ; dive time minutes | Attention: do not change the position of
83 apnoe_dive_secs res 1 ; dive time seconds | these 2 Variables relative to each other!
84
85
86 ;---- Profile Recording
87 sampling_rate res 1 ; configured sampling rate
88 sampling_timer res 1 ; sampling timer
89
90 ;---- Simulator Mode
91 simulatormode_depth res 1 ; depth in simulator mode
92
93 ;---- HUD / Sensor Data
94 hud_status_byte res 1 ; HUD status byte, see definition of flags | Attention: keep relative position
95 hud_battery_mv res 2 ; hud/ppo2 monitor battery voltage in mV | between these two variables!
96
97
98 ; 28 byte user data
99 ; 32 byte tmp data placed by C compiler
100 ; 20 byte variables placed by math library
101 ; ==
102 ; 80 byte used, 16 byte free (96 byte total available)
103
104 global HW_descriptor
105 global HW_variants
106 global HW_flags_state
107 global OS_flags_persist
108 global OS_flags_ISR1
109 global OS_flags_ISR2
110 global OM_flags_mode
111 global DM_flags_deco
112 global cpu_speed_request
113 global cpu_speed_state
114 global timebase
115 global eventbase
116 global isr_timeout_timer
117 global isr_timeout_reload
118 global total_divetime_secs
119 global counted_divetime_mins
120 global counted_divetime_secs
121 global apnoe_surface_secs
122 global apnoe_surface_mins
123 global apnoe_dive_secs
124 global apnoe_dive_mins
125 global sampling_rate
126 global sampling_timer
127 global simulatormode_depth
128 global hud_status_byte
129 global hud_battery_mv
130
131 ;-----------------------------------------------------------------------------
132
133 hwos CODE
35 134
36 ;============================================================================= 135 ;=============================================================================
37 136
38 global init_ostc 137 global init_ostc
39 init_ostc: 138 init_ostc:
40 ; init oscillator 139
41 banksel common ; bank 1 140 ; Oscillator
141 banksel common ; select bank common
42 movlw b'01110010' 142 movlw b'01110010'
43 movwf OSCCON ; 16 MHz INTOSC 143 movwf OSCCON ; 16 MHz INTOSC
44 movlw b'00001000' 144 movlw b'00001000'
45 movwf OSCCON2 ; secondary oscillator running 145 movwf OSCCON2 ; secondary oscillator running
46 movlw b'00000000' 146 movlw b'00000000'
47 movwf OSCTUNE ; 4x PLL disable (Bit 6) - only works with 8 or 16MHz (=32 or 64MHz) 147 movwf OSCTUNE ; 4x PLL disable (Bit 6) - only works with 8 or 16MHz (=32 or 64MHz)
48 148
49 movlw d'2' ; coding for speed normal 149 movlw coding_speed_normal ; coding for normal CPU speed
50 movff WREG,cpu_speed_request ; CPU shall run with normal speed 150 movwf cpu_speed_request ; store CPU shall run with normal speed
51 movff WREG,cpu_speed_state ; CPU does run with normal speed 151 movwf cpu_speed_state ; store CPU does run with normal speed
52 152
53 ; bcf RCON,SBOREN ; brown-out off (Not needed, set in bootloader) 153 ;bcf RCON,SBOREN ; brown-out off (not needed here, is handled in bootloader)
54 bcf RCON,IPEN ; priority interrupts off 154 bcf RCON,IPEN ; priority interrupts off
55 155
56 banksel WDTCON 156 banksel WDTCON
57 movlw b'10000000' 157 movlw b'10000000'
58 movwf WDTCON ; setup watchdog 158 movwf WDTCON ; setup watchdog
59 159
60 160
61 ; I/O Ports 161 ; I/O Ports
62 banksel 0xF16 ; addresses, F16h through F5Fh, are also used by SFRs, but are not part of the access RAM 162 banksel 0xF16 ; addresses, F16h through F5Fh, are also used by SFRs, but are not part of the access RAM
63
64 clrf REFOCON ; no reference oscillator active on REFO pin 163 clrf REFOCON ; no reference oscillator active on REFO pin
65 clrf ODCON1 ; disable open drain capability 164 clrf ODCON1 ; disable open drain capability
66 clrf ODCON2 ; disable open drain capability 165 clrf ODCON2 ; disable open drain capability
67 clrf ODCON3 ; disable open drain capability 166 clrf ODCON3 ; disable open drain capability
68 clrf CM1CON ; disable 167 clrf CM1CON ; disable
73 movwf ANCON0 172 movwf ANCON0
74 movlw b'00000111' ; ANSEL, AN8, AN9, AN10 -> Analog input 173 movlw b'00000111' ; ANSEL, AN8, AN9, AN10 -> Analog input
75 movwf ANCON1 174 movwf ANCON1
76 movlw b'00000010' ; ANSEL, AN17 -> Analog input 175 movlw b'00000010' ; ANSEL, AN17 -> Analog input
77 movwf ANCON2 176 movwf ANCON2
78
79 banksel common 177 banksel common
80 178
81 ; movlw b'00000000' ; 1= input -> Data TFT_high 179 ; movlw b'00000000' ; 1= input -> Data TFT_high
82 clrf TRISA 180 clrf TRISA
83 ; movlw b'00000000' ; init port 181 ; movlw b'00000000' ; init port
96 movlw b'00100000' ; 1= input, RD0 -> TFT_NCS, RD1 -> TFT_RS, RD2 -> TFT_NWR, RD3 -> TFT_RD, RD4 -> MOSI_Flash, RD5 -> MISO_Flash, RD6 -> CLK_Flash, RD7 -> TFT_NRESET 194 movlw b'00100000' ; 1= input, RD0 -> TFT_NCS, RD1 -> TFT_RS, RD2 -> TFT_NWR, RD3 -> TFT_RD, RD4 -> MOSI_Flash, RD5 -> MISO_Flash, RD6 -> CLK_Flash, RD7 -> TFT_NRESET
97 movwf TRISD 195 movwf TRISD
98 ; movlw b'00000000' ; init port 196 ; movlw b'00000000' ; init port
99 clrf PORTD 197 clrf PORTD
100 198
101 ; movlw b'00000000' ; 1= input, RE1 -> Power_IR, RE2 -> CS_MCP, RE3 -> LED_blue, RE4 -> power_sw1, RE5 -> Set to 1 for cR hardware 199 ; movlw b'00000000' ; 1= input, RE1 -> Power_IR, RE2 -> CS_MCP, RE3 -> LED_blue, RE4 -> power_sw1, RE5 -> set to 1 for cR hardware
102 clrf TRISE 200 clrf TRISE
103 movlw b'00110001' ; init port 201 movlw b'00110001' ; init port
104 movwf PORTE 202 movwf PORTE
105 203
106 movlw b'01111110' ; 1= input, (RF1, RF2, RF3, RF4, RF5) -> Analog 204 movlw b'01111110' ; 1= input, (RF1, RF2, RF3, RF4, RF5) -> Analog
116 ; movlw b'00000000' ; 1= input -> Data TFT_low 214 ; movlw b'00000000' ; 1= input -> Data TFT_low
117 clrf TRISH 215 clrf TRISH
118 ; movlw b'00000000' ; init port 216 ; movlw b'00000000' ; init port
119 clrf PORTH 217 clrf PORTH
120 218
121 movlw b'10011011' ; 1= input, RJ4 -> vusb_in, RJ5 -> power_sw2, RJ6 -> CLK_MS5541, RJ7 -> MISO_MS5541 219 movlw b'10011011' ; 1= input, RJ4 -> vusb_in, RJ5 -> power_sw2, RJ6 -> CLK_MS5541, RJ7 -> MISO_MS5541
122 movwf TRISJ 220 movwf TRISJ
123 movlw b'00100000' ; init port 221 movlw b'00100000' ; init port
124 movwf PORTJ 222 movwf PORTJ
125 223
224
126 ; disable Charger by default 225 ; disable Charger by default
127 bsf charge_disable ; set charging-inhibit signal 226 bsf charge_disable ; set charging-inhibit signal
128 bcf TRISE,2 227 bcf charge_enable ; activate charging-inhibit signal
129 228
229
130 ; Timer 0 230 ; Timer 0
131 movlw b'00000001' ; timer0 with 1:4 prescaler 231 movlw b'00000001' ; timer0 with 1:4 prescaler
132 movwf T0CON 232 movwf T0CON
133 233
234
134 ; Timer 1 - Button hold-down timer 235 ; Timer 1 - Button hold-down timer
135 movlw b'10001100' ; 32768Hz clock source, 1:1 prescaler -> ; 30.51757813 µs/bit in TMR1L:TMR1H 236 movlw b'10001100' ; 32768 Hz clock source, 1:1 prescaler -> ; 30.51757813 µs/bit in TMR1L:TMR1H
136 movwf T1CON 237 movwf T1CON
137 238
239
138 ; RTCC 240 ; RTCC
139 banksel 0xF16 ; Addresses, F16h through F5Fh, are also used by SFRs, but are not part of the Access RAM. 241 banksel 0xF16 ; addresses, F16h through F5Fh, are also used by SFRs, but are not part of the access RAM
140 movlw 0x55 242 movlw 0x55
141 movwf EECON2 243 movwf EECON2
142 movlw 0xAA 244 movlw 0xAA
143 movwf EECON2 245 movwf EECON2
144 bsf RTCCFG,RTCWREN ; Unlock sequence for RTCWREN 246 bsf RTCCFG,RTCWREN ; unlock sequence for RTCWREN
145 bsf RTCCFG,RTCPTR1 247 bsf RTCCFG,RTCPTR1
146 bsf RTCCFG,RTCPTR0 248 bsf RTCCFG,RTCPTR0
147 bsf RTCCFG,RTCEN ; Module enable 249 bsf RTCCFG,RTCEN ; module enable
148 bsf RTCCFG,RTCOE ; Output enable 250 bsf RTCCFG,RTCOE ; output enable
149 movlw b'00000100' ; 32768Hz SOCS on RTCC pin (PORTG,4) Bit7-5: Pullups for Port D, E and J 251 movlw b'00000100' ; 32768 Hz SOCS on RTCC pin (PORTG,4) Bit7-5: pull-ups for Port D, E and J
150 movwf PADCFG1 252 movwf PADCFG1
151 movlw b'11000100' 253 movlw b'11000000'
152 movwf ALRMCFG ; 1 second alarm 254 movwf ALRMCFG ; 1/2 second alarm
153 movlw d'1' 255 movlw d'1'
154 movwf ALRMRPT ; Alarm repeat counter 256 movwf ALRMRPT ; alarm repeat counter
155 movlw 0x55 257 movlw 0x55
156 movwf EECON2 258 movwf EECON2
157 movlw 0xAA 259 movlw 0xAA
158 movwf EECON2 260 movwf EECON2
159 bcf RTCCFG,RTCWREN ; Lock sequence for RTCWREN 261 bcf RTCCFG,RTCWREN ; lock sequence for RTCWREN
160 banksel common 262 banksel common
263
161 264
162 ; A/D Converter 265 ; A/D Converter
163 movlw b'00011000' ; power off ADC, select AN6 266 movlw b'00011000' ; power off ADC, select AN6
164 movwf ADCON0 267 movwf ADCON0
165 movlw b'00100000' ; 2.048V Vref+ 268 movlw b'00100000' ; 2.048V Vref+
166 movwf ADCON1 269 movwf ADCON1
167 movlw b'10001101' ; right aligned 270 movlw b'10001101' ; right aligned
168 movwf ADCON2 271 movwf ADCON2
169 272
170 ; init serial port1 (TRISC6/7) 273
274 ; serial Port 1 (TRISC6/7)
171 movlw b'00001000' ; BRG16=1 275 movlw b'00001000' ; BRG16=1
172 movwf BAUDCON1 276 movwf BAUDCON1
173 movlw .34 ; SPBRGH:SPBRG = .34 : 114285 BAUD @ 16MHz (+0.79% Error to 115200 BAUD) 277 movlw .34 ; SPBRGH:SPBRG = .34 : 114285 BAUD @ 16MHz (+0.79% Error at 115200 BAUD)
174 movwf SPBRG1 ; SPBRGH:SPBRG = .207 : 19230 BAUD @ 16MHz (-0.16% Error to 19200 BAUD) 278 movwf SPBRG1 ; SPBRGH:SPBRG = .207 : 19230 BAUD @ 16MHz (-0.16% Error at 19200 BAUD)
175 clrf SPBRGH1 ; 279 clrf SPBRGH1 ;
176 280
177 clrf RCSTA1 281 clrf RCSTA1
178 clrf TXSTA1 ; UART disable 282 clrf TXSTA1 ; UART disable
179 bcf PORTC,6 ; TX hard to GND 283 bcf PORTC,6 ; TX hard to GND
180 284
181 ; init serial port2 (TRISG2) 285
182 banksel BAUDCON2 286 ; serial Port 2 (TRISG2) for IR/S8 digital interface
183 movlw b'00100000' ; BRG16=0 ; inverted for IR 287 ;
184 movwf BAUDCON2 288 ; - will be initialized by enable_ir_s8 (eeprom_rs232.asm) in case IR/S8 shall be available
185 movlw b'00100000' ; BRGH=0, SYNC=0 289
186 movwf TXSTA2 290
187 movlw .102 ; SPBRGH:SPBRG = .102 : 2403 BAUD @ 16MHz 291 ; Timer 3 for IR-RX Timeout
188 movwf SPBRG2 292 IFDEF _external_sensor
189 clrf SPBRGH2
190 movlw b'10010000'
191 movwf RCSTA2
192 banksel common
193
194 ; Timer3 for IR-RX Timeout
195 clrf T3GCON ; reset Timer3 gate control register 293 clrf T3GCON ; reset Timer3 gate control register
196 movlw b'10001001' ; 1:1 prescaler -> 2 seconds@32768Hz, synced 294 movlw b'10001001' ; synced, 1:1 prescaler -> 2 seconds till overrun @ 32768 Hz,
197 ; 30,51757813µs/bit in TMR3L:TMR3H 295 ; incrementing by 1 bit each 30.51757813 µs
198 movwf T3CON 296 movwf T3CON
297 ENDIF
298
199 299
200 ; SPI Module(s) 300 ; SPI Module(s)
201 ; SPI2: External Flash 301 ; SPI2: External Flash
202 movlw b'00110000' 302 movlw b'00110000'
203 movwf SSP2CON1 303 movwf SSP2CON1
204 ; movlw b'00000000' 304 ; movlw b'00000000'
205 clrf SSP2STAT 305 clrf SSP2STAT
206 ; ->0,25MHz Bit clock @1MHz mode (Eco) 306 ; -> 0.25 MHz Bit clock @ 1 MHz mode (Eco)
207 ; -> 4MHz Bit clock @16MHz mode (Normal) 307 ; -> 4 MHz Bit clock @ 16 MHz mode (Normal)
208 ; -> 16MHz Bit clock @64MHz mode (Fastest) 308 ; -> 16 MHz Bit clock @ 64 MHz mode (Fastest)
309
209 310
210 ; MSSP1 Module: I2C Master 311 ; MSSP1 Module: I2C Master
211 movlw b'00101000' ; I2C master mode 312 movlw b'00101000' ; I2C master mode
212 movwf SSP1CON1 313 movwf SSP1CON1
213 ; movlw b'00000000' 314 ; movlw b'00000000'
214 clrf SSP1CON2 315 clrf SSP1CON2
215 movlw 0x27 316 movlw 0x27
216 movwf SSP1ADD ; 100kHz @ 16MHz Fosc 317 movwf SSP1ADD ; 100kHz @ 16MHz Fosc
217 318
319
218 ; PWM Module(s) 320 ; PWM Module(s)
219 ; PWM1 for LED dimming 321 ; PWM 1 for LED dimming
220 movlw b'00001100' 322 movlw b'00001100'
221 movwf CCP1CON 323 movwf CCP1CON
222 movlw b'00000001' 324 movlw b'00000001'
223 movwf PSTR1CON ; pulse steering disabled 325 movwf PSTR1CON ; pulse steering disabled
224 movlw d'255' 326 movlw d'255'
227 clrf CCPR1L ; duty cycle 329 clrf CCPR1L ; duty cycle
228 clrf CCPR1H ; duty cycle 330 clrf CCPR1H ; duty cycle
229 movlw T2CON_NORMAL 331 movlw T2CON_NORMAL
230 movwf T2CON 332 movwf T2CON
231 333
232 ; Timer5 for ISR-independent wait routines 334
335 ; Timer 5 for ISR-independent wait routines
233 clrf T5GCON ; reset Timer5 gate control register 336 clrf T5GCON ; reset Timer5 gate control register
234 movlw b'10001001' ; 1:1 prescaler -> 2 seconds@32768Hz, synced 337 movlw b'10001011' ; synced, 16 bit mode, 1:1 prescaler -> 2 seconds till overrun @ 32768 Hz,
235 ; 30,51757813µs/bit in TMR5L:TMR5H 338 movwf T5CON ; incrementing by 1 bit each 30.51757813 µs
236 movwf T5CON 339
237 340
238 ; Timer7 for 62,5ms Interrupt (Sensor states) 341 banksel 0xF16 ; addresses F16h through F5Fh are also used by SFRs, but are not part of the access RAM
239 banksel 0xF16 ; addresses, F16h through F5Fh, are also used by SFRs, but are not part of the access RAM 342
343 ; Timer 7 for 62.5 ms Interrupt (sensor states)
240 clrf T7GCON ; reset Timer7 gate control register 344 clrf T7GCON ; reset Timer7 gate control register
241 movlw b'10001001' ; 1:1 prescaler -> 2 seconds@32768Hz, synced 345 movlw b'10001001' ; 1:1 prescaler -> 2 seconds @ 32768 Hz, synced
242 movwf T7CON 346 movwf T7CON
243 clrf TMR7L 347 clrf TMR7L
244 movlw .248 348 movlw .248
245 movwf TMR7H ; -> Rollover after 2048 cycles -> 62,5ms 349 movwf TMR7H ; -> rollover after 2048 cycles -> 62.5 ms
246 350
247 ; Turn off unused timer 351
352 ; turn off unused timers
248 movlw b'11000000' 353 movlw b'11000000'
249 movwf PMD0 354 movwf PMD0
355 IFDEF _external_sensor
250 movlw b'11010001' 356 movlw b'11010001'
357 ELSE
358 movlw b'11011001' ; includes turning off timer 3
359 ENDIF
251 movwf PMD1 360 movwf PMD1
252 movlw b'11010111' 361 movlw b'11010111'
253 movwf PMD2 362 movwf PMD2
254 movlw b'11111111' 363 movlw b'11111111'
255 movwf PMD3 364 movwf PMD3
256 365
257 ; CTMU 366
367 ; turn off unused CTMU
258 clrf CTMUCONH 368 clrf CTMUCONH
259 clrf CTMUCONL 369 clrf CTMUCONL
260 clrf CTMUICON 370 clrf CTMUICON
371
261 banksel common 372 banksel common
373
262 374
263 ; Interrupts 375 ; Interrupts
264 movlw b'11010000' 376 movlw b'11010000'
265 movwf INTCON 377 movwf INTCON
266 movlw b'00001000' ; BIT7=1: pullup for PORTB disabled 378 movlw b'00001000' ; Bit7=1: pull-up for PORTB disabled
267 movwf INTCON2 379 movwf INTCON2
268 movlw b'00000000' 380 movlw b'00000000'
269 movwf INTCON3 381 movwf INTCON3
270 movlw b'00000001' ; Bit0: TMR1 382 movlw b'00000001' ; Bit0: TMR1
271 movwf PIE1 383 movwf PIE1
276 movlw b'00100001' ; Bit0: RTCC, Bit5: UART2 388 movlw b'00100001' ; Bit0: RTCC, Bit5: UART2
277 movwf PIE3 389 movwf PIE3
278 movlw b'00001000' ; Bit3: TMR7 390 movlw b'00001000' ; Bit3: TMR7
279 movwf PIE5 391 movwf PIE5
280 392
281 bsf power_sw1 393 bcf active_reset_ostc_rx ; release RESET from RX circuitry
282 btfss power_sw1 394 ;bra power_up_switches
283 bra $-4 395
284 bsf power_sw2 396
285 btfss power_sw2 397 global power_up_switches
286 bra $-4 398 power_up_switches:
287 399 bsf power_sw1 ; switch on power supply for switch 1
288 bcf active_reset_ostc_rx ; start RX from RESET 400 btfss power_sw1 ; power established?
401 bra $-4 ; NO - wait
402 bsf power_sw2 ; switch on power supply for switch 2
403 btfss power_sw2 ; power established?
404 bra $-4 ; NO - wait
289 405
290 return 406 return
291 407
292 ;============================================================================= 408 ;=============================================================================
293 global speed_eco 409 ; CPU speed change request functions
294 speed_eco: 410
295 movlw d'1' 411 global request_speed_eco
296 movff WREG,cpu_speed_request ; bank-independent 412 request_speed_eco:
297 ; Done in ISR 413 movlw coding_speed_eco ; load coding for eco speed
414 movwf cpu_speed_request ; request ISR to change the CPU speed
415 return ; done
416
417 global request_speed_normal
418 request_speed_normal:
419 movlw coding_speed_normal ; load coding for normal speed
420 movwf cpu_speed_request ; request ISR to change the CPU speed
421 return ; done
422
423 global request_speed_fastest
424 request_speed_fastest:
425 movlw coding_speed_fastest ; load coding for fastest speed
426 movwf cpu_speed_request ; request ISR to change the CPU speed
427 return ; done
428
429 ;=============================================================================
430 ; Backup the first 128 bytes from program memory to EEPROM
431 ;
432 global backup_flash_page
433 backup_flash_page:
434 banksel common
435 movlw 0x00 ; start address in internal program memory
436 movwf TBLPTRL
437 movwf TBLPTRH
438 movwf TBLPTRU
439
440 movlw .128 ; copy 1 block = 128 byte
441 movwf lo ; byte counter
442
443 clrf EEADR ; start address in EEPROM, low
444 movlw .3 ; start address in EEPROM, high
445 movwf EEADRH
446
447 TBLRD*- ; dummy read to be in 128 byte block
448 backup_flash_loop:
449 tblrd+* ; read one byte from program memory (with pre-increment)
450 movff TABLAT,EEDATA ; transfer byte from program memory read to EEPROM write
451 call write_eeprom ; execute EEPROM write
452 incf EEADR,F ; increment EEPROM address
453 decfsz lo,F ; 128 byte done?
454 bra backup_flash_loop ; NO - loop
455 clrf EEADRH ; YES - reset EEPROM high address
456 return ; - done
457
458 ;=============================================================================
459 ; Restore the first 128 bytes from EEPROM to program memory
460 ;
461 global restore_flash
462 restore_flash:
463 banksel common
464 movlw 0x00 ; start address in internal program memory
465 movwf TBLPTRL
466 movwf TBLPTRH
467 movwf TBLPTRU
468
469 movlw b'10010100' ; setup block erase
470 rcall restore_write ; execute block erase
471
472 movlw .128 ; copy 1 block = 128 byte
473 movwf lo ; byte counter
474
475 clrf EEADR ; start address in EEPROM, low
476 movlw .3 ; start address in EEPROM, high
477 movwf EEADRH
478
479 TBLRD*- ; dummy read to be in 128 byte block
480 restore_flash_loop:
481 call read_eeprom ; read one byte from EEPROM
482 incf EEADR,F ; increment EEPROM address
483 movff EEDATA,TABLAT ; transfer byte from EEPROM read to program memory write
484 tblwt+* ; execute program memory write (with pre-increment)
485 decfsz lo,F ; 128 bytes done?
486 bra restore_flash_loop ; NO - loop
487 movlw b'10000100' ; YES - setup block write
488 rcall restore_write ; - execute block write
489 reset ; - done, reset CPU
490
491 restore_write:
492 movwf EECON1 ; type of memory to write in
493 movlw 0x55
494 movwf EECON2
495 movlw 0xAA
496 movwf EECON2
497 bsf EECON1,WR ; execute write
498 nop
499 nop
298 return 500 return
299 ;=============================================================================
300 global speed_normal
301 speed_normal:
302 movlw d'2'
303 movff WREG,cpu_speed_request ; bank-independent
304 ; Done in ISR
305 return
306 ;=============================================================================
307 global speed_fastest
308 speed_fastest:
309 movlw d'3'
310 movff WREG,cpu_speed_request ; bank-independent
311 ; Done in ISR
312 return
313 ;=============================================================================
314 501
315 END 502 END