Mercurial > public > hwos_code
annotate src/hwos.asm @ 642:a9a0188091e4
fix rare upgrade issue with OSTC sport 2019 hardware
| author | heinrichsweikamp |
|---|---|
| date | Thu, 14 Jan 2021 16:24:07 +0100 |
| parents | 8c1f1f334275 |
| children | 7d8a4c60ec1a 5b7fe7777425 |
| rev | line source |
|---|---|
| 0 | 1 ;============================================================================= |
| 2 ; | |
| 634 | 3 ; File hwos.asm * combined next generation V3.09.4e |
| 0 | 4 ; |
| 275 | 5 ; Definition of the hwOS dive computer platform. |
| 0 | 6 ; |
| 7 ; Copyright (c) 2011, JD Gascuel, HeinrichsWeikamp, all right reserved. | |
| 8 ;============================================================================= | |
| 9 ; HISTORY | |
| 604 | 10 ; 2011-05-24 : [jDG] Cleanups from initial Matthias code |
| 11 ; 2011-06-24 : [MH] Added clock speeds | |
| 12 | |
| 623 | 13 ;============================================================================= |
| 14 | |
| 634 | 15 #DEFINE INSIDE_HWOS_ASM |
| 604 | 16 |
| 275 | 17 #include "hwos.inc" |
| 623 | 18 #include "eeprom_rs232.inc" |
| 0 | 19 |
| 634 | 20 ;----------------------------- PIC Configuration ----------------------------- |
| 21 ; | |
| 22 CONFIG RETEN = OFF ; regulator power while in sleep mode controlled by SRETEN bit | |
| 23 CONFIG SOSCSEL = HIGH ; high power SOSC circuit selected | |
| 24 CONFIG XINST = OFF ; extended instruction set disabled | |
| 623 | 25 CONFIG FOSC = INTIO2 ; internal RC oscillator, no clock-out |
| 634 | 26 CONFIG PLLCFG = OFF ; oscillator used directly |
| 27 CONFIG IESO = OFF ; two-speed start-up disabled | |
| 28 CONFIG PWRTEN = OFF ; power-up timer disabled, because incompatible with ICD3 (Ri-400) | |
| 29 CONFIG BOREN = ON ; brown-out reset controlled with SBOREN bit | |
| 30 CONFIG BORV = 2 ; brown-out reset voltage 2.0V | |
| 31 CONFIG BORPWR = MEDIUM ; brown-out monitoring set to medium power level | |
| 32 CONFIG WDTEN = ON ; watchdog timer enabled, controlled by SWDTEN bit | |
| 33 CONFIG WDTPS = 128 ; watchdog timer post-scaler 1:128 | |
| 34 CONFIG RTCOSC = SOSCREF ; RTCC uses SOSC as ref clock | |
| 35 CONFIG MCLRE = ON ; MCLR enabled, RG5 disabled | |
| 36 CONFIG CCP2MX = PORTBE ; ECCP2 muxed with RE7 (micro-controller mode) /RB3 (other modes) | |
| 623 | 37 |
| 38 | |
| 39 ;---------------------------- Bank0 ACCESS RAM ------------------------------- | |
| 634 | 40 ; |
| 623 | 41 ac_ram equ 0x000 |
| 42 ac_ram udata_acs ac_ram ; access RAM data | |
| 43 | |
| 44 | |
| 45 ;---- Flags - Hardware Descriptors | |
| 46 HW_descriptor res 1 ; OSTC - model descriptor (cleared & rebuilt in restart) | |
| 47 HW_variants res 1 ; OSTC - model variants (NOT cleared in restart) | |
| 628 | 48 |
| 623 | 49 ;---- Flags - Hardware States |
| 628 | 50 HW_flags_state1 res 1 ; hardware - states 1 |
| 51 HW_flags_state2 res 1 ; hardware - states 2 | |
| 623 | 52 |
| 53 ;--- Flags - Operating System | |
| 54 OS_flags_persist res 1 ; system - persistent settings (NOT cleared in restart) | |
| 55 OS_flags_ISR1 res 1 ; system - ISR control 1 | |
| 56 OS_flags_ISR2 res 1 ; system - ISR control 2 | |
| 57 | |
| 58 ;---- Flags - Operating Modes | |
| 59 OM_flags_mode res 1 ; operating modes | |
| 60 | |
| 61 ;---- Flags - Dive Modes | |
| 62 DM_flags_deco res 1 ; dive mode - main dive & deco mode | |
| 63 | |
| 64 ;---- CPU Speed | |
| 65 cpu_speed_request res 1 ; requested CPU speed: =1: eco, =2: normal, =3: fastest | |
| 66 cpu_speed_state res 1 ; current CPU speed: =1: eco, =2: normal, =3: fastest | |
| 67 | |
| 68 ;---- Timebase & Eventbase | |
| 69 timebase res 1 ; timed trigger flags and running timebase | |
| 70 eventbase res 1 ; event trigger flags | |
| 71 | |
| 72 ;---- Timeout-Timer Service | |
| 73 isr_timeout_timer res 1 ; timeout timer | |
| 74 isr_timeout_reload res 1 ; timeout reload value | |
| 75 | |
| 76 ;---- Dive Times | |
| 77 total_divetime_secs res 2 ; total dive time, seconds | |
| 78 counted_divetime_mins res 2 ; counted dive time, minutes | Attention: do not change the position of | |
| 79 counted_divetime_secs res 1 ; counted dive time, seconds | these 2 Variables relative to each other! | |
| 604 | 80 |
| 623 | 81 ;---- Dive Times / Apnoe |
| 82 apnoe_surface_mins res 1 ; surface time minutes | Attention: do not change the position of | |
| 83 apnoe_surface_secs res 1 ; surface time seconds | these 2 Variables relative to each other! | |
| 84 | |
| 85 apnoe_dive_mins res 1 ; dive time minutes | Attention: do not change the position of | |
| 86 apnoe_dive_secs res 1 ; dive time seconds | these 2 Variables relative to each other! | |
| 87 | |
| 88 ;---- Profile Recording | |
| 89 sampling_rate res 1 ; configured sampling rate | |
| 90 sampling_timer res 1 ; sampling timer | |
| 91 | |
| 92 ;---- Simulator Mode | |
| 93 simulatormode_depth res 1 ; depth in simulator mode | |
| 94 | |
| 95 ;---- HUD / Sensor Data | |
| 96 hud_status_byte res 1 ; HUD status byte, see definition of flags | Attention: keep relative position | |
| 97 hud_battery_mv res 2 ; hud/ppo2 monitor battery voltage in mV | between these two variables! | |
| 98 | |
| 634 | 99 ;---- Battery Management |
| 100 battery_capacity_internal res 2 ; for internal battery gauging | |
| 101 battery_capacity res 2 ; for battery gauge IC | |
| 102 battery_offset res 2 ; for battery gauge IC | |
| 103 battery_type res 1 ; =0:1.5V, =1:3.6V Saft, =2:LiIon 3.7V/0.8Ah, =3:LiIon 3.7V/3.1Ah, =4: LiIon 3.7V/2.3Ah | |
| 104 battery_accumulated_charge res 2 ; raw values in battery gauge IC | |
| 105 battery_temperature res 2 ; battery temperature in 0.1 Kelvin | |
| 106 gauge_status_byte res 1 ; gauge IC status byte | |
| 623 | 107 |
| 634 | 108 |
| 109 | |
| 110 ; 40 byte user data | |
| 623 | 111 ; 32 byte tmp data placed by C compiler |
| 112 ; 20 byte variables placed by math library | |
| 113 ; == | |
| 634 | 114 ; 92 byte used, 4 byte free (96 byte total available) |
| 623 | 115 |
| 631 | 116 |
| 623 | 117 global HW_descriptor |
| 118 global HW_variants | |
| 628 | 119 global HW_flags_state1 |
| 120 global HW_flags_state2 | |
| 623 | 121 global OS_flags_persist |
| 122 global OS_flags_ISR1 | |
| 123 global OS_flags_ISR2 | |
| 124 global OM_flags_mode | |
| 125 global DM_flags_deco | |
| 126 global cpu_speed_request | |
| 127 global cpu_speed_state | |
| 128 global timebase | |
| 129 global eventbase | |
| 130 global isr_timeout_timer | |
| 131 global isr_timeout_reload | |
| 132 global total_divetime_secs | |
| 133 global counted_divetime_mins | |
| 134 global counted_divetime_secs | |
| 135 global apnoe_surface_secs | |
| 136 global apnoe_surface_mins | |
| 137 global apnoe_dive_secs | |
| 138 global apnoe_dive_mins | |
| 139 global sampling_rate | |
| 140 global sampling_timer | |
| 141 global simulatormode_depth | |
| 142 global hud_status_byte | |
| 143 global hud_battery_mv | |
| 634 | 144 global battery_capacity_internal |
| 145 global battery_capacity | |
| 146 global battery_offset | |
| 147 global battery_type | |
| 148 global battery_accumulated_charge | |
| 149 global battery_temperature | |
| 150 global gauge_status_byte | |
| 151 | |
| 152 | |
| 153 ;============================================================================= | |
| 154 hwos1 CODE | |
| 155 ;============================================================================= | |
| 623 | 156 |
| 157 ;----------------------------------------------------------------------------- | |
| 634 | 158 ; Master Initialization of Hardware Resources |
| 159 ; | |
| 604 | 160 global init_ostc |
| 275 | 161 init_ostc: |
| 623 | 162 |
| 163 ; Oscillator | |
| 164 banksel common ; select bank common | |
| 634 | 165 movlw b'01110010' ; select 16 MHz INTOSC |
| 166 movwf OSCCON ; ... | |
| 167 movlw b'00001000' ; secondary oscillator running | |
| 168 movwf OSCCON2 ; ... | |
| 169 movlw b'00000000' ; 4x PLL disable (Bit 6) - only works with 8 or 16MHz (=32 or 64MHz) | |
| 170 movwf OSCTUNE ; ... | |
| 608 | 171 |
| 623 | 172 movlw coding_speed_normal ; coding for normal CPU speed |
| 173 movwf cpu_speed_request ; store CPU shall run with normal speed | |
| 174 movwf cpu_speed_state ; store CPU does run with normal speed | |
| 608 | 175 |
|
642
a9a0188091e4
fix rare upgrade issue with OSTC sport 2019 hardware
heinrichsweikamp
parents:
640
diff
changeset
|
176 ;bcf RCON,SBOREN ; brown-out off (not needed here, is handled in bootloader) |
| 604 | 177 bcf RCON,IPEN ; priority interrupts off |
| 608 | 178 |
| 604 | 179 banksel WDTCON |
| 634 | 180 movlw b'10000000' ; setup watchdog |
| 181 movwf WDTCON ; ... | |
| 0 | 182 |
| 608 | 183 |
| 0 | 184 ; I/O Ports |
| 634 | 185 banksel 0xF16 ; addresses F16h ... F5Fh are not part of the access RAM |
| 186 | |
| 604 | 187 clrf REFOCON ; no reference oscillator active on REFO pin |
| 188 clrf ODCON1 ; disable open drain capability | |
| 189 clrf ODCON2 ; disable open drain capability | |
| 190 clrf ODCON3 ; disable open drain capability | |
| 634 | 191 clrf CM1CON ; disable comparator 1 |
| 192 clrf CM2CON ; disable comparator 2 | |
| 193 clrf CM3CON ; disable comparator 3 | |
| 0 | 194 |
| 634 | 195 movlw b'11000000' ; ANSEL0: AN7, AN6 -> analog inputs, PORTA is digital |
| 196 movwf ANCON0 ; ... | |
| 197 movlw b'00000111' ; ANSEL1: AN8, AN9, AN10 -> analog input | |
| 198 movwf ANCON1 ; ... | |
| 640 | 199 clrf ANCON2 |
| 634 | 200 |
| 201 banksel common ; back to bank common | |
| 0 | 202 |
| 604 | 203 ; movlw b'00000000' ; 1= input -> Data TFT_high |
| 634 | 204 clrf TRISA ; ... |
| 604 | 205 ; movlw b'00000000' ; init port |
| 634 | 206 clrf PORTA ; ... |
| 0 | 207 |
| 604 | 208 movlw b'00000011' ; 1= input, (RB0, RB1) -> switches, RB2 -> Power_MCP, RB3 -> s8_npower, RB4 -> LED_green/rx_nreset, RB5 -> /TFT_POWER |
| 634 | 209 movwf TRISB ; ... |
| 604 | 210 movlw b'00111000' ; init port, rx_nreset=1 -> hard reset RX |
| 634 | 211 movwf PORTB ; ... |
| 0 | 212 |
| 604 | 213 movlw b'10011010' ; 1= input, (RC0, RC1) -> SOSC, RC2 -> TFT_LED_PWM, (RC3,RC4) -> I²C, RC5 -> MOSI_MS5541, (RC6, RC7) -> UART1 |
| 634 | 214 movwf TRISC ; ... |
| 604 | 215 ; movlw b'00000000' ; init port |
| 634 | 216 clrf PORTC ; ... |
| 0 | 217 |
| 604 | 218 movlw b'00100000' ; 1= input, RD0 -> TFT_NCS, RD1 -> TFT_RS, RD2 -> TFT_NWR, RD3 -> TFT_RD, RD4 -> MOSI_Flash, RD5 -> MISO_Flash, RD6 -> CLK_Flash, RD7 -> TFT_NRESET |
| 634 | 219 movwf TRISD ; ... |
| 604 | 220 ; movlw b'00000000' ; init port |
| 634 | 221 clrf PORTD ; ... |
| 0 | 222 |
| 628 | 223 movlw b'00100000' ; 1= input, RE0 -> not_Power_BLE, RE1 -> Power_IR, RE2 -> CS_MCP, RE3 -> LED_blue, RE4 -> power_sw1, RE5 -> leave as input |
| 634 | 224 movwf TRISE ; ... |
| 627 | 225 movlw b'00010001' ; init port |
| 634 | 226 movwf PORTE ; ... |
| 0 | 227 |
| 604 | 228 movlw b'01111110' ; 1= input, (RF1, RF2, RF3, RF4, RF5) -> Analog |
| 634 | 229 movwf TRISF ; ... |
| 604 | 230 ; movlw b'00000000' ; init port |
| 634 | 231 clrf PORTF ; ... |
| 0 | 232 |
| 640 | 233 movlw b'00000110' ; 1= input, <7:6> not implemented, RG0 -> TX3_PIEZO_CFG, , RG1 -> TX2, RG2 -> RX2, RG3 -> AN17_RSSI, RG4 -> SOSC_OUT, RG5 -> /RESET |
| 634 | 234 movwf TRISG ; ... |
| 604 | 235 movlw b'00000001' ; init port |
| 634 | 236 movwf PORTG ; ... |
| 0 | 237 |
| 604 | 238 ; movlw b'00000000' ; 1= input -> Data TFT_low |
| 634 | 239 clrf TRISH ; ... |
| 604 | 240 ; movlw b'00000000' ; init port |
| 634 | 241 clrf PORTH ; ... |
| 0 | 242 |
| 623 | 243 movlw b'10011011' ; 1= input, RJ4 -> vusb_in, RJ5 -> power_sw2, RJ6 -> CLK_MS5541, RJ7 -> MISO_MS5541 |
| 634 | 244 movwf TRISJ ; ... |
| 604 | 245 movlw b'00100000' ; init port |
| 634 | 246 movwf PORTJ ; ... |
| 0 | 247 |
| 623 | 248 |
| 618 | 249 ; disable Charger by default |
| 623 | 250 bsf charge_disable ; set charging-inhibit signal |
| 251 bcf charge_enable ; activate charging-inhibit signal | |
| 252 | |
| 253 | |
| 634 | 254 ; Timer 7 for 62.5 ms Interrupt (Sensor States) |
| 255 banksel 0xF16 ; addresses F16h...F5Fh are not part of the access RAM | |
| 256 clrf T7GCON ; clear timer 7 gate control register | |
| 257 movlw b'10001101' ; bit 7-6: 10 = clock source SOSC/SCLKI (with bit 3 = 1) | |
| 258 ; bit 5-4: 00 = 1:1 prescaler | |
| 259 ; bit 3: 1 = clock source SOSC/SCLKI (with bit 7-6 = 10) | |
| 260 ; bit 2: 1 = DO NOT synchronize external clock input (else OSTC won't wake up from sleep!) | |
| 261 ; bit 1: 0 = 2x 8 bit operation | |
| 262 ; bit 0: 1 = timer enabled | |
| 263 ; 32768 Hz clock source, 1:1 prescaler -> timer counts at 30.51757813 µs/bit | |
| 264 movwf T7CON ; ... | |
| 265 movlw .248 ; load timer 7, high byte (8x256 ticks -> 62.5 ms) | |
| 266 movwf TMR7H ; ... | |
| 267 clrf TMR7L ; load timer 7, low byte | |
| 0 | 268 |
| 623 | 269 |
| 634 | 270 ; Timer 0 - not used |
| 271 movlw b'00000001' ; timer0 stopped (1:4 prescaler) | |
| 272 movwf T0CON ; ... | |
| 273 | |
| 274 | |
| 275 ; Timer 1 - Button hold-down Timer | |
| 276 ; movlw b'10001100' ; old setting | |
| 277 movlw b'10001010' ; bit 7-6: 10 = clock source SOSC/SCLKI (with bit 3 = 1) | |
| 278 ; bit 5-4: 00 = 1:1 prescaler | |
| 279 ; bit 3: 1 = clock source SOSC/SCLKI (with bit 7-6 = 10) | |
| 280 ; bit 2: 0 = synchronize external clock input | |
| 281 ; bit 1: 1 = 16 bit operation | |
| 282 ; bit 0: 0 = timer stopped | |
| 283 ; 32768 Hz clock source, 1:1 prescaler -> timer counts at 30.51757813 µs/bit | |
| 284 movwf T1CON ; ... | |
| 0 | 285 |
| 623 | 286 |
| 0 | 287 ; RTCC |
| 623 | 288 banksel 0xF16 ; addresses, F16h through F5Fh, are also used by SFRs, but are not part of the access RAM |
| 634 | 289 movlw 0x55 ; unlock sequence for RTCWREN |
| 290 movwf EECON2 ; ... | |
| 291 movlw 0xAA ; ... | |
| 292 movwf EECON2 ; ... | |
| 293 bsf RTCCFG,RTCWREN ; unlock access to RTC | |
| 294 bsf RTCCFG,RTCPTR1 ; set pointer register to b'11' | |
| 295 bsf RTCCFG,RTCPTR0 ; .. | |
| 623 | 296 bsf RTCCFG,RTCEN ; module enable |
| 297 bsf RTCCFG,RTCOE ; output enable | |
| 298 movlw b'00000100' ; 32768 Hz SOCS on RTCC pin (PORTG,4) Bit7-5: pull-ups for Port D, E and J | |
| 634 | 299 movwf PADCFG1 ; ... |
| 300 movlw b'11000000' ; 1/2 second alarm | |
| 301 movwf ALRMCFG ; ... | |
| 302 movlw d'1' ; select alarm repeat counter to 1 | |
| 303 movwf ALRMRPT ; ... | |
| 304 movlw 0x55 ; unlock sequence for RTCWREN | |
| 305 movwf EECON2 ; ... | |
| 306 movlw 0xAA ; ... | |
| 307 movwf EECON2 ; ... | |
| 308 bcf RTCCFG,RTCWREN ; lock access to RTC | |
| 309 banksel common ; back to bank common | |
| 623 | 310 |
| 614 | 311 |
| 0 | 312 ; A/D Converter |
| 313 movlw b'00011000' ; power off ADC, select AN6 | |
| 634 | 314 movwf ADCON0 ; ... |
| 0 | 315 movlw b'00100000' ; 2.048V Vref+ |
| 634 | 316 movwf ADCON1 ; ... |
| 640 | 317 movlw b'10001111' ; right aligned, 2 x T_AD acquisition time, clock derived from A/D RC oscillator (To be CPU-clock independent) |
| 634 | 318 movwf ADCON2 ; ... |
| 0 | 319 |
| 623 | 320 |
| 634 | 321 ; Serial Port 1 (TRISC6/7) |
| 631 | 322 movlw b'00001000' ; switch baud generator to 16 bit mode (BRG16=1) |
| 323 movwf BAUDCON1 ; ... | |
| 324 ; SPBRGH:SPBRG = .34 : 114285 BAUD @ 16MHz (+0.79% error at 115200 baud) | |
| 325 ; SPBRGH:SPBRG = .207 : 19230 BAUD @ 16MHz (-0.16% error at 19200 baud) | |
| 326 movlw .34 ; select 114285 baud (low byte) | |
| 327 movwf SPBRG1 ; ... | |
| 328 clrf SPBRGH1 ; ... (high byte) | |
| 204 | 329 |
| 631 | 330 clrf RCSTA1 ; disable UART RX |
| 331 clrf TXSTA1 ; disable UART TX | |
| 332 bcf PORTC,6 ; tie TX output hard to GND | |
| 0 | 333 |
| 623 | 334 |
| 634 | 335 ; Serial Port 2 (TRISG2) for IR/S8 digital Interface |
| 623 | 336 ; |
| 337 ; - will be initialized by enable_ir_s8 (eeprom_rs232.asm) in case IR/S8 shall be available | |
| 338 | |
| 0 | 339 |
| 623 | 340 ; Timer 3 for IR-RX Timeout |
| 341 IFDEF _external_sensor | |
| 634 | 342 clrf T3GCON ; clear Timer3 gate control register |
| 343 ; movlw b'10001101' ; old value | |
| 344 movlw b'10001011' ; bit 7-6: 10 = clock source SOSC/SCLKI (with bit 3 = 1) | |
| 345 ; bit 5-4: 00 = 1:1 prescaler | |
| 346 ; bit 3: 1 = clock source SOSC/SCLKI (with bit 7-6 = 10) | |
| 347 ; bit 2: 0 = synchronize external clock input | |
| 348 ; bit 1: 1 = 16 bit operation | |
| 349 ; bit 0: 1 = timer enabled | |
| 350 ; 32768 Hz clock source, 1:1 prescaler -> timer counts at 30.51757813 µs/bit | |
| 351 movwf T3CON ; ... | |
| 623 | 352 ENDIF |
| 353 | |
| 0 | 354 |
| 355 ; SPI Module(s) | |
| 356 ; SPI2: External Flash | |
| 634 | 357 movlw b'00110000' ; set up SPI module |
| 358 movwf SSP2CON1 ; ... | |
| 359 clrf SSP2STAT ; ... | |
| 360 ; resulting bit clocks: 0.25 MHz @ 1 MHz CPU clock (Eco) | |
| 361 ; 4.00 MHz @ 16 MHz CPU clock (Normal) | |
| 362 ; 16.00 MHz @ 64 MHz CPU clock (Fastest) | |
| 623 | 363 |
| 0 | 364 |
| 365 ; MSSP1 Module: I2C Master | |
| 634 | 366 movlw b'00101000' ; set up I2C to master mode |
| 367 movwf SSP1CON1 ; ... | |
| 368 clrf SSP1CON2 ; ... | |
| 369 movlw 0x9C ; select speed 100kHz @ 64MHz Fosc | |
| 370 movwf SSP1ADD ; ... | |
| 0 | 371 |
| 623 | 372 |
| 0 | 373 ; PWM Module(s) |
| 623 | 374 ; PWM 1 for LED dimming |
| 634 | 375 movlw b'00001100' ; set up PWM module |
| 376 movwf CCP1CON ; ... | |
| 377 movlw b'00000001' ; pulse steering disabled | |
| 378 movwf PSTR1CON ; ... | |
| 379 movlw d'254' ; select period | |
| 380 movwf PR2 ; ... | |
| 604 | 381 ; 255 is max brightness (300 mW) |
| 634 | 382 clrf CCPR1L ; duty cycle, low byte |
| 383 clrf CCPR1H ; duty cycle, high byte | |
| 384 movlw T2CON_NORMAL ; set timer for normal dimming | |
| 385 movwf T2CON ; ... | |
| 623 | 386 |
| 0 | 387 |
| 634 | 388 ; Timer 5 for ISR-independent Wait/Timeout |
| 389 clrf T5GCON ; clear Timer5 gate control register | |
| 390 ; movlw b'10001111' ; old value | |
| 391 movlw b'10001011' ; bit 7-6: 10 = clock source SOSC/SCLKI (with bit 3 = 1) | |
| 392 ; bit 5-4: 00 = 1:1 prescaler | |
| 393 ; bit 3: 1 = clock source SOSC/SCLKI (with bit 7-6 = 10) | |
| 394 ; bit 2: 0 = synchronize external clock input | |
| 395 ; bit 1: 1 = 16 bit operation | |
| 396 ; bit 0: 1 = timer enabled | |
| 397 ; 32768 Hz clock source, 1:1 prescaler -> timer counts at 30.51757813 µs/bit | |
| 398 movwf T5CON ; ... | |
| 0 | 399 |
| 640 | 400 ; Timer 4 for debounce of new digital piezo circuity |
| 401 movlw b'01111011' ; 1:8 Postscale, Prescale = 1, Timer 4 OFF | |
| 402 movwf T4CON | |
| 403 setf PR4 | |
| 404 | |
| 634 | 405 ; turn off unused Timers |
| 640 | 406 banksel 0xF16 ; addresses F16h...F5Fh are not part of the access RAM |
| 634 | 407 movlw b'11000000' ; disable ECCP3 and ECCP2 |
| 408 movwf PMD0 ; ... | |
| 623 | 409 IFDEF _external_sensor |
| 640 | 410 movlw b'11000001' ; disable PSP, CTMU and EMB |
| 623 | 411 ELSE |
| 640 | 412 movlw b'11001001' ; disable PSP, CTMU, Timer 3 and EMB |
| 623 | 413 ENDIF |
| 634 | 414 movwf PMD1 ; ... |
| 415 movlw b'11010111' ; disable timer 10, timer 8, timer 6 and comparators 1-3 | |
| 416 movwf PMD2 ; ... | |
| 417 movlw b'11111111' ; disable CCP 4-10 and timer 12 | |
| 418 movwf PMD3 ; ... | |
| 608 | 419 |
| 623 | 420 |
| 421 ; turn off unused CTMU | |
| 634 | 422 ;banksel 0xF16 ; addresses F16h...F5Fh are not part of the access RAM |
| 423 clrf CTMUCONH ; disable CTMU | |
| 424 clrf CTMUCONL ; ... | |
| 425 clrf CTMUICON ; ... | |
| 426 | |
| 623 | 427 |
| 604 | 428 banksel common |
| 608 | 429 |
| 623 | 430 |
| 0 | 431 ; Interrupts |
| 634 | 432 bcf PIR5,TMR7IF ; if applicable clear timer 7 IRQ flag |
| 0 | 433 |
| 634 | 434 movlw b'11010000' ; enable global IRQ, peripheral IRQ and external IRQ 0 |
| 435 movwf INTCON ; ... | |
| 436 movlw b'00001000' ; external IRQ 0 on falling edge, pull-up of PORTB by TRIS register | |
| 437 movwf INTCON2 ; ... | |
| 438 movlw b'00000000' ; disable external IRQs 1,2,3 | |
| 439 movwf INTCON3 ; ... | |
| 440 movlw b'00000001' ; enable timer 1 IRQ | |
| 441 movwf PIE1 ; ... | |
| 442 movlw b'00000010' ; enable timer 3 IRQ | |
| 443 movwf PIE2 ; ... | |
| 444 movlw b'00000000' ; enable timer 5 IRQ | |
| 445 movwf PIE5 ; ... | |
| 446 movlw b'00000001' ; enable RTCC IRQ | |
| 447 movwf PIE3 ; ... | |
| 640 | 448 movlw b'00001001' ; enable timer 7 and timer 4 IRQ |
| 634 | 449 movwf PIE5 ; ... |
| 450 | |
| 451 ; Release RESET from RX Circuitry | |
| 452 bcf active_reset_ostc_rx | |
| 453 | |
| 454 ; Power-up the Switches | |
| 623 | 455 ;bra power_up_switches |
| 456 | |
| 0 | 457 |
| 634 | 458 ;----------------------------------------------------------------------------- |
| 459 ; Power-up the Switches | |
| 460 ; | |
| 623 | 461 global power_up_switches |
| 462 power_up_switches: | |
| 463 bsf power_sw1 ; switch on power supply for switch 1 | |
| 464 btfss power_sw1 ; power established? | |
| 465 bra $-4 ; NO - wait | |
| 634 | 466 |
| 623 | 467 bsf power_sw2 ; switch on power supply for switch 2 |
| 468 btfss power_sw2 ; power established? | |
| 469 bra $-4 ; NO - wait | |
| 204 | 470 |
| 634 | 471 return ; done |
| 472 | |
| 0 | 473 |
| 474 ;============================================================================= | |
| 634 | 475 hwos2 CODE |
| 476 ;============================================================================= | |
| 623 | 477 |
| 634 | 478 ;----------------------------------------------------------------------------- |
| 479 ; CPU Speed Change Requests | |
| 480 ; | |
| 623 | 481 global request_speed_eco |
| 482 request_speed_eco: | |
| 483 movlw coding_speed_eco ; load coding for eco speed | |
| 484 movwf cpu_speed_request ; request ISR to change the CPU speed | |
| 485 return ; done | |
| 486 | |
| 487 global request_speed_normal | |
| 488 request_speed_normal: | |
| 489 movlw coding_speed_normal ; load coding for normal speed | |
| 490 movwf cpu_speed_request ; request ISR to change the CPU speed | |
| 491 return ; done | |
| 492 | |
| 493 global request_speed_fastest | |
| 494 request_speed_fastest: | |
| 495 movlw coding_speed_fastest ; load coding for fastest speed | |
| 496 movwf cpu_speed_request ; request ISR to change the CPU speed | |
| 497 return ; done | |
| 498 | |
| 634 | 499 |
| 0 | 500 ;============================================================================= |
| 634 | 501 hwos3 CODE |
| 502 ;============================================================================= | |
| 503 | |
| 504 ;----------------------------------------------------------------------------- | |
| 505 ; Backup the first 128 bytes from program FLASH to EEPROM | |
| 623 | 506 ; |
| 507 global backup_flash_page | |
| 508 backup_flash_page: | |
| 509 banksel common | |
| 631 | 510 |
| 634 | 511 ; set start address in internal program FLASH |
| 631 | 512 movlw 0x00 ; set 0x000000 |
| 513 movwf TBLPTRL ; ... | |
| 514 movwf TBLPTRH ; ... | |
| 515 movwf TBLPTRU ; ... | |
| 516 TBLRD*- ; dummy read to be in 128 byte block | |
| 517 | |
| 518 ; set start address in EEPROM | |
| 519 EEPROM_SET_ADDRESS eeprom_prog_page0_backup | |
| 623 | 520 |
| 521 movlw .128 ; copy 1 block = 128 byte | |
| 631 | 522 movwf eeprom_loop ; initialize loop counter |
| 623 | 523 backup_flash_loop: |
| 634 | 524 tblrd+* ; read one byte from program FLASH (with pre-increment) |
| 525 movff TABLAT,EEDATA ; transfer byte from program FLASH read to EEPROM write | |
| 631 | 526 call write_eeprom ; execute EEPROM write |
| 623 | 527 incf EEADR,F ; increment EEPROM address |
| 631 | 528 decfsz eeprom_loop,F ; all 128 byte done? |
| 623 | 529 bra backup_flash_loop ; NO - loop |
| 631 | 530 return ; YES - done |
| 623 | 531 |
| 634 | 532 |
| 0 | 533 ;============================================================================= |
| 634 | 534 hwos4 CODE |
| 535 ;============================================================================= | |
| 536 | |
| 537 ;----------------------------------------------------------------------------- | |
| 538 ; Restore the first 128 bytes from EEPROM to program FLASH | |
| 623 | 539 ; |
| 540 global restore_flash | |
| 541 restore_flash: | |
| 542 banksel common | |
| 631 | 543 |
| 634 | 544 ;set start address in internal program FLASH |
| 631 | 545 movlw 0x00 ; set 0x000000 |
| 546 movwf TBLPTRL ; ... | |
| 547 movwf TBLPTRH ; ... | |
| 548 movwf TBLPTRU ; ... | |
| 549 TBLRD*- ; dummy read to be in 128 byte block | |
| 623 | 550 |
| 551 movlw b'10010100' ; setup block erase | |
| 552 rcall restore_write ; execute block erase | |
| 553 | |
| 631 | 554 ; set start address in EEPROM |
| 555 EEPROM_SET_ADDRESS eeprom_prog_page0_backup | |
| 623 | 556 |
| 631 | 557 movlw .128 ; copy 1 block = 128 byte |
| 558 movwf eeprom_loop ; initialize loop counter | |
| 623 | 559 restore_flash_loop: |
| 631 | 560 call read_eeprom ; execute EEPROM read |
| 623 | 561 incf EEADR,F ; increment EEPROM address |
| 634 | 562 movff EEDATA,TABLAT ; transfer byte from EEPROM read to program FLASH write |
| 563 tblwt+* ; execute program FLASH write (with pre-increment) | |
| 631 | 564 decfsz eeprom_loop,F ; all 128 bytes done? |
| 565 bra restore_flash_loop ; NO - loop | |
| 623 | 566 movlw b'10000100' ; YES - setup block write |
| 567 rcall restore_write ; - execute block write | |
| 568 reset ; - done, reset CPU | |
| 569 | |
| 570 restore_write: | |
| 631 | 571 movwf EECON1 ; configure operation |
| 572 movlw 0x55 ; unlock sequence | |
| 573 movwf EECON2 ; ... | |
| 574 movlw 0xAA ; ... | |
| 575 movwf EECON2 ; ... | |
| 576 bsf EECON1,WR ; execute operation | |
| 577 nop ; wait for operation to complete | |
| 578 nop ; ... | |
| 579 return ; done | |
| 580 | |
| 634 | 581 |
| 631 | 582 ;============================================================================= |
| 634 | 583 hwos5 CODE |
| 584 ;============================================================================= | |
| 585 | |
| 586 ;----------------------------------------------------------------------------- | |
| 587 ; Memory clear and move Functions, to be used via Macros | |
| 631 | 588 ; |
| 589 global memory_clear | |
| 590 memory_clear: | |
| 591 clrf POSTINC1 ; clear address | |
| 592 decfsz WREG ; decrement loop counter, became zero? | |
| 593 bra memory_clear ; NO - loop | |
| 594 return ; YES - done | |
| 595 | |
| 596 global memory_move | |
| 597 memory_move: | |
| 598 movff POSTINC1,POSTINC2 ; copy from-to | |
| 599 decfsz WREG ; decrement loop counter, became zero? | |
| 600 bra memory_move ; NO - loop | |
| 601 return ; YES - done | |
| 0 | 602 |
| 634 | 603 |
| 604 ;============================================================================= | |
| 605 hwos6 CODE | |
| 606 ;============================================================================= | |
| 607 | |
| 608 ;----------------------------------------------------------------------------- | |
| 609 ; Read CPU Silicon Version | |
| 610 ; | |
| 611 global get_cpu_version | |
| 612 get_cpu_version: | |
| 613 movlw 0xFE ; select address 0x3FFFFE | |
| 614 movwf TBLPTRL ; ... | |
| 615 movlw 0xFF ; ... | |
| 616 movwf TBLPTRH ; ... | |
| 617 movlw 0x3F ; ... | |
| 618 movwf TBLPTRU ; ... | |
| 619 TBLRD*+ ; read DEVID1 byte | |
| 620 movlw b'00011111' ; load mask for silicon version | |
| 621 andwf TABLAT,W ; apply mask and store result in WREG | |
| 622 return ; done | |
| 623 | |
| 624 ;----------------------------------------------------------------------------- | |
| 625 | |
| 626 END |