Mercurial > public > hwos_code
annotate src/hwos.asm @ 656:8af5aefbcdaf default tip
Update to 3.31 beta
| author | heinrichsweikamp |
|---|---|
| date | Thu, 27 Nov 2025 18:32:58 +0100 |
| parents | 75e90cd0c2c3 |
| children |
| rev | line source |
|---|---|
| 0 | 1 ;============================================================================= |
| 2 ; | |
| 634 | 3 ; File hwos.asm * combined next generation V3.09.4e |
| 0 | 4 ; |
| 275 | 5 ; Definition of the hwOS dive computer platform. |
| 0 | 6 ; |
| 654 | 7 ; Copyright (c) 2011, JD Gascuel, heinrichs weikamp gmbh, all right reserved. |
| 0 | 8 ;============================================================================= |
| 9 ; HISTORY | |
| 604 | 10 ; 2011-05-24 : [jDG] Cleanups from initial Matthias code |
| 11 ; 2011-06-24 : [MH] Added clock speeds | |
| 12 | |
| 623 | 13 ;============================================================================= |
| 14 | |
| 634 | 15 #DEFINE INSIDE_HWOS_ASM |
| 604 | 16 |
| 275 | 17 #include "hwos.inc" |
| 623 | 18 #include "eeprom_rs232.inc" |
| 0 | 19 |
| 634 | 20 ;----------------------------- PIC Configuration ----------------------------- |
| 656 | 21 |
| 634 | 22 CONFIG RETEN = OFF ; regulator power while in sleep mode controlled by SRETEN bit |
| 23 CONFIG SOSCSEL = HIGH ; high power SOSC circuit selected | |
| 24 CONFIG XINST = OFF ; extended instruction set disabled | |
| 623 | 25 CONFIG FOSC = INTIO2 ; internal RC oscillator, no clock-out |
| 634 | 26 CONFIG PLLCFG = OFF ; oscillator used directly |
| 27 CONFIG IESO = OFF ; two-speed start-up disabled | |
| 28 CONFIG PWRTEN = OFF ; power-up timer disabled, because incompatible with ICD3 (Ri-400) | |
| 29 CONFIG BOREN = ON ; brown-out reset controlled with SBOREN bit | |
| 30 CONFIG BORV = 2 ; brown-out reset voltage 2.0V | |
| 31 CONFIG BORPWR = MEDIUM ; brown-out monitoring set to medium power level | |
| 32 CONFIG WDTEN = ON ; watchdog timer enabled, controlled by SWDTEN bit | |
| 33 CONFIG WDTPS = 128 ; watchdog timer post-scaler 1:128 | |
| 34 CONFIG RTCOSC = SOSCREF ; RTCC uses SOSC as ref clock | |
| 35 CONFIG MCLRE = ON ; MCLR enabled, RG5 disabled | |
| 36 CONFIG CCP2MX = PORTBE ; ECCP2 muxed with RE7 (micro-controller mode) /RB3 (other modes) | |
| 623 | 37 |
| 38 | |
| 39 ;---------------------------- Bank0 ACCESS RAM ------------------------------- | |
| 634 | 40 ; |
| 623 | 41 ac_ram equ 0x000 |
| 42 ac_ram udata_acs ac_ram ; access RAM data | |
| 43 | |
| 44 | |
| 45 ;---- Flags - Hardware Descriptors | |
| 46 HW_descriptor res 1 ; OSTC - model descriptor (cleared & rebuilt in restart) | |
| 643 | 47 HW_variants res 1 ; OSTC - model variants (NOT cleared in restart) |
| 48 HW_variants2 res 1 ; OSTC - more model variants (NOT cleared in restart) | |
| 656 | 49 HW_variants3 res 1 ; OSTC - more model variants (NOT cleared in restart) |
| 643 | 50 |
| 623 | 51 ;---- Flags - Hardware States |
| 628 | 52 HW_flags_state1 res 1 ; hardware - states 1 |
| 53 HW_flags_state2 res 1 ; hardware - states 2 | |
| 643 | 54 HW_flags_state3 res 1 ; hardware - states 3 |
| 623 | 55 |
| 56 ;--- Flags - Operating System | |
| 57 OS_flags_persist res 1 ; system - persistent settings (NOT cleared in restart) | |
| 58 OS_flags_ISR1 res 1 ; system - ISR control 1 | |
| 59 OS_flags_ISR2 res 1 ; system - ISR control 2 | |
| 60 | |
| 61 ;---- Flags - Operating Modes | |
| 62 OM_flags_mode res 1 ; operating modes | |
| 63 | |
| 64 ;---- Flags - Dive Modes | |
| 65 DM_flags_deco res 1 ; dive mode - main dive & deco mode | |
| 66 | |
| 67 ;---- CPU Speed | |
| 68 cpu_speed_request res 1 ; requested CPU speed: =1: eco, =2: normal, =3: fastest | |
| 69 cpu_speed_state res 1 ; current CPU speed: =1: eco, =2: normal, =3: fastest | |
| 70 | |
| 71 ;---- Timebase & Eventbase | |
| 72 timebase res 1 ; timed trigger flags and running timebase | |
| 73 eventbase res 1 ; event trigger flags | |
| 74 | |
| 75 ;---- Timeout-Timer Service | |
| 76 isr_timeout_timer res 1 ; timeout timer | |
| 77 isr_timeout_reload res 1 ; timeout reload value | |
| 78 | |
| 79 ;---- Dive Times | |
| 80 total_divetime_secs res 2 ; total dive time, seconds | |
| 81 counted_divetime_mins res 2 ; counted dive time, minutes | Attention: do not change the position of | |
| 82 counted_divetime_secs res 1 ; counted dive time, seconds | these 2 Variables relative to each other! | |
| 604 | 83 |
| 623 | 84 ;---- Dive Times / Apnoe |
| 85 apnoe_surface_mins res 1 ; surface time minutes | Attention: do not change the position of | |
| 86 apnoe_surface_secs res 1 ; surface time seconds | these 2 Variables relative to each other! | |
| 87 | |
| 88 apnoe_dive_mins res 1 ; dive time minutes | Attention: do not change the position of | |
| 89 apnoe_dive_secs res 1 ; dive time seconds | these 2 Variables relative to each other! | |
| 90 | |
| 91 ;---- Profile Recording | |
| 92 sampling_rate res 1 ; configured sampling rate | |
| 93 sampling_timer res 1 ; sampling timer | |
| 94 | |
| 95 ;---- Simulator Mode | |
| 96 simulatormode_depth res 1 ; depth in simulator mode | |
| 97 | |
| 98 ;---- HUD / Sensor Data | |
| 99 hud_status_byte res 1 ; HUD status byte, see definition of flags | Attention: keep relative position | |
| 100 hud_battery_mv res 2 ; hud/ppo2 monitor battery voltage in mV | between these two variables! | |
| 101 | |
| 634 | 102 ;---- Battery Management |
| 103 battery_capacity_internal res 2 ; for internal battery gauging | |
| 104 battery_capacity res 2 ; for battery gauge IC | |
| 105 battery_offset res 2 ; for battery gauge IC | |
| 106 battery_type res 1 ; =0:1.5V, =1:3.6V Saft, =2:LiIon 3.7V/0.8Ah, =3:LiIon 3.7V/3.1Ah, =4: LiIon 3.7V/2.3Ah | |
| 107 battery_accumulated_charge res 2 ; raw values in battery gauge IC | |
| 108 battery_temperature res 2 ; battery temperature in 0.1 Kelvin | |
| 656 | 109 |
| 623 | 110 |
| 634 | 111 |
| 112 | |
| 643 | 113 ; 44 byte user data |
| 623 | 114 ; 32 byte tmp data placed by C compiler |
| 115 ; 20 byte variables placed by math library | |
| 116 ; == | |
| 643 | 117 ; 96 byte used, 0 byte free (96 byte total available) |
| 623 | 118 |
| 631 | 119 |
| 623 | 120 global HW_descriptor |
| 121 global HW_variants | |
| 643 | 122 global HW_variants2 |
| 656 | 123 global HW_variants3 |
| 628 | 124 global HW_flags_state1 |
| 125 global HW_flags_state2 | |
| 643 | 126 global HW_flags_state3 |
| 623 | 127 global OS_flags_persist |
| 128 global OS_flags_ISR1 | |
| 129 global OS_flags_ISR2 | |
| 130 global OM_flags_mode | |
| 131 global DM_flags_deco | |
| 132 global cpu_speed_request | |
| 133 global cpu_speed_state | |
| 134 global timebase | |
| 135 global eventbase | |
| 136 global isr_timeout_timer | |
| 137 global isr_timeout_reload | |
| 138 global total_divetime_secs | |
| 139 global counted_divetime_mins | |
| 140 global counted_divetime_secs | |
| 141 global apnoe_surface_secs | |
| 142 global apnoe_surface_mins | |
| 143 global apnoe_dive_secs | |
| 144 global apnoe_dive_mins | |
| 145 global sampling_rate | |
| 146 global sampling_timer | |
| 147 global simulatormode_depth | |
| 148 global hud_status_byte | |
| 149 global hud_battery_mv | |
| 634 | 150 global battery_capacity_internal |
| 151 global battery_capacity | |
| 152 global battery_offset | |
| 153 global battery_type | |
| 154 global battery_accumulated_charge | |
| 155 global battery_temperature | |
| 656 | 156 |
| 634 | 157 |
| 158 | |
| 159 ;============================================================================= | |
| 160 hwos1 CODE | |
| 161 ;============================================================================= | |
| 623 | 162 |
| 163 ;----------------------------------------------------------------------------- | |
| 634 | 164 ; Master Initialization of Hardware Resources |
| 165 ; | |
| 604 | 166 global init_ostc |
| 275 | 167 init_ostc: |
| 623 | 168 |
| 169 ; Oscillator | |
| 170 banksel common ; select bank common | |
| 634 | 171 movlw b'01110010' ; select 16 MHz INTOSC |
| 172 movwf OSCCON ; ... | |
| 173 movlw b'00001000' ; secondary oscillator running | |
| 174 movwf OSCCON2 ; ... | |
| 175 movlw b'00000000' ; 4x PLL disable (Bit 6) - only works with 8 or 16MHz (=32 or 64MHz) | |
| 176 movwf OSCTUNE ; ... | |
| 608 | 177 |
| 623 | 178 movlw coding_speed_normal ; coding for normal CPU speed |
| 179 movwf cpu_speed_request ; store CPU shall run with normal speed | |
| 180 movwf cpu_speed_state ; store CPU does run with normal speed | |
| 608 | 181 |
|
642
a9a0188091e4
fix rare upgrade issue with OSTC sport 2019 hardware
heinrichsweikamp
parents:
640
diff
changeset
|
182 ;bcf RCON,SBOREN ; brown-out off (not needed here, is handled in bootloader) |
| 604 | 183 bcf RCON,IPEN ; priority interrupts off |
| 608 | 184 |
| 604 | 185 banksel WDTCON |
| 645 | 186 movlw b'00010000' ; setup watchdog, put VCORE Reg into Ultra Low-Power mode in Sleep |
| 634 | 187 movwf WDTCON ; ... |
| 0 | 188 |
| 608 | 189 |
| 0 | 190 ; I/O Ports |
| 634 | 191 banksel 0xF16 ; addresses F16h ... F5Fh are not part of the access RAM |
| 192 | |
| 604 | 193 clrf REFOCON ; no reference oscillator active on REFO pin |
| 194 clrf ODCON1 ; disable open drain capability | |
| 195 clrf ODCON2 ; disable open drain capability | |
| 196 clrf ODCON3 ; disable open drain capability | |
| 634 | 197 clrf CM1CON ; disable comparator 1 |
| 198 clrf CM2CON ; disable comparator 2 | |
| 199 clrf CM3CON ; disable comparator 3 | |
| 0 | 200 |
| 634 | 201 movlw b'11000000' ; ANSEL0: AN7, AN6 -> analog inputs, PORTA is digital |
| 202 movwf ANCON0 ; ... | |
| 203 movlw b'00000111' ; ANSEL1: AN8, AN9, AN10 -> analog input | |
| 204 movwf ANCON1 ; ... | |
| 640 | 205 clrf ANCON2 |
| 634 | 206 |
| 207 banksel common ; back to bank common | |
| 0 | 208 |
| 604 | 209 ; movlw b'00000000' ; 1= input -> Data TFT_high |
| 634 | 210 clrf TRISA ; ... |
| 604 | 211 ; movlw b'00000000' ; init port |
| 634 | 212 clrf PORTA ; ... |
| 0 | 213 |
| 604 | 214 movlw b'00000011' ; 1= input, (RB0, RB1) -> switches, RB2 -> Power_MCP, RB3 -> s8_npower, RB4 -> LED_green/rx_nreset, RB5 -> /TFT_POWER |
| 634 | 215 movwf TRISB ; ... |
| 604 | 216 movlw b'00111000' ; init port, rx_nreset=1 -> hard reset RX |
| 634 | 217 movwf PORTB ; ... |
| 0 | 218 |
| 604 | 219 movlw b'10011010' ; 1= input, (RC0, RC1) -> SOSC, RC2 -> TFT_LED_PWM, (RC3,RC4) -> I²C, RC5 -> MOSI_MS5541, (RC6, RC7) -> UART1 |
| 634 | 220 movwf TRISC ; ... |
| 604 | 221 ; movlw b'00000000' ; init port |
| 634 | 222 clrf PORTC ; ... |
| 0 | 223 |
| 604 | 224 movlw b'00100000' ; 1= input, RD0 -> TFT_NCS, RD1 -> TFT_RS, RD2 -> TFT_NWR, RD3 -> TFT_RD, RD4 -> MOSI_Flash, RD5 -> MISO_Flash, RD6 -> CLK_Flash, RD7 -> TFT_NRESET |
| 634 | 225 movwf TRISD ; ... |
| 604 | 226 ; movlw b'00000000' ; init port |
| 634 | 227 clrf PORTD ; ... |
| 0 | 228 |
| 628 | 229 movlw b'00100000' ; 1= input, RE0 -> not_Power_BLE, RE1 -> Power_IR, RE2 -> CS_MCP, RE3 -> LED_blue, RE4 -> power_sw1, RE5 -> leave as input |
| 634 | 230 movwf TRISE ; ... |
| 627 | 231 movlw b'00010001' ; init port |
| 634 | 232 movwf PORTE ; ... |
| 0 | 233 |
| 604 | 234 movlw b'01111110' ; 1= input, (RF1, RF2, RF3, RF4, RF5) -> Analog |
| 634 | 235 movwf TRISF ; ... |
| 604 | 236 ; movlw b'00000000' ; init port |
| 634 | 237 clrf PORTF ; ... |
| 0 | 238 |
| 640 | 239 movlw b'00000110' ; 1= input, <7:6> not implemented, RG0 -> TX3_PIEZO_CFG, , RG1 -> TX2, RG2 -> RX2, RG3 -> AN17_RSSI, RG4 -> SOSC_OUT, RG5 -> /RESET |
| 634 | 240 movwf TRISG ; ... |
| 604 | 241 movlw b'00000001' ; init port |
| 634 | 242 movwf PORTG ; ... |
| 0 | 243 |
| 604 | 244 ; movlw b'00000000' ; 1= input -> Data TFT_low |
| 634 | 245 clrf TRISH ; ... |
| 604 | 246 ; movlw b'00000000' ; init port |
| 634 | 247 clrf PORTH ; ... |
| 0 | 248 |
| 623 | 249 movlw b'10011011' ; 1= input, RJ4 -> vusb_in, RJ5 -> power_sw2, RJ6 -> CLK_MS5541, RJ7 -> MISO_MS5541 |
| 634 | 250 movwf TRISJ ; ... |
| 604 | 251 movlw b'00100000' ; init port |
| 634 | 252 movwf PORTJ ; ... |
| 0 | 253 |
| 623 | 254 |
| 618 | 255 ; disable Charger by default |
| 623 | 256 bsf charge_disable ; set charging-inhibit signal |
| 257 bcf charge_enable ; activate charging-inhibit signal | |
| 258 | |
| 259 | |
| 634 | 260 ; Timer 7 for 62.5 ms Interrupt (Sensor States) |
| 261 banksel 0xF16 ; addresses F16h...F5Fh are not part of the access RAM | |
| 262 clrf T7GCON ; clear timer 7 gate control register | |
| 263 movlw b'10001101' ; bit 7-6: 10 = clock source SOSC/SCLKI (with bit 3 = 1) | |
| 264 ; bit 5-4: 00 = 1:1 prescaler | |
| 265 ; bit 3: 1 = clock source SOSC/SCLKI (with bit 7-6 = 10) | |
| 266 ; bit 2: 1 = DO NOT synchronize external clock input (else OSTC won't wake up from sleep!) | |
| 267 ; bit 1: 0 = 2x 8 bit operation | |
| 268 ; bit 0: 1 = timer enabled | |
| 269 ; 32768 Hz clock source, 1:1 prescaler -> timer counts at 30.51757813 µs/bit | |
| 270 movwf T7CON ; ... | |
| 271 movlw .248 ; load timer 7, high byte (8x256 ticks -> 62.5 ms) | |
| 272 movwf TMR7H ; ... | |
| 273 clrf TMR7L ; load timer 7, low byte | |
| 0 | 274 |
| 623 | 275 |
| 634 | 276 ; Timer 0 - not used |
| 277 movlw b'00000001' ; timer0 stopped (1:4 prescaler) | |
| 278 movwf T0CON ; ... | |
| 279 | |
| 280 | |
| 281 ; Timer 1 - Button hold-down Timer | |
| 282 ; movlw b'10001100' ; old setting | |
| 283 movlw b'10001010' ; bit 7-6: 10 = clock source SOSC/SCLKI (with bit 3 = 1) | |
| 284 ; bit 5-4: 00 = 1:1 prescaler | |
| 285 ; bit 3: 1 = clock source SOSC/SCLKI (with bit 7-6 = 10) | |
| 286 ; bit 2: 0 = synchronize external clock input | |
| 287 ; bit 1: 1 = 16 bit operation | |
| 288 ; bit 0: 0 = timer stopped | |
| 289 ; 32768 Hz clock source, 1:1 prescaler -> timer counts at 30.51757813 µs/bit | |
| 290 movwf T1CON ; ... | |
| 0 | 291 |
| 623 | 292 |
| 0 | 293 ; RTCC |
| 623 | 294 banksel 0xF16 ; addresses, F16h through F5Fh, are also used by SFRs, but are not part of the access RAM |
| 634 | 295 movlw 0x55 ; unlock sequence for RTCWREN |
| 296 movwf EECON2 ; ... | |
| 297 movlw 0xAA ; ... | |
| 298 movwf EECON2 ; ... | |
| 299 bsf RTCCFG,RTCWREN ; unlock access to RTC | |
| 300 bsf RTCCFG,RTCPTR1 ; set pointer register to b'11' | |
| 301 bsf RTCCFG,RTCPTR0 ; .. | |
| 623 | 302 bsf RTCCFG,RTCEN ; module enable |
| 303 bsf RTCCFG,RTCOE ; output enable | |
| 304 movlw b'00000100' ; 32768 Hz SOCS on RTCC pin (PORTG,4) Bit7-5: pull-ups for Port D, E and J | |
| 634 | 305 movwf PADCFG1 ; ... |
| 306 movlw b'11000000' ; 1/2 second alarm | |
| 307 movwf ALRMCFG ; ... | |
| 308 movlw d'1' ; select alarm repeat counter to 1 | |
| 309 movwf ALRMRPT ; ... | |
| 310 movlw 0x55 ; unlock sequence for RTCWREN | |
| 311 movwf EECON2 ; ... | |
| 312 movlw 0xAA ; ... | |
| 313 movwf EECON2 ; ... | |
| 314 bcf RTCCFG,RTCWREN ; lock access to RTC | |
| 315 banksel common ; back to bank common | |
| 623 | 316 |
| 614 | 317 |
| 0 | 318 ; A/D Converter |
| 319 movlw b'00011000' ; power off ADC, select AN6 | |
| 634 | 320 movwf ADCON0 ; ... |
| 0 | 321 movlw b'00100000' ; 2.048V Vref+ |
| 634 | 322 movwf ADCON1 ; ... |
| 640 | 323 movlw b'10001111' ; right aligned, 2 x T_AD acquisition time, clock derived from A/D RC oscillator (To be CPU-clock independent) |
| 634 | 324 movwf ADCON2 ; ... |
| 0 | 325 |
| 623 | 326 |
| 634 | 327 ; Serial Port 1 (TRISC6/7) |
| 631 | 328 movlw b'00001000' ; switch baud generator to 16 bit mode (BRG16=1) |
| 329 movwf BAUDCON1 ; ... | |
| 330 ; SPBRGH:SPBRG = .34 : 114285 BAUD @ 16MHz (+0.79% error at 115200 baud) | |
| 331 ; SPBRGH:SPBRG = .207 : 19230 BAUD @ 16MHz (-0.16% error at 19200 baud) | |
| 332 movlw .34 ; select 114285 baud (low byte) | |
| 333 movwf SPBRG1 ; ... | |
| 334 clrf SPBRGH1 ; ... (high byte) | |
| 204 | 335 |
| 631 | 336 clrf RCSTA1 ; disable UART RX |
| 337 clrf TXSTA1 ; disable UART TX | |
| 338 bcf PORTC,6 ; tie TX output hard to GND | |
| 0 | 339 |
| 623 | 340 |
| 634 | 341 ; Serial Port 2 (TRISG2) for IR/S8 digital Interface |
| 623 | 342 ; |
| 343 ; - will be initialized by enable_ir_s8 (eeprom_rs232.asm) in case IR/S8 shall be available | |
| 344 | |
| 0 | 345 |
| 623 | 346 ; Timer 3 for IR-RX Timeout |
| 656 | 347 IFDEF _external_sensor_eccr |
| 634 | 348 clrf T3GCON ; clear Timer3 gate control register |
| 349 ; movlw b'10001101' ; old value | |
| 350 movlw b'10001011' ; bit 7-6: 10 = clock source SOSC/SCLKI (with bit 3 = 1) | |
| 351 ; bit 5-4: 00 = 1:1 prescaler | |
| 352 ; bit 3: 1 = clock source SOSC/SCLKI (with bit 7-6 = 10) | |
| 353 ; bit 2: 0 = synchronize external clock input | |
| 354 ; bit 1: 1 = 16 bit operation | |
| 355 ; bit 0: 1 = timer enabled | |
| 356 ; 32768 Hz clock source, 1:1 prescaler -> timer counts at 30.51757813 µs/bit | |
| 357 movwf T3CON ; ... | |
| 623 | 358 ENDIF |
| 359 | |
| 0 | 360 |
| 361 ; SPI Module(s) | |
| 362 ; SPI2: External Flash | |
| 634 | 363 movlw b'00110000' ; set up SPI module |
| 364 movwf SSP2CON1 ; ... | |
| 365 clrf SSP2STAT ; ... | |
| 366 ; resulting bit clocks: 0.25 MHz @ 1 MHz CPU clock (Eco) | |
| 367 ; 4.00 MHz @ 16 MHz CPU clock (Normal) | |
| 368 ; 16.00 MHz @ 64 MHz CPU clock (Fastest) | |
| 623 | 369 |
| 0 | 370 |
| 371 ; MSSP1 Module: I2C Master | |
| 656 | 372 movlw b'00000000' ; enable slew rate control |
| 373 movwf SSP1STAT ; ... | |
| 634 | 374 movlw b'00101000' ; set up I2C to master mode |
| 375 movwf SSP1CON1 ; ... | |
| 376 clrf SSP1CON2 ; ... | |
| 643 | 377 movlw i2c_speed_value |
| 634 | 378 movwf SSP1ADD ; ... |
| 0 | 379 |
| 623 | 380 |
| 0 | 381 ; PWM Module(s) |
| 623 | 382 ; PWM 1 for LED dimming |
| 634 | 383 movlw b'00001100' ; set up PWM module |
| 384 movwf CCP1CON ; ... | |
| 385 movlw b'00000001' ; pulse steering disabled | |
| 386 movwf PSTR1CON ; ... | |
| 387 movlw d'254' ; select period | |
| 388 movwf PR2 ; ... | |
| 604 | 389 ; 255 is max brightness (300 mW) |
| 634 | 390 clrf CCPR1L ; duty cycle, low byte |
| 391 clrf CCPR1H ; duty cycle, high byte | |
| 392 movlw T2CON_NORMAL ; set timer for normal dimming | |
| 393 movwf T2CON ; ... | |
| 623 | 394 |
| 0 | 395 |
| 634 | 396 ; Timer 5 for ISR-independent Wait/Timeout |
| 397 clrf T5GCON ; clear Timer5 gate control register | |
| 398 ; movlw b'10001111' ; old value | |
| 399 movlw b'10001011' ; bit 7-6: 10 = clock source SOSC/SCLKI (with bit 3 = 1) | |
| 400 ; bit 5-4: 00 = 1:1 prescaler | |
| 401 ; bit 3: 1 = clock source SOSC/SCLKI (with bit 7-6 = 10) | |
| 402 ; bit 2: 0 = synchronize external clock input | |
| 403 ; bit 1: 1 = 16 bit operation | |
| 404 ; bit 0: 1 = timer enabled | |
| 405 ; 32768 Hz clock source, 1:1 prescaler -> timer counts at 30.51757813 µs/bit | |
| 406 movwf T5CON ; ... | |
| 0 | 407 |
| 640 | 408 ; Timer 4 for debounce of new digital piezo circuity |
| 409 movlw b'01111011' ; 1:8 Postscale, Prescale = 1, Timer 4 OFF | |
| 410 movwf T4CON | |
| 411 setf PR4 | |
| 412 | |
| 634 | 413 ; turn off unused Timers |
| 640 | 414 banksel 0xF16 ; addresses F16h...F5Fh are not part of the access RAM |
| 634 | 415 movlw b'11000000' ; disable ECCP3 and ECCP2 |
| 416 movwf PMD0 ; ... | |
| 656 | 417 IFDEF _external_sensor_eccr |
| 640 | 418 movlw b'11000001' ; disable PSP, CTMU and EMB |
| 623 | 419 ELSE |
| 640 | 420 movlw b'11001001' ; disable PSP, CTMU, Timer 3 and EMB |
| 623 | 421 ENDIF |
| 634 | 422 movwf PMD1 ; ... |
| 423 movlw b'11010111' ; disable timer 10, timer 8, timer 6 and comparators 1-3 | |
| 424 movwf PMD2 ; ... | |
| 425 movlw b'11111111' ; disable CCP 4-10 and timer 12 | |
| 426 movwf PMD3 ; ... | |
| 608 | 427 |
| 623 | 428 |
| 429 ; turn off unused CTMU | |
| 634 | 430 ;banksel 0xF16 ; addresses F16h...F5Fh are not part of the access RAM |
| 431 clrf CTMUCONH ; disable CTMU | |
| 432 clrf CTMUCONL ; ... | |
| 433 clrf CTMUICON ; ... | |
| 434 | |
| 623 | 435 |
| 604 | 436 banksel common |
| 608 | 437 |
| 623 | 438 |
| 0 | 439 ; Interrupts |
| 634 | 440 bcf PIR5,TMR7IF ; if applicable clear timer 7 IRQ flag |
| 0 | 441 |
| 634 | 442 movlw b'11010000' ; enable global IRQ, peripheral IRQ and external IRQ 0 |
| 443 movwf INTCON ; ... | |
| 444 movlw b'00001000' ; external IRQ 0 on falling edge, pull-up of PORTB by TRIS register | |
| 445 movwf INTCON2 ; ... | |
| 446 movlw b'00000000' ; disable external IRQs 1,2,3 | |
| 447 movwf INTCON3 ; ... | |
| 448 movlw b'00000001' ; enable timer 1 IRQ | |
| 449 movwf PIE1 ; ... | |
| 450 movlw b'00000010' ; enable timer 3 IRQ | |
| 451 movwf PIE2 ; ... | |
| 452 movlw b'00000001' ; enable RTCC IRQ | |
| 453 movwf PIE3 ; ... | |
| 640 | 454 movlw b'00001001' ; enable timer 7 and timer 4 IRQ |
| 634 | 455 movwf PIE5 ; ... |
| 456 | |
| 457 ; Release RESET from RX Circuitry | |
| 458 bcf active_reset_ostc_rx | |
| 459 | |
| 460 ; Power-up the Switches | |
| 623 | 461 bsf power_sw1 ; switch on power supply for switch 1 |
| 650 | 462 nop |
| 623 | 463 bsf power_sw2 ; switch on power supply for switch 2 |
| 634 | 464 return ; done |
| 465 | |
| 0 | 466 |
| 467 ;============================================================================= | |
| 634 | 468 hwos2 CODE |
| 469 ;============================================================================= | |
| 623 | 470 |
| 634 | 471 ;----------------------------------------------------------------------------- |
| 472 ; CPU Speed Change Requests | |
| 473 ; | |
| 623 | 474 global request_speed_eco |
| 475 request_speed_eco: | |
| 476 movlw coding_speed_eco ; load coding for eco speed | |
| 477 movwf cpu_speed_request ; request ISR to change the CPU speed | |
| 478 return ; done | |
| 479 | |
| 480 global request_speed_normal | |
| 481 request_speed_normal: | |
| 482 movlw coding_speed_normal ; load coding for normal speed | |
| 483 movwf cpu_speed_request ; request ISR to change the CPU speed | |
| 484 return ; done | |
| 485 | |
| 486 global request_speed_fastest | |
| 487 request_speed_fastest: | |
| 488 movlw coding_speed_fastest ; load coding for fastest speed | |
| 489 movwf cpu_speed_request ; request ISR to change the CPU speed | |
| 490 return ; done | |
| 491 | |
| 634 | 492 |
| 0 | 493 ;============================================================================= |
| 634 | 494 hwos3 CODE |
| 495 ;============================================================================= | |
| 496 | |
| 497 ;----------------------------------------------------------------------------- | |
| 498 ; Backup the first 128 bytes from program FLASH to EEPROM | |
| 623 | 499 ; |
| 500 global backup_flash_page | |
| 501 backup_flash_page: | |
| 502 banksel common | |
| 631 | 503 |
| 634 | 504 ; set start address in internal program FLASH |
| 631 | 505 movlw 0x00 ; set 0x000000 |
| 506 movwf TBLPTRL ; ... | |
| 507 movwf TBLPTRH ; ... | |
| 508 movwf TBLPTRU ; ... | |
| 509 TBLRD*- ; dummy read to be in 128 byte block | |
| 510 | |
| 511 ; set start address in EEPROM | |
| 512 EEPROM_SET_ADDRESS eeprom_prog_page0_backup | |
| 623 | 513 |
| 514 movlw .128 ; copy 1 block = 128 byte | |
| 631 | 515 movwf eeprom_loop ; initialize loop counter |
| 623 | 516 backup_flash_loop: |
| 634 | 517 tblrd+* ; read one byte from program FLASH (with pre-increment) |
| 518 movff TABLAT,EEDATA ; transfer byte from program FLASH read to EEPROM write | |
| 631 | 519 call write_eeprom ; execute EEPROM write |
| 623 | 520 incf EEADR,F ; increment EEPROM address |
| 631 | 521 decfsz eeprom_loop,F ; all 128 byte done? |
| 623 | 522 bra backup_flash_loop ; NO - loop |
| 631 | 523 return ; YES - done |
| 623 | 524 |
| 634 | 525 |
| 0 | 526 ;============================================================================= |
| 634 | 527 hwos4 CODE |
| 528 ;============================================================================= | |
| 529 | |
| 530 ;----------------------------------------------------------------------------- | |
| 531 ; Restore the first 128 bytes from EEPROM to program FLASH | |
| 623 | 532 ; |
| 533 global restore_flash | |
| 534 restore_flash: | |
| 535 banksel common | |
| 654 | 536 bcf INTCON,GIE |
| 631 | 537 |
| 634 | 538 ;set start address in internal program FLASH |
| 631 | 539 movlw 0x00 ; set 0x000000 |
| 540 movwf TBLPTRL ; ... | |
| 541 movwf TBLPTRH ; ... | |
| 542 movwf TBLPTRU ; ... | |
| 623 | 543 |
| 544 movlw b'10010100' ; setup block erase | |
| 545 rcall restore_write ; execute block erase | |
| 546 | |
| 656 | 547 TBLRD*- ; dummy read to be in 128 byte block |
| 548 | |
| 631 | 549 ; set start address in EEPROM |
| 550 EEPROM_SET_ADDRESS eeprom_prog_page0_backup | |
| 623 | 551 |
| 631 | 552 movlw .128 ; copy 1 block = 128 byte |
| 553 movwf eeprom_loop ; initialize loop counter | |
| 623 | 554 restore_flash_loop: |
| 631 | 555 call read_eeprom ; execute EEPROM read |
| 623 | 556 incf EEADR,F ; increment EEPROM address |
| 634 | 557 movff EEDATA,TABLAT ; transfer byte from EEPROM read to program FLASH write |
| 558 tblwt+* ; execute program FLASH write (with pre-increment) | |
| 631 | 559 decfsz eeprom_loop,F ; all 128 bytes done? |
| 560 bra restore_flash_loop ; NO - loop | |
| 623 | 561 movlw b'10000100' ; YES - setup block write |
| 562 rcall restore_write ; - execute block write | |
| 563 reset ; - done, reset CPU | |
| 564 | |
| 565 restore_write: | |
| 631 | 566 movwf EECON1 ; configure operation |
| 567 movlw 0x55 ; unlock sequence | |
| 568 movwf EECON2 ; ... | |
| 569 movlw 0xAA ; ... | |
| 570 movwf EECON2 ; ... | |
| 571 bsf EECON1,WR ; execute operation | |
| 572 nop ; wait for operation to complete | |
| 573 nop ; ... | |
| 574 return ; done | |
| 575 | |
| 634 | 576 |
| 631 | 577 ;============================================================================= |
| 634 | 578 hwos5 CODE |
| 579 ;============================================================================= | |
| 580 | |
| 581 ;----------------------------------------------------------------------------- | |
| 582 ; Memory clear and move Functions, to be used via Macros | |
| 631 | 583 ; |
| 584 global memory_clear | |
| 585 memory_clear: | |
| 586 clrf POSTINC1 ; clear address | |
| 587 decfsz WREG ; decrement loop counter, became zero? | |
| 588 bra memory_clear ; NO - loop | |
| 589 return ; YES - done | |
| 590 | |
| 591 global memory_move | |
| 592 memory_move: | |
| 593 movff POSTINC1,POSTINC2 ; copy from-to | |
| 594 decfsz WREG ; decrement loop counter, became zero? | |
| 595 bra memory_move ; NO - loop | |
| 596 return ; YES - done | |
| 0 | 597 |
| 634 | 598 |
| 599 ;============================================================================= | |
| 600 hwos6 CODE | |
| 601 ;============================================================================= | |
| 602 | |
| 603 ;----------------------------------------------------------------------------- | |
| 604 ; Read CPU Silicon Version | |
| 605 ; | |
| 606 global get_cpu_version | |
| 607 get_cpu_version: | |
| 608 movlw 0xFE ; select address 0x3FFFFE | |
| 609 movwf TBLPTRL ; ... | |
| 610 movlw 0xFF ; ... | |
| 611 movwf TBLPTRH ; ... | |
| 612 movlw 0x3F ; ... | |
| 613 movwf TBLPTRU ; ... | |
| 648 | 614 TBLRD*+ ; read DEVID1 byte |
| 615 btfss TABLAT,6 | |
| 616 bsf less_io_cpu ; Less I/O CPU found | |
| 634 | 617 movlw b'00011111' ; load mask for silicon version |
| 618 andwf TABLAT,W ; apply mask and store result in WREG | |
| 619 return ; done | |
| 620 | |
| 621 ;----------------------------------------------------------------------------- | |
| 622 | |
| 623 END |