annotate src/eeprom_rs232.asm @ 651:682c514c53c0

3.21 release preparations
author heinrichsweikamp
date Fri, 14 Apr 2023 09:00:19 +0200
parents bc214815deb2
children 75e90cd0c2c3
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1 ;=============================================================================
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2 ;
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3 ; File eeprom_rs232.asm * combined next generation V3.09.4n
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4 ;
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5 ; Internal EEPROM, RS232
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6 ;
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7 ; Copyright (c) 2011, JD Gascuel, HeinrichsWeikamp, all right reserved.
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8 ;=============================================================================
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9 ; HISTORY
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10 ; 2011-08-06 : [mH] moving from OSTC code
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11
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12 #include "hwos.inc"
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13 #include "wait.inc"
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14 #include "shared_definitions.h"
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15 #include "rtc.inc"
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16 #include "external_flash.inc"
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17
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18 #DEFINE INSIDE_EEPROM_RS232
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19 #include "eeprom_rs232.inc"
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20
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21
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22 extern lt2942_charge_done
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23
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24
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25 ;=============================================================================
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26 eeprom CODE
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27 ;=============================================================================
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28
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29 ;-----------------------------------------------------------------------------
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30 ;
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31 ; EEPROM Functions - for EEPROM Macros and Memory Map, see eeprom_rs232.inc
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32 ;
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33 ;-----------------------------------------------------------------------------
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34
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35
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36 ;-----------------------------------------------------------------------------
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37 ; Read from internal EEPROM
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38 ;
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39 ; Input: EEADRH:EEADR = EEPROM address
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40 ; Output: EEDATA
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41 ; Trashed: NONE
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42 ;
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43 global read_eeprom
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44 read_eeprom:
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45 bcf EECON1,EEPGD ; access data EEPROM
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46 bcf EECON1,CFGS ; ...
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47 bsf EECON1,RD ; initiate reading
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48 return ; done
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49
0
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50
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51 ;-----------------------------------------------------------------------------
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52 ; Write into internal EEPROM
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53 ;
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54 ; Input: EEADRH:EEADR = EEPROM address
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55 ; EEDATA = byte to write
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56 ; Trashed: WREG
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57 ;
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58 global write_eeprom
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59 write_eeprom:
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60 bcf EECON1,EEPGD ; access data EEPROM
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61 bcf EECON1,CFGS ; ...
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62 bsf EECON1,WREN ; enable writing
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63 bcf INTCON,GIE ; disable interrupts
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64 movlw 0x55 ; unlock sequence
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65 movwf EECON2 ; ...
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66 movlw 0xAA ; ...
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67 movwf EECON2 ; ...
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68 bsf EECON1,WR ; start write operation
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69 write_eeprom_loop:
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70 btfsc EECON1,WR ; write completed?
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71 bra write_eeprom_loop ; NO - loop waiting
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72 btfsc EECON1,WRERR ; All ok?
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73 rcall write_eeprom_error ; NO, something failed.
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74 bcf EECON1,WREN ; YES - disable writing
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75 bsf INTCON,GIE ; - re-enable interrupts
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76 return ; - done
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77 write_eeprom_error:
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78 bsf eeprom_write_error_flag ; Set error flag
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79 ; Try again (once)
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80 movlw 0x55 ; unlock sequence
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81 movwf EECON2 ; ...
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82 movlw 0xAA ; ...
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83 movwf EECON2 ; ...
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84 bsf EECON1,WR ; start write operation
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85 write_eeprom_loop2:
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86 btfsc EECON1,WR ; write completed?
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87 bra write_eeprom_loop2 ; NO - loop waiting
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88 return
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89
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91 ;-----------------------------------------------------------------------------
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92 ; EEPROM read and write Functions to be used via Macros
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93 ;
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94 global eeprom_read_common
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95 eeprom_read_common:
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96 movwf eeprom_loop ; initialize loop counter
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97 eeprom_read_common_loop:
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98 rcall read_eeprom ; execute read
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99 movff EEDATA,POSTINC1 ; copy byte from EEPROM data register to memory
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100 incf EEADR,F ; advance to next EEPROM cell
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101 decfsz eeprom_loop,F ; decrement loop counter, all done?
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102 bra eeprom_read_common_loop ; NO - loop
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103 return ; YES - done
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104
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105 global eeprom_write_common
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106 eeprom_write_common:
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107 movwf eeprom_loop ; initialize loop counter
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108 eeprom_write_common_loop:
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109 movff POSTINC1,EEDATA ; copy byte from memory to EEPROM data register
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110 rcall write_eeprom ; execute write
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111 incf EEADR,F ; advance to next EEPROM cell
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112 decfsz eeprom_loop,F ; decrement loop counter, all done?
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113 bra eeprom_write_common_loop ; NO - loop
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114 return ; YES - done
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115
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116
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117 ;-----------------------------------------------------------------------------
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118 ; Read OSTC Serial Number
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119 ;
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120 global eeprom_serial_number_read
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121 eeprom_serial_number_read:
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122 EEPROM_II_READ eeprom_ostc_serial,mpr ; read serial number
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123 return ; done
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124
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125
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126 ;-----------------------------------------------------------------------------
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127 ; Read and Write Dive Number Offset
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128 ;
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129 global eeprom_log_offset_read
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130 eeprom_log_offset_read:
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131 EEPROM_II_READ eeprom_log_offset,mpr ; read log offset
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132 return ; done
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133
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134 global eeprom_log_offset_write
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135 eeprom_log_offset_write:
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136 EEPROM_II_WRITE mpr,eeprom_log_offset ; write log-offset
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137 return ; done
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138
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139
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140 ;-----------------------------------------------------------------------------
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141 ; Read and Write total Number of Dives
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142 ;
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143 global eeprom_total_dives_read
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144 eeprom_total_dives_read:
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145 EEPROM_II_READ eeprom_num_dives,mpr ; read total dives
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146 return ; done
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147
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148 global eeprom_total_dives_write
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149 eeprom_total_dives_write:
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150 EEPROM_II_WRITE mpr,eeprom_num_dives ; write total dives
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151 return ; done
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152
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153
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154 ;-----------------------------------------------------------------------------
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155 ; Read and Write the Battery Type and Gauge Reading
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156 ;
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157 global eeprom_battery_gauge_read
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158 eeprom_battery_gauge_read:
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159 ; retrieve battery gauge from EEPROM 0x07-0x0C
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160 bsf block_battery_gauge ; suspend ISR from accessing the battery gauge
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161 EEPROM_CC_READ eeprom_battery_type, battery_type ; 1 byte read from EEPROM
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162 EEPROM_RR_READ eeprom_battery_gauge,battery_gauge,.6 ; 6 byte read from EEPROM
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163 bcf block_battery_gauge ; allow ISR to access the battery gauge again
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164 return ; done
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165
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166 global eeprom_battery_gauge_write
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167 eeprom_battery_gauge_write:
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168 bsf block_battery_gauge ; suspend ISR from accessing the battery gauge
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169 EEPROM_CC_WRITE battery_type, eeprom_battery_type ; 1 byte write to EEPROM
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170 update_battery_gauge:
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171 EEPROM_RR_WRITE battery_gauge,eeprom_battery_gauge,.6 ; 6 byte write to EEPROM
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172 bcf block_battery_gauge ; allow ISR to access the battery gauge again
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173 return ; done
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174
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175
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176 ;-----------------------------------------------------------------------------
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177 ; Memorize the Checksum of the Firmware in the update Storage
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178 ;
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179 global eeprom_memorize_fw_checksum
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180 eeprom_memorize_fw_checksum:
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diff changeset
181 EXT_FLASH_ADDR 0x3E000D ; address firmware ID at 0x3E000D
4050675965ea 3.10 stable release
heinrichsweikamp
parents: 631
diff changeset
182 FLASH_CW_READ_0x40 ; read firmware ID to WREG
4050675965ea 3.10 stable release
heinrichsweikamp
parents: 631
diff changeset
183 movff WREG,buffer+.5 ; append firmware ID to checksum
4050675965ea 3.10 stable release
heinrichsweikamp
parents: 631
diff changeset
184 EEPROM_RR_WRITE buffer,eeprom_fw_chksum_current,.6 ; do a 6 byte write to EEPROM
4050675965ea 3.10 stable release
heinrichsweikamp
parents: 631
diff changeset
185 return ; done
4050675965ea 3.10 stable release
heinrichsweikamp
parents: 631
diff changeset
186
4050675965ea 3.10 stable release
heinrichsweikamp
parents: 631
diff changeset
187
4050675965ea 3.10 stable release
heinrichsweikamp
parents: 631
diff changeset
188 ;-----------------------------------------------------------------------------
4050675965ea 3.10 stable release
heinrichsweikamp
parents: 631
diff changeset
189 ; Read and Write the Deco Status
631
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
190 ;
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
191 global eeprom_deco_data_read
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
192 eeprom_deco_data_read:
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
193
634
4050675965ea 3.10 stable release
heinrichsweikamp
parents: 631
diff changeset
194 btfsc RCON,POR ; was there a power outage?
631
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
195 bra eeprom_deco_data_read_1 ; NO - RTC is up-to-date
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
196
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
197 EEPROM_RR_READ eeprom_deco_data_timestamp,rtc_latched_year,.6 ; 6 byte read from EEPROM
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
198 call rtc_set_rtc ; recover RTC to last known time & date
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
199
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
200 eeprom_deco_data_read_1:
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
201
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
202 ; restore surface interval
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
203 EEPROM_II_READ eeprom_deco_data_surfinterval,mpr ; 2 byte read from EEPROM
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
204 SMOVII mpr,surface_interval_mins ; ISR-safe copy of surface interval
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
205
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
206 ; bank 3: restore desaturation status
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
207 EEPROM_RR_READ eeprom_deco_data_bank3,0x300,.9 ; 9 byte read from EEPROM
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
208
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
209 ; bank 5: restore CNS
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
210 EEPROM_RR_READ eeprom_deco_data_bank5,0x500,.4 ; 4 byte read from EEPROM
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
211
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
212 ; bank 7: restore tissue pressures
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
213 EEPROM_RR_READ eeprom_deco_data_bank7,0x700,.128 ; 128 byte read from EEPROM
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
214
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
215 return ; done
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
216
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
217
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
218 global eeprom_deco_data_write
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
219 eeprom_deco_data_write:
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
220
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
221 ; invalidate current data in vault
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
222 movlw DECO_DATA_INVALID_TOKEN ; deco data invalid token
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
223 EEPROM_CC_WRITE WREG,eeprom_deco_data_validity ; 1 byte write to EEPROM
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
224
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
225 ; store vault version
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
226 movlw eeprom_vault_version ; deco data format version
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
227 EEPROM_CC_WRITE WREG,eeprom_deco_data_version ; 1 byte write to EEPROM
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
228
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
229 ; store date/time
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
230 SMOVSS rtc_year,rtc_latched_year ; ISR-safe 6 byte copy of date and time
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
231 EEPROM_RR_WRITE rtc_latched_year,eeprom_deco_data_timestamp,.6 ; 6 byte write to EEPROM
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
232
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
233 ; store surface interval
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
234 SMOVII surface_interval_mins,mpr ; ISR-safe copy of surface interval
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
235 EEPROM_II_WRITE mpr,eeprom_deco_data_surfinterval ; 2 byte write to EEPROM
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
236
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
237 ; bank 3: store desaturation status
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
238 EEPROM_RR_WRITE 0x300,eeprom_deco_data_bank3,.9 ; 9 byte write to EEPROM
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
239
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
240 ; bank 5: store CNS
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
241 EEPROM_RR_WRITE 0x500,eeprom_deco_data_bank5,.4 ; 4 byte write to EEPROM
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
242
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
243 ; bank 7: store tissue pressures
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
244 EEPROM_RR_WRITE 0x700,eeprom_deco_data_bank7,.128 ; 128 byte write to EEPROM
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
245
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
246 ; indicate new valid data in vault
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
247 movlw DECO_DATA_VALID_TOKEN ; deco data valid token
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
248 EEPROM_CC_WRITE WREG,eeprom_deco_data_validity ; 1 byte write to EEPROM
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
249
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
250 return ; done
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
251
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
252
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
253 ;=============================================================================
634
4050675965ea 3.10 stable release
heinrichsweikamp
parents: 631
diff changeset
254 rs232 CODE
623
c40025d8e750 3.03 beta released
heinrichsweikamp
parents: 604
diff changeset
255 ;=============================================================================
c40025d8e750 3.03 beta released
heinrichsweikamp
parents: 604
diff changeset
256
634
4050675965ea 3.10 stable release
heinrichsweikamp
parents: 631
diff changeset
257 ;-----------------------------------------------------------------------------
4050675965ea 3.10 stable release
heinrichsweikamp
parents: 631
diff changeset
258 ;
4050675965ea 3.10 stable release
heinrichsweikamp
parents: 631
diff changeset
259 ; RS232 Functions
4050675965ea 3.10 stable release
heinrichsweikamp
parents: 631
diff changeset
260 ;
4050675965ea 3.10 stable release
heinrichsweikamp
parents: 631
diff changeset
261 ;-----------------------------------------------------------------------------
0
heinrichsweikamp
parents:
diff changeset
262
heinrichsweikamp
parents:
diff changeset
263
634
4050675965ea 3.10 stable release
heinrichsweikamp
parents: 631
diff changeset
264 ;-----------------------------------------------------------------------------
4050675965ea 3.10 stable release
heinrichsweikamp
parents: 631
diff changeset
265 ; Switch-On the IR/S8 Port
4050675965ea 3.10 stable release
heinrichsweikamp
parents: 631
diff changeset
266 ;
4050675965ea 3.10 stable release
heinrichsweikamp
parents: 631
diff changeset
267 global enable_ir_s8_analog
4050675965ea 3.10 stable release
heinrichsweikamp
parents: 631
diff changeset
268 enable_ir_s8_analog:
623
c40025d8e750 3.03 beta released
heinrichsweikamp
parents: 604
diff changeset
269 ;initialize serial port2 (TRISG2)
634
4050675965ea 3.10 stable release
heinrichsweikamp
parents: 631
diff changeset
270 btfsc ext_input_s8_ana ; do we have an S8/analog input?
4050675965ea 3.10 stable release
heinrichsweikamp
parents: 631
diff changeset
271 bra enable_s8_analog ; YES - enable S8/analog input
4050675965ea 3.10 stable release
heinrichsweikamp
parents: 631
diff changeset
272 ;bra enable_ir ; NO - enable IR digital input
0
heinrichsweikamp
parents:
diff changeset
273
634
4050675965ea 3.10 stable release
heinrichsweikamp
parents: 631
diff changeset
274 enable_ir:
4050675965ea 3.10 stable release
heinrichsweikamp
parents: 631
diff changeset
275 banksel BAUDCON2 ; select bank for IO register access
4050675965ea 3.10 stable release
heinrichsweikamp
parents: 631
diff changeset
276 movlw b'00100000' ; speed generator configuration: BRG16=0, inverted for IR
4050675965ea 3.10 stable release
heinrichsweikamp
parents: 631
diff changeset
277 movwf BAUDCON2 ; ...
4050675965ea 3.10 stable release
heinrichsweikamp
parents: 631
diff changeset
278 movlw b'00100000' ; TX configuration: BRGH=0, SYNC=0
4050675965ea 3.10 stable release
heinrichsweikamp
parents: 631
diff changeset
279 movwf TXSTA2 ; ...
4050675965ea 3.10 stable release
heinrichsweikamp
parents: 631
diff changeset
280 movlw .102 ; speed configuration: SPBRGH:SPBRG = .102 : 2403 BAUD @ 16 MHz
4050675965ea 3.10 stable release
heinrichsweikamp
parents: 631
diff changeset
281 movwf SPBRG2 ; ...
4050675965ea 3.10 stable release
heinrichsweikamp
parents: 631
diff changeset
282 clrf SPBRGH2 ; ...
4050675965ea 3.10 stable release
heinrichsweikamp
parents: 631
diff changeset
283 movlw b'10010000' ; RX configuration
4050675965ea 3.10 stable release
heinrichsweikamp
parents: 631
diff changeset
284 movwf RCSTA2 ; ...
4050675965ea 3.10 stable release
heinrichsweikamp
parents: 631
diff changeset
285 banksel common ; back to bank common
4050675965ea 3.10 stable release
heinrichsweikamp
parents: 631
diff changeset
286 bsf ir_power ; power-up IR
4050675965ea 3.10 stable release
heinrichsweikamp
parents: 631
diff changeset
287 btfss ir_power ; power-up confirmed?
4050675965ea 3.10 stable release
heinrichsweikamp
parents: 631
diff changeset
288 bra $-6 ; NO - loop and wait
4050675965ea 3.10 stable release
heinrichsweikamp
parents: 631
diff changeset
289 bsf PIE3,RC2IE ; enable RC2 INT
4050675965ea 3.10 stable release
heinrichsweikamp
parents: 631
diff changeset
290 return ; done
4050675965ea 3.10 stable release
heinrichsweikamp
parents: 631
diff changeset
291
4050675965ea 3.10 stable release
heinrichsweikamp
parents: 631
diff changeset
292 enable_s8_analog:
629
237931377539 3.07 stable release
heinrichsweikamp
parents: 628
diff changeset
293 banksel TXSTA2 ; select bank for IO register access
631
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
294 clrf TXSTA2 ; reset UART 2 TX function
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
295 clrf RCSTA2 ; reset UART 2 RX function
623
c40025d8e750 3.03 beta released
heinrichsweikamp
parents: 604
diff changeset
296 banksel common ; back to bank common
631
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
297
634
4050675965ea 3.10 stable release
heinrichsweikamp
parents: 631
diff changeset
298 bsf mcp_power ; power-up instrumentation amp (used by S8 and analog input)
631
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
299 btfss mcp_power ; power-up completed?
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
300 bra $-4 ; NO - loop
113
heinrichsweikamp
parents: 0
diff changeset
301
634
4050675965ea 3.10 stable release
heinrichsweikamp
parents: 631
diff changeset
302 ; branch according to S8 / analog selection
631
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
303 TSTOSS opt_s8_mode ; =0: analog, =1: digital RS232
634
4050675965ea 3.10 stable release
heinrichsweikamp
parents: 631
diff changeset
304 bra enable_analog ; -> analog
631
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
305
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
306 ; configure S8 digital interface
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
307 bcf s8_npower ; power S8 HUD (inverted via P-MOS transistor)
623
c40025d8e750 3.03 beta released
heinrichsweikamp
parents: 604
diff changeset
308 WAITMS d'30' ; NO - wait 30 ms
631
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
309 banksel BAUDCON2 ; select bank for IO register access
634
4050675965ea 3.10 stable release
heinrichsweikamp
parents: 631
diff changeset
310 movlw b'00000000' ; speed generator configuration: BRG16=0, normal for S8
4050675965ea 3.10 stable release
heinrichsweikamp
parents: 631
diff changeset
311 movwf BAUDCON2 ; ...
4050675965ea 3.10 stable release
heinrichsweikamp
parents: 631
diff changeset
312 movlw b'00100000' ; TX configuration: BRGH=0, SYNC=0
4050675965ea 3.10 stable release
heinrichsweikamp
parents: 631
diff changeset
313 movwf TXSTA2 ; ...
4050675965ea 3.10 stable release
heinrichsweikamp
parents: 631
diff changeset
314 movlw .25 ; speed configuration: SPBRGH:SPBRG = .25 : 9615 BAUD @ 16 MHz
4050675965ea 3.10 stable release
heinrichsweikamp
parents: 631
diff changeset
315 movwf SPBRG2 ; ...
4050675965ea 3.10 stable release
heinrichsweikamp
parents: 631
diff changeset
316 movlw b'10010000' ; RX configuration
4050675965ea 3.10 stable release
heinrichsweikamp
parents: 631
diff changeset
317 movwf RCSTA2 ; ...
623
c40025d8e750 3.03 beta released
heinrichsweikamp
parents: 604
diff changeset
318 banksel common ; back to bank common
631
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
319 bsf PIE3,RC2IE ; enable RC2 INT
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 386
diff changeset
320 return
113
heinrichsweikamp
parents: 0
diff changeset
321
634
4050675965ea 3.10 stable release
heinrichsweikamp
parents: 631
diff changeset
322 enable_analog:
631
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
323 ; S8 analog interface
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
324 bcf PIE3,RC2IE ; disable RC2 INT
634
4050675965ea 3.10 stable release
heinrichsweikamp
parents: 631
diff changeset
325 bsf s8_npower ; power-down S8 digital interface
4050675965ea 3.10 stable release
heinrichsweikamp
parents: 631
diff changeset
326 return ; done
631
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
327
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
328
634
4050675965ea 3.10 stable release
heinrichsweikamp
parents: 631
diff changeset
329 ;-----------------------------------------------------------------------------
4050675965ea 3.10 stable release
heinrichsweikamp
parents: 631
diff changeset
330 ; Shut-Down the IR/S8 Port
4050675965ea 3.10 stable release
heinrichsweikamp
parents: 631
diff changeset
331 ;
4050675965ea 3.10 stable release
heinrichsweikamp
parents: 631
diff changeset
332 global disable_ir_s8_analog
4050675965ea 3.10 stable release
heinrichsweikamp
parents: 631
diff changeset
333 disable_ir_s8_analog:
631
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
334 banksel TXSTA2 ; select bank for IO register access
634
4050675965ea 3.10 stable release
heinrichsweikamp
parents: 631
diff changeset
335 clrf TXSTA2 ; shut down TX function
4050675965ea 3.10 stable release
heinrichsweikamp
parents: 631
diff changeset
336 clrf RCSTA2 ; shut down RX function
4050675965ea 3.10 stable release
heinrichsweikamp
parents: 631
diff changeset
337 banksel common ; back to bank common
4050675965ea 3.10 stable release
heinrichsweikamp
parents: 631
diff changeset
338 bcf PIE3,RC2IE ; disable RC2 INT
4050675965ea 3.10 stable release
heinrichsweikamp
parents: 631
diff changeset
339 bcf ir_power ; power down IR receiver
4050675965ea 3.10 stable release
heinrichsweikamp
parents: 631
diff changeset
340 bcf mcp_power ; power-down instrumentation amp
4050675965ea 3.10 stable release
heinrichsweikamp
parents: 631
diff changeset
341 bsf s8_npower ; power-down S8 digital interface
4050675965ea 3.10 stable release
heinrichsweikamp
parents: 631
diff changeset
342 return ; done
4050675965ea 3.10 stable release
heinrichsweikamp
parents: 631
diff changeset
343
4050675965ea 3.10 stable release
heinrichsweikamp
parents: 631
diff changeset
344
4050675965ea 3.10 stable release
heinrichsweikamp
parents: 631
diff changeset
345 ;-----------------------------------------------------------------------------
4050675965ea 3.10 stable release
heinrichsweikamp
parents: 631
diff changeset
346 ; Send Byte in WREG via the IR/S8 Port
4050675965ea 3.10 stable release
heinrichsweikamp
parents: 631
diff changeset
347 ;
4050675965ea 3.10 stable release
heinrichsweikamp
parents: 631
diff changeset
348 global ir_s8_tx_single
4050675965ea 3.10 stable release
heinrichsweikamp
parents: 631
diff changeset
349 ir_s8_tx_single:
4050675965ea 3.10 stable release
heinrichsweikamp
parents: 631
diff changeset
350 banksel TXSTA2 ; UART 2 is outside of the access RAM
4050675965ea 3.10 stable release
heinrichsweikamp
parents: 631
diff changeset
351 movwf TXREG2 ; transmit byte
4050675965ea 3.10 stable release
heinrichsweikamp
parents: 631
diff changeset
352 ir_s8_tx_single_loop:
4050675965ea 3.10 stable release
heinrichsweikamp
parents: 631
diff changeset
353 btfss TXSTA2,TRMT ; TX completed?
4050675965ea 3.10 stable release
heinrichsweikamp
parents: 631
diff changeset
354 bra ir_s8_tx_single_loop ; NO - wait...
4050675965ea 3.10 stable release
heinrichsweikamp
parents: 631
diff changeset
355 banksel common ; YES - back to bank common
631
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
356 return ; - done
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
357
634
4050675965ea 3.10 stable release
heinrichsweikamp
parents: 631
diff changeset
358
631
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
359 ;-----------------------------------------------------------------------------
634
4050675965ea 3.10 stable release
heinrichsweikamp
parents: 631
diff changeset
360 ; Switch-On USB/BT Port
4050675965ea 3.10 stable release
heinrichsweikamp
parents: 631
diff changeset
361 ;
0
heinrichsweikamp
parents:
diff changeset
362 global enable_rs232
heinrichsweikamp
parents:
diff changeset
363 enable_rs232:
623
c40025d8e750 3.03 beta released
heinrichsweikamp
parents: 604
diff changeset
364 call request_speed_normal ; request CPU speed change to normal speed
c40025d8e750 3.03 beta released
heinrichsweikamp
parents: 604
diff changeset
365 enable_rs232_1:
c40025d8e750 3.03 beta released
heinrichsweikamp
parents: 604
diff changeset
366 btfss speed_is_normal ; speed = normal?
631
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
367 bra enable_rs232_1 ; NO - loop waiting for ISR to have adjusted the speed
640
8c1f1f334275 3.13 release
heinrichsweikamp
parents: 634
diff changeset
368 bsf TRISC,7
631
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
369 bcf PORTE,0 ; YES - switch port to comm
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
370 bsf PORTJ,2 ; - /Reset (required for very old OSTC sport)
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
371 movlw b'00100100' ; - TX configuration: TX enabled, async, high speed
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
372 movwf TXSTA1 ; - ...
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
373 movlw b'10010000' ; - RX configuration: port enabled, RX enabled
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
374 movwf RCSTA1 ; - ...
634
4050675965ea 3.10 stable release
heinrichsweikamp
parents: 631
diff changeset
375 IFNDEF _comm_debug
4050675965ea 3.10 stable release
heinrichsweikamp
parents: 631
diff changeset
376 movlw HIGH(.65536-rx_timeout*.32) ; - define TMR5H initialization value for RX timeout (rx_timeout defined in hwos.inc)
4050675965ea 3.10 stable release
heinrichsweikamp
parents: 631
diff changeset
377 ELSE
4050675965ea 3.10 stable release
heinrichsweikamp
parents: 631
diff changeset
378 include "math.inc"
4050675965ea 3.10 stable release
heinrichsweikamp
parents: 631
diff changeset
379 movff opt_comm_timeout,xA+0 ; - get timeout setting in multiples of 10 ms (opt_comm_timeout: 10 .. 200 x 10 ms)
4050675965ea 3.10 stable release
heinrichsweikamp
parents: 631
diff changeset
380 clrf xA+1 ; - ...
4050675965ea 3.10 stable release
heinrichsweikamp
parents: 631
diff changeset
381 MOVLI .320,xB ; - multiply with 10 to get timeout in ms and 32 because tmr5 ticks 32x per ms
4050675965ea 3.10 stable release
heinrichsweikamp
parents: 631
diff changeset
382 call mult16x16 ; - xC = xA * xB = timer ticks to go until timeout
4050675965ea 3.10 stable release
heinrichsweikamp
parents: 631
diff changeset
383 MOVII xC,sub_b ; - multiplication result is max. 64000
4050675965ea 3.10 stable release
heinrichsweikamp
parents: 631
diff changeset
384 MOVLI .65535,sub_a ; - timer wraps around after 65535
4050675965ea 3.10 stable release
heinrichsweikamp
parents: 631
diff changeset
385 call subU16 ; - sub_c = sub_a - sub_b = start value for timer
4050675965ea 3.10 stable release
heinrichsweikamp
parents: 631
diff changeset
386
4050675965ea 3.10 stable release
heinrichsweikamp
parents: 631
diff changeset
387 movlw .244 ; safety maximum value for rx_timeout_tmr5h_load (minimum timeout interval)
4050675965ea 3.10 stable release
heinrichsweikamp
parents: 631
diff changeset
388 cpfslt sub_c+1 ; result > safety value?
4050675965ea 3.10 stable release
heinrichsweikamp
parents: 631
diff changeset
389 movwf sub_c+1 ; YES - revert to safety value
4050675965ea 3.10 stable release
heinrichsweikamp
parents: 631
diff changeset
390
4050675965ea 3.10 stable release
heinrichsweikamp
parents: 631
diff changeset
391 movf sub_c+1,W ; - keep only the upper byte as TMR5H initialization value for RX timeout
4050675965ea 3.10 stable release
heinrichsweikamp
parents: 631
diff changeset
392 ENDIF
4050675965ea 3.10 stable release
heinrichsweikamp
parents: 631
diff changeset
393 movwf rx_timeout_tmr5h_load ; - store for later use
631
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
394 return ; - done
0
heinrichsweikamp
parents:
diff changeset
395
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 386
diff changeset
396
634
4050675965ea 3.10 stable release
heinrichsweikamp
parents: 631
diff changeset
397 ;-----------------------------------------------------------------------------
4050675965ea 3.10 stable release
heinrichsweikamp
parents: 631
diff changeset
398 ; Shut-Down USB/BT Port
4050675965ea 3.10 stable release
heinrichsweikamp
parents: 631
diff changeset
399 ;
0
heinrichsweikamp
parents:
diff changeset
400 global disable_rs232
heinrichsweikamp
parents:
diff changeset
401 disable_rs232:
631
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
402 clrf RCSTA1 ; disable RX
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
403 clrf TXSTA1 ; disable TX
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
404 bcf PORTC,6 ; switch TX pin hard to GND
634
4050675965ea 3.10 stable release
heinrichsweikamp
parents: 631
diff changeset
405 bsf PORTE,0 ; power down BT chip
631
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
406 bcf PORTJ,2 ; /Reset (required for very old OSTC sport)
640
8c1f1f334275 3.13 release
heinrichsweikamp
parents: 634
diff changeset
407 bcf TRISC,7
8c1f1f334275 3.13 release
heinrichsweikamp
parents: 634
diff changeset
408 bcf PORTC,7 ; switch RX pin hard to GND
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 386
diff changeset
409 return
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 386
diff changeset
410
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 386
diff changeset
411
634
4050675965ea 3.10 stable release
heinrichsweikamp
parents: 631
diff changeset
412 ;-----------------------------------------------------------------------------
4050675965ea 3.10 stable release
heinrichsweikamp
parents: 631
diff changeset
413 ; Wait for last Byte to be sent out of USB/BT Port
4050675965ea 3.10 stable release
heinrichsweikamp
parents: 631
diff changeset
414 ;
631
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
415 global rs232_wait_tx ; ++++ do not touch WREG here! ++++
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
416 rs232_wait_tx:
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
417 btfss TXSTA1,TRMT ; last byte completely shifted out on TX pin?
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
418 bra rs232_wait_tx ; NO - wait...
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
419 btfss ble_available ; YES - OSTC running with Bluetooth?
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
420 return ; NO - done
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
421 btfsc NRTS ; YES - Bluetooth module also completed TX?
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
422 bra rs232_wait_tx ; NO - wait...
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
423 return ; YES - done
623
c40025d8e750 3.03 beta released
heinrichsweikamp
parents: 604
diff changeset
424
c40025d8e750 3.03 beta released
heinrichsweikamp
parents: 604
diff changeset
425
634
4050675965ea 3.10 stable release
heinrichsweikamp
parents: 631
diff changeset
426 ;-----------------------------------------------------------------------------
4050675965ea 3.10 stable release
heinrichsweikamp
parents: 631
diff changeset
427 ; Receive one Byte via the USB/BT Port
4050675965ea 3.10 stable release
heinrichsweikamp
parents: 631
diff changeset
428 ;
4050675965ea 3.10 stable release
heinrichsweikamp
parents: 631
diff changeset
429 ; ++++ make this code as fast as possible! ++++
4050675965ea 3.10 stable release
heinrichsweikamp
parents: 631
diff changeset
430 ; ++++ do not touch WREG here! ++++
4050675965ea 3.10 stable release
heinrichsweikamp
parents: 631
diff changeset
431 ;
4050675965ea 3.10 stable release
heinrichsweikamp
parents: 631
diff changeset
432 global serial_rx_single
4050675965ea 3.10 stable release
heinrichsweikamp
parents: 631
diff changeset
433 serial_rx_single:
631
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
434 bcf rs232_rx_timeout ; clear timeout flag
634
4050675965ea 3.10 stable release
heinrichsweikamp
parents: 631
diff changeset
435 btfsc PIR1,RCIF ; received a data byte? (bit is set on RX completion and reset on reading RCREG1)
4050675965ea 3.10 stable release
heinrichsweikamp
parents: 631
diff changeset
436 return ; YES - done (fast path)
4050675965ea 3.10 stable release
heinrichsweikamp
parents: 631
diff changeset
437 movff rx_timeout_tmr5h_load,TMR5H ; NO - load TMR5 high with timeout value
631
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
438 clrf TMR5L ; - load TMR5 low with a zero, writing low starts the timer
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
439 bcf PIR5,TMR5IF ; - clear timer overflow flag
634
4050675965ea 3.10 stable release
heinrichsweikamp
parents: 631
diff changeset
440 serial_rx_single_loop:
631
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
441 btfsc PIR1,RCIF ; received a data byte?
634
4050675965ea 3.10 stable release
heinrichsweikamp
parents: 631
diff changeset
442 return ; YES - done
631
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
443 btfss PIR5,TMR5IF ; NO - timer overflow (timeout)?
634
4050675965ea 3.10 stable release
heinrichsweikamp
parents: 631
diff changeset
444 bra serial_rx_single_loop ; NO - continue waiting
4050675965ea 3.10 stable release
heinrichsweikamp
parents: 631
diff changeset
445 ;bra serial_rx_timeout ; YES - timeout
623
c40025d8e750 3.03 beta released
heinrichsweikamp
parents: 604
diff changeset
446
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 386
diff changeset
447
631
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
448 ;-----------------------------------------------------------------------------
634
4050675965ea 3.10 stable release
heinrichsweikamp
parents: 631
diff changeset
449 ; Helper Function: Timeout in serial_rx_single / serial_tx_steam
4050675965ea 3.10 stable release
heinrichsweikamp
parents: 631
diff changeset
450 ;
4050675965ea 3.10 stable release
heinrichsweikamp
parents: 631
diff changeset
451 serial_rx_timeout:
4050675965ea 3.10 stable release
heinrichsweikamp
parents: 631
diff changeset
452 bsf rs232_rx_timeout ; set timeout flag
4050675965ea 3.10 stable release
heinrichsweikamp
parents: 631
diff changeset
453 bcf RCSTA1,CREN ; clear receiver status: disable RX,
4050675965ea 3.10 stable release
heinrichsweikamp
parents: 631
diff changeset
454 bsf RCSTA1,CREN ; ... enable again RX
4050675965ea 3.10 stable release
heinrichsweikamp
parents: 631
diff changeset
455 return ; done
4050675965ea 3.10 stable release
heinrichsweikamp
parents: 631
diff changeset
456
623
c40025d8e750 3.03 beta released
heinrichsweikamp
parents: 604
diff changeset
457
634
4050675965ea 3.10 stable release
heinrichsweikamp
parents: 631
diff changeset
458 ;-----------------------------------------------------------------------------
4050675965ea 3.10 stable release
heinrichsweikamp
parents: 631
diff changeset
459 ; Send and Receive Functions to be used via Macros
4050675965ea 3.10 stable release
heinrichsweikamp
parents: 631
diff changeset
460 ;-----------------------------------------------------------------------------
4050675965ea 3.10 stable release
heinrichsweikamp
parents: 631
diff changeset
461
4050675965ea 3.10 stable release
heinrichsweikamp
parents: 631
diff changeset
462 ;-----------------------------------------------------------------------------
4050675965ea 3.10 stable release
heinrichsweikamp
parents: 631
diff changeset
463 ; Send a Range of 1-256 Bytes from Memory via the USB/BT Port
631
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
464 ;
634
4050675965ea 3.10 stable release
heinrichsweikamp
parents: 631
diff changeset
465 global serial_tx_steam
4050675965ea 3.10 stable release
heinrichsweikamp
parents: 631
diff changeset
466 serial_tx_steam:
631
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
467 movwf eeprom_loop ; initialize loop counter (eeprom variable used here)
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
468 serial_tx_ram_loop:
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
469 rcall rs232_wait_tx ; wait for completion of last transmit
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
470 movff POSTINC2,TXREG1 ; send a byte from memory to serial
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
471 decfsz eeprom_loop,F ; decrement loop counter, became zero?
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
472 bra serial_tx_ram_loop ; NO - loop
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
473 return ; YES - done
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 386
diff changeset
474
623
c40025d8e750 3.03 beta released
heinrichsweikamp
parents: 604
diff changeset
475
634
4050675965ea 3.10 stable release
heinrichsweikamp
parents: 631
diff changeset
476 ;-----------------------------------------------------------------------------
4050675965ea 3.10 stable release
heinrichsweikamp
parents: 631
diff changeset
477 ; Receive a Range of 1-256 Byte via the USB/BT Port and write them to Memory
4050675965ea 3.10 stable release
heinrichsweikamp
parents: 631
diff changeset
478 ; ++++ make this code as fast as possible! ++++
631
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
479 ;
634
4050675965ea 3.10 stable release
heinrichsweikamp
parents: 631
diff changeset
480 global serial_rx_stream
4050675965ea 3.10 stable release
heinrichsweikamp
parents: 631
diff changeset
481 serial_rx_stream:
631
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
482 movwf eeprom_loop ; initialize loop counter (eeprom variable used here)
634
4050675965ea 3.10 stable release
heinrichsweikamp
parents: 631
diff changeset
483 serial_rx_stream_loop:
631
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
484 btfss PIR1,RCIF ; received a data byte? (bit is set on RX complete and reset on reading RCREG1)
634
4050675965ea 3.10 stable release
heinrichsweikamp
parents: 631
diff changeset
485 bra serial_rx_stream_tmr ; NO - enter receive loop with timeout
4050675965ea 3.10 stable release
heinrichsweikamp
parents: 631
diff changeset
486 ;bra serial_rx_stream_received ; YES - copy to memory, tick counter, ...
4050675965ea 3.10 stable release
heinrichsweikamp
parents: 631
diff changeset
487
4050675965ea 3.10 stable release
heinrichsweikamp
parents: 631
diff changeset
488 serial_rx_stream_received:
4050675965ea 3.10 stable release
heinrichsweikamp
parents: 631
diff changeset
489 movff RCREG1,POSTINC2 ; copy received byte to memory
4050675965ea 3.10 stable release
heinrichsweikamp
parents: 631
diff changeset
490 decfsz eeprom_loop,F ; decrement loop counter, became zero?
4050675965ea 3.10 stable release
heinrichsweikamp
parents: 631
diff changeset
491 bra serial_rx_stream_loop ; NO - await next byte
4050675965ea 3.10 stable release
heinrichsweikamp
parents: 631
diff changeset
492 bcf rs232_rx_timeout ; YES - clear timeout flag
4050675965ea 3.10 stable release
heinrichsweikamp
parents: 631
diff changeset
493 return ; - all bytes received, done
4050675965ea 3.10 stable release
heinrichsweikamp
parents: 631
diff changeset
494
4050675965ea 3.10 stable release
heinrichsweikamp
parents: 631
diff changeset
495 serial_rx_stream_tmr:
4050675965ea 3.10 stable release
heinrichsweikamp
parents: 631
diff changeset
496 movff rx_timeout_tmr5h_load,TMR5H ; load TMR5 high with timeout value
4050675965ea 3.10 stable release
heinrichsweikamp
parents: 631
diff changeset
497 clrf TMR5L ; load TMR5 low with a zero, writing to low starts the timer
631
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
498 bcf PIR5,TMR5IF ; clear timer overflow flag
634
4050675965ea 3.10 stable release
heinrichsweikamp
parents: 631
diff changeset
499 serial_rx_stream_tmr_loop:
4050675965ea 3.10 stable release
heinrichsweikamp
parents: 631
diff changeset
500 btfsc PIR1,RCIF ; received a data byte? (bit is set on RX complete and reset on reading RCREG1)
4050675965ea 3.10 stable release
heinrichsweikamp
parents: 631
diff changeset
501 bra serial_rx_stream_received ; YES - copy to memory, tick counter, ...
4050675965ea 3.10 stable release
heinrichsweikamp
parents: 631
diff changeset
502 btfss PIR5,TMR5IF ; NO - timer overflow (timeout)?
4050675965ea 3.10 stable release
heinrichsweikamp
parents: 631
diff changeset
503 bra serial_rx_stream_tmr_loop ; NO - continue waiting
4050675965ea 3.10 stable release
heinrichsweikamp
parents: 631
diff changeset
504 bra serial_rx_timeout ; YES - timeout
623
c40025d8e750 3.03 beta released
heinrichsweikamp
parents: 604
diff changeset
505
631
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
506 ;-----------------------------------------------------------------------------
634
4050675965ea 3.10 stable release
heinrichsweikamp
parents: 631
diff changeset
507
648
aeca5717d9eb 3.17 / 10.72 release
heinrichs weikamp
parents: 640
diff changeset
508 ;-----------------------------------------------------------------------------
aeca5717d9eb 3.17 / 10.72 release
heinrichs weikamp
parents: 640
diff changeset
509 ; Add new services and characteristics to new BLE (type 2) module
aeca5717d9eb 3.17 / 10.72 release
heinrichs weikamp
parents: 640
diff changeset
510 ;-----------------------------------------------------------------------------
aeca5717d9eb 3.17 / 10.72 release
heinrichs weikamp
parents: 640
diff changeset
511 global ble2_configure
aeca5717d9eb 3.17 / 10.72 release
heinrichs weikamp
parents: 640
diff changeset
512 ble2_configure:
aeca5717d9eb 3.17 / 10.72 release
heinrichs weikamp
parents: 640
diff changeset
513 rcall enable_rs232
aeca5717d9eb 3.17 / 10.72 release
heinrichs weikamp
parents: 640
diff changeset
514 bcf NCTS ; Clear to send
aeca5717d9eb 3.17 / 10.72 release
heinrichs weikamp
parents: 640
diff changeset
515 call wait_1s
aeca5717d9eb 3.17 / 10.72 release
heinrichs weikamp
parents: 640
diff changeset
516 call wait_1s
650
bc214815deb2 3.19/10.75 release
heinrichsweikamp
parents: 648
diff changeset
517 call wait_1s
bc214815deb2 3.19/10.75 release
heinrichsweikamp
parents: 648
diff changeset
518 call wait_1s
648
aeca5717d9eb 3.17 / 10.72 release
heinrichs weikamp
parents: 640
diff changeset
519 bcf PORTB,6
650
bc214815deb2 3.19/10.75 release
heinrichsweikamp
parents: 648
diff changeset
520 nop
648
aeca5717d9eb 3.17 / 10.72 release
heinrichs weikamp
parents: 640
diff changeset
521 bsf PORTB,6 ; rising edge -> Command mode
aeca5717d9eb 3.17 / 10.72 release
heinrichs weikamp
parents: 640
diff changeset
522
aeca5717d9eb 3.17 / 10.72 release
heinrichs weikamp
parents: 640
diff changeset
523 ; point to config table
aeca5717d9eb 3.17 / 10.72 release
heinrichs weikamp
parents: 640
diff changeset
524 movlw LOW ble_AT1
aeca5717d9eb 3.17 / 10.72 release
heinrichs weikamp
parents: 640
diff changeset
525 movwf TBLPTRL
aeca5717d9eb 3.17 / 10.72 release
heinrichs weikamp
parents: 640
diff changeset
526 movlw HIGH ble_AT1
aeca5717d9eb 3.17 / 10.72 release
heinrichs weikamp
parents: 640
diff changeset
527 movwf TBLPTRH
aeca5717d9eb 3.17 / 10.72 release
heinrichs weikamp
parents: 640
diff changeset
528 movlw UPPER ble_AT1
aeca5717d9eb 3.17 / 10.72 release
heinrichs weikamp
parents: 640
diff changeset
529 movwf TBLPTRU
aeca5717d9eb 3.17 / 10.72 release
heinrichs weikamp
parents: 640
diff changeset
530 rcall ble_init_loop
aeca5717d9eb 3.17 / 10.72 release
heinrichs weikamp
parents: 640
diff changeset
531
aeca5717d9eb 3.17 / 10.72 release
heinrichs weikamp
parents: 640
diff changeset
532 rcall disable_rs232
aeca5717d9eb 3.17 / 10.72 release
heinrichs weikamp
parents: 640
diff changeset
533 bcf PORTB,6 ; keep low for min. current consumption
aeca5717d9eb 3.17 / 10.72 release
heinrichs weikamp
parents: 640
diff changeset
534 return ; done.
aeca5717d9eb 3.17 / 10.72 release
heinrichs weikamp
parents: 640
diff changeset
535
aeca5717d9eb 3.17 / 10.72 release
heinrichs weikamp
parents: 640
diff changeset
536 ble_init_loop:
aeca5717d9eb 3.17 / 10.72 release
heinrichs weikamp
parents: 640
diff changeset
537 TBLRD*+
aeca5717d9eb 3.17 / 10.72 release
heinrichs weikamp
parents: 640
diff changeset
538 movlw 0xFF ; end
aeca5717d9eb 3.17 / 10.72 release
heinrichs weikamp
parents: 640
diff changeset
539 cpfseq TABLAT
aeca5717d9eb 3.17 / 10.72 release
heinrichs weikamp
parents: 640
diff changeset
540 bra ble_init_loop1 ; not end
aeca5717d9eb 3.17 / 10.72 release
heinrichs weikamp
parents: 640
diff changeset
541 ; quit (return)
aeca5717d9eb 3.17 / 10.72 release
heinrichs weikamp
parents: 640
diff changeset
542 return ; done.
aeca5717d9eb 3.17 / 10.72 release
heinrichs weikamp
parents: 640
diff changeset
543 ble_init_loop1:
aeca5717d9eb 3.17 / 10.72 release
heinrichs weikamp
parents: 640
diff changeset
544 movlw 0xFE ; WAIT 20ms
aeca5717d9eb 3.17 / 10.72 release
heinrichs weikamp
parents: 640
diff changeset
545 cpfseq TABLAT
aeca5717d9eb 3.17 / 10.72 release
heinrichs weikamp
parents: 640
diff changeset
546 bra ble_init_loop2 ; not wait 20ms
aeca5717d9eb 3.17 / 10.72 release
heinrichs weikamp
parents: 640
diff changeset
547 WAITMS d'20'
aeca5717d9eb 3.17 / 10.72 release
heinrichs weikamp
parents: 640
diff changeset
548 bra ble_init_loop
aeca5717d9eb 3.17 / 10.72 release
heinrichs weikamp
parents: 640
diff changeset
549 ble_init_loop2:
aeca5717d9eb 3.17 / 10.72 release
heinrichs weikamp
parents: 640
diff changeset
550 movlw 0xFD ; WAIT 1s
aeca5717d9eb 3.17 / 10.72 release
heinrichs weikamp
parents: 640
diff changeset
551 cpfseq TABLAT
aeca5717d9eb 3.17 / 10.72 release
heinrichs weikamp
parents: 640
diff changeset
552 bra ble_init_loop3 ; not wait 1s
aeca5717d9eb 3.17 / 10.72 release
heinrichs weikamp
parents: 640
diff changeset
553 call wait_1s
aeca5717d9eb 3.17 / 10.72 release
heinrichs weikamp
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diff changeset
554 bra ble_init_loop
aeca5717d9eb 3.17 / 10.72 release
heinrichs weikamp
parents: 640
diff changeset
555 ble_init_loop3:
aeca5717d9eb 3.17 / 10.72 release
heinrichs weikamp
parents: 640
diff changeset
556 movf TABLAT,W
aeca5717d9eb 3.17 / 10.72 release
heinrichs weikamp
parents: 640
diff changeset
557 SERIAL_CC_SEND WREG
aeca5717d9eb 3.17 / 10.72 release
heinrichs weikamp
parents: 640
diff changeset
558 bra ble_init_loop
aeca5717d9eb 3.17 / 10.72 release
heinrichs weikamp
parents: 640
diff changeset
559
aeca5717d9eb 3.17 / 10.72 release
heinrichs weikamp
parents: 640
diff changeset
560 ble_AT1: ; config table
aeca5717d9eb 3.17 / 10.72 release
heinrichs weikamp
parents: 640
diff changeset
561 ; 0xFF at the end
aeca5717d9eb 3.17 / 10.72 release
heinrichs weikamp
parents: 640
diff changeset
562 ; 0xFE: 20ms delay
aeca5717d9eb 3.17 / 10.72 release
heinrichs weikamp
parents: 640
diff changeset
563 ; 0xFD: 1s delay
aeca5717d9eb 3.17 / 10.72 release
heinrichs weikamp
parents: 640
diff changeset
564 ; .13: cr character
650
bc214815deb2 3.19/10.75 release
heinrichsweikamp
parents: 648
diff changeset
565 db 0xFD,0xFD,0xFD,0xFD ; Wait 4 seconds
648
aeca5717d9eb 3.17 / 10.72 release
heinrichs weikamp
parents: 640
diff changeset
566 db "AT+UDSC=0,0",.13,0xFE,0xFE ; Disable SPP Server on ID0 (and wait 40ms)
aeca5717d9eb 3.17 / 10.72 release
heinrichs weikamp
parents: 640
diff changeset
567 db "AT+UDSC=0,3",.13,0xFE,0xFE ; SPP Server on ID0 (and wait 40ms)
aeca5717d9eb 3.17 / 10.72 release
heinrichs weikamp
parents: 640
diff changeset
568 db "AT+UDSC=1,0",.13,0xFE,0xFE ; Disable SPS Server on ID1 (and wait 40ms)
aeca5717d9eb 3.17 / 10.72 release
heinrichs weikamp
parents: 640
diff changeset
569 db "AT+UDSC=1,6",.13,0xFE,0xFE ; SPS Server on ID1 (and wait 40ms)
aeca5717d9eb 3.17 / 10.72 release
heinrichs weikamp
parents: 640
diff changeset
570 db "AT&W",.13,0xFE ; write settings into eeprom (and wait 20ms)
aeca5717d9eb 3.17 / 10.72 release
heinrichs weikamp
parents: 640
diff changeset
571 db "AT+CPWROFF",.13,0xFD,0xFD,0xFF ; save and reboot (and wait 2 seconds)
aeca5717d9eb 3.17 / 10.72 release
heinrichs weikamp
parents: 640
diff changeset
572
aeca5717d9eb 3.17 / 10.72 release
heinrichs weikamp
parents: 640
diff changeset
573
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 386
diff changeset
574 END