annotate src/eeprom_rs232.asm @ 646:5b7fe7777425

3.16 release
author heinrichs weikamp
date Thu, 14 Oct 2021 12:03:24 +0200
parents 8c1f1f334275
children aeca5717d9eb
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1 ;=============================================================================
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2 ;
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3 ; File eeprom_rs232.asm * combined next generation V3.09.4n
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4 ;
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5 ; Internal EEPROM, RS232
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6 ;
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7 ; Copyright (c) 2011, JD Gascuel, HeinrichsWeikamp, all right reserved.
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8 ;=============================================================================
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9 ; HISTORY
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10 ; 2011-08-06 : [mH] moving from OSTC code
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11
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12 #include "hwos.inc"
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13 #include "wait.inc"
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14 #include "shared_definitions.h"
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15 #include "rtc.inc"
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16 #include "external_flash.inc"
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17
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18 #DEFINE INSIDE_EEPROM_RS232
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19 #include "eeprom_rs232.inc"
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20
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21
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22 extern lt2942_charge_done
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23
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24
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25 ;=============================================================================
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26 eeprom CODE
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27 ;=============================================================================
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28
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29 ;-----------------------------------------------------------------------------
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30 ;
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31 ; EEPROM Functions - for EEPROM Macros and Memory Map, see eeprom_rs232.inc
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32 ;
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33 ;-----------------------------------------------------------------------------
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34
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35
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36 ;-----------------------------------------------------------------------------
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37 ; Read from internal EEPROM
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38 ;
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39 ; Input: EEADRH:EEADR = EEPROM address
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40 ; Output: EEDATA
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41 ; Trashed: NONE
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42 ;
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43 global read_eeprom
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44 read_eeprom:
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45 bcf EECON1,EEPGD ; access data EEPROM
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46 bcf EECON1,CFGS ; ...
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47 bsf EECON1,RD ; initiate reading
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48 return ; done
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49
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50
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51 ;-----------------------------------------------------------------------------
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52 ; Write into internal EEPROM
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53 ;
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54 ; Input: EEADRH:EEADR = EEPROM address
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55 ; EEDATA = byte to write
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56 ; Trashed: WREG
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57 ;
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58 global write_eeprom
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59 write_eeprom:
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60 bcf EECON1,EEPGD ; access data EEPROM
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61 bcf EECON1,CFGS ; ...
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62 bsf EECON1,WREN ; enable writing
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63 bcf INTCON,GIE ; disable interrupts
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64 movlw 0x55 ; unlock sequence
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65 movwf EECON2 ; ...
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66 movlw 0xAA ; ...
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67 movwf EECON2 ; ...
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68 bsf EECON1,WR ; start write operation
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69 write_eeprom_loop:
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70 btfsc EECON1,WR ; write completed?
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71 bra write_eeprom_loop ; NO - loop waiting
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72 bcf EECON1,WREN ; YES - disable writing
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73 bsf INTCON,GIE ; - re-enable interrupts
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74 return ; - done
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75
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76
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77 ;-----------------------------------------------------------------------------
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78 ; EEPROM read and write Functions to be used via Macros
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79 ;
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80 global eeprom_read_common
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81 eeprom_read_common:
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82 movwf eeprom_loop ; initialize loop counter
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83 eeprom_read_common_loop:
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84 rcall read_eeprom ; execute read
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85 movff EEDATA,POSTINC1 ; copy byte from EEPROM data register to memory
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86 incf EEADR,F ; advance to next EEPROM cell
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87 decfsz eeprom_loop,F ; decrement loop counter, all done?
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88 bra eeprom_read_common_loop ; NO - loop
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89 return ; YES - done
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90
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91 global eeprom_write_common
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92 eeprom_write_common:
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93 movwf eeprom_loop ; initialize loop counter
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94 eeprom_write_common_loop:
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95 movff POSTINC1,EEDATA ; copy byte from memory to EEPROM data register
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96 rcall write_eeprom ; execute write
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97 incf EEADR,F ; advance to next EEPROM cell
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98 decfsz eeprom_loop,F ; decrement loop counter, all done?
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99 bra eeprom_write_common_loop ; NO - loop
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100 return ; YES - done
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101
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102
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103 ;-----------------------------------------------------------------------------
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104 ; Read OSTC Serial Number
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105 ;
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106 global eeprom_serial_number_read
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107 eeprom_serial_number_read:
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108 EEPROM_II_READ eeprom_ostc_serial,mpr ; read serial number
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109 return ; done
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110
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111
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112 ;-----------------------------------------------------------------------------
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113 ; Read and Write Dive Number Offset
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114 ;
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115 global eeprom_log_offset_read
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116 eeprom_log_offset_read:
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117 EEPROM_II_READ eeprom_log_offset,mpr ; read log offset
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118 return ; done
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119
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120 global eeprom_log_offset_write
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121 eeprom_log_offset_write:
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122 EEPROM_II_WRITE mpr,eeprom_log_offset ; write log-offset
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123 return ; done
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124
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125
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126 ;-----------------------------------------------------------------------------
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127 ; Read and Write total Number of Dives
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128 ;
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129 global eeprom_total_dives_read
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130 eeprom_total_dives_read:
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131 EEPROM_II_READ eeprom_num_dives,mpr ; read total dives
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132 return ; done
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133
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134 global eeprom_total_dives_write
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135 eeprom_total_dives_write:
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136 EEPROM_II_WRITE mpr,eeprom_num_dives ; write total dives
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137 return ; done
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138
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139
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140 ;-----------------------------------------------------------------------------
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141 ; Read and Write the Battery Type and Gauge Reading
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142 ;
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143 global eeprom_battery_gauge_read
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144 eeprom_battery_gauge_read:
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145 ; retrieve battery gauge from EEPROM 0x07-0x0C
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146 bsf block_battery_gauge ; suspend ISR from accessing the battery gauge
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147 EEPROM_CC_READ eeprom_battery_type, battery_type ; 1 byte read from EEPROM
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148 EEPROM_RR_READ eeprom_battery_gauge,battery_gauge,.6 ; 6 byte read from EEPROM
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149 bcf block_battery_gauge ; allow ISR to access the battery gauge again
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150 return ; done
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151
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152 global eeprom_battery_gauge_write
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153 eeprom_battery_gauge_write:
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154 bsf block_battery_gauge ; suspend ISR from accessing the battery gauge
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155 EEPROM_CC_WRITE battery_type, eeprom_battery_type ; 1 byte write to EEPROM
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156 update_battery_gauge:
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157 EEPROM_RR_WRITE battery_gauge,eeprom_battery_gauge,.6 ; 6 byte write to EEPROM
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158 bcf block_battery_gauge ; allow ISR to access the battery gauge again
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159 return ; done
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160
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161
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162 ;-----------------------------------------------------------------------------
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163 ; Memorize the Checksum of the Firmware in the update Storage
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164 ;
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165 global eeprom_memorize_fw_checksum
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166 eeprom_memorize_fw_checksum:
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167 EXT_FLASH_ADDR 0x3E000D ; address firmware ID at 0x3E000D
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168 FLASH_CW_READ_0x40 ; read firmware ID to WREG
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169 movff WREG,buffer+.5 ; append firmware ID to checksum
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170 EEPROM_RR_WRITE buffer,eeprom_fw_chksum_current,.6 ; do a 6 byte write to EEPROM
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171 return ; done
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172
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173
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174 ;-----------------------------------------------------------------------------
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175 ; Read and Write the Deco Status
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176 ;
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177 global eeprom_deco_data_read
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178 eeprom_deco_data_read:
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179
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180 btfsc RCON,POR ; was there a power outage?
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181 bra eeprom_deco_data_read_1 ; NO - RTC is up-to-date
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heinrichsweikamp
parents: 629
diff changeset
182
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
183 EEPROM_RR_READ eeprom_deco_data_timestamp,rtc_latched_year,.6 ; 6 byte read from EEPROM
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
184 call rtc_set_rtc ; recover RTC to last known time & date
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
185
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
186 eeprom_deco_data_read_1:
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
187
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
188 ; restore surface interval
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
189 EEPROM_II_READ eeprom_deco_data_surfinterval,mpr ; 2 byte read from EEPROM
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
190 SMOVII mpr,surface_interval_mins ; ISR-safe copy of surface interval
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
191
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
192 ; bank 3: restore desaturation status
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
193 EEPROM_RR_READ eeprom_deco_data_bank3,0x300,.9 ; 9 byte read from EEPROM
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
194
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
195 ; bank 5: restore CNS
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
196 EEPROM_RR_READ eeprom_deco_data_bank5,0x500,.4 ; 4 byte read from EEPROM
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
197
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
198 ; bank 7: restore tissue pressures
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
199 EEPROM_RR_READ eeprom_deco_data_bank7,0x700,.128 ; 128 byte read from EEPROM
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
200
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
201 return ; done
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
202
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
203
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
204 global eeprom_deco_data_write
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
205 eeprom_deco_data_write:
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
206
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
207 ; invalidate current data in vault
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
208 movlw DECO_DATA_INVALID_TOKEN ; deco data invalid token
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
209 EEPROM_CC_WRITE WREG,eeprom_deco_data_validity ; 1 byte write to EEPROM
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
210
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
211 ; store vault version
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
212 movlw eeprom_vault_version ; deco data format version
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
213 EEPROM_CC_WRITE WREG,eeprom_deco_data_version ; 1 byte write to EEPROM
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
214
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
215 ; store date/time
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
216 SMOVSS rtc_year,rtc_latched_year ; ISR-safe 6 byte copy of date and time
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
217 EEPROM_RR_WRITE rtc_latched_year,eeprom_deco_data_timestamp,.6 ; 6 byte write to EEPROM
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
218
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
219 ; store surface interval
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
220 SMOVII surface_interval_mins,mpr ; ISR-safe copy of surface interval
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
221 EEPROM_II_WRITE mpr,eeprom_deco_data_surfinterval ; 2 byte write to EEPROM
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
222
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
223 ; bank 3: store desaturation status
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
224 EEPROM_RR_WRITE 0x300,eeprom_deco_data_bank3,.9 ; 9 byte write to EEPROM
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
225
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
226 ; bank 5: store CNS
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
227 EEPROM_RR_WRITE 0x500,eeprom_deco_data_bank5,.4 ; 4 byte write to EEPROM
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
228
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
229 ; bank 7: store tissue pressures
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
230 EEPROM_RR_WRITE 0x700,eeprom_deco_data_bank7,.128 ; 128 byte write to EEPROM
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
231
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
232 ; indicate new valid data in vault
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
233 movlw DECO_DATA_VALID_TOKEN ; deco data valid token
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
234 EEPROM_CC_WRITE WREG,eeprom_deco_data_validity ; 1 byte write to EEPROM
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
235
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
236 return ; done
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
237
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
238
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
239 ;=============================================================================
634
4050675965ea 3.10 stable release
heinrichsweikamp
parents: 631
diff changeset
240 rs232 CODE
623
c40025d8e750 3.03 beta released
heinrichsweikamp
parents: 604
diff changeset
241 ;=============================================================================
c40025d8e750 3.03 beta released
heinrichsweikamp
parents: 604
diff changeset
242
634
4050675965ea 3.10 stable release
heinrichsweikamp
parents: 631
diff changeset
243 ;-----------------------------------------------------------------------------
4050675965ea 3.10 stable release
heinrichsweikamp
parents: 631
diff changeset
244 ;
4050675965ea 3.10 stable release
heinrichsweikamp
parents: 631
diff changeset
245 ; RS232 Functions
4050675965ea 3.10 stable release
heinrichsweikamp
parents: 631
diff changeset
246 ;
4050675965ea 3.10 stable release
heinrichsweikamp
parents: 631
diff changeset
247 ;-----------------------------------------------------------------------------
0
heinrichsweikamp
parents:
diff changeset
248
heinrichsweikamp
parents:
diff changeset
249
634
4050675965ea 3.10 stable release
heinrichsweikamp
parents: 631
diff changeset
250 ;-----------------------------------------------------------------------------
4050675965ea 3.10 stable release
heinrichsweikamp
parents: 631
diff changeset
251 ; Switch-On the IR/S8 Port
4050675965ea 3.10 stable release
heinrichsweikamp
parents: 631
diff changeset
252 ;
4050675965ea 3.10 stable release
heinrichsweikamp
parents: 631
diff changeset
253 global enable_ir_s8_analog
4050675965ea 3.10 stable release
heinrichsweikamp
parents: 631
diff changeset
254 enable_ir_s8_analog:
623
c40025d8e750 3.03 beta released
heinrichsweikamp
parents: 604
diff changeset
255 ;initialize serial port2 (TRISG2)
634
4050675965ea 3.10 stable release
heinrichsweikamp
parents: 631
diff changeset
256 btfsc ext_input_s8_ana ; do we have an S8/analog input?
4050675965ea 3.10 stable release
heinrichsweikamp
parents: 631
diff changeset
257 bra enable_s8_analog ; YES - enable S8/analog input
4050675965ea 3.10 stable release
heinrichsweikamp
parents: 631
diff changeset
258 ;bra enable_ir ; NO - enable IR digital input
0
heinrichsweikamp
parents:
diff changeset
259
634
4050675965ea 3.10 stable release
heinrichsweikamp
parents: 631
diff changeset
260 enable_ir:
4050675965ea 3.10 stable release
heinrichsweikamp
parents: 631
diff changeset
261 banksel BAUDCON2 ; select bank for IO register access
4050675965ea 3.10 stable release
heinrichsweikamp
parents: 631
diff changeset
262 movlw b'00100000' ; speed generator configuration: BRG16=0, inverted for IR
4050675965ea 3.10 stable release
heinrichsweikamp
parents: 631
diff changeset
263 movwf BAUDCON2 ; ...
4050675965ea 3.10 stable release
heinrichsweikamp
parents: 631
diff changeset
264 movlw b'00100000' ; TX configuration: BRGH=0, SYNC=0
4050675965ea 3.10 stable release
heinrichsweikamp
parents: 631
diff changeset
265 movwf TXSTA2 ; ...
4050675965ea 3.10 stable release
heinrichsweikamp
parents: 631
diff changeset
266 movlw .102 ; speed configuration: SPBRGH:SPBRG = .102 : 2403 BAUD @ 16 MHz
4050675965ea 3.10 stable release
heinrichsweikamp
parents: 631
diff changeset
267 movwf SPBRG2 ; ...
4050675965ea 3.10 stable release
heinrichsweikamp
parents: 631
diff changeset
268 clrf SPBRGH2 ; ...
4050675965ea 3.10 stable release
heinrichsweikamp
parents: 631
diff changeset
269 movlw b'10010000' ; RX configuration
4050675965ea 3.10 stable release
heinrichsweikamp
parents: 631
diff changeset
270 movwf RCSTA2 ; ...
4050675965ea 3.10 stable release
heinrichsweikamp
parents: 631
diff changeset
271 banksel common ; back to bank common
4050675965ea 3.10 stable release
heinrichsweikamp
parents: 631
diff changeset
272 bsf ir_power ; power-up IR
4050675965ea 3.10 stable release
heinrichsweikamp
parents: 631
diff changeset
273 btfss ir_power ; power-up confirmed?
4050675965ea 3.10 stable release
heinrichsweikamp
parents: 631
diff changeset
274 bra $-6 ; NO - loop and wait
4050675965ea 3.10 stable release
heinrichsweikamp
parents: 631
diff changeset
275 bsf PIE3,RC2IE ; enable RC2 INT
4050675965ea 3.10 stable release
heinrichsweikamp
parents: 631
diff changeset
276 return ; done
4050675965ea 3.10 stable release
heinrichsweikamp
parents: 631
diff changeset
277
4050675965ea 3.10 stable release
heinrichsweikamp
parents: 631
diff changeset
278 enable_s8_analog:
629
237931377539 3.07 stable release
heinrichsweikamp
parents: 628
diff changeset
279 banksel TXSTA2 ; select bank for IO register access
631
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
280 clrf TXSTA2 ; reset UART 2 TX function
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
281 clrf RCSTA2 ; reset UART 2 RX function
623
c40025d8e750 3.03 beta released
heinrichsweikamp
parents: 604
diff changeset
282 banksel common ; back to bank common
631
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
283
634
4050675965ea 3.10 stable release
heinrichsweikamp
parents: 631
diff changeset
284 bsf mcp_power ; power-up instrumentation amp (used by S8 and analog input)
631
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
285 btfss mcp_power ; power-up completed?
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
286 bra $-4 ; NO - loop
113
heinrichsweikamp
parents: 0
diff changeset
287
634
4050675965ea 3.10 stable release
heinrichsweikamp
parents: 631
diff changeset
288 ; branch according to S8 / analog selection
631
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
289 TSTOSS opt_s8_mode ; =0: analog, =1: digital RS232
634
4050675965ea 3.10 stable release
heinrichsweikamp
parents: 631
diff changeset
290 bra enable_analog ; -> analog
631
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
291
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
292 ; configure S8 digital interface
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
293 bcf s8_npower ; power S8 HUD (inverted via P-MOS transistor)
623
c40025d8e750 3.03 beta released
heinrichsweikamp
parents: 604
diff changeset
294 WAITMS d'30' ; NO - wait 30 ms
631
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
295 banksel BAUDCON2 ; select bank for IO register access
634
4050675965ea 3.10 stable release
heinrichsweikamp
parents: 631
diff changeset
296 movlw b'00000000' ; speed generator configuration: BRG16=0, normal for S8
4050675965ea 3.10 stable release
heinrichsweikamp
parents: 631
diff changeset
297 movwf BAUDCON2 ; ...
4050675965ea 3.10 stable release
heinrichsweikamp
parents: 631
diff changeset
298 movlw b'00100000' ; TX configuration: BRGH=0, SYNC=0
4050675965ea 3.10 stable release
heinrichsweikamp
parents: 631
diff changeset
299 movwf TXSTA2 ; ...
4050675965ea 3.10 stable release
heinrichsweikamp
parents: 631
diff changeset
300 movlw .25 ; speed configuration: SPBRGH:SPBRG = .25 : 9615 BAUD @ 16 MHz
4050675965ea 3.10 stable release
heinrichsweikamp
parents: 631
diff changeset
301 movwf SPBRG2 ; ...
4050675965ea 3.10 stable release
heinrichsweikamp
parents: 631
diff changeset
302 movlw b'10010000' ; RX configuration
4050675965ea 3.10 stable release
heinrichsweikamp
parents: 631
diff changeset
303 movwf RCSTA2 ; ...
623
c40025d8e750 3.03 beta released
heinrichsweikamp
parents: 604
diff changeset
304 banksel common ; back to bank common
631
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
305 bsf PIE3,RC2IE ; enable RC2 INT
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 386
diff changeset
306 return
113
heinrichsweikamp
parents: 0
diff changeset
307
634
4050675965ea 3.10 stable release
heinrichsweikamp
parents: 631
diff changeset
308 enable_analog:
631
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
309 ; S8 analog interface
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
310 bcf PIE3,RC2IE ; disable RC2 INT
634
4050675965ea 3.10 stable release
heinrichsweikamp
parents: 631
diff changeset
311 bsf s8_npower ; power-down S8 digital interface
4050675965ea 3.10 stable release
heinrichsweikamp
parents: 631
diff changeset
312 return ; done
631
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
313
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
314
634
4050675965ea 3.10 stable release
heinrichsweikamp
parents: 631
diff changeset
315 ;-----------------------------------------------------------------------------
4050675965ea 3.10 stable release
heinrichsweikamp
parents: 631
diff changeset
316 ; Shut-Down the IR/S8 Port
4050675965ea 3.10 stable release
heinrichsweikamp
parents: 631
diff changeset
317 ;
4050675965ea 3.10 stable release
heinrichsweikamp
parents: 631
diff changeset
318 global disable_ir_s8_analog
4050675965ea 3.10 stable release
heinrichsweikamp
parents: 631
diff changeset
319 disable_ir_s8_analog:
631
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
320 banksel TXSTA2 ; select bank for IO register access
634
4050675965ea 3.10 stable release
heinrichsweikamp
parents: 631
diff changeset
321 clrf TXSTA2 ; shut down TX function
4050675965ea 3.10 stable release
heinrichsweikamp
parents: 631
diff changeset
322 clrf RCSTA2 ; shut down RX function
4050675965ea 3.10 stable release
heinrichsweikamp
parents: 631
diff changeset
323 banksel common ; back to bank common
4050675965ea 3.10 stable release
heinrichsweikamp
parents: 631
diff changeset
324 bcf PIE3,RC2IE ; disable RC2 INT
4050675965ea 3.10 stable release
heinrichsweikamp
parents: 631
diff changeset
325 bcf ir_power ; power down IR receiver
4050675965ea 3.10 stable release
heinrichsweikamp
parents: 631
diff changeset
326 bcf mcp_power ; power-down instrumentation amp
4050675965ea 3.10 stable release
heinrichsweikamp
parents: 631
diff changeset
327 bsf s8_npower ; power-down S8 digital interface
4050675965ea 3.10 stable release
heinrichsweikamp
parents: 631
diff changeset
328 return ; done
4050675965ea 3.10 stable release
heinrichsweikamp
parents: 631
diff changeset
329
4050675965ea 3.10 stable release
heinrichsweikamp
parents: 631
diff changeset
330
4050675965ea 3.10 stable release
heinrichsweikamp
parents: 631
diff changeset
331 ;-----------------------------------------------------------------------------
4050675965ea 3.10 stable release
heinrichsweikamp
parents: 631
diff changeset
332 ; Send Byte in WREG via the IR/S8 Port
4050675965ea 3.10 stable release
heinrichsweikamp
parents: 631
diff changeset
333 ;
4050675965ea 3.10 stable release
heinrichsweikamp
parents: 631
diff changeset
334 global ir_s8_tx_single
4050675965ea 3.10 stable release
heinrichsweikamp
parents: 631
diff changeset
335 ir_s8_tx_single:
4050675965ea 3.10 stable release
heinrichsweikamp
parents: 631
diff changeset
336 banksel TXSTA2 ; UART 2 is outside of the access RAM
4050675965ea 3.10 stable release
heinrichsweikamp
parents: 631
diff changeset
337 movwf TXREG2 ; transmit byte
4050675965ea 3.10 stable release
heinrichsweikamp
parents: 631
diff changeset
338 ir_s8_tx_single_loop:
4050675965ea 3.10 stable release
heinrichsweikamp
parents: 631
diff changeset
339 btfss TXSTA2,TRMT ; TX completed?
4050675965ea 3.10 stable release
heinrichsweikamp
parents: 631
diff changeset
340 bra ir_s8_tx_single_loop ; NO - wait...
4050675965ea 3.10 stable release
heinrichsweikamp
parents: 631
diff changeset
341 banksel common ; YES - back to bank common
631
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
342 return ; - done
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
343
634
4050675965ea 3.10 stable release
heinrichsweikamp
parents: 631
diff changeset
344
631
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
345 ;-----------------------------------------------------------------------------
634
4050675965ea 3.10 stable release
heinrichsweikamp
parents: 631
diff changeset
346 ; Switch-On USB/BT Port
4050675965ea 3.10 stable release
heinrichsweikamp
parents: 631
diff changeset
347 ;
0
heinrichsweikamp
parents:
diff changeset
348 global enable_rs232
heinrichsweikamp
parents:
diff changeset
349 enable_rs232:
623
c40025d8e750 3.03 beta released
heinrichsweikamp
parents: 604
diff changeset
350 call request_speed_normal ; request CPU speed change to normal speed
c40025d8e750 3.03 beta released
heinrichsweikamp
parents: 604
diff changeset
351 enable_rs232_1:
c40025d8e750 3.03 beta released
heinrichsweikamp
parents: 604
diff changeset
352 btfss speed_is_normal ; speed = normal?
631
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
353 bra enable_rs232_1 ; NO - loop waiting for ISR to have adjusted the speed
640
8c1f1f334275 3.13 release
heinrichsweikamp
parents: 634
diff changeset
354 bsf TRISC,7
631
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
355 bcf PORTE,0 ; YES - switch port to comm
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
356 bsf PORTJ,2 ; - /Reset (required for very old OSTC sport)
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
357 movlw b'00100100' ; - TX configuration: TX enabled, async, high speed
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
358 movwf TXSTA1 ; - ...
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
359 movlw b'10010000' ; - RX configuration: port enabled, RX enabled
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
360 movwf RCSTA1 ; - ...
634
4050675965ea 3.10 stable release
heinrichsweikamp
parents: 631
diff changeset
361 IFNDEF _comm_debug
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diff changeset
362 movlw HIGH(.65536-rx_timeout*.32) ; - define TMR5H initialization value for RX timeout (rx_timeout defined in hwos.inc)
4050675965ea 3.10 stable release
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diff changeset
363 ELSE
4050675965ea 3.10 stable release
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diff changeset
364 include "math.inc"
4050675965ea 3.10 stable release
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diff changeset
365 movff opt_comm_timeout,xA+0 ; - get timeout setting in multiples of 10 ms (opt_comm_timeout: 10 .. 200 x 10 ms)
4050675965ea 3.10 stable release
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diff changeset
366 clrf xA+1 ; - ...
4050675965ea 3.10 stable release
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diff changeset
367 MOVLI .320,xB ; - multiply with 10 to get timeout in ms and 32 because tmr5 ticks 32x per ms
4050675965ea 3.10 stable release
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diff changeset
368 call mult16x16 ; - xC = xA * xB = timer ticks to go until timeout
4050675965ea 3.10 stable release
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diff changeset
369 MOVII xC,sub_b ; - multiplication result is max. 64000
4050675965ea 3.10 stable release
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diff changeset
370 MOVLI .65535,sub_a ; - timer wraps around after 65535
4050675965ea 3.10 stable release
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diff changeset
371 call subU16 ; - sub_c = sub_a - sub_b = start value for timer
4050675965ea 3.10 stable release
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diff changeset
372
4050675965ea 3.10 stable release
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diff changeset
373 movlw .244 ; safety maximum value for rx_timeout_tmr5h_load (minimum timeout interval)
4050675965ea 3.10 stable release
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parents: 631
diff changeset
374 cpfslt sub_c+1 ; result > safety value?
4050675965ea 3.10 stable release
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parents: 631
diff changeset
375 movwf sub_c+1 ; YES - revert to safety value
4050675965ea 3.10 stable release
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parents: 631
diff changeset
376
4050675965ea 3.10 stable release
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diff changeset
377 movf sub_c+1,W ; - keep only the upper byte as TMR5H initialization value for RX timeout
4050675965ea 3.10 stable release
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diff changeset
378 ENDIF
4050675965ea 3.10 stable release
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diff changeset
379 movwf rx_timeout_tmr5h_load ; - store for later use
631
185ba2f91f59 3.09 beta 1 release
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diff changeset
380 return ; - done
0
heinrichsweikamp
parents:
diff changeset
381
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 386
diff changeset
382
634
4050675965ea 3.10 stable release
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diff changeset
383 ;-----------------------------------------------------------------------------
4050675965ea 3.10 stable release
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parents: 631
diff changeset
384 ; Shut-Down USB/BT Port
4050675965ea 3.10 stable release
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parents: 631
diff changeset
385 ;
0
heinrichsweikamp
parents:
diff changeset
386 global disable_rs232
heinrichsweikamp
parents:
diff changeset
387 disable_rs232:
631
185ba2f91f59 3.09 beta 1 release
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parents: 629
diff changeset
388 clrf RCSTA1 ; disable RX
185ba2f91f59 3.09 beta 1 release
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diff changeset
389 clrf TXSTA1 ; disable TX
185ba2f91f59 3.09 beta 1 release
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parents: 629
diff changeset
390 bcf PORTC,6 ; switch TX pin hard to GND
634
4050675965ea 3.10 stable release
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diff changeset
391 bsf PORTE,0 ; power down BT chip
631
185ba2f91f59 3.09 beta 1 release
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parents: 629
diff changeset
392 bcf PORTJ,2 ; /Reset (required for very old OSTC sport)
640
8c1f1f334275 3.13 release
heinrichsweikamp
parents: 634
diff changeset
393 bcf TRISC,7
8c1f1f334275 3.13 release
heinrichsweikamp
parents: 634
diff changeset
394 bcf PORTC,7 ; switch RX pin hard to GND
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 386
diff changeset
395 return
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 386
diff changeset
396
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 386
diff changeset
397
634
4050675965ea 3.10 stable release
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diff changeset
398 ;-----------------------------------------------------------------------------
4050675965ea 3.10 stable release
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parents: 631
diff changeset
399 ; Wait for last Byte to be sent out of USB/BT Port
4050675965ea 3.10 stable release
heinrichsweikamp
parents: 631
diff changeset
400 ;
631
185ba2f91f59 3.09 beta 1 release
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parents: 629
diff changeset
401 global rs232_wait_tx ; ++++ do not touch WREG here! ++++
185ba2f91f59 3.09 beta 1 release
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diff changeset
402 rs232_wait_tx:
185ba2f91f59 3.09 beta 1 release
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diff changeset
403 btfss TXSTA1,TRMT ; last byte completely shifted out on TX pin?
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
404 bra rs232_wait_tx ; NO - wait...
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
405 btfss ble_available ; YES - OSTC running with Bluetooth?
185ba2f91f59 3.09 beta 1 release
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parents: 629
diff changeset
406 return ; NO - done
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
407 btfsc NRTS ; YES - Bluetooth module also completed TX?
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
408 bra rs232_wait_tx ; NO - wait...
185ba2f91f59 3.09 beta 1 release
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parents: 629
diff changeset
409 return ; YES - done
623
c40025d8e750 3.03 beta released
heinrichsweikamp
parents: 604
diff changeset
410
c40025d8e750 3.03 beta released
heinrichsweikamp
parents: 604
diff changeset
411
634
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diff changeset
412 ;-----------------------------------------------------------------------------
4050675965ea 3.10 stable release
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parents: 631
diff changeset
413 ; Receive one Byte via the USB/BT Port
4050675965ea 3.10 stable release
heinrichsweikamp
parents: 631
diff changeset
414 ;
4050675965ea 3.10 stable release
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parents: 631
diff changeset
415 ; ++++ make this code as fast as possible! ++++
4050675965ea 3.10 stable release
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diff changeset
416 ; ++++ do not touch WREG here! ++++
4050675965ea 3.10 stable release
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diff changeset
417 ;
4050675965ea 3.10 stable release
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diff changeset
418 global serial_rx_single
4050675965ea 3.10 stable release
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diff changeset
419 serial_rx_single:
631
185ba2f91f59 3.09 beta 1 release
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diff changeset
420 bcf rs232_rx_timeout ; clear timeout flag
634
4050675965ea 3.10 stable release
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parents: 631
diff changeset
421 btfsc PIR1,RCIF ; received a data byte? (bit is set on RX completion and reset on reading RCREG1)
4050675965ea 3.10 stable release
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parents: 631
diff changeset
422 return ; YES - done (fast path)
4050675965ea 3.10 stable release
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diff changeset
423 movff rx_timeout_tmr5h_load,TMR5H ; NO - load TMR5 high with timeout value
631
185ba2f91f59 3.09 beta 1 release
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diff changeset
424 clrf TMR5L ; - load TMR5 low with a zero, writing low starts the timer
185ba2f91f59 3.09 beta 1 release
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diff changeset
425 bcf PIR5,TMR5IF ; - clear timer overflow flag
634
4050675965ea 3.10 stable release
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diff changeset
426 serial_rx_single_loop:
631
185ba2f91f59 3.09 beta 1 release
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parents: 629
diff changeset
427 btfsc PIR1,RCIF ; received a data byte?
634
4050675965ea 3.10 stable release
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diff changeset
428 return ; YES - done
631
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
429 btfss PIR5,TMR5IF ; NO - timer overflow (timeout)?
634
4050675965ea 3.10 stable release
heinrichsweikamp
parents: 631
diff changeset
430 bra serial_rx_single_loop ; NO - continue waiting
4050675965ea 3.10 stable release
heinrichsweikamp
parents: 631
diff changeset
431 ;bra serial_rx_timeout ; YES - timeout
623
c40025d8e750 3.03 beta released
heinrichsweikamp
parents: 604
diff changeset
432
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 386
diff changeset
433
631
185ba2f91f59 3.09 beta 1 release
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diff changeset
434 ;-----------------------------------------------------------------------------
634
4050675965ea 3.10 stable release
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diff changeset
435 ; Helper Function: Timeout in serial_rx_single / serial_tx_steam
4050675965ea 3.10 stable release
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diff changeset
436 ;
4050675965ea 3.10 stable release
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parents: 631
diff changeset
437 serial_rx_timeout:
4050675965ea 3.10 stable release
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parents: 631
diff changeset
438 bsf rs232_rx_timeout ; set timeout flag
4050675965ea 3.10 stable release
heinrichsweikamp
parents: 631
diff changeset
439 bcf RCSTA1,CREN ; clear receiver status: disable RX,
4050675965ea 3.10 stable release
heinrichsweikamp
parents: 631
diff changeset
440 bsf RCSTA1,CREN ; ... enable again RX
4050675965ea 3.10 stable release
heinrichsweikamp
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diff changeset
441 return ; done
4050675965ea 3.10 stable release
heinrichsweikamp
parents: 631
diff changeset
442
623
c40025d8e750 3.03 beta released
heinrichsweikamp
parents: 604
diff changeset
443
634
4050675965ea 3.10 stable release
heinrichsweikamp
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diff changeset
444 ;-----------------------------------------------------------------------------
4050675965ea 3.10 stable release
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parents: 631
diff changeset
445 ; Send and Receive Functions to be used via Macros
4050675965ea 3.10 stable release
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diff changeset
446 ;-----------------------------------------------------------------------------
4050675965ea 3.10 stable release
heinrichsweikamp
parents: 631
diff changeset
447
4050675965ea 3.10 stable release
heinrichsweikamp
parents: 631
diff changeset
448 ;-----------------------------------------------------------------------------
4050675965ea 3.10 stable release
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diff changeset
449 ; Send a Range of 1-256 Bytes from Memory via the USB/BT Port
631
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
450 ;
634
4050675965ea 3.10 stable release
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parents: 631
diff changeset
451 global serial_tx_steam
4050675965ea 3.10 stable release
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diff changeset
452 serial_tx_steam:
631
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
453 movwf eeprom_loop ; initialize loop counter (eeprom variable used here)
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
454 serial_tx_ram_loop:
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
455 rcall rs232_wait_tx ; wait for completion of last transmit
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
456 movff POSTINC2,TXREG1 ; send a byte from memory to serial
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
457 decfsz eeprom_loop,F ; decrement loop counter, became zero?
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
458 bra serial_tx_ram_loop ; NO - loop
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
459 return ; YES - done
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 386
diff changeset
460
623
c40025d8e750 3.03 beta released
heinrichsweikamp
parents: 604
diff changeset
461
634
4050675965ea 3.10 stable release
heinrichsweikamp
parents: 631
diff changeset
462 ;-----------------------------------------------------------------------------
4050675965ea 3.10 stable release
heinrichsweikamp
parents: 631
diff changeset
463 ; Receive a Range of 1-256 Byte via the USB/BT Port and write them to Memory
4050675965ea 3.10 stable release
heinrichsweikamp
parents: 631
diff changeset
464 ; ++++ make this code as fast as possible! ++++
631
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
465 ;
634
4050675965ea 3.10 stable release
heinrichsweikamp
parents: 631
diff changeset
466 global serial_rx_stream
4050675965ea 3.10 stable release
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parents: 631
diff changeset
467 serial_rx_stream:
631
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
468 movwf eeprom_loop ; initialize loop counter (eeprom variable used here)
634
4050675965ea 3.10 stable release
heinrichsweikamp
parents: 631
diff changeset
469 serial_rx_stream_loop:
631
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
470 btfss PIR1,RCIF ; received a data byte? (bit is set on RX complete and reset on reading RCREG1)
634
4050675965ea 3.10 stable release
heinrichsweikamp
parents: 631
diff changeset
471 bra serial_rx_stream_tmr ; NO - enter receive loop with timeout
4050675965ea 3.10 stable release
heinrichsweikamp
parents: 631
diff changeset
472 ;bra serial_rx_stream_received ; YES - copy to memory, tick counter, ...
4050675965ea 3.10 stable release
heinrichsweikamp
parents: 631
diff changeset
473
4050675965ea 3.10 stable release
heinrichsweikamp
parents: 631
diff changeset
474 serial_rx_stream_received:
4050675965ea 3.10 stable release
heinrichsweikamp
parents: 631
diff changeset
475 movff RCREG1,POSTINC2 ; copy received byte to memory
4050675965ea 3.10 stable release
heinrichsweikamp
parents: 631
diff changeset
476 decfsz eeprom_loop,F ; decrement loop counter, became zero?
4050675965ea 3.10 stable release
heinrichsweikamp
parents: 631
diff changeset
477 bra serial_rx_stream_loop ; NO - await next byte
4050675965ea 3.10 stable release
heinrichsweikamp
parents: 631
diff changeset
478 bcf rs232_rx_timeout ; YES - clear timeout flag
4050675965ea 3.10 stable release
heinrichsweikamp
parents: 631
diff changeset
479 return ; - all bytes received, done
4050675965ea 3.10 stable release
heinrichsweikamp
parents: 631
diff changeset
480
4050675965ea 3.10 stable release
heinrichsweikamp
parents: 631
diff changeset
481 serial_rx_stream_tmr:
4050675965ea 3.10 stable release
heinrichsweikamp
parents: 631
diff changeset
482 movff rx_timeout_tmr5h_load,TMR5H ; load TMR5 high with timeout value
4050675965ea 3.10 stable release
heinrichsweikamp
parents: 631
diff changeset
483 clrf TMR5L ; load TMR5 low with a zero, writing to low starts the timer
631
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
484 bcf PIR5,TMR5IF ; clear timer overflow flag
634
4050675965ea 3.10 stable release
heinrichsweikamp
parents: 631
diff changeset
485 serial_rx_stream_tmr_loop:
4050675965ea 3.10 stable release
heinrichsweikamp
parents: 631
diff changeset
486 btfsc PIR1,RCIF ; received a data byte? (bit is set on RX complete and reset on reading RCREG1)
4050675965ea 3.10 stable release
heinrichsweikamp
parents: 631
diff changeset
487 bra serial_rx_stream_received ; YES - copy to memory, tick counter, ...
4050675965ea 3.10 stable release
heinrichsweikamp
parents: 631
diff changeset
488 btfss PIR5,TMR5IF ; NO - timer overflow (timeout)?
4050675965ea 3.10 stable release
heinrichsweikamp
parents: 631
diff changeset
489 bra serial_rx_stream_tmr_loop ; NO - continue waiting
4050675965ea 3.10 stable release
heinrichsweikamp
parents: 631
diff changeset
490 bra serial_rx_timeout ; YES - timeout
623
c40025d8e750 3.03 beta released
heinrichsweikamp
parents: 604
diff changeset
491
631
185ba2f91f59 3.09 beta 1 release
heinrichsweikamp
parents: 629
diff changeset
492 ;-----------------------------------------------------------------------------
634
4050675965ea 3.10 stable release
heinrichsweikamp
parents: 631
diff changeset
493
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 386
diff changeset
494 END