Mercurial > public > hwos_code

annotate src/eeprom_rs232.asm @ 503:4542d03f748a

Find changesets by keywords (author, files, the commit message), revision number or hash, or revset expression.
NEW: Last Dive customviews in surface mode with divetime, depth and interval
author heinrichsweikamp
date Sun, 11 Jun 2017 17:11:40 +0200
parents 3c55627d5f8f
children b455b31ce022
Ignore whitespace changes - Everywhere: Within whitespace: At end of lines:
rev   line source
0
heinrichsweikamp
parents:
diff changeset
1 ;=============================================================================
heinrichsweikamp
parents:
diff changeset
2 ;
heinrichsweikamp
parents:
diff changeset
3 ; File eeprom_rs232.asm
heinrichsweikamp
parents:
diff changeset
4 ;
heinrichsweikamp
parents:
diff changeset
5 ; Internal EEPROM, RS232
heinrichsweikamp
parents:
diff changeset
6 ;
heinrichsweikamp
parents:
diff changeset
7 ; Copyright (c) 2011, JD Gascuel, HeinrichsWeikamp, all right reserved.
heinrichsweikamp
parents:
diff changeset
8 ;=============================================================================
heinrichsweikamp
parents:
diff changeset
9 ; HISTORY
heinrichsweikamp
parents:
diff changeset
10 ; 2011-08-06 : [mH] moving from OSTC code
heinrichsweikamp
parents:
diff changeset
11
275
653a3ab08062 rename into hwOS
heinrichsweikamp
parents: 236
diff changeset
12 #include "hwos.inc"
0
heinrichsweikamp
parents:
diff changeset
13 #include "wait.inc"
heinrichsweikamp
parents:
diff changeset
14
heinrichsweikamp
parents:
diff changeset
15 ;=============================================================================
heinrichsweikamp
parents:
diff changeset
16 eeprom code 0xF00000+0x10
heinrichsweikamp
parents:
diff changeset
17 ; Skip SERIAL number. Should not be overwritten.
heinrichsweikamp
parents:
diff changeset
18 global eeprom_serial_save, eeprom_opt_backup
heinrichsweikamp
parents:
diff changeset
19 eeprom_serial_save res 2
heinrichsweikamp
parents:
diff changeset
20 eeprom_opt_backup res 0x3E
heinrichsweikamp
parents:
diff changeset
21
heinrichsweikamp
parents:
diff changeset
22 ;=============================================================================
heinrichsweikamp
parents:
diff changeset
23 basic CODE
heinrichsweikamp
parents:
diff changeset
24
heinrichsweikamp
parents:
diff changeset
25 global write_int_eeprom_1
heinrichsweikamp
parents:
diff changeset
26 write_int_eeprom_1:
heinrichsweikamp
parents:
diff changeset
27 movwf EEADR
heinrichsweikamp
parents:
diff changeset
28 bra write_eeprom ; writes and "returns" after write
heinrichsweikamp
parents:
diff changeset
29
heinrichsweikamp
parents:
diff changeset
30 global read_int_eeprom_1
heinrichsweikamp
parents:
diff changeset
31 read_int_eeprom_1:
heinrichsweikamp
parents:
diff changeset
32 movwf EEADR
heinrichsweikamp
parents:
diff changeset
33 bra read_eeprom ; reads and "returns" after write
heinrichsweikamp
parents:
diff changeset
34
heinrichsweikamp
parents:
diff changeset
35 ;=============================================================================
heinrichsweikamp
parents:
diff changeset
36 ; reads from internal eeprom
heinrichsweikamp
parents:
diff changeset
37 ; Input: EEADRH:EEADR = EEPROM address.
heinrichsweikamp
parents:
diff changeset
38 ; Output: EEDATA.
heinrichsweikamp
parents:
diff changeset
39 ; Trashed: NONE.
heinrichsweikamp
parents:
diff changeset
40 global read_eeprom
heinrichsweikamp
parents:
diff changeset
41 read_eeprom:
heinrichsweikamp
parents:
diff changeset
42 bcf EECON1,EEPGD
heinrichsweikamp
parents:
diff changeset
43 bcf EECON1,CFGS
heinrichsweikamp
parents:
diff changeset
44 bsf EECON1,RD
heinrichsweikamp
parents:
diff changeset
45 return
heinrichsweikamp
parents:
diff changeset
46
heinrichsweikamp
parents:
diff changeset
47 ;=============================================================================
heinrichsweikamp
parents:
diff changeset
48 ; writes into internal eeprom
heinrichsweikamp
parents:
diff changeset
49 ; Input: EEADRH:EEADR = EEPROM address.
heinrichsweikamp
parents:
diff changeset
50 ; EEDATA = byte to write.
heinrichsweikamp
parents:
diff changeset
51 ; Trashed: WREG.
heinrichsweikamp
parents:
diff changeset
52 global write_eeprom
heinrichsweikamp
parents:
diff changeset
53 write_eeprom:
heinrichsweikamp
parents:
diff changeset
54 bcf EECON1,EEPGD
heinrichsweikamp
parents:
diff changeset
55 bcf EECON1,CFGS
heinrichsweikamp
parents:
diff changeset
56 bsf EECON1,WREN
heinrichsweikamp
parents:
diff changeset
57
133
939f1e83c4c2 BUGFIX: Surface interval was not displayed correctly in some cases
heinrichsweikamp
parents: 113
diff changeset
58 bcf INTCON,GIE ; Disable interrups for the next 5 instructions
0
heinrichsweikamp
parents:
diff changeset
59 movlw 0x55
heinrichsweikamp
parents:
diff changeset
60 movwf EECON2
heinrichsweikamp
parents:
diff changeset
61 movlw 0xAA
heinrichsweikamp
parents:
diff changeset
62 movwf EECON2
heinrichsweikamp
parents:
diff changeset
63 bsf EECON1,WR
heinrichsweikamp
parents:
diff changeset
64 bsf INTCON,GIE ; ...but the flag for the ISR routines were still set, so they will interrupt now!
heinrichsweikamp
parents:
diff changeset
65
heinrichsweikamp
parents:
diff changeset
66 write_eep2:
heinrichsweikamp
parents:
diff changeset
67 btfsc EECON1,WR
heinrichsweikamp
parents:
diff changeset
68 bra write_eep2 ; wait about 4ms...
heinrichsweikamp
parents:
diff changeset
69 bcf EECON1,WREN
heinrichsweikamp
parents:
diff changeset
70 return
heinrichsweikamp
parents:
diff changeset
71
224
5a4801918be9 temporally disable "Copy disable flags from digital input" routine
heinrichsweikamp
parents: 218
diff changeset
72 global disable_ir_s8
5a4801918be9 temporally disable "Copy disable flags from digital input" routine
heinrichsweikamp
parents: 218
diff changeset
73 disable_ir_s8:
0
heinrichsweikamp
parents:
diff changeset
74 banksel TXSTA2
heinrichsweikamp
parents:
diff changeset
75 clrf TXSTA2
heinrichsweikamp
parents:
diff changeset
76 clrf RCSTA2
heinrichsweikamp
parents:
diff changeset
77 banksel common
heinrichsweikamp
parents:
diff changeset
78 bcf ir_power ; IR off
113
heinrichsweikamp
parents: 0
diff changeset
79 bcf mcp_power ; Power-down intrumentation amp
heinrichsweikamp
parents: 0
diff changeset
80 bsf s8_npower ; Power-down S8 HUD
0
heinrichsweikamp
parents:
diff changeset
81 return
heinrichsweikamp
parents:
diff changeset
82
187
669b5d00706d CHANGE: Longer timeout (4 min) for calibration menu
heinrichsweikamp
parents: 151
diff changeset
83 global enable_ir_s8
669b5d00706d CHANGE: Longer timeout (4 min) for calibration menu
heinrichsweikamp
parents: 151
diff changeset
84 enable_ir_s8:
0
heinrichsweikamp
parents:
diff changeset
85 ;init serial port2 (TRISG2)
236
e2ea74646127 configure hardware_flag byte
heinrichsweikamp
parents: 235
diff changeset
86 btfsc analog_o2_input
113
heinrichsweikamp
parents: 0
diff changeset
87 bra enable_s8 ; Start S8
heinrichsweikamp
parents: 0
diff changeset
88
heinrichsweikamp
parents: 0
diff changeset
89 banksel BAUDCON2
heinrichsweikamp
parents: 0
diff changeset
90 movlw b'00100000' ; BRG16=0 ; inverted for IR
heinrichsweikamp
parents: 0
diff changeset
91 movwf BAUDCON2
0
heinrichsweikamp
parents:
diff changeset
92 movlw b'00100000' ; BRGH=0, SYNC=0
heinrichsweikamp
parents:
diff changeset
93 movwf TXSTA2
heinrichsweikamp
parents:
diff changeset
94 movlw .102 ; SPBRGH:SPBRG = .102 : 2403 BAUD @ 16MHz
heinrichsweikamp
parents:
diff changeset
95 movwf SPBRG2
heinrichsweikamp
parents:
diff changeset
96 movlw b'10010000'
heinrichsweikamp
parents:
diff changeset
97 movwf RCSTA2
heinrichsweikamp
parents:
diff changeset
98 banksel common
113
heinrichsweikamp
parents: 0
diff changeset
99 bsf ir_power ; Power-up IR
0
heinrichsweikamp
parents:
diff changeset
100 btfss ir_power
heinrichsweikamp
parents:
diff changeset
101 bra $-6
heinrichsweikamp
parents:
diff changeset
102 return
heinrichsweikamp
parents:
diff changeset
103
113
heinrichsweikamp
parents: 0
diff changeset
104 enable_s8:
heinrichsweikamp
parents: 0
diff changeset
105 ; Check for Digital/Analog
heinrichsweikamp
parents: 0
diff changeset
106 bsf s8_npower ; Power-down S8 HUD
heinrichsweikamp
parents: 0
diff changeset
107 WAITMS d'1' ; Very short delay
heinrichsweikamp
parents: 0
diff changeset
108 bsf mcp_power ; Power-up intrumentation amp
heinrichsweikamp
parents: 0
diff changeset
109 btfss mcp_power
heinrichsweikamp
parents: 0
diff changeset
110 bra $-6
heinrichsweikamp
parents: 0
diff changeset
111 banksel TXSTA2
heinrichsweikamp
parents: 0
diff changeset
112 clrf TXSTA2
heinrichsweikamp
parents: 0
diff changeset
113 clrf RCSTA2
heinrichsweikamp
parents: 0
diff changeset
114 banksel common
heinrichsweikamp
parents: 0
diff changeset
115
heinrichsweikamp
parents: 0
diff changeset
116 ; It may be digital, check for voltage when isolator is powered
heinrichsweikamp
parents: 0
diff changeset
117 bcf s8_npower ; Power S8 HUD
heinrichsweikamp
parents: 0
diff changeset
118 WAITMS d'1' ; Very short delay
heinrichsweikamp
parents: 0
diff changeset
119
heinrichsweikamp
parents: 0
diff changeset
120 btfsc PORTG,2 ; RX2=1?
heinrichsweikamp
parents: 0
diff changeset
121 bra enable_s8_2 ; Yes, digital
heinrichsweikamp
parents: 0
diff changeset
122 WAITMS d'30'
heinrichsweikamp
parents: 0
diff changeset
123 btfsc PORTG,2 ; RX2=1?
heinrichsweikamp
parents: 0
diff changeset
124 bra enable_s8_2 ; Yes, digital
heinrichsweikamp
parents: 0
diff changeset
125
heinrichsweikamp
parents: 0
diff changeset
126 ; Not found, set to analog (fail-safe)
heinrichsweikamp
parents: 0
diff changeset
127
heinrichsweikamp
parents: 0
diff changeset
128 enable_s8_analog:
heinrichsweikamp
parents: 0
diff changeset
129 ; S8 Analog
heinrichsweikamp
parents: 0
diff changeset
130 bsf s8_npower ; Power-down S8 HUD
heinrichsweikamp
parents: 0
diff changeset
131 bcf s8_digital ; Clear flag
heinrichsweikamp
parents: 0
diff changeset
132 return
heinrichsweikamp
parents: 0
diff changeset
133
heinrichsweikamp
parents: 0
diff changeset
134 enable_s8_2: ; S8 Digital
heinrichsweikamp
parents: 0
diff changeset
135 banksel BAUDCON2
heinrichsweikamp
parents: 0
diff changeset
136 movlw b'00000000' ; BRG16=0 ; normal for S8
heinrichsweikamp
parents: 0
diff changeset
137 movwf BAUDCON2
heinrichsweikamp
parents: 0
diff changeset
138 movlw b'00100000' ; BRGH=0, SYNC=0
heinrichsweikamp
parents: 0
diff changeset
139 movwf TXSTA2
heinrichsweikamp
parents: 0
diff changeset
140 movlw .25 ; SPBRGH:SPBRG = .25 : 9615 BAUD @ 16MHz
heinrichsweikamp
parents: 0
diff changeset
141 movwf SPBRG2
heinrichsweikamp
parents: 0
diff changeset
142 movlw b'10010000'
heinrichsweikamp
parents: 0
diff changeset
143 movwf RCSTA2
heinrichsweikamp
parents: 0
diff changeset
144 banksel common
heinrichsweikamp
parents: 0
diff changeset
145 bsf s8_digital ; Set flag
heinrichsweikamp
parents: 0
diff changeset
146 return
heinrichsweikamp
parents: 0
diff changeset
147
0
heinrichsweikamp
parents:
diff changeset
148 ;=============================================================================
heinrichsweikamp
parents:
diff changeset
149 global enable_rs232
heinrichsweikamp
parents:
diff changeset
150 enable_rs232:
heinrichsweikamp
parents:
diff changeset
151 call speed_normal ; 16MHz
heinrichsweikamp
parents:
diff changeset
152 enable_rs232_2:
heinrichsweikamp
parents:
diff changeset
153 movlw T2CON_NORMAL
heinrichsweikamp
parents:
diff changeset
154 cpfseq T2CON
heinrichsweikamp
parents:
diff changeset
155 bra enable_rs232_2 ; Wait until speed is normal
218
8fbd8c5ac51f 1.71beta start
heinrichsweikamp
parents: 209
diff changeset
156 bcf PORTE,0 ; Start comms
0
heinrichsweikamp
parents:
diff changeset
157 ;init serial port1 (TRISC6/7)
heinrichsweikamp
parents:
diff changeset
158 movlw b'00100100' ; BRGH=1, SYNC=0
heinrichsweikamp
parents:
diff changeset
159 movwf TXSTA1
heinrichsweikamp
parents:
diff changeset
160 movlw b'10010000'
heinrichsweikamp
parents:
diff changeset
161 movwf RCSTA1
heinrichsweikamp
parents:
diff changeset
162 return
heinrichsweikamp
parents:
diff changeset
163
heinrichsweikamp
parents:
diff changeset
164 global disable_rs232
heinrichsweikamp
parents:
diff changeset
165 disable_rs232:
heinrichsweikamp
parents:
diff changeset
166 clrf RCSTA1
heinrichsweikamp
parents:
diff changeset
167 clrf TXSTA1 ; UART disable
198
c511dc403d7e (Slightly) reduce current consumption in Eco and sleep mode
heinrichsweikamp
parents: 187
diff changeset
168 bcf PORTC,6 ; TX hard to GND
218
8fbd8c5ac51f 1.71beta start
heinrichsweikamp
parents: 209
diff changeset
169 bsf PORTE,0 ; Stop comms
0
heinrichsweikamp
parents:
diff changeset
170 return
heinrichsweikamp
parents:
diff changeset
171
344
1e342e433839 CHANGE: GF and aGF high range increased to 45-110%
heinrichsweikamp
parents: 276
diff changeset
172
0
heinrichsweikamp
parents:
diff changeset
173 global rs232_wait_tx
heinrichsweikamp
parents:
diff changeset
174 rs232_wait_tx:
113
heinrichsweikamp
parents: 0
diff changeset
175 btfss TXSTA1,TRMT ; RS232 Busy?
0
heinrichsweikamp
parents:
diff changeset
176 bra rs232_wait_tx ; yes, wait...
344
1e342e433839 CHANGE: GF and aGF high range increased to 45-110%
heinrichsweikamp
parents: 276
diff changeset
177
1e342e433839 CHANGE: GF and aGF high range increased to 45-110%
heinrichsweikamp
parents: 276
diff changeset
178 btfss ble_available ; ble available?
1e342e433839 CHANGE: GF and aGF high range increased to 45-110%
heinrichsweikamp
parents: 276
diff changeset
179 return ; No, done.
350
2fd258596af0 some cleanups
heinrichsweikamp
parents: 344
diff changeset
180
344
1e342e433839 CHANGE: GF and aGF high range increased to 45-110%
heinrichsweikamp
parents: 276
diff changeset
181 btfsc NRTS ; Wait for Bluetooth module
350
2fd258596af0 some cleanups
heinrichsweikamp
parents: 344
diff changeset
182 bra rs232_wait_tx ; yes, wait...
0
heinrichsweikamp
parents:
diff changeset
183 return ; Done.
heinrichsweikamp
parents:
diff changeset
184
113
heinrichsweikamp
parents: 0
diff changeset
185 global rs232_wait_tx2
heinrichsweikamp
parents: 0
diff changeset
186 rs232_wait_tx2:
heinrichsweikamp
parents: 0
diff changeset
187 banksel TXSTA2
209
56276a2418f9 cleanup
heinrichsweikamp
parents: 204
diff changeset
188 rs232_wait_tx2_1:
113
heinrichsweikamp
parents: 0
diff changeset
189 btfss TXSTA2,TRMT ; RS232 Busy?
209
56276a2418f9 cleanup
heinrichsweikamp
parents: 204
diff changeset
190 bra rs232_wait_tx2_1 ; yes, wait...
113
heinrichsweikamp
parents: 0
diff changeset
191 banksel common
heinrichsweikamp
parents: 0
diff changeset
192 return ; Done.
heinrichsweikamp
parents: 0
diff changeset
193
0
heinrichsweikamp
parents:
diff changeset
194 global rs232_get_byte
heinrichsweikamp
parents:
diff changeset
195 rs232_get_byte:
heinrichsweikamp
parents:
diff changeset
196 bcf rs232_recieve_overflow ; clear flag
378
7faa688db105 BUGFIX: BLE timings for MAC issues
heinrichsweikamp
parents: 350
diff changeset
197 movlw .10
7faa688db105 BUGFIX: BLE timings for MAC issues
heinrichsweikamp
parents: 350
diff changeset
198 movwf uart1_temp
0
heinrichsweikamp
parents:
diff changeset
199 clrf uart2_temp
378
7faa688db105 BUGFIX: BLE timings for MAC issues
heinrichsweikamp
parents: 350
diff changeset
200 clrf uart3_temp
0
heinrichsweikamp
parents:
diff changeset
201 rs232_get_byte2:
heinrichsweikamp
parents:
diff changeset
202 btfsc PIR1,RCIF ; data arrived?
386
3c55627d5f8f some cleanups, jump to 1.90 stable
heinrichsweikamp
parents: 378
diff changeset
203 return ; Yes
378
7faa688db105 BUGFIX: BLE timings for MAC issues
heinrichsweikamp
parents: 350
diff changeset
204 decfsz uart3_temp,F
7faa688db105 BUGFIX: BLE timings for MAC issues
heinrichsweikamp
parents: 350
diff changeset
205 bra rs232_get_byte2
0
heinrichsweikamp
parents:
diff changeset
206 decfsz uart2_temp,F
378
7faa688db105 BUGFIX: BLE timings for MAC issues
heinrichsweikamp
parents: 350
diff changeset
207 bra rs232_get_byte2
0
heinrichsweikamp
parents:
diff changeset
208 decfsz uart1_temp,F
heinrichsweikamp
parents:
diff changeset
209 bra rs232_get_byte2
386
3c55627d5f8f some cleanups, jump to 1.90 stable
heinrichsweikamp
parents: 378
diff changeset
210 ; timeout occoured (about 400ms)
0
heinrichsweikamp
parents:
diff changeset
211 bsf rs232_recieve_overflow ; set flag
378
7faa688db105 BUGFIX: BLE timings for MAC issues
heinrichsweikamp
parents: 350
diff changeset
212 rs232_get_byte3:
0
heinrichsweikamp
parents:
diff changeset
213 bcf RCSTA1,CREN ; Clear receiver status
heinrichsweikamp
parents:
diff changeset
214 bsf RCSTA1,CREN
heinrichsweikamp
parents:
diff changeset
215 return ; and return anyway
heinrichsweikamp
parents:
diff changeset
216
heinrichsweikamp
parents:
diff changeset
217 END