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annotate src/rtc.asm @ 565:0ba88db66492

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CHANGE: Limit button sensitivity to 80%
author heinrichsweikamp
date Tue, 06 Feb 2018 10:07:38 +0100
parents b7eb98dbd800
children b455b31ce022
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1 ;=============================================================================
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2 ;
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3 ; File rtc.asm
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4 ;
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5 ;
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6 ; Copyright (c) 2011, JD Gascuel, HeinrichsWeikamp, all right reserved.
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7 ;=============================================================================
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8 ; HISTORY
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9 ; 2011-08-08 : [mH] moving from OSTC code
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10
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653a3ab08062 rename into hwOS
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11 #include "hwos.inc"
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12 #include "math.inc"
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13
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14 sensors CODE
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15
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16 global rtc_init
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17 rtc_init:
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18 movlw .1
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19 movwf secs
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20 movlw .59
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21 movwf mins
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22 movlw .12
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23 movwf hours
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b7eb98dbd800 bump to 2.96beta (REFACTORED VERSION)
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24 movlw .2
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25 movwf day
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b7eb98dbd800 bump to 2.96beta (REFACTORED VERSION)
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26 movlw .12
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27 movwf month
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8dfb93e80338 NEW: Deep Sleep mode for OSTC Plus and OSTC 2 (2017) (Entered automatically)
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28 movlw .17
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29 movwf year
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2c58631d5229 minor cleanups
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30 ; rcall rtc_set_rtc ; writes mins,sec,hours,day,month and year to rtc module
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31 ; return
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32
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33 global rtc_set_rtc
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34 rtc_set_rtc:
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35 banksel 0xF16 ; Addresses, F16h through F5Fh, are also used by SFRs, but are not part of the Access RAM.
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36 movlw 0x55
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37 movwf EECON2
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38 movlw 0xAA
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39 movwf EECON2
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40 bsf RTCCFG,RTCWREN ; Unlock sequence for RTCWREN
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41 bsf RTCCFG,RTCPTR1
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42 bsf RTCCFG,RTCPTR0 ; year
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43 movff year,WREG
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44 rcall rtc_dec2bcd ; IN: temp1 in WREG, OUT: WREG in BCD, also sets to bank16h!
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45 movwf RTCVALL ; year
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46 movwf RTCVALH ; dummy write
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47 movff day,WREG
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48 rcall rtc_dec2bcd ; IN: temp1 in WREG, OUT: WREG in BCD, also sets to bank16h!
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49 movwf RTCVALL ;day
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50 movff month,WREG
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51 rcall rtc_dec2bcd ; IN: temp1 in WREG, OUT: WREG in BCD, also sets to bank16h!
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52 movwf RTCVALH ;month
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53 movff hours,WREG
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54 rcall rtc_dec2bcd ; IN: temp1 in WREG, OUT: WREG in BCD, also sets to bank16h!
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55 movwf RTCVALL ;hours
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56 movlw d'0'
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57 rcall rtc_dec2bcd ; IN: temp1 in WREG, OUT: WREG in BCD, also sets to bank16h!
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58 movwf RTCVALH ;weekday
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59 movff secs,WREG
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60 rcall rtc_dec2bcd ; IN: temp1 in WREG, OUT: WREG in BCD, also sets to bank16h!
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61 movwf RTCVALL ;secs
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62 movff mins,WREG
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63 rcall rtc_dec2bcd ; IN: temp1 in WREG, OUT: WREG in BCD, also sets to bank16h!
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64 movwf RTCVALH ;minutes
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65 movlw 0x55
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66 movwf EECON2
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67 movlw 0xAA
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68 movwf EECON2
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69 bcf RTCCFG,RTCWREN ; Lock sequence for RTCWREN
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70 banksel common
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71 return
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72
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73 rtc_dec2bcd:
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74 banksel temp1
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75 movwf temp1 ; Input in dec
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76 setf temp2 ; 10s
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77
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78 rtc_dec2bcd2:
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79 incf temp2,F ; Count 10's
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80 movlw d'10'
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81 subwf temp1,F
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82 btfss STATUS,N
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83 bra rtc_dec2bcd2
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84 movlw d'10'
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85 addwf temp1,F ; 1s
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86 swapf temp2,W ; swap to bit 7-4 -> WREG
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87 addwf temp1,W ; Result in BCD
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88 banksel 0xF16 ; Addresses, F16h through F5Fh, are also used by SFRs, but are not part of the Access RAM.
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89 return
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90
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91 END