Mercurial > public > hwos_code
annotate src/hwos.asm @ 645:070528a88715
3.16 release
| author | heinrichsweikamp |
|---|---|
| date | Sun, 07 Nov 2021 12:39:23 +0100 |
| parents | 7d8a4c60ec1a |
| children | ef2ed7e3a895 |
| rev | line source |
|---|---|
| 0 | 1 ;============================================================================= |
| 2 ; | |
| 634 | 3 ; File hwos.asm * combined next generation V3.09.4e |
| 0 | 4 ; |
| 275 | 5 ; Definition of the hwOS dive computer platform. |
| 0 | 6 ; |
| 7 ; Copyright (c) 2011, JD Gascuel, HeinrichsWeikamp, all right reserved. | |
| 8 ;============================================================================= | |
| 9 ; HISTORY | |
| 604 | 10 ; 2011-05-24 : [jDG] Cleanups from initial Matthias code |
| 11 ; 2011-06-24 : [MH] Added clock speeds | |
| 12 | |
| 623 | 13 ;============================================================================= |
| 14 | |
| 634 | 15 #DEFINE INSIDE_HWOS_ASM |
| 604 | 16 |
| 275 | 17 #include "hwos.inc" |
| 623 | 18 #include "eeprom_rs232.inc" |
| 0 | 19 |
| 634 | 20 ;----------------------------- PIC Configuration ----------------------------- |
| 21 ; | |
| 22 CONFIG RETEN = OFF ; regulator power while in sleep mode controlled by SRETEN bit | |
| 23 CONFIG SOSCSEL = HIGH ; high power SOSC circuit selected | |
| 24 CONFIG XINST = OFF ; extended instruction set disabled | |
| 623 | 25 CONFIG FOSC = INTIO2 ; internal RC oscillator, no clock-out |
| 634 | 26 CONFIG PLLCFG = OFF ; oscillator used directly |
| 27 CONFIG IESO = OFF ; two-speed start-up disabled | |
| 28 CONFIG PWRTEN = OFF ; power-up timer disabled, because incompatible with ICD3 (Ri-400) | |
| 29 CONFIG BOREN = ON ; brown-out reset controlled with SBOREN bit | |
| 30 CONFIG BORV = 2 ; brown-out reset voltage 2.0V | |
| 31 CONFIG BORPWR = MEDIUM ; brown-out monitoring set to medium power level | |
| 32 CONFIG WDTEN = ON ; watchdog timer enabled, controlled by SWDTEN bit | |
| 33 CONFIG WDTPS = 128 ; watchdog timer post-scaler 1:128 | |
| 34 CONFIG RTCOSC = SOSCREF ; RTCC uses SOSC as ref clock | |
| 35 CONFIG MCLRE = ON ; MCLR enabled, RG5 disabled | |
| 36 CONFIG CCP2MX = PORTBE ; ECCP2 muxed with RE7 (micro-controller mode) /RB3 (other modes) | |
| 623 | 37 |
| 38 | |
| 39 ;---------------------------- Bank0 ACCESS RAM ------------------------------- | |
| 634 | 40 ; |
| 623 | 41 ac_ram equ 0x000 |
| 42 ac_ram udata_acs ac_ram ; access RAM data | |
| 43 | |
| 44 | |
| 45 ;---- Flags - Hardware Descriptors | |
| 46 HW_descriptor res 1 ; OSTC - model descriptor (cleared & rebuilt in restart) | |
| 643 | 47 HW_variants res 1 ; OSTC - model variants (NOT cleared in restart) |
| 48 HW_variants2 res 1 ; OSTC - more model variants (NOT cleared in restart) | |
| 49 | |
| 623 | 50 ;---- Flags - Hardware States |
| 628 | 51 HW_flags_state1 res 1 ; hardware - states 1 |
| 52 HW_flags_state2 res 1 ; hardware - states 2 | |
| 643 | 53 HW_flags_state3 res 1 ; hardware - states 3 |
| 623 | 54 |
| 55 ;--- Flags - Operating System | |
| 56 OS_flags_persist res 1 ; system - persistent settings (NOT cleared in restart) | |
| 57 OS_flags_ISR1 res 1 ; system - ISR control 1 | |
| 58 OS_flags_ISR2 res 1 ; system - ISR control 2 | |
| 59 | |
| 60 ;---- Flags - Operating Modes | |
| 61 OM_flags_mode res 1 ; operating modes | |
| 62 | |
| 63 ;---- Flags - Dive Modes | |
| 64 DM_flags_deco res 1 ; dive mode - main dive & deco mode | |
| 65 | |
| 66 ;---- CPU Speed | |
| 67 cpu_speed_request res 1 ; requested CPU speed: =1: eco, =2: normal, =3: fastest | |
| 68 cpu_speed_state res 1 ; current CPU speed: =1: eco, =2: normal, =3: fastest | |
| 69 | |
| 70 ;---- Timebase & Eventbase | |
| 71 timebase res 1 ; timed trigger flags and running timebase | |
| 72 eventbase res 1 ; event trigger flags | |
| 73 | |
| 74 ;---- Timeout-Timer Service | |
| 75 isr_timeout_timer res 1 ; timeout timer | |
| 76 isr_timeout_reload res 1 ; timeout reload value | |
| 77 | |
| 78 ;---- Dive Times | |
| 79 total_divetime_secs res 2 ; total dive time, seconds | |
| 80 counted_divetime_mins res 2 ; counted dive time, minutes | Attention: do not change the position of | |
| 81 counted_divetime_secs res 1 ; counted dive time, seconds | these 2 Variables relative to each other! | |
| 604 | 82 |
| 623 | 83 ;---- Dive Times / Apnoe |
| 84 apnoe_surface_mins res 1 ; surface time minutes | Attention: do not change the position of | |
| 85 apnoe_surface_secs res 1 ; surface time seconds | these 2 Variables relative to each other! | |
| 86 | |
| 87 apnoe_dive_mins res 1 ; dive time minutes | Attention: do not change the position of | |
| 88 apnoe_dive_secs res 1 ; dive time seconds | these 2 Variables relative to each other! | |
| 89 | |
| 90 ;---- Profile Recording | |
| 91 sampling_rate res 1 ; configured sampling rate | |
| 92 sampling_timer res 1 ; sampling timer | |
| 93 | |
| 94 ;---- Simulator Mode | |
| 95 simulatormode_depth res 1 ; depth in simulator mode | |
| 96 | |
| 97 ;---- HUD / Sensor Data | |
| 98 hud_status_byte res 1 ; HUD status byte, see definition of flags | Attention: keep relative position | |
| 99 hud_battery_mv res 2 ; hud/ppo2 monitor battery voltage in mV | between these two variables! | |
| 100 | |
| 634 | 101 ;---- Battery Management |
| 102 battery_capacity_internal res 2 ; for internal battery gauging | |
| 103 battery_capacity res 2 ; for battery gauge IC | |
| 104 battery_offset res 2 ; for battery gauge IC | |
| 105 battery_type res 1 ; =0:1.5V, =1:3.6V Saft, =2:LiIon 3.7V/0.8Ah, =3:LiIon 3.7V/3.1Ah, =4: LiIon 3.7V/2.3Ah | |
| 106 battery_accumulated_charge res 2 ; raw values in battery gauge IC | |
| 107 battery_temperature res 2 ; battery temperature in 0.1 Kelvin | |
| 108 gauge_status_byte res 1 ; gauge IC status byte | |
| 623 | 109 |
| 634 | 110 |
| 111 | |
| 643 | 112 ; 44 byte user data |
| 623 | 113 ; 32 byte tmp data placed by C compiler |
| 114 ; 20 byte variables placed by math library | |
| 115 ; == | |
| 643 | 116 ; 96 byte used, 0 byte free (96 byte total available) |
| 623 | 117 |
| 631 | 118 |
| 623 | 119 global HW_descriptor |
| 120 global HW_variants | |
| 643 | 121 global HW_variants2 |
| 628 | 122 global HW_flags_state1 |
| 123 global HW_flags_state2 | |
| 643 | 124 global HW_flags_state3 |
| 623 | 125 global OS_flags_persist |
| 126 global OS_flags_ISR1 | |
| 127 global OS_flags_ISR2 | |
| 128 global OM_flags_mode | |
| 129 global DM_flags_deco | |
| 130 global cpu_speed_request | |
| 131 global cpu_speed_state | |
| 132 global timebase | |
| 133 global eventbase | |
| 134 global isr_timeout_timer | |
| 135 global isr_timeout_reload | |
| 136 global total_divetime_secs | |
| 137 global counted_divetime_mins | |
| 138 global counted_divetime_secs | |
| 139 global apnoe_surface_secs | |
| 140 global apnoe_surface_mins | |
| 141 global apnoe_dive_secs | |
| 142 global apnoe_dive_mins | |
| 143 global sampling_rate | |
| 144 global sampling_timer | |
| 145 global simulatormode_depth | |
| 146 global hud_status_byte | |
| 147 global hud_battery_mv | |
| 634 | 148 global battery_capacity_internal |
| 149 global battery_capacity | |
| 150 global battery_offset | |
| 151 global battery_type | |
| 152 global battery_accumulated_charge | |
| 153 global battery_temperature | |
| 154 global gauge_status_byte | |
| 155 | |
| 156 | |
| 157 ;============================================================================= | |
| 158 hwos1 CODE | |
| 159 ;============================================================================= | |
| 623 | 160 |
| 161 ;----------------------------------------------------------------------------- | |
| 634 | 162 ; Master Initialization of Hardware Resources |
| 163 ; | |
| 604 | 164 global init_ostc |
| 275 | 165 init_ostc: |
| 623 | 166 |
| 167 ; Oscillator | |
| 168 banksel common ; select bank common | |
| 634 | 169 movlw b'01110010' ; select 16 MHz INTOSC |
| 170 movwf OSCCON ; ... | |
| 171 movlw b'00001000' ; secondary oscillator running | |
| 172 movwf OSCCON2 ; ... | |
| 173 movlw b'00000000' ; 4x PLL disable (Bit 6) - only works with 8 or 16MHz (=32 or 64MHz) | |
| 174 movwf OSCTUNE ; ... | |
| 608 | 175 |
| 623 | 176 movlw coding_speed_normal ; coding for normal CPU speed |
| 177 movwf cpu_speed_request ; store CPU shall run with normal speed | |
| 178 movwf cpu_speed_state ; store CPU does run with normal speed | |
| 608 | 179 |
|
642
a9a0188091e4
fix rare upgrade issue with OSTC sport 2019 hardware
heinrichsweikamp
parents:
640
diff
changeset
|
180 ;bcf RCON,SBOREN ; brown-out off (not needed here, is handled in bootloader) |
| 604 | 181 bcf RCON,IPEN ; priority interrupts off |
| 608 | 182 |
| 604 | 183 banksel WDTCON |
| 645 | 184 movlw b'00010000' ; setup watchdog, put VCORE Reg into Ultra Low-Power mode in Sleep |
| 634 | 185 movwf WDTCON ; ... |
| 0 | 186 |
| 608 | 187 |
| 0 | 188 ; I/O Ports |
| 634 | 189 banksel 0xF16 ; addresses F16h ... F5Fh are not part of the access RAM |
| 190 | |
| 604 | 191 clrf REFOCON ; no reference oscillator active on REFO pin |
| 192 clrf ODCON1 ; disable open drain capability | |
| 193 clrf ODCON2 ; disable open drain capability | |
| 194 clrf ODCON3 ; disable open drain capability | |
| 634 | 195 clrf CM1CON ; disable comparator 1 |
| 196 clrf CM2CON ; disable comparator 2 | |
| 197 clrf CM3CON ; disable comparator 3 | |
| 0 | 198 |
| 634 | 199 movlw b'11000000' ; ANSEL0: AN7, AN6 -> analog inputs, PORTA is digital |
| 200 movwf ANCON0 ; ... | |
| 201 movlw b'00000111' ; ANSEL1: AN8, AN9, AN10 -> analog input | |
| 202 movwf ANCON1 ; ... | |
| 640 | 203 clrf ANCON2 |
| 634 | 204 |
| 205 banksel common ; back to bank common | |
| 0 | 206 |
| 604 | 207 ; movlw b'00000000' ; 1= input -> Data TFT_high |
| 634 | 208 clrf TRISA ; ... |
| 604 | 209 ; movlw b'00000000' ; init port |
| 634 | 210 clrf PORTA ; ... |
| 0 | 211 |
| 604 | 212 movlw b'00000011' ; 1= input, (RB0, RB1) -> switches, RB2 -> Power_MCP, RB3 -> s8_npower, RB4 -> LED_green/rx_nreset, RB5 -> /TFT_POWER |
| 634 | 213 movwf TRISB ; ... |
| 604 | 214 movlw b'00111000' ; init port, rx_nreset=1 -> hard reset RX |
| 634 | 215 movwf PORTB ; ... |
| 0 | 216 |
| 604 | 217 movlw b'10011010' ; 1= input, (RC0, RC1) -> SOSC, RC2 -> TFT_LED_PWM, (RC3,RC4) -> I²C, RC5 -> MOSI_MS5541, (RC6, RC7) -> UART1 |
| 634 | 218 movwf TRISC ; ... |
| 604 | 219 ; movlw b'00000000' ; init port |
| 634 | 220 clrf PORTC ; ... |
| 0 | 221 |
| 604 | 222 movlw b'00100000' ; 1= input, RD0 -> TFT_NCS, RD1 -> TFT_RS, RD2 -> TFT_NWR, RD3 -> TFT_RD, RD4 -> MOSI_Flash, RD5 -> MISO_Flash, RD6 -> CLK_Flash, RD7 -> TFT_NRESET |
| 634 | 223 movwf TRISD ; ... |
| 604 | 224 ; movlw b'00000000' ; init port |
| 634 | 225 clrf PORTD ; ... |
| 0 | 226 |
| 628 | 227 movlw b'00100000' ; 1= input, RE0 -> not_Power_BLE, RE1 -> Power_IR, RE2 -> CS_MCP, RE3 -> LED_blue, RE4 -> power_sw1, RE5 -> leave as input |
| 634 | 228 movwf TRISE ; ... |
| 627 | 229 movlw b'00010001' ; init port |
| 634 | 230 movwf PORTE ; ... |
| 0 | 231 |
| 604 | 232 movlw b'01111110' ; 1= input, (RF1, RF2, RF3, RF4, RF5) -> Analog |
| 634 | 233 movwf TRISF ; ... |
| 604 | 234 ; movlw b'00000000' ; init port |
| 634 | 235 clrf PORTF ; ... |
| 0 | 236 |
| 640 | 237 movlw b'00000110' ; 1= input, <7:6> not implemented, RG0 -> TX3_PIEZO_CFG, , RG1 -> TX2, RG2 -> RX2, RG3 -> AN17_RSSI, RG4 -> SOSC_OUT, RG5 -> /RESET |
| 634 | 238 movwf TRISG ; ... |
| 604 | 239 movlw b'00000001' ; init port |
| 634 | 240 movwf PORTG ; ... |
| 0 | 241 |
| 604 | 242 ; movlw b'00000000' ; 1= input -> Data TFT_low |
| 634 | 243 clrf TRISH ; ... |
| 604 | 244 ; movlw b'00000000' ; init port |
| 634 | 245 clrf PORTH ; ... |
| 0 | 246 |
| 623 | 247 movlw b'10011011' ; 1= input, RJ4 -> vusb_in, RJ5 -> power_sw2, RJ6 -> CLK_MS5541, RJ7 -> MISO_MS5541 |
| 634 | 248 movwf TRISJ ; ... |
| 604 | 249 movlw b'00100000' ; init port |
| 634 | 250 movwf PORTJ ; ... |
| 0 | 251 |
| 623 | 252 |
| 618 | 253 ; disable Charger by default |
| 623 | 254 bsf charge_disable ; set charging-inhibit signal |
| 255 bcf charge_enable ; activate charging-inhibit signal | |
| 256 | |
| 257 | |
| 634 | 258 ; Timer 7 for 62.5 ms Interrupt (Sensor States) |
| 259 banksel 0xF16 ; addresses F16h...F5Fh are not part of the access RAM | |
| 260 clrf T7GCON ; clear timer 7 gate control register | |
| 261 movlw b'10001101' ; bit 7-6: 10 = clock source SOSC/SCLKI (with bit 3 = 1) | |
| 262 ; bit 5-4: 00 = 1:1 prescaler | |
| 263 ; bit 3: 1 = clock source SOSC/SCLKI (with bit 7-6 = 10) | |
| 264 ; bit 2: 1 = DO NOT synchronize external clock input (else OSTC won't wake up from sleep!) | |
| 265 ; bit 1: 0 = 2x 8 bit operation | |
| 266 ; bit 0: 1 = timer enabled | |
| 267 ; 32768 Hz clock source, 1:1 prescaler -> timer counts at 30.51757813 µs/bit | |
| 268 movwf T7CON ; ... | |
| 269 movlw .248 ; load timer 7, high byte (8x256 ticks -> 62.5 ms) | |
| 270 movwf TMR7H ; ... | |
| 271 clrf TMR7L ; load timer 7, low byte | |
| 0 | 272 |
| 623 | 273 |
| 634 | 274 ; Timer 0 - not used |
| 275 movlw b'00000001' ; timer0 stopped (1:4 prescaler) | |
| 276 movwf T0CON ; ... | |
| 277 | |
| 278 | |
| 279 ; Timer 1 - Button hold-down Timer | |
| 280 ; movlw b'10001100' ; old setting | |
| 281 movlw b'10001010' ; bit 7-6: 10 = clock source SOSC/SCLKI (with bit 3 = 1) | |
| 282 ; bit 5-4: 00 = 1:1 prescaler | |
| 283 ; bit 3: 1 = clock source SOSC/SCLKI (with bit 7-6 = 10) | |
| 284 ; bit 2: 0 = synchronize external clock input | |
| 285 ; bit 1: 1 = 16 bit operation | |
| 286 ; bit 0: 0 = timer stopped | |
| 287 ; 32768 Hz clock source, 1:1 prescaler -> timer counts at 30.51757813 µs/bit | |
| 288 movwf T1CON ; ... | |
| 0 | 289 |
| 623 | 290 |
| 0 | 291 ; RTCC |
| 623 | 292 banksel 0xF16 ; addresses, F16h through F5Fh, are also used by SFRs, but are not part of the access RAM |
| 634 | 293 movlw 0x55 ; unlock sequence for RTCWREN |
| 294 movwf EECON2 ; ... | |
| 295 movlw 0xAA ; ... | |
| 296 movwf EECON2 ; ... | |
| 297 bsf RTCCFG,RTCWREN ; unlock access to RTC | |
| 298 bsf RTCCFG,RTCPTR1 ; set pointer register to b'11' | |
| 299 bsf RTCCFG,RTCPTR0 ; .. | |
| 623 | 300 bsf RTCCFG,RTCEN ; module enable |
| 301 bsf RTCCFG,RTCOE ; output enable | |
| 302 movlw b'00000100' ; 32768 Hz SOCS on RTCC pin (PORTG,4) Bit7-5: pull-ups for Port D, E and J | |
| 634 | 303 movwf PADCFG1 ; ... |
| 304 movlw b'11000000' ; 1/2 second alarm | |
| 305 movwf ALRMCFG ; ... | |
| 306 movlw d'1' ; select alarm repeat counter to 1 | |
| 307 movwf ALRMRPT ; ... | |
| 308 movlw 0x55 ; unlock sequence for RTCWREN | |
| 309 movwf EECON2 ; ... | |
| 310 movlw 0xAA ; ... | |
| 311 movwf EECON2 ; ... | |
| 312 bcf RTCCFG,RTCWREN ; lock access to RTC | |
| 313 banksel common ; back to bank common | |
| 623 | 314 |
| 614 | 315 |
| 0 | 316 ; A/D Converter |
| 317 movlw b'00011000' ; power off ADC, select AN6 | |
| 634 | 318 movwf ADCON0 ; ... |
| 0 | 319 movlw b'00100000' ; 2.048V Vref+ |
| 634 | 320 movwf ADCON1 ; ... |
| 640 | 321 movlw b'10001111' ; right aligned, 2 x T_AD acquisition time, clock derived from A/D RC oscillator (To be CPU-clock independent) |
| 634 | 322 movwf ADCON2 ; ... |
| 0 | 323 |
| 623 | 324 |
| 634 | 325 ; Serial Port 1 (TRISC6/7) |
| 631 | 326 movlw b'00001000' ; switch baud generator to 16 bit mode (BRG16=1) |
| 327 movwf BAUDCON1 ; ... | |
| 328 ; SPBRGH:SPBRG = .34 : 114285 BAUD @ 16MHz (+0.79% error at 115200 baud) | |
| 329 ; SPBRGH:SPBRG = .207 : 19230 BAUD @ 16MHz (-0.16% error at 19200 baud) | |
| 330 movlw .34 ; select 114285 baud (low byte) | |
| 331 movwf SPBRG1 ; ... | |
| 332 clrf SPBRGH1 ; ... (high byte) | |
| 204 | 333 |
| 631 | 334 clrf RCSTA1 ; disable UART RX |
| 335 clrf TXSTA1 ; disable UART TX | |
| 336 bcf PORTC,6 ; tie TX output hard to GND | |
| 0 | 337 |
| 623 | 338 |
| 634 | 339 ; Serial Port 2 (TRISG2) for IR/S8 digital Interface |
| 623 | 340 ; |
| 341 ; - will be initialized by enable_ir_s8 (eeprom_rs232.asm) in case IR/S8 shall be available | |
| 342 | |
| 0 | 343 |
| 623 | 344 ; Timer 3 for IR-RX Timeout |
| 345 IFDEF _external_sensor | |
| 634 | 346 clrf T3GCON ; clear Timer3 gate control register |
| 347 ; movlw b'10001101' ; old value | |
| 348 movlw b'10001011' ; bit 7-6: 10 = clock source SOSC/SCLKI (with bit 3 = 1) | |
| 349 ; bit 5-4: 00 = 1:1 prescaler | |
| 350 ; bit 3: 1 = clock source SOSC/SCLKI (with bit 7-6 = 10) | |
| 351 ; bit 2: 0 = synchronize external clock input | |
| 352 ; bit 1: 1 = 16 bit operation | |
| 353 ; bit 0: 1 = timer enabled | |
| 354 ; 32768 Hz clock source, 1:1 prescaler -> timer counts at 30.51757813 µs/bit | |
| 355 movwf T3CON ; ... | |
| 623 | 356 ENDIF |
| 357 | |
| 0 | 358 |
| 359 ; SPI Module(s) | |
| 360 ; SPI2: External Flash | |
| 634 | 361 movlw b'00110000' ; set up SPI module |
| 362 movwf SSP2CON1 ; ... | |
| 363 clrf SSP2STAT ; ... | |
| 364 ; resulting bit clocks: 0.25 MHz @ 1 MHz CPU clock (Eco) | |
| 365 ; 4.00 MHz @ 16 MHz CPU clock (Normal) | |
| 366 ; 16.00 MHz @ 64 MHz CPU clock (Fastest) | |
| 623 | 367 |
| 0 | 368 |
| 369 ; MSSP1 Module: I2C Master | |
| 634 | 370 movlw b'00101000' ; set up I2C to master mode |
| 371 movwf SSP1CON1 ; ... | |
| 372 clrf SSP1CON2 ; ... | |
| 643 | 373 movlw i2c_speed_value |
| 634 | 374 movwf SSP1ADD ; ... |
| 0 | 375 |
| 623 | 376 |
| 0 | 377 ; PWM Module(s) |
| 623 | 378 ; PWM 1 for LED dimming |
| 634 | 379 movlw b'00001100' ; set up PWM module |
| 380 movwf CCP1CON ; ... | |
| 381 movlw b'00000001' ; pulse steering disabled | |
| 382 movwf PSTR1CON ; ... | |
| 383 movlw d'254' ; select period | |
| 384 movwf PR2 ; ... | |
| 604 | 385 ; 255 is max brightness (300 mW) |
| 634 | 386 clrf CCPR1L ; duty cycle, low byte |
| 387 clrf CCPR1H ; duty cycle, high byte | |
| 388 movlw T2CON_NORMAL ; set timer for normal dimming | |
| 389 movwf T2CON ; ... | |
| 623 | 390 |
| 0 | 391 |
| 634 | 392 ; Timer 5 for ISR-independent Wait/Timeout |
| 393 clrf T5GCON ; clear Timer5 gate control register | |
| 394 ; movlw b'10001111' ; old value | |
| 395 movlw b'10001011' ; bit 7-6: 10 = clock source SOSC/SCLKI (with bit 3 = 1) | |
| 396 ; bit 5-4: 00 = 1:1 prescaler | |
| 397 ; bit 3: 1 = clock source SOSC/SCLKI (with bit 7-6 = 10) | |
| 398 ; bit 2: 0 = synchronize external clock input | |
| 399 ; bit 1: 1 = 16 bit operation | |
| 400 ; bit 0: 1 = timer enabled | |
| 401 ; 32768 Hz clock source, 1:1 prescaler -> timer counts at 30.51757813 µs/bit | |
| 402 movwf T5CON ; ... | |
| 0 | 403 |
| 640 | 404 ; Timer 4 for debounce of new digital piezo circuity |
| 405 movlw b'01111011' ; 1:8 Postscale, Prescale = 1, Timer 4 OFF | |
| 406 movwf T4CON | |
| 407 setf PR4 | |
| 408 | |
| 634 | 409 ; turn off unused Timers |
| 640 | 410 banksel 0xF16 ; addresses F16h...F5Fh are not part of the access RAM |
| 634 | 411 movlw b'11000000' ; disable ECCP3 and ECCP2 |
| 412 movwf PMD0 ; ... | |
| 623 | 413 IFDEF _external_sensor |
| 640 | 414 movlw b'11000001' ; disable PSP, CTMU and EMB |
| 623 | 415 ELSE |
| 640 | 416 movlw b'11001001' ; disable PSP, CTMU, Timer 3 and EMB |
| 623 | 417 ENDIF |
| 634 | 418 movwf PMD1 ; ... |
| 419 movlw b'11010111' ; disable timer 10, timer 8, timer 6 and comparators 1-3 | |
| 420 movwf PMD2 ; ... | |
| 421 movlw b'11111111' ; disable CCP 4-10 and timer 12 | |
| 422 movwf PMD3 ; ... | |
| 608 | 423 |
| 623 | 424 |
| 425 ; turn off unused CTMU | |
| 634 | 426 ;banksel 0xF16 ; addresses F16h...F5Fh are not part of the access RAM |
| 427 clrf CTMUCONH ; disable CTMU | |
| 428 clrf CTMUCONL ; ... | |
| 429 clrf CTMUICON ; ... | |
| 430 | |
| 623 | 431 |
| 604 | 432 banksel common |
| 608 | 433 |
| 623 | 434 |
| 0 | 435 ; Interrupts |
| 634 | 436 bcf PIR5,TMR7IF ; if applicable clear timer 7 IRQ flag |
| 0 | 437 |
| 634 | 438 movlw b'11010000' ; enable global IRQ, peripheral IRQ and external IRQ 0 |
| 439 movwf INTCON ; ... | |
| 440 movlw b'00001000' ; external IRQ 0 on falling edge, pull-up of PORTB by TRIS register | |
| 441 movwf INTCON2 ; ... | |
| 442 movlw b'00000000' ; disable external IRQs 1,2,3 | |
| 443 movwf INTCON3 ; ... | |
| 444 movlw b'00000001' ; enable timer 1 IRQ | |
| 445 movwf PIE1 ; ... | |
| 446 movlw b'00000010' ; enable timer 3 IRQ | |
| 447 movwf PIE2 ; ... | |
| 448 movlw b'00000001' ; enable RTCC IRQ | |
| 449 movwf PIE3 ; ... | |
| 640 | 450 movlw b'00001001' ; enable timer 7 and timer 4 IRQ |
| 634 | 451 movwf PIE5 ; ... |
| 452 | |
| 453 ; Release RESET from RX Circuitry | |
| 454 bcf active_reset_ostc_rx | |
| 455 | |
| 456 ; Power-up the Switches | |
| 623 | 457 ;bra power_up_switches |
| 458 | |
| 0 | 459 |
| 634 | 460 ;----------------------------------------------------------------------------- |
| 461 ; Power-up the Switches | |
| 462 ; | |
| 623 | 463 global power_up_switches |
| 464 power_up_switches: | |
| 465 bsf power_sw1 ; switch on power supply for switch 1 | |
| 466 btfss power_sw1 ; power established? | |
| 467 bra $-4 ; NO - wait | |
| 634 | 468 |
| 623 | 469 bsf power_sw2 ; switch on power supply for switch 2 |
| 470 btfss power_sw2 ; power established? | |
| 471 bra $-4 ; NO - wait | |
| 204 | 472 |
| 634 | 473 return ; done |
| 474 | |
| 0 | 475 |
| 476 ;============================================================================= | |
| 634 | 477 hwos2 CODE |
| 478 ;============================================================================= | |
| 623 | 479 |
| 634 | 480 ;----------------------------------------------------------------------------- |
| 481 ; CPU Speed Change Requests | |
| 482 ; | |
| 623 | 483 global request_speed_eco |
| 484 request_speed_eco: | |
| 485 movlw coding_speed_eco ; load coding for eco speed | |
| 486 movwf cpu_speed_request ; request ISR to change the CPU speed | |
| 487 return ; done | |
| 488 | |
| 489 global request_speed_normal | |
| 490 request_speed_normal: | |
| 491 movlw coding_speed_normal ; load coding for normal speed | |
| 492 movwf cpu_speed_request ; request ISR to change the CPU speed | |
| 493 return ; done | |
| 494 | |
| 495 global request_speed_fastest | |
| 496 request_speed_fastest: | |
| 497 movlw coding_speed_fastest ; load coding for fastest speed | |
| 498 movwf cpu_speed_request ; request ISR to change the CPU speed | |
| 499 return ; done | |
| 500 | |
| 634 | 501 |
| 0 | 502 ;============================================================================= |
| 634 | 503 hwos3 CODE |
| 504 ;============================================================================= | |
| 505 | |
| 506 ;----------------------------------------------------------------------------- | |
| 507 ; Backup the first 128 bytes from program FLASH to EEPROM | |
| 623 | 508 ; |
| 509 global backup_flash_page | |
| 510 backup_flash_page: | |
| 511 banksel common | |
| 631 | 512 |
| 634 | 513 ; set start address in internal program FLASH |
| 631 | 514 movlw 0x00 ; set 0x000000 |
| 515 movwf TBLPTRL ; ... | |
| 516 movwf TBLPTRH ; ... | |
| 517 movwf TBLPTRU ; ... | |
| 518 TBLRD*- ; dummy read to be in 128 byte block | |
| 519 | |
| 520 ; set start address in EEPROM | |
| 521 EEPROM_SET_ADDRESS eeprom_prog_page0_backup | |
| 623 | 522 |
| 523 movlw .128 ; copy 1 block = 128 byte | |
| 631 | 524 movwf eeprom_loop ; initialize loop counter |
| 623 | 525 backup_flash_loop: |
| 634 | 526 tblrd+* ; read one byte from program FLASH (with pre-increment) |
| 527 movff TABLAT,EEDATA ; transfer byte from program FLASH read to EEPROM write | |
| 631 | 528 call write_eeprom ; execute EEPROM write |
| 623 | 529 incf EEADR,F ; increment EEPROM address |
| 631 | 530 decfsz eeprom_loop,F ; all 128 byte done? |
| 623 | 531 bra backup_flash_loop ; NO - loop |
| 631 | 532 return ; YES - done |
| 623 | 533 |
| 634 | 534 |
| 0 | 535 ;============================================================================= |
| 634 | 536 hwos4 CODE |
| 537 ;============================================================================= | |
| 538 | |
| 539 ;----------------------------------------------------------------------------- | |
| 540 ; Restore the first 128 bytes from EEPROM to program FLASH | |
| 623 | 541 ; |
| 542 global restore_flash | |
| 543 restore_flash: | |
| 544 banksel common | |
| 631 | 545 |
| 634 | 546 ;set start address in internal program FLASH |
| 631 | 547 movlw 0x00 ; set 0x000000 |
| 548 movwf TBLPTRL ; ... | |
| 549 movwf TBLPTRH ; ... | |
| 550 movwf TBLPTRU ; ... | |
| 551 TBLRD*- ; dummy read to be in 128 byte block | |
| 623 | 552 |
| 553 movlw b'10010100' ; setup block erase | |
| 554 rcall restore_write ; execute block erase | |
| 555 | |
| 631 | 556 ; set start address in EEPROM |
| 557 EEPROM_SET_ADDRESS eeprom_prog_page0_backup | |
| 623 | 558 |
| 631 | 559 movlw .128 ; copy 1 block = 128 byte |
| 560 movwf eeprom_loop ; initialize loop counter | |
| 623 | 561 restore_flash_loop: |
| 631 | 562 call read_eeprom ; execute EEPROM read |
| 623 | 563 incf EEADR,F ; increment EEPROM address |
| 634 | 564 movff EEDATA,TABLAT ; transfer byte from EEPROM read to program FLASH write |
| 565 tblwt+* ; execute program FLASH write (with pre-increment) | |
| 631 | 566 decfsz eeprom_loop,F ; all 128 bytes done? |
| 567 bra restore_flash_loop ; NO - loop | |
| 623 | 568 movlw b'10000100' ; YES - setup block write |
| 569 rcall restore_write ; - execute block write | |
| 570 reset ; - done, reset CPU | |
| 571 | |
| 572 restore_write: | |
| 631 | 573 movwf EECON1 ; configure operation |
| 574 movlw 0x55 ; unlock sequence | |
| 575 movwf EECON2 ; ... | |
| 576 movlw 0xAA ; ... | |
| 577 movwf EECON2 ; ... | |
| 578 bsf EECON1,WR ; execute operation | |
| 579 nop ; wait for operation to complete | |
| 580 nop ; ... | |
| 581 return ; done | |
| 582 | |
| 634 | 583 |
| 631 | 584 ;============================================================================= |
| 634 | 585 hwos5 CODE |
| 586 ;============================================================================= | |
| 587 | |
| 588 ;----------------------------------------------------------------------------- | |
| 589 ; Memory clear and move Functions, to be used via Macros | |
| 631 | 590 ; |
| 591 global memory_clear | |
| 592 memory_clear: | |
| 593 clrf POSTINC1 ; clear address | |
| 594 decfsz WREG ; decrement loop counter, became zero? | |
| 595 bra memory_clear ; NO - loop | |
| 596 return ; YES - done | |
| 597 | |
| 598 global memory_move | |
| 599 memory_move: | |
| 600 movff POSTINC1,POSTINC2 ; copy from-to | |
| 601 decfsz WREG ; decrement loop counter, became zero? | |
| 602 bra memory_move ; NO - loop | |
| 603 return ; YES - done | |
| 0 | 604 |
| 634 | 605 |
| 606 ;============================================================================= | |
| 607 hwos6 CODE | |
| 608 ;============================================================================= | |
| 609 | |
| 610 ;----------------------------------------------------------------------------- | |
| 611 ; Read CPU Silicon Version | |
| 612 ; | |
| 613 global get_cpu_version | |
| 614 get_cpu_version: | |
| 615 movlw 0xFE ; select address 0x3FFFFE | |
| 616 movwf TBLPTRL ; ... | |
| 617 movlw 0xFF ; ... | |
| 618 movwf TBLPTRH ; ... | |
| 619 movlw 0x3F ; ... | |
| 620 movwf TBLPTRU ; ... | |
| 621 TBLRD*+ ; read DEVID1 byte | |
| 622 movlw b'00011111' ; load mask for silicon version | |
| 623 andwf TABLAT,W ; apply mask and store result in WREG | |
| 624 return ; done | |
| 625 | |
| 626 ;----------------------------------------------------------------------------- | |
| 627 | |
| 628 END |