annotate src/comm.asm @ 592:05053910d668

BUGFIX: Re-enable Sensors after sleep in PSCR mode
author heinrichsweikamp
date Wed, 18 Apr 2018 17:03:52 +0200
parents b455b31ce022
children c31e0292bc92
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1 ;=============================================================================
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2 ;
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3 ; File comm.asm REFACTORED VERSION 2.98
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4 ;
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5 ; RS232 via USB
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6 ;
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7 ; Copyright (c) 2012, JD Gascuel, HeinrichsWeikamp, all right reserved.
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8 ;=============================================================================
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9 ; HISTORY
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10 ; 2011-08-22 : [mH] Creation
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11 ; 2012-02-11 : [jDG] Added "c" set custom text, and "i" identify.
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12
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653a3ab08062 rename into hwOS
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13 #include "hwos.inc"
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14 #include "eeprom_rs232.inc"
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15 #include "tft.inc"
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16 #include "wait.inc"
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17 #include "strings.inc"
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18 #include "convert.inc"
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19 #include "external_flash.inc"
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20 #include "tft_outputs.inc"
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21 #include "surfmode.inc"
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22 #include "rtc.inc"
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23 #include "adc_lightsensor.inc"
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24 #include "shared_definitions.h"
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25
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26 extern restart
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27 extern option_reset_all
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28 extern option_check_all
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29 extern gaslist_cleanup_list
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30 extern get_first_gas_to_WREG
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31 extern get_first_dil_to_WREG
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32 extern vault_decodata_into_eeprom
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33 extern color_image
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34
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35
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36 #DEFINE timeout_comm_pre_mode .240 ; Pre-loop
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37 #DEFINE timeout_comm_mode .120 ; Download mode
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38 #DEFINE timeout_service_mode .120 ; Service mode
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39
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40 #DEFINE comm_title_row .0
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41 #DEFINE comm_title_column_usb .50
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42 #DEFINE comm_title_column_ble .25
0
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43
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44 #DEFINE comm_string_row .30
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45 #DEFINE comm_string_column .40
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46
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47 #DEFINE comm_status1_row .70
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48 #DEFINE comm_status1_column .10
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49 #DEFINE comm_status2_row .100
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50 #DEFINE comm_status2_column comm_status1_column
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51 #DEFINE comm_status3_row .130
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52 #DEFINE comm_status3_column comm_status1_column
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53
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54 #DEFINE comm_warning_row .160
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55 #DEFINE comm_warning_column .65
0
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56
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57 comm code
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58
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59 ; test for comm
218
8fbd8c5ac51f 1.71beta start
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60 global comm_mode, comm_mode0
0
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61 comm_mode:
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62 WAITMS d'1'
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63 btfss vusb_in ; USB plugged in?
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64 return ; No, it was only a glitch
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65 WAITMS d'1'
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66 btfss vusb_in ; USB plugged in?
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67 return ; No, it was only a glitch
218
8fbd8c5ac51f 1.71beta start
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68 comm_mode0:
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69 call TFT_ClearScreen
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70 WIN_COLOR color_greenish
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71 btfsc ble_available ; ble available
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72 bra comm_mode0_ble
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73 WIN_SMALL comm_title_column_usb, comm_title_row
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74 STRCPY_TEXT_PRINT tUsbTitle ; USB Mode
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75 bra comm_mode0_common
269
1207cf9a9408 adjust menu for different hardware versions
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76 comm_mode0_ble:
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77 WIN_SMALL comm_title_column_ble, comm_title_row
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78 STRCPY_TEXT_PRINT tBleTitle ; BLE Mode
269
1207cf9a9408 adjust menu for different hardware versions
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79 comm_mode0_common:
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80 call TFT_standard_color
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81 WIN_TOP .10
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82 WIN_LEFT .1
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83 movlw 0xDE
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84 movwf TBLPTRL
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85 movlw 0xEE
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86 movwf TBLPTRH
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87 movlw 0x01
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88 movwf TBLPTRU
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89 call color_image ; Show USB logo
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90 WIN_SMALL comm_status1_column,comm_status1_row
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91 STRCPY_TEXT_PRINT tUsbStarting ; Starting...
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92 call TFT_serial ; Show serial and firmware version
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93 bcf enable_screen_dumps ; =1: Ignore vin_usb, wait for "l" command (Screen dump)
0
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94 bcf switch_right
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95 bcf comm_service_enabled
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96 bsf menubit
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97 bcf battery_removed_in_usb ; =1: The battery has been removed in USB (properly not used for anything useful)
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98 movlw timeout_comm_pre_mode
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99 movwf comm_timeout
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100 WIN_SMALL comm_status1_column+.80,comm_status1_row
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101 STRCPY_TEXT_PRINT tUsbStartDone ; Done...
0
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102 call enable_rs232 ; Also sets to speed_normal ...
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103 comm_mode1:
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104 bcf onesecupdate
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105 bcf LEDr
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106 dcfsnz comm_timeout,F
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107 bra comm_service_exit ; Timeout -> Exit
0
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108 comm_mode2:
350
2fd258596af0 some cleanups
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109 rcall comm_write_get_byte
0
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110
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111 movlw 0xAA ; start byte=0xAA?
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112 cpfseq RCREG1
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113 bra comm_mode2a
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114 bra comm_mode2b ; Start byte for service mode found
0
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115 comm_mode2a:
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116 movlw 0xBB ; start byte=0xBB?
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117 cpfseq RCREG1
393
9e5abca93c32 tweak response timing in comm mode
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118 bra comm_mode2c
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119 bra comm_download_mode ; Start byte for download mode found
0
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120
393
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121 comm_mode2c:
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122 btfss vusb_in ; USB plugged in?
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123 bra comm_service_exit_nousb_delay ; Disconnected -> Exit
393
9e5abca93c32 tweak response timing in comm mode
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124 comm_mode4a:
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125 btfsc switch_right ; Abort with right
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126 bra comm_service_exit
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127
9e5abca93c32 tweak response timing in comm mode
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128 btfsc onesecupdate
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129 bra comm_mode1
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130
582
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131 bra comm_mode2 ; Cycle
393
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132
0
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133 comm_mode2b:
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134 ; Startbyte found
354
043890f06bce some cleanups
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135 rcall comm_rs232_wait_tx ; Wait for UART
0
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136 movlw 0x4B
560
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137 movwf TXREG1 ; Send Answer
0
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138 ; Now, check comm command
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139
560
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140 rcall comm_write_get_byte ; first byte
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141 rcall comm_rs232_wait_tx ; Wait for UART
582
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142 movff RCREG1,TXREG1 ; Echo
0
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143 movlw UPPER comm_service_key
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144 cpfseq RCREG1
582
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145 bra comm_mode1 ; Wrong -> Restart
560
b7eb98dbd800 bump to 2.96beta (REFACTORED VERSION)
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146 rcall comm_write_get_byte ; second byte
354
043890f06bce some cleanups
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147 rcall comm_rs232_wait_tx ; Wait for UART
582
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148 movff RCREG1,TXREG1 ; Echo
0
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149 movlw HIGH (comm_service_key & 0xFFFF)
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150 cpfseq RCREG1
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151 bra comm_mode1 ; Wrong -> Restart
560
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152 rcall comm_write_get_byte ; third byte
354
043890f06bce some cleanups
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153 rcall comm_rs232_wait_tx ; Wait for UART
582
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154 movff RCREG1,TXREG1 ; Echo
0
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155 movlw LOW comm_service_key
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156 cpfseq RCREG1
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157 bra comm_mode1 ; Wrong -> Restart
0
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158
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159 ; Enable comm service mode
582
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160 WIN_SMALL comm_status2_column, comm_status2_row
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161 STRCPY_TEXT_PRINT tUsbServiceMode ; Service mode enabled
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162 bsf comm_service_enabled ; Set flag...
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163 bra comm_download_mode0 ; ... but use common routine
69
50697bd41c54 +CHANGE: Some French Translations
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164
50697bd41c54 +CHANGE: Some French Translations
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165 comm_service_exit_nousb_delay:
582
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166 WAITMS d'200'
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167 btfsc vusb_in ; USB plugged in?
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168 bra comm_mode4a ; (Still) connected, return
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169 comm_service_exit_nousb: ; Disconnected -> Exit
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170 WIN_SMALL comm_status3_column, comm_status3_row
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171 STRCPY_TEXT_PRINT tUsbClosed ; Port closed
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172 bra comm_service_exit_common
0
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173
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174 comm_service_exit:
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175 WIN_SMALL comm_status3_column, comm_status3_row
582
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176 STRCPY_TEXT_PRINT tUsbExit ; Exited
0
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177 comm_service_exit_common:
560
b7eb98dbd800 bump to 2.96beta (REFACTORED VERSION)
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178 rcall comm_rs232_wait_tx ; Wait for UART
582
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179 movlw 0xFF ; Reply FF
0
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180 movwf TXREG1 ; Send Answer
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181
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182 ; Wait 1 second
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183 bcf onesecupdate
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184 btfss onesecupdate
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185 bra $-2
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186 ; Wait 1 second
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187 bcf onesecupdate
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188 btfss onesecupdate
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189 bra $-2
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190
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191 call disable_rs232
582
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192 goto restart
0
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193
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194 ;-----------------------------------------------------------------------------
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195
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196 comm_service_ll_bootloader:
582
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197 bsf LEDr
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198 WIN_SMALL comm_status3_column, comm_status3_row
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199 STRCPY_TEXT_PRINT tUsbLlBld ; Low Level Bootloader started
b455b31ce022 work on 2.97 stable
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200 WIN_TOP comm_warning_row
b455b31ce022 work on 2.97 stable
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201 WIN_LEFT comm_warning_column
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202 TFT_WRITE_PROM_IMAGE dive_warning2_block ; Show Warning icon
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203 goto 0x1FF0C
0
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204
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205 ;-----------------------------------------------------------------------------
273
12ee30cbced9 CHANGE: Automatically abort connection fail after 2mins (Bluetooth only)
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206 ; send firmware to bootloader
0
heinrichsweikamp
parents:
diff changeset
207 ;
heinrichsweikamp
parents:
diff changeset
208 comm_send_firmware:
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
209 movlw 0x50 ; send echo
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
210 movwf TXREG1
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
211 rcall comm_rs232_wait_tx ; Wait for UART
0
heinrichsweikamp
parents:
diff changeset
212
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
213 ; Read 5 bytes into buffer.
0
heinrichsweikamp
parents:
diff changeset
214 lfsr FSR2,buffer
heinrichsweikamp
parents:
diff changeset
215 movlw .5 ; counter
heinrichsweikamp
parents:
diff changeset
216 movwf lo
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
217 movlw 0x55 ; 5'ft byte checksum.
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
218 movwf hi
0
heinrichsweikamp
parents:
diff changeset
219
heinrichsweikamp
parents:
diff changeset
220 comm_send_firmware_loop:
350
2fd258596af0 some cleanups
heinrichsweikamp
parents: 347
diff changeset
221 rcall comm_write_get_byte
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
222 btfsc rs232_receive_overflow ; Got byte?
560
b7eb98dbd800 bump to 2.96beta (REFACTORED VERSION)
heinrichsweikamp
parents: 512
diff changeset
223 bra comm_send_firmware_abort ; No, abort!
0
heinrichsweikamp
parents:
diff changeset
224 movf RCREG1,W
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
225 movwf POSTINC2 ; Store checksum byte.
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
226 xorwf hi,F ; Also xor into checksum
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
227 rlncf hi,F ; And rotate it.
0
heinrichsweikamp
parents:
diff changeset
228 decfsz lo,F
heinrichsweikamp
parents:
diff changeset
229 bra comm_send_firmware_loop
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
230
0
heinrichsweikamp
parents:
diff changeset
231 ; Check that 5ft byte checksum's checksum
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
232 movf hi,W
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
233 bnz comm_send_firmware_failed
0
heinrichsweikamp
parents:
diff changeset
234
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
235 movlw 0x4C ; send OK
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
236 movwf TXREG1
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
237 rcall comm_rs232_wait_tx ; Wait for UART
0
heinrichsweikamp
parents:
diff changeset
238
heinrichsweikamp
parents:
diff changeset
239 ; Passed: goto second stage verification.
heinrichsweikamp
parents:
diff changeset
240 ; NOTE: Bootloader is Bank0. With buffer at address 0x200.
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
241 call vault_decodata_into_eeprom ; Store last deco data (And Time/Date) into EEPROM
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
242 goto 0x1FDF0 ; And pray...
0
heinrichsweikamp
parents:
diff changeset
243
heinrichsweikamp
parents:
diff changeset
244 comm_send_firmware_failed:
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
245 WIN_SMALL comm_string_column, comm_string_row
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
246 call TFT_warnings_color
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
247 STRCPY_PRINT "Checksum failed"
0
heinrichsweikamp
parents:
diff changeset
248
heinrichsweikamp
parents:
diff changeset
249 comm_send_firmware_abort:
heinrichsweikamp
parents:
diff changeset
250
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
251 movlw 0xFF ; send ABORTED byte.
0
heinrichsweikamp
parents:
diff changeset
252 movwf TXREG1
heinrichsweikamp
parents:
diff changeset
253 bra comm_download_mode0 ; Done.
heinrichsweikamp
parents:
diff changeset
254
heinrichsweikamp
parents:
diff changeset
255 ;-----------------------------------------------------------------------------
heinrichsweikamp
parents:
diff changeset
256 ; Reset to Dive 1 in logbook
heinrichsweikamp
parents:
diff changeset
257
heinrichsweikamp
parents:
diff changeset
258 comm_reset_logbook_pointers:
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
259 call eeprom_reset_logbook_pointers ; clear logbook pointers in EEPROM...
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
260 call ext_flash_erase_logbook ; ... and complete logbook (!)
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
261 bra comm_download_mode0 ; done
0
heinrichsweikamp
parents:
diff changeset
262
heinrichsweikamp
parents:
diff changeset
263 ;-----------------------------------------------------------------------------
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
264 comm_reset_battery_gauge: ; Resets battery gauge registers
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
265 call reset_battery_pointer ; Resets battery pointer 0x07-0x0C and battery_gauge:5
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
266 bra comm_download_mode0 ; Done.
0
heinrichsweikamp
parents:
diff changeset
267
heinrichsweikamp
parents:
diff changeset
268 ;-----------------------------------------------------------------------------
heinrichsweikamp
parents:
diff changeset
269 ; erases range in 4kB steps
heinrichsweikamp
parents:
diff changeset
270
heinrichsweikamp
parents:
diff changeset
271 comm_erase_range4kb:
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
272 movlw 0x42 ; send echo
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
273 movwf TXREG1
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
274 rcall comm_rs232_wait_tx ; Wait for UART
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
275 bcf INTCON,GIE ; All interrupts off!
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
276 rcall comm_get_flash_address ; Get three bytes address or return
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
277 btfsc rs232_receive_overflow ; Got Data?
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
278 bra comm_download_mode0 ; No, Done.
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
279 rcall comm_write_get_byte
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
280 btfsc rs232_receive_overflow ; Got byte?
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
281 bra comm_download_mode0 ; No, Done.
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
282 movff RCREG1,lo
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
283 ; Got 4 bytes: 3 bytes address and 1 byte (lo) amount of 4kB blocks
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
284 comm_erase_range4kb_loop:
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
285 call ext_flash_erase4kB ; Erase block!
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
286 movlw 0x10
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
287 addwf ext_flash_address+1,F
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
288 movlw .0
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
289 addwfc ext_flash_address+2,F ; Increase address by .4096, or 0x1000
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
290 decfsz lo,F
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
291 bra comm_erase_range4kb_loop ; Loop until lo=zero
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
292 bra comm_download_mode0 ; Done (Sends the 4C OK too).
0
heinrichsweikamp
parents:
diff changeset
293
heinrichsweikamp
parents:
diff changeset
294 ;-----------------------------------------------------------------------------
heinrichsweikamp
parents:
diff changeset
295
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
296 comm_erase_4kb: ; Get 3 bytes start address
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
297 bcf INTCON,GIE ; All interrupts off!
0
heinrichsweikamp
parents:
diff changeset
298
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
299 rcall comm_get_flash_address ; Get three bytes address or return
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
300 btfsc rs232_receive_overflow ; Got Data?
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
301 bra comm_download_mode0 ; No, Done.
0
heinrichsweikamp
parents:
diff changeset
302
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
303 call ext_flash_erase4kB ; Erase one block
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
304 bra comm_download_mode0 ; Done.
0
heinrichsweikamp
parents:
diff changeset
305
heinrichsweikamp
parents:
diff changeset
306 ;-----------------------------------------------------------------------------
heinrichsweikamp
parents:
diff changeset
307
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
308 comm_write_range: ; Get 3 bytes start address
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
309 movlw 0x30 ; send echo
0
heinrichsweikamp
parents:
diff changeset
310 movwf TXREG1
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
311 rcall comm_rs232_wait_tx ; Wait for UART
0
heinrichsweikamp
parents:
diff changeset
312
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
313 bcf INTCON,GIE ; All interrupts off!
0
heinrichsweikamp
parents:
diff changeset
314
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
315 rcall comm_get_flash_address ; Get three bytes address or return
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
316 btfsc rs232_receive_overflow ; Got Data?
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
317 bra comm_download_mode0 ; No, Done.
0
heinrichsweikamp
parents:
diff changeset
318
heinrichsweikamp
parents:
diff changeset
319 comm_write_range_loop:
350
2fd258596af0 some cleanups
heinrichsweikamp
parents: 347
diff changeset
320 rcall comm_write_get_byte
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
321 btfsc rs232_receive_overflow ; Got byte?
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
322 bra comm_download_mode0 ; No, Done (and send OK byte too).
0
heinrichsweikamp
parents:
diff changeset
323 movf RCREG1,W
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
324 ; bsf NCTS ; Hold Bluetooth Chip (Requires PC/Android/iOS side to use flow control...)
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
325 call ext_flash_byte_write_comms ; write one byte
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
326 ; bcf NCTS ; Release Bluetooth Chip (Requires PC/Android/iOS side to use flow control...)
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
327 call incf_ext_flash_address_p1 ; increase address+1
420
789230298511 fix handling for new flash memory chip
heinrichsweikamp
parents: 399
diff changeset
328 bra comm_write_range_loop
0
heinrichsweikamp
parents:
diff changeset
329
heinrichsweikamp
parents:
diff changeset
330 ;-----------------------------------------------------------------------------
heinrichsweikamp
parents:
diff changeset
331
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
332 comm_send_range: ; Get 3 bytes start address and 3 bytes amount
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
333 movlw 0x20 ; send echo
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
334 movwf TXREG1
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
335 rcall comm_rs232_wait_tx ; Wait for UART
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
336 bcf INTCON,GIE ; All interrupts off!
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
337 rcall comm_get_flash_address ; Get three bytes address or return
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
338 btfsc rs232_receive_overflow ; Got Data?
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
339 bra comm_download_mode0 ; No, Done.
350
2fd258596af0 some cleanups
heinrichsweikamp
parents: 347
diff changeset
340 rcall comm_write_get_byte
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
341 btfsc rs232_receive_overflow ; Got byte?
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
342 bra comm_download_mode0 ; No, Done.
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
343 movff RCREG1,up
350
2fd258596af0 some cleanups
heinrichsweikamp
parents: 347
diff changeset
344 rcall comm_write_get_byte
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
345 btfsc rs232_receive_overflow ; Got byte?
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
346 bra comm_download_mode0 ; No, Done.
0
heinrichsweikamp
parents:
diff changeset
347 movff RCREG1,hi
350
2fd258596af0 some cleanups
heinrichsweikamp
parents: 347
diff changeset
348 rcall comm_write_get_byte
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
349 btfsc rs232_receive_overflow ; Got byte?
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
350 bra comm_download_mode0 ; No, Done.
0
heinrichsweikamp
parents:
diff changeset
351 movff RCREG1,lo
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
352 ; If lo==0, we must precondition hi because there are to many bytes send !
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
353 movf lo,W
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
354 bnz $+4
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
355 decf hi,F
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
356 movlw 0x40
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
357 cpfslt up ; Abort when up > 0x3F
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
358 bra comm_download_mode0 ; Abort
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
359 ; 6 bytes received, send data
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
360 ; needs ext_flash_address:3 start address and up:hi:lo amount
0
heinrichsweikamp
parents:
diff changeset
361 call ext_flash_read_block_start
heinrichsweikamp
parents:
diff changeset
362 movwf TXREG1
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
363 bra comm_send_range24 ; counter 24bit
0
heinrichsweikamp
parents:
diff changeset
364 comm_send_range24_loop:
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
365 call ext_flash_read_block ; Read one byte
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
366 movwf TXREG1 ; Start new transmit
0
heinrichsweikamp
parents:
diff changeset
367 comm_send_range24:
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
368 rcall comm_rs232_wait_tx ; Wait for UART
0
heinrichsweikamp
parents:
diff changeset
369 decfsz lo,F
heinrichsweikamp
parents:
diff changeset
370 bra comm_send_range24_loop
heinrichsweikamp
parents:
diff changeset
371 decf hi,F
heinrichsweikamp
parents:
diff changeset
372 movlw 0xFF
heinrichsweikamp
parents:
diff changeset
373 cpfseq hi
heinrichsweikamp
parents:
diff changeset
374 bra comm_send_range24_loop
heinrichsweikamp
parents:
diff changeset
375 decf up,F
heinrichsweikamp
parents:
diff changeset
376 movlw 0xFF
heinrichsweikamp
parents:
diff changeset
377 cpfseq up
heinrichsweikamp
parents:
diff changeset
378 bra comm_send_range24_loop
heinrichsweikamp
parents:
diff changeset
379 call ext_flash_read_block_stop
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
380 bra comm_download_mode0 ; Done.
0
heinrichsweikamp
parents:
diff changeset
381
heinrichsweikamp
parents:
diff changeset
382 ;-----------------------------------------------------------------------------
heinrichsweikamp
parents:
diff changeset
383
heinrichsweikamp
parents:
diff changeset
384 comm_get_flash_address:
350
2fd258596af0 some cleanups
heinrichsweikamp
parents: 347
diff changeset
385 rcall comm_write_get_byte
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
386 btfsc rs232_receive_overflow ; Got byte?
0
heinrichsweikamp
parents:
diff changeset
387 return ; No, return
heinrichsweikamp
parents:
diff changeset
388 movff RCREG1,ext_flash_address+2
350
2fd258596af0 some cleanups
heinrichsweikamp
parents: 347
diff changeset
389 rcall comm_write_get_byte
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
390 btfsc rs232_receive_overflow ; Got byte?
0
heinrichsweikamp
parents:
diff changeset
391 return ; No, return
heinrichsweikamp
parents:
diff changeset
392 movff RCREG1,ext_flash_address+1
350
2fd258596af0 some cleanups
heinrichsweikamp
parents: 347
diff changeset
393 rcall comm_write_get_byte
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
394 btfsc rs232_receive_overflow ; Got byte?
0
heinrichsweikamp
parents:
diff changeset
395 return ; No, return
heinrichsweikamp
parents:
diff changeset
396 movff RCREG1,ext_flash_address+0
heinrichsweikamp
parents:
diff changeset
397 return
heinrichsweikamp
parents:
diff changeset
398
heinrichsweikamp
parents:
diff changeset
399 ;-----------------------------------------------------------------------------
heinrichsweikamp
parents:
diff changeset
400
heinrichsweikamp
parents:
diff changeset
401 comm_download_mode:
heinrichsweikamp
parents:
diff changeset
402 ; Enable comm download mode
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
403 WIN_SMALL comm_status2_column, comm_status2_row
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
404 STRCPY_TEXT_PRINT tUsbDownloadMode ; Download mode enabled
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
405 bsf INTCON,GIE ; All interrupts on
560
b7eb98dbd800 bump to 2.96beta (REFACTORED VERSION)
heinrichsweikamp
parents: 512
diff changeset
406 rcall comm_rs232_wait_tx ; Wait for UART
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
407 movlw 0xBB ; Command Echo
0
heinrichsweikamp
parents:
diff changeset
408 movwf TXREG1 ; Send Answer
heinrichsweikamp
parents:
diff changeset
409 comm_download_mode0:
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
410 bsf INTCON,GIE ; All interrupts on
560
b7eb98dbd800 bump to 2.96beta (REFACTORED VERSION)
heinrichsweikamp
parents: 512
diff changeset
411 rcall comm_rs232_wait_tx ; Wait for UART
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
412 movlw 0x4C ; 4C in service mode
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
413 btfss comm_service_enabled
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
414 movlw 0x4D ; 4D in download mode
0
heinrichsweikamp
parents:
diff changeset
415 movwf TXREG1 ; Send Answer
heinrichsweikamp
parents:
diff changeset
416 movlw timeout_service_mode
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
417 movwf comm_timeout ; Timeout
0
heinrichsweikamp
parents:
diff changeset
418 bcf switch_right
heinrichsweikamp
parents:
diff changeset
419 comm_download_mode1:
heinrichsweikamp
parents:
diff changeset
420 bcf onesecupdate
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
421 dcfsnz comm_timeout,F
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
422 bra comm_service_exit ; Timeout -> Exit
0
heinrichsweikamp
parents:
diff changeset
423 comm_download_mode2:
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
424 rcall comm_write_get_byte ; Check for a byte
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
425 btfsc comm_service_enabled
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
426 btg LEDr ; Blink in Service mode
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
427 btfss vusb_in ; USB plugged in?
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
428 bra comm_service_exit_nousb ; Disconnected -> Exit
0
heinrichsweikamp
parents:
diff changeset
429 btfsc switch_right ; Abort with right
heinrichsweikamp
parents:
diff changeset
430 bra comm_service_exit
heinrichsweikamp
parents:
diff changeset
431 btfsc onesecupdate
heinrichsweikamp
parents:
diff changeset
432 bra comm_download_mode1
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
433 btfsc rs232_receive_overflow
560
b7eb98dbd800 bump to 2.96beta (REFACTORED VERSION)
heinrichsweikamp
parents: 512
diff changeset
434 bra comm_download_mode2 ; Wait for command byte
0
heinrichsweikamp
parents:
diff changeset
435
heinrichsweikamp
parents:
diff changeset
436 ; command received!
heinrichsweikamp
parents:
diff changeset
437 bcf LEDr
heinrichsweikamp
parents:
diff changeset
438 movlw 0xFF
heinrichsweikamp
parents:
diff changeset
439 cpfseq RCREG1
heinrichsweikamp
parents:
diff changeset
440 bra $+4
heinrichsweikamp
parents:
diff changeset
441 bra comm_service_exit ; exit
heinrichsweikamp
parents:
diff changeset
442 movlw "a"
heinrichsweikamp
parents:
diff changeset
443 cpfseq RCREG1
heinrichsweikamp
parents:
diff changeset
444 bra $+4
heinrichsweikamp
parents:
diff changeset
445 bra comm_send_headers ; Send all 256 dive headers
heinrichsweikamp
parents:
diff changeset
446 movlw "b"
heinrichsweikamp
parents:
diff changeset
447 cpfseq RCREG1
heinrichsweikamp
parents:
diff changeset
448 bra $+4
heinrichsweikamp
parents:
diff changeset
449 bra comm_set_time ; Read time and date from the PC and set clock
heinrichsweikamp
parents:
diff changeset
450 movlw "c"
heinrichsweikamp
parents:
diff changeset
451 cpfseq RCREG1
heinrichsweikamp
parents:
diff changeset
452 bra $+4
heinrichsweikamp
parents:
diff changeset
453 bra comm_set_custom_text ; Send a opt_name_length byte string of custom text.
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
454 movlw "f" ; 0x66
0
heinrichsweikamp
parents:
diff changeset
455 cpfseq RCREG1
heinrichsweikamp
parents:
diff changeset
456 bra $+4
heinrichsweikamp
parents:
diff changeset
457 bra comm_send_dive ; Send header and profile for one dive
heinrichsweikamp
parents:
diff changeset
458 movlw "i"
heinrichsweikamp
parents:
diff changeset
459 cpfseq RCREG1
heinrichsweikamp
parents:
diff changeset
460 bra $+4
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
461 bra comm_identify ; Send firmware, serial, etc.
235
23311219dacc under construction: new hardware_flag to configure different hardware versions
heinrichsweikamp
parents: 223
diff changeset
462 movlw "j"
23311219dacc under construction: new hardware_flag to configure different hardware versions
heinrichsweikamp
parents: 223
diff changeset
463 cpfseq RCREG1
23311219dacc under construction: new hardware_flag to configure different hardware versions
heinrichsweikamp
parents: 223
diff changeset
464 bra $+4
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
465 bra comm_hardware_descriptor ; Send hardware descriptor byte
441
360acdcda0d7 +BUGFIX: Compatibility with "hwOS Config" fixed
heinrichsweikamp
parents: 426
diff changeset
466 movlw 0x60
360acdcda0d7 +BUGFIX: Compatibility with "hwOS Config" fixed
heinrichsweikamp
parents: 426
diff changeset
467 cpfseq RCREG1
360acdcda0d7 +BUGFIX: Compatibility with "hwOS Config" fixed
heinrichsweikamp
parents: 426
diff changeset
468 bra $+4
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
469 bra comm_feature_and_hardware ; Send more detailed informations
0
heinrichsweikamp
parents:
diff changeset
470 movlw "n"
heinrichsweikamp
parents:
diff changeset
471 cpfseq RCREG1
heinrichsweikamp
parents:
diff changeset
472 bra $+4
80
db920ca01491 new commands in download mode:
mh@mh-THINK.localdomain
parents: 79
diff changeset
473 goto comm_send_string ; Send a 15byte string to the screen
346
cf9ce6053dee New option to download "Compact Headers". Improved BLE support (OSTC 2 and OSTC 3+), updated OSTC interface documentation
heinrichsweikamp
parents: 337
diff changeset
474 movlw "m"
cf9ce6053dee New option to download "Compact Headers". Improved BLE support (OSTC 2 and OSTC 3+), updated OSTC interface documentation
heinrichsweikamp
parents: 337
diff changeset
475 cpfseq RCREG1
cf9ce6053dee New option to download "Compact Headers". Improved BLE support (OSTC 2 and OSTC 3+), updated OSTC interface documentation
heinrichsweikamp
parents: 337
diff changeset
476 bra $+4
cf9ce6053dee New option to download "Compact Headers". Improved BLE support (OSTC 2 and OSTC 3+), updated OSTC interface documentation
heinrichsweikamp
parents: 337
diff changeset
477 goto comm_send_compact_headers ; Send all 256 compact headers
0
heinrichsweikamp
parents:
diff changeset
478 movlw "l"
heinrichsweikamp
parents:
diff changeset
479 cpfseq RCREG1
heinrichsweikamp
parents:
diff changeset
480 bra $+4
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
481 call TFT_dump_screen ; Dump the screen contents
79
0fc8113ddf6d new command in download mode: "r" - read setting
mh@mh-THINK.localdomain
parents: 69
diff changeset
482 movlw "r"
0fc8113ddf6d new command in download mode: "r" - read setting
mh@mh-THINK.localdomain
parents: 69
diff changeset
483 cpfseq RCREG1
0fc8113ddf6d new command in download mode: "r" - read setting
mh@mh-THINK.localdomain
parents: 69
diff changeset
484 bra $+4
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
485 bra comm_read_setting ; Read a setting (And send via USB)
80
db920ca01491 new commands in download mode:
mh@mh-THINK.localdomain
parents: 79
diff changeset
486 movlw "w"
db920ca01491 new commands in download mode:
mh@mh-THINK.localdomain
parents: 79
diff changeset
487 cpfseq RCREG1
db920ca01491 new commands in download mode:
mh@mh-THINK.localdomain
parents: 79
diff changeset
488 bra $+4
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
489 bra comm_write_setting ; Write a setting (Into RAM)
80
db920ca01491 new commands in download mode:
mh@mh-THINK.localdomain
parents: 79
diff changeset
490 movlw "x"
db920ca01491 new commands in download mode:
mh@mh-THINK.localdomain
parents: 79
diff changeset
491 cpfseq RCREG1
db920ca01491 new commands in download mode:
mh@mh-THINK.localdomain
parents: 79
diff changeset
492 bra $+4
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
493 bra comm_option_reset_all ; Reset all options to factory default.
0
heinrichsweikamp
parents:
diff changeset
494
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
495 btfss comm_service_enabled ; Done for Download mode
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
496 bra comm_download_mode0 ; Loop with timeout reset
0
heinrichsweikamp
parents:
diff changeset
497
heinrichsweikamp
parents:
diff changeset
498 movlw 0x20
heinrichsweikamp
parents:
diff changeset
499 cpfseq RCREG1
heinrichsweikamp
parents:
diff changeset
500 bra $+4
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
501 bra comm_send_range ; send hi:lo:ext_flash_rw bytes starting from ext_flash_address:3
0
heinrichsweikamp
parents:
diff changeset
502 movlw 0x22
heinrichsweikamp
parents:
diff changeset
503 cpfseq RCREG1
heinrichsweikamp
parents:
diff changeset
504 bra $+4
heinrichsweikamp
parents:
diff changeset
505 bra comm_reset_logbook_pointers ; Resets all logbook pointers and the logbook (!)
heinrichsweikamp
parents:
diff changeset
506 movlw 0x23
heinrichsweikamp
parents:
diff changeset
507 cpfseq RCREG1
heinrichsweikamp
parents:
diff changeset
508 bra $+4
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
509 bra comm_reset_battery_gauge ; Resets battery gauge registers
0
heinrichsweikamp
parents:
diff changeset
510 movlw 0x30
heinrichsweikamp
parents:
diff changeset
511 cpfseq RCREG1
heinrichsweikamp
parents:
diff changeset
512 bra $+4
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
513 bra comm_write_range ; write bytes starting from ext_flash_address:3 (Stop when timeout)
0
heinrichsweikamp
parents:
diff changeset
514 movlw 0x40
heinrichsweikamp
parents:
diff changeset
515 cpfseq RCREG1
heinrichsweikamp
parents:
diff changeset
516 bra $+4
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
517 bra comm_erase_4kb ; erases 4kB block from ext_flash_address:3 (Warning: No confirmation or built-in security here...)
0
heinrichsweikamp
parents:
diff changeset
518 movlw 0x42
heinrichsweikamp
parents:
diff changeset
519 cpfseq RCREG1
heinrichsweikamp
parents:
diff changeset
520 bra $+4
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
521 bra comm_erase_range4kb ; erases range in 4kB steps (Get 3 bytes address and 1byte amount of 4kB blocks)
0
heinrichsweikamp
parents:
diff changeset
522 movlw 0x50
heinrichsweikamp
parents:
diff changeset
523 cpfseq RCREG1
heinrichsweikamp
parents:
diff changeset
524 bra $+4
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
525 bra comm_send_firmware ; send firmware to bootloader
147
fdd4e30846ae some cleanup
heinrichsweikamp
parents: 136
diff changeset
526 ; movlw "t"
fdd4e30846ae some cleanup
heinrichsweikamp
parents: 136
diff changeset
527 ; cpfseq RCREG1
fdd4e30846ae some cleanup
heinrichsweikamp
parents: 136
diff changeset
528 ; bra $+4
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
529 ; goto testloop ; Start raw-data testloop
0
heinrichsweikamp
parents:
diff changeset
530 movlw 0xC1
heinrichsweikamp
parents:
diff changeset
531 cpfseq RCREG1
heinrichsweikamp
parents:
diff changeset
532 bra $+4
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
533 bra comm_service_ll_bootloader ; Start low-level bootloader
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
534 bra comm_download_mode0 ; Loop with timeout reset
0
heinrichsweikamp
parents:
diff changeset
535
heinrichsweikamp
parents:
diff changeset
536 ;-----------------------------------------------------------------------------
heinrichsweikamp
parents:
diff changeset
537
346
cf9ce6053dee New option to download "Compact Headers". Improved BLE support (OSTC 2 and OSTC 3+), updated OSTC interface documentation
heinrichsweikamp
parents: 337
diff changeset
538 comm_send_compact_headers:
560
b7eb98dbd800 bump to 2.96beta (REFACTORED VERSION)
heinrichsweikamp
parents: 512
diff changeset
539 movlw "m" ; send echo
346
cf9ce6053dee New option to download "Compact Headers". Improved BLE support (OSTC 2 and OSTC 3+), updated OSTC interface documentation
heinrichsweikamp
parents: 337
diff changeset
540 movwf TXREG1
347
7e5772df60cd Changed content for new 0x6F command (Get compact headers)
heinrichsweikamp
parents: 346
diff changeset
541 ; Send 13 bytes/dive (Compact Header)
7e5772df60cd Changed content for new 0x6F command (Get compact headers)
heinrichsweikamp
parents: 346
diff changeset
542 ; 1st: 200009h-200016h
7e5772df60cd Changed content for new 0x6F command (Get compact headers)
heinrichsweikamp
parents: 346
diff changeset
543 ; 2nd: 201009h-201016h
7e5772df60cd Changed content for new 0x6F command (Get compact headers)
heinrichsweikamp
parents: 346
diff changeset
544 ; 3rd: 202009h-202016h
7e5772df60cd Changed content for new 0x6F command (Get compact headers)
heinrichsweikamp
parents: 346
diff changeset
545 ; 100: 264009h-264016h
7e5772df60cd Changed content for new 0x6F command (Get compact headers)
heinrichsweikamp
parents: 346
diff changeset
546 ; 256: 2FF009h-2FF016h
346
cf9ce6053dee New option to download "Compact Headers". Improved BLE support (OSTC 2 and OSTC 3+), updated OSTC interface documentation
heinrichsweikamp
parents: 337
diff changeset
547 movlw 0x1F
cf9ce6053dee New option to download "Compact Headers". Improved BLE support (OSTC 2 and OSTC 3+), updated OSTC interface documentation
heinrichsweikamp
parents: 337
diff changeset
548 movwf ext_flash_address+2
cf9ce6053dee New option to download "Compact Headers". Improved BLE support (OSTC 2 and OSTC 3+), updated OSTC interface documentation
heinrichsweikamp
parents: 337
diff changeset
549 movlw 0xF0
cf9ce6053dee New option to download "Compact Headers". Improved BLE support (OSTC 2 and OSTC 3+), updated OSTC interface documentation
heinrichsweikamp
parents: 337
diff changeset
550 movwf ext_flash_address+1
cf9ce6053dee New option to download "Compact Headers". Improved BLE support (OSTC 2 and OSTC 3+), updated OSTC interface documentation
heinrichsweikamp
parents: 337
diff changeset
551
cf9ce6053dee New option to download "Compact Headers". Improved BLE support (OSTC 2 and OSTC 3+), updated OSTC interface documentation
heinrichsweikamp
parents: 337
diff changeset
552 comm_send_compact_headers2:
347
7e5772df60cd Changed content for new 0x6F command (Get compact headers)
heinrichsweikamp
parents: 346
diff changeset
553 movlw 0x09
346
cf9ce6053dee New option to download "Compact Headers". Improved BLE support (OSTC 2 and OSTC 3+), updated OSTC interface documentation
heinrichsweikamp
parents: 337
diff changeset
554 movwf ext_flash_address+0
cf9ce6053dee New option to download "Compact Headers". Improved BLE support (OSTC 2 and OSTC 3+), updated OSTC interface documentation
heinrichsweikamp
parents: 337
diff changeset
555 ; Adjust address for next dive
cf9ce6053dee New option to download "Compact Headers". Improved BLE support (OSTC 2 and OSTC 3+), updated OSTC interface documentation
heinrichsweikamp
parents: 337
diff changeset
556 movlw 0x10
cf9ce6053dee New option to download "Compact Headers". Improved BLE support (OSTC 2 and OSTC 3+), updated OSTC interface documentation
heinrichsweikamp
parents: 337
diff changeset
557 addwf ext_flash_address+1
cf9ce6053dee New option to download "Compact Headers". Improved BLE support (OSTC 2 and OSTC 3+), updated OSTC interface documentation
heinrichsweikamp
parents: 337
diff changeset
558 movlw 0x00
cf9ce6053dee New option to download "Compact Headers". Improved BLE support (OSTC 2 and OSTC 3+), updated OSTC interface documentation
heinrichsweikamp
parents: 337
diff changeset
559 addwfc ext_flash_address+2
cf9ce6053dee New option to download "Compact Headers". Improved BLE support (OSTC 2 and OSTC 3+), updated OSTC interface documentation
heinrichsweikamp
parents: 337
diff changeset
560
cf9ce6053dee New option to download "Compact Headers". Improved BLE support (OSTC 2 and OSTC 3+), updated OSTC interface documentation
heinrichsweikamp
parents: 337
diff changeset
561 movlw 0x30
560
b7eb98dbd800 bump to 2.96beta (REFACTORED VERSION)
heinrichsweikamp
parents: 512
diff changeset
562 cpfseq ext_flash_address+2 ; All 256 dive send?
b7eb98dbd800 bump to 2.96beta (REFACTORED VERSION)
heinrichsweikamp
parents: 512
diff changeset
563 bra comm_send_compact_headers4 ; No, continue
b7eb98dbd800 bump to 2.96beta (REFACTORED VERSION)
heinrichsweikamp
parents: 512
diff changeset
564 bra comm_download_mode0 ; Done. Loop with timeout reset
346
cf9ce6053dee New option to download "Compact Headers". Improved BLE support (OSTC 2 and OSTC 3+), updated OSTC interface documentation
heinrichsweikamp
parents: 337
diff changeset
565
cf9ce6053dee New option to download "Compact Headers". Improved BLE support (OSTC 2 and OSTC 3+), updated OSTC interface documentation
heinrichsweikamp
parents: 337
diff changeset
566 comm_send_compact_headers4:
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
567 movlw .13
346
cf9ce6053dee New option to download "Compact Headers". Improved BLE support (OSTC 2 and OSTC 3+), updated OSTC interface documentation
heinrichsweikamp
parents: 337
diff changeset
568 movwf lo ; Counter
560
b7eb98dbd800 bump to 2.96beta (REFACTORED VERSION)
heinrichsweikamp
parents: 512
diff changeset
569 rcall comm_rs232_wait_tx ; Wait for UART
346
cf9ce6053dee New option to download "Compact Headers". Improved BLE support (OSTC 2 and OSTC 3+), updated OSTC interface documentation
heinrichsweikamp
parents: 337
diff changeset
570 call ext_flash_read_block_start ; 1st byte
cf9ce6053dee New option to download "Compact Headers". Improved BLE support (OSTC 2 and OSTC 3+), updated OSTC interface documentation
heinrichsweikamp
parents: 337
diff changeset
571 movwf TXREG1
cf9ce6053dee New option to download "Compact Headers". Improved BLE support (OSTC 2 and OSTC 3+), updated OSTC interface documentation
heinrichsweikamp
parents: 337
diff changeset
572 bra comm_send_compact_headers3 ; counter 24bit
cf9ce6053dee New option to download "Compact Headers". Improved BLE support (OSTC 2 and OSTC 3+), updated OSTC interface documentation
heinrichsweikamp
parents: 337
diff changeset
573 comm_send_compact_headers_loop:
cf9ce6053dee New option to download "Compact Headers". Improved BLE support (OSTC 2 and OSTC 3+), updated OSTC interface documentation
heinrichsweikamp
parents: 337
diff changeset
574 call ext_flash_read_block ; Read one byte
cf9ce6053dee New option to download "Compact Headers". Improved BLE support (OSTC 2 and OSTC 3+), updated OSTC interface documentation
heinrichsweikamp
parents: 337
diff changeset
575 movwf TXREG1 ; Start new transmit
cf9ce6053dee New option to download "Compact Headers". Improved BLE support (OSTC 2 and OSTC 3+), updated OSTC interface documentation
heinrichsweikamp
parents: 337
diff changeset
576 comm_send_compact_headers3:
560
b7eb98dbd800 bump to 2.96beta (REFACTORED VERSION)
heinrichsweikamp
parents: 512
diff changeset
577 rcall comm_rs232_wait_tx ; Wait for UART
346
cf9ce6053dee New option to download "Compact Headers". Improved BLE support (OSTC 2 and OSTC 3+), updated OSTC interface documentation
heinrichsweikamp
parents: 337
diff changeset
578 decfsz lo,F
cf9ce6053dee New option to download "Compact Headers". Improved BLE support (OSTC 2 and OSTC 3+), updated OSTC interface documentation
heinrichsweikamp
parents: 337
diff changeset
579 bra comm_send_compact_headers_loop
cf9ce6053dee New option to download "Compact Headers". Improved BLE support (OSTC 2 and OSTC 3+), updated OSTC interface documentation
heinrichsweikamp
parents: 337
diff changeset
580 call ext_flash_read_block_stop
347
7e5772df60cd Changed content for new 0x6F command (Get compact headers)
heinrichsweikamp
parents: 346
diff changeset
581
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
582 ; Offset to total dive counter
356
fcf3ae0fee6a Changed content for new 0x6F command (Get compact headers)
heinrichsweikamp
parents: 354
diff changeset
583 movlw .80
fcf3ae0fee6a Changed content for new 0x6F command (Get compact headers)
heinrichsweikamp
parents: 354
diff changeset
584 movwf ext_flash_address+0
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
585 call ext_flash_read_block_start ; 1st byte
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
586 movwf TXREG1
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
587 rcall comm_rs232_wait_tx ; Wait for UART
356
fcf3ae0fee6a Changed content for new 0x6F command (Get compact headers)
heinrichsweikamp
parents: 354
diff changeset
588 call ext_flash_read_block ; 2nd byte
fcf3ae0fee6a Changed content for new 0x6F command (Get compact headers)
heinrichsweikamp
parents: 354
diff changeset
589 movwf TXREG1
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
590 call ext_flash_read_block_stop
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
591 rcall comm_rs232_wait_tx ; Wait for UART
356
fcf3ae0fee6a Changed content for new 0x6F command (Get compact headers)
heinrichsweikamp
parents: 354
diff changeset
592
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
593 ; Offset to Logbook-Profile version
391
682199d87b5c add profile version to compact headers
heinrichsweikamp
parents: 378
diff changeset
594 movlw .8
682199d87b5c add profile version to compact headers
heinrichsweikamp
parents: 378
diff changeset
595 movwf ext_flash_address+0
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
596 call ext_flash_byte_read ; Get byte
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
597 movwf TXREG1
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
598 rcall comm_rs232_wait_tx ; Wait for UART
560
b7eb98dbd800 bump to 2.96beta (REFACTORED VERSION)
heinrichsweikamp
parents: 512
diff changeset
599 bra comm_send_compact_headers2 ; continue
346
cf9ce6053dee New option to download "Compact Headers". Improved BLE support (OSTC 2 and OSTC 3+), updated OSTC interface documentation
heinrichsweikamp
parents: 337
diff changeset
600
cf9ce6053dee New option to download "Compact Headers". Improved BLE support (OSTC 2 and OSTC 3+), updated OSTC interface documentation
heinrichsweikamp
parents: 337
diff changeset
601
cf9ce6053dee New option to download "Compact Headers". Improved BLE support (OSTC 2 and OSTC 3+), updated OSTC interface documentation
heinrichsweikamp
parents: 337
diff changeset
602 ;-----------------------------------------------------------------------------
cf9ce6053dee New option to download "Compact Headers". Improved BLE support (OSTC 2 and OSTC 3+), updated OSTC interface documentation
heinrichsweikamp
parents: 337
diff changeset
603
0
heinrichsweikamp
parents:
diff changeset
604 comm_send_headers:
560
b7eb98dbd800 bump to 2.96beta (REFACTORED VERSION)
heinrichsweikamp
parents: 512
diff changeset
605 movlw "a" ; send echo
0
heinrichsweikamp
parents:
diff changeset
606 movwf TXREG1
heinrichsweikamp
parents:
diff changeset
607 ; Send 256 bytes/dive (Header)
heinrichsweikamp
parents:
diff changeset
608 ; 1st: 200000h-2000FFh
heinrichsweikamp
parents:
diff changeset
609 ; 2nd: 201000h-2010FFh
heinrichsweikamp
parents:
diff changeset
610 ; 3rd: 202000h-2020FFh
heinrichsweikamp
parents:
diff changeset
611 ; 100: 264000h-2640FFh
heinrichsweikamp
parents:
diff changeset
612 ; 256: 2FF000h-2FF0FFh
heinrichsweikamp
parents:
diff changeset
613 movlw 0x1F
heinrichsweikamp
parents:
diff changeset
614 movwf ext_flash_address+2
heinrichsweikamp
parents:
diff changeset
615 movlw 0xF0
heinrichsweikamp
parents:
diff changeset
616 movwf ext_flash_address+1
heinrichsweikamp
parents:
diff changeset
617 comm_send_headers2:
560
b7eb98dbd800 bump to 2.96beta (REFACTORED VERSION)
heinrichsweikamp
parents: 512
diff changeset
618 clrf ext_flash_address+0
0
heinrichsweikamp
parents:
diff changeset
619 ; Adjust address for next dive
heinrichsweikamp
parents:
diff changeset
620 movlw 0x10
heinrichsweikamp
parents:
diff changeset
621 addwf ext_flash_address+1
heinrichsweikamp
parents:
diff changeset
622 movlw 0x00
heinrichsweikamp
parents:
diff changeset
623 addwfc ext_flash_address+2
heinrichsweikamp
parents:
diff changeset
624 movlw 0x30
560
b7eb98dbd800 bump to 2.96beta (REFACTORED VERSION)
heinrichsweikamp
parents: 512
diff changeset
625 cpfseq ext_flash_address+2 ; All 256 dive send?
0
heinrichsweikamp
parents:
diff changeset
626 bra comm_send_headers4 ; No, continue
560
b7eb98dbd800 bump to 2.96beta (REFACTORED VERSION)
heinrichsweikamp
parents: 512
diff changeset
627 bra comm_download_mode0 ; Done. Loop with timeout reset
0
heinrichsweikamp
parents:
diff changeset
628 comm_send_headers4:
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
629 clrf lo ; Counter
560
b7eb98dbd800 bump to 2.96beta (REFACTORED VERSION)
heinrichsweikamp
parents: 512
diff changeset
630 rcall comm_rs232_wait_tx ; Wait for UART
0
heinrichsweikamp
parents:
diff changeset
631 call ext_flash_read_block_start ; 1st byte
heinrichsweikamp
parents:
diff changeset
632 movwf TXREG1
560
b7eb98dbd800 bump to 2.96beta (REFACTORED VERSION)
heinrichsweikamp
parents: 512
diff changeset
633 bra comm_send_headers3 ; counter 24bit
0
heinrichsweikamp
parents:
diff changeset
634 comm_send_headers_loop:
heinrichsweikamp
parents:
diff changeset
635 call ext_flash_read_block ; Read one byte
heinrichsweikamp
parents:
diff changeset
636 movwf TXREG1 ; Start new transmit
heinrichsweikamp
parents:
diff changeset
637 comm_send_headers3:
560
b7eb98dbd800 bump to 2.96beta (REFACTORED VERSION)
heinrichsweikamp
parents: 512
diff changeset
638 rcall comm_rs232_wait_tx ; Wait for UART
0
heinrichsweikamp
parents:
diff changeset
639 decfsz lo,F
heinrichsweikamp
parents:
diff changeset
640 bra comm_send_headers_loop
heinrichsweikamp
parents:
diff changeset
641 call ext_flash_read_block_stop
560
b7eb98dbd800 bump to 2.96beta (REFACTORED VERSION)
heinrichsweikamp
parents: 512
diff changeset
642 bra comm_send_headers2 ; continue
0
heinrichsweikamp
parents:
diff changeset
643
heinrichsweikamp
parents:
diff changeset
644 ;-----------------------------------------------------------------------------
80
db920ca01491 new commands in download mode:
mh@mh-THINK.localdomain
parents: 79
diff changeset
645
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
646 comm_option_reset_all: ; Reset all options to factory default.
560
b7eb98dbd800 bump to 2.96beta (REFACTORED VERSION)
heinrichsweikamp
parents: 512
diff changeset
647 movlw "x" ; send echo
80
db920ca01491 new commands in download mode:
mh@mh-THINK.localdomain
parents: 79
diff changeset
648 movwf TXREG1
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
649 call option_reset_all
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
650 bra comm_download_mode0 ; Done. back to loop with timeout reset
80
db920ca01491 new commands in download mode:
mh@mh-THINK.localdomain
parents: 79
diff changeset
651
db920ca01491 new commands in download mode:
mh@mh-THINK.localdomain
parents: 79
diff changeset
652 ;-----------------------------------------------------------------------------
0
heinrichsweikamp
parents:
diff changeset
653
350
2fd258596af0 some cleanups
heinrichsweikamp
parents: 347
diff changeset
654 comm_write_get_byte:
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
655 goto rs232_get_byte ; returns...
350
2fd258596af0 some cleanups
heinrichsweikamp
parents: 347
diff changeset
656
354
043890f06bce some cleanups
heinrichsweikamp
parents: 350
diff changeset
657 comm_rs232_wait_tx:
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
658 goto rs232_wait_tx ; returns...
350
2fd258596af0 some cleanups
heinrichsweikamp
parents: 347
diff changeset
659
0
heinrichsweikamp
parents:
diff changeset
660 comm_set_time:
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
661 movlw "b" ; send echo
0
heinrichsweikamp
parents:
diff changeset
662 movwf TXREG1
heinrichsweikamp
parents:
diff changeset
663
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
664 rcall comm_rs232_wait_tx ; wait for UART
350
2fd258596af0 some cleanups
heinrichsweikamp
parents: 347
diff changeset
665 rcall comm_write_get_byte
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
666 btfsc rs232_receive_overflow ; Got byte?
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
667 bra comm_download_mode0 ; No, abort
0
heinrichsweikamp
parents:
diff changeset
668 movff RCREG1, hours
heinrichsweikamp
parents:
diff changeset
669 movlw d'24'
heinrichsweikamp
parents:
diff changeset
670 cpfslt hours
heinrichsweikamp
parents:
diff changeset
671 clrf hours
350
2fd258596af0 some cleanups
heinrichsweikamp
parents: 347
diff changeset
672 rcall comm_write_get_byte
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
673 btfsc rs232_receive_overflow ; Got byte?
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
674 bra comm_download_mode0 ; No, abort
0
heinrichsweikamp
parents:
diff changeset
675 movff RCREG1, mins
heinrichsweikamp
parents:
diff changeset
676 movlw d'60'
heinrichsweikamp
parents:
diff changeset
677 cpfslt mins
heinrichsweikamp
parents:
diff changeset
678 clrf mins
350
2fd258596af0 some cleanups
heinrichsweikamp
parents: 347
diff changeset
679 rcall comm_write_get_byte
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
680 btfsc rs232_receive_overflow ; Got byte?
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
681 bra comm_download_mode0 ; No, abort
0
heinrichsweikamp
parents:
diff changeset
682 movff RCREG1, secs
heinrichsweikamp
parents:
diff changeset
683 movlw d'60'
heinrichsweikamp
parents:
diff changeset
684 cpfslt secs
heinrichsweikamp
parents:
diff changeset
685 clrf secs
350
2fd258596af0 some cleanups
heinrichsweikamp
parents: 347
diff changeset
686 rcall comm_write_get_byte
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
687 btfsc rs232_receive_overflow ; Got byte?
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
688 bra comm_download_mode0 ; No, abort
0
heinrichsweikamp
parents:
diff changeset
689 movff RCREG1, month
heinrichsweikamp
parents:
diff changeset
690 movlw d'13'
heinrichsweikamp
parents:
diff changeset
691 cpfslt month
heinrichsweikamp
parents:
diff changeset
692 movwf month
350
2fd258596af0 some cleanups
heinrichsweikamp
parents: 347
diff changeset
693 rcall comm_write_get_byte
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
694 btfsc rs232_receive_overflow ; Got byte?
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
695 bra comm_download_mode0 ; No, abort
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
696 call comm_check_day ; Check day
350
2fd258596af0 some cleanups
heinrichsweikamp
parents: 347
diff changeset
697 rcall comm_write_get_byte
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
698 btfsc rs232_receive_overflow ; Got byte?
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
699 bra comm_download_mode0 ; No, abort
0
heinrichsweikamp
parents:
diff changeset
700 movff RCREG1, year
heinrichsweikamp
parents:
diff changeset
701 movlw d'100'
heinrichsweikamp
parents:
diff changeset
702 cpfslt year
heinrichsweikamp
parents:
diff changeset
703 clrf year
heinrichsweikamp
parents:
diff changeset
704 ; All ok, set RTCC
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
705 call rtc_set_rtc ; writes mins,sec,hours,day,month and year to RTC module
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
706 bra comm_download_mode0 ; Done. back to loop with timeout reset
0
heinrichsweikamp
parents:
diff changeset
707
heinrichsweikamp
parents:
diff changeset
708 ;-----------------------------------------------------------------------------
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
709 ; Set OSTC3 custom text string (opt_name_length ASCII chars).
0
heinrichsweikamp
parents:
diff changeset
710 ;
heinrichsweikamp
parents:
diff changeset
711
heinrichsweikamp
parents:
diff changeset
712 comm_set_custom_text:
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
713 movlw "c" ; send echo
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
714 movwf TXREG1
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
715 rcall comm_rs232_wait_tx ; wait for UART
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
716 lfsr FSR2,opt_name
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
717 movlw opt_name_length
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
718 movwf lo ; counter
0
heinrichsweikamp
parents:
diff changeset
719 comm_set_ctext_loop:
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
720 rcall comm_write_get_byte
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
721 btfsc rs232_receive_overflow ; Got byte?
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
722 bra comm_set_ctext_loop_done ; no, abort
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
723 movff RCREG1,POSTINC2 ; Store character
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
724 decfsz lo,F
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
725 bra comm_set_ctext_loop
136
9a637c9bb19a rename Deco Planner to Simulator
heinrichsweikamp
parents: 128
diff changeset
726 comm_set_ctext_loop_done:
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
727 tstfsz lo ; Got opt_name_length bytes?
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
728 bra comm_set_ctext_loop_done2 ; no, clear remaining chars
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
729 bra comm_download_mode0 ; Done. Loop with timeout reset
136
9a637c9bb19a rename Deco Planner to Simulator
heinrichsweikamp
parents: 128
diff changeset
730 comm_set_ctext_loop_done2:
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
731 clrf POSTINC2
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
732 decfsz lo,F
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
733 bra comm_set_ctext_loop_done2
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
734 bra comm_download_mode0 ; Done. Loop with timeout reset
0
heinrichsweikamp
parents:
diff changeset
735
heinrichsweikamp
parents:
diff changeset
736 ;-----------------------------------------------------------------------------
heinrichsweikamp
parents:
diff changeset
737 ; Reply Serial (2 bytes low:high), firmware (major.minor) and custom text.
heinrichsweikamp
parents:
diff changeset
738 ;
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
739
0
heinrichsweikamp
parents:
diff changeset
740 comm_identify:
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
741 movlw "i" ; send echo
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
742 movwf TXREG1
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
743 rcall comm_rs232_wait_tx ; wait for UART
0
heinrichsweikamp
parents:
diff changeset
744
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
745 ;---- Read serial from internal EEPROM address 0000
0
heinrichsweikamp
parents:
diff changeset
746 clrf EEADRH
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
747 clrf EEADR ; Get Serial number LOW
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
748 call read_eeprom ; read byte
0
heinrichsweikamp
parents:
diff changeset
749 movff EEDATA,lo
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
750 incf EEADR,F ; Get Serial number HIGH
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
751 call read_eeprom ; read byte
0
heinrichsweikamp
parents:
diff changeset
752 movff EEDATA,hi
heinrichsweikamp
parents:
diff changeset
753
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
754 ;---- Emit serial number
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
755 movff lo,TXREG1
354
043890f06bce some cleanups
heinrichsweikamp
parents: 350
diff changeset
756 rcall comm_rs232_wait_tx
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
757 movff hi,TXREG1
354
043890f06bce some cleanups
heinrichsweikamp
parents: 350
diff changeset
758 rcall comm_rs232_wait_tx
0
heinrichsweikamp
parents:
diff changeset
759
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
760 ;---- Emit firmware hi.lo
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
761 movlw softwareversion_x
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
762 movwf TXREG1
354
043890f06bce some cleanups
heinrichsweikamp
parents: 350
diff changeset
763 rcall comm_rs232_wait_tx
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
764 movlw softwareversion_y
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
765 movwf TXREG1
354
043890f06bce some cleanups
heinrichsweikamp
parents: 350
diff changeset
766 rcall comm_rs232_wait_tx
0
heinrichsweikamp
parents:
diff changeset
767
heinrichsweikamp
parents:
diff changeset
768 ;---- Emit custom text
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
769 movlw opt_name_length
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
770 movwf hi
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
771 lfsr FSR2,opt_name
0
heinrichsweikamp
parents:
diff changeset
772
heinrichsweikamp
parents:
diff changeset
773 common_identify_loop:
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
774 movff POSTINC2,TXREG1
354
043890f06bce some cleanups
heinrichsweikamp
parents: 350
diff changeset
775 rcall comm_rs232_wait_tx
0
heinrichsweikamp
parents:
diff changeset
776 decfsz hi,F
heinrichsweikamp
parents:
diff changeset
777 bra common_identify_loop
heinrichsweikamp
parents:
diff changeset
778
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
779 bra comm_download_mode0 ; Done.
0
heinrichsweikamp
parents:
diff changeset
780
235
23311219dacc under construction: new hardware_flag to configure different hardware versions
heinrichsweikamp
parents: 223
diff changeset
781 ;-----------------------------------------------------------------------------
23311219dacc under construction: new hardware_flag to configure different hardware versions
heinrichsweikamp
parents: 223
diff changeset
782 ; Reply hardware descriptor byte
23311219dacc under construction: new hardware_flag to configure different hardware versions
heinrichsweikamp
parents: 223
diff changeset
783 ;
23311219dacc under construction: new hardware_flag to configure different hardware versions
heinrichsweikamp
parents: 223
diff changeset
784
23311219dacc under construction: new hardware_flag to configure different hardware versions
heinrichsweikamp
parents: 223
diff changeset
785 comm_hardware_descriptor:
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
786 movlw "j" ; send echo
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
787 movwf TXREG1
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
788 rcall comm_rs232_wait_tx ; wait for UART
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
789 movff hardware_flag,TXREG1
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
790 bra comm_download_mode0 ; Done.
0
heinrichsweikamp
parents:
diff changeset
791
441
360acdcda0d7 +BUGFIX: Compatibility with "hwOS Config" fixed
heinrichsweikamp
parents: 426
diff changeset
792 comm_feature_and_hardware:
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
793 movlw 0x60 ; send echo
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
794 movwf TXREG1
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
795 rcall comm_rs232_wait_tx ; wait for UART
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
796 movlw 0x00 ; Hardware high byte
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
797 movwf TXREG1
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
798 rcall comm_rs232_wait_tx ; wait for UART
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
799 movff hardware_flag,TXREG1
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
800 rcall comm_rs232_wait_tx ; wait for UART
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
801 movlw 0x00 ; Feature high Byte
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
802 movwf TXREG1
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
803 rcall comm_rs232_wait_tx ; wait for UART
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
804 movlw 0x00 ; Feature low Byte
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
805 movwf TXREG1
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
806 rcall comm_rs232_wait_tx ; wait for UART
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
807 movlw 0x00 ; Model descriptor byte
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
808 movwf TXREG1
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
809 bra comm_download_mode0 ; Done.
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
810
0
heinrichsweikamp
parents:
diff changeset
811 ;-----------------------------------------------------------------------------
heinrichsweikamp
parents:
diff changeset
812
heinrichsweikamp
parents:
diff changeset
813 comm_send_dive:
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
814 movlw "f"; 0x66 ; send echo
0
heinrichsweikamp
parents:
diff changeset
815 movwf TXREG1
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
816
350
2fd258596af0 some cleanups
heinrichsweikamp
parents: 347
diff changeset
817 rcall comm_write_get_byte
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
818 btfsc rs232_receive_overflow ; Got byte?
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
819 bra comm_download_mode0 ; No, abort!
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
820 movff RCREG1,lo ; Store dive number (0-255)
0
heinrichsweikamp
parents:
diff changeset
821 ; First, send the header (again)
heinrichsweikamp
parents:
diff changeset
822 ; Set ext_flash_address:3 to TOC entry of this dive
heinrichsweikamp
parents:
diff changeset
823 ; 1st: 200000h-200FFFh -> lo=0
heinrichsweikamp
parents:
diff changeset
824 ; 2nd: 201000h-201FFFh -> lo=1
heinrichsweikamp
parents:
diff changeset
825 ; 3rd: 202000h-202FFFh -> lo=2
heinrichsweikamp
parents:
diff changeset
826 ; 256: 2FF000h-2FFFFFh -> lo=255
heinrichsweikamp
parents:
diff changeset
827 clrf ext_flash_address+0
heinrichsweikamp
parents:
diff changeset
828 clrf ext_flash_address+1
heinrichsweikamp
parents:
diff changeset
829 movlw 0x20
heinrichsweikamp
parents:
diff changeset
830 movwf ext_flash_address+2
heinrichsweikamp
parents:
diff changeset
831 movlw .16
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
832 mulwf lo ; lo*16 = offset to 0x2000 (up:hi)
0
heinrichsweikamp
parents:
diff changeset
833 movf PRODL,W
heinrichsweikamp
parents:
diff changeset
834 addwf ext_flash_address+1,F
heinrichsweikamp
parents:
diff changeset
835 movf PRODH,W
heinrichsweikamp
parents:
diff changeset
836 addwfc ext_flash_address+2,F
heinrichsweikamp
parents:
diff changeset
837
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
838 incf_ext_flash_address d'2' ; Skip 0xFA, 0xFA
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
839 call ext_flash_byte_read_plus ; Read start address of profile
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
840 movff ext_flash_rw,ext_flash_log_pointer+0
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
841 call ext_flash_byte_read_plus ; Read start address of profile
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
842 movff ext_flash_rw,ext_flash_log_pointer+1
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
843 call ext_flash_byte_read_plus ; Read start address of profile
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
844 movff ext_flash_rw,ext_flash_log_pointer+2
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
845 call ext_flash_byte_read_plus ; Read end address of profile
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
846 movff ext_flash_rw,ext_flash_end_pointer+0
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
847 call ext_flash_byte_read_plus ; Read end address of profile
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
848 movff ext_flash_rw,ext_flash_end_pointer+1
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
849 call ext_flash_byte_read_plus ; Read end address of profile
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
850 movff ext_flash_rw,ext_flash_end_pointer+2
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
851 decf_ext_flash_address d'8' ; Back again to first 0xFA in header
0
heinrichsweikamp
parents:
diff changeset
852
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
853 movf ext_flash_log_pointer+0,W
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
854 cpfseq ext_flash_end_pointer+0 ; Equal?
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
855 bra comm_send_dive1 ; No, Send header
0
heinrichsweikamp
parents:
diff changeset
856
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
857 movf ext_flash_log_pointer+1,W
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
858 cpfseq ext_flash_end_pointer+1 ; Equal?
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
859 bra comm_send_dive1 ; No, Send header
0
heinrichsweikamp
parents:
diff changeset
860
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
861 movf ext_flash_log_pointer+2,W
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
862 cpfseq ext_flash_end_pointer+2 ; Equal?
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
863 bra comm_send_dive1 ; No, Send header
0
heinrichsweikamp
parents:
diff changeset
864
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
865 ; Start=End -> Not good, abort
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
866 bra comm_download_mode0 ; Done. Loop with timeout reset
0
heinrichsweikamp
parents:
diff changeset
867
heinrichsweikamp
parents:
diff changeset
868 comm_send_dive1:
heinrichsweikamp
parents:
diff changeset
869 ; Send header
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
870 clrf hi ; Counter
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
871 rcall comm_rs232_wait_tx ; Wait for UART
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
872 call ext_flash_read_block_start ; 1st byte
0
heinrichsweikamp
parents:
diff changeset
873 movwf TXREG1
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
874 bra comm_send_dive_header
0
heinrichsweikamp
parents:
diff changeset
875 comm_send_dive_header2:
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
876 call ext_flash_read_block ; Read one byte
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
877 movwf TXREG1 ; Start new transmit
0
heinrichsweikamp
parents:
diff changeset
878 comm_send_dive_header:
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
879 rcall comm_rs232_wait_tx ; Wait for UART
0
heinrichsweikamp
parents:
diff changeset
880 decfsz hi,F
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
881 bra comm_send_dive_header2
0
heinrichsweikamp
parents:
diff changeset
882 call ext_flash_read_block_stop
heinrichsweikamp
parents:
diff changeset
883
heinrichsweikamp
parents:
diff changeset
884 ; Set address for profile
heinrichsweikamp
parents:
diff changeset
885 movff ext_flash_log_pointer+0,ext_flash_address+0
heinrichsweikamp
parents:
diff changeset
886 movff ext_flash_log_pointer+1,ext_flash_address+1
heinrichsweikamp
parents:
diff changeset
887 movff ext_flash_log_pointer+2,ext_flash_address+2
heinrichsweikamp
parents:
diff changeset
888
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
889 movlw .6 ; Skip 6byte short header in profile - only for internal use
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
890 call incf_ext_flash_address0_0x20 ; increases bytes in ext_flash_address:3 with 0x200000 bank switching
0
heinrichsweikamp
parents:
diff changeset
891
512
heinrichsweikamp
parents: 507
diff changeset
892 ; Set address for short header/compact header, Byte 0
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
893
0
heinrichsweikamp
parents:
diff changeset
894 comm_send_dive_profile:
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
895 call ext_flash_byte_read_plus_0x20 ; Read one byte into ext_flash_rw, takes care of banking at 0x200000
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
896 rcall comm_rs232_wait_tx ; Wait for UART
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
897 movff ext_flash_rw,TXREG1 ; Send a byte
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
898
0
heinrichsweikamp
parents:
diff changeset
899 ; 24bit compare with end address
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
900 movff ext_flash_end_pointer+0,WREG
0
heinrichsweikamp
parents:
diff changeset
901 cpfseq ext_flash_address+0
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
902 bra comm_send_dive_profile
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
903 movff ext_flash_end_pointer+1,WREG
0
heinrichsweikamp
parents:
diff changeset
904 cpfseq ext_flash_address+1
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
905 bra comm_send_dive_profile
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
906 movff ext_flash_end_pointer+2,WREG
0
heinrichsweikamp
parents:
diff changeset
907 cpfseq ext_flash_address+2
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
908 bra comm_send_dive_profile
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
909
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
910 rcall comm_read_setting_wait ; Wait for UART
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
911 bra comm_download_mode0 ; Done. Loop with timeout reset
0
heinrichsweikamp
parents:
diff changeset
912
heinrichsweikamp
parents:
diff changeset
913 ;-----------------------------------------------------------------------------
heinrichsweikamp
parents:
diff changeset
914
79
0fc8113ddf6d new command in download mode: "r" - read setting
mh@mh-THINK.localdomain
parents: 69
diff changeset
915 comm_read_setting:
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
916 movlw "r"
79
0fc8113ddf6d new command in download mode: "r" - read setting
mh@mh-THINK.localdomain
parents: 69
diff changeset
917 movwf TXREG1
350
2fd258596af0 some cleanups
heinrichsweikamp
parents: 347
diff changeset
918 rcall comm_write_get_byte
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
919 btfsc rs232_receive_overflow ; Got byte?
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
920 bra comm_read_abort ; No, abort!
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
921 rcall comm_read_setting_wait ; Wait for UART
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
922 movlw 0x0F
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
923 cpfsgt RCREG1 ; 0x00-0x0F: unused
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
924 bra comm_read_abort ; abort!
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
925 subwf RCREG1,W ; Subtract unused commands
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
926 dcfsnz WREG
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
927 bra comm_read_gas1 ; RCREG1=0x10
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
928 dcfsnz WREG
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
929 bra comm_read_gas2 ; RCREG1=0x11
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
930 dcfsnz WREG
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
931 bra comm_read_gas3 ; RCREG1=0x12
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
932 dcfsnz WREG
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
933 bra comm_read_gas4 ; RCREG1=0x13
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
934 dcfsnz WREG
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
935 bra comm_read_gas5 ; RCREG1=0x14
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
936 dcfsnz WREG
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
937 bra comm_read_dil1 ; RCREG1=0x15
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
938 dcfsnz WREG
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
939 bra comm_read_dil2 ; RCREG1=0x16
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
940 dcfsnz WREG
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
941 bra comm_read_dil3 ; RCREG1=0x17
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
942 dcfsnz WREG
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
943 bra comm_read_dil4 ; RCREG1=0x18
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
944 dcfsnz WREG
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
945 bra comm_read_dil5 ; RCREG1=0x19
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
946 dcfsnz WREG
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
947 bra comm_read_sp1 ; RCREG1=0x1A
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
948 dcfsnz WREG
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
949 bra comm_read_sp2 ; RCREG1=0x1B
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
950 dcfsnz WREG
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
951 bra comm_read_sp3 ; RCREG1=0x1C
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
952 dcfsnz WREG
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
953 bra comm_read_sp4 ; RCREG1=0x1D
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
954 dcfsnz WREG
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
955 bra comm_read_sp5 ; RCREG1=0x1E
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
956 dcfsnz WREG
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
957 movff opt_ccr_mode, TXREG1 ; RCREG1=0x1F
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
958 dcfsnz WREG
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
959 movff opt_dive_mode, TXREG1 ; RCREG1=0x20
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
960 dcfsnz WREG
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
961 movff char_I_deco_model, TXREG1 ; RCREG1=0x21
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
962 dcfsnz WREG
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
963 movff char_I_ppO2_max, TXREG1 ; RCREG1=0x22
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
964 dcfsnz WREG
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
965 movff char_I_ppO2_min, TXREG1 ; RCREG1=0x23
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
966 dcfsnz WREG
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
967 movff char_I_extra_time, TXREG1 ; RCREG1=0x24
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
968 dcfsnz WREG
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
969 movff opt_GF_low, TXREG1 ; RCREG1=0x25
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
970 dcfsnz WREG
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
971 movff opt_GF_high, TXREG1 ; RCREG1=0x26
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
972 dcfsnz WREG
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
973 movff opt_aGF_low, TXREG1 ; RCREG1=0x27
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
974 dcfsnz WREG
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
975 movff opt_aGF_high, TXREG1 ; RCREG1=0x28
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
976 dcfsnz WREG
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
977 movff opt_enable_aGF, TXREG1 ; RCREG1=0x29
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
978 dcfsnz WREG
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
979 movff opt_sat_multiplier_non_gf, TXREG1 ; RCREG1=0x2A
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
980 dcfsnz WREG
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
981 movff opt_desat_multiplier_non_gf, TXREG1 ; RCREG1=0x2B
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
982 dcfsnz WREG
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
983 movff opt_last_stop, TXREG1 ; RCREG1=0x2C
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
984 dcfsnz WREG
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
985 movff opt_brightness, TXREG1 ; RCREG1=0x2D
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
986 dcfsnz WREG
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
987 movff opt_units, TXREG1 ; RCREG1=0x2E
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
988 dcfsnz WREG
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
989 movff opt_sampling_rate, TXREG1 ; RCREG1=0x2F
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
990 dcfsnz WREG
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
991 movff opt_salinity, TXREG1 ; RCREG1=0x30
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
992 dcfsnz WREG
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
993 movff opt_dive_color_scheme, TXREG1 ; RCREG1=0x31
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
994 dcfsnz WREG
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
995 movff opt_language, TXREG1 ; RCREG1=0x32
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
996 dcfsnz WREG
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
997 movff opt_dateformat, TXREG1 ; RCREG1=0x33
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
998 dcfsnz WREG
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
999 movff opt_compass_gain, TXREG1 ; RCREG1=0x34
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1000 dcfsnz WREG
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1001 movff opt_pressure_adjust, TXREG1 ; RCREG1=0x35
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1002 dcfsnz WREG
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1003 movff opt_enable_safetystop, TXREG1 ; RCREG1=0x36
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1004 dcfsnz WREG
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1005 movff opt_calibration_O2_ratio, TXREG1; RCREG1=0x37
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1006 dcfsnz WREG
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1007 clrf TXREG1 ; RCREG1=0x38 NOT USED ANYMORE (ex opt_sensor_fallback)
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1008 dcfsnz WREG
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1009 movff opt_flip_screen, TXREG1 ; RCREG1=0x39
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1010 dcfsnz WREG
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1011 movff opt_cR_button_left, TXREG1 ; RCREG1=0x3A
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1012 dcfsnz WREG
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1013 movff opt_cR_button_right, TXREG1 ; RCREG1=0x3B
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1014 dcfsnz WREG
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1015 movff char_I_bottom_usage, TXREG1 ; RCREG1=0x3C
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1016 dcfsnz WREG
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1017 movff char_I_deco_usage, TXREG1 ; RCREG1=0x3D
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1018 dcfsnz WREG
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1019 movff opt_modwarning, TXREG1 ; RCREG1=0x3E
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1020 dcfsnz WREG
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1021 movff opt_vsitextv2, TXREG1 ; RCREG1=0x3F
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1022 dcfsnz WREG
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1023 movff opt_vsigraph, TXREG1 ; RCREG1=0x40
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1024 dcfsnz WREG
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1025 movff opt_showppo2, TXREG1 ; RCREG1=0x41
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1026 dcfsnz WREG
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1027 movff opt_temperature_adjust, TXREG1 ; RCREG1=0x42
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1028 dcfsnz WREG
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1029 movff opt_safety_stop_length, TXREG1 ; RCREG1=0x43
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1030 dcfsnz WREG
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1031 movff opt_safety_stop_start, TXREG1 ; RCREG1=0x44
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1032 dcfsnz WREG
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1033 movff opt_safety_stop_end, TXREG1 ; RCREG1=0x45
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1034 dcfsnz WREG
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1035 movff opt_safety_stop_reset, TXREG1 ; RCREG1=0x46
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1036 dcfsnz WREG
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1037 clrf TXREG1 ; RCREG1=0x47, ignore conservatism for standard hwOS
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1038 dcfsnz WREG
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1039 movff opt_diveTimeout, TXREG1 ; RCREG1=0x48
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1040 dcfsnz WREG
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1041 movff button_polarity, TXREG1 ; RCREG1=0x49
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1042 dcfsnz WREG
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1043 movff char_I_PSCR_drop, TXREG1 ; RCREG1=0x4A
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1044 dcfsnz WREG
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1045 movff char_I_PSCR_lungratio, TXREG1 ; RCREG1=0x4B
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1046 dcfsnz WREG
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1047 movff char_I_ppO2_max_deco, TXREG1 ; RCREG1=0x4C
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1048 dcfsnz WREG
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1049 movff char_I_ppO2_min_loop, TXREG1 ; RCREG1=0x4D
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1050 dcfsnz WREG
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1051 movff char_I_tank_size+0, TXREG1 ; RCREG1=0x4E
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1052 dcfsnz WREG
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1053 movff char_I_tank_size+1, TXREG1 ; RCREG1=0x4F
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1054 dcfsnz WREG
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1055 movff char_I_tank_size+2, TXREG1 ; RCREG1=0x50
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1056 dcfsnz WREG
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1057 movff char_I_tank_size+3, TXREG1 ; RCREG1=0x51
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1058 dcfsnz WREG
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1059 movff char_I_tank_size+4, TXREG1 ; RCREG1=0x52
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1060 dcfsnz WREG
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1061 movff char_I_tank_pres_fill+0, TXREG1 ; RCREG1=0x53
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1062 dcfsnz WREG
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1063 movff char_I_tank_pres_fill+1, TXREG1 ; RCREG1=0x54
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1064 dcfsnz WREG
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1065 movff char_I_tank_pres_fill+2, TXREG1 ; RCREG1=0x55
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1066 dcfsnz WREG
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1067 movff char_I_tank_pres_fill+3, TXREG1 ; RCREG1=0x56
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1068 dcfsnz WREG
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1069 movff char_I_tank_pres_fill+4, TXREG1 ; RCREG1=0x57
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1070 dcfsnz WREG
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1071 movff char_I_cc_max_frac_o2, TXREG1 ; RCREG1=0x58
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1072 dcfsnz WREG
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1073 movff opt_sim_setpoint_number, TXREG1 ; RCREG1=0x59
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1074 dcfsnz WREG
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1075 movff opt_calc_asc_gasvolume, TXREG1 ; RCREG1=0x5A
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1076 dcfsnz WREG
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1077 movff opt_sim_use_aGF, TXREG1 ; RCREG1=0x5B
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1078 dcfsnz WREG
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1079 movff char_I_altitude_wait, TXREG1 ; RCREG1=0x5C
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1080 dcfsnz WREG
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1081 movff opt_enable_IBCD, TXREG1 ; RCREG1=0x5D
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1082 dcfsnz WREG
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1083 movff opt_sat_multiplier_gf, TXREG1 ; RCREG1=0x5E
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1084 dcfsnz WREG
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1085 movff opt_desat_multiplier_gf, TXREG1; RCREG1=0x5F
562
8b7ea27ea1fa seperate desat and sat multipliers for GF and Non-GF modes. Set to 100/100 as default in GF mode
heinrichsweikamp
parents: 560
diff changeset
1086
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1087
79
0fc8113ddf6d new command in download mode: "r" - read setting
mh@mh-THINK.localdomain
parents: 69
diff changeset
1088 comm_read_abort:
255
ad62dff7739a add bearing option to compass
heinrichsweikamp
parents: 252
diff changeset
1089 comm_read_done:
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1090 bra comm_download_mode0 ; Done. Loop with timeout reset
79
0fc8113ddf6d new command in download mode: "r" - read setting
mh@mh-THINK.localdomain
parents: 69
diff changeset
1091
0fc8113ddf6d new command in download mode: "r" - read setting
mh@mh-THINK.localdomain
parents: 69
diff changeset
1092 comm_read_setting_wait:
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1093 bra comm_rs232_wait_tx ; Wait for UART (and return!)
157
5ee76921e359 make new parameters configurable through pc
heinrichsweikamp
parents: 150
diff changeset
1094
79
0fc8113ddf6d new command in download mode: "r" - read setting
mh@mh-THINK.localdomain
parents: 69
diff changeset
1095 comm_read_gas1:
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1096 movff opt_gas_O2_ratio+0, TXREG1
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1097 rcall comm_read_setting_wait ; Wait for UART
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1098 movff opt_gas_He_ratio+0, TXREG1
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1099 rcall comm_read_setting_wait ; Wait for UART
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1100 movff opt_gas_type+0, TXREG1
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1101 rcall comm_read_setting_wait ; Wait for UART
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1102 movff opt_OC_bail_gas_change+0,TXREG1
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1103 bra comm_read_done ; Done. Wait for UART and loop with timeout reset
79
0fc8113ddf6d new command in download mode: "r" - read setting
mh@mh-THINK.localdomain
parents: 69
diff changeset
1104 comm_read_gas2:
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1105 movff opt_gas_O2_ratio+1, TXREG1
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1106 rcall comm_read_setting_wait ; Wait for UART
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1107 movff opt_gas_He_ratio+1, TXREG1
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1108 rcall comm_read_setting_wait ; Wait for UART
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1109 movff opt_gas_type+1, TXREG1
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1110 rcall comm_read_setting_wait ; Wait for UART
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1111 movff opt_OC_bail_gas_change+1,TXREG1
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1112 bra comm_read_done ; Done. Wait for UART and loop with timeout reset
79
0fc8113ddf6d new command in download mode: "r" - read setting
mh@mh-THINK.localdomain
parents: 69
diff changeset
1113 comm_read_gas3:
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1114 movff opt_gas_O2_ratio+2, TXREG1
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1115 rcall comm_read_setting_wait ; Wait for UART
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1116 movff opt_gas_He_ratio+2, TXREG1
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1117 rcall comm_read_setting_wait ; Wait for UART
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1118 movff opt_gas_type+2, TXREG1
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1119 rcall comm_read_setting_wait ; Wait for UART
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1120 movff opt_OC_bail_gas_change+2,TXREG1
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1121 bra comm_read_done ; Done. Wait for UART and loop with timeout reset
79
0fc8113ddf6d new command in download mode: "r" - read setting
mh@mh-THINK.localdomain
parents: 69
diff changeset
1122 comm_read_gas4:
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1123 movff opt_gas_O2_ratio+3, TXREG1
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1124 rcall comm_read_setting_wait ; Wait for UART
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1125 movff opt_gas_He_ratio+3, TXREG1
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1126 rcall comm_read_setting_wait ; Wait for UART
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1127 movff opt_gas_type+3, TXREG1
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1128 rcall comm_read_setting_wait ; Wait for UART
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1129 movff opt_OC_bail_gas_change+3,TXREG1
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1130 bra comm_read_done ; Done. Wait for UART and loop with timeout reset
79
0fc8113ddf6d new command in download mode: "r" - read setting
mh@mh-THINK.localdomain
parents: 69
diff changeset
1131 comm_read_gas5:
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1132 movff opt_gas_O2_ratio+4, TXREG1
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1133 rcall comm_read_setting_wait ; Wait for UART
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1134 movff opt_gas_He_ratio+4, TXREG1
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1135 rcall comm_read_setting_wait ; Wait for UART
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1136 movff opt_gas_type+4, TXREG1
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1137 rcall comm_read_setting_wait ; Wait for UART
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1138 movff opt_OC_bail_gas_change+4,TXREG1
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1139 bra comm_read_done ; Done. Wait for UART and loop with timeout reset
79
0fc8113ddf6d new command in download mode: "r" - read setting
mh@mh-THINK.localdomain
parents: 69
diff changeset
1140
0fc8113ddf6d new command in download mode: "r" - read setting
mh@mh-THINK.localdomain
parents: 69
diff changeset
1141 comm_read_dil1:
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1142 movff opt_dil_O2_ratio+0, TXREG1
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1143 rcall comm_read_setting_wait ; Wait for UART
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1144 movff opt_dil_He_ratio+0, TXREG1
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1145 rcall comm_read_setting_wait ; Wait for UART
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1146 movff opt_dil_type+0, TXREG1
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1147 rcall comm_read_setting_wait ; Wait for UART
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1148 movff char_I_dil_change+0,TXREG1
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1149 bra comm_read_done ; Done. Wait for UART and loop with timeout reset
79
0fc8113ddf6d new command in download mode: "r" - read setting
mh@mh-THINK.localdomain
parents: 69
diff changeset
1150 comm_read_dil2:
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1151 movff opt_dil_O2_ratio+1, TXREG1
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1152 rcall comm_read_setting_wait ; Wait for UART
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1153 movff opt_dil_He_ratio+1, TXREG1
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1154 rcall comm_read_setting_wait ; Wait for UART
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1155 movff opt_dil_type+1, TXREG1
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1156 rcall comm_read_setting_wait ; Wait for UART
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1157 movff char_I_dil_change+1,TXREG1
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1158 bra comm_read_done ; Done. Wait for UART and loop with timeout reset
79
0fc8113ddf6d new command in download mode: "r" - read setting
mh@mh-THINK.localdomain
parents: 69
diff changeset
1159 comm_read_dil3:
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1160 movff opt_dil_O2_ratio+2, TXREG1
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1161 rcall comm_read_setting_wait ; Wait for UART
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1162 movff opt_dil_He_ratio+2, TXREG1
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1163 rcall comm_read_setting_wait ; Wait for UART
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1164 movff opt_dil_type+2, TXREG1
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1165 rcall comm_read_setting_wait ; Wait for UART
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1166 movff char_I_dil_change+2,TXREG1
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1167 bra comm_read_done ; Done. Wait for UART and loop with timeout reset
79
0fc8113ddf6d new command in download mode: "r" - read setting
mh@mh-THINK.localdomain
parents: 69
diff changeset
1168 comm_read_dil4:
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1169 movff opt_dil_O2_ratio+3, TXREG1
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1170 rcall comm_read_setting_wait ; Wait for UART
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1171 movff opt_dil_He_ratio+3, TXREG1
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1172 rcall comm_read_setting_wait ; Wait for UART
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1173 movff opt_dil_type+3, TXREG1
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1174 rcall comm_read_setting_wait ; Wait for UART
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1175 movff char_I_dil_change+3,TXREG1
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1176 bra comm_read_done ; Done. Wait for UART and loop with timeout reset
79
0fc8113ddf6d new command in download mode: "r" - read setting
mh@mh-THINK.localdomain
parents: 69
diff changeset
1177 comm_read_dil5:
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1178 movff opt_dil_O2_ratio+4, TXREG1
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1179 rcall comm_read_setting_wait ; Wait for UART
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1180 movff opt_dil_He_ratio+4, TXREG1
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1181 rcall comm_read_setting_wait ; Wait for UART
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1182 movff opt_dil_type+4, TXREG1
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1183 rcall comm_read_setting_wait ; Wait for UART
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1184 movff char_I_dil_change+4,TXREG1
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1185 bra comm_read_done ; Done. Wait for UART and loop with timeout reset
79
0fc8113ddf6d new command in download mode: "r" - read setting
mh@mh-THINK.localdomain
parents: 69
diff changeset
1186
0fc8113ddf6d new command in download mode: "r" - read setting
mh@mh-THINK.localdomain
parents: 69
diff changeset
1187 comm_read_sp1:
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1188 movff char_I_setpoint_cbar+0, TXREG1
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1189 rcall comm_read_setting_wait ; Wait for UART
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1190 movff char_I_setpoint_change+0, TXREG1
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1191 bra comm_read_done ; Done. Wait for UART and loop with timeout reset
79
0fc8113ddf6d new command in download mode: "r" - read setting
mh@mh-THINK.localdomain
parents: 69
diff changeset
1192 comm_read_sp2:
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1193 movff char_I_setpoint_cbar+1, TXREG1
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1194 rcall comm_read_setting_wait ; Wait for UART
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1195 movff char_I_setpoint_change+1, TXREG1
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1196 bra comm_read_done ; Done. Wait for UART and loop with timeout reset
79
0fc8113ddf6d new command in download mode: "r" - read setting
mh@mh-THINK.localdomain
parents: 69
diff changeset
1197 comm_read_sp3:
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1198 movff char_I_setpoint_cbar+2, TXREG1
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1199 rcall comm_read_setting_wait ; Wait for UART
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1200 movff char_I_setpoint_change+2, TXREG1
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1201 bra comm_read_done ; Done. Wait for UART and loop with timeout reset
79
0fc8113ddf6d new command in download mode: "r" - read setting
mh@mh-THINK.localdomain
parents: 69
diff changeset
1202 comm_read_sp4:
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1203 movff char_I_setpoint_cbar+3, TXREG1
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1204 rcall comm_read_setting_wait ; Wait for UART
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1205 movff char_I_setpoint_change+3, TXREG1
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1206 bra comm_read_done ; Done. Wait for UART and loop with timeout reset
79
0fc8113ddf6d new command in download mode: "r" - read setting
mh@mh-THINK.localdomain
parents: 69
diff changeset
1207 comm_read_sp5:
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1208 movff char_I_setpoint_cbar+4, TXREG1
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1209 rcall comm_read_setting_wait ; Wait for UART
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1210 movff char_I_setpoint_change+4, TXREG1
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1211 bra comm_read_done ; Done. Wait for UART and loop with timeout reset
110
d39493c786a2 BUGFIX: OSTC settings via USB issues
heinrichsweikamp
parents: 97
diff changeset
1212
79
0fc8113ddf6d new command in download mode: "r" - read setting
mh@mh-THINK.localdomain
parents: 69
diff changeset
1213
80
db920ca01491 new commands in download mode:
mh@mh-THINK.localdomain
parents: 79
diff changeset
1214 ;-----------------------------------------------------------------------------
238
49512af55afc cleanup
heinrichsweikamp
parents: 235
diff changeset
1215 comm_write_gas1:
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1216 movff RCREG1,opt_gas_O2_ratio+0
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1217 rcall comm_write_get_byte
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1218 movff RCREG1,opt_gas_He_ratio+0
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1219 rcall comm_write_get_byte
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1220 movff RCREG1,opt_gas_type+0
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1221 rcall comm_write_get_byte
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1222 movff RCREG1,opt_OC_bail_gas_change+0
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1223 bra comm_write_abort ; Done. Loop with timeout reset
238
49512af55afc cleanup
heinrichsweikamp
parents: 235
diff changeset
1224 comm_write_gas2:
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1225 movff RCREG1,opt_gas_O2_ratio+1
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1226 rcall comm_write_get_byte
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1227 movff RCREG1,opt_gas_He_ratio+1
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1228 rcall comm_write_get_byte
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1229 movff RCREG1,opt_gas_type+1
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1230 rcall comm_write_get_byte
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1231 movff RCREG1,opt_OC_bail_gas_change+1
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1232 bra comm_write_abort ; Done. Loop with timeout reset
238
49512af55afc cleanup
heinrichsweikamp
parents: 235
diff changeset
1233 comm_write_gas3:
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1234 movff RCREG1,opt_gas_O2_ratio+2
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1235 rcall comm_write_get_byte
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1236 movff RCREG1,opt_gas_He_ratio+2
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1237 rcall comm_write_get_byte
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1238 movff RCREG1,opt_gas_type+2
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1239 rcall comm_write_get_byte
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1240 movff RCREG1,opt_OC_bail_gas_change+2
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1241 bra comm_write_abort ; Done. Loop with timeout reset
238
49512af55afc cleanup
heinrichsweikamp
parents: 235
diff changeset
1242 comm_write_gas4:
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1243 movff RCREG1,opt_gas_O2_ratio+3
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1244 rcall comm_write_get_byte
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1245 movff RCREG1,opt_gas_He_ratio+3
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1246 rcall comm_write_get_byte
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1247 movff RCREG1,opt_gas_type+3
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1248 rcall comm_write_get_byte
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1249 movff RCREG1,opt_OC_bail_gas_change+3
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1250 bra comm_write_abort ; Done. Loop with timeout reset
238
49512af55afc cleanup
heinrichsweikamp
parents: 235
diff changeset
1251 comm_write_gas5:
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1252 movff RCREG1,opt_gas_O2_ratio+4
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1253 rcall comm_write_get_byte
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1254 movff RCREG1,opt_gas_He_ratio+4
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1255 rcall comm_write_get_byte
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1256 movff RCREG1,opt_gas_type+4
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1257 rcall comm_write_get_byte
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1258 movff RCREG1,opt_OC_bail_gas_change+4
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1259 bra comm_write_abort ; Done. Loop with timeout reset
80
db920ca01491 new commands in download mode:
mh@mh-THINK.localdomain
parents: 79
diff changeset
1260
db920ca01491 new commands in download mode:
mh@mh-THINK.localdomain
parents: 79
diff changeset
1261
db920ca01491 new commands in download mode:
mh@mh-THINK.localdomain
parents: 79
diff changeset
1262 comm_write_setting:
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1263 movlw "w"
80
db920ca01491 new commands in download mode:
mh@mh-THINK.localdomain
parents: 79
diff changeset
1264 movwf TXREG1
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1265 rcall comm_write_get_byte ; "Byte 2"
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1266 btfsc rs232_receive_overflow ; Got byte?
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1267 bra comm_write_abort ; No, abort!
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1268 movff RCREG1,lo ; Copy
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1269 rcall comm_write_get_byte ; "Byte 3"
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1270 rcall comm_read_setting_wait ; Wait for UART
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1271 movlw 0x0F
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1272 cpfsgt lo ; 0x00-0x0F: unused
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1273 bra comm_write_abort ; abort!
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1274 subwf lo,W ; Subtract unused commands
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1275 dcfsnz WREG
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1276 bra comm_write_gas1 ; RCREG1=0x10
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1277 dcfsnz WREG
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1278 bra comm_write_gas2 ; RCREG1=0x11
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1279 dcfsnz WREG
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1280 bra comm_write_gas3 ; RCREG1=0x12
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1281 dcfsnz WREG
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1282 bra comm_write_gas4 ; RCREG1=0x13
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1283 dcfsnz WREG
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1284 bra comm_write_gas5 ; RCREG1=0x14
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1285 dcfsnz WREG
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1286 bra comm_write_dil1 ; RCREG1=0x15
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1287 dcfsnz WREG
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1288 bra comm_write_dil2 ; RCREG1=0x16
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1289 dcfsnz WREG
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1290 bra comm_write_dil3 ; RCREG1=0x17
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1291 dcfsnz WREG
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1292 bra comm_write_dil4 ; RCREG1=0x18
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1293 dcfsnz WREG
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1294 bra comm_write_dil5 ; RCREG1=0x19
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1295 dcfsnz WREG
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1296 bra comm_write_sp1 ; RCREG1=0x1A
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1297 dcfsnz WREG
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1298 bra comm_write_sp2 ; RCREG1=0x1B
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1299 dcfsnz WREG
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1300 bra comm_write_sp3 ; RCREG1=0x1C
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1301 dcfsnz WREG
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1302 bra comm_write_sp4 ; RCREG1=0x1D
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1303 dcfsnz WREG
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1304 bra comm_write_sp5 ; RCREG1=0x1E
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1305 dcfsnz WREG
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1306 movff RCREG1, opt_ccr_mode ; RCREG1=0x1F
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1307 dcfsnz WREG
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1308 movff RCREG1, opt_dive_mode ; RCREG1=0x20
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1309 dcfsnz WREG
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1310 movff RCREG1, char_I_deco_model ; RCREG1=0x21
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1311 dcfsnz WREG
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1312 movff RCREG1, char_I_ppO2_max ; RCREG1=0x22
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1313 dcfsnz WREG
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1314 movff RCREG1, char_I_ppO2_min ; RCREG1=0x23
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1315 dcfsnz WREG
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1316 movff RCREG1, char_I_extra_time ; RCREG1=0x24
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1317 dcfsnz WREG
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1318 movff RCREG1, opt_GF_low ; RCREG1=0x25
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1319 dcfsnz WREG
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1320 movff RCREG1, opt_GF_high ; RCREG1=0x26
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1321 dcfsnz WREG
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1322 movff RCREG1, opt_aGF_low ; RCREG1=0x27
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1323 dcfsnz WREG
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1324 movff RCREG1, opt_aGF_high ; RCREG1=0x28
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1325 dcfsnz WREG
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1326 movff RCREG1, opt_enable_aGF ; RCREG1=0x29
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1327 dcfsnz WREG
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1328 movff RCREG1, opt_sat_multiplier_non_gf ; RCREG1=0x2A
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1329 dcfsnz WREG
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1330 movff RCREG1, opt_desat_multiplier_non_gf ; RCREG1=0x2B
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1331 dcfsnz WREG
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1332 movff RCREG1, opt_last_stop ; RCREG1=0x2C
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1333 dcfsnz WREG
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1334 movff RCREG1, opt_brightness ; RCREG1=0x2D
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1335 dcfsnz WREG
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1336 movff RCREG1, opt_units ; RCREG1=0x2E
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1337 dcfsnz WREG
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1338 movff RCREG1, opt_sampling_rate ; RCREG1=0x2F
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1339 dcfsnz WREG
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1340 movff RCREG1, opt_salinity ; RCREG1=0x30
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1341 dcfsnz WREG
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1342 movff RCREG1, opt_dive_color_scheme ; RCREG1=0x31
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1343 dcfsnz WREG
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1344 movff RCREG1, opt_language ; RCREG1=0x32
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1345 dcfsnz WREG
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1346 movff RCREG1, opt_dateformat ; RCREG1=0x33
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1347 dcfsnz WREG
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1348 movff RCREG1, opt_compass_gain ; RCREG1=0x34
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1349 dcfsnz WREG
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1350 movff RCREG1, opt_pressure_adjust ; RCREG1=0x35
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1351 dcfsnz WREG
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1352 movff RCREG1, opt_enable_safetystop ; RCREG1=0x36
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1353 dcfsnz WREG
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1354 movff RCREG1, opt_calibration_O2_ratio; RCREG1=0x37
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1355 dcfsnz WREG
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1356 nop ; RCREG1=0x38 NOT USED ANYMORE (ex opt_sensor_fallback)
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1357 dcfsnz WREG
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1358 movff RCREG1, opt_flip_screen ; RCREG1=0x39
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1359 dcfsnz WREG
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1360 movff RCREG1, opt_cR_button_left ; RCREG1=0x3A
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1361 dcfsnz WREG
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1362 movff RCREG1, opt_cR_button_right ; RCREG1=0x3B
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1363 dcfsnz WREG
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1364 movff RCREG1, char_I_bottom_usage ; RCREG1=0x3C
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1365 dcfsnz WREG
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1366 movff RCREG1, char_I_deco_usage ; RCREG1=0x3D
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1367 dcfsnz WREG
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1368 movff RCREG1, opt_modwarning ; RCREG1=0x3E
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1369 dcfsnz WREG
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1370 movff RCREG1, opt_vsitextv2 ; RCREG1=0x3F
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1371 dcfsnz WREG
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1372 movff RCREG1, opt_vsigraph ; RCREG1=0x40
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1373 dcfsnz WREG
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1374 movff RCREG1, opt_showppo2 ; RCREG1=0x41
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1375 dcfsnz WREG
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1376 movff RCREG1, opt_temperature_adjust ; RCREG1=0x42
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1377 dcfsnz WREG
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1378 movff RCREG1, opt_safety_stop_length ; RCREG1=0x43
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1379 dcfsnz WREG
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1380 movff RCREG1, opt_safety_stop_start ; RCREG1=0x44
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1381 dcfsnz WREG
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1382 movff RCREG1, opt_safety_stop_end ; RCREG1=0x45
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1383 dcfsnz WREG
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1384 movff RCREG1, opt_safety_stop_reset ; RCREG1=0x46
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1385 dcfsnz WREG
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1386 nop ; RCREG1=0x47, ignore conservatism for standard hwOS
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1387 dcfsnz WREG
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1388 movff RCREG1, opt_diveTimeout ; RCREG1=0x48
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1389 dcfsnz WREG
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1390 bra comm_write_button_polarity ; RCREG1=0x49
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1391 dcfsnz WREG
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1392 movff RCREG1, char_I_PSCR_drop ; RCREG1=0x4A
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1393 dcfsnz WREG
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1394 movff RCREG1, char_I_PSCR_lungratio ; RCREG1=0x4B
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1395 dcfsnz WREG
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1396 movff RCREG1, char_I_ppO2_max_deco ; RCREG1=0x4C
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1397 dcfsnz WREG
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1398 movff RCREG1, char_I_ppO2_min_loop ; RCREG1=0x4D
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1399 dcfsnz WREG
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1400 movff RCREG1, char_I_tank_size+0 ; RCREG1=0x4E
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1401 dcfsnz WREG
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1402 movff RCREG1, char_I_tank_size+1 ; RCREG1=0x4F
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1403 dcfsnz WREG
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1404 movff RCREG1, char_I_tank_size+2 ; RCREG1=0x50
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1405 dcfsnz WREG
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1406 movff RCREG1, char_I_tank_size+3 ; RCREG1=0x51
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1407 dcfsnz WREG
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1408 movff RCREG1, char_I_tank_size+4 ; RCREG1=0x52
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1409 dcfsnz WREG
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1410 movff RCREG1, char_I_tank_pres_fill+0 ; RCREG1=0x53
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1411 dcfsnz WREG
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1412 movff RCREG1, char_I_tank_pres_fill+1 ; RCREG1=0x54
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1413 dcfsnz WREG
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1414 movff RCREG1, char_I_tank_pres_fill+2 ; RCREG1=0x55
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1415 dcfsnz WREG
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1416 movff RCREG1, char_I_tank_pres_fill+3 ; RCREG1=0x56
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1417 dcfsnz WREG
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1418 movff RCREG1, char_I_tank_pres_fill+4 ; RCREG1=0x57
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1419 dcfsnz WREG
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1420 movff RCREG1, char_I_cc_max_frac_o2 ; RCREG1=0x58
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1421 dcfsnz WREG
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1422 movff RCREG1, opt_sim_setpoint_number ; RCREG1=0x59
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1423 dcfsnz WREG
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1424 movff RCREG1, opt_calc_asc_gasvolume ; RCREG1=0x5A
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1425 dcfsnz WREG
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1426 movff RCREG1, opt_sim_use_aGF ; RCREG1=0x5B
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1427 dcfsnz WREG
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1428 movff RCREG1, char_I_altitude_wait ; RCREG1=0x5C
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1429 dcfsnz WREG
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1430 movff RCREG1, opt_enable_IBCD ; RCREG1=0x5D
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1431 dcfsnz WREG
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1432 movff RCREG1, opt_sat_multiplier_gf ; RCREG1=0x5E
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1433 dcfsnz WREG
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1434 movff RCREG1, opt_desat_multiplier_gf ; RCREG1=0x5F
560
b7eb98dbd800 bump to 2.96beta (REFACTORED VERSION)
heinrichsweikamp
parents: 512
diff changeset
1435
562
8b7ea27ea1fa seperate desat and sat multipliers for GF and Non-GF modes. Set to 100/100 as default in GF mode
heinrichsweikamp
parents: 560
diff changeset
1436
80
db920ca01491 new commands in download mode:
mh@mh-THINK.localdomain
parents: 79
diff changeset
1437 comm_write_abort:
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1438 ; Check Options, gases and diluents
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1439 call option_check_all ; Check all options (and reset if not within their min/max boundaries)
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1440 bsf ccr_diluent_setup ; =1: Setting up Diluents ("Gas6-10")
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1441 call gaslist_cleanup_list ; Takes care that only one gas can be first and first has 0m change depth
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1442 bcf ccr_diluent_setup ; =1: Setting up Diluents ("Gas6-10")
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1443 call gaslist_cleanup_list ; Takes care that only one gas can be first and first has 0m change depth
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1444 call get_first_gas_to_WREG ; Makes sure at least one Gas is "First"
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1445 call get_first_dil_to_WREG ; Makes sure at least one Diluent is "First"
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1446 goto comm_download_mode0 ; Done. Loop with timeout reset
80
db920ca01491 new commands in download mode:
mh@mh-THINK.localdomain
parents: 79
diff changeset
1447
db920ca01491 new commands in download mode:
mh@mh-THINK.localdomain
parents: 79
diff changeset
1448 comm_write_dil1:
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1449 movff RCREG1,opt_dil_O2_ratio+0
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1450 rcall comm_write_get_byte
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1451 movff RCREG1,opt_dil_He_ratio+0
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1452 rcall comm_write_get_byte
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1453 movff RCREG1,opt_dil_type+0
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1454 rcall comm_write_get_byte
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1455 movff RCREG1,char_I_dil_change+0
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1456 bra comm_write_abort ; Done. Loop with timeout reset
80
db920ca01491 new commands in download mode:
mh@mh-THINK.localdomain
parents: 79
diff changeset
1457 comm_write_dil2:
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1458 movff RCREG1,opt_dil_O2_ratio+1
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1459 rcall comm_write_get_byte
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1460 movff RCREG1,opt_dil_He_ratio+1
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1461 rcall comm_write_get_byte
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1462 movff RCREG1,opt_dil_type+1
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1463 rcall comm_write_get_byte
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1464 movff RCREG1,char_I_dil_change+1
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1465 bra comm_write_abort ; Done. Loop with timeout reset
80
db920ca01491 new commands in download mode:
mh@mh-THINK.localdomain
parents: 79
diff changeset
1466 comm_write_dil3:
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1467 movff RCREG1,opt_dil_O2_ratio+2
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1468 rcall comm_write_get_byte
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1469 movff RCREG1,opt_dil_He_ratio+2
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1470 rcall comm_write_get_byte
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1471 movff RCREG1,opt_dil_type+2
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1472 rcall comm_write_get_byte
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1473 movff RCREG1,char_I_dil_change+2
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1474 bra comm_write_abort ; Done. Loop with timeout reset
80
db920ca01491 new commands in download mode:
mh@mh-THINK.localdomain
parents: 79
diff changeset
1475 comm_write_dil4:
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1476 movff RCREG1,opt_dil_O2_ratio+3
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1477 rcall comm_write_get_byte
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1478 movff RCREG1,opt_dil_He_ratio+3
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1479 rcall comm_write_get_byte
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1480 movff RCREG1,opt_dil_type+3
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1481 rcall comm_write_get_byte
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1482 movff RCREG1,char_I_dil_change+3
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1483 bra comm_write_abort ; Done. Loop with timeout reset
80
db920ca01491 new commands in download mode:
mh@mh-THINK.localdomain
parents: 79
diff changeset
1484 comm_write_dil5:
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1485 movff RCREG1,opt_dil_O2_ratio+4
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1486 rcall comm_write_get_byte
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1487 movff RCREG1,opt_dil_He_ratio+4
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1488 rcall comm_write_get_byte
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1489 movff RCREG1,opt_dil_type+4
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1490 rcall comm_write_get_byte
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1491 movff RCREG1,char_I_dil_change+4
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1492 bra comm_write_abort ; Done. Loop with timeout reset
80
db920ca01491 new commands in download mode:
mh@mh-THINK.localdomain
parents: 79
diff changeset
1493
db920ca01491 new commands in download mode:
mh@mh-THINK.localdomain
parents: 79
diff changeset
1494 comm_write_sp1:
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1495 movff RCREG1,char_I_setpoint_cbar+0
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1496 rcall comm_write_get_byte
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1497 movff RCREG1,char_I_setpoint_change+0
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1498 bra comm_write_abort ; Done. Loop with timeout reset
80
db920ca01491 new commands in download mode:
mh@mh-THINK.localdomain
parents: 79
diff changeset
1499 comm_write_sp2:
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1500 movff RCREG1,char_I_setpoint_cbar+1
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1501 rcall comm_write_get_byte
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1502 movff RCREG1,char_I_setpoint_change+1
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1503 bra comm_write_abort ; Done. Loop with timeout reset
80
db920ca01491 new commands in download mode:
mh@mh-THINK.localdomain
parents: 79
diff changeset
1504 comm_write_sp3:
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1505 movff RCREG1,char_I_setpoint_cbar+2
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1506 rcall comm_write_get_byte
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1507 movff RCREG1,char_I_setpoint_change+2
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1508 bra comm_write_abort ; Done. Loop with timeout reset
80
db920ca01491 new commands in download mode:
mh@mh-THINK.localdomain
parents: 79
diff changeset
1509 comm_write_sp4:
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1510 movff RCREG1,char_I_setpoint_cbar+3
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1511 rcall comm_write_get_byte
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1512 movff RCREG1,char_I_setpoint_change+3
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1513 bra comm_write_abort ; Done. Loop with timeout reset
80
db920ca01491 new commands in download mode:
mh@mh-THINK.localdomain
parents: 79
diff changeset
1514 comm_write_sp5:
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1515 movff RCREG1,char_I_setpoint_cbar+4
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1516 rcall comm_write_get_byte
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1517 movff RCREG1,char_I_setpoint_change+4
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1518 bra comm_write_abort ; Done. Loop with timeout reset
80
db920ca01491 new commands in download mode:
mh@mh-THINK.localdomain
parents: 79
diff changeset
1519
79
0fc8113ddf6d new command in download mode: "r" - read setting
mh@mh-THINK.localdomain
parents: 69
diff changeset
1520 ;-----------------------------------------------------------------------------
0fc8113ddf6d new command in download mode: "r" - read setting
mh@mh-THINK.localdomain
parents: 69
diff changeset
1521
0
heinrichsweikamp
parents:
diff changeset
1522 comm_send_string:
heinrichsweikamp
parents:
diff changeset
1523 movlw "n" ; send echo
heinrichsweikamp
parents:
diff changeset
1524 movwf TXREG1
560
b7eb98dbd800 bump to 2.96beta (REFACTORED VERSION)
heinrichsweikamp
parents: 512
diff changeset
1525 rcall comm_rs232_wait_tx ; Wait for UART
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1526 WIN_SMALL comm_string_column, comm_string_row
0
heinrichsweikamp
parents:
diff changeset
1527 movlw .16
heinrichsweikamp
parents:
diff changeset
1528 movwf lo ; counter
heinrichsweikamp
parents:
diff changeset
1529 comm_send_string_loop:
562
8b7ea27ea1fa seperate desat and sat multipliers for GF and Non-GF modes. Set to 100/100 as default in GF mode
heinrichsweikamp
parents: 560
diff changeset
1530 call comm_write_get_byte
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1531 btfsc rs232_receive_overflow ; Got byte?
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1532 bra comm_send_string_abort ; No, abort!
0
heinrichsweikamp
parents:
diff changeset
1533 movff RCREG1,POSTINC2 ; Store character
heinrichsweikamp
parents:
diff changeset
1534 decfsz lo,F
heinrichsweikamp
parents:
diff changeset
1535 bra comm_send_string_loop
heinrichsweikamp
parents:
diff changeset
1536 comm_send_string_abort:
heinrichsweikamp
parents:
diff changeset
1537 STRCAT_PRINT "" ; Show the text
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1538 goto comm_download_mode0 ; Done. Loop with timeout reset
0
heinrichsweikamp
parents:
diff changeset
1539
heinrichsweikamp
parents:
diff changeset
1540 ;-----------------------------------------------------------------------------
heinrichsweikamp
parents:
diff changeset
1541
heinrichsweikamp
parents:
diff changeset
1542 comm_check_day:
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1543 movff RCREG1,day
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1544 movff month,lo ; new month
0
heinrichsweikamp
parents:
diff changeset
1545 dcfsnz lo,F
heinrichsweikamp
parents:
diff changeset
1546 movlw .31
heinrichsweikamp
parents:
diff changeset
1547 dcfsnz lo,F
heinrichsweikamp
parents:
diff changeset
1548 movlw .28
heinrichsweikamp
parents:
diff changeset
1549 dcfsnz lo,F
heinrichsweikamp
parents:
diff changeset
1550 movlw .31
heinrichsweikamp
parents:
diff changeset
1551 dcfsnz lo,F
heinrichsweikamp
parents:
diff changeset
1552 movlw .30
heinrichsweikamp
parents:
diff changeset
1553 dcfsnz lo,F
heinrichsweikamp
parents:
diff changeset
1554 movlw .31
heinrichsweikamp
parents:
diff changeset
1555 dcfsnz lo,F
heinrichsweikamp
parents:
diff changeset
1556 movlw .30
heinrichsweikamp
parents:
diff changeset
1557 dcfsnz lo,F
heinrichsweikamp
parents:
diff changeset
1558 movlw .31
heinrichsweikamp
parents:
diff changeset
1559 dcfsnz lo,F
heinrichsweikamp
parents:
diff changeset
1560 movlw .31
heinrichsweikamp
parents:
diff changeset
1561 dcfsnz lo,F
heinrichsweikamp
parents:
diff changeset
1562 movlw .30
heinrichsweikamp
parents:
diff changeset
1563 dcfsnz lo,F
heinrichsweikamp
parents:
diff changeset
1564 movlw .31
heinrichsweikamp
parents:
diff changeset
1565 dcfsnz lo,F
heinrichsweikamp
parents:
diff changeset
1566 movlw .30
heinrichsweikamp
parents:
diff changeset
1567 dcfsnz lo,F
heinrichsweikamp
parents:
diff changeset
1568 movlw .31
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1569 cpfsgt day ; day ok?
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1570 return ; OK
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1571 movlw .1 ; not OK, set to 1st
0
heinrichsweikamp
parents:
diff changeset
1572 movwf day
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1573 return
0
heinrichsweikamp
parents:
diff changeset
1574
475
237afdfb4918 2.12 release candidate...
heinrichsweikamp
parents: 464
diff changeset
1575 comm_write_button_polarity:
237afdfb4918 2.12 release candidate...
heinrichsweikamp
parents: 464
diff changeset
1576 ; Store RCREG1 into EEPROM .897
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1577 movlw LOW .897
475
237afdfb4918 2.12 release candidate...
heinrichsweikamp
parents: 464
diff changeset
1578 movwf EEADR
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1579 movlw HIGH .897
475
237afdfb4918 2.12 release candidate...
heinrichsweikamp
parents: 464
diff changeset
1580 movwf EEADRH
237afdfb4918 2.12 release candidate...
heinrichsweikamp
parents: 464
diff changeset
1581 movff RCREG1,EEDATA
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1582 movff EEDATA,button_polarity ; 0xFF (Both normal), 0x00 (Both inverted), 0x01 (Left inverted only), 0x02 (Right inverted only)
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1583 call write_eeprom ; EEDATA into EEPROM@EEADR
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1584 clrf EEADRH ; Reset EEADRH
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1585 goto comm_download_mode0 ; Done. Loop with timeout reset
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1586
0
heinrichsweikamp
parents:
diff changeset
1587 ;----------------------------------------------------------------------------
582
b455b31ce022 work on 2.97 stable
heinrichsweikamp
parents: 562
diff changeset
1588 END