# HG changeset patch
# User jDG
# Date 1513602235 -3600
# Node ID 2de06b1abed31f7e2e901498c5c8a0dc558cb7de
# Parent b355f462c952d7f18b53b1ad5577eba7d3785e2d
CLEAN retrieve original startup code. reset linker script.
diff -r b355f462c952 -r 2de06b1abed3 .hgsubstate
--- a/.hgsubstate Fri Dec 15 02:06:18 2017 +0100
+++ b/.hgsubstate Mon Dec 18 14:03:55 2017 +0100
@@ -1,3 +1,3 @@
e501ab2a9b3c9c17be7ede397fbfc6904fc09be0 Common
-b306d93b7de906ac2bb2e467aedd5373671e3718 Discovery
+629a09234249d701b2a493c47d84ce2ce5af92c9 Discovery
14a446c4e560520adf6261cb68411284a3a964ab Small_CPU
diff -r b355f462c952 -r 2de06b1abed3 OtherSources/stm32f4xx_hal_msp_hw1.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/OtherSources/stm32f4xx_hal_msp_hw1.c Mon Dec 18 14:03:55 2017 +0100
@@ -0,0 +1,870 @@
+/**
+ ******************************************************************************
+ * File Name : stm32f4xx_hal_msp.c
+ * Date : 04/12/2014 15:39:26
+ * Description : This file provides code for the MSP Initialization
+ * and de-Initialization codes.
+ ******************************************************************************
+ *
+ * COPYRIGHT(c) 2014 STMicroelectronics
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal.h"
+#include "ostc.h"
+
+
+DMA_HandleTypeDef hdma_spi1_tx;
+
+DMA_HandleTypeDef hdma_spi1_rx;
+
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+
+/**
+ * Initializes the Global MSP.
+ */
+void HAL_MspInit(void)
+{
+ /* USER CODE BEGIN MspInit 0 */
+ /* USER CODE END MspInit 0 */
+
+ HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_2);
+
+ /* System interrupt init*/
+ /** SysTick_IRQn interrupt configuration
+ * use 1 by Christian
+ */
+ HAL_NVIC_SetPriority(SysTick_IRQn, 1, 0);
+
+ /* USER CODE BEGIN MspInit 1 */
+ /* always set priority right */
+ HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_2);
+ /* USER CODE END MspInit 1 */
+}
+
+void HAL_DMA2D_MspInit(DMA2D_HandleTypeDef* hdma2d)
+{
+
+ if(hdma2d->Instance==DMA2D)
+ {
+ /* USER CODE BEGIN DMA2D_MspInit 0 */
+
+ /* USER CODE END DMA2D_MspInit 0 */
+ /* Peripheral clock enable */
+ __DMA2D_CLK_ENABLE();
+ /* USER CODE BEGIN DMA2D_MspInit 1 */
+ HAL_NVIC_SetPriority(DMA2D_IRQn, 1, 2);
+ HAL_NVIC_EnableIRQ(DMA2D_IRQn);
+ /* USER CODE END DMA2D_MspInit 1 */
+ }
+
+}
+
+void HAL_DMA2D_MspDeInit(DMA2D_HandleTypeDef* hdma2d)
+{
+
+ if(hdma2d->Instance==DMA2D)
+ {
+ /* USER CODE BEGIN DMA2D_MspDeInit 0 */
+
+ /* USER CODE END DMA2D_MspDeInit 0 */
+ /* Peripheral clock disable */
+ __DMA2D_CLK_DISABLE();
+ /* USER CODE BEGIN DMA2D_MspDeInit 1 */
+ __DMA2D_RELEASE_RESET();
+ /* USER CODE END DMA2D_MspDeInit 1 */
+ }
+
+}
+
+void HAL_LTDC_MspInit(LTDC_HandleTypeDef* hltdc)
+{
+
+ GPIO_InitTypeDef GPIO_InitStruct;
+ if(hltdc->Instance==LTDC)
+ {
+ /* USER CODE BEGIN LTDC_MspInit 0 */
+ __GPIOE_CLK_ENABLE();
+ __GPIOF_CLK_ENABLE();
+ __GPIOG_CLK_ENABLE();
+ __GPIOH_CLK_ENABLE();
+ __GPIOI_CLK_ENABLE();
+
+ /* USER CODE END LTDC_MspInit 0 */
+ /* Peripheral clock enable */
+ __LTDC_CLK_ENABLE();
+
+ /**LTDC GPIO Configuration
+ PE4 ------> LTDC_B0
+ PE5 ------> LTDC_G0
+ PE6 ------> LTDC_G1
+ PI9 ------> LTDC_VSYNC
+ PI10 ------> LTDC_HSYNC
+ PF10 ------> LTDC_DE
+ PH2 ------> LTDC_R0
+ PH3 ------> LTDC_R1
+ PH8 ------> LTDC_R2
+ PH9 ------> LTDC_R3
+ PH10 ------> LTDC_R4
+ PH11 ------> LTDC_R5
+ PH12 ------> LTDC_R6
+ PG6 ------> LTDC_R7
+ PG7 ------> LTDC_CLK
+ PH13 ------> LTDC_G2
+ PH14 ------> LTDC_G3
+ PH15 ------> LTDC_G4
+ PI0 ------> LTDC_G5
+ PI1 ------> LTDC_G6
+ PI2 ------> LTDC_G7
+ PG10 ------> LTDC_B2
+ PG11 ------> LTDC_B3
+ PG12 ------> LTDC_B1
+ PI4 ------> LTDC_B4
+ PI5 ------> LTDC_B5
+ PI6 ------> LTDC_B6
+ PI7 ------> LTDC_B7
+ */
+ GPIO_InitStruct.Pin = GPIO_PIN_4|GPIO_PIN_5|GPIO_PIN_6;
+ GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+ GPIO_InitStruct.Pull = GPIO_NOPULL;
+ GPIO_InitStruct.Speed = GPIO_SPEED_LOW;
+ GPIO_InitStruct.Alternate = GPIO_AF14_LTDC;
+ HAL_GPIO_Init(GPIOE, &GPIO_InitStruct);
+
+ GPIO_InitStruct.Pin = GPIO_PIN_9|GPIO_PIN_10|GPIO_PIN_0|GPIO_PIN_1
+ |GPIO_PIN_2|GPIO_PIN_4|GPIO_PIN_5|GPIO_PIN_6
+ |GPIO_PIN_7;
+ GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+ GPIO_InitStruct.Pull = GPIO_NOPULL;
+ GPIO_InitStruct.Speed = GPIO_SPEED_LOW;
+ GPIO_InitStruct.Alternate = GPIO_AF14_LTDC;
+ HAL_GPIO_Init(GPIOI, &GPIO_InitStruct);
+
+ GPIO_InitStruct.Pin = GPIO_PIN_10;
+ GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+ GPIO_InitStruct.Pull = GPIO_NOPULL;
+ GPIO_InitStruct.Speed = GPIO_SPEED_LOW;
+ GPIO_InitStruct.Alternate = GPIO_AF14_LTDC;
+ HAL_GPIO_Init(GPIOF, &GPIO_InitStruct);
+
+ GPIO_InitStruct.Pin = GPIO_PIN_2|GPIO_PIN_3|GPIO_PIN_8|GPIO_PIN_9
+ |GPIO_PIN_10|GPIO_PIN_11|GPIO_PIN_12|GPIO_PIN_13
+ |GPIO_PIN_14|GPIO_PIN_15;
+ GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+ GPIO_InitStruct.Pull = GPIO_NOPULL;
+ GPIO_InitStruct.Speed = GPIO_SPEED_LOW;
+ GPIO_InitStruct.Alternate = GPIO_AF14_LTDC;
+ HAL_GPIO_Init(GPIOH, &GPIO_InitStruct);
+
+ GPIO_InitStruct.Pin = GPIO_PIN_6|GPIO_PIN_7|GPIO_PIN_10|GPIO_PIN_11
+ |GPIO_PIN_12;
+ GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+ GPIO_InitStruct.Pull = GPIO_NOPULL;
+ GPIO_InitStruct.Speed = GPIO_SPEED_LOW;
+ GPIO_InitStruct.Alternate = GPIO_AF14_LTDC;
+ HAL_GPIO_Init(GPIOG, &GPIO_InitStruct);
+
+ /* USER CODE BEGIN LTDC_MspInit 1 */
+
+ /* USER CODE END LTDC_MspInit 1 */
+ }
+
+}
+
+void HAL_LTDC_MspDeInit(LTDC_HandleTypeDef* hltdc)
+{
+
+ if(hltdc->Instance==LTDC)
+ {
+ /* USER CODE BEGIN LTDC_MspDeInit 0 */
+
+ /* USER CODE END LTDC_MspDeInit 0 */
+ /* Peripheral clock disable */
+ __LTDC_CLK_DISABLE();
+
+ /**LTDC GPIO Configuration
+ PE4 ------> LTDC_B0
+ PE5 ------> LTDC_G0
+ PE6 ------> LTDC_G1
+ PI9 ------> LTDC_VSYNC
+ PI10 ------> LTDC_HSYNC
+ PF10 ------> LTDC_DE
+ PH2 ------> LTDC_R0
+ PH3 ------> LTDC_R1
+ PH8 ------> LTDC_R2
+ PH9 ------> LTDC_R3
+ PH10 ------> LTDC_R4
+ PH11 ------> LTDC_R5
+ PH12 ------> LTDC_R6
+ PG6 ------> LTDC_R7
+ PG7 ------> LTDC_CLK
+ PH13 ------> LTDC_G2
+ PH14 ------> LTDC_G3
+ PH15 ------> LTDC_G4
+ PI0 ------> LTDC_G5
+ PI1 ------> LTDC_G6
+ PI2 ------> LTDC_G7
+ PG10 ------> LTDC_B2
+ PG11 ------> LTDC_B3
+ PG12 ------> LTDC_B1
+ PI4 ------> LTDC_B4
+ PI5 ------> LTDC_B5
+ PI6 ------> LTDC_B6
+ PI7 ------> LTDC_B7
+ */
+ HAL_GPIO_DeInit(GPIOE, GPIO_PIN_4|GPIO_PIN_5|GPIO_PIN_6);
+
+ HAL_GPIO_DeInit(GPIOI, GPIO_PIN_9|GPIO_PIN_10|GPIO_PIN_0|GPIO_PIN_1
+ |GPIO_PIN_2|GPIO_PIN_4|GPIO_PIN_5|GPIO_PIN_6
+ |GPIO_PIN_7);
+
+ HAL_GPIO_DeInit(GPIOF, GPIO_PIN_10);
+
+ HAL_GPIO_DeInit(GPIOH, GPIO_PIN_2|GPIO_PIN_3|GPIO_PIN_8|GPIO_PIN_9
+ |GPIO_PIN_10|GPIO_PIN_11|GPIO_PIN_12|GPIO_PIN_13
+ |GPIO_PIN_14|GPIO_PIN_15);
+
+ HAL_GPIO_DeInit(GPIOG, GPIO_PIN_6|GPIO_PIN_7|GPIO_PIN_10|GPIO_PIN_11
+ |GPIO_PIN_12);
+
+ /* USER CODE BEGIN LTDC_MspDeInit 1 */
+ __LTDC_RELEASE_RESET();
+
+ /* USER CODE END LTDC_MspDeInit 1 */
+ }
+
+}
+
+void HAL_SPI_MspInit(SPI_HandleTypeDef* hspi)
+{
+
+ GPIO_InitTypeDef GPIO_InitStruct;
+ if(hspi->Instance==SPI1)
+ {
+ /* USER CODE BEGIN SPI1_MspInit 0 */
+ __GPIOA_CLK_ENABLE();
+ __GPIOB_CLK_ENABLE();
+ __DMA2_CLK_ENABLE();
+
+ /* USER CODE END SPI1_MspInit 0 */
+ /* Peripheral clock enable */
+ __SPI1_CLK_ENABLE();
+
+ /**SPI1 GPIO Configuration
+ alt: PA4 ------> SPI1_NSS, jetzt soft
+ PA5 ------> SPI1_SCK
+ alt: PA6 ------> SPI1_MISO
+ neu: PB4 ------> SPI1_MISO
+ PA7 ------> SPI1_MOSI
+ */
+// GPIO_InitStruct.Pin = GPIO_PIN_4|GPIO_PIN_5|GPIO_PIN_6|GPIO_PIN_7;
+ GPIO_InitStruct.Pin = GPIO_PIN_5|GPIO_PIN_7;
+ GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+ GPIO_InitStruct.Pull = GPIO_NOPULL;
+ GPIO_InitStruct.Speed = GPIO_SPEED_MEDIUM;//GPIO_SPEED_LOW;
+ GPIO_InitStruct.Alternate = GPIO_AF5_SPI1;
+ HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
+ GPIO_InitStruct.Pin = GPIO_PIN_4;
+ HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
+
+ /* Peripheral DMA init*/
+
+ hdma_spi1_tx.Instance = DMA2_Stream3;
+ hdma_spi1_tx.Init.Channel = DMA_CHANNEL_3;
+ hdma_spi1_tx.Init.Direction = DMA_MEMORY_TO_PERIPH;
+ hdma_spi1_tx.Init.PeriphInc = DMA_PINC_DISABLE;
+ hdma_spi1_tx.Init.MemInc = DMA_MINC_ENABLE;
+ hdma_spi1_tx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE;
+ hdma_spi1_tx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE;
+ hdma_spi1_tx.Init.Mode = DMA_NORMAL;
+ hdma_spi1_tx.Init.Priority = DMA_PRIORITY_LOW;
+ hdma_spi1_tx.Init.FIFOMode = DMA_FIFOMODE_DISABLE;
+/* by christian */
+hdma_spi1_tx.Init.MemBurst = DMA_MBURST_INC4;
+hdma_spi1_tx.Init.PeriphBurst = DMA_PBURST_INC4;
+ HAL_DMA_Init(&hdma_spi1_tx);
+
+ __HAL_LINKDMA(hspi,hdmatx,hdma_spi1_tx);
+
+ hdma_spi1_rx.Instance = DMA2_Stream0;
+ hdma_spi1_rx.Init.Channel = DMA_CHANNEL_3;
+ hdma_spi1_rx.Init.Direction = DMA_PERIPH_TO_MEMORY;
+ hdma_spi1_rx.Init.PeriphInc = DMA_PINC_DISABLE;
+ hdma_spi1_rx.Init.MemInc = DMA_MINC_ENABLE;
+ hdma_spi1_rx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE;
+ hdma_spi1_rx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE;
+ hdma_spi1_rx.Init.Mode = DMA_NORMAL;
+ hdma_spi1_rx.Init.Priority = DMA_PRIORITY_HIGH;
+ hdma_spi1_rx.Init.FIFOMode = DMA_FIFOMODE_DISABLE;
+/* by christian */
+hdma_spi1_rx.Init.FIFOThreshold = DMA_FIFO_THRESHOLD_FULL;
+
+hdma_spi1_rx.Init.MemBurst = DMA_MBURST_INC4;
+hdma_spi1_rx.Init.PeriphBurst = DMA_PBURST_INC4;
+ HAL_DMA_Init(&hdma_spi1_rx);
+
+ __HAL_LINKDMA(hspi, hdmarx, hdma_spi1_rx);
+
+ /*##-4- Configure the NVIC for DMA #########################################*/
+ /* NVIC configuration for DMA transfer complete interrupt (SPI1_TX) */
+ HAL_NVIC_SetPriority(DMA2_Stream3_IRQn, 0, 1);
+ HAL_NVIC_EnableIRQ(DMA2_Stream3_IRQn);
+
+
+ /* NVIC configuration for DMA transfer complete interrupt (SPI1_RX) */
+ HAL_NVIC_SetPriority(DMA2_Stream0_IRQn, 0, 0);
+ HAL_NVIC_EnableIRQ(DMA2_Stream0_IRQn);
+
+ }
+ else if(hspi->Instance==SPI2)
+ {
+ /* USER CODE BEGIN SPI2_MspInit 0 */
+ __GPIOB_CLK_ENABLE();
+
+ /* USER CODE END SPI2_MspInit 0 */
+ /* Peripheral clock enable */
+ __SPI2_CLK_ENABLE();
+
+ /**SPI2 GPIO Configuration
+ PB13 ------> SPI2_SCK
+ PB14 ------> SPI2_MISO
+ PB15 ------> SPI2_MOSI
+ */
+ GPIO_InitStruct.Pin = GPIO_PIN_13|GPIO_PIN_14|GPIO_PIN_15;
+ GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+ GPIO_InitStruct.Pull = GPIO_NOPULL;
+ GPIO_InitStruct.Speed = GPIO_SPEED_LOW;
+ GPIO_InitStruct.Alternate = GPIO_AF5_SPI2;
+ HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
+
+ /* USER CODE BEGIN SPI2_MspInit 1 */
+
+ /* USER CODE END SPI2_MspInit 1 */
+ }
+ else if(hspi->Instance==SPI5)
+ {
+ /* USER CODE BEGIN SPI5_MspInit 0 */
+ __GPIOF_CLK_ENABLE();
+
+ /* USER CODE END SPI5_MspInit 0 */
+ /* Peripheral clock enable */
+ __SPI5_CLK_ENABLE();
+
+ /**SPI5 GPIO Configuration
+ PF7 ------> SPI5_SCK
+ PF8 ------> SPI5_MISO
+ PF9 ------> SPI5_MOSI
+ */
+ GPIO_InitStruct.Pin = GPIO_PIN_7|GPIO_PIN_8|GPIO_PIN_9;
+ GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+ GPIO_InitStruct.Pull = GPIO_NOPULL;
+ GPIO_InitStruct.Speed = GPIO_SPEED_MEDIUM;//GPIO_SPEED_LOW;
+ GPIO_InitStruct.Alternate = GPIO_AF5_SPI5;
+ HAL_GPIO_Init(GPIOF, &GPIO_InitStruct);
+
+ /* USER CODE BEGIN SPI5_MspInit 1 */
+
+ /* USER CODE END SPI5_MspInit 1 */
+ }
+
+}
+
+void HAL_SPI_MspDeInit(SPI_HandleTypeDef* hspi)
+{
+
+ if(hspi->Instance==SPI1)
+ {
+ /* USER CODE BEGIN SPI1_MspDeInit 0 */
+ __SPI1_FORCE_RESET();
+ __SPI1_RELEASE_RESET();
+
+ /* USER CODE END SPI1_MspDeInit 0 */
+ /* Peripheral clock disable */
+ __SPI1_CLK_DISABLE();
+
+ /**SPI1 GPIO Configuration
+ PA4 ------> SPI1_NSS
+ PA5 ------> SPI1_SCK
+ PA6 ------> SPI1_MISO
+ PA7 ------> SPI1_MOSI
+ */
+ HAL_GPIO_DeInit(GPIOA, GPIO_PIN_4|GPIO_PIN_5|GPIO_PIN_6|GPIO_PIN_7);
+
+ /* Peripheral DMA DeInit*/
+ HAL_DMA_DeInit(hspi->hdmatx);
+ HAL_DMA_DeInit(hspi->hdmarx);
+ /* USER CODE BEGIN SPI1_MspDeInit 1 */
+
+ /* USER CODE END SPI1_MspDeInit 1 */
+ }
+ else if(hspi->Instance==SPI2)
+ {
+ /* USER CODE BEGIN SPI2_MspDeInit 0 */
+
+ /* USER CODE END SPI2_MspDeInit 0 */
+ /* Peripheral clock disable */
+ __SPI2_CLK_DISABLE();
+
+ /**SPI2 GPIO Configuration
+ PB13 ------> SPI2_SCK
+ PB14 ------> SPI2_MISO
+ PB15 ------> SPI2_MOSI
+ */
+ HAL_GPIO_DeInit(GPIOB, GPIO_PIN_13|GPIO_PIN_14|GPIO_PIN_15);
+
+ /* USER CODE BEGIN SPI2_MspDeInit 1 */
+
+ /* USER CODE END SPI2_MspDeInit 1 */
+ }
+ else if(hspi->Instance==SPI5)
+ {
+ /* USER CODE BEGIN SPI5_MspDeInit 0 */
+ __SPI5_FORCE_RESET();
+ __SPI5_RELEASE_RESET();
+
+ /* USER CODE END SPI5_MspDeInit 0 */
+ /* Peripheral clock disable */
+ __SPI5_CLK_DISABLE();
+
+ /**SPI5 GPIO Configuration
+ PF7 ------> SPI5_SCK
+ PF8 ------> SPI5_MISO
+ PF9 ------> SPI5_MOSI
+ */
+ HAL_GPIO_DeInit(GPIOF, GPIO_PIN_7|GPIO_PIN_8|GPIO_PIN_9);
+
+ /* USER CODE BEGIN SPI5_MspDeInit 1 */
+
+ /* USER CODE END SPI5_MspDeInit 1 */
+ }
+
+}
+
+void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef* htim_pwm)
+{
+ GPIO_InitTypeDef GPIO_InitStruct;
+ if(htim_pwm->Instance==TIM_BACKLIGHT)
+ {
+ TIM_BACKLIGHT_GPIO_ENABLE();
+ TIM_BACKLIGHT_CLK_ENABLE();
+
+ GPIO_InitStruct.Pin = TIM_BACKLIGHT_PIN;
+ GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+ GPIO_InitStruct.Pull = GPIO_NOPULL;
+ GPIO_InitStruct.Speed = GPIO_SPEED_LOW;
+ GPIO_InitStruct.Alternate = GPIO_AF2_TIM3;
+ HAL_GPIO_Init(TIM_BACKLIGHT_GPIO_PORT, &GPIO_InitStruct);
+ }
+
+}
+
+void HAL_TIM_Base_MspInit(TIM_HandleTypeDef* htim_base)
+{
+ if(htim_base->Instance==TIMx)
+ {
+ TIMx_CLK_ENABLE();
+
+ HAL_NVIC_SetPriority(TIMx_IRQn, 2, 1);
+ HAL_NVIC_EnableIRQ(TIMx_IRQn);
+
+ }
+}
+
+void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef* htim_pwm)
+{
+
+ if(htim_pwm->Instance==TIM2)
+ {
+ /* USER CODE BEGIN TIM2_MspDeInit 0 */
+
+ /* USER CODE END TIM2_MspDeInit 0 */
+ /* Peripheral clock disable */
+ __TIM2_CLK_DISABLE();
+
+ /**TIM2 GPIO Configuration
+ PA15 ------> TIM2_CH1
+ */
+ HAL_GPIO_DeInit(GPIOA, GPIO_PIN_15);
+
+ /* USER CODE BEGIN TIM2_MspDeInit 1 */
+
+ /* USER CODE END TIM2_MspDeInit 1 */
+ }
+
+}
+
+void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef* htim_base)
+{
+
+ if(htim_base->Instance==TIM3)
+ {
+ /* USER CODE BEGIN TIM3_MspDeInit 0 */
+
+ /* USER CODE END TIM3_MspDeInit 0 */
+ /* Peripheral clock disable */
+ __TIM3_CLK_DISABLE();
+
+ /**TIM3 GPIO Configuration
+ PC7 ------> TIM3_CH2
+ */
+ HAL_GPIO_DeInit(GPIOC, GPIO_PIN_7);
+
+ /* USER CODE BEGIN TIM3_MspDeInit 1 */
+
+ /* USER CODE END TIM3_MspDeInit 1 */
+ }
+
+}
+
+void HAL_UART_MspInit(UART_HandleTypeDef* huart)
+{
+
+ GPIO_InitTypeDef GPIO_InitStruct;
+ if(huart->Instance==USART1)
+ {
+ /* USER CODE BEGIN USART1_MspInit 0 */
+ __GPIOA_CLK_ENABLE();
+
+ /* USER CODE END USART1_MspInit 0 */
+ /* Peripheral clock enable */
+ __USART1_CLK_ENABLE();
+
+ /**USART1 GPIO Configuration
+ PA9 ------> USART1_TX
+ PA10 ------> USART1_RX
+ */
+ GPIO_InitStruct.Pin = GPIO_PIN_9|GPIO_PIN_10;
+ GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+ GPIO_InitStruct.Pull = GPIO_PULLUP;
+ GPIO_InitStruct.Speed = GPIO_SPEED_FAST;//GPIO_SPEED_LOW;
+ GPIO_InitStruct.Alternate = GPIO_AF7_USART1;
+ HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
+
+ HAL_NVIC_SetPriority(USART1_IRQn, 0, 1);
+ HAL_NVIC_EnableIRQ(USART1_IRQn);
+ }
+ else if(huart->Instance==USART_IR_HUD) /* USART2 */
+ {
+ USART_IR_HUD_CLK_ENABLE();
+ USART_IR_HUD_TX_GPIO_CLK_ENABLE();
+ USART_IR_HUD_RX_GPIO_CLK_ENABLE();
+
+ /**USART2 GPIO Configuration
+ PD5 ------> USART2_TX
+ PD6 ------> USART2_RX
+ */
+
+ GPIO_InitStruct.Pin = USART_IR_HUD_TX_PIN;
+ GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+ GPIO_InitStruct.Pull = GPIO_PULLUP;
+ GPIO_InitStruct.Speed = GPIO_SPEED_LOW;
+ GPIO_InitStruct.Alternate = USART_IR_HUD_TX_AF;
+ HAL_GPIO_Init(USART_IR_HUD_TX_GPIO_PORT, &GPIO_InitStruct);
+
+ GPIO_InitStruct.Pin = USART_IR_HUD_RX_PIN;
+ GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+ GPIO_InitStruct.Pull = GPIO_PULLUP;
+ GPIO_InitStruct.Speed = GPIO_SPEED_LOW;
+ GPIO_InitStruct.Alternate = USART_IR_HUD_RX_AF;
+ HAL_GPIO_Init(USART_IR_HUD_RX_GPIO_PORT, &GPIO_InitStruct);
+
+ HAL_NVIC_SetPriority(USART_IR_HUD_IRQn, 0, 1);
+ HAL_NVIC_EnableIRQ(USART_IR_HUD_IRQn);
+ }
+ else if(huart->Instance==USART3)
+ {
+ /* USER CODE BEGIN USART3_MspInit 0 */
+
+ /* USER CODE END USART3_MspInit 0 */
+ /* Peripheral clock enable */
+ __USART3_CLK_ENABLE();
+
+ /**USART3 GPIO Configuration
+ PC10 ------> USART3_TX
+ PC11 ------> USART3_RX
+ */
+ GPIO_InitStruct.Pin = GPIO_PIN_10|GPIO_PIN_11;
+ GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+ GPIO_InitStruct.Pull = GPIO_PULLUP;
+ GPIO_InitStruct.Speed = GPIO_SPEED_LOW;
+ GPIO_InitStruct.Alternate = GPIO_AF7_USART3;
+ HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
+
+ /* USER CODE BEGIN USART3_MspInit 1 */
+
+ /* USER CODE END USART3_MspInit 1 */
+ }
+
+}
+
+void HAL_UART_MspDeInit(UART_HandleTypeDef* huart)
+{
+
+ if(huart->Instance==USART1)
+ {
+ /* USER CODE BEGIN USART1_MspDeInit 0 */
+
+ /* USER CODE END USART1_MspDeInit 0 */
+ /* Peripheral clock disable */
+ __USART1_CLK_DISABLE();
+
+ /**USART1 GPIO Configuration
+ PA9 ------> USART1_TX
+ PA10 ------> USART1_RX
+ */
+ HAL_GPIO_DeInit(GPIOA, GPIO_PIN_9|GPIO_PIN_10);
+
+ /* USER CODE BEGIN USART1_MspDeInit 1 */
+
+ /* USER CODE END USART1_MspDeInit 1 */
+ }
+ else if(huart->Instance==USART2)
+ {
+ /* USER CODE BEGIN USART2_MspDeInit 0 */
+
+ /* USER CODE END USART2_MspDeInit 0 */
+ /* Peripheral clock disable */
+ __USART2_CLK_DISABLE();
+
+ /**USART2 GPIO Configuration
+ PD5 ------> USART2_TX
+ PD6 ------> USART2_RX
+ */
+ HAL_GPIO_DeInit(GPIOD, GPIO_PIN_5|GPIO_PIN_6);
+
+ /* USER CODE BEGIN USART2_MspDeInit 1 */
+
+ /* USER CODE END USART2_MspDeInit 1 */
+ }
+ else if(huart->Instance==USART3)
+ {
+ /* USER CODE BEGIN USART3_MspDeInit 0 */
+
+ /* USER CODE END USART3_MspDeInit 0 */
+ /* Peripheral clock disable */
+ __USART3_CLK_DISABLE();
+
+ /**USART3 GPIO Configuration
+ PC10 ------> USART3_TX
+ PC11 ------> USART3_RX
+ */
+ HAL_GPIO_DeInit(GPIOC, GPIO_PIN_10|GPIO_PIN_11);
+
+ /* USER CODE BEGIN USART3_MspDeInit 1 */
+
+ /* USER CODE END USART3_MspDeInit 1 */
+ }
+
+}
+
+static int FMC_Initialized = 0;
+
+static void HAL_FMC_MspInit(void){
+ GPIO_InitTypeDef GPIO_InitStruct;
+ if (FMC_Initialized) {
+ return;
+ }
+ FMC_Initialized = 1;
+ /* Peripheral clock enable */
+ /* by christian */
+ __GPIOC_CLK_ENABLE();
+ __GPIOD_CLK_ENABLE();
+ __GPIOE_CLK_ENABLE();
+ __GPIOF_CLK_ENABLE();
+ __GPIOG_CLK_ENABLE();
+ __GPIOH_CLK_ENABLE();
+
+ __FMC_CLK_ENABLE();
+
+ /** FMC GPIO Configuration
+ PF0 ------> FMC_A0
+ PF1 ------> FMC_A1
+ PF2 ------> FMC_A2
+ PF3 ------> FMC_A3
+ PF4 ------> FMC_A4
+ PF5 ------> FMC_A5
+ PC0 ------> FMC_SDNWE
+ PF11 ------> FMC_SDNRAS
+ PF12 ------> FMC_A6
+ PF13 ------> FMC_A7
+ PF14 ------> FMC_A8
+ PF15 ------> FMC_A9
+ PG0 ------> FMC_A10
+ PG1 ------> FMC_A11
+ PE7 ------> FMC_D4
+ PE8 ------> FMC_D5
+ PE9 ------> FMC_D6
+ PE10 ------> FMC_D7
+ PE11 ------> FMC_D8
+ PE12 ------> FMC_D9
+ PE13 ------> FMC_D10
+ PE14 ------> FMC_D11
+ PE15 ------> FMC_D12
+ PH6 ------> FMC_SDNE1 neu
+ PH7 ------> FMC_SDCKE1 neu
+ PD8 ------> FMC_D13
+ PD9 ------> FMC_D14
+ PD10 ------> FMC_D15
+ PD14 ------> FMC_D0
+ PD15 ------> FMC_D1
+ PG2 ------> FMC_A12
+ PG4 ------> FMC_BA0
+ PG5 ------> FMC_BA1
+ PG8 ------> FMC_SDCLK
+ PD0 ------> FMC_D2
+ PD1 ------> FMC_D3
+ PG15 ------> FMC_SDNCAS
+ PE0 ------> FMC_NBL0
+ PE1 ------> FMC_NBL1
+ */
+
+ GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+ GPIO_InitStruct.Pull = GPIO_NOPULL;
+ GPIO_InitStruct.Speed = GPIO_SPEED_FAST;
+ GPIO_InitStruct.Alternate = GPIO_AF12_FMC;
+
+
+ GPIO_InitStruct.Pin = GPIO_PIN_0;
+ HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
+
+ GPIO_InitStruct.Pin = GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10|GPIO_PIN_14
+ |GPIO_PIN_15|GPIO_PIN_0|GPIO_PIN_1;
+ HAL_GPIO_Init(GPIOD, &GPIO_InitStruct);
+
+ GPIO_InitStruct.Pin = GPIO_PIN_7|GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10
+ |GPIO_PIN_11|GPIO_PIN_12|GPIO_PIN_13|GPIO_PIN_14
+ |GPIO_PIN_15|GPIO_PIN_0|GPIO_PIN_1;
+ HAL_GPIO_Init(GPIOE, &GPIO_InitStruct);
+
+ GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_3
+ |GPIO_PIN_4|GPIO_PIN_5|GPIO_PIN_11|GPIO_PIN_12
+ |GPIO_PIN_13|GPIO_PIN_14|GPIO_PIN_15;
+ HAL_GPIO_Init(GPIOF, &GPIO_InitStruct);
+
+ GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_4
+ |GPIO_PIN_5|GPIO_PIN_8|GPIO_PIN_15;
+ HAL_GPIO_Init(GPIOG, &GPIO_InitStruct);
+
+ GPIO_InitStruct.Pin = GPIO_PIN_6|GPIO_PIN_7;
+ HAL_GPIO_Init(GPIOH, &GPIO_InitStruct);
+
+
+}
+
+void HAL_SDRAM_MspInit(SDRAM_HandleTypeDef* hsdram){
+ HAL_FMC_MspInit();
+}
+
+static int FMC_DeInitialized = 0;
+
+static void HAL_FMC_MspDeInit(void){
+ if (FMC_DeInitialized) {
+ return;
+ }
+ FMC_DeInitialized = 1;
+ /* Peripheral clock enable */
+ __FMC_CLK_DISABLE();
+
+ /** FMC GPIO Configuration
+ PF0 ------> FMC_A0
+ PF1 ------> FMC_A1
+ PF2 ------> FMC_A2
+ PF3 ------> FMC_A3
+ PF4 ------> FMC_A4
+ PF5 ------> FMC_A5
+ PC0 ------> FMC_SDNWE
+ PF11 ------> FMC_SDNRAS
+ PF12 ------> FMC_A6
+ PF13 ------> FMC_A7
+ PF14 ------> FMC_A8
+ PF15 ------> FMC_A9
+ PG0 ------> FMC_A10
+ PG1 ------> FMC_A11
+ PE7 ------> FMC_D4
+ PE8 ------> FMC_D5
+ PE9 ------> FMC_D6
+ PE10 ------> FMC_D7
+ PE11 ------> FMC_D8
+ PE12 ------> FMC_D9
+ PE13 ------> FMC_D10
+ PE14 ------> FMC_D11
+ PE15 ------> FMC_D12
+ PH6 ------> FMC_SDNE1
+ PH7 ------> FMC_SDCKE1
+ PD8 ------> FMC_D13
+ PD9 ------> FMC_D14
+ PD10 ------> FMC_D15
+ PD14 ------> FMC_D0
+ PD15 ------> FMC_D1
+ PG2 ------> FMC_A12
+ PG4 ------> FMC_BA0
+ PG5 ------> FMC_BA1
+ PG8 ------> FMC_SDCLK
+ PD0 ------> FMC_D2
+ PD1 ------> FMC_D3
+ PG15 ------> FMC_SDNCAS
+ PE0 ------> FMC_NBL0
+ PE1 ------> FMC_NBL1
+ */
+ HAL_GPIO_DeInit(GPIOF, GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_3
+ |GPIO_PIN_4|GPIO_PIN_5|GPIO_PIN_11|GPIO_PIN_12
+ |GPIO_PIN_13|GPIO_PIN_14|GPIO_PIN_15);
+
+ HAL_GPIO_DeInit(GPIOC, GPIO_PIN_0);
+
+ HAL_GPIO_DeInit(GPIOG, GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_4
+ |GPIO_PIN_5|GPIO_PIN_8|GPIO_PIN_15);
+
+ HAL_GPIO_DeInit(GPIOE, GPIO_PIN_7|GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10
+ |GPIO_PIN_11|GPIO_PIN_12|GPIO_PIN_13|GPIO_PIN_14
+ |GPIO_PIN_15|GPIO_PIN_0|GPIO_PIN_1);
+
+ HAL_GPIO_DeInit(GPIOH, GPIO_PIN_6|GPIO_PIN_7);
+
+ HAL_GPIO_DeInit(GPIOD, GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10|GPIO_PIN_14
+ |GPIO_PIN_15|GPIO_PIN_0|GPIO_PIN_1);
+
+}
+
+void HAL_SDRAM_MspDeInit(SDRAM_HandleTypeDef* hsdram){
+ HAL_FMC_MspDeInit();
+}
+
+/* USER CODE BEGIN 1 */
+
+/* USER CODE END 1 */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff -r b355f462c952 -r 2de06b1abed3 OtherSources/stm32f4xx_hal_msp_hw2.c
--- a/OtherSources/stm32f4xx_hal_msp_hw2.c Fri Dec 15 02:06:18 2017 +0100
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,889 +0,0 @@
-/**
- ******************************************************************************
- * File Name : stm32f4xx_hal_msp.c
- * Date : 04/12/2014 15:39:26
- * Description : This file provides code for the MSP Initialization
- * and de-Initialization codes.
- ******************************************************************************
- *
- * COPYRIGHT(c) 2014 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx_hal.h"
-#include "ostc.h"
-
-
-DMA_HandleTypeDef hdma_spi1_tx;
-
-DMA_HandleTypeDef hdma_spi1_rx;
-
-/* USER CODE BEGIN 0 */
-
-/* USER CODE END 0 */
-
-/**
- * Initializes the Global MSP.
- */
-void HAL_MspInit(void)
-{
- /* USER CODE BEGIN MspInit 0 */
- /* USER CODE END MspInit 0 */
-
- HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_2);
-
- /* System interrupt init*/
- /** SysTick_IRQn interrupt configuration
- * use 1 by Christian
- */
- HAL_NVIC_SetPriority(SysTick_IRQn, 1, 0);
-
- /* USER CODE BEGIN MspInit 1 */
- /* always set priority right */
- HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_2);
- /* USER CODE END MspInit 1 */
-}
-
-void HAL_DMA2D_MspInit(DMA2D_HandleTypeDef* hdma2d)
-{
-
- if(hdma2d->Instance==DMA2D)
- {
- /* USER CODE BEGIN DMA2D_MspInit 0 */
-
- /* USER CODE END DMA2D_MspInit 0 */
- /* Peripheral clock enable */
- __DMA2D_CLK_ENABLE();
- /* USER CODE BEGIN DMA2D_MspInit 1 */
- HAL_NVIC_SetPriority(DMA2D_IRQn, 1, 2);
- HAL_NVIC_EnableIRQ(DMA2D_IRQn);
- /* USER CODE END DMA2D_MspInit 1 */
- }
-
-}
-
-void HAL_DMA2D_MspDeInit(DMA2D_HandleTypeDef* hdma2d)
-{
-
- if(hdma2d->Instance==DMA2D)
- {
- /* USER CODE BEGIN DMA2D_MspDeInit 0 */
-
- /* USER CODE END DMA2D_MspDeInit 0 */
- /* Peripheral clock disable */
- __DMA2D_CLK_DISABLE();
- /* USER CODE BEGIN DMA2D_MspDeInit 1 */
- __DMA2D_RELEASE_RESET();
- /* USER CODE END DMA2D_MspDeInit 1 */
- }
-
-}
-
-void HAL_LTDC_MspInit(LTDC_HandleTypeDef* hltdc)
-{
-
- GPIO_InitTypeDef GPIO_InitStruct;
- if(hltdc->Instance==LTDC)
- {
- /* USER CODE BEGIN LTDC_MspInit 0 */
- __GPIOE_CLK_ENABLE();
- __GPIOF_CLK_ENABLE();
- __GPIOG_CLK_ENABLE();
- __GPIOH_CLK_ENABLE();
- __GPIOI_CLK_ENABLE();
-
- /* USER CODE END LTDC_MspInit 0 */
- /* Peripheral clock enable */
- __LTDC_CLK_ENABLE();
-
- /**LTDC GPIO Configuration
- PE4 ------> LTDC_B0
- PE5 ------> LTDC_G0
- PE6 ------> LTDC_G1
- PI9 ------> LTDC_VSYNC
- PI10 ------> LTDC_HSYNC
- PF10 ------> LTDC_DE
- PH2 ------> LTDC_R0
- PH3 ------> LTDC_R1
- PH8 ------> LTDC_R2
- PH9 ------> LTDC_R3
- PH10 ------> LTDC_R4
- PH11 ------> LTDC_R5
- PH12 ------> LTDC_R6
- PG6 ------> LTDC_R7
- PG7 ------> LTDC_CLK
- PH13 ------> LTDC_G2
- PH14 ------> LTDC_G3
- PH15 ------> LTDC_G4
- PI0 ------> LTDC_G5
- PI1 ------> LTDC_G6
- PI2 ------> LTDC_G7
- PG10 ------> LTDC_B2
- PG11 ------> LTDC_B3
- PG12 ------> LTDC_B1
- PI4 ------> LTDC_B4
- PI5 ------> LTDC_B5
- PI6 ------> LTDC_B6
- PI7 ------> LTDC_B7
- */
- GPIO_InitStruct.Pin = GPIO_PIN_4|GPIO_PIN_5|GPIO_PIN_6;
- GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
- GPIO_InitStruct.Pull = GPIO_NOPULL;
- GPIO_InitStruct.Speed = GPIO_SPEED_LOW;
- GPIO_InitStruct.Alternate = GPIO_AF14_LTDC;
- HAL_GPIO_Init(GPIOE, &GPIO_InitStruct);
-
- GPIO_InitStruct.Pin = GPIO_PIN_9|GPIO_PIN_10|GPIO_PIN_0|GPIO_PIN_1
- |GPIO_PIN_2|GPIO_PIN_4|GPIO_PIN_5|GPIO_PIN_6
- |GPIO_PIN_7;
- GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
- GPIO_InitStruct.Pull = GPIO_NOPULL;
- GPIO_InitStruct.Speed = GPIO_SPEED_LOW;
- GPIO_InitStruct.Alternate = GPIO_AF14_LTDC;
- HAL_GPIO_Init(GPIOI, &GPIO_InitStruct);
-
- GPIO_InitStruct.Pin = GPIO_PIN_10;
- GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
- GPIO_InitStruct.Pull = GPIO_NOPULL;
- GPIO_InitStruct.Speed = GPIO_SPEED_LOW;
- GPIO_InitStruct.Alternate = GPIO_AF14_LTDC;
- HAL_GPIO_Init(GPIOF, &GPIO_InitStruct);
-
- GPIO_InitStruct.Pin = GPIO_PIN_2|GPIO_PIN_3|GPIO_PIN_8|GPIO_PIN_9
- |GPIO_PIN_10|GPIO_PIN_11|GPIO_PIN_12|GPIO_PIN_13
- |GPIO_PIN_14|GPIO_PIN_15;
- GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
- GPIO_InitStruct.Pull = GPIO_NOPULL;
- GPIO_InitStruct.Speed = GPIO_SPEED_LOW;
- GPIO_InitStruct.Alternate = GPIO_AF14_LTDC;
- HAL_GPIO_Init(GPIOH, &GPIO_InitStruct);
-
- GPIO_InitStruct.Pin = GPIO_PIN_6|GPIO_PIN_7|GPIO_PIN_10|GPIO_PIN_11
- |GPIO_PIN_12;
- GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
- GPIO_InitStruct.Pull = GPIO_NOPULL;
- GPIO_InitStruct.Speed = GPIO_SPEED_LOW;
- GPIO_InitStruct.Alternate = GPIO_AF14_LTDC;
- HAL_GPIO_Init(GPIOG, &GPIO_InitStruct);
-
- /* USER CODE BEGIN LTDC_MspInit 1 */
-
- /* USER CODE END LTDC_MspInit 1 */
- }
-
-}
-
-void HAL_LTDC_MspDeInit(LTDC_HandleTypeDef* hltdc)
-{
-
- if(hltdc->Instance==LTDC)
- {
- /* USER CODE BEGIN LTDC_MspDeInit 0 */
-
- /* USER CODE END LTDC_MspDeInit 0 */
- /* Peripheral clock disable */
- __LTDC_CLK_DISABLE();
-
- /**LTDC GPIO Configuration
- PE4 ------> LTDC_B0
- PE5 ------> LTDC_G0
- PE6 ------> LTDC_G1
- PI9 ------> LTDC_VSYNC
- PI10 ------> LTDC_HSYNC
- PF10 ------> LTDC_DE
- PH2 ------> LTDC_R0
- PH3 ------> LTDC_R1
- PH8 ------> LTDC_R2
- PH9 ------> LTDC_R3
- PH10 ------> LTDC_R4
- PH11 ------> LTDC_R5
- PH12 ------> LTDC_R6
- PG6 ------> LTDC_R7
- PG7 ------> LTDC_CLK
- PH13 ------> LTDC_G2
- PH14 ------> LTDC_G3
- PH15 ------> LTDC_G4
- PI0 ------> LTDC_G5
- PI1 ------> LTDC_G6
- PI2 ------> LTDC_G7
- PG10 ------> LTDC_B2
- PG11 ------> LTDC_B3
- PG12 ------> LTDC_B1
- PI4 ------> LTDC_B4
- PI5 ------> LTDC_B5
- PI6 ------> LTDC_B6
- PI7 ------> LTDC_B7
- */
- HAL_GPIO_DeInit(GPIOE, GPIO_PIN_4|GPIO_PIN_5|GPIO_PIN_6);
-
- HAL_GPIO_DeInit(GPIOI, GPIO_PIN_9|GPIO_PIN_10|GPIO_PIN_0|GPIO_PIN_1
- |GPIO_PIN_2|GPIO_PIN_4|GPIO_PIN_5|GPIO_PIN_6
- |GPIO_PIN_7);
-
- HAL_GPIO_DeInit(GPIOF, GPIO_PIN_10);
-
- HAL_GPIO_DeInit(GPIOH, GPIO_PIN_2|GPIO_PIN_3|GPIO_PIN_8|GPIO_PIN_9
- |GPIO_PIN_10|GPIO_PIN_11|GPIO_PIN_12|GPIO_PIN_13
- |GPIO_PIN_14|GPIO_PIN_15);
-
- HAL_GPIO_DeInit(GPIOG, GPIO_PIN_6|GPIO_PIN_7|GPIO_PIN_10|GPIO_PIN_11
- |GPIO_PIN_12);
-
- /* USER CODE BEGIN LTDC_MspDeInit 1 */
- __LTDC_RELEASE_RESET();
-
- /* USER CODE END LTDC_MspDeInit 1 */
- }
-
-}
-
-void HAL_SPI_MspInit(SPI_HandleTypeDef* hspi)
-{
-
- GPIO_InitTypeDef GPIO_InitStruct;
- if(hspi->Instance==SPI1)
- {
- /* USER CODE BEGIN SPI1_MspInit 0 */
- __GPIOA_CLK_ENABLE();
- __GPIOB_CLK_ENABLE();
- __DMA2_CLK_ENABLE();
-
- /* USER CODE END SPI1_MspInit 0 */
- /* Peripheral clock enable */
- __SPI1_CLK_ENABLE();
-
- /**SPI1 GPIO Configuration
- alt: PA4 ------> SPI1_NSS, jetzt soft
- PA5 ------> SPI1_SCK
- alt: PA6 ------> SPI1_MISO
- neu: PB4 ------> SPI1_MISO
- PA7 ------> SPI1_MOSI
- */
-// GPIO_InitStruct.Pin = GPIO_PIN_4|GPIO_PIN_5|GPIO_PIN_6|GPIO_PIN_7;
- GPIO_InitStruct.Pin = GPIO_PIN_5|GPIO_PIN_7;
- GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
- GPIO_InitStruct.Pull = GPIO_NOPULL;
- GPIO_InitStruct.Speed = GPIO_SPEED_MEDIUM;//GPIO_SPEED_LOW;
- GPIO_InitStruct.Alternate = GPIO_AF5_SPI1;
- HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
- GPIO_InitStruct.Pin = GPIO_PIN_4;
- HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
-
- /* Peripheral DMA init*/
-
- hdma_spi1_tx.Instance = DMA2_Stream3;
- hdma_spi1_tx.Init.Channel = DMA_CHANNEL_3;
- hdma_spi1_tx.Init.Direction = DMA_MEMORY_TO_PERIPH;
- hdma_spi1_tx.Init.PeriphInc = DMA_PINC_DISABLE;
- hdma_spi1_tx.Init.MemInc = DMA_MINC_ENABLE;
- hdma_spi1_tx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE;
- hdma_spi1_tx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE;
- hdma_spi1_tx.Init.Mode = DMA_NORMAL;
- hdma_spi1_tx.Init.Priority = DMA_PRIORITY_LOW;
- hdma_spi1_tx.Init.FIFOMode = DMA_FIFOMODE_DISABLE;
-/* by christian */
-hdma_spi1_tx.Init.MemBurst = DMA_MBURST_INC4;
-hdma_spi1_tx.Init.PeriphBurst = DMA_PBURST_INC4;
- HAL_DMA_Init(&hdma_spi1_tx);
-
- __HAL_LINKDMA(hspi,hdmatx,hdma_spi1_tx);
-
- hdma_spi1_rx.Instance = DMA2_Stream0;
- hdma_spi1_rx.Init.Channel = DMA_CHANNEL_3;
- hdma_spi1_rx.Init.Direction = DMA_PERIPH_TO_MEMORY;
- hdma_spi1_rx.Init.PeriphInc = DMA_PINC_DISABLE;
- hdma_spi1_rx.Init.MemInc = DMA_MINC_ENABLE;
- hdma_spi1_rx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE;
- hdma_spi1_rx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE;
- hdma_spi1_rx.Init.Mode = DMA_NORMAL;
- hdma_spi1_rx.Init.Priority = DMA_PRIORITY_HIGH;
- hdma_spi1_rx.Init.FIFOMode = DMA_FIFOMODE_DISABLE;
-/* by christian */
-hdma_spi1_rx.Init.FIFOThreshold = DMA_FIFO_THRESHOLD_FULL;
-
-hdma_spi1_rx.Init.MemBurst = DMA_MBURST_INC4;
-hdma_spi1_rx.Init.PeriphBurst = DMA_PBURST_INC4;
- HAL_DMA_Init(&hdma_spi1_rx);
-
- __HAL_LINKDMA(hspi, hdmarx, hdma_spi1_rx);
-
- /*##-4- Configure the NVIC for DMA #########################################*/
- /* NVIC configuration for DMA transfer complete interrupt (SPI1_TX) */
- HAL_NVIC_SetPriority(DMA2_Stream3_IRQn, 0, 1);
- HAL_NVIC_EnableIRQ(DMA2_Stream3_IRQn);
-
-
- /* NVIC configuration for DMA transfer complete interrupt (SPI1_RX) */
- HAL_NVIC_SetPriority(DMA2_Stream0_IRQn, 0, 0);
- HAL_NVIC_EnableIRQ(DMA2_Stream0_IRQn);
-
- }
- else if(hspi->Instance==SPI2)
- {
- /* USER CODE BEGIN SPI2_MspInit 0 */
- __GPIOB_CLK_ENABLE();
-
- /* USER CODE END SPI2_MspInit 0 */
- /* Peripheral clock enable */
- __SPI2_CLK_ENABLE();
-
- /**SPI2 GPIO Configuration
- PB13 ------> SPI2_SCK
- PB14 ------> SPI2_MISO
- PB15 ------> SPI2_MOSI
- */
- GPIO_InitStruct.Pin = GPIO_PIN_13|GPIO_PIN_14|GPIO_PIN_15;
- GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
- GPIO_InitStruct.Pull = GPIO_NOPULL;
- GPIO_InitStruct.Speed = GPIO_SPEED_LOW;
- GPIO_InitStruct.Alternate = GPIO_AF5_SPI2;
- HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
-
- /* USER CODE BEGIN SPI2_MspInit 1 */
-
- /* USER CODE END SPI2_MspInit 1 */
- }
- else if(hspi->Instance==SPI5)
- {
- /* USER CODE BEGIN SPI5_MspInit 0 */
- __GPIOF_CLK_ENABLE();
-
- /* USER CODE END SPI5_MspInit 0 */
- /* Peripheral clock enable */
- __SPI5_CLK_ENABLE();
-
- /**SPI5 GPIO Configuration
- PF7 ------> SPI5_SCK
- PF8 ------> SPI5_MISO
- PF9 ------> SPI5_MOSI
- */
- GPIO_InitStruct.Pin = GPIO_PIN_7|GPIO_PIN_8|GPIO_PIN_9;
- GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
- GPIO_InitStruct.Pull = GPIO_NOPULL;
- GPIO_InitStruct.Speed = GPIO_SPEED_MEDIUM;//GPIO_SPEED_LOW;
- GPIO_InitStruct.Alternate = GPIO_AF5_SPI5;
- HAL_GPIO_Init(GPIOF, &GPIO_InitStruct);
-
- /* USER CODE BEGIN SPI5_MspInit 1 */
-
- /* USER CODE END SPI5_MspInit 1 */
- }
-
-}
-
-void HAL_SPI_MspDeInit(SPI_HandleTypeDef* hspi)
-{
-
- if(hspi->Instance==SPI1)
- {
- /* USER CODE BEGIN SPI1_MspDeInit 0 */
- __SPI1_FORCE_RESET();
- __SPI1_RELEASE_RESET();
-
- /* USER CODE END SPI1_MspDeInit 0 */
- /* Peripheral clock disable */
- __SPI1_CLK_DISABLE();
-
- /**SPI1 GPIO Configuration
- PA4 ------> SPI1_NSS
- PA5 ------> SPI1_SCK
- PA6 ------> SPI1_MISO
- PA7 ------> SPI1_MOSI
- */
- HAL_GPIO_DeInit(GPIOA, GPIO_PIN_4|GPIO_PIN_5|GPIO_PIN_6|GPIO_PIN_7);
-
- /* Peripheral DMA DeInit*/
- HAL_DMA_DeInit(hspi->hdmatx);
- HAL_DMA_DeInit(hspi->hdmarx);
- /* USER CODE BEGIN SPI1_MspDeInit 1 */
-
- /* USER CODE END SPI1_MspDeInit 1 */
- }
- else if(hspi->Instance==SPI2)
- {
- /* USER CODE BEGIN SPI2_MspDeInit 0 */
-
- /* USER CODE END SPI2_MspDeInit 0 */
- /* Peripheral clock disable */
- __SPI2_CLK_DISABLE();
-
- /**SPI2 GPIO Configuration
- PB13 ------> SPI2_SCK
- PB14 ------> SPI2_MISO
- PB15 ------> SPI2_MOSI
- */
- HAL_GPIO_DeInit(GPIOB, GPIO_PIN_13|GPIO_PIN_14|GPIO_PIN_15);
-
- /* USER CODE BEGIN SPI2_MspDeInit 1 */
-
- /* USER CODE END SPI2_MspDeInit 1 */
- }
- else if(hspi->Instance==SPI5)
- {
- /* USER CODE BEGIN SPI5_MspDeInit 0 */
- __SPI5_FORCE_RESET();
- __SPI5_RELEASE_RESET();
-
- /* USER CODE END SPI5_MspDeInit 0 */
- /* Peripheral clock disable */
- __SPI5_CLK_DISABLE();
-
- /**SPI5 GPIO Configuration
- PF7 ------> SPI5_SCK
- PF8 ------> SPI5_MISO
- PF9 ------> SPI5_MOSI
- */
- HAL_GPIO_DeInit(GPIOF, GPIO_PIN_7|GPIO_PIN_8|GPIO_PIN_9);
-
- /* USER CODE BEGIN SPI5_MspDeInit 1 */
-
- /* USER CODE END SPI5_MspDeInit 1 */
- }
-
-}
-
-void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef* htim_pwm)
-{
- GPIO_InitTypeDef GPIO_InitStruct;
- if(htim_pwm->Instance==TIM_BACKLIGHT)
- {
- TIM_BACKLIGHT_GPIO_ENABLE();
- TIM_BACKLIGHT_CLK_ENABLE();
-
- GPIO_InitStruct.Pin = TIM_BACKLIGHT_PIN;
- GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
- GPIO_InitStruct.Pull = GPIO_NOPULL;
- GPIO_InitStruct.Speed = GPIO_SPEED_LOW;
- GPIO_InitStruct.Alternate = GPIO_AF2_TIM3;
- HAL_GPIO_Init(TIM_BACKLIGHT_GPIO_PORT, &GPIO_InitStruct);
- }
-
-}
-
-void HAL_TIM_Base_MspInit(TIM_HandleTypeDef* htim_base)
-{
- if(htim_base->Instance==TIMx)
- {
- TIMx_CLK_ENABLE();
-
- HAL_NVIC_SetPriority(TIMx_IRQn, 2, 1);
- HAL_NVIC_EnableIRQ(TIMx_IRQn);
- }
- if(htim_base->Instance==TIM7)
- {
- __TIM7_CLK_ENABLE();
-
- HAL_NVIC_SetPriority(TIM7_IRQn, 2, 0);
- HAL_NVIC_EnableIRQ(TIM7_IRQn);
- }
-}
-
-void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef* htim_pwm)
-{
-
- if(htim_pwm->Instance==TIM2)
- {
- /* USER CODE BEGIN TIM2_MspDeInit 0 */
-
- /* USER CODE END TIM2_MspDeInit 0 */
- /* Peripheral clock disable */
- __TIM2_CLK_DISABLE();
-
- /**TIM2 GPIO Configuration
- PA15 ------> TIM2_CH1
- */
- HAL_GPIO_DeInit(GPIOA, GPIO_PIN_15);
-
- /* USER CODE BEGIN TIM2_MspDeInit 1 */
-
- /* USER CODE END TIM2_MspDeInit 1 */
- }
-
-}
-
-void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef* htim_base)
-{
-
- if(htim_base->Instance==TIM3)
- {
- /* USER CODE BEGIN TIM3_MspDeInit 0 */
-
- /* USER CODE END TIM3_MspDeInit 0 */
- /* Peripheral clock disable */
- __TIM3_CLK_DISABLE();
-
- /**TIM3 GPIO Configuration
- PC7 ------> TIM3_CH2
- */
- HAL_GPIO_DeInit(GPIOC, GPIO_PIN_7);
-
- /* USER CODE BEGIN TIM3_MspDeInit 1 */
-
- /* USER CODE END TIM3_MspDeInit 1 */
- }
-
-}
-
-void HAL_UART_MspInit(UART_HandleTypeDef* huart)
-{
-
- GPIO_InitTypeDef GPIO_InitStruct;
- if(huart->Instance==USART1)
- {
- /* USER CODE BEGIN USART1_MspInit 0 */
- __GPIOA_CLK_ENABLE();
-
- /* USER CODE END USART1_MspInit 0 */
- /* Peripheral clock enable */
- __USART1_CLK_ENABLE();
-
- /**USART1 GPIO Configuration
- PA9 ------> USART1_TX
- PA10 ------> USART1_RX
- PA11 ------> USART1_CTS
- PA12 ------> USART1_RTS
- */
-#ifdef USARTx_CTS_PIN
- GPIO_InitStruct.Pin = GPIO_PIN_9|GPIO_PIN_10|GPIO_PIN_11|GPIO_PIN_12;
-#else
- GPIO_InitStruct.Pin = GPIO_PIN_9|GPIO_PIN_10;
-#endif
- GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
- GPIO_InitStruct.Pull = GPIO_PULLUP;
- GPIO_InitStruct.Speed = GPIO_SPEED_FAST;//GPIO_SPEED_LOW;
- GPIO_InitStruct.Alternate = GPIO_AF7_USART1;
- HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
-
- HAL_NVIC_SetPriority(USART1_IRQn, 0, 1);
- HAL_NVIC_EnableIRQ(USART1_IRQn);
- }
-#ifdef USART_IR_HUD
- else if(huart->Instance==USART_IR_HUD) /* USART2 */
- {
- USART_IR_HUD_CLK_ENABLE();
- USART_IR_HUD_TX_GPIO_CLK_ENABLE();
- USART_IR_HUD_RX_GPIO_CLK_ENABLE();
-
- /**USART2 GPIO Configuration
- PD5 ------> USART2_TX
- PD6 ------> USART2_RX
- */
-
- GPIO_InitStruct.Pin = USART_IR_HUD_TX_PIN;
- GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
- GPIO_InitStruct.Pull = GPIO_PULLUP;
- GPIO_InitStruct.Speed = GPIO_SPEED_LOW;
- GPIO_InitStruct.Alternate = USART_IR_HUD_TX_AF;
- HAL_GPIO_Init(USART_IR_HUD_TX_GPIO_PORT, &GPIO_InitStruct);
-
- GPIO_InitStruct.Pin = USART_IR_HUD_RX_PIN;
- GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
- GPIO_InitStruct.Pull = GPIO_PULLUP;
- GPIO_InitStruct.Speed = GPIO_SPEED_LOW;
- GPIO_InitStruct.Alternate = USART_IR_HUD_RX_AF;
- HAL_GPIO_Init(USART_IR_HUD_RX_GPIO_PORT, &GPIO_InitStruct);
-
- HAL_NVIC_SetPriority(USART_IR_HUD_IRQn, 0, 1);
- HAL_NVIC_EnableIRQ(USART_IR_HUD_IRQn);
- }
-#endif
- else if(huart->Instance==USART3)
- {
- /* USER CODE BEGIN USART3_MspInit 0 */
-
- /* USER CODE END USART3_MspInit 0 */
- /* Peripheral clock enable */
- __USART3_CLK_ENABLE();
-
- /**USART3 GPIO Configuration
- PC10 ------> USART3_TX
- PC11 ------> USART3_RX
- */
- GPIO_InitStruct.Pin = GPIO_PIN_10|GPIO_PIN_11;
- GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
- GPIO_InitStruct.Pull = GPIO_PULLUP;
- GPIO_InitStruct.Speed = GPIO_SPEED_LOW;
- GPIO_InitStruct.Alternate = GPIO_AF7_USART3;
- HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
-
- /* USER CODE BEGIN USART3_MspInit 1 */
-
- /* USER CODE END USART3_MspInit 1 */
- }
-
-}
-
-void HAL_UART_MspDeInit(UART_HandleTypeDef* huart)
-{
-
- if(huart->Instance==USART1)
- {
- /* USER CODE BEGIN USART1_MspDeInit 0 */
-
- /* USER CODE END USART1_MspDeInit 0 */
- /* Peripheral clock disable */
- HAL_NVIC_DisableIRQ(USART1_IRQn);
- __USART1_CLK_DISABLE();
-
- /**USART1 GPIO Configuration
- PA9 ------> USART1_TX
- PA10 ------> USART1_RX
- */
-#ifdef USARTx_CTS_PIN
- HAL_GPIO_DeInit(GPIOA, GPIO_PIN_9|GPIO_PIN_10|GPIO_PIN_11|GPIO_PIN_12);
-#else
- HAL_GPIO_DeInit(GPIOA, GPIO_PIN_9|GPIO_PIN_10);
-#endif
-
- /* USER CODE BEGIN USART1_MspDeInit 1 */
-
- /* USER CODE END USART1_MspDeInit 1 */
- }
- else if(huart->Instance==USART2)
- {
- /* USER CODE BEGIN USART2_MspDeInit 0 */
-
- /* USER CODE END USART2_MspDeInit 0 */
- /* Peripheral clock disable */
- __USART2_CLK_DISABLE();
-
- /**USART2 GPIO Configuration
- PD5 ------> USART2_TX
- PD6 ------> USART2_RX
- */
- HAL_GPIO_DeInit(GPIOD, GPIO_PIN_5|GPIO_PIN_6);
-
- /* USER CODE BEGIN USART2_MspDeInit 1 */
-
- /* USER CODE END USART2_MspDeInit 1 */
- }
- else if(huart->Instance==USART3)
- {
- /* USER CODE BEGIN USART3_MspDeInit 0 */
-
- /* USER CODE END USART3_MspDeInit 0 */
- /* Peripheral clock disable */
- __USART3_CLK_DISABLE();
-
- /**USART3 GPIO Configuration
- PC10 ------> USART3_TX
- PC11 ------> USART3_RX
- */
- HAL_GPIO_DeInit(GPIOC, GPIO_PIN_10|GPIO_PIN_11);
-
- /* USER CODE BEGIN USART3_MspDeInit 1 */
-
- /* USER CODE END USART3_MspDeInit 1 */
- }
-
-}
-
-static int FMC_Initialized = 0;
-
-static void HAL_FMC_MspInit(void){
- GPIO_InitTypeDef GPIO_InitStruct;
- if (FMC_Initialized) {
- return;
- }
- FMC_Initialized = 1;
- /* Peripheral clock enable */
- /* by christian */
- __GPIOC_CLK_ENABLE();
- __GPIOD_CLK_ENABLE();
- __GPIOE_CLK_ENABLE();
- __GPIOF_CLK_ENABLE();
- __GPIOG_CLK_ENABLE();
- __GPIOH_CLK_ENABLE();
-
- __FMC_CLK_ENABLE();
-
- /** FMC GPIO Configuration
- PF0 ------> FMC_A0
- PF1 ------> FMC_A1
- PF2 ------> FMC_A2
- PF3 ------> FMC_A3
- PF4 ------> FMC_A4
- PF5 ------> FMC_A5
- PC0 ------> FMC_SDNWE
- PF11 ------> FMC_SDNRAS
- PF12 ------> FMC_A6
- PF13 ------> FMC_A7
- PF14 ------> FMC_A8
- PF15 ------> FMC_A9
- PG0 ------> FMC_A10
- PG1 ------> FMC_A11
- PE7 ------> FMC_D4
- PE8 ------> FMC_D5
- PE9 ------> FMC_D6
- PE10 ------> FMC_D7
- PE11 ------> FMC_D8
- PE12 ------> FMC_D9
- PE13 ------> FMC_D10
- PE14 ------> FMC_D11
- PE15 ------> FMC_D12
- PH6 ------> FMC_SDNE1 neu
- PH7 ------> FMC_SDCKE1 neu
- PD8 ------> FMC_D13
- PD9 ------> FMC_D14
- PD10 ------> FMC_D15
- PD14 ------> FMC_D0
- PD15 ------> FMC_D1
- PG2 ------> FMC_A12
- PG4 ------> FMC_BA0
- PG5 ------> FMC_BA1
- PG8 ------> FMC_SDCLK
- PD0 ------> FMC_D2
- PD1 ------> FMC_D3
- PG15 ------> FMC_SDNCAS
- PE0 ------> FMC_NBL0
- PE1 ------> FMC_NBL1
- */
-
- GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
- GPIO_InitStruct.Pull = GPIO_NOPULL;
- GPIO_InitStruct.Speed = GPIO_SPEED_FAST;
- GPIO_InitStruct.Alternate = GPIO_AF12_FMC;
-
-
- GPIO_InitStruct.Pin = GPIO_PIN_0;
- HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
-
- GPIO_InitStruct.Pin = GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10|GPIO_PIN_14
- |GPIO_PIN_15|GPIO_PIN_0|GPIO_PIN_1;
- HAL_GPIO_Init(GPIOD, &GPIO_InitStruct);
-
- GPIO_InitStruct.Pin = GPIO_PIN_7|GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10
- |GPIO_PIN_11|GPIO_PIN_12|GPIO_PIN_13|GPIO_PIN_14
- |GPIO_PIN_15|GPIO_PIN_0|GPIO_PIN_1;
- HAL_GPIO_Init(GPIOE, &GPIO_InitStruct);
-
- GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_3
- |GPIO_PIN_4|GPIO_PIN_5|GPIO_PIN_11|GPIO_PIN_12
- |GPIO_PIN_13|GPIO_PIN_14|GPIO_PIN_15;
- HAL_GPIO_Init(GPIOF, &GPIO_InitStruct);
-
- GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_4
- |GPIO_PIN_5|GPIO_PIN_8|GPIO_PIN_15;
- HAL_GPIO_Init(GPIOG, &GPIO_InitStruct);
-
- GPIO_InitStruct.Pin = GPIO_PIN_6|GPIO_PIN_7;
- HAL_GPIO_Init(GPIOH, &GPIO_InitStruct);
-
-
-}
-
-void HAL_SDRAM_MspInit(SDRAM_HandleTypeDef* hsdram){
- HAL_FMC_MspInit();
-}
-
-static int FMC_DeInitialized = 0;
-
-static void HAL_FMC_MspDeInit(void){
- if (FMC_DeInitialized) {
- return;
- }
- FMC_DeInitialized = 1;
- /* Peripheral clock enable */
- __FMC_CLK_DISABLE();
-
- /** FMC GPIO Configuration
- PF0 ------> FMC_A0
- PF1 ------> FMC_A1
- PF2 ------> FMC_A2
- PF3 ------> FMC_A3
- PF4 ------> FMC_A4
- PF5 ------> FMC_A5
- PC0 ------> FMC_SDNWE
- PF11 ------> FMC_SDNRAS
- PF12 ------> FMC_A6
- PF13 ------> FMC_A7
- PF14 ------> FMC_A8
- PF15 ------> FMC_A9
- PG0 ------> FMC_A10
- PG1 ------> FMC_A11
- PE7 ------> FMC_D4
- PE8 ------> FMC_D5
- PE9 ------> FMC_D6
- PE10 ------> FMC_D7
- PE11 ------> FMC_D8
- PE12 ------> FMC_D9
- PE13 ------> FMC_D10
- PE14 ------> FMC_D11
- PE15 ------> FMC_D12
- PH6 ------> FMC_SDNE1
- PH7 ------> FMC_SDCKE1
- PD8 ------> FMC_D13
- PD9 ------> FMC_D14
- PD10 ------> FMC_D15
- PD14 ------> FMC_D0
- PD15 ------> FMC_D1
- PG2 ------> FMC_A12
- PG4 ------> FMC_BA0
- PG5 ------> FMC_BA1
- PG8 ------> FMC_SDCLK
- PD0 ------> FMC_D2
- PD1 ------> FMC_D3
- PG15 ------> FMC_SDNCAS
- PE0 ------> FMC_NBL0
- PE1 ------> FMC_NBL1
- */
- HAL_GPIO_DeInit(GPIOF, GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_3
- |GPIO_PIN_4|GPIO_PIN_5|GPIO_PIN_11|GPIO_PIN_12
- |GPIO_PIN_13|GPIO_PIN_14|GPIO_PIN_15);
-
- HAL_GPIO_DeInit(GPIOC, GPIO_PIN_0);
-
- HAL_GPIO_DeInit(GPIOG, GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_4
- |GPIO_PIN_5|GPIO_PIN_8|GPIO_PIN_15);
-
- HAL_GPIO_DeInit(GPIOE, GPIO_PIN_7|GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10
- |GPIO_PIN_11|GPIO_PIN_12|GPIO_PIN_13|GPIO_PIN_14
- |GPIO_PIN_15|GPIO_PIN_0|GPIO_PIN_1);
-
- HAL_GPIO_DeInit(GPIOH, GPIO_PIN_6|GPIO_PIN_7);
-
- HAL_GPIO_DeInit(GPIOD, GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10|GPIO_PIN_14
- |GPIO_PIN_15|GPIO_PIN_0|GPIO_PIN_1);
-
-}
-
-void HAL_SDRAM_MspDeInit(SDRAM_HandleTypeDef* hsdram){
- HAL_FMC_MspDeInit();
-}
-
-/* USER CODE BEGIN 1 */
-
-/* USER CODE END 1 */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff -r b355f462c952 -r 2de06b1abed3 OtherSources/system_stm32f4xx.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/OtherSources/system_stm32f4xx.c Mon Dec 18 14:03:55 2017 +0100
@@ -0,0 +1,522 @@
+/**
+ ******************************************************************************
+ * @file system_stm32f4xx.c
+ * @author MCD Application Team
+ * @version V2.1.0
+ * @date 19-June-2014
+ * @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File.
+ *
+ * This file provides two functions and one global variable to be called from
+ * user application:
+ * - SystemInit(): This function is called at startup just after reset and
+ * before branch to main program. This call is made inside
+ * the "startup_stm32f4xx.s" file.
+ *
+ * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
+ * by the user application to setup the SysTick
+ * timer or configure other parameters.
+ *
+ * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
+ * be called whenever the core clock is changed
+ * during program execution.
+ *
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * © COPYRIGHT 2014 STMicroelectronics
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/** @addtogroup CMSIS
+ * @{
+ */
+
+/** @addtogroup stm32f4xx_system
+ * @{
+ */
+
+/** @addtogroup STM32F4xx_System_Private_Includes
+ * @{
+ */
+
+
+#include "stm32f4xx.h"
+
+#if !defined (HSE_VALUE)
+ #define HSE_VALUE ((uint32_t)8000000) /*!< Default value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined (HSI_VALUE)
+ #define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F4xx_System_Private_TypesDefinitions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F4xx_System_Private_Defines
+ * @{
+ */
+
+/************************* Miscellaneous Configuration ************************/
+/*!< Uncomment the following line if you need to use external SRAM or SDRAM mounted
+ on STM324xG_EVAL/STM324x9I_EVAL boards as data memory */
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
+/* #define DATA_IN_ExtSRAM */
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
+
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
+/* #define DATA_IN_ExtSDRAM */
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
+
+#if defined(DATA_IN_ExtSRAM) && defined(DATA_IN_ExtSDRAM)
+ #error "Please select DATA_IN_ExtSRAM or DATA_IN_ExtSDRAM "
+#endif /* DATA_IN_ExtSRAM && DATA_IN_ExtSDRAM */
+
+/*!< Uncomment the following line if you need to relocate your vector Table in
+ Internal SRAM. */
+/* #define VECT_TAB_SRAM */
+#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field.
+ This value must be a multiple of 0x200. */
+/******************************************************************************/
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F4xx_System_Private_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F4xx_System_Private_Variables
+ * @{
+ */
+ /* This variable is updated in three ways:
+ 1) by calling CMSIS function SystemCoreClockUpdate()
+ 2) by calling HAL API function HAL_RCC_GetHCLKFreq()
+ 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
+ Note: If you use this function to configure the system clock; then there
+ is no need to call the 2 first functions listed above, since SystemCoreClock
+ variable is updated automatically.
+ */
+ uint32_t SystemCoreClock = 16000000;
+ __IO const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F4xx_System_Private_FunctionPrototypes
+ * @{
+ */
+
+#if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
+ static void SystemInit_ExtMemCtl(void);
+#endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F4xx_System_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief Setup the microcontroller system
+ * Initialize the FPU setting, vector table location and External memory
+ * configuration.
+ * @param None
+ * @retval None
+ */
+void SystemInit(void)
+{
+ /* FPU settings ------------------------------------------------------------*/
+ #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+ SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */
+ #endif
+ /* Reset the RCC clock configuration to the default reset state ------------*/
+ /* Set HSION bit */
+ RCC->CR |= (uint32_t)0x00000001;
+
+ /* Reset CFGR register */
+ RCC->CFGR = 0x00000000;
+
+ /* Reset HSEON, CSSON and PLLON bits */
+ RCC->CR &= (uint32_t)0xFEF6FFFF;
+
+ /* Reset PLLCFGR register */
+ RCC->PLLCFGR = 0x24003010;
+
+ /* Reset HSEBYP bit */
+ RCC->CR &= (uint32_t)0xFFFBFFFF;
+
+ /* Disable all interrupts */
+ RCC->CIR = 0x00000000;
+
+#if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
+ SystemInit_ExtMemCtl();
+#endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
+
+ /* Configure the Vector Table location add offset address ------------------*/
+#ifdef VECT_TAB_SRAM
+ SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
+#else
+ SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
+#endif
+}
+
+/**
+ * @brief Update SystemCoreClock variable according to Clock Register Values.
+ * The SystemCoreClock variable contains the core clock (HCLK), it can
+ * be used by the user application to setup the SysTick timer or configure
+ * other parameters.
+ *
+ * @note Each time the core clock (HCLK) changes, this function must be called
+ * to update SystemCoreClock variable value. Otherwise, any configuration
+ * based on this variable will be incorrect.
+ *
+ * @note - The system frequency computed by this function is not the real
+ * frequency in the chip. It is calculated based on the predefined
+ * constant and the selected clock source:
+ *
+ * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
+ *
+ * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
+ *
+ * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
+ * or HSI_VALUE(*) multiplied/divided by the PLL factors.
+ *
+ * (*) HSI_VALUE is a constant defined in stm32f4xx_hal_conf.h file (default value
+ * 16 MHz) but the real value may vary depending on the variations
+ * in voltage and temperature.
+ *
+ * (**) HSE_VALUE is a constant defined in stm32f4xx_hal_conf.h file (its value
+ * depends on the application requirements), user has to ensure that HSE_VALUE
+ * is same as the real frequency of the crystal used. Otherwise, this function
+ * may have wrong result.
+ *
+ * - The result of this function could be not correct when using fractional
+ * value for HSE crystal.
+ *
+ * @param None
+ * @retval None
+ */
+void SystemCoreClockUpdate(void)
+{
+ uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2;
+
+ /* Get SYSCLK source -------------------------------------------------------*/
+ tmp = RCC->CFGR & RCC_CFGR_SWS;
+
+ switch (tmp)
+ {
+ case 0x00: /* HSI used as system clock source */
+ SystemCoreClock = HSI_VALUE;
+ break;
+ case 0x04: /* HSE used as system clock source */
+ SystemCoreClock = HSE_VALUE;
+ break;
+ case 0x08: /* PLL used as system clock source */
+
+ /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N
+ SYSCLK = PLL_VCO / PLL_P
+ */
+ pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22;
+ pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
+
+ if (pllsource != 0)
+ {
+ /* HSE used as PLL clock source */
+ pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
+ }
+ else
+ {
+ /* HSI used as PLL clock source */
+ pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
+ }
+
+ pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2;
+ SystemCoreClock = pllvco/pllp;
+ break;
+ default:
+ SystemCoreClock = HSI_VALUE;
+ break;
+ }
+ /* Compute HCLK frequency --------------------------------------------------*/
+ /* Get HCLK prescaler */
+ tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
+ /* HCLK frequency */
+ SystemCoreClock >>= tmp;
+}
+
+#if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
+/**
+ * @brief Setup the external memory controller.
+ * Called in startup_stm32f4xx.s before jump to main.
+ * This function configures the external memories (SRAM/SDRAM)
+ * This SRAM/SDRAM will be used as program data memory (including heap and stack).
+ * @param None
+ * @retval None
+ */
+void SystemInit_ExtMemCtl(void)
+{
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
+#if defined (DATA_IN_ExtSDRAM)
+ register uint32_t tmpreg = 0, timeout = 0xFFFF;
+ register uint32_t index;
+
+ /* Enable GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH and GPIOI interface
+ clock */
+ RCC->AHB1ENR |= 0x000001F8;
+
+ /* Connect PDx pins to FMC Alternate function */
+ GPIOD->AFR[0] = 0x000000CC;
+ GPIOD->AFR[1] = 0xCC000CCC;
+ /* Configure PDx pins in Alternate function mode */
+ GPIOD->MODER = 0xA02A000A;
+ /* Configure PDx pins speed to 50 MHz */
+ GPIOD->OSPEEDR = 0xA02A000A;
+ /* Configure PDx pins Output type to push-pull */
+ GPIOD->OTYPER = 0x00000000;
+ /* No pull-up, pull-down for PDx pins */
+ GPIOD->PUPDR = 0x00000000;
+
+ /* Connect PEx pins to FMC Alternate function */
+ GPIOE->AFR[0] = 0xC00000CC;
+ GPIOE->AFR[1] = 0xCCCCCCCC;
+ /* Configure PEx pins in Alternate function mode */
+ GPIOE->MODER = 0xAAAA800A;
+ /* Configure PEx pins speed to 50 MHz */
+ GPIOE->OSPEEDR = 0xAAAA800A;
+ /* Configure PEx pins Output type to push-pull */
+ GPIOE->OTYPER = 0x00000000;
+ /* No pull-up, pull-down for PEx pins */
+ GPIOE->PUPDR = 0x00000000;
+
+ /* Connect PFx pins to FMC Alternate function */
+ GPIOF->AFR[0] = 0xCCCCCCCC;
+ GPIOF->AFR[1] = 0xCCCCCCCC;
+ /* Configure PFx pins in Alternate function mode */
+ GPIOF->MODER = 0xAA800AAA;
+ /* Configure PFx pins speed to 50 MHz */
+ GPIOF->OSPEEDR = 0xAA800AAA;
+ /* Configure PFx pins Output type to push-pull */
+ GPIOF->OTYPER = 0x00000000;
+ /* No pull-up, pull-down for PFx pins */
+ GPIOF->PUPDR = 0x00000000;
+
+ /* Connect PGx pins to FMC Alternate function */
+ GPIOG->AFR[0] = 0xCCCCCCCC;
+ GPIOG->AFR[1] = 0xCCCCCCCC;
+ /* Configure PGx pins in Alternate function mode */
+ GPIOG->MODER = 0xAAAAAAAA;
+ /* Configure PGx pins speed to 50 MHz */
+ GPIOG->OSPEEDR = 0xAAAAAAAA;
+ /* Configure PGx pins Output type to push-pull */
+ GPIOG->OTYPER = 0x00000000;
+ /* No pull-up, pull-down for PGx pins */
+ GPIOG->PUPDR = 0x00000000;
+
+ /* Connect PHx pins to FMC Alternate function */
+ GPIOH->AFR[0] = 0x00C0CC00;
+ GPIOH->AFR[1] = 0xCCCCCCCC;
+ /* Configure PHx pins in Alternate function mode */
+ GPIOH->MODER = 0xAAAA08A0;
+ /* Configure PHx pins speed to 50 MHz */
+ GPIOH->OSPEEDR = 0xAAAA08A0;
+ /* Configure PHx pins Output type to push-pull */
+ GPIOH->OTYPER = 0x00000000;
+ /* No pull-up, pull-down for PHx pins */
+ GPIOH->PUPDR = 0x00000000;
+
+ /* Connect PIx pins to FMC Alternate function */
+ GPIOI->AFR[0] = 0xCCCCCCCC;
+ GPIOI->AFR[1] = 0x00000CC0;
+ /* Configure PIx pins in Alternate function mode */
+ GPIOI->MODER = 0x0028AAAA;
+ /* Configure PIx pins speed to 50 MHz */
+ GPIOI->OSPEEDR = 0x0028AAAA;
+ /* Configure PIx pins Output type to push-pull */
+ GPIOI->OTYPER = 0x00000000;
+ /* No pull-up, pull-down for PIx pins */
+ GPIOI->PUPDR = 0x00000000;
+
+/*-- FMC Configuration ------------------------------------------------------*/
+ /* Enable the FMC interface clock */
+ RCC->AHB3ENR |= 0x00000001;
+
+ /* Configure and enable SDRAM bank1 */
+ FMC_Bank5_6->SDCR[0] = 0x000019E0;
+ FMC_Bank5_6->SDTR[0] = 0x01115351;
+
+ /* SDRAM initialization sequence */
+ /* Clock enable command */
+ FMC_Bank5_6->SDCMR = 0x00000011;
+ tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
+ while((tmpreg != 0) && (timeout-- > 0))
+ {
+ tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
+ }
+
+ /* Delay */
+ for (index = 0; index<1000; index++);
+
+ /* PALL command */
+ FMC_Bank5_6->SDCMR = 0x00000012;
+ timeout = 0xFFFF;
+ while((tmpreg != 0) && (timeout-- > 0))
+ {
+ tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
+ }
+
+ /* Auto refresh command */
+ FMC_Bank5_6->SDCMR = 0x00000073;
+ timeout = 0xFFFF;
+ while((tmpreg != 0) && (timeout-- > 0))
+ {
+ tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
+ }
+
+ /* MRD register program */
+ FMC_Bank5_6->SDCMR = 0x00046014;
+ timeout = 0xFFFF;
+ while((tmpreg != 0) && (timeout-- > 0))
+ {
+ tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
+ }
+
+ /* Set refresh count */
+ tmpreg = FMC_Bank5_6->SDRTR;
+ FMC_Bank5_6->SDRTR = (tmpreg | (0x0000027C<<1));
+
+ /* Disable write protection */
+ tmpreg = FMC_Bank5_6->SDCR[0];
+ FMC_Bank5_6->SDCR[0] = (tmpreg & 0xFFFFFDFF);
+#endif /* DATA_IN_ExtSDRAM */
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
+
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
+#if defined(DATA_IN_ExtSRAM)
+/*-- GPIOs Configuration -----------------------------------------------------*/
+ /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */
+ RCC->AHB1ENR |= 0x00000078;
+
+ /* Connect PDx pins to FMC Alternate function */
+ GPIOD->AFR[0] = 0x00CCC0CC;
+ GPIOD->AFR[1] = 0xCCCCCCCC;
+ /* Configure PDx pins in Alternate function mode */
+ GPIOD->MODER = 0xAAAA0A8A;
+ /* Configure PDx pins speed to 100 MHz */
+ GPIOD->OSPEEDR = 0xFFFF0FCF;
+ /* Configure PDx pins Output type to push-pull */
+ GPIOD->OTYPER = 0x00000000;
+ /* No pull-up, pull-down for PDx pins */
+ GPIOD->PUPDR = 0x00000000;
+
+ /* Connect PEx pins to FMC Alternate function */
+ GPIOE->AFR[0] = 0xC00CC0CC;
+ GPIOE->AFR[1] = 0xCCCCCCCC;
+ /* Configure PEx pins in Alternate function mode */
+ GPIOE->MODER = 0xAAAA828A;
+ /* Configure PEx pins speed to 100 MHz */
+ GPIOE->OSPEEDR = 0xFFFFC3CF;
+ /* Configure PEx pins Output type to push-pull */
+ GPIOE->OTYPER = 0x00000000;
+ /* No pull-up, pull-down for PEx pins */
+ GPIOE->PUPDR = 0x00000000;
+
+ /* Connect PFx pins to FMC Alternate function */
+ GPIOF->AFR[0] = 0x00CCCCCC;
+ GPIOF->AFR[1] = 0xCCCC0000;
+ /* Configure PFx pins in Alternate function mode */
+ GPIOF->MODER = 0xAA000AAA;
+ /* Configure PFx pins speed to 100 MHz */
+ GPIOF->OSPEEDR = 0xFF000FFF;
+ /* Configure PFx pins Output type to push-pull */
+ GPIOF->OTYPER = 0x00000000;
+ /* No pull-up, pull-down for PFx pins */
+ GPIOF->PUPDR = 0x00000000;
+
+ /* Connect PGx pins to FMC Alternate function */
+ GPIOG->AFR[0] = 0x00CCCCCC;
+ GPIOG->AFR[1] = 0x000000C0;
+ /* Configure PGx pins in Alternate function mode */
+ GPIOG->MODER = 0x00085AAA;
+ /* Configure PGx pins speed to 100 MHz */
+ GPIOG->OSPEEDR = 0x000CAFFF;
+ /* Configure PGx pins Output type to push-pull */
+ GPIOG->OTYPER = 0x00000000;
+ /* No pull-up, pull-down for PGx pins */
+ GPIOG->PUPDR = 0x00000000;
+
+/*-- FMC/FSMC Configuration --------------------------------------------------*/
+ /* Enable the FMC/FSMC interface clock */
+ RCC->AHB3ENR |= 0x00000001;
+
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx)
+ /* Configure and enable Bank1_SRAM2 */
+ FMC_Bank1->BTCR[2] = 0x00001011;
+ FMC_Bank1->BTCR[3] = 0x00000201;
+ FMC_Bank1E->BWTR[2] = 0x0fffffff;
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
+
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx)
+ /* Configure and enable Bank1_SRAM2 */
+ FSMC_Bank1->BTCR[2] = 0x00001011;
+ FSMC_Bank1->BTCR[3] = 0x00000201;
+ FSMC_Bank1E->BWTR[2] = 0x0FFFFFFF;
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
+
+#endif /* DATA_IN_ExtSRAM */
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
+}
+#endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff -r b355f462c952 -r 2de06b1abed3 OtherSources/system_stm32f4xx_special_plus_256k.c
--- a/OtherSources/system_stm32f4xx_special_plus_256k.c Fri Dec 15 02:06:18 2017 +0100
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,273 +0,0 @@
-/**
- ******************************************************************************
- * @file system_stm32f4xx.c
- * @author MCD Application Team
- * @version V1.1.0
- * @date 17-February-2017
- * @brief - CMSIS Cortex-M4 Device Peripheral Access Layer System Source File.
- * - This file is dedicated only for STM32F29 NUCLEO 144 boards.
- *
- * This file provides two functions and one global variable to be called from
- * user application:
- * - SystemInit(): This function is called at startup just after reset and
- * before branch to main program. This call is made inside
- * the "startup_stm32f4xx.s" file.
- *
- * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
- * by the user application to setup the SysTick
- * timer or configure other parameters.
- *
- * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
- * be called whenever the core clock is changed
- * during program execution.
- *
- *
- ******************************************************************************
- * @attention
- *
- * © COPYRIGHT 2017 STMicroelectronics
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/** @addtogroup CMSIS
- * @{
- */
-
-/** @addtogroup stm32f4xx_system
- * @{
- */
-
-/** @addtogroup STM32F4xx_System_Private_Includes
- * @{
- */
-
-
-#include "stm32f4xx.h"
-
-#if !defined (HSE_VALUE)
- #define HSE_VALUE ((uint32_t)8000000) /*!< Default value of the External oscillator in Hz */
-#endif /* HSE_VALUE */
-
-#if !defined (HSI_VALUE)
- #define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/
-#endif /* HSI_VALUE */
-
-/**
- * @}
- */
-
-/** @addtogroup STM32F4xx_System_Private_TypesDefinitions
- * @{
- */
-
-/**
- * @}
- */
-
-/** @addtogroup STM32F4xx_System_Private_Defines
- * @{
- */
-
-/************************* Miscellaneous Configuration ************************/
-/*!< Uncomment the following line if you need to relocate your vector Table in
- Internal SRAM. */
-/* #define VECT_TAB_SRAM */
-#define VECT_TAB_OFFSET 0x40000 /*!< Vector Table base offset field.
- This value must be a multiple of 0x200. */
-/******************************************************************************/
-
-/**
- * @}
- */
-
-/** @addtogroup STM32F4xx_System_Private_Macros
- * @{
- */
-
-/**
- * @}
- */
-
-/** @addtogroup STM32F4xx_System_Private_Variables
- * @{
- */
- /* This variable is updated in three ways:
- 1) by calling CMSIS function SystemCoreClockUpdate()
- 2) by calling HAL API function HAL_RCC_GetHCLKFreq()
- 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
- Note: If you use this function to configure the system clock; then there
- is no need to call the 2 first functions listed above, since SystemCoreClock
- variable is updated automatically.
- */
-uint32_t SystemCoreClock = 16000000;
-const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
-const uint8_t APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4};
-/**
- * @}
- */
-
-
-/** @addtogroup STM32F4xx_System_Private_Functions
- * @{
- */
-
-/**
- * @brief Setup the microcontroller system
- * Initialize the FPU setting, vector table location and External memory
- * configuration.
- * @param None
- * @retval None
- */
-void SystemInit(void)
-{
- /* FPU settings ------------------------------------------------------------*/
- #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
- SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */
- #endif
- /* Reset the RCC clock configuration to the default reset state ------------*/
- /* Set HSION bit */
- RCC->CR |= (uint32_t)0x00000001;
-
- /* Reset CFGR register */
- RCC->CFGR = 0x00000000;
-
- /* Reset HSEON, CSSON and PLLON bits */
- RCC->CR &= (uint32_t)0xFEF6FFFF;
-
- /* Reset PLLCFGR register */
- RCC->PLLCFGR = 0x24003010;
-
- /* Reset HSEBYP bit */
- RCC->CR &= (uint32_t)0xFFFBFFFF;
-
- /* Disable all interrupts */
- RCC->CIR = 0x00000000;
-
-
- /* Configure the Vector Table location add offset address ------------------*/
-#ifdef VECT_TAB_SRAM
- SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
-#else
- SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
-#endif
-}
-
-/**
- * @brief Update SystemCoreClock variable according to Clock Register Values.
- * The SystemCoreClock variable contains the core clock (HCLK), it can
- * be used by the user application to setup the SysTick timer or configure
- * other parameters.
- *
- * @note Each time the core clock (HCLK) changes, this function must be called
- * to update SystemCoreClock variable value. Otherwise, any configuration
- * based on this variable will be incorrect.
- *
- * @note - The system frequency computed by this function is not the real
- * frequency in the chip. It is calculated based on the predefined
- * constant and the selected clock source:
- *
- * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
- *
- * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
- *
- * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
- * or HSI_VALUE(*) multiplied/divided by the PLL factors.
- *
- * (*) HSI_VALUE is a constant defined in stm32f4xx_hal_conf.h file (default value
- * 16 MHz) but the real value may vary depending on the variations
- * in voltage and temperature.
- *
- * (**) HSE_VALUE is a constant defined in stm32f4xx_hal_conf.h file (its value
- * depends on the application requirements), user has to ensure that HSE_VALUE
- * is same as the real frequency of the crystal used. Otherwise, this function
- * may have wrong result.
- *
- * - The result of this function could be not correct when using fractional
- * value for HSE crystal.
- *
- * @param None
- * @retval None
- */
-void SystemCoreClockUpdate(void)
-{
- uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2;
-
- /* Get SYSCLK source -------------------------------------------------------*/
- tmp = RCC->CFGR & RCC_CFGR_SWS;
-
- switch (tmp)
- {
- case 0x00: /* HSI used as system clock source */
- SystemCoreClock = HSI_VALUE;
- break;
- case 0x04: /* HSE used as system clock source */
- SystemCoreClock = HSE_VALUE;
- break;
- case 0x08: /* PLL used as system clock source */
-
- /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N
- SYSCLK = PLL_VCO / PLL_P
- */
- pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22;
- pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
-
- if (pllsource != 0)
- {
- /* HSE used as PLL clock source */
- pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
- }
- else
- {
- /* HSI used as PLL clock source */
- pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
- }
-
- pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2;
- SystemCoreClock = pllvco/pllp;
- break;
- default:
- SystemCoreClock = HSI_VALUE;
- break;
- }
- /* Compute HCLK frequency --------------------------------------------------*/
- /* Get HCLK prescaler */
- tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
- /* HCLK frequency */
- SystemCoreClock >>= tmp;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/