Bugfix simulator/planer: For deco calculation two structures are used. The calculation structure and the input structure. During simulation fast forward (+5min) the input structure is manipulated. Especially for vpm calculation it could happen that the input structure was manipulated and then overwritten by the calculation structure => deco and tts may have wrong values. To avoid this thedeco calculation status is now checked before doing the FF manupulation. Based an calculation state deco or input structures are manipulated. Surface time stamp in planer view: The planer used its own (buggy) implementation for calculation of tts. The timestamp for the surface arrival did not match the bottom time + TTS. The new implementation uses the tts calculated by the deco loop for generation of surface time stamp.

# How to Create From Scratch a Project for _CPU2-RTE_ Code #

Follow the same procedure than for [CPU1](Detailed CPU1-Discovery Project.md), with changes:

- Create a new _board_ for processor:  
>   Series: `STM32F4`  
>   Mcu: `STM32F411xE`  
>   Debug: `JTAG`  

- Add `Small_CPU` linked source directory (instead of _Discovery_)

- Use linker script `OSTC4/Small_CPU/CPU2-F411.ld`