Mercurial > public > ostc4
view Common/Drivers/STM32F4xx/Include/stm32f469xx.h @ 924:4d98fb2a178e Evo_2_23
Bugfix real scrubber time decreased in sim mode:
In the previous version the condition check for dive / simulation had been commented out causing the scrubber timer to be decreased during simulator usage. The problem has been fixed. In addition the scrubbertimer will now be maintained in simulator mode. In case the +5 minutes option is used the scrubber time is decreased by 5 minutes as well.
| author | Ideenmodellierer |
|---|---|
| date | Wed, 13 Nov 2024 17:55:05 +0100 |
| parents | c78bcbd5deda |
| children |
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/** ****************************************************************************** * @file stm32f469xx.h * @author MCD Application Team * @brief CMSIS STM32F469xx Device Peripheral Access Layer Header File. * * This file contains: * - Data structures and the address mapping for all peripherals * - peripherals registers declarations and bits definition * - Macros to access peripheral’s registers hardware * ****************************************************************************** * @attention * * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2> * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: * 1. Redistributions of source code must retain the above copyright notice, * this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright notice, * this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. * 3. Neither the name of STMicroelectronics nor the names of its contributors * may be used to endorse or promote products derived from this software * without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * ****************************************************************************** */ /** @addtogroup CMSIS_Device * @{ */ /** @addtogroup stm32f469xx * @{ */ #ifndef __STM32F469xx_H #define __STM32F469xx_H #ifdef __cplusplus extern "C" { #endif /* __cplusplus */ /** @addtogroup Configuration_section_for_CMSIS * @{ */ /** * @brief Configuration of the Cortex-M4 Processor and Core Peripherals */ #define __CM4_REV 0x0001U /*!< Core revision r0p1 */ #define __MPU_PRESENT 1U /*!< STM32F4XX provides an MPU */ #define __NVIC_PRIO_BITS 4U /*!< STM32F4XX uses 4 Bits for the Priority Levels */ #define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */ #define __FPU_PRESENT 1U /*!< FPU present */ /** * @} */ /** @addtogroup Peripheral_interrupt_number_definition * @{ */ /** * @brief STM32F4XX Interrupt Number Definition, according to the selected device * in @ref Library_configuration_section */ typedef enum { /****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/ NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */ BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */ UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */ SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */ DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */ PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */ SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */ /****** STM32 specific Interrupt Numbers **********************************************************************/ WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */ PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */ TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */ RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line */ FLASH_IRQn = 4, /*!< FLASH global Interrupt */ RCC_IRQn = 5, /*!< RCC global Interrupt */ EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */ EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */ EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */ EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */ EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */ DMA1_Stream0_IRQn = 11, /*!< DMA1 Stream 0 global Interrupt */ DMA1_Stream1_IRQn = 12, /*!< DMA1 Stream 1 global Interrupt */ DMA1_Stream2_IRQn = 13, /*!< DMA1 Stream 2 global Interrupt */ DMA1_Stream3_IRQn = 14, /*!< DMA1 Stream 3 global Interrupt */ DMA1_Stream4_IRQn = 15, /*!< DMA1 Stream 4 global Interrupt */ DMA1_Stream5_IRQn = 16, /*!< DMA1 Stream 5 global Interrupt */ DMA1_Stream6_IRQn = 17, /*!< DMA1 Stream 6 global Interrupt */ ADC_IRQn = 18, /*!< ADC1, ADC2 and ADC3 global Interrupts */ CAN1_TX_IRQn = 19, /*!< CAN1 TX Interrupt */ CAN1_RX0_IRQn = 20, /*!< CAN1 RX0 Interrupt */ CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */ CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */ EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ TIM1_BRK_TIM9_IRQn = 24, /*!< TIM1 Break interrupt and TIM9 global interrupt */ TIM1_UP_TIM10_IRQn = 25, /*!< TIM1 Update Interrupt and TIM10 global interrupt */ TIM1_TRG_COM_TIM11_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */ TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ USART1_IRQn = 37, /*!< USART1 global Interrupt */ USART2_IRQn = 38, /*!< USART2 global Interrupt */ USART3_IRQn = 39, /*!< USART3 global Interrupt */ EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */ OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS Wakeup through EXTI line interrupt */ TIM8_BRK_TIM12_IRQn = 43, /*!< TIM8 Break Interrupt and TIM12 global interrupt */ TIM8_UP_TIM13_IRQn = 44, /*!< TIM8 Update Interrupt and TIM13 global interrupt */ TIM8_TRG_COM_TIM14_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */ TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare global interrupt */ DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */ FMC_IRQn = 48, /*!< FMC global Interrupt */ SDIO_IRQn = 49, /*!< SDIO global Interrupt */ TIM5_IRQn = 50, /*!< TIM5 global Interrupt */ SPI3_IRQn = 51, /*!< SPI3 global Interrupt */ UART4_IRQn = 52, /*!< UART4 global Interrupt */ UART5_IRQn = 53, /*!< UART5 global Interrupt */ TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC1&2 underrun error interrupts */ TIM7_IRQn = 55, /*!< TIM7 global interrupt */ DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */ DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */ DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */ DMA2_Stream3_IRQn = 59, /*!< DMA2 Stream 3 global Interrupt */ DMA2_Stream4_IRQn = 60, /*!< DMA2 Stream 4 global Interrupt */ ETH_IRQn = 61, /*!< Ethernet global Interrupt */ ETH_WKUP_IRQn = 62, /*!< Ethernet Wakeup through EXTI line Interrupt */ CAN2_TX_IRQn = 63, /*!< CAN2 TX Interrupt */ CAN2_RX0_IRQn = 64, /*!< CAN2 RX0 Interrupt */ CAN2_RX1_IRQn = 65, /*!< CAN2 RX1 Interrupt */ CAN2_SCE_IRQn = 66, /*!< CAN2 SCE Interrupt */ OTG_FS_IRQn = 67, /*!< USB OTG FS global Interrupt */ DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */ DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */ DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */ USART6_IRQn = 71, /*!< USART6 global interrupt */ I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */ I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */ OTG_HS_EP1_OUT_IRQn = 74, /*!< USB OTG HS End Point 1 Out global interrupt */ OTG_HS_EP1_IN_IRQn = 75, /*!< USB OTG HS End Point 1 In global interrupt */ OTG_HS_WKUP_IRQn = 76, /*!< USB OTG HS Wakeup through EXTI interrupt */ OTG_HS_IRQn = 77, /*!< USB OTG HS global interrupt */ DCMI_IRQn = 78, /*!< DCMI global interrupt */ HASH_RNG_IRQn = 80, /*!< Hash and Rng global interrupt */ FPU_IRQn = 81, /*!< FPU global interrupt */ UART7_IRQn = 82, /*!< UART7 global interrupt */ UART8_IRQn = 83, /*!< UART8 global interrupt */ SPI4_IRQn = 84, /*!< SPI4 global Interrupt */ SPI5_IRQn = 85, /*!< SPI5 global Interrupt */ SPI6_IRQn = 86, /*!< SPI6 global Interrupt */ SAI1_IRQn = 87, /*!< SAI1 global Interrupt */ LTDC_IRQn = 88, /*!< LTDC global Interrupt */ LTDC_ER_IRQn = 89, /*!< LTDC Error global Interrupt */ DMA2D_IRQn = 90, /*!< DMA2D global Interrupt */ QUADSPI_IRQn = 91, /*!< QUADSPI global Interrupt */ DSI_IRQn = 92 /*!< DSI global Interrupt */ } IRQn_Type; /** * @} */ #include "core_cm4.h" /* Cortex-M4 processor and core peripherals */ #include "system_stm32f4xx.h" #include <stdint.h> /** @addtogroup Peripheral_registers_structures * @{ */ /** * @brief Analog to Digital Converter */ typedef struct { __IO uint32_t SR; /*!< ADC status register, Address offset: 0x00 */ __IO uint32_t CR1; /*!< ADC control register 1, Address offset: 0x04 */ __IO uint32_t CR2; /*!< ADC control register 2, Address offset: 0x08 */ __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x0C */ __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x10 */ __IO uint32_t JOFR1; /*!< ADC injected channel data offset register 1, Address offset: 0x14 */ __IO uint32_t JOFR2; /*!< ADC injected channel data offset register 2, Address offset: 0x18 */ __IO uint32_t JOFR3; /*!< ADC injected channel data offset register 3, Address offset: 0x1C */ __IO uint32_t JOFR4; /*!< ADC injected channel data offset register 4, Address offset: 0x20 */ __IO uint32_t HTR; /*!< ADC watchdog higher threshold register, Address offset: 0x24 */ __IO uint32_t LTR; /*!< ADC watchdog lower threshold register, Address offset: 0x28 */ __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x2C */ __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x30 */ __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x34 */ __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x38*/ __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x3C */ __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x40 */ __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x44 */ __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x48 */ __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x4C */ } ADC_TypeDef; typedef struct { __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1 base address + 0x300 */ __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1 base address + 0x304 */ __IO uint32_t CDR; /*!< ADC common regular data register for dual AND triple modes, Address offset: ADC1 base address + 0x308 */ } ADC_Common_TypeDef; /** * @brief Controller Area Network TxMailBox */ typedef struct { __IO uint32_t TIR; /*!< CAN TX mailbox identifier register */ __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */ __IO uint32_t TDLR; /*!< CAN mailbox data low register */ __IO uint32_t TDHR; /*!< CAN mailbox data high register */ } CAN_TxMailBox_TypeDef; /** * @brief Controller Area Network FIFOMailBox */ typedef struct { __IO uint32_t RIR; /*!< CAN receive FIFO mailbox identifier register */ __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */ __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */ __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */ } CAN_FIFOMailBox_TypeDef; /** * @brief Controller Area Network FilterRegister */ typedef struct { __IO uint32_t FR1; /*!< CAN Filter bank register 1 */ __IO uint32_t FR2; /*!< CAN Filter bank register 1 */ } CAN_FilterRegister_TypeDef; /** * @brief Controller Area Network */ typedef struct { __IO uint32_t MCR; /*!< CAN master control register, Address offset: 0x00 */ __IO uint32_t MSR; /*!< CAN master status register, Address offset: 0x04 */ __IO uint32_t TSR; /*!< CAN transmit status register, Address offset: 0x08 */ __IO uint32_t RF0R; /*!< CAN receive FIFO 0 register, Address offset: 0x0C */ __IO uint32_t RF1R; /*!< CAN receive FIFO 1 register, Address offset: 0x10 */ __IO uint32_t IER; /*!< CAN interrupt enable register, Address offset: 0x14 */ __IO uint32_t ESR; /*!< CAN error status register, Address offset: 0x18 */ __IO uint32_t BTR; /*!< CAN bit timing register, Address offset: 0x1C */ uint32_t RESERVED0[88]; /*!< Reserved, 0x020 - 0x17F */ CAN_TxMailBox_TypeDef sTxMailBox[3]; /*!< CAN Tx MailBox, Address offset: 0x180 - 0x1AC */ CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; /*!< CAN FIFO MailBox, Address offset: 0x1B0 - 0x1CC */ uint32_t RESERVED1[12]; /*!< Reserved, 0x1D0 - 0x1FF */ __IO uint32_t FMR; /*!< CAN filter master register, Address offset: 0x200 */ __IO uint32_t FM1R; /*!< CAN filter mode register, Address offset: 0x204 */ uint32_t RESERVED2; /*!< Reserved, 0x208 */ __IO uint32_t FS1R; /*!< CAN filter scale register, Address offset: 0x20C */ uint32_t RESERVED3; /*!< Reserved, 0x210 */ __IO uint32_t FFA1R; /*!< CAN filter FIFO assignment register, Address offset: 0x214 */ uint32_t RESERVED4; /*!< Reserved, 0x218 */ __IO uint32_t FA1R; /*!< CAN filter activation register, Address offset: 0x21C */ uint32_t RESERVED5[8]; /*!< Reserved, 0x220-0x23F */ CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register, Address offset: 0x240-0x31C */ } CAN_TypeDef; /** * @brief CRC calculation unit */ typedef struct { __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ uint8_t RESERVED0; /*!< Reserved, 0x05 */ uint16_t RESERVED1; /*!< Reserved, 0x06 */ __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ } CRC_TypeDef; /** * @brief Digital to Analog Converter */ typedef struct { __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */ __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */ __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */ __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */ __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */ __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */ __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */ __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */ __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */ __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */ __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */ __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */ __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */ __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */ } DAC_TypeDef; /** * @brief Debug MCU */ typedef struct { __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */ __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */ __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */ }DBGMCU_TypeDef; /** * @brief DCMI */ typedef struct { __IO uint32_t CR; /*!< DCMI control register 1, Address offset: 0x00 */ __IO uint32_t SR; /*!< DCMI status register, Address offset: 0x04 */ __IO uint32_t RISR; /*!< DCMI raw interrupt status register, Address offset: 0x08 */ __IO uint32_t IER; /*!< DCMI interrupt enable register, Address offset: 0x0C */ __IO uint32_t MISR; /*!< DCMI masked interrupt status register, Address offset: 0x10 */ __IO uint32_t ICR; /*!< DCMI interrupt clear register, Address offset: 0x14 */ __IO uint32_t ESCR; /*!< DCMI embedded synchronization code register, Address offset: 0x18 */ __IO uint32_t ESUR; /*!< DCMI embedded synchronization unmask register, Address offset: 0x1C */ __IO uint32_t CWSTRTR; /*!< DCMI crop window start, Address offset: 0x20 */ __IO uint32_t CWSIZER; /*!< DCMI crop window size, Address offset: 0x24 */ __IO uint32_t DR; /*!< DCMI data register, Address offset: 0x28 */ } DCMI_TypeDef; /** * @brief DMA Controller */ typedef struct { __IO uint32_t CR; /*!< DMA stream x configuration register */ __IO uint32_t NDTR; /*!< DMA stream x number of data register */ __IO uint32_t PAR; /*!< DMA stream x peripheral address register */ __IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */ __IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */ __IO uint32_t FCR; /*!< DMA stream x FIFO control register */ } DMA_Stream_TypeDef; typedef struct { __IO uint32_t LISR; /*!< DMA low interrupt status register, Address offset: 0x00 */ __IO uint32_t HISR; /*!< DMA high interrupt status register, Address offset: 0x04 */ __IO uint32_t LIFCR; /*!< DMA low interrupt flag clear register, Address offset: 0x08 */ __IO uint32_t HIFCR; /*!< DMA high interrupt flag clear register, Address offset: 0x0C */ } DMA_TypeDef; /** * @brief DMA2D Controller */ typedef struct { __IO uint32_t CR; /*!< DMA2D Control Register, Address offset: 0x00 */ __IO uint32_t ISR; /*!< DMA2D Interrupt Status Register, Address offset: 0x04 */ __IO uint32_t IFCR; /*!< DMA2D Interrupt Flag Clear Register, Address offset: 0x08 */ __IO uint32_t FGMAR; /*!< DMA2D Foreground Memory Address Register, Address offset: 0x0C */ __IO uint32_t FGOR; /*!< DMA2D Foreground Offset Register, Address offset: 0x10 */ __IO uint32_t BGMAR; /*!< DMA2D Background Memory Address Register, Address offset: 0x14 */ __IO uint32_t BGOR; /*!< DMA2D Background Offset Register, Address offset: 0x18 */ __IO uint32_t FGPFCCR; /*!< DMA2D Foreground PFC Control Register, Address offset: 0x1C */ __IO uint32_t FGCOLR; /*!< DMA2D Foreground Color Register, Address offset: 0x20 */ __IO uint32_t BGPFCCR; /*!< DMA2D Background PFC Control Register, Address offset: 0x24 */ __IO uint32_t BGCOLR; /*!< DMA2D Background Color Register, Address offset: 0x28 */ __IO uint32_t FGCMAR; /*!< DMA2D Foreground CLUT Memory Address Register, Address offset: 0x2C */ __IO uint32_t BGCMAR; /*!< DMA2D Background CLUT Memory Address Register, Address offset: 0x30 */ __IO uint32_t OPFCCR; /*!< DMA2D Output PFC Control Register, Address offset: 0x34 */ __IO uint32_t OCOLR; /*!< DMA2D Output Color Register, Address offset: 0x38 */ __IO uint32_t OMAR; /*!< DMA2D Output Memory Address Register, Address offset: 0x3C */ __IO uint32_t OOR; /*!< DMA2D Output Offset Register, Address offset: 0x40 */ __IO uint32_t NLR; /*!< DMA2D Number of Line Register, Address offset: 0x44 */ __IO uint32_t LWR; /*!< DMA2D Line Watermark Register, Address offset: 0x48 */ __IO uint32_t AMTCR; /*!< DMA2D AHB Master Timer Configuration Register, Address offset: 0x4C */ uint32_t RESERVED[236]; /*!< Reserved, 0x50-0x3FF */ __IO uint32_t FGCLUT[256]; /*!< DMA2D Foreground CLUT, Address offset:400-7FF */ __IO uint32_t BGCLUT[256]; /*!< DMA2D Background CLUT, Address offset:800-BFF */ } DMA2D_TypeDef; /** * @brief DSI Controller */ typedef struct { __IO uint32_t VR; /*!< DSI Host Version Register, Address offset: 0x00 */ __IO uint32_t CR; /*!< DSI Host Control Register, Address offset: 0x04 */ __IO uint32_t CCR; /*!< DSI HOST Clock Control Register, Address offset: 0x08 */ __IO uint32_t LVCIDR; /*!< DSI Host LTDC VCID Register, Address offset: 0x0C */ __IO uint32_t LCOLCR; /*!< DSI Host LTDC Color Coding Register, Address offset: 0x10 */ __IO uint32_t LPCR; /*!< DSI Host LTDC Polarity Configuration Register, Address offset: 0x14 */ __IO uint32_t LPMCR; /*!< DSI Host Low-Power Mode Configuration Register, Address offset: 0x18 */ uint32_t RESERVED0[4]; /*!< Reserved, 0x1C - 0x2B */ __IO uint32_t PCR; /*!< DSI Host Protocol Configuration Register, Address offset: 0x2C */ __IO uint32_t GVCIDR; /*!< DSI Host Generic VCID Register, Address offset: 0x30 */ __IO uint32_t MCR; /*!< DSI Host Mode Configuration Register, Address offset: 0x34 */ __IO uint32_t VMCR; /*!< DSI Host Video Mode Configuration Register, Address offset: 0x38 */ __IO uint32_t VPCR; /*!< DSI Host Video Packet Configuration Register, Address offset: 0x3C */ __IO uint32_t VCCR; /*!< DSI Host Video Chunks Configuration Register, Address offset: 0x40 */ __IO uint32_t VNPCR; /*!< DSI Host Video Null Packet Configuration Register, Address offset: 0x44 */ __IO uint32_t VHSACR; /*!< DSI Host Video HSA Configuration Register, Address offset: 0x48 */ __IO uint32_t VHBPCR; /*!< DSI Host Video HBP Configuration Register, Address offset: 0x4C */ __IO uint32_t VLCR; /*!< DSI Host Video Line Configuration Register, Address offset: 0x50 */ __IO uint32_t VVSACR; /*!< DSI Host Video VSA Configuration Register, Address offset: 0x54 */ __IO uint32_t VVBPCR; /*!< DSI Host Video VBP Configuration Register, Address offset: 0x58 */ __IO uint32_t VVFPCR; /*!< DSI Host Video VFP Configuration Register, Address offset: 0x5C */ __IO uint32_t VVACR; /*!< DSI Host Video VA Configuration Register, Address offset: 0x60 */ __IO uint32_t LCCR; /*!< DSI Host LTDC Command Configuration Register, Address offset: 0x64 */ __IO uint32_t CMCR; /*!< DSI Host Command Mode Configuration Register, Address offset: 0x68 */ __IO uint32_t GHCR; /*!< DSI Host Generic Header Configuration Register, Address offset: 0x6C */ __IO uint32_t GPDR; /*!< DSI Host Generic Payload Data Register, Address offset: 0x70 */ __IO uint32_t GPSR; /*!< DSI Host Generic Packet Status Register, Address offset: 0x74 */ __IO uint32_t TCCR[6]; /*!< DSI Host Timeout Counter Configuration Register, Address offset: 0x78-0x8F */ __IO uint32_t TDCR; /*!< DSI Host 3D Configuration Register, Address offset: 0x90 */ __IO uint32_t CLCR; /*!< DSI Host Clock Lane Configuration Register, Address offset: 0x94 */ __IO uint32_t CLTCR; /*!< DSI Host Clock Lane Timer Configuration Register, Address offset: 0x98 */ __IO uint32_t DLTCR; /*!< DSI Host Data Lane Timer Configuration Register, Address offset: 0x9C */ __IO uint32_t PCTLR; /*!< DSI Host PHY Control Register, Address offset: 0xA0 */ __IO uint32_t PCONFR; /*!< DSI Host PHY Configuration Register, Address offset: 0xA4 */ __IO uint32_t PUCR; /*!< DSI Host PHY ULPS Control Register, Address offset: 0xA8 */ __IO uint32_t PTTCR; /*!< DSI Host PHY TX Triggers Configuration Register, Address offset: 0xAC */ __IO uint32_t PSR; /*!< DSI Host PHY Status Register, Address offset: 0xB0 */ uint32_t RESERVED1[2]; /*!< Reserved, 0xB4 - 0xBB */ __IO uint32_t ISR[2]; /*!< DSI Host Interrupt & Status Register, Address offset: 0xBC-0xC3 */ __IO uint32_t IER[2]; /*!< DSI Host Interrupt Enable Register, Address offset: 0xC4-0xCB */ uint32_t RESERVED2[3]; /*!< Reserved, 0xD0 - 0xD7 */ __IO uint32_t FIR[2]; /*!< DSI Host Force Interrupt Register, Address offset: 0xD8-0xDF */ uint32_t RESERVED3[8]; /*!< Reserved, 0xE0 - 0xFF */ __IO uint32_t VSCR; /*!< DSI Host Video Shadow Control Register, Address offset: 0x100 */ uint32_t RESERVED4[2]; /*!< Reserved, 0x104 - 0x10B */ __IO uint32_t LCVCIDR; /*!< DSI Host LTDC Current VCID Register, Address offset: 0x10C */ __IO uint32_t LCCCR; /*!< DSI Host LTDC Current Color Coding Register, Address offset: 0x110 */ uint32_t RESERVED5; /*!< Reserved, 0x114 */ __IO uint32_t LPMCCR; /*!< DSI Host Low-power Mode Current Configuration Register, Address offset: 0x118 */ uint32_t RESERVED6[7]; /*!< Reserved, 0x11C - 0x137 */ __IO uint32_t VMCCR; /*!< DSI Host Video Mode Current Configuration Register, Address offset: 0x138 */ __IO uint32_t VPCCR; /*!< DSI Host Video Packet Current Configuration Register, Address offset: 0x13C */ __IO uint32_t VCCCR; /*!< DSI Host Video Chuncks Current Configuration Register, Address offset: 0x140 */ __IO uint32_t VNPCCR; /*!< DSI Host Video Null Packet Current Configuration Register, Address offset: 0x144 */ __IO uint32_t VHSACCR; /*!< DSI Host Video HSA Current Configuration Register, Address offset: 0x148 */ __IO uint32_t VHBPCCR; /*!< DSI Host Video HBP Current Configuration Register, Address offset: 0x14C */ __IO uint32_t VLCCR; /*!< DSI Host Video Line Current Configuration Register, Address offset: 0x150 */ __IO uint32_t VVSACCR; /*!< DSI Host Video VSA Current Configuration Register, Address offset: 0x154 */ __IO uint32_t VVBPCCR; /*!< DSI Host Video VBP Current Configuration Register, Address offset: 0x158 */ __IO uint32_t VVFPCCR; /*!< DSI Host Video VFP Current Configuration Register, Address offset: 0x15C */ __IO uint32_t VVACCR; /*!< DSI Host Video VA Current Configuration Register, Address offset: 0x160 */ uint32_t RESERVED7[11]; /*!< Reserved, 0x164 - 0x18F */ __IO uint32_t TDCCR; /*!< DSI Host 3D Current Configuration Register, Address offset: 0x190 */ uint32_t RESERVED8[155]; /*!< Reserved, 0x194 - 0x3FF */ __IO uint32_t WCFGR; /*!< DSI Wrapper Configuration Register, Address offset: 0x400 */ __IO uint32_t WCR; /*!< DSI Wrapper Control Register, Address offset: 0x404 */ __IO uint32_t WIER; /*!< DSI Wrapper Interrupt Enable Register, Address offset: 0x408 */ __IO uint32_t WISR; /*!< DSI Wrapper Interrupt and Status Register, Address offset: 0x40C */ __IO uint32_t WIFCR; /*!< DSI Wrapper Interrupt Flag Clear Register, Address offset: 0x410 */ uint32_t RESERVED9; /*!< Reserved, 0x414 */ __IO uint32_t WPCR[5]; /*!< DSI Wrapper PHY Configuration Register, Address offset: 0x418-0x42B */ uint32_t RESERVED10; /*!< Reserved, 0x42C */ __IO uint32_t WRPCR; /*!< DSI Wrapper Regulator and PLL Control Register, Address offset: 0x430 */ } DSI_TypeDef; /** * @brief Ethernet MAC */ typedef struct { __IO uint32_t MACCR; __IO uint32_t MACFFR; __IO uint32_t MACHTHR; __IO uint32_t MACHTLR; __IO uint32_t MACMIIAR; __IO uint32_t MACMIIDR; __IO uint32_t MACFCR; __IO uint32_t MACVLANTR; /* 8 */ uint32_t RESERVED0[2]; __IO uint32_t MACRWUFFR; /* 11 */ __IO uint32_t MACPMTCSR; uint32_t RESERVED1; __IO uint32_t MACDBGR; __IO uint32_t MACSR; /* 15 */ __IO uint32_t MACIMR; __IO uint32_t MACA0HR; __IO uint32_t MACA0LR; __IO uint32_t MACA1HR; __IO uint32_t MACA1LR; __IO uint32_t MACA2HR; __IO uint32_t MACA2LR; __IO uint32_t MACA3HR; __IO uint32_t MACA3LR; /* 24 */ uint32_t RESERVED2[40]; __IO uint32_t MMCCR; /* 65 */ __IO uint32_t MMCRIR; __IO uint32_t MMCTIR; __IO uint32_t MMCRIMR; __IO uint32_t MMCTIMR; /* 69 */ uint32_t RESERVED3[14]; __IO uint32_t MMCTGFSCCR; /* 84 */ __IO uint32_t MMCTGFMSCCR; uint32_t RESERVED4[5]; __IO uint32_t MMCTGFCR; uint32_t RESERVED5[10]; __IO uint32_t MMCRFCECR; __IO uint32_t MMCRFAECR; uint32_t RESERVED6[10]; __IO uint32_t MMCRGUFCR; uint32_t RESERVED7[334]; __IO uint32_t PTPTSCR; __IO uint32_t PTPSSIR; __IO uint32_t PTPTSHR; __IO uint32_t PTPTSLR; __IO uint32_t PTPTSHUR; __IO uint32_t PTPTSLUR; __IO uint32_t PTPTSAR; __IO uint32_t PTPTTHR; __IO uint32_t PTPTTLR; __IO uint32_t RESERVED8; __IO uint32_t PTPTSSR; uint32_t RESERVED9[565]; __IO uint32_t DMABMR; __IO uint32_t DMATPDR; __IO uint32_t DMARPDR; __IO uint32_t DMARDLAR; __IO uint32_t DMATDLAR; __IO uint32_t DMASR; __IO uint32_t DMAOMR; __IO uint32_t DMAIER; __IO uint32_t DMAMFBOCR; __IO uint32_t DMARSWTR; uint32_t RESERVED10[8]; __IO uint32_t DMACHTDR; __IO uint32_t DMACHRDR; __IO uint32_t DMACHTBAR; __IO uint32_t DMACHRBAR; } ETH_TypeDef; /** * @brief External Interrupt/Event Controller */ typedef struct { __IO uint32_t IMR; /*!< EXTI Interrupt mask register, Address offset: 0x00 */ __IO uint32_t EMR; /*!< EXTI Event mask register, Address offset: 0x04 */ __IO uint32_t RTSR; /*!< EXTI Rising trigger selection register, Address offset: 0x08 */ __IO uint32_t FTSR; /*!< EXTI Falling trigger selection register, Address offset: 0x0C */ __IO uint32_t SWIER; /*!< EXTI Software interrupt event register, Address offset: 0x10 */ __IO uint32_t PR; /*!< EXTI Pending register, Address offset: 0x14 */ } EXTI_TypeDef; /** * @brief FLASH Registers */ typedef struct { __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */ __IO uint32_t KEYR; /*!< FLASH key register, Address offset: 0x04 */ __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x08 */ __IO uint32_t SR; /*!< FLASH status register, Address offset: 0x0C */ __IO uint32_t CR; /*!< FLASH control register, Address offset: 0x10 */ __IO uint32_t OPTCR; /*!< FLASH option control register , Address offset: 0x14 */ __IO uint32_t OPTCR1; /*!< FLASH option control register 1, Address offset: 0x18 */ } FLASH_TypeDef; /** * @brief Flexible Memory Controller */ typedef struct { __IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */ } FMC_Bank1_TypeDef; /** * @brief Flexible Memory Controller Bank1E */ typedef struct { __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */ } FMC_Bank1E_TypeDef; /** * @brief Flexible Memory Controller Bank3 */ typedef struct { __IO uint32_t PCR; /*!< NAND Flash control register, Address offset: 0x80 */ __IO uint32_t SR; /*!< NAND Flash FIFO status and interrupt register, Address offset: 0x84 */ __IO uint32_t PMEM; /*!< NAND Flash Common memory space timing register, Address offset: 0x88 */ __IO uint32_t PATT; /*!< NAND Flash Attribute memory space timing register, Address offset: 0x8C */ uint32_t RESERVED; /*!< Reserved, 0x90 */ __IO uint32_t ECCR; /*!< NAND Flash ECC result registers, Address offset: 0x94 */ } FMC_Bank3_TypeDef; /** * @brief Flexible Memory Controller Bank5_6 */ typedef struct { __IO uint32_t SDCR[2]; /*!< SDRAM Control registers , Address offset: 0x140-0x144 */ __IO uint32_t SDTR[2]; /*!< SDRAM Timing registers , Address offset: 0x148-0x14C */ __IO uint32_t SDCMR; /*!< SDRAM Command Mode register, Address offset: 0x150 */ __IO uint32_t SDRTR; /*!< SDRAM Refresh Timer register, Address offset: 0x154 */ __IO uint32_t SDSR; /*!< SDRAM Status register, Address offset: 0x158 */ } FMC_Bank5_6_TypeDef; /** * @brief General Purpose I/O */ typedef struct { __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */ __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */ __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */ __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */ __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */ __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */ __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */ __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */ __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */ } GPIO_TypeDef; /** * @brief System configuration controller */ typedef struct { __IO uint32_t MEMRMP; /*!< SYSCFG memory remap register, Address offset: 0x00 */ __IO uint32_t PMC; /*!< SYSCFG peripheral mode configuration register, Address offset: 0x04 */ __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */ uint32_t RESERVED[2]; /*!< Reserved, 0x18-0x1C */ __IO uint32_t CMPCR; /*!< SYSCFG Compensation cell control register, Address offset: 0x20 */ } SYSCFG_TypeDef; /** * @brief Inter-integrated Circuit Interface */ typedef struct { __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */ __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */ __IO uint32_t OAR1; /*!< I2C Own address register 1, Address offset: 0x08 */ __IO uint32_t OAR2; /*!< I2C Own address register 2, Address offset: 0x0C */ __IO uint32_t DR; /*!< I2C Data register, Address offset: 0x10 */ __IO uint32_t SR1; /*!< I2C Status register 1, Address offset: 0x14 */ __IO uint32_t SR2; /*!< I2C Status register 2, Address offset: 0x18 */ __IO uint32_t CCR; /*!< I2C Clock control register, Address offset: 0x1C */ __IO uint32_t TRISE; /*!< I2C TRISE register, Address offset: 0x20 */ __IO uint32_t FLTR; /*!< I2C FLTR register, Address offset: 0x24 */ } I2C_TypeDef; /** * @brief Independent WATCHDOG */ typedef struct { __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */ __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */ __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */ __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */ } IWDG_TypeDef; /** * @brief LCD-TFT Display Controller */ typedef struct { uint32_t RESERVED0[2]; /*!< Reserved, 0x00-0x04 */ __IO uint32_t SSCR; /*!< LTDC Synchronization Size Configuration Register, Address offset: 0x08 */ __IO uint32_t BPCR; /*!< LTDC Back Porch Configuration Register, Address offset: 0x0C */ __IO uint32_t AWCR; /*!< LTDC Active Width Configuration Register, Address offset: 0x10 */ __IO uint32_t TWCR; /*!< LTDC Total Width Configuration Register, Address offset: 0x14 */ __IO uint32_t GCR; /*!< LTDC Global Control Register, Address offset: 0x18 */ uint32_t RESERVED1[2]; /*!< Reserved, 0x1C-0x20 */ __IO uint32_t SRCR; /*!< LTDC Shadow Reload Configuration Register, Address offset: 0x24 */ uint32_t RESERVED2[1]; /*!< Reserved, 0x28 */ __IO uint32_t BCCR; /*!< LTDC Background Color Configuration Register, Address offset: 0x2C */ uint32_t RESERVED3[1]; /*!< Reserved, 0x30 */ __IO uint32_t IER; /*!< LTDC Interrupt Enable Register, Address offset: 0x34 */ __IO uint32_t ISR; /*!< LTDC Interrupt Status Register, Address offset: 0x38 */ __IO uint32_t ICR; /*!< LTDC Interrupt Clear Register, Address offset: 0x3C */ __IO uint32_t LIPCR; /*!< LTDC Line Interrupt Position Configuration Register, Address offset: 0x40 */ __IO uint32_t CPSR; /*!< LTDC Current Position Status Register, Address offset: 0x44 */ __IO uint32_t CDSR; /*!< LTDC Current Display Status Register, Address offset: 0x48 */ } LTDC_TypeDef; /** * @brief LCD-TFT Display layer x Controller */ typedef struct { __IO uint32_t CR; /*!< LTDC Layerx Control Register Address offset: 0x84 */ __IO uint32_t WHPCR; /*!< LTDC Layerx Window Horizontal Position Configuration Register Address offset: 0x88 */ __IO uint32_t WVPCR; /*!< LTDC Layerx Window Vertical Position Configuration Register Address offset: 0x8C */ __IO uint32_t CKCR; /*!< LTDC Layerx Color Keying Configuration Register Address offset: 0x90 */ __IO uint32_t PFCR; /*!< LTDC Layerx Pixel Format Configuration Register Address offset: 0x94 */ __IO uint32_t CACR; /*!< LTDC Layerx Constant Alpha Configuration Register Address offset: 0x98 */ __IO uint32_t DCCR; /*!< LTDC Layerx Default Color Configuration Register Address offset: 0x9C */ __IO uint32_t BFCR; /*!< LTDC Layerx Blending Factors Configuration Register Address offset: 0xA0 */ uint32_t RESERVED0[2]; /*!< Reserved */ __IO uint32_t CFBAR; /*!< LTDC Layerx Color Frame Buffer Address Register Address offset: 0xAC */ __IO uint32_t CFBLR; /*!< LTDC Layerx Color Frame Buffer Length Register Address offset: 0xB0 */ __IO uint32_t CFBLNR; /*!< LTDC Layerx ColorFrame Buffer Line Number Register Address offset: 0xB4 */ uint32_t RESERVED1[3]; /*!< Reserved */ __IO uint32_t CLUTWR; /*!< LTDC Layerx CLUT Write Register Address offset: 0x144*/ } LTDC_Layer_TypeDef; /** * @brief Power Control */ typedef struct { __IO uint32_t CR; /*!< PWR power control register, Address offset: 0x00 */ __IO uint32_t CSR; /*!< PWR power control/status register, Address offset: 0x04 */ } PWR_TypeDef; /** * @brief Reset and Clock Control */ typedef struct { __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */ __IO uint32_t PLLCFGR; /*!< RCC PLL configuration register, Address offset: 0x04 */ __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x08 */ __IO uint32_t CIR; /*!< RCC clock interrupt register, Address offset: 0x0C */ __IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x10 */ __IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x14 */ __IO uint32_t AHB3RSTR; /*!< RCC AHB3 peripheral reset register, Address offset: 0x18 */ uint32_t RESERVED0; /*!< Reserved, 0x1C */ __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x20 */ __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x24 */ uint32_t RESERVED1[2]; /*!< Reserved, 0x28-0x2C */ __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clock register, Address offset: 0x30 */ __IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clock register, Address offset: 0x34 */ __IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clock register, Address offset: 0x38 */ uint32_t RESERVED2; /*!< Reserved, 0x3C */ __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral clock enable register, Address offset: 0x40 */ __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock enable register, Address offset: 0x44 */ uint32_t RESERVED3[2]; /*!< Reserved, 0x48-0x4C */ __IO uint32_t AHB1LPENR; /*!< RCC AHB1 peripheral clock enable in low power mode register, Address offset: 0x50 */ __IO uint32_t AHB2LPENR; /*!< RCC AHB2 peripheral clock enable in low power mode register, Address offset: 0x54 */ __IO uint32_t AHB3LPENR; /*!< RCC AHB3 peripheral clock enable in low power mode register, Address offset: 0x58 */ uint32_t RESERVED4; /*!< Reserved, 0x5C */ __IO uint32_t APB1LPENR; /*!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x60 */ __IO uint32_t APB2LPENR; /*!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x64 */ uint32_t RESERVED5[2]; /*!< Reserved, 0x68-0x6C */ __IO uint32_t BDCR; /*!< RCC Backup domain control register, Address offset: 0x70 */ __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x74 */ uint32_t RESERVED6[2]; /*!< Reserved, 0x78-0x7C */ __IO uint32_t SSCGR; /*!< RCC spread spectrum clock generation register, Address offset: 0x80 */ __IO uint32_t PLLI2SCFGR; /*!< RCC PLLI2S configuration register, Address offset: 0x84 */ __IO uint32_t PLLSAICFGR; /*!< RCC PLLSAI configuration register, Address offset: 0x88 */ __IO uint32_t DCKCFGR; /*!< RCC Dedicated Clocks configuration register, Address offset: 0x8C */ } RCC_TypeDef; /** * @brief Real-Time Clock */ typedef struct { __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */ __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */ __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */ __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */ __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */ __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */ __IO uint32_t CALIBR; /*!< RTC calibration register, Address offset: 0x18 */ __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */ __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */ __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */ __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */ __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */ __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */ __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */ __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */ __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */ __IO uint32_t TAFCR; /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */ __IO uint32_t ALRMASSR;/*!< RTC alarm A sub second register, Address offset: 0x44 */ __IO uint32_t ALRMBSSR;/*!< RTC alarm B sub second register, Address offset: 0x48 */ uint32_t RESERVED7; /*!< Reserved, 0x4C */ __IO uint32_t BKP0R; /*!< RTC backup register 1, Address offset: 0x50 */ __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */ __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */ __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */ __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */ __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */ __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */ __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */ __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */ __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */ __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */ __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */ __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */ __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */ __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */ __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */ __IO uint32_t BKP16R; /*!< RTC backup register 16, Address offset: 0x90 */ __IO uint32_t BKP17R; /*!< RTC backup register 17, Address offset: 0x94 */ __IO uint32_t BKP18R; /*!< RTC backup register 18, Address offset: 0x98 */ __IO uint32_t BKP19R; /*!< RTC backup register 19, Address offset: 0x9C */ } RTC_TypeDef; /** * @brief Serial Audio Interface */ typedef struct { __IO uint32_t GCR; /*!< SAI global configuration register, Address offset: 0x00 */ } SAI_TypeDef; typedef struct { __IO uint32_t CR1; /*!< SAI block x configuration register 1, Address offset: 0x04 */ __IO uint32_t CR2; /*!< SAI block x configuration register 2, Address offset: 0x08 */ __IO uint32_t FRCR; /*!< SAI block x frame configuration register, Address offset: 0x0C */ __IO uint32_t SLOTR; /*!< SAI block x slot register, Address offset: 0x10 */ __IO uint32_t IMR; /*!< SAI block x interrupt mask register, Address offset: 0x14 */ __IO uint32_t SR; /*!< SAI block x status register, Address offset: 0x18 */ __IO uint32_t CLRFR; /*!< SAI block x clear flag register, Address offset: 0x1C */ __IO uint32_t DR; /*!< SAI block x data register, Address offset: 0x20 */ } SAI_Block_TypeDef; /** * @brief SD host Interface */ typedef struct { __IO uint32_t POWER; /*!< SDIO power control register, Address offset: 0x00 */ __IO uint32_t CLKCR; /*!< SDI clock control register, Address offset: 0x04 */ __IO uint32_t ARG; /*!< SDIO argument register, Address offset: 0x08 */ __IO uint32_t CMD; /*!< SDIO command register, Address offset: 0x0C */ __IO const uint32_t RESPCMD; /*!< SDIO command response register, Address offset: 0x10 */ __IO const uint32_t RESP1; /*!< SDIO response 1 register, Address offset: 0x14 */ __IO const uint32_t RESP2; /*!< SDIO response 2 register, Address offset: 0x18 */ __IO const uint32_t RESP3; /*!< SDIO response 3 register, Address offset: 0x1C */ __IO const uint32_t RESP4; /*!< SDIO response 4 register, Address offset: 0x20 */ __IO uint32_t DTIMER; /*!< SDIO data timer register, Address offset: 0x24 */ __IO uint32_t DLEN; /*!< SDIO data length register, Address offset: 0x28 */ __IO uint32_t DCTRL; /*!< SDIO data control register, Address offset: 0x2C */ __IO const uint32_t DCOUNT; /*!< SDIO data counter register, Address offset: 0x30 */ __IO const uint32_t STA; /*!< SDIO status register, Address offset: 0x34 */ __IO uint32_t ICR; /*!< SDIO interrupt clear register, Address offset: 0x38 */ __IO uint32_t MASK; /*!< SDIO mask register, Address offset: 0x3C */ uint32_t RESERVED0[2]; /*!< Reserved, 0x40-0x44 */ __IO const uint32_t FIFOCNT; /*!< SDIO FIFO counter register, Address offset: 0x48 */ uint32_t RESERVED1[13]; /*!< Reserved, 0x4C-0x7C */ __IO uint32_t FIFO; /*!< SDIO data FIFO register, Address offset: 0x80 */ } SDIO_TypeDef; /** * @brief Serial Peripheral Interface */ typedef struct { __IO uint32_t CR1; /*!< SPI control register 1 (not used in I2S mode), Address offset: 0x00 */ __IO uint32_t CR2; /*!< SPI control register 2, Address offset: 0x04 */ __IO uint32_t SR; /*!< SPI status register, Address offset: 0x08 */ __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */ __IO uint32_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */ __IO uint32_t RXCRCR; /*!< SPI RX CRC register (not used in I2S mode), Address offset: 0x14 */ __IO uint32_t TXCRCR; /*!< SPI TX CRC register (not used in I2S mode), Address offset: 0x18 */ __IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */ __IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */ } SPI_TypeDef; /** * @brief QUAD Serial Peripheral Interface */ typedef struct { __IO uint32_t CR; /*!< QUADSPI Control register, Address offset: 0x00 */ __IO uint32_t DCR; /*!< QUADSPI Device Configuration register, Address offset: 0x04 */ __IO uint32_t SR; /*!< QUADSPI Status register, Address offset: 0x08 */ __IO uint32_t FCR; /*!< QUADSPI Flag Clear register, Address offset: 0x0C */ __IO uint32_t DLR; /*!< QUADSPI Data Length register, Address offset: 0x10 */ __IO uint32_t CCR; /*!< QUADSPI Communication Configuration register, Address offset: 0x14 */ __IO uint32_t AR; /*!< QUADSPI Address register, Address offset: 0x18 */ __IO uint32_t ABR; /*!< QUADSPI Alternate Bytes register, Address offset: 0x1C */ __IO uint32_t DR; /*!< QUADSPI Data register, Address offset: 0x20 */ __IO uint32_t PSMKR; /*!< QUADSPI Polling Status Mask register, Address offset: 0x24 */ __IO uint32_t PSMAR; /*!< QUADSPI Polling Status Match register, Address offset: 0x28 */ __IO uint32_t PIR; /*!< QUADSPI Polling Interval register, Address offset: 0x2C */ __IO uint32_t LPTR; /*!< QUADSPI Low Power Timeout register, Address offset: 0x30 */ } QUADSPI_TypeDef; /** * @brief TIM */ typedef struct { __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */ __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */ __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */ __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */ __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */ __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */ __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */ __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */ __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */ __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */ __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */ __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */ __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */ __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */ __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */ __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */ __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */ __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */ __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */ __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */ } TIM_TypeDef; /** * @brief Universal Synchronous Asynchronous Receiver Transmitter */ typedef struct { __IO uint32_t SR; /*!< USART Status register, Address offset: 0x00 */ __IO uint32_t DR; /*!< USART Data register, Address offset: 0x04 */ __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x08 */ __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x0C */ __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x10 */ __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x14 */ __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x18 */ } USART_TypeDef; /** * @brief Window WATCHDOG */ typedef struct { __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */ __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */ __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */ } WWDG_TypeDef; /** * @brief RNG */ typedef struct { __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */ __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */ __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */ } RNG_TypeDef; /** * @brief USB_OTG_Core_Registers */ typedef struct { __IO uint32_t GOTGCTL; /*!< USB_OTG Control and Status Register 000h */ __IO uint32_t GOTGINT; /*!< USB_OTG Interrupt Register 004h */ __IO uint32_t GAHBCFG; /*!< Core AHB Configuration Register 008h */ __IO uint32_t GUSBCFG; /*!< Core USB Configuration Register 00Ch */ __IO uint32_t GRSTCTL; /*!< Core Reset Register 010h */ __IO uint32_t GINTSTS; /*!< Core Interrupt Register 014h */ __IO uint32_t GINTMSK; /*!< Core Interrupt Mask Register 018h */ __IO uint32_t GRXSTSR; /*!< Receive Sts Q Read Register 01Ch */ __IO uint32_t GRXSTSP; /*!< Receive Sts Q Read & POP Register 020h */ __IO uint32_t GRXFSIZ; /*!< Receive FIFO Size Register 024h */ __IO uint32_t DIEPTXF0_HNPTXFSIZ; /*!< EP0 / Non Periodic Tx FIFO Size Register 028h */ __IO uint32_t HNPTXSTS; /*!< Non Periodic Tx FIFO/Queue Sts reg 02Ch */ uint32_t Reserved30[2]; /*!< Reserved 030h */ __IO uint32_t GCCFG; /*!< General Purpose IO Register 038h */ __IO uint32_t CID; /*!< User ID Register 03Ch */ uint32_t Reserved5[3]; /*!< Reserved 040h-048h */ __IO uint32_t GHWCFG3; /*!< User HW config3 04Ch */ uint32_t Reserved6; /*!< Reserved 050h */ __IO uint32_t GLPMCFG; /*!< LPM Register 054h */ uint32_t Reserved; /*!< Reserved 058h */ __IO uint32_t GDFIFOCFG; /*!< DFIFO Software Config Register 05Ch */ uint32_t Reserved43[40]; /*!< Reserved 058h-0FFh */ __IO uint32_t HPTXFSIZ; /*!< Host Periodic Tx FIFO Size Reg 100h */ __IO uint32_t DIEPTXF[0x0F]; /*!< dev Periodic Transmit FIFO */ } USB_OTG_GlobalTypeDef; /** * @brief USB_OTG_device_Registers */ typedef struct { __IO uint32_t DCFG; /*!< dev Configuration Register 800h */ __IO uint32_t DCTL; /*!< dev Control Register 804h */ __IO uint32_t DSTS; /*!< dev Status Register (RO) 808h */ uint32_t Reserved0C; /*!< Reserved 80Ch */ __IO uint32_t DIEPMSK; /*!< dev IN Endpoint Mask 810h */ __IO uint32_t DOEPMSK; /*!< dev OUT Endpoint Mask 814h */ __IO uint32_t DAINT; /*!< dev All Endpoints Itr Reg 818h */ __IO uint32_t DAINTMSK; /*!< dev All Endpoints Itr Mask 81Ch */ uint32_t Reserved20; /*!< Reserved 820h */ uint32_t Reserved9; /*!< Reserved 824h */ __IO uint32_t DVBUSDIS; /*!< dev VBUS discharge Register 828h */ __IO uint32_t DVBUSPULSE; /*!< dev VBUS Pulse Register 82Ch */ __IO uint32_t DTHRCTL; /*!< dev threshold 830h */ __IO uint32_t DIEPEMPMSK; /*!< dev empty msk 834h */ __IO uint32_t DEACHINT; /*!< dedicated EP interrupt 838h */ __IO uint32_t DEACHMSK; /*!< dedicated EP msk 83Ch */ uint32_t Reserved40; /*!< dedicated EP mask 840h */ __IO uint32_t DINEP1MSK; /*!< dedicated EP mask 844h */ uint32_t Reserved44[15]; /*!< Reserved 844-87Ch */ __IO uint32_t DOUTEP1MSK; /*!< dedicated EP msk 884h */ } USB_OTG_DeviceTypeDef; /** * @brief USB_OTG_IN_Endpoint-Specific_Register */ typedef struct { __IO uint32_t DIEPCTL; /*!< dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h */ uint32_t Reserved04; /*!< Reserved 900h + (ep_num * 20h) + 04h */ __IO uint32_t DIEPINT; /*!< dev IN Endpoint Itr Reg 900h + (ep_num * 20h) + 08h */ uint32_t Reserved0C; /*!< Reserved 900h + (ep_num * 20h) + 0Ch */ __IO uint32_t DIEPTSIZ; /*!< IN Endpoint Txfer Size 900h + (ep_num * 20h) + 10h */ __IO uint32_t DIEPDMA; /*!< IN Endpoint DMA Address Reg 900h + (ep_num * 20h) + 14h */ __IO uint32_t DTXFSTS; /*!< IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h */ uint32_t Reserved18; /*!< Reserved 900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch */ } USB_OTG_INEndpointTypeDef; /** * @brief USB_OTG_OUT_Endpoint-Specific_Registers */ typedef struct { __IO uint32_t DOEPCTL; /*!< dev OUT Endpoint Control Reg B00h + (ep_num * 20h) + 00h */ uint32_t Reserved04; /*!< Reserved B00h + (ep_num * 20h) + 04h */ __IO uint32_t DOEPINT; /*!< dev OUT Endpoint Itr Reg B00h + (ep_num * 20h) + 08h */ uint32_t Reserved0C; /*!< Reserved B00h + (ep_num * 20h) + 0Ch */ __IO uint32_t DOEPTSIZ; /*!< dev OUT Endpoint Txfer Size B00h + (ep_num * 20h) + 10h */ __IO uint32_t DOEPDMA; /*!< dev OUT Endpoint DMA Address B00h + (ep_num * 20h) + 14h */ uint32_t Reserved18[2]; /*!< Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch */ } USB_OTG_OUTEndpointTypeDef; /** * @brief USB_OTG_Host_Mode_Register_Structures */ typedef struct { __IO uint32_t HCFG; /*!< Host Configuration Register 400h */ __IO uint32_t HFIR; /*!< Host Frame Interval Register 404h */ __IO uint32_t HFNUM; /*!< Host Frame Nbr/Frame Remaining 408h */ uint32_t Reserved40C; /*!< Reserved 40Ch */ __IO uint32_t HPTXSTS; /*!< Host Periodic Tx FIFO/ Queue Status 410h */ __IO uint32_t HAINT; /*!< Host All Channels Interrupt Register 414h */ __IO uint32_t HAINTMSK; /*!< Host All Channels Interrupt Mask 418h */ } USB_OTG_HostTypeDef; /** * @brief USB_OTG_Host_Channel_Specific_Registers */ typedef struct { __IO uint32_t HCCHAR; /*!< Host Channel Characteristics Register 500h */ __IO uint32_t HCSPLT; /*!< Host Channel Split Control Register 504h */ __IO uint32_t HCINT; /*!< Host Channel Interrupt Register 508h */ __IO uint32_t HCINTMSK; /*!< Host Channel Interrupt Mask Register 50Ch */ __IO uint32_t HCTSIZ; /*!< Host Channel Transfer Size Register 510h */ __IO uint32_t HCDMA; /*!< Host Channel DMA Address Register 514h */ uint32_t Reserved[2]; /*!< Reserved */ } USB_OTG_HostChannelTypeDef; /** * @} */ /** @addtogroup Peripheral_memory_map * @{ */ #define FLASH_BASE 0x08000000U /*!< FLASH(up to 1 MB) base address in the alias region */ #define CCMDATARAM_BASE 0x10000000U /*!< CCM(core coupled memory) data RAM(64 KB) base address in the alias region */ #define SRAM1_BASE 0x20000000U /*!< SRAM1(160 KB) base address in the alias region */ #define SRAM2_BASE 0x20028000U /*!< SRAM2(32 KB) base address in the alias region */ #define SRAM3_BASE 0x20030000U /*!< SRAM3(128 KB) base address in the alias region */ #define PERIPH_BASE 0x40000000U /*!< Peripheral base address in the alias region */ #define BKPSRAM_BASE 0x40024000U /*!< Backup SRAM(4 KB) base address in the alias region */ #define FMC_R_BASE 0xA0000000U /*!< FMC registers base address */ #define QSPI_R_BASE 0xA0001000U /*!< QuadSPI registers base address */ #define SRAM1_BB_BASE 0x22000000U /*!< SRAM1(112 KB) base address in the bit-band region */ #define SRAM2_BB_BASE 0x22500000U /*!< SRAM2(16 KB) base address in the bit-band region */ #define SRAM3_BB_BASE 0x22600000U /*!< SRAM3(64 KB) base address in the bit-band region */ #define PERIPH_BB_BASE 0x42000000U /*!< Peripheral base address in the bit-band region */ #define BKPSRAM_BB_BASE 0x42480000U /*!< Backup SRAM(4 KB) base address in the bit-band region */ #define FLASH_END 0x081FFFFFU /*!< FLASH end address */ #define FLASH_OTP_BASE 0x1FFF7800U /*!< Base address of : (up to 528 Bytes) embedded FLASH OTP Area */ #define FLASH_OTP_END 0x1FFF7A0FU /*!< End address of : (up to 528 Bytes) embedded FLASH OTP Area */ #define CCMDATARAM_END 0x1000FFFFU /*!< CCM data RAM end address */ /* Legacy defines */ #define SRAM_BASE SRAM1_BASE #define SRAM_BB_BASE SRAM1_BB_BASE /*!< Peripheral memory map */ #define APB1PERIPH_BASE PERIPH_BASE #define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000U) #define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000U) #define AHB2PERIPH_BASE (PERIPH_BASE + 0x10000000U) /*!< APB1 peripherals */ #define TIM2_BASE (APB1PERIPH_BASE + 0x0000U) #define TIM3_BASE (APB1PERIPH_BASE + 0x0400U) #define TIM4_BASE (APB1PERIPH_BASE + 0x0800U) #define TIM5_BASE (APB1PERIPH_BASE + 0x0C00U) #define TIM6_BASE (APB1PERIPH_BASE + 0x1000U) #define TIM7_BASE (APB1PERIPH_BASE + 0x1400U) #define TIM12_BASE (APB1PERIPH_BASE + 0x1800U) #define TIM13_BASE (APB1PERIPH_BASE + 0x1C00U) #define TIM14_BASE (APB1PERIPH_BASE + 0x2000U) #define RTC_BASE (APB1PERIPH_BASE + 0x2800U) #define WWDG_BASE (APB1PERIPH_BASE + 0x2C00U) #define IWDG_BASE (APB1PERIPH_BASE + 0x3000U) #define I2S2ext_BASE (APB1PERIPH_BASE + 0x3400U) #define SPI2_BASE (APB1PERIPH_BASE + 0x3800U) #define SPI3_BASE (APB1PERIPH_BASE + 0x3C00U) #define I2S3ext_BASE (APB1PERIPH_BASE + 0x4000U) #define USART2_BASE (APB1PERIPH_BASE + 0x4400U) #define USART3_BASE (APB1PERIPH_BASE + 0x4800U) #define UART4_BASE (APB1PERIPH_BASE + 0x4C00U) #define UART5_BASE (APB1PERIPH_BASE + 0x5000U) #define I2C1_BASE (APB1PERIPH_BASE + 0x5400U) #define I2C2_BASE (APB1PERIPH_BASE + 0x5800U) #define I2C3_BASE (APB1PERIPH_BASE + 0x5C00U) #define CAN1_BASE (APB1PERIPH_BASE + 0x6400U) #define CAN2_BASE (APB1PERIPH_BASE + 0x6800U) #define PWR_BASE (APB1PERIPH_BASE + 0x7000U) #define DAC_BASE (APB1PERIPH_BASE + 0x7400U) #define UART7_BASE (APB1PERIPH_BASE + 0x7800U) #define UART8_BASE (APB1PERIPH_BASE + 0x7C00U) /*!< APB2 peripherals */ #define TIM1_BASE (APB2PERIPH_BASE + 0x0000U) #define TIM8_BASE (APB2PERIPH_BASE + 0x0400U) #define USART1_BASE (APB2PERIPH_BASE + 0x1000U) #define USART6_BASE (APB2PERIPH_BASE + 0x1400U) #define ADC1_BASE (APB2PERIPH_BASE + 0x2000U) #define ADC2_BASE (APB2PERIPH_BASE + 0x2100U) #define ADC3_BASE (APB2PERIPH_BASE + 0x2200U) #define ADC123_COMMON_BASE (APB2PERIPH_BASE + 0x2300U) /* Legacy define */ #define ADC_BASE ADC123_COMMON_BASE #define SDIO_BASE (APB2PERIPH_BASE + 0x2C00U) #define SPI1_BASE (APB2PERIPH_BASE + 0x3000U) #define SPI4_BASE (APB2PERIPH_BASE + 0x3400U) #define SYSCFG_BASE (APB2PERIPH_BASE + 0x3800U) #define EXTI_BASE (APB2PERIPH_BASE + 0x3C00U) #define TIM9_BASE (APB2PERIPH_BASE + 0x4000U) #define TIM10_BASE (APB2PERIPH_BASE + 0x4400U) #define TIM11_BASE (APB2PERIPH_BASE + 0x4800U) #define SPI5_BASE (APB2PERIPH_BASE + 0x5000U) #define SPI6_BASE (APB2PERIPH_BASE + 0x5400U) #define SAI1_BASE (APB2PERIPH_BASE + 0x5800U) #define SAI1_Block_A_BASE (SAI1_BASE + 0x004U) #define SAI1_Block_B_BASE (SAI1_BASE + 0x024U) #define LTDC_BASE (APB2PERIPH_BASE + 0x6800U) #define LTDC_Layer1_BASE (LTDC_BASE + 0x84U) #define LTDC_Layer2_BASE (LTDC_BASE + 0x104U) #define DSI_BASE (APB2PERIPH_BASE + 0x6C00U) /*!< AHB1 peripherals */ #define GPIOA_BASE (AHB1PERIPH_BASE + 0x0000U) #define GPIOB_BASE (AHB1PERIPH_BASE + 0x0400U) #define GPIOC_BASE (AHB1PERIPH_BASE + 0x0800U) #define GPIOD_BASE (AHB1PERIPH_BASE + 0x0C00U) #define GPIOE_BASE (AHB1PERIPH_BASE + 0x1000U) #define GPIOF_BASE (AHB1PERIPH_BASE + 0x1400U) #define GPIOG_BASE (AHB1PERIPH_BASE + 0x1800U) #define GPIOH_BASE (AHB1PERIPH_BASE + 0x1C00U) #define GPIOI_BASE (AHB1PERIPH_BASE + 0x2000U) #define GPIOJ_BASE (AHB1PERIPH_BASE + 0x2400U) #define GPIOK_BASE (AHB1PERIPH_BASE + 0x2800U) #define CRC_BASE (AHB1PERIPH_BASE + 0x3000U) #define RCC_BASE (AHB1PERIPH_BASE + 0x3800U) #define FLASH_R_BASE (AHB1PERIPH_BASE + 0x3C00U) #define DMA1_BASE (AHB1PERIPH_BASE + 0x6000U) #define DMA1_Stream0_BASE (DMA1_BASE + 0x010U) #define DMA1_Stream1_BASE (DMA1_BASE + 0x028U) #define DMA1_Stream2_BASE (DMA1_BASE + 0x040U) #define DMA1_Stream3_BASE (DMA1_BASE + 0x058U) #define DMA1_Stream4_BASE (DMA1_BASE + 0x070U) #define DMA1_Stream5_BASE (DMA1_BASE + 0x088U) #define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0U) #define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8U) #define DMA2_BASE (AHB1PERIPH_BASE + 0x6400U) #define DMA2_Stream0_BASE (DMA2_BASE + 0x010U) #define DMA2_Stream1_BASE (DMA2_BASE + 0x028U) #define DMA2_Stream2_BASE (DMA2_BASE + 0x040U) #define DMA2_Stream3_BASE (DMA2_BASE + 0x058U) #define DMA2_Stream4_BASE (DMA2_BASE + 0x070U) #define DMA2_Stream5_BASE (DMA2_BASE + 0x088U) #define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0U) #define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8U) #define ETH_BASE (AHB1PERIPH_BASE + 0x8000U) #define ETH_MAC_BASE (ETH_BASE) #define ETH_MMC_BASE (ETH_BASE + 0x0100U) #define ETH_PTP_BASE (ETH_BASE + 0x0700U) #define ETH_DMA_BASE (ETH_BASE + 0x1000U) #define DMA2D_BASE (AHB1PERIPH_BASE + 0xB000U) /*!< AHB2 peripherals */ #define DCMI_BASE (AHB2PERIPH_BASE + 0x50000U) #define RNG_BASE (AHB2PERIPH_BASE + 0x60800U) /*!< FMC Bankx registers base address */ #define FMC_Bank1_R_BASE (FMC_R_BASE + 0x0000U) #define FMC_Bank1E_R_BASE (FMC_R_BASE + 0x0104U) #define FMC_Bank3_R_BASE (FMC_R_BASE + 0x0080U) #define FMC_Bank5_6_R_BASE (FMC_R_BASE + 0x0140U) /*!< Debug MCU registers base address */ #define DBGMCU_BASE 0xE0042000U /*!< USB registers base address */ #define USB_OTG_HS_PERIPH_BASE 0x40040000U #define USB_OTG_FS_PERIPH_BASE 0x50000000U #define USB_OTG_GLOBAL_BASE 0x000U #define USB_OTG_DEVICE_BASE 0x800U #define USB_OTG_IN_ENDPOINT_BASE 0x900U #define USB_OTG_OUT_ENDPOINT_BASE 0xB00U #define USB_OTG_EP_REG_SIZE 0x20U #define USB_OTG_HOST_BASE 0x400U #define USB_OTG_HOST_PORT_BASE 0x440U #define USB_OTG_HOST_CHANNEL_BASE 0x500U #define USB_OTG_HOST_CHANNEL_SIZE 0x20U #define USB_OTG_PCGCCTL_BASE 0xE00U #define USB_OTG_FIFO_BASE 0x1000U #define USB_OTG_FIFO_SIZE 0x1000U #define UID_BASE 0x1FFF7A10U /*!< Unique device ID register base address */ #define FLASHSIZE_BASE 0x1FFF7A22U /*!< FLASH Size register base address */ #define PACKAGE_BASE 0x1FFF7BF0U /*!< Package size register base address */ /** * @} */ /** @addtogroup Peripheral_declaration * @{ */ #define TIM2 ((TIM_TypeDef *) TIM2_BASE) #define TIM3 ((TIM_TypeDef *) TIM3_BASE) #define TIM4 ((TIM_TypeDef *) TIM4_BASE) #define TIM5 ((TIM_TypeDef *) TIM5_BASE) #define TIM6 ((TIM_TypeDef *) TIM6_BASE) #define TIM7 ((TIM_TypeDef *) TIM7_BASE) #define TIM12 ((TIM_TypeDef *) TIM12_BASE) #define TIM13 ((TIM_TypeDef *) TIM13_BASE) #define TIM14 ((TIM_TypeDef *) TIM14_BASE) #define RTC ((RTC_TypeDef *) RTC_BASE) #define WWDG ((WWDG_TypeDef *) WWDG_BASE) #define IWDG ((IWDG_TypeDef *) IWDG_BASE) #define I2S2ext ((SPI_TypeDef *) I2S2ext_BASE) #define SPI2 ((SPI_TypeDef *) SPI2_BASE) #define SPI3 ((SPI_TypeDef *) SPI3_BASE) #define I2S3ext ((SPI_TypeDef *) I2S3ext_BASE) #define USART2 ((USART_TypeDef *) USART2_BASE) #define USART3 ((USART_TypeDef *) USART3_BASE) #define UART4 ((USART_TypeDef *) UART4_BASE) #define UART5 ((USART_TypeDef *) UART5_BASE) #define I2C1 ((I2C_TypeDef *) I2C1_BASE) #define I2C2 ((I2C_TypeDef *) I2C2_BASE) #define I2C3 ((I2C_TypeDef *) I2C3_BASE) #define CAN1 ((CAN_TypeDef *) CAN1_BASE) #define CAN2 ((CAN_TypeDef *) CAN2_BASE) #define PWR ((PWR_TypeDef *) PWR_BASE) #define DAC1 ((DAC_TypeDef *) DAC_BASE) #define DAC ((DAC_TypeDef *) DAC_BASE) /* Kept for legacy purpose */ #define UART7 ((USART_TypeDef *) UART7_BASE) #define UART8 ((USART_TypeDef *) UART8_BASE) #define TIM1 ((TIM_TypeDef *) TIM1_BASE) #define TIM8 ((TIM_TypeDef *) TIM8_BASE) #define USART1 ((USART_TypeDef *) USART1_BASE) #define USART6 ((USART_TypeDef *) USART6_BASE) #define ADC1 ((ADC_TypeDef *) ADC1_BASE) #define ADC2 ((ADC_TypeDef *) ADC2_BASE) #define ADC3 ((ADC_TypeDef *) ADC3_BASE) #define ADC123_COMMON ((ADC_Common_TypeDef *) ADC123_COMMON_BASE) /* Legacy define */ #define ADC ADC123_COMMON #define SDIO ((SDIO_TypeDef *) SDIO_BASE) #define SPI1 ((SPI_TypeDef *) SPI1_BASE) #define SPI4 ((SPI_TypeDef *) SPI4_BASE) #define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE) #define EXTI ((EXTI_TypeDef *) EXTI_BASE) #define TIM9 ((TIM_TypeDef *) TIM9_BASE) #define TIM10 ((TIM_TypeDef *) TIM10_BASE) #define TIM11 ((TIM_TypeDef *) TIM11_BASE) #define SPI5 ((SPI_TypeDef *) SPI5_BASE) #define SPI6 ((SPI_TypeDef *) SPI6_BASE) #define SAI1 ((SAI_TypeDef *) SAI1_BASE) #define SAI1_Block_A ((SAI_Block_TypeDef *)SAI1_Block_A_BASE) #define SAI1_Block_B ((SAI_Block_TypeDef *)SAI1_Block_B_BASE) #define LTDC ((LTDC_TypeDef *)LTDC_BASE) #define LTDC_Layer1 ((LTDC_Layer_TypeDef *)LTDC_Layer1_BASE) #define LTDC_Layer2 ((LTDC_Layer_TypeDef *)LTDC_Layer2_BASE) #define DSI ((DSI_TypeDef *)DSI_BASE) #define GPIOA ((GPIO_TypeDef *) GPIOA_BASE) #define GPIOB ((GPIO_TypeDef *) GPIOB_BASE) #define GPIOC ((GPIO_TypeDef *) GPIOC_BASE) #define GPIOD ((GPIO_TypeDef *) GPIOD_BASE) #define GPIOE ((GPIO_TypeDef *) GPIOE_BASE) #define GPIOF ((GPIO_TypeDef *) GPIOF_BASE) #define GPIOG ((GPIO_TypeDef *) GPIOG_BASE) #define GPIOH ((GPIO_TypeDef *) GPIOH_BASE) #define GPIOI ((GPIO_TypeDef *) GPIOI_BASE) #define GPIOJ ((GPIO_TypeDef *) GPIOJ_BASE) #define GPIOK ((GPIO_TypeDef *) GPIOK_BASE) #define CRC ((CRC_TypeDef *) CRC_BASE) #define RCC ((RCC_TypeDef *) RCC_BASE) #define FLASH ((FLASH_TypeDef *) FLASH_R_BASE) #define DMA1 ((DMA_TypeDef *) DMA1_BASE) #define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE) #define DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE) #define DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE) #define DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE) #define DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE) #define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE) #define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE) #define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE) #define DMA2 ((DMA_TypeDef *) DMA2_BASE) #define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE) #define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE) #define DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE) #define DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE) #define DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE) #define DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE) #define DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE) #define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE) #define ETH ((ETH_TypeDef *) ETH_BASE) #define DMA2D ((DMA2D_TypeDef *)DMA2D_BASE) #define DCMI ((DCMI_TypeDef *) DCMI_BASE) #define RNG ((RNG_TypeDef *) RNG_BASE) #define FMC_Bank1 ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE) #define FMC_Bank1E ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE) #define FMC_Bank3 ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE) #define FMC_Bank5_6 ((FMC_Bank5_6_TypeDef *) FMC_Bank5_6_R_BASE) #define QUADSPI ((QUADSPI_TypeDef *) QSPI_R_BASE) #define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE) #define USB_OTG_FS ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_PERIPH_BASE) #define USB_OTG_HS ((USB_OTG_GlobalTypeDef *) USB_OTG_HS_PERIPH_BASE) /** * @} */ /** @addtogroup Exported_constants * @{ */ /** @addtogroup Peripheral_Registers_Bits_Definition * @{ */ /******************************************************************************/ /* Peripheral Registers_Bits_Definition */ /******************************************************************************/ /******************************************************************************/ /* */ /* Analog to Digital Converter */ /* */ /******************************************************************************/ /* * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie) */ #define ADC_MULTIMODE_SUPPORT /*!<ADC Multimode feature available on specific devices */ /******************** Bit definition for ADC_SR register ********************/ #define ADC_SR_AWD_Pos (0U) #define ADC_SR_AWD_Msk (0x1U << ADC_SR_AWD_Pos) /*!< 0x00000001 */ #define ADC_SR_AWD ADC_SR_AWD_Msk /*!<Analog watchdog flag */ #define ADC_SR_EOC_Pos (1U) #define ADC_SR_EOC_Msk (0x1U << ADC_SR_EOC_Pos) /*!< 0x00000002 */ #define ADC_SR_EOC ADC_SR_EOC_Msk /*!<End of conversion */ #define ADC_SR_JEOC_Pos (2U) #define ADC_SR_JEOC_Msk (0x1U << ADC_SR_JEOC_Pos) /*!< 0x00000004 */ #define ADC_SR_JEOC ADC_SR_JEOC_Msk /*!<Injected channel end of conversion */ #define ADC_SR_JSTRT_Pos (3U) #define ADC_SR_JSTRT_Msk (0x1U << ADC_SR_JSTRT_Pos) /*!< 0x00000008 */ #define ADC_SR_JSTRT ADC_SR_JSTRT_Msk /*!<Injected channel Start flag */ #define ADC_SR_STRT_Pos (4U) #define ADC_SR_STRT_Msk (0x1U << ADC_SR_STRT_Pos) /*!< 0x00000010 */ #define ADC_SR_STRT ADC_SR_STRT_Msk /*!<Regular channel Start flag */ #define ADC_SR_OVR_Pos (5U) #define ADC_SR_OVR_Msk (0x1U << ADC_SR_OVR_Pos) /*!< 0x00000020 */ #define ADC_SR_OVR ADC_SR_OVR_Msk /*!<Overrun flag */ /******************* Bit definition for ADC_CR1 register ********************/ #define ADC_CR1_AWDCH_Pos (0U) #define ADC_CR1_AWDCH_Msk (0x1FU << ADC_CR1_AWDCH_Pos) /*!< 0x0000001F */ #define ADC_CR1_AWDCH ADC_CR1_AWDCH_Msk /*!<AWDCH[4:0] bits (Analog watchdog channel select bits) */ #define ADC_CR1_AWDCH_0 (0x01U << ADC_CR1_AWDCH_Pos) /*!< 0x00000001 */ #define ADC_CR1_AWDCH_1 (0x02U << ADC_CR1_AWDCH_Pos) /*!< 0x00000002 */ #define ADC_CR1_AWDCH_2 (0x04U << ADC_CR1_AWDCH_Pos) /*!< 0x00000004 */ #define ADC_CR1_AWDCH_3 (0x08U << ADC_CR1_AWDCH_Pos) /*!< 0x00000008 */ #define ADC_CR1_AWDCH_4 (0x10U << ADC_CR1_AWDCH_Pos) /*!< 0x00000010 */ #define ADC_CR1_EOCIE_Pos (5U) #define ADC_CR1_EOCIE_Msk (0x1U << ADC_CR1_EOCIE_Pos) /*!< 0x00000020 */ #define ADC_CR1_EOCIE ADC_CR1_EOCIE_Msk /*!<Interrupt enable for EOC */ #define ADC_CR1_AWDIE_Pos (6U) #define ADC_CR1_AWDIE_Msk (0x1U << ADC_CR1_AWDIE_Pos) /*!< 0x00000040 */ #define ADC_CR1_AWDIE ADC_CR1_AWDIE_Msk /*!<AAnalog Watchdog interrupt enable */ #define ADC_CR1_JEOCIE_Pos (7U) #define ADC_CR1_JEOCIE_Msk (0x1U << ADC_CR1_JEOCIE_Pos) /*!< 0x00000080 */ #define ADC_CR1_JEOCIE ADC_CR1_JEOCIE_Msk /*!<Interrupt enable for injected channels */ #define ADC_CR1_SCAN_Pos (8U) #define ADC_CR1_SCAN_Msk (0x1U << ADC_CR1_SCAN_Pos) /*!< 0x00000100 */ #define ADC_CR1_SCAN ADC_CR1_SCAN_Msk /*!<Scan mode */ #define ADC_CR1_AWDSGL_Pos (9U) #define ADC_CR1_AWDSGL_Msk (0x1U << ADC_CR1_AWDSGL_Pos) /*!< 0x00000200 */ #define ADC_CR1_AWDSGL ADC_CR1_AWDSGL_Msk /*!<Enable the watchdog on a single channel in scan mode */ #define ADC_CR1_JAUTO_Pos (10U) #define ADC_CR1_JAUTO_Msk (0x1U << ADC_CR1_JAUTO_Pos) /*!< 0x00000400 */ #define ADC_CR1_JAUTO ADC_CR1_JAUTO_Msk /*!<Automatic injected group conversion */ #define ADC_CR1_DISCEN_Pos (11U) #define ADC_CR1_DISCEN_Msk (0x1U << ADC_CR1_DISCEN_Pos) /*!< 0x00000800 */ #define ADC_CR1_DISCEN ADC_CR1_DISCEN_Msk /*!<Discontinuous mode on regular channels */ #define ADC_CR1_JDISCEN_Pos (12U) #define ADC_CR1_JDISCEN_Msk (0x1U << ADC_CR1_JDISCEN_Pos) /*!< 0x00001000 */ #define ADC_CR1_JDISCEN ADC_CR1_JDISCEN_Msk /*!<Discontinuous mode on injected channels */ #define ADC_CR1_DISCNUM_Pos (13U) #define ADC_CR1_DISCNUM_Msk (0x7U << ADC_CR1_DISCNUM_Pos) /*!< 0x0000E000 */ #define ADC_CR1_DISCNUM ADC_CR1_DISCNUM_Msk /*!<DISCNUM[2:0] bits (Discontinuous mode channel count) */ #define ADC_CR1_DISCNUM_0 (0x1U << ADC_CR1_DISCNUM_Pos) /*!< 0x00002000 */ #define ADC_CR1_DISCNUM_1 (0x2U << ADC_CR1_DISCNUM_Pos) /*!< 0x00004000 */ #define ADC_CR1_DISCNUM_2 (0x4U << ADC_CR1_DISCNUM_Pos) /*!< 0x00008000 */ #define ADC_CR1_JAWDEN_Pos (22U) #define ADC_CR1_JAWDEN_Msk (0x1U << ADC_CR1_JAWDEN_Pos) /*!< 0x00400000 */ #define ADC_CR1_JAWDEN ADC_CR1_JAWDEN_Msk /*!<Analog watchdog enable on injected channels */ #define ADC_CR1_AWDEN_Pos (23U) #define ADC_CR1_AWDEN_Msk (0x1U << ADC_CR1_AWDEN_Pos) /*!< 0x00800000 */ #define ADC_CR1_AWDEN ADC_CR1_AWDEN_Msk /*!<Analog watchdog enable on regular channels */ #define ADC_CR1_RES_Pos (24U) #define ADC_CR1_RES_Msk (0x3U << ADC_CR1_RES_Pos) /*!< 0x03000000 */ #define ADC_CR1_RES ADC_CR1_RES_Msk /*!<RES[2:0] bits (Resolution) */ #define ADC_CR1_RES_0 (0x1U << ADC_CR1_RES_Pos) /*!< 0x01000000 */ #define ADC_CR1_RES_1 (0x2U << ADC_CR1_RES_Pos) /*!< 0x02000000 */ #define ADC_CR1_OVRIE_Pos (26U) #define ADC_CR1_OVRIE_Msk (0x1U << ADC_CR1_OVRIE_Pos) /*!< 0x04000000 */ #define ADC_CR1_OVRIE ADC_CR1_OVRIE_Msk /*!<overrun interrupt enable */ /******************* Bit definition for ADC_CR2 register ********************/ #define ADC_CR2_ADON_Pos (0U) #define ADC_CR2_ADON_Msk (0x1U << ADC_CR2_ADON_Pos) /*!< 0x00000001 */ #define ADC_CR2_ADON ADC_CR2_ADON_Msk /*!<A/D Converter ON / OFF */ #define ADC_CR2_CONT_Pos (1U) #define ADC_CR2_CONT_Msk (0x1U << ADC_CR2_CONT_Pos) /*!< 0x00000002 */ #define ADC_CR2_CONT ADC_CR2_CONT_Msk /*!<Continuous Conversion */ #define ADC_CR2_DMA_Pos (8U) #define ADC_CR2_DMA_Msk (0x1U << ADC_CR2_DMA_Pos) /*!< 0x00000100 */ #define ADC_CR2_DMA ADC_CR2_DMA_Msk /*!<Direct Memory access mode */ #define ADC_CR2_DDS_Pos (9U) #define ADC_CR2_DDS_Msk (0x1U << ADC_CR2_DDS_Pos) /*!< 0x00000200 */ #define ADC_CR2_DDS ADC_CR2_DDS_Msk /*!<DMA disable selection (Single ADC) */ #define ADC_CR2_EOCS_Pos (10U) #define ADC_CR2_EOCS_Msk (0x1U << ADC_CR2_EOCS_Pos) /*!< 0x00000400 */ #define ADC_CR2_EOCS ADC_CR2_EOCS_Msk /*!<End of conversion selection */ #define ADC_CR2_ALIGN_Pos (11U) #define ADC_CR2_ALIGN_Msk (0x1U << ADC_CR2_ALIGN_Pos) /*!< 0x00000800 */ #define ADC_CR2_ALIGN ADC_CR2_ALIGN_Msk /*!<Data Alignment */ #define ADC_CR2_JEXTSEL_Pos (16U) #define ADC_CR2_JEXTSEL_Msk (0xFU << ADC_CR2_JEXTSEL_Pos) /*!< 0x000F0000 */ #define ADC_CR2_JEXTSEL ADC_CR2_JEXTSEL_Msk /*!<JEXTSEL[3:0] bits (External event select for injected group) */ #define ADC_CR2_JEXTSEL_0 (0x1U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00010000 */ #define ADC_CR2_JEXTSEL_1 (0x2U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00020000 */ #define ADC_CR2_JEXTSEL_2 (0x4U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00040000 */ #define ADC_CR2_JEXTSEL_3 (0x8U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00080000 */ #define ADC_CR2_JEXTEN_Pos (20U) #define ADC_CR2_JEXTEN_Msk (0x3U << ADC_CR2_JEXTEN_Pos) /*!< 0x00300000 */ #define ADC_CR2_JEXTEN ADC_CR2_JEXTEN_Msk /*!<JEXTEN[1:0] bits (External Trigger Conversion mode for injected channelsp) */ #define ADC_CR2_JEXTEN_0 (0x1U << ADC_CR2_JEXTEN_Pos) /*!< 0x00100000 */ #define ADC_CR2_JEXTEN_1 (0x2U << ADC_CR2_JEXTEN_Pos) /*!< 0x00200000 */ #define ADC_CR2_JSWSTART_Pos (22U) #define ADC_CR2_JSWSTART_Msk (0x1U << ADC_CR2_JSWSTART_Pos) /*!< 0x00400000 */ #define ADC_CR2_JSWSTART ADC_CR2_JSWSTART_Msk /*!<Start Conversion of injected channels */ #define ADC_CR2_EXTSEL_Pos (24U) #define ADC_CR2_EXTSEL_Msk (0xFU << ADC_CR2_EXTSEL_Pos) /*!< 0x0F000000 */ #define ADC_CR2_EXTSEL ADC_CR2_EXTSEL_Msk /*!<EXTSEL[3:0] bits (External Event Select for regular group) */ #define ADC_CR2_EXTSEL_0 (0x1U << ADC_CR2_EXTSEL_Pos) /*!< 0x01000000 */ #define ADC_CR2_EXTSEL_1 (0x2U << ADC_CR2_EXTSEL_Pos) /*!< 0x02000000 */ #define ADC_CR2_EXTSEL_2 (0x4U << ADC_CR2_EXTSEL_Pos) /*!< 0x04000000 */ #define ADC_CR2_EXTSEL_3 (0x8U << ADC_CR2_EXTSEL_Pos) /*!< 0x08000000 */ #define ADC_CR2_EXTEN_Pos (28U) #define ADC_CR2_EXTEN_Msk (0x3U << ADC_CR2_EXTEN_Pos) /*!< 0x30000000 */ #define ADC_CR2_EXTEN ADC_CR2_EXTEN_Msk /*!<EXTEN[1:0] bits (External Trigger Conversion mode for regular channelsp) */ #define ADC_CR2_EXTEN_0 (0x1U << ADC_CR2_EXTEN_Pos) /*!< 0x10000000 */ #define ADC_CR2_EXTEN_1 (0x2U << ADC_CR2_EXTEN_Pos) /*!< 0x20000000 */ #define ADC_CR2_SWSTART_Pos (30U) #define ADC_CR2_SWSTART_Msk (0x1U << ADC_CR2_SWSTART_Pos) /*!< 0x40000000 */ #define ADC_CR2_SWSTART ADC_CR2_SWSTART_Msk /*!<Start Conversion of regular channels */ /****************** Bit definition for ADC_SMPR1 register *******************/ #define ADC_SMPR1_SMP10_Pos (0U) #define ADC_SMPR1_SMP10_Msk (0x7U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000007 */ #define ADC_SMPR1_SMP10 ADC_SMPR1_SMP10_Msk /*!<SMP10[2:0] bits (Channel 10 Sample time selection) */ #define ADC_SMPR1_SMP10_0 (0x1U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000001 */ #define ADC_SMPR1_SMP10_1 (0x2U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000002 */ #define ADC_SMPR1_SMP10_2 (0x4U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000004 */ #define ADC_SMPR1_SMP11_Pos (3U) #define ADC_SMPR1_SMP11_Msk (0x7U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000038 */ #define ADC_SMPR1_SMP11 ADC_SMPR1_SMP11_Msk /*!<SMP11[2:0] bits (Channel 11 Sample time selection) */ #define ADC_SMPR1_SMP11_0 (0x1U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000008 */ #define ADC_SMPR1_SMP11_1 (0x2U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000010 */ #define ADC_SMPR1_SMP11_2 (0x4U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000020 */ #define ADC_SMPR1_SMP12_Pos (6U) #define ADC_SMPR1_SMP12_Msk (0x7U << ADC_SMPR1_SMP12_Pos) /*!< 0x000001C0 */ #define ADC_SMPR1_SMP12 ADC_SMPR1_SMP12_Msk /*!<SMP12[2:0] bits (Channel 12 Sample time selection) */ #define ADC_SMPR1_SMP12_0 (0x1U << ADC_SMPR1_SMP12_Pos) /*!< 0x00000040 */ #define ADC_SMPR1_SMP12_1 (0x2U << ADC_SMPR1_SMP12_Pos) /*!< 0x00000080 */ #define ADC_SMPR1_SMP12_2 (0x4U << ADC_SMPR1_SMP12_Pos) /*!< 0x00000100 */ #define ADC_SMPR1_SMP13_Pos (9U) #define ADC_SMPR1_SMP13_Msk (0x7U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000E00 */ #define ADC_SMPR1_SMP13 ADC_SMPR1_SMP13_Msk /*!<SMP13[2:0] bits (Channel 13 Sample time selection) */ #define ADC_SMPR1_SMP13_0 (0x1U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000200 */ #define ADC_SMPR1_SMP13_1 (0x2U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000400 */ #define ADC_SMPR1_SMP13_2 (0x4U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000800 */ #define ADC_SMPR1_SMP14_Pos (12U) #define ADC_SMPR1_SMP14_Msk (0x7U << ADC_SMPR1_SMP14_Pos) /*!< 0x00007000 */ #define ADC_SMPR1_SMP14 ADC_SMPR1_SMP14_Msk /*!<SMP14[2:0] bits (Channel 14 Sample time selection) */ #define ADC_SMPR1_SMP14_0 (0x1U << ADC_SMPR1_SMP14_Pos) /*!< 0x00001000 */ #define ADC_SMPR1_SMP14_1 (0x2U << ADC_SMPR1_SMP14_Pos) /*!< 0x00002000 */ #define ADC_SMPR1_SMP14_2 (0x4U << ADC_SMPR1_SMP14_Pos) /*!< 0x00004000 */ #define ADC_SMPR1_SMP15_Pos (15U) #define ADC_SMPR1_SMP15_Msk (0x7U << ADC_SMPR1_SMP15_Pos) /*!< 0x00038000 */ #define ADC_SMPR1_SMP15 ADC_SMPR1_SMP15_Msk /*!<SMP15[2:0] bits (Channel 15 Sample time selection) */ #define ADC_SMPR1_SMP15_0 (0x1U << ADC_SMPR1_SMP15_Pos) /*!< 0x00008000 */ #define ADC_SMPR1_SMP15_1 (0x2U << ADC_SMPR1_SMP15_Pos) /*!< 0x00010000 */ #define ADC_SMPR1_SMP15_2 (0x4U << ADC_SMPR1_SMP15_Pos) /*!< 0x00020000 */ #define ADC_SMPR1_SMP16_Pos (18U) #define ADC_SMPR1_SMP16_Msk (0x7U << ADC_SMPR1_SMP16_Pos) /*!< 0x001C0000 */ #define ADC_SMPR1_SMP16 ADC_SMPR1_SMP16_Msk /*!<SMP16[2:0] bits (Channel 16 Sample time selection) */ #define ADC_SMPR1_SMP16_0 (0x1U << ADC_SMPR1_SMP16_Pos) /*!< 0x00040000 */ #define ADC_SMPR1_SMP16_1 (0x2U << ADC_SMPR1_SMP16_Pos) /*!< 0x00080000 */ #define ADC_SMPR1_SMP16_2 (0x4U << ADC_SMPR1_SMP16_Pos) /*!< 0x00100000 */ #define ADC_SMPR1_SMP17_Pos (21U) #define ADC_SMPR1_SMP17_Msk (0x7U << ADC_SMPR1_SMP17_Pos) /*!< 0x00E00000 */ #define ADC_SMPR1_SMP17 ADC_SMPR1_SMP17_Msk /*!<SMP17[2:0] bits (Channel 17 Sample time selection) */ #define ADC_SMPR1_SMP17_0 (0x1U << ADC_SMPR1_SMP17_Pos) /*!< 0x00200000 */ #define ADC_SMPR1_SMP17_1 (0x2U << ADC_SMPR1_SMP17_Pos) /*!< 0x00400000 */ #define ADC_SMPR1_SMP17_2 (0x4U << ADC_SMPR1_SMP17_Pos) /*!< 0x00800000 */ #define ADC_SMPR1_SMP18_Pos (24U) #define ADC_SMPR1_SMP18_Msk (0x7U << ADC_SMPR1_SMP18_Pos) /*!< 0x07000000 */ #define ADC_SMPR1_SMP18 ADC_SMPR1_SMP18_Msk /*!<SMP18[2:0] bits (Channel 18 Sample time selection) */ #define ADC_SMPR1_SMP18_0 (0x1U << ADC_SMPR1_SMP18_Pos) /*!< 0x01000000 */ #define ADC_SMPR1_SMP18_1 (0x2U << ADC_SMPR1_SMP18_Pos) /*!< 0x02000000 */ #define ADC_SMPR1_SMP18_2 (0x4U << ADC_SMPR1_SMP18_Pos) /*!< 0x04000000 */ /****************** Bit definition for ADC_SMPR2 register *******************/ #define ADC_SMPR2_SMP0_Pos (0U) #define ADC_SMPR2_SMP0_Msk (0x7U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000007 */ #define ADC_SMPR2_SMP0 ADC_SMPR2_SMP0_Msk /*!<SMP0[2:0] bits (Channel 0 Sample time selection) */ #define ADC_SMPR2_SMP0_0 (0x1U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000001 */ #define ADC_SMPR2_SMP0_1 (0x2U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000002 */ #define ADC_SMPR2_SMP0_2 (0x4U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000004 */ #define ADC_SMPR2_SMP1_Pos (3U) #define ADC_SMPR2_SMP1_Msk (0x7U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000038 */ #define ADC_SMPR2_SMP1 ADC_SMPR2_SMP1_Msk /*!<SMP1[2:0] bits (Channel 1 Sample time selection) */ #define ADC_SMPR2_SMP1_0 (0x1U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000008 */ #define ADC_SMPR2_SMP1_1 (0x2U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000010 */ #define ADC_SMPR2_SMP1_2 (0x4U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000020 */ #define ADC_SMPR2_SMP2_Pos (6U) #define ADC_SMPR2_SMP2_Msk (0x7U << ADC_SMPR2_SMP2_Pos) /*!< 0x000001C0 */ #define ADC_SMPR2_SMP2 ADC_SMPR2_SMP2_Msk /*!<SMP2[2:0] bits (Channel 2 Sample time selection) */ #define ADC_SMPR2_SMP2_0 (0x1U << ADC_SMPR2_SMP2_Pos) /*!< 0x00000040 */ #define ADC_SMPR2_SMP2_1 (0x2U << ADC_SMPR2_SMP2_Pos) /*!< 0x00000080 */ #define ADC_SMPR2_SMP2_2 (0x4U << ADC_SMPR2_SMP2_Pos) /*!< 0x00000100 */ #define ADC_SMPR2_SMP3_Pos (9U) #define ADC_SMPR2_SMP3_Msk (0x7U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000E00 */ #define ADC_SMPR2_SMP3 ADC_SMPR2_SMP3_Msk /*!<SMP3[2:0] bits (Channel 3 Sample time selection) */ #define ADC_SMPR2_SMP3_0 (0x1U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000200 */ #define ADC_SMPR2_SMP3_1 (0x2U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000400 */ #define ADC_SMPR2_SMP3_2 (0x4U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000800 */ #define ADC_SMPR2_SMP4_Pos (12U) #define ADC_SMPR2_SMP4_Msk (0x7U << ADC_SMPR2_SMP4_Pos) /*!< 0x00007000 */ #define ADC_SMPR2_SMP4 ADC_SMPR2_SMP4_Msk /*!<SMP4[2:0] bits (Channel 4 Sample time selection) */ #define ADC_SMPR2_SMP4_0 (0x1U << ADC_SMPR2_SMP4_Pos) /*!< 0x00001000 */ #define ADC_SMPR2_SMP4_1 (0x2U << ADC_SMPR2_SMP4_Pos) /*!< 0x00002000 */ #define ADC_SMPR2_SMP4_2 (0x4U << ADC_SMPR2_SMP4_Pos) /*!< 0x00004000 */ #define ADC_SMPR2_SMP5_Pos (15U) #define ADC_SMPR2_SMP5_Msk (0x7U << ADC_SMPR2_SMP5_Pos) /*!< 0x00038000 */ #define ADC_SMPR2_SMP5 ADC_SMPR2_SMP5_Msk /*!<SMP5[2:0] bits (Channel 5 Sample time selection) */ #define ADC_SMPR2_SMP5_0 (0x1U << ADC_SMPR2_SMP5_Pos) /*!< 0x00008000 */ #define ADC_SMPR2_SMP5_1 (0x2U << ADC_SMPR2_SMP5_Pos) /*!< 0x00010000 */ #define ADC_SMPR2_SMP5_2 (0x4U << ADC_SMPR2_SMP5_Pos) /*!< 0x00020000 */ #define ADC_SMPR2_SMP6_Pos (18U) #define ADC_SMPR2_SMP6_Msk (0x7U << ADC_SMPR2_SMP6_Pos) /*!< 0x001C0000 */ #define ADC_SMPR2_SMP6 ADC_SMPR2_SMP6_Msk /*!<SMP6[2:0] bits (Channel 6 Sample time selection) */ #define ADC_SMPR2_SMP6_0 (0x1U << ADC_SMPR2_SMP6_Pos) /*!< 0x00040000 */ #define ADC_SMPR2_SMP6_1 (0x2U << ADC_SMPR2_SMP6_Pos) /*!< 0x00080000 */ #define ADC_SMPR2_SMP6_2 (0x4U << ADC_SMPR2_SMP6_Pos) /*!< 0x00100000 */ #define ADC_SMPR2_SMP7_Pos (21U) #define ADC_SMPR2_SMP7_Msk (0x7U << ADC_SMPR2_SMP7_Pos) /*!< 0x00E00000 */ #define ADC_SMPR2_SMP7 ADC_SMPR2_SMP7_Msk /*!<SMP7[2:0] bits (Channel 7 Sample time selection) */ #define ADC_SMPR2_SMP7_0 (0x1U << ADC_SMPR2_SMP7_Pos) /*!< 0x00200000 */ #define ADC_SMPR2_SMP7_1 (0x2U << ADC_SMPR2_SMP7_Pos) /*!< 0x00400000 */ #define ADC_SMPR2_SMP7_2 (0x4U << ADC_SMPR2_SMP7_Pos) /*!< 0x00800000 */ #define ADC_SMPR2_SMP8_Pos (24U) #define ADC_SMPR2_SMP8_Msk (0x7U << ADC_SMPR2_SMP8_Pos) /*!< 0x07000000 */ #define ADC_SMPR2_SMP8 ADC_SMPR2_SMP8_Msk /*!<SMP8[2:0] bits (Channel 8 Sample time selection) */ #define ADC_SMPR2_SMP8_0 (0x1U << ADC_SMPR2_SMP8_Pos) /*!< 0x01000000 */ #define ADC_SMPR2_SMP8_1 (0x2U << ADC_SMPR2_SMP8_Pos) /*!< 0x02000000 */ #define ADC_SMPR2_SMP8_2 (0x4U << ADC_SMPR2_SMP8_Pos) /*!< 0x04000000 */ #define ADC_SMPR2_SMP9_Pos (27U) #define ADC_SMPR2_SMP9_Msk (0x7U << ADC_SMPR2_SMP9_Pos) /*!< 0x38000000 */ #define ADC_SMPR2_SMP9 ADC_SMPR2_SMP9_Msk /*!<SMP9[2:0] bits (Channel 9 Sample time selection) */ #define ADC_SMPR2_SMP9_0 (0x1U << ADC_SMPR2_SMP9_Pos) /*!< 0x08000000 */ #define ADC_SMPR2_SMP9_1 (0x2U << ADC_SMPR2_SMP9_Pos) /*!< 0x10000000 */ #define ADC_SMPR2_SMP9_2 (0x4U << ADC_SMPR2_SMP9_Pos) /*!< 0x20000000 */ /****************** Bit definition for ADC_JOFR1 register *******************/ #define ADC_JOFR1_JOFFSET1_Pos (0U) #define ADC_JOFR1_JOFFSET1_Msk (0xFFFU << ADC_JOFR1_JOFFSET1_Pos) /*!< 0x00000FFF */ #define ADC_JOFR1_JOFFSET1 ADC_JOFR1_JOFFSET1_Msk /*!<Data offset for injected channel 1 */ /****************** Bit definition for ADC_JOFR2 register *******************/ #define ADC_JOFR2_JOFFSET2_Pos (0U) #define ADC_JOFR2_JOFFSET2_Msk (0xFFFU << ADC_JOFR2_JOFFSET2_Pos) /*!< 0x00000FFF */ #define ADC_JOFR2_JOFFSET2 ADC_JOFR2_JOFFSET2_Msk /*!<Data offset for injected channel 2 */ /****************** Bit definition for ADC_JOFR3 register *******************/ #define ADC_JOFR3_JOFFSET3_Pos (0U) #define ADC_JOFR3_JOFFSET3_Msk (0xFFFU << ADC_JOFR3_JOFFSET3_Pos) /*!< 0x00000FFF */ #define ADC_JOFR3_JOFFSET3 ADC_JOFR3_JOFFSET3_Msk /*!<Data offset for injected channel 3 */ /****************** Bit definition for ADC_JOFR4 register *******************/ #define ADC_JOFR4_JOFFSET4_Pos (0U) #define ADC_JOFR4_JOFFSET4_Msk (0xFFFU << ADC_JOFR4_JOFFSET4_Pos) /*!< 0x00000FFF */ #define ADC_JOFR4_JOFFSET4 ADC_JOFR4_JOFFSET4_Msk /*!<Data offset for injected channel 4 */ /******************* Bit definition for ADC_HTR register ********************/ #define ADC_HTR_HT_Pos (0U) #define ADC_HTR_HT_Msk (0xFFFU << ADC_HTR_HT_Pos) /*!< 0x00000FFF */ #define ADC_HTR_HT ADC_HTR_HT_Msk /*!<Analog watchdog high threshold */ /******************* Bit definition for ADC_LTR register ********************/ #define ADC_LTR_LT_Pos (0U) #define ADC_LTR_LT_Msk (0xFFFU << ADC_LTR_LT_Pos) /*!< 0x00000FFF */ #define ADC_LTR_LT ADC_LTR_LT_Msk /*!<Analog watchdog low threshold */ /******************* Bit definition for ADC_SQR1 register *******************/ #define ADC_SQR1_SQ13_Pos (0U) #define ADC_SQR1_SQ13_Msk (0x1FU << ADC_SQR1_SQ13_Pos) /*!< 0x0000001F */ #define ADC_SQR1_SQ13 ADC_SQR1_SQ13_Msk /*!<SQ13[4:0] bits (13th conversion in regular sequence) */ #define ADC_SQR1_SQ13_0 (0x01U << ADC_SQR1_SQ13_Pos) /*!< 0x00000001 */ #define ADC_SQR1_SQ13_1 (0x02U << ADC_SQR1_SQ13_Pos) /*!< 0x00000002 */ #define ADC_SQR1_SQ13_2 (0x04U << ADC_SQR1_SQ13_Pos) /*!< 0x00000004 */ #define ADC_SQR1_SQ13_3 (0x08U << ADC_SQR1_SQ13_Pos) /*!< 0x00000008 */ #define ADC_SQR1_SQ13_4 (0x10U << ADC_SQR1_SQ13_Pos) /*!< 0x00000010 */ #define ADC_SQR1_SQ14_Pos (5U) #define ADC_SQR1_SQ14_Msk (0x1FU << ADC_SQR1_SQ14_Pos) /*!< 0x000003E0 */ #define ADC_SQR1_SQ14 ADC_SQR1_SQ14_Msk /*!<SQ14[4:0] bits (14th conversion in regular sequence) */ #define ADC_SQR1_SQ14_0 (0x01U << ADC_SQR1_SQ14_Pos) /*!< 0x00000020 */ #define ADC_SQR1_SQ14_1 (0x02U << ADC_SQR1_SQ14_Pos) /*!< 0x00000040 */ #define ADC_SQR1_SQ14_2 (0x04U << ADC_SQR1_SQ14_Pos) /*!< 0x00000080 */ #define ADC_SQR1_SQ14_3 (0x08U << ADC_SQR1_SQ14_Pos) /*!< 0x00000100 */ #define ADC_SQR1_SQ14_4 (0x10U << ADC_SQR1_SQ14_Pos) /*!< 0x00000200 */ #define ADC_SQR1_SQ15_Pos (10U) #define ADC_SQR1_SQ15_Msk (0x1FU << ADC_SQR1_SQ15_Pos) /*!< 0x00007C00 */ #define ADC_SQR1_SQ15 ADC_SQR1_SQ15_Msk /*!<SQ15[4:0] bits (15th conversion in regular sequence) */ #define ADC_SQR1_SQ15_0 (0x01U << ADC_SQR1_SQ15_Pos) /*!< 0x00000400 */ #define ADC_SQR1_SQ15_1 (0x02U << ADC_SQR1_SQ15_Pos) /*!< 0x00000800 */ #define ADC_SQR1_SQ15_2 (0x04U << ADC_SQR1_SQ15_Pos) /*!< 0x00001000 */ #define ADC_SQR1_SQ15_3 (0x08U << ADC_SQR1_SQ15_Pos) /*!< 0x00002000 */ #define ADC_SQR1_SQ15_4 (0x10U << ADC_SQR1_SQ15_Pos) /*!< 0x00004000 */ #define ADC_SQR1_SQ16_Pos (15U) #define ADC_SQR1_SQ16_Msk (0x1FU << ADC_SQR1_SQ16_Pos) /*!< 0x000F8000 */ #define ADC_SQR1_SQ16 ADC_SQR1_SQ16_Msk /*!<SQ16[4:0] bits (16th conversion in regular sequence) */ #define ADC_SQR1_SQ16_0 (0x01U << ADC_SQR1_SQ16_Pos) /*!< 0x00008000 */ #define ADC_SQR1_SQ16_1 (0x02U << ADC_SQR1_SQ16_Pos) /*!< 0x00010000 */ #define ADC_SQR1_SQ16_2 (0x04U << ADC_SQR1_SQ16_Pos) /*!< 0x00020000 */ #define ADC_SQR1_SQ16_3 (0x08U << ADC_SQR1_SQ16_Pos) /*!< 0x00040000 */ #define ADC_SQR1_SQ16_4 (0x10U << ADC_SQR1_SQ16_Pos) /*!< 0x00080000 */ #define ADC_SQR1_L_Pos (20U) #define ADC_SQR1_L_Msk (0xFU << ADC_SQR1_L_Pos) /*!< 0x00F00000 */ #define ADC_SQR1_L ADC_SQR1_L_Msk /*!<L[3:0] bits (Regular channel sequence length) */ #define ADC_SQR1_L_0 (0x1U << ADC_SQR1_L_Pos) /*!< 0x00100000 */ #define ADC_SQR1_L_1 (0x2U << ADC_SQR1_L_Pos) /*!< 0x00200000 */ #define ADC_SQR1_L_2 (0x4U << ADC_SQR1_L_Pos) /*!< 0x00400000 */ #define ADC_SQR1_L_3 (0x8U << ADC_SQR1_L_Pos) /*!< 0x00800000 */ /******************* Bit definition for ADC_SQR2 register *******************/ #define ADC_SQR2_SQ7_Pos (0U) #define ADC_SQR2_SQ7_Msk (0x1FU << ADC_SQR2_SQ7_Pos) /*!< 0x0000001F */ #define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk /*!<SQ7[4:0] bits (7th conversion in regular sequence) */ #define ADC_SQR2_SQ7_0 (0x01U << ADC_SQR2_SQ7_Pos) /*!< 0x00000001 */ #define ADC_SQR2_SQ7_1 (0x02U << ADC_SQR2_SQ7_Pos) /*!< 0x00000002 */ #define ADC_SQR2_SQ7_2 (0x04U << ADC_SQR2_SQ7_Pos) /*!< 0x00000004 */ #define ADC_SQR2_SQ7_3 (0x08U << ADC_SQR2_SQ7_Pos) /*!< 0x00000008 */ #define ADC_SQR2_SQ7_4 (0x10U << ADC_SQR2_SQ7_Pos) /*!< 0x00000010 */ #define ADC_SQR2_SQ8_Pos (5U) #define ADC_SQR2_SQ8_Msk (0x1FU << ADC_SQR2_SQ8_Pos) /*!< 0x000003E0 */ #define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk /*!<SQ8[4:0] bits (8th conversion in regular sequence) */ #define ADC_SQR2_SQ8_0 (0x01U << ADC_SQR2_SQ8_Pos) /*!< 0x00000020 */ #define ADC_SQR2_SQ8_1 (0x02U << ADC_SQR2_SQ8_Pos) /*!< 0x00000040 */ #define ADC_SQR2_SQ8_2 (0x04U << ADC_SQR2_SQ8_Pos) /*!< 0x00000080 */ #define ADC_SQR2_SQ8_3 (0x08U << ADC_SQR2_SQ8_Pos) /*!< 0x00000100 */ #define ADC_SQR2_SQ8_4 (0x10U << ADC_SQR2_SQ8_Pos) /*!< 0x00000200 */ #define ADC_SQR2_SQ9_Pos (10U) #define ADC_SQR2_SQ9_Msk (0x1FU << ADC_SQR2_SQ9_Pos) /*!< 0x00007C00 */ #define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk /*!<SQ9[4:0] bits (9th conversion in regular sequence) */ #define ADC_SQR2_SQ9_0 (0x01U << ADC_SQR2_SQ9_Pos) /*!< 0x00000400 */ #define ADC_SQR2_SQ9_1 (0x02U << ADC_SQR2_SQ9_Pos) /*!< 0x00000800 */ #define ADC_SQR2_SQ9_2 (0x04U << ADC_SQR2_SQ9_Pos) /*!< 0x00001000 */ #define ADC_SQR2_SQ9_3 (0x08U << ADC_SQR2_SQ9_Pos) /*!< 0x00002000 */ #define ADC_SQR2_SQ9_4 (0x10U << ADC_SQR2_SQ9_Pos) /*!< 0x00004000 */ #define ADC_SQR2_SQ10_Pos (15U) #define ADC_SQR2_SQ10_Msk (0x1FU << ADC_SQR2_SQ10_Pos) /*!< 0x000F8000 */ #define ADC_SQR2_SQ10 ADC_SQR2_SQ10_Msk /*!<SQ10[4:0] bits (10th conversion in regular sequence) */ #define ADC_SQR2_SQ10_0 (0x01U << ADC_SQR2_SQ10_Pos) /*!< 0x00008000 */ #define ADC_SQR2_SQ10_1 (0x02U << ADC_SQR2_SQ10_Pos) /*!< 0x00010000 */ #define ADC_SQR2_SQ10_2 (0x04U << ADC_SQR2_SQ10_Pos) /*!< 0x00020000 */ #define ADC_SQR2_SQ10_3 (0x08U << ADC_SQR2_SQ10_Pos) /*!< 0x00040000 */ #define ADC_SQR2_SQ10_4 (0x10U << ADC_SQR2_SQ10_Pos) /*!< 0x00080000 */ #define ADC_SQR2_SQ11_Pos (20U) #define ADC_SQR2_SQ11_Msk (0x1FU << ADC_SQR2_SQ11_Pos) /*!< 0x01F00000 */ #define ADC_SQR2_SQ11 ADC_SQR2_SQ11_Msk /*!<SQ11[4:0] bits (11th conversion in regular sequence) */ #define ADC_SQR2_SQ11_0 (0x01U << ADC_SQR2_SQ11_Pos) /*!< 0x00100000 */ #define ADC_SQR2_SQ11_1 (0x02U << ADC_SQR2_SQ11_Pos) /*!< 0x00200000 */ #define ADC_SQR2_SQ11_2 (0x04U << ADC_SQR2_SQ11_Pos) /*!< 0x00400000 */ #define ADC_SQR2_SQ11_3 (0x08U << ADC_SQR2_SQ11_Pos) /*!< 0x00800000 */ #define ADC_SQR2_SQ11_4 (0x10U << ADC_SQR2_SQ11_Pos) /*!< 0x01000000 */ #define ADC_SQR2_SQ12_Pos (25U) #define ADC_SQR2_SQ12_Msk (0x1FU << ADC_SQR2_SQ12_Pos) /*!< 0x3E000000 */ #define ADC_SQR2_SQ12 ADC_SQR2_SQ12_Msk /*!<SQ12[4:0] bits (12th conversion in regular sequence) */ #define ADC_SQR2_SQ12_0 (0x01U << ADC_SQR2_SQ12_Pos) /*!< 0x02000000 */ #define ADC_SQR2_SQ12_1 (0x02U << ADC_SQR2_SQ12_Pos) /*!< 0x04000000 */ #define ADC_SQR2_SQ12_2 (0x04U << ADC_SQR2_SQ12_Pos) /*!< 0x08000000 */ #define ADC_SQR2_SQ12_3 (0x08U << ADC_SQR2_SQ12_Pos) /*!< 0x10000000 */ #define ADC_SQR2_SQ12_4 (0x10U << ADC_SQR2_SQ12_Pos) /*!< 0x20000000 */ /******************* Bit definition for ADC_SQR3 register *******************/ #define ADC_SQR3_SQ1_Pos (0U) #define ADC_SQR3_SQ1_Msk (0x1FU << ADC_SQR3_SQ1_Pos) /*!< 0x0000001F */ #define ADC_SQR3_SQ1 ADC_SQR3_SQ1_Msk /*!<SQ1[4:0] bits (1st conversion in regular sequence) */ #define ADC_SQR3_SQ1_0 (0x01U << ADC_SQR3_SQ1_Pos) /*!< 0x00000001 */ #define ADC_SQR3_SQ1_1 (0x02U << ADC_SQR3_SQ1_Pos) /*!< 0x00000002 */ #define ADC_SQR3_SQ1_2 (0x04U << ADC_SQR3_SQ1_Pos) /*!< 0x00000004 */ #define ADC_SQR3_SQ1_3 (0x08U << ADC_SQR3_SQ1_Pos) /*!< 0x00000008 */ #define ADC_SQR3_SQ1_4 (0x10U << ADC_SQR3_SQ1_Pos) /*!< 0x00000010 */ #define ADC_SQR3_SQ2_Pos (5U) #define ADC_SQR3_SQ2_Msk (0x1FU << ADC_SQR3_SQ2_Pos) /*!< 0x000003E0 */ #define ADC_SQR3_SQ2 ADC_SQR3_SQ2_Msk /*!<SQ2[4:0] bits (2nd conversion in regular sequence) */ #define ADC_SQR3_SQ2_0 (0x01U << ADC_SQR3_SQ2_Pos) /*!< 0x00000020 */ #define ADC_SQR3_SQ2_1 (0x02U << ADC_SQR3_SQ2_Pos) /*!< 0x00000040 */ #define ADC_SQR3_SQ2_2 (0x04U << ADC_SQR3_SQ2_Pos) /*!< 0x00000080 */ #define ADC_SQR3_SQ2_3 (0x08U << ADC_SQR3_SQ2_Pos) /*!< 0x00000100 */ #define ADC_SQR3_SQ2_4 (0x10U << ADC_SQR3_SQ2_Pos) /*!< 0x00000200 */ #define ADC_SQR3_SQ3_Pos (10U) #define ADC_SQR3_SQ3_Msk (0x1FU << ADC_SQR3_SQ3_Pos) /*!< 0x00007C00 */ #define ADC_SQR3_SQ3 ADC_SQR3_SQ3_Msk /*!<SQ3[4:0] bits (3rd conversion in regular sequence) */ #define ADC_SQR3_SQ3_0 (0x01U << ADC_SQR3_SQ3_Pos) /*!< 0x00000400 */ #define ADC_SQR3_SQ3_1 (0x02U << ADC_SQR3_SQ3_Pos) /*!< 0x00000800 */ #define ADC_SQR3_SQ3_2 (0x04U << ADC_SQR3_SQ3_Pos) /*!< 0x00001000 */ #define ADC_SQR3_SQ3_3 (0x08U << ADC_SQR3_SQ3_Pos) /*!< 0x00002000 */ #define ADC_SQR3_SQ3_4 (0x10U << ADC_SQR3_SQ3_Pos) /*!< 0x00004000 */ #define ADC_SQR3_SQ4_Pos (15U) #define ADC_SQR3_SQ4_Msk (0x1FU << ADC_SQR3_SQ4_Pos) /*!< 0x000F8000 */ #define ADC_SQR3_SQ4 ADC_SQR3_SQ4_Msk /*!<SQ4[4:0] bits (4th conversion in regular sequence) */ #define ADC_SQR3_SQ4_0 (0x01U << ADC_SQR3_SQ4_Pos) /*!< 0x00008000 */ #define ADC_SQR3_SQ4_1 (0x02U << ADC_SQR3_SQ4_Pos) /*!< 0x00010000 */ #define ADC_SQR3_SQ4_2 (0x04U << ADC_SQR3_SQ4_Pos) /*!< 0x00020000 */ #define ADC_SQR3_SQ4_3 (0x08U << ADC_SQR3_SQ4_Pos) /*!< 0x00040000 */ #define ADC_SQR3_SQ4_4 (0x10U << ADC_SQR3_SQ4_Pos) /*!< 0x00080000 */ #define ADC_SQR3_SQ5_Pos (20U) #define ADC_SQR3_SQ5_Msk (0x1FU << ADC_SQR3_SQ5_Pos) /*!< 0x01F00000 */ #define ADC_SQR3_SQ5 ADC_SQR3_SQ5_Msk /*!<SQ5[4:0] bits (5th conversion in regular sequence) */ #define ADC_SQR3_SQ5_0 (0x01U << ADC_SQR3_SQ5_Pos) /*!< 0x00100000 */ #define ADC_SQR3_SQ5_1 (0x02U << ADC_SQR3_SQ5_Pos) /*!< 0x00200000 */ #define ADC_SQR3_SQ5_2 (0x04U << ADC_SQR3_SQ5_Pos) /*!< 0x00400000 */ #define ADC_SQR3_SQ5_3 (0x08U << ADC_SQR3_SQ5_Pos) /*!< 0x00800000 */ #define ADC_SQR3_SQ5_4 (0x10U << ADC_SQR3_SQ5_Pos) /*!< 0x01000000 */ #define ADC_SQR3_SQ6_Pos (25U) #define ADC_SQR3_SQ6_Msk (0x1FU << ADC_SQR3_SQ6_Pos) /*!< 0x3E000000 */ #define ADC_SQR3_SQ6 ADC_SQR3_SQ6_Msk /*!<SQ6[4:0] bits (6th conversion in regular sequence) */ #define ADC_SQR3_SQ6_0 (0x01U << ADC_SQR3_SQ6_Pos) /*!< 0x02000000 */ #define ADC_SQR3_SQ6_1 (0x02U << ADC_SQR3_SQ6_Pos) /*!< 0x04000000 */ #define ADC_SQR3_SQ6_2 (0x04U << ADC_SQR3_SQ6_Pos) /*!< 0x08000000 */ #define ADC_SQR3_SQ6_3 (0x08U << ADC_SQR3_SQ6_Pos) /*!< 0x10000000 */ #define ADC_SQR3_SQ6_4 (0x10U << ADC_SQR3_SQ6_Pos) /*!< 0x20000000 */ /******************* Bit definition for ADC_JSQR register *******************/ #define ADC_JSQR_JSQ1_Pos (0U) #define ADC_JSQR_JSQ1_Msk (0x1FU << ADC_JSQR_JSQ1_Pos) /*!< 0x0000001F */ #define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk /*!<JSQ1[4:0] bits (1st conversion in injected sequence) */ #define ADC_JSQR_JSQ1_0 (0x01U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000001 */ #define ADC_JSQR_JSQ1_1 (0x02U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000002 */ #define ADC_JSQR_JSQ1_2 (0x04U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000004 */ #define ADC_JSQR_JSQ1_3 (0x08U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000008 */ #define ADC_JSQR_JSQ1_4 (0x10U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000010 */ #define ADC_JSQR_JSQ2_Pos (5U) #define ADC_JSQR_JSQ2_Msk (0x1FU << ADC_JSQR_JSQ2_Pos) /*!< 0x000003E0 */ #define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk /*!<JSQ2[4:0] bits (2nd conversion in injected sequence) */ #define ADC_JSQR_JSQ2_0 (0x01U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000020 */ #define ADC_JSQR_JSQ2_1 (0x02U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000040 */ #define ADC_JSQR_JSQ2_2 (0x04U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000080 */ #define ADC_JSQR_JSQ2_3 (0x08U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000100 */ #define ADC_JSQR_JSQ2_4 (0x10U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000200 */ #define ADC_JSQR_JSQ3_Pos (10U) #define ADC_JSQR_JSQ3_Msk (0x1FU << ADC_JSQR_JSQ3_Pos) /*!< 0x00007C00 */ #define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk /*!<JSQ3[4:0] bits (3rd conversion in injected sequence) */ #define ADC_JSQR_JSQ3_0 (0x01U << ADC_JSQR_JSQ3_Pos) /*!< 0x00000400 */ #define ADC_JSQR_JSQ3_1 (0x02U << ADC_JSQR_JSQ3_Pos) /*!< 0x00000800 */ #define ADC_JSQR_JSQ3_2 (0x04U << ADC_JSQR_JSQ3_Pos) /*!< 0x00001000 */ #define ADC_JSQR_JSQ3_3 (0x08U << ADC_JSQR_JSQ3_Pos) /*!< 0x00002000 */ #define ADC_JSQR_JSQ3_4 (0x10U << ADC_JSQR_JSQ3_Pos) /*!< 0x00004000 */ #define ADC_JSQR_JSQ4_Pos (15U) #define ADC_JSQR_JSQ4_Msk (0x1FU << ADC_JSQR_JSQ4_Pos) /*!< 0x000F8000 */ #define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk /*!<JSQ4[4:0] bits (4th conversion in injected sequence) */ #define ADC_JSQR_JSQ4_0 (0x01U << ADC_JSQR_JSQ4_Pos) /*!< 0x00008000 */ #define ADC_JSQR_JSQ4_1 (0x02U << ADC_JSQR_JSQ4_Pos) /*!< 0x00010000 */ #define ADC_JSQR_JSQ4_2 (0x04U << ADC_JSQR_JSQ4_Pos) /*!< 0x00020000 */ #define ADC_JSQR_JSQ4_3 (0x08U << ADC_JSQR_JSQ4_Pos) /*!< 0x00040000 */ #define ADC_JSQR_JSQ4_4 (0x10U << ADC_JSQR_JSQ4_Pos) /*!< 0x00080000 */ #define ADC_JSQR_JL_Pos (20U) #define ADC_JSQR_JL_Msk (0x3U << ADC_JSQR_JL_Pos) /*!< 0x00300000 */ #define ADC_JSQR_JL ADC_JSQR_JL_Msk /*!<JL[1:0] bits (Injected Sequence length) */ #define ADC_JSQR_JL_0 (0x1U << ADC_JSQR_JL_Pos) /*!< 0x00100000 */ #define ADC_JSQR_JL_1 (0x2U << ADC_JSQR_JL_Pos) /*!< 0x00200000 */ /******************* Bit definition for ADC_JDR1 register *******************/ #define ADC_JDR1_JDATA_Pos (0U) #define ADC_JDR1_JDATA_Msk (0xFFFFU << ADC_JDR1_JDATA_Pos) /*!< 0x0000FFFF */ #define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /*!<Injected data */ /******************* Bit definition for ADC_JDR2 register *******************/ #define ADC_JDR2_JDATA_Pos (0U) #define ADC_JDR2_JDATA_Msk (0xFFFFU << ADC_JDR2_JDATA_Pos) /*!< 0x0000FFFF */ #define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /*!<Injected data */ /******************* Bit definition for ADC_JDR3 register *******************/ #define ADC_JDR3_JDATA_Pos (0U) #define ADC_JDR3_JDATA_Msk (0xFFFFU << ADC_JDR3_JDATA_Pos) /*!< 0x0000FFFF */ #define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /*!<Injected data */ /******************* Bit definition for ADC_JDR4 register *******************/ #define ADC_JDR4_JDATA_Pos (0U) #define ADC_JDR4_JDATA_Msk (0xFFFFU << ADC_JDR4_JDATA_Pos) /*!< 0x0000FFFF */ #define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /*!<Injected data */ /******************** Bit definition for ADC_DR register ********************/ #define ADC_DR_DATA_Pos (0U) #define ADC_DR_DATA_Msk (0xFFFFU << ADC_DR_DATA_Pos) /*!< 0x0000FFFF */ #define ADC_DR_DATA ADC_DR_DATA_Msk /*!<Regular data */ #define ADC_DR_ADC2DATA_Pos (16U) #define ADC_DR_ADC2DATA_Msk (0xFFFFU << ADC_DR_ADC2DATA_Pos) /*!< 0xFFFF0000 */ #define ADC_DR_ADC2DATA ADC_DR_ADC2DATA_Msk /*!<ADC2 data */ /******************* Bit definition for ADC_CSR register ********************/ #define ADC_CSR_AWD1_Pos (0U) #define ADC_CSR_AWD1_Msk (0x1U << ADC_CSR_AWD1_Pos) /*!< 0x00000001 */ #define ADC_CSR_AWD1 ADC_CSR_AWD1_Msk /*!<ADC1 Analog watchdog flag */ #define ADC_CSR_EOC1_Pos (1U) #define ADC_CSR_EOC1_Msk (0x1U << ADC_CSR_EOC1_Pos) /*!< 0x00000002 */ #define ADC_CSR_EOC1 ADC_CSR_EOC1_Msk /*!<ADC1 End of conversion */ #define ADC_CSR_JEOC1_Pos (2U) #define ADC_CSR_JEOC1_Msk (0x1U << ADC_CSR_JEOC1_Pos) /*!< 0x00000004 */ #define ADC_CSR_JEOC1 ADC_CSR_JEOC1_Msk /*!<ADC1 Injected channel end of conversion */ #define ADC_CSR_JSTRT1_Pos (3U) #define ADC_CSR_JSTRT1_Msk (0x1U << ADC_CSR_JSTRT1_Pos) /*!< 0x00000008 */ #define ADC_CSR_JSTRT1 ADC_CSR_JSTRT1_Msk /*!<ADC1 Injected channel Start flag */ #define ADC_CSR_STRT1_Pos (4U) #define ADC_CSR_STRT1_Msk (0x1U << ADC_CSR_STRT1_Pos) /*!< 0x00000010 */ #define ADC_CSR_STRT1 ADC_CSR_STRT1_Msk /*!<ADC1 Regular channel Start flag */ #define ADC_CSR_OVR1_Pos (5U) #define ADC_CSR_OVR1_Msk (0x1U << ADC_CSR_OVR1_Pos) /*!< 0x00000020 */ #define ADC_CSR_OVR1 ADC_CSR_OVR1_Msk /*!<ADC1 DMA overrun flag */ #define ADC_CSR_AWD2_Pos (8U) #define ADC_CSR_AWD2_Msk (0x1U << ADC_CSR_AWD2_Pos) /*!< 0x00000100 */ #define ADC_CSR_AWD2 ADC_CSR_AWD2_Msk /*!<ADC2 Analog watchdog flag */ #define ADC_CSR_EOC2_Pos (9U) #define ADC_CSR_EOC2_Msk (0x1U << ADC_CSR_EOC2_Pos) /*!< 0x00000200 */ #define ADC_CSR_EOC2 ADC_CSR_EOC2_Msk /*!<ADC2 End of conversion */ #define ADC_CSR_JEOC2_Pos (10U) #define ADC_CSR_JEOC2_Msk (0x1U << ADC_CSR_JEOC2_Pos) /*!< 0x00000400 */ #define ADC_CSR_JEOC2 ADC_CSR_JEOC2_Msk /*!<ADC2 Injected channel end of conversion */ #define ADC_CSR_JSTRT2_Pos (11U) #define ADC_CSR_JSTRT2_Msk (0x1U << ADC_CSR_JSTRT2_Pos) /*!< 0x00000800 */ #define ADC_CSR_JSTRT2 ADC_CSR_JSTRT2_Msk /*!<ADC2 Injected channel Start flag */ #define ADC_CSR_STRT2_Pos (12U) #define ADC_CSR_STRT2_Msk (0x1U << ADC_CSR_STRT2_Pos) /*!< 0x00001000 */ #define ADC_CSR_STRT2 ADC_CSR_STRT2_Msk /*!<ADC2 Regular channel Start flag */ #define ADC_CSR_OVR2_Pos (13U) #define ADC_CSR_OVR2_Msk (0x1U << ADC_CSR_OVR2_Pos) /*!< 0x00002000 */ #define ADC_CSR_OVR2 ADC_CSR_OVR2_Msk /*!<ADC2 DMA overrun flag */ #define ADC_CSR_AWD3_Pos (16U) #define ADC_CSR_AWD3_Msk (0x1U << ADC_CSR_AWD3_Pos) /*!< 0x00010000 */ #define ADC_CSR_AWD3 ADC_CSR_AWD3_Msk /*!<ADC3 Analog watchdog flag */ #define ADC_CSR_EOC3_Pos (17U) #define ADC_CSR_EOC3_Msk (0x1U << ADC_CSR_EOC3_Pos) /*!< 0x00020000 */ #define ADC_CSR_EOC3 ADC_CSR_EOC3_Msk /*!<ADC3 End of conversion */ #define ADC_CSR_JEOC3_Pos (18U) #define ADC_CSR_JEOC3_Msk (0x1U << ADC_CSR_JEOC3_Pos) /*!< 0x00040000 */ #define ADC_CSR_JEOC3 ADC_CSR_JEOC3_Msk /*!<ADC3 Injected channel end of conversion */ #define ADC_CSR_JSTRT3_Pos (19U) #define ADC_CSR_JSTRT3_Msk (0x1U << ADC_CSR_JSTRT3_Pos) /*!< 0x00080000 */ #define ADC_CSR_JSTRT3 ADC_CSR_JSTRT3_Msk /*!<ADC3 Injected channel Start flag */ #define ADC_CSR_STRT3_Pos (20U) #define ADC_CSR_STRT3_Msk (0x1U << ADC_CSR_STRT3_Pos) /*!< 0x00100000 */ #define ADC_CSR_STRT3 ADC_CSR_STRT3_Msk /*!<ADC3 Regular channel Start flag */ #define ADC_CSR_OVR3_Pos (21U) #define ADC_CSR_OVR3_Msk (0x1U << ADC_CSR_OVR3_Pos) /*!< 0x00200000 */ #define ADC_CSR_OVR3 ADC_CSR_OVR3_Msk /*!<ADC3 DMA overrun flag */ /* Legacy defines */ #define ADC_CSR_DOVR1 ADC_CSR_OVR1 #define ADC_CSR_DOVR2 ADC_CSR_OVR2 #define ADC_CSR_DOVR3 ADC_CSR_OVR3 /******************* Bit definition for ADC_CCR register ********************/ #define ADC_CCR_MULTI_Pos (0U) #define ADC_CCR_MULTI_Msk (0x1FU << ADC_CCR_MULTI_Pos) /*!< 0x0000001F */ #define ADC_CCR_MULTI ADC_CCR_MULTI_Msk /*!<MULTI[4:0] bits (Multi-ADC mode selection) */ #define ADC_CCR_MULTI_0 (0x01U << ADC_CCR_MULTI_Pos) /*!< 0x00000001 */ #define ADC_CCR_MULTI_1 (0x02U << ADC_CCR_MULTI_Pos) /*!< 0x00000002 */ #define ADC_CCR_MULTI_2 (0x04U << ADC_CCR_MULTI_Pos) /*!< 0x00000004 */ #define ADC_CCR_MULTI_3 (0x08U << ADC_CCR_MULTI_Pos) /*!< 0x00000008 */ #define ADC_CCR_MULTI_4 (0x10U << ADC_CCR_MULTI_Pos) /*!< 0x00000010 */ #define ADC_CCR_DELAY_Pos (8U) #define ADC_CCR_DELAY_Msk (0xFU << ADC_CCR_DELAY_Pos) /*!< 0x00000F00 */ #define ADC_CCR_DELAY ADC_CCR_DELAY_Msk /*!<DELAY[3:0] bits (Delay between 2 sampling phases) */ #define ADC_CCR_DELAY_0 (0x1U << ADC_CCR_DELAY_Pos) /*!< 0x00000100 */ #define ADC_CCR_DELAY_1 (0x2U << ADC_CCR_DELAY_Pos) /*!< 0x00000200 */ #define ADC_CCR_DELAY_2 (0x4U << ADC_CCR_DELAY_Pos) /*!< 0x00000400 */ #define ADC_CCR_DELAY_3 (0x8U << ADC_CCR_DELAY_Pos) /*!< 0x00000800 */ #define ADC_CCR_DDS_Pos (13U) #define ADC_CCR_DDS_Msk (0x1U << ADC_CCR_DDS_Pos) /*!< 0x00002000 */ #define ADC_CCR_DDS ADC_CCR_DDS_Msk /*!<DMA disable selection (Multi-ADC mode) */ #define ADC_CCR_DMA_Pos (14U) #define ADC_CCR_DMA_Msk (0x3U << ADC_CCR_DMA_Pos) /*!< 0x0000C000 */ #define ADC_CCR_DMA ADC_CCR_DMA_Msk /*!<DMA[1:0] bits (Direct Memory Access mode for multimode) */ #define ADC_CCR_DMA_0 (0x1U << ADC_CCR_DMA_Pos) /*!< 0x00004000 */ #define ADC_CCR_DMA_1 (0x2U << ADC_CCR_DMA_Pos) /*!< 0x00008000 */ #define ADC_CCR_ADCPRE_Pos (16U) #define ADC_CCR_ADCPRE_Msk (0x3U << ADC_CCR_ADCPRE_Pos) /*!< 0x00030000 */ #define ADC_CCR_ADCPRE ADC_CCR_ADCPRE_Msk /*!<ADCPRE[1:0] bits (ADC prescaler) */ #define ADC_CCR_ADCPRE_0 (0x1U << ADC_CCR_ADCPRE_Pos) /*!< 0x00010000 */ #define ADC_CCR_ADCPRE_1 (0x2U << ADC_CCR_ADCPRE_Pos) /*!< 0x00020000 */ #define ADC_CCR_VBATE_Pos (22U) #define ADC_CCR_VBATE_Msk (0x1U << ADC_CCR_VBATE_Pos) /*!< 0x00400000 */ #define ADC_CCR_VBATE ADC_CCR_VBATE_Msk /*!<VBAT Enable */ #define ADC_CCR_TSVREFE_Pos (23U) #define ADC_CCR_TSVREFE_Msk (0x1U << ADC_CCR_TSVREFE_Pos) /*!< 0x00800000 */ #define ADC_CCR_TSVREFE ADC_CCR_TSVREFE_Msk /*!<Temperature Sensor and VREFINT Enable */ /******************* Bit definition for ADC_CDR register ********************/ #define ADC_CDR_DATA1_Pos (0U) #define ADC_CDR_DATA1_Msk (0xFFFFU << ADC_CDR_DATA1_Pos) /*!< 0x0000FFFF */ #define ADC_CDR_DATA1 ADC_CDR_DATA1_Msk /*!<1st data of a pair of regular conversions */ #define ADC_CDR_DATA2_Pos (16U) #define ADC_CDR_DATA2_Msk (0xFFFFU << ADC_CDR_DATA2_Pos) /*!< 0xFFFF0000 */ #define ADC_CDR_DATA2 ADC_CDR_DATA2_Msk /*!<2nd data of a pair of regular conversions */ /* Legacy defines */ #define ADC_CDR_RDATA_MST ADC_CDR_DATA1 #define ADC_CDR_RDATA_SLV ADC_CDR_DATA2 /******************************************************************************/ /* */ /* Controller Area Network */ /* */ /******************************************************************************/ /*!<CAN control and status registers */ /******************* Bit definition for CAN_MCR register ********************/ #define CAN_MCR_INRQ_Pos (0U) #define CAN_MCR_INRQ_Msk (0x1U << CAN_MCR_INRQ_Pos) /*!< 0x00000001 */ #define CAN_MCR_INRQ CAN_MCR_INRQ_Msk /*!<Initialization Request */ #define CAN_MCR_SLEEP_Pos (1U) #define CAN_MCR_SLEEP_Msk (0x1U << CAN_MCR_SLEEP_Pos) /*!< 0x00000002 */ #define CAN_MCR_SLEEP CAN_MCR_SLEEP_Msk /*!<Sleep Mode Request */ #define CAN_MCR_TXFP_Pos (2U) #define CAN_MCR_TXFP_Msk (0x1U << CAN_MCR_TXFP_Pos) /*!< 0x00000004 */ #define CAN_MCR_TXFP CAN_MCR_TXFP_Msk /*!<Transmit FIFO Priority */ #define CAN_MCR_RFLM_Pos (3U) #define CAN_MCR_RFLM_Msk (0x1U << CAN_MCR_RFLM_Pos) /*!< 0x00000008 */ #define CAN_MCR_RFLM CAN_MCR_RFLM_Msk /*!<Receive FIFO Locked Mode */ #define CAN_MCR_NART_Pos (4U) #define CAN_MCR_NART_Msk (0x1U << CAN_MCR_NART_Pos) /*!< 0x00000010 */ #define CAN_MCR_NART CAN_MCR_NART_Msk /*!<No Automatic Retransmission */ #define CAN_MCR_AWUM_Pos (5U) #define CAN_MCR_AWUM_Msk (0x1U << CAN_MCR_AWUM_Pos) /*!< 0x00000020 */ #define CAN_MCR_AWUM CAN_MCR_AWUM_Msk /*!<Automatic Wakeup Mode */ #define CAN_MCR_ABOM_Pos (6U) #define CAN_MCR_ABOM_Msk (0x1U << CAN_MCR_ABOM_Pos) /*!< 0x00000040 */ #define CAN_MCR_ABOM CAN_MCR_ABOM_Msk /*!<Automatic Bus-Off Management */ #define CAN_MCR_TTCM_Pos (7U) #define CAN_MCR_TTCM_Msk (0x1U << CAN_MCR_TTCM_Pos) /*!< 0x00000080 */ #define CAN_MCR_TTCM CAN_MCR_TTCM_Msk /*!<Time Triggered Communication Mode */ #define CAN_MCR_RESET_Pos (15U) #define CAN_MCR_RESET_Msk (0x1U << CAN_MCR_RESET_Pos) /*!< 0x00008000 */ #define CAN_MCR_RESET CAN_MCR_RESET_Msk /*!<bxCAN software master reset */ #define CAN_MCR_DBF_Pos (16U) #define CAN_MCR_DBF_Msk (0x1U << CAN_MCR_DBF_Pos) /*!< 0x00010000 */ #define CAN_MCR_DBF CAN_MCR_DBF_Msk /*!<bxCAN Debug freeze */ /******************* Bit definition for CAN_MSR register ********************/ #define CAN_MSR_INAK_Pos (0U) #define CAN_MSR_INAK_Msk (0x1U << CAN_MSR_INAK_Pos) /*!< 0x00000001 */ #define CAN_MSR_INAK CAN_MSR_INAK_Msk /*!<Initialization Acknowledge */ #define CAN_MSR_SLAK_Pos (1U) #define CAN_MSR_SLAK_Msk (0x1U << CAN_MSR_SLAK_Pos) /*!< 0x00000002 */ #define CAN_MSR_SLAK CAN_MSR_SLAK_Msk /*!<Sleep Acknowledge */ #define CAN_MSR_ERRI_Pos (2U) #define CAN_MSR_ERRI_Msk (0x1U << CAN_MSR_ERRI_Pos) /*!< 0x00000004 */ #define CAN_MSR_ERRI CAN_MSR_ERRI_Msk /*!<Error Interrupt */ #define CAN_MSR_WKUI_Pos (3U) #define CAN_MSR_WKUI_Msk (0x1U << CAN_MSR_WKUI_Pos) /*!< 0x00000008 */ #define CAN_MSR_WKUI CAN_MSR_WKUI_Msk /*!<Wakeup Interrupt */ #define CAN_MSR_SLAKI_Pos (4U) #define CAN_MSR_SLAKI_Msk (0x1U << CAN_MSR_SLAKI_Pos) /*!< 0x00000010 */ #define CAN_MSR_SLAKI CAN_MSR_SLAKI_Msk /*!<Sleep Acknowledge Interrupt */ #define CAN_MSR_TXM_Pos (8U) #define CAN_MSR_TXM_Msk (0x1U << CAN_MSR_TXM_Pos) /*!< 0x00000100 */ #define CAN_MSR_TXM CAN_MSR_TXM_Msk /*!<Transmit Mode */ #define CAN_MSR_RXM_Pos (9U) #define CAN_MSR_RXM_Msk (0x1U << CAN_MSR_RXM_Pos) /*!< 0x00000200 */ #define CAN_MSR_RXM CAN_MSR_RXM_Msk /*!<Receive Mode */ #define CAN_MSR_SAMP_Pos (10U) #define CAN_MSR_SAMP_Msk (0x1U << CAN_MSR_SAMP_Pos) /*!< 0x00000400 */ #define CAN_MSR_SAMP CAN_MSR_SAMP_Msk /*!<Last Sample Point */ #define CAN_MSR_RX_Pos (11U) #define CAN_MSR_RX_Msk (0x1U << CAN_MSR_RX_Pos) /*!< 0x00000800 */ #define CAN_MSR_RX CAN_MSR_RX_Msk /*!<CAN Rx Signal */ /******************* Bit definition for CAN_TSR register ********************/ #define CAN_TSR_RQCP0_Pos (0U) #define CAN_TSR_RQCP0_Msk (0x1U << CAN_TSR_RQCP0_Pos) /*!< 0x00000001 */ #define CAN_TSR_RQCP0 CAN_TSR_RQCP0_Msk /*!<Request Completed Mailbox0 */ #define CAN_TSR_TXOK0_Pos (1U) #define CAN_TSR_TXOK0_Msk (0x1U << CAN_TSR_TXOK0_Pos) /*!< 0x00000002 */ #define CAN_TSR_TXOK0 CAN_TSR_TXOK0_Msk /*!<Transmission OK of Mailbox0 */ #define CAN_TSR_ALST0_Pos (2U) #define CAN_TSR_ALST0_Msk (0x1U << CAN_TSR_ALST0_Pos) /*!< 0x00000004 */ #define CAN_TSR_ALST0 CAN_TSR_ALST0_Msk /*!<Arbitration Lost for Mailbox0 */ #define CAN_TSR_TERR0_Pos (3U) #define CAN_TSR_TERR0_Msk (0x1U << CAN_TSR_TERR0_Pos) /*!< 0x00000008 */ #define CAN_TSR_TERR0 CAN_TSR_TERR0_Msk /*!<Transmission Error of Mailbox0 */ #define CAN_TSR_ABRQ0_Pos (7U) #define CAN_TSR_ABRQ0_Msk (0x1U << CAN_TSR_ABRQ0_Pos) /*!< 0x00000080 */ #define CAN_TSR_ABRQ0 CAN_TSR_ABRQ0_Msk /*!<Abort Request for Mailbox0 */ #define CAN_TSR_RQCP1_Pos (8U) #define CAN_TSR_RQCP1_Msk (0x1U << CAN_TSR_RQCP1_Pos) /*!< 0x00000100 */ #define CAN_TSR_RQCP1 CAN_TSR_RQCP1_Msk /*!<Request Completed Mailbox1 */ #define CAN_TSR_TXOK1_Pos (9U) #define CAN_TSR_TXOK1_Msk (0x1U << CAN_TSR_TXOK1_Pos) /*!< 0x00000200 */ #define CAN_TSR_TXOK1 CAN_TSR_TXOK1_Msk /*!<Transmission OK of Mailbox1 */ #define CAN_TSR_ALST1_Pos (10U) #define CAN_TSR_ALST1_Msk (0x1U << CAN_TSR_ALST1_Pos) /*!< 0x00000400 */ #define CAN_TSR_ALST1 CAN_TSR_ALST1_Msk /*!<Arbitration Lost for Mailbox1 */ #define CAN_TSR_TERR1_Pos (11U) #define CAN_TSR_TERR1_Msk (0x1U << CAN_TSR_TERR1_Pos) /*!< 0x00000800 */ #define CAN_TSR_TERR1 CAN_TSR_TERR1_Msk /*!<Transmission Error of Mailbox1 */ #define CAN_TSR_ABRQ1_Pos (15U) #define CAN_TSR_ABRQ1_Msk (0x1U << CAN_TSR_ABRQ1_Pos) /*!< 0x00008000 */ #define CAN_TSR_ABRQ1 CAN_TSR_ABRQ1_Msk /*!<Abort Request for Mailbox 1 */ #define CAN_TSR_RQCP2_Pos (16U) #define CAN_TSR_RQCP2_Msk (0x1U << CAN_TSR_RQCP2_Pos) /*!< 0x00010000 */ #define CAN_TSR_RQCP2 CAN_TSR_RQCP2_Msk /*!<Request Completed Mailbox2 */ #define CAN_TSR_TXOK2_Pos (17U) #define CAN_TSR_TXOK2_Msk (0x1U << CAN_TSR_TXOK2_Pos) /*!< 0x00020000 */ #define CAN_TSR_TXOK2 CAN_TSR_TXOK2_Msk /*!<Transmission OK of Mailbox 2 */ #define CAN_TSR_ALST2_Pos (18U) #define CAN_TSR_ALST2_Msk (0x1U << CAN_TSR_ALST2_Pos) /*!< 0x00040000 */ #define CAN_TSR_ALST2 CAN_TSR_ALST2_Msk /*!<Arbitration Lost for mailbox 2 */ #define CAN_TSR_TERR2_Pos (19U) #define CAN_TSR_TERR2_Msk (0x1U << CAN_TSR_TERR2_Pos) /*!< 0x00080000 */ #define CAN_TSR_TERR2 CAN_TSR_TERR2_Msk /*!<Transmission Error of Mailbox 2 */ #define CAN_TSR_ABRQ2_Pos (23U) #define CAN_TSR_ABRQ2_Msk (0x1U << CAN_TSR_ABRQ2_Pos) /*!< 0x00800000 */ #define CAN_TSR_ABRQ2 CAN_TSR_ABRQ2_Msk /*!<Abort Request for Mailbox 2 */ #define CAN_TSR_CODE_Pos (24U) #define CAN_TSR_CODE_Msk (0x3U << CAN_TSR_CODE_Pos) /*!< 0x03000000 */ #define CAN_TSR_CODE CAN_TSR_CODE_Msk /*!<Mailbox Code */ #define CAN_TSR_TME_Pos (26U) #define CAN_TSR_TME_Msk (0x7U << CAN_TSR_TME_Pos) /*!< 0x1C000000 */ #define CAN_TSR_TME CAN_TSR_TME_Msk /*!<TME[2:0] bits */ #define CAN_TSR_TME0_Pos (26U) #define CAN_TSR_TME0_Msk (0x1U << CAN_TSR_TME0_Pos) /*!< 0x04000000 */ #define CAN_TSR_TME0 CAN_TSR_TME0_Msk /*!<Transmit Mailbox 0 Empty */ #define CAN_TSR_TME1_Pos (27U) #define CAN_TSR_TME1_Msk (0x1U << CAN_TSR_TME1_Pos) /*!< 0x08000000 */ #define CAN_TSR_TME1 CAN_TSR_TME1_Msk /*!<Transmit Mailbox 1 Empty */ #define CAN_TSR_TME2_Pos (28U) #define CAN_TSR_TME2_Msk (0x1U << CAN_TSR_TME2_Pos) /*!< 0x10000000 */ #define CAN_TSR_TME2 CAN_TSR_TME2_Msk /*!<Transmit Mailbox 2 Empty */ #define CAN_TSR_LOW_Pos (29U) #define CAN_TSR_LOW_Msk (0x7U << CAN_TSR_LOW_Pos) /*!< 0xE0000000 */ #define CAN_TSR_LOW CAN_TSR_LOW_Msk /*!<LOW[2:0] bits */ #define CAN_TSR_LOW0_Pos (29U) #define CAN_TSR_LOW0_Msk (0x1U << CAN_TSR_LOW0_Pos) /*!< 0x20000000 */ #define CAN_TSR_LOW0 CAN_TSR_LOW0_Msk /*!<Lowest Priority Flag for Mailbox 0 */ #define CAN_TSR_LOW1_Pos (30U) #define CAN_TSR_LOW1_Msk (0x1U << CAN_TSR_LOW1_Pos) /*!< 0x40000000 */ #define CAN_TSR_LOW1 CAN_TSR_LOW1_Msk /*!<Lowest Priority Flag for Mailbox 1 */ #define CAN_TSR_LOW2_Pos (31U) #define CAN_TSR_LOW2_Msk (0x1U << CAN_TSR_LOW2_Pos) /*!< 0x80000000 */ #define CAN_TSR_LOW2 CAN_TSR_LOW2_Msk /*!<Lowest Priority Flag for Mailbox 2 */ /******************* Bit definition for CAN_RF0R register *******************/ #define CAN_RF0R_FMP0_Pos (0U) #define CAN_RF0R_FMP0_Msk (0x3U << CAN_RF0R_FMP0_Pos) /*!< 0x00000003 */ #define CAN_RF0R_FMP0 CAN_RF0R_FMP0_Msk /*!<FIFO 0 Message Pending */ #define CAN_RF0R_FULL0_Pos (3U) #define CAN_RF0R_FULL0_Msk (0x1U << CAN_RF0R_FULL0_Pos) /*!< 0x00000008 */ #define CAN_RF0R_FULL0 CAN_RF0R_FULL0_Msk /*!<FIFO 0 Full */ #define CAN_RF0R_FOVR0_Pos (4U) #define CAN_RF0R_FOVR0_Msk (0x1U << CAN_RF0R_FOVR0_Pos) /*!< 0x00000010 */ #define CAN_RF0R_FOVR0 CAN_RF0R_FOVR0_Msk /*!<FIFO 0 Overrun */ #define CAN_RF0R_RFOM0_Pos (5U) #define CAN_RF0R_RFOM0_Msk (0x1U << CAN_RF0R_RFOM0_Pos) /*!< 0x00000020 */ #define CAN_RF0R_RFOM0 CAN_RF0R_RFOM0_Msk /*!<Release FIFO 0 Output Mailbox */ /******************* Bit definition for CAN_RF1R register *******************/ #define CAN_RF1R_FMP1_Pos (0U) #define CAN_RF1R_FMP1_Msk (0x3U << CAN_RF1R_FMP1_Pos) /*!< 0x00000003 */ #define CAN_RF1R_FMP1 CAN_RF1R_FMP1_Msk /*!<FIFO 1 Message Pending */ #define CAN_RF1R_FULL1_Pos (3U) #define CAN_RF1R_FULL1_Msk (0x1U << CAN_RF1R_FULL1_Pos) /*!< 0x00000008 */ #define CAN_RF1R_FULL1 CAN_RF1R_FULL1_Msk /*!<FIFO 1 Full */ #define CAN_RF1R_FOVR1_Pos (4U) #define CAN_RF1R_FOVR1_Msk (0x1U << CAN_RF1R_FOVR1_Pos) /*!< 0x00000010 */ #define CAN_RF1R_FOVR1 CAN_RF1R_FOVR1_Msk /*!<FIFO 1 Overrun */ #define CAN_RF1R_RFOM1_Pos (5U) #define CAN_RF1R_RFOM1_Msk (0x1U << CAN_RF1R_RFOM1_Pos) /*!< 0x00000020 */ #define CAN_RF1R_RFOM1 CAN_RF1R_RFOM1_Msk /*!<Release FIFO 1 Output Mailbox */ /******************** Bit definition for CAN_IER register *******************/ #define CAN_IER_TMEIE_Pos (0U) #define CAN_IER_TMEIE_Msk (0x1U << CAN_IER_TMEIE_Pos) /*!< 0x00000001 */ #define CAN_IER_TMEIE CAN_IER_TMEIE_Msk /*!<Transmit Mailbox Empty Interrupt Enable */ #define CAN_IER_FMPIE0_Pos (1U) #define CAN_IER_FMPIE0_Msk (0x1U << CAN_IER_FMPIE0_Pos) /*!< 0x00000002 */ #define CAN_IER_FMPIE0 CAN_IER_FMPIE0_Msk /*!<FIFO Message Pending Interrupt Enable */ #define CAN_IER_FFIE0_Pos (2U) #define CAN_IER_FFIE0_Msk (0x1U << CAN_IER_FFIE0_Pos) /*!< 0x00000004 */ #define CAN_IER_FFIE0 CAN_IER_FFIE0_Msk /*!<FIFO Full Interrupt Enable */ #define CAN_IER_FOVIE0_Pos (3U) #define CAN_IER_FOVIE0_Msk (0x1U << CAN_IER_FOVIE0_Pos) /*!< 0x00000008 */ #define CAN_IER_FOVIE0 CAN_IER_FOVIE0_Msk /*!<FIFO Overrun Interrupt Enable */ #define CAN_IER_FMPIE1_Pos (4U) #define CAN_IER_FMPIE1_Msk (0x1U << CAN_IER_FMPIE1_Pos) /*!< 0x00000010 */ #define CAN_IER_FMPIE1 CAN_IER_FMPIE1_Msk /*!<FIFO Message Pending Interrupt Enable */ #define CAN_IER_FFIE1_Pos (5U) #define CAN_IER_FFIE1_Msk (0x1U << CAN_IER_FFIE1_Pos) /*!< 0x00000020 */ #define CAN_IER_FFIE1 CAN_IER_FFIE1_Msk /*!<FIFO Full Interrupt Enable */ #define CAN_IER_FOVIE1_Pos (6U) #define CAN_IER_FOVIE1_Msk (0x1U << CAN_IER_FOVIE1_Pos) /*!< 0x00000040 */ #define CAN_IER_FOVIE1 CAN_IER_FOVIE1_Msk /*!<FIFO Overrun Interrupt Enable */ #define CAN_IER_EWGIE_Pos (8U) #define CAN_IER_EWGIE_Msk (0x1U << CAN_IER_EWGIE_Pos) /*!< 0x00000100 */ #define CAN_IER_EWGIE CAN_IER_EWGIE_Msk /*!<Error Warning Interrupt Enable */ #define CAN_IER_EPVIE_Pos (9U) #define CAN_IER_EPVIE_Msk (0x1U << CAN_IER_EPVIE_Pos) /*!< 0x00000200 */ #define CAN_IER_EPVIE CAN_IER_EPVIE_Msk /*!<Error Passive Interrupt Enable */ #define CAN_IER_BOFIE_Pos (10U) #define CAN_IER_BOFIE_Msk (0x1U << CAN_IER_BOFIE_Pos) /*!< 0x00000400 */ #define CAN_IER_BOFIE CAN_IER_BOFIE_Msk /*!<Bus-Off Interrupt Enable */ #define CAN_IER_LECIE_Pos (11U) #define CAN_IER_LECIE_Msk (0x1U << CAN_IER_LECIE_Pos) /*!< 0x00000800 */ #define CAN_IER_LECIE CAN_IER_LECIE_Msk /*!<Last Error Code Interrupt Enable */ #define CAN_IER_ERRIE_Pos (15U) #define CAN_IER_ERRIE_Msk (0x1U << CAN_IER_ERRIE_Pos) /*!< 0x00008000 */ #define CAN_IER_ERRIE CAN_IER_ERRIE_Msk /*!<Error Interrupt Enable */ #define CAN_IER_WKUIE_Pos (16U) #define CAN_IER_WKUIE_Msk (0x1U << CAN_IER_WKUIE_Pos) /*!< 0x00010000 */ #define CAN_IER_WKUIE CAN_IER_WKUIE_Msk /*!<Wakeup Interrupt Enable */ #define CAN_IER_SLKIE_Pos (17U) #define CAN_IER_SLKIE_Msk (0x1U << CAN_IER_SLKIE_Pos) /*!< 0x00020000 */ #define CAN_IER_SLKIE CAN_IER_SLKIE_Msk /*!<Sleep Interrupt Enable */ #define CAN_IER_EWGIE_Pos (8U) /******************** Bit definition for CAN_ESR register *******************/ #define CAN_ESR_EWGF_Pos (0U) #define CAN_ESR_EWGF_Msk (0x1U << CAN_ESR_EWGF_Pos) /*!< 0x00000001 */ #define CAN_ESR_EWGF CAN_ESR_EWGF_Msk /*!<Error Warning Flag */ #define CAN_ESR_EPVF_Pos (1U) #define CAN_ESR_EPVF_Msk (0x1U << CAN_ESR_EPVF_Pos) /*!< 0x00000002 */ #define CAN_ESR_EPVF CAN_ESR_EPVF_Msk /*!<Error Passive Flag */ #define CAN_ESR_BOFF_Pos (2U) #define CAN_ESR_BOFF_Msk (0x1U << CAN_ESR_BOFF_Pos) /*!< 0x00000004 */ #define CAN_ESR_BOFF CAN_ESR_BOFF_Msk /*!<Bus-Off Flag */ #define CAN_ESR_LEC_Pos (4U) #define CAN_ESR_LEC_Msk (0x7U << CAN_ESR_LEC_Pos) /*!< 0x00000070 */ #define CAN_ESR_LEC CAN_ESR_LEC_Msk /*!<LEC[2:0] bits (Last Error Code) */ #define CAN_ESR_LEC_0 (0x1U << CAN_ESR_LEC_Pos) /*!< 0x00000010 */ #define CAN_ESR_LEC_1 (0x2U << CAN_ESR_LEC_Pos) /*!< 0x00000020 */ #define CAN_ESR_LEC_2 (0x4U << CAN_ESR_LEC_Pos) /*!< 0x00000040 */ #define CAN_ESR_TEC_Pos (16U) #define CAN_ESR_TEC_Msk (0xFFU << CAN_ESR_TEC_Pos) /*!< 0x00FF0000 */ #define CAN_ESR_TEC CAN_ESR_TEC_Msk /*!<Least significant byte of the 9-bit Transmit Error Counter */ #define CAN_ESR_REC_Pos (24U) #define CAN_ESR_REC_Msk (0xFFU << CAN_ESR_REC_Pos) /*!< 0xFF000000 */ #define CAN_ESR_REC CAN_ESR_REC_Msk /*!<Receive Error Counter */ /******************* Bit definition for CAN_BTR register ********************/ #define CAN_BTR_BRP_Pos (0U) #define CAN_BTR_BRP_Msk (0x3FFU << CAN_BTR_BRP_Pos) /*!< 0x000003FF */ #define CAN_BTR_BRP CAN_BTR_BRP_Msk /*!<Baud Rate Prescaler */ #define CAN_BTR_TS1_Pos (16U) #define CAN_BTR_TS1_Msk (0xFU << CAN_BTR_TS1_Pos) /*!< 0x000F0000 */ #define CAN_BTR_TS1 CAN_BTR_TS1_Msk /*!<Time Segment 1 */ #define CAN_BTR_TS1_0 (0x1U << CAN_BTR_TS1_Pos) /*!< 0x00010000 */ #define CAN_BTR_TS1_1 (0x2U << CAN_BTR_TS1_Pos) /*!< 0x00020000 */ #define CAN_BTR_TS1_2 (0x4U << CAN_BTR_TS1_Pos) /*!< 0x00040000 */ #define CAN_BTR_TS1_3 (0x8U << CAN_BTR_TS1_Pos) /*!< 0x00080000 */ #define CAN_BTR_TS2_Pos (20U) #define CAN_BTR_TS2_Msk (0x7U << CAN_BTR_TS2_Pos) /*!< 0x00700000 */ #define CAN_BTR_TS2 CAN_BTR_TS2_Msk /*!<Time Segment 2 */ #define CAN_BTR_TS2_0 (0x1U << CAN_BTR_TS2_Pos) /*!< 0x00100000 */ #define CAN_BTR_TS2_1 (0x2U << CAN_BTR_TS2_Pos) /*!< 0x00200000 */ #define CAN_BTR_TS2_2 (0x4U << CAN_BTR_TS2_Pos) /*!< 0x00400000 */ #define CAN_BTR_SJW_Pos (24U) #define CAN_BTR_SJW_Msk (0x3U << CAN_BTR_SJW_Pos) /*!< 0x03000000 */ #define CAN_BTR_SJW CAN_BTR_SJW_Msk /*!<Resynchronization Jump Width */ #define CAN_BTR_SJW_0 (0x1U << CAN_BTR_SJW_Pos) /*!< 0x01000000 */ #define CAN_BTR_SJW_1 (0x2U << CAN_BTR_SJW_Pos) /*!< 0x02000000 */ #define CAN_BTR_LBKM_Pos (30U) #define CAN_BTR_LBKM_Msk (0x1U << CAN_BTR_LBKM_Pos) /*!< 0x40000000 */ #define CAN_BTR_LBKM CAN_BTR_LBKM_Msk /*!<Loop Back Mode (Debug) */ #define CAN_BTR_SILM_Pos (31U) #define CAN_BTR_SILM_Msk (0x1U << CAN_BTR_SILM_Pos) /*!< 0x80000000 */ #define CAN_BTR_SILM CAN_BTR_SILM_Msk /*!<Silent Mode */ /*!<Mailbox registers */ /****************** Bit definition for CAN_TI0R register ********************/ #define CAN_TI0R_TXRQ_Pos (0U) #define CAN_TI0R_TXRQ_Msk (0x1U << CAN_TI0R_TXRQ_Pos) /*!< 0x00000001 */ #define CAN_TI0R_TXRQ CAN_TI0R_TXRQ_Msk /*!<Transmit Mailbox Request */ #define CAN_TI0R_RTR_Pos (1U) #define CAN_TI0R_RTR_Msk (0x1U << CAN_TI0R_RTR_Pos) /*!< 0x00000002 */ #define CAN_TI0R_RTR CAN_TI0R_RTR_Msk /*!<Remote Transmission Request */ #define CAN_TI0R_IDE_Pos (2U) #define CAN_TI0R_IDE_Msk (0x1U << CAN_TI0R_IDE_Pos) /*!< 0x00000004 */ #define CAN_TI0R_IDE CAN_TI0R_IDE_Msk /*!<Identifier Extension */ #define CAN_TI0R_EXID_Pos (3U) #define CAN_TI0R_EXID_Msk (0x3FFFFU << CAN_TI0R_EXID_Pos) /*!< 0x001FFFF8 */ #define CAN_TI0R_EXID CAN_TI0R_EXID_Msk /*!<Extended Identifier */ #define CAN_TI0R_STID_Pos (21U) #define CAN_TI0R_STID_Msk (0x7FFU << CAN_TI0R_STID_Pos) /*!< 0xFFE00000 */ #define CAN_TI0R_STID CAN_TI0R_STID_Msk /*!<Standard Identifier or Extended Identifier */ /****************** Bit definition for CAN_TDT0R register *******************/ #define CAN_TDT0R_DLC_Pos (0U) #define CAN_TDT0R_DLC_Msk (0xFU << CAN_TDT0R_DLC_Pos) /*!< 0x0000000F */ #define CAN_TDT0R_DLC CAN_TDT0R_DLC_Msk /*!<Data Length Code */ #define CAN_TDT0R_TGT_Pos (8U) #define CAN_TDT0R_TGT_Msk (0x1U << CAN_TDT0R_TGT_Pos) /*!< 0x00000100 */ #define CAN_TDT0R_TGT CAN_TDT0R_TGT_Msk /*!<Transmit Global Time */ #define CAN_TDT0R_TIME_Pos (16U) #define CAN_TDT0R_TIME_Msk (0xFFFFU << CAN_TDT0R_TIME_Pos) /*!< 0xFFFF0000 */ #define CAN_TDT0R_TIME CAN_TDT0R_TIME_Msk /*!<Message Time Stamp */ /****************** Bit definition for CAN_TDL0R register *******************/ #define CAN_TDL0R_DATA0_Pos (0U) #define CAN_TDL0R_DATA0_Msk (0xFFU << CAN_TDL0R_DATA0_Pos) /*!< 0x000000FF */ #define CAN_TDL0R_DATA0 CAN_TDL0R_DATA0_Msk /*!<Data byte 0 */ #define CAN_TDL0R_DATA1_Pos (8U) #define CAN_TDL0R_DATA1_Msk (0xFFU << CAN_TDL0R_DATA1_Pos) /*!< 0x0000FF00 */ #define CAN_TDL0R_DATA1 CAN_TDL0R_DATA1_Msk /*!<Data byte 1 */ #define CAN_TDL0R_DATA2_Pos (16U) #define CAN_TDL0R_DATA2_Msk (0xFFU << CAN_TDL0R_DATA2_Pos) /*!< 0x00FF0000 */ #define CAN_TDL0R_DATA2 CAN_TDL0R_DATA2_Msk /*!<Data byte 2 */ #define CAN_TDL0R_DATA3_Pos (24U) #define CAN_TDL0R_DATA3_Msk (0xFFU << CAN_TDL0R_DATA3_Pos) /*!< 0xFF000000 */ #define CAN_TDL0R_DATA3 CAN_TDL0R_DATA3_Msk /*!<Data byte 3 */ /****************** Bit definition for CAN_TDH0R register *******************/ #define CAN_TDH0R_DATA4_Pos (0U) #define CAN_TDH0R_DATA4_Msk (0xFFU << CAN_TDH0R_DATA4_Pos) /*!< 0x000000FF */ #define CAN_TDH0R_DATA4 CAN_TDH0R_DATA4_Msk /*!<Data byte 4 */ #define CAN_TDH0R_DATA5_Pos (8U) #define CAN_TDH0R_DATA5_Msk (0xFFU << CAN_TDH0R_DATA5_Pos) /*!< 0x0000FF00 */ #define CAN_TDH0R_DATA5 CAN_TDH0R_DATA5_Msk /*!<Data byte 5 */ #define CAN_TDH0R_DATA6_Pos (16U) #define CAN_TDH0R_DATA6_Msk (0xFFU << CAN_TDH0R_DATA6_Pos) /*!< 0x00FF0000 */ #define CAN_TDH0R_DATA6 CAN_TDH0R_DATA6_Msk /*!<Data byte 6 */ #define CAN_TDH0R_DATA7_Pos (24U) #define CAN_TDH0R_DATA7_Msk (0xFFU << CAN_TDH0R_DATA7_Pos) /*!< 0xFF000000 */ #define CAN_TDH0R_DATA7 CAN_TDH0R_DATA7_Msk /*!<Data byte 7 */ /******************* Bit definition for CAN_TI1R register *******************/ #define CAN_TI1R_TXRQ_Pos (0U) #define CAN_TI1R_TXRQ_Msk (0x1U << CAN_TI1R_TXRQ_Pos) /*!< 0x00000001 */ #define CAN_TI1R_TXRQ CAN_TI1R_TXRQ_Msk /*!<Transmit Mailbox Request */ #define CAN_TI1R_RTR_Pos (1U) #define CAN_TI1R_RTR_Msk (0x1U << CAN_TI1R_RTR_Pos) /*!< 0x00000002 */ #define CAN_TI1R_RTR CAN_TI1R_RTR_Msk /*!<Remote Transmission Request */ #define CAN_TI1R_IDE_Pos (2U) #define CAN_TI1R_IDE_Msk (0x1U << CAN_TI1R_IDE_Pos) /*!< 0x00000004 */ #define CAN_TI1R_IDE CAN_TI1R_IDE_Msk /*!<Identifier Extension */ #define CAN_TI1R_EXID_Pos (3U) #define CAN_TI1R_EXID_Msk (0x3FFFFU << CAN_TI1R_EXID_Pos) /*!< 0x001FFFF8 */ #define CAN_TI1R_EXID CAN_TI1R_EXID_Msk /*!<Extended Identifier */ #define CAN_TI1R_STID_Pos (21U) #define CAN_TI1R_STID_Msk (0x7FFU << CAN_TI1R_STID_Pos) /*!< 0xFFE00000 */ #define CAN_TI1R_STID CAN_TI1R_STID_Msk /*!<Standard Identifier or Extended Identifier */ /******************* Bit definition for CAN_TDT1R register ******************/ #define CAN_TDT1R_DLC_Pos (0U) #define CAN_TDT1R_DLC_Msk (0xFU << CAN_TDT1R_DLC_Pos) /*!< 0x0000000F */ #define CAN_TDT1R_DLC CAN_TDT1R_DLC_Msk /*!<Data Length Code */ #define CAN_TDT1R_TGT_Pos (8U) #define CAN_TDT1R_TGT_Msk (0x1U << CAN_TDT1R_TGT_Pos) /*!< 0x00000100 */ #define CAN_TDT1R_TGT CAN_TDT1R_TGT_Msk /*!<Transmit Global Time */ #define CAN_TDT1R_TIME_Pos (16U) #define CAN_TDT1R_TIME_Msk (0xFFFFU << CAN_TDT1R_TIME_Pos) /*!< 0xFFFF0000 */ #define CAN_TDT1R_TIME CAN_TDT1R_TIME_Msk /*!<Message Time Stamp */ /******************* Bit definition for CAN_TDL1R register ******************/ #define CAN_TDL1R_DATA0_Pos (0U) #define CAN_TDL1R_DATA0_Msk (0xFFU << CAN_TDL1R_DATA0_Pos) /*!< 0x000000FF */ #define CAN_TDL1R_DATA0 CAN_TDL1R_DATA0_Msk /*!<Data byte 0 */ #define CAN_TDL1R_DATA1_Pos (8U) #define CAN_TDL1R_DATA1_Msk (0xFFU << CAN_TDL1R_DATA1_Pos) /*!< 0x0000FF00 */ #define CAN_TDL1R_DATA1 CAN_TDL1R_DATA1_Msk /*!<Data byte 1 */ #define CAN_TDL1R_DATA2_Pos (16U) #define CAN_TDL1R_DATA2_Msk (0xFFU << CAN_TDL1R_DATA2_Pos) /*!< 0x00FF0000 */ #define CAN_TDL1R_DATA2 CAN_TDL1R_DATA2_Msk /*!<Data byte 2 */ #define CAN_TDL1R_DATA3_Pos (24U) #define CAN_TDL1R_DATA3_Msk (0xFFU << CAN_TDL1R_DATA3_Pos) /*!< 0xFF000000 */ #define CAN_TDL1R_DATA3 CAN_TDL1R_DATA3_Msk /*!<Data byte 3 */ /******************* Bit definition for CAN_TDH1R register ******************/ #define CAN_TDH1R_DATA4_Pos (0U) #define CAN_TDH1R_DATA4_Msk (0xFFU << CAN_TDH1R_DATA4_Pos) /*!< 0x000000FF */ #define CAN_TDH1R_DATA4 CAN_TDH1R_DATA4_Msk /*!<Data byte 4 */ #define CAN_TDH1R_DATA5_Pos (8U) #define CAN_TDH1R_DATA5_Msk (0xFFU << CAN_TDH1R_DATA5_Pos) /*!< 0x0000FF00 */ #define CAN_TDH1R_DATA5 CAN_TDH1R_DATA5_Msk /*!<Data byte 5 */ #define CAN_TDH1R_DATA6_Pos (16U) #define CAN_TDH1R_DATA6_Msk (0xFFU << CAN_TDH1R_DATA6_Pos) /*!< 0x00FF0000 */ #define CAN_TDH1R_DATA6 CAN_TDH1R_DATA6_Msk /*!<Data byte 6 */ #define CAN_TDH1R_DATA7_Pos (24U) #define CAN_TDH1R_DATA7_Msk (0xFFU << CAN_TDH1R_DATA7_Pos) /*!< 0xFF000000 */ #define CAN_TDH1R_DATA7 CAN_TDH1R_DATA7_Msk /*!<Data byte 7 */ /******************* Bit definition for CAN_TI2R register *******************/ #define CAN_TI2R_TXRQ_Pos (0U) #define CAN_TI2R_TXRQ_Msk (0x1U << CAN_TI2R_TXRQ_Pos) /*!< 0x00000001 */ #define CAN_TI2R_TXRQ CAN_TI2R_TXRQ_Msk /*!<Transmit Mailbox Request */ #define CAN_TI2R_RTR_Pos (1U) #define CAN_TI2R_RTR_Msk (0x1U << CAN_TI2R_RTR_Pos) /*!< 0x00000002 */ #define CAN_TI2R_RTR CAN_TI2R_RTR_Msk /*!<Remote Transmission Request */ #define CAN_TI2R_IDE_Pos (2U) #define CAN_TI2R_IDE_Msk (0x1U << CAN_TI2R_IDE_Pos) /*!< 0x00000004 */ #define CAN_TI2R_IDE CAN_TI2R_IDE_Msk /*!<Identifier Extension */ #define CAN_TI2R_EXID_Pos (3U) #define CAN_TI2R_EXID_Msk (0x3FFFFU << CAN_TI2R_EXID_Pos) /*!< 0x001FFFF8 */ #define CAN_TI2R_EXID CAN_TI2R_EXID_Msk /*!<Extended identifier */ #define CAN_TI2R_STID_Pos (21U) #define CAN_TI2R_STID_Msk (0x7FFU << CAN_TI2R_STID_Pos) /*!< 0xFFE00000 */ #define CAN_TI2R_STID CAN_TI2R_STID_Msk /*!<Standard Identifier or Extended Identifier */ /******************* Bit definition for CAN_TDT2R register ******************/ #define CAN_TDT2R_DLC_Pos (0U) #define CAN_TDT2R_DLC_Msk (0xFU << CAN_TDT2R_DLC_Pos) /*!< 0x0000000F */ #define CAN_TDT2R_DLC CAN_TDT2R_DLC_Msk /*!<Data Length Code */ #define CAN_TDT2R_TGT_Pos (8U) #define CAN_TDT2R_TGT_Msk (0x1U << CAN_TDT2R_TGT_Pos) /*!< 0x00000100 */ #define CAN_TDT2R_TGT CAN_TDT2R_TGT_Msk /*!<Transmit Global Time */ #define CAN_TDT2R_TIME_Pos (16U) #define CAN_TDT2R_TIME_Msk (0xFFFFU << CAN_TDT2R_TIME_Pos) /*!< 0xFFFF0000 */ #define CAN_TDT2R_TIME CAN_TDT2R_TIME_Msk /*!<Message Time Stamp */ /******************* Bit definition for CAN_TDL2R register ******************/ #define CAN_TDL2R_DATA0_Pos (0U) #define CAN_TDL2R_DATA0_Msk (0xFFU << CAN_TDL2R_DATA0_Pos) /*!< 0x000000FF */ #define CAN_TDL2R_DATA0 CAN_TDL2R_DATA0_Msk /*!<Data byte 0 */ #define CAN_TDL2R_DATA1_Pos (8U) #define CAN_TDL2R_DATA1_Msk (0xFFU << CAN_TDL2R_DATA1_Pos) /*!< 0x0000FF00 */ #define CAN_TDL2R_DATA1 CAN_TDL2R_DATA1_Msk /*!<Data byte 1 */ #define CAN_TDL2R_DATA2_Pos (16U) #define CAN_TDL2R_DATA2_Msk (0xFFU << CAN_TDL2R_DATA2_Pos) /*!< 0x00FF0000 */ #define CAN_TDL2R_DATA2 CAN_TDL2R_DATA2_Msk /*!<Data byte 2 */ #define CAN_TDL2R_DATA3_Pos (24U) #define CAN_TDL2R_DATA3_Msk (0xFFU << CAN_TDL2R_DATA3_Pos) /*!< 0xFF000000 */ #define CAN_TDL2R_DATA3 CAN_TDL2R_DATA3_Msk /*!<Data byte 3 */ /******************* Bit definition for CAN_TDH2R register ******************/ #define CAN_TDH2R_DATA4_Pos (0U) #define CAN_TDH2R_DATA4_Msk (0xFFU << CAN_TDH2R_DATA4_Pos) /*!< 0x000000FF */ #define CAN_TDH2R_DATA4 CAN_TDH2R_DATA4_Msk /*!<Data byte 4 */ #define CAN_TDH2R_DATA5_Pos (8U) #define CAN_TDH2R_DATA5_Msk (0xFFU << CAN_TDH2R_DATA5_Pos) /*!< 0x0000FF00 */ #define CAN_TDH2R_DATA5 CAN_TDH2R_DATA5_Msk /*!<Data byte 5 */ #define CAN_TDH2R_DATA6_Pos (16U) #define CAN_TDH2R_DATA6_Msk (0xFFU << CAN_TDH2R_DATA6_Pos) /*!< 0x00FF0000 */ #define CAN_TDH2R_DATA6 CAN_TDH2R_DATA6_Msk /*!<Data byte 6 */ #define CAN_TDH2R_DATA7_Pos (24U) #define CAN_TDH2R_DATA7_Msk (0xFFU << CAN_TDH2R_DATA7_Pos) /*!< 0xFF000000 */ #define CAN_TDH2R_DATA7 CAN_TDH2R_DATA7_Msk /*!<Data byte 7 */ /******************* Bit definition for CAN_RI0R register *******************/ #define CAN_RI0R_RTR_Pos (1U) #define CAN_RI0R_RTR_Msk (0x1U << CAN_RI0R_RTR_Pos) /*!< 0x00000002 */ #define CAN_RI0R_RTR CAN_RI0R_RTR_Msk /*!<Remote Transmission Request */ #define CAN_RI0R_IDE_Pos (2U) #define CAN_RI0R_IDE_Msk (0x1U << CAN_RI0R_IDE_Pos) /*!< 0x00000004 */ #define CAN_RI0R_IDE CAN_RI0R_IDE_Msk /*!<Identifier Extension */ #define CAN_RI0R_EXID_Pos (3U) #define CAN_RI0R_EXID_Msk (0x3FFFFU << CAN_RI0R_EXID_Pos) /*!< 0x001FFFF8 */ #define CAN_RI0R_EXID CAN_RI0R_EXID_Msk /*!<Extended Identifier */ #define CAN_RI0R_STID_Pos (21U) #define CAN_RI0R_STID_Msk (0x7FFU << CAN_RI0R_STID_Pos) /*!< 0xFFE00000 */ #define CAN_RI0R_STID CAN_RI0R_STID_Msk /*!<Standard Identifier or Extended Identifier */ /******************* Bit definition for CAN_RDT0R register ******************/ #define CAN_RDT0R_DLC_Pos (0U) #define CAN_RDT0R_DLC_Msk (0xFU << CAN_RDT0R_DLC_Pos) /*!< 0x0000000F */ #define CAN_RDT0R_DLC CAN_RDT0R_DLC_Msk /*!<Data Length Code */ #define CAN_RDT0R_FMI_Pos (8U) #define CAN_RDT0R_FMI_Msk (0xFFU << CAN_RDT0R_FMI_Pos) /*!< 0x0000FF00 */ #define CAN_RDT0R_FMI CAN_RDT0R_FMI_Msk /*!<Filter Match Index */ #define CAN_RDT0R_TIME_Pos (16U) #define CAN_RDT0R_TIME_Msk (0xFFFFU << CAN_RDT0R_TIME_Pos) /*!< 0xFFFF0000 */ #define CAN_RDT0R_TIME CAN_RDT0R_TIME_Msk /*!<Message Time Stamp */ /******************* Bit definition for CAN_RDL0R register ******************/ #define CAN_RDL0R_DATA0_Pos (0U) #define CAN_RDL0R_DATA0_Msk (0xFFU << CAN_RDL0R_DATA0_Pos) /*!< 0x000000FF */ #define CAN_RDL0R_DATA0 CAN_RDL0R_DATA0_Msk /*!<Data byte 0 */ #define CAN_RDL0R_DATA1_Pos (8U) #define CAN_RDL0R_DATA1_Msk (0xFFU << CAN_RDL0R_DATA1_Pos) /*!< 0x0000FF00 */ #define CAN_RDL0R_DATA1 CAN_RDL0R_DATA1_Msk /*!<Data byte 1 */ #define CAN_RDL0R_DATA2_Pos (16U) #define CAN_RDL0R_DATA2_Msk (0xFFU << CAN_RDL0R_DATA2_Pos) /*!< 0x00FF0000 */ #define CAN_RDL0R_DATA2 CAN_RDL0R_DATA2_Msk /*!<Data byte 2 */ #define CAN_RDL0R_DATA3_Pos (24U) #define CAN_RDL0R_DATA3_Msk (0xFFU << CAN_RDL0R_DATA3_Pos) /*!< 0xFF000000 */ #define CAN_RDL0R_DATA3 CAN_RDL0R_DATA3_Msk /*!<Data byte 3 */ /******************* Bit definition for CAN_RDH0R register ******************/ #define CAN_RDH0R_DATA4_Pos (0U) #define CAN_RDH0R_DATA4_Msk (0xFFU << CAN_RDH0R_DATA4_Pos) /*!< 0x000000FF */ #define CAN_RDH0R_DATA4 CAN_RDH0R_DATA4_Msk /*!<Data byte 4 */ #define CAN_RDH0R_DATA5_Pos (8U) #define CAN_RDH0R_DATA5_Msk (0xFFU << CAN_RDH0R_DATA5_Pos) /*!< 0x0000FF00 */ #define CAN_RDH0R_DATA5 CAN_RDH0R_DATA5_Msk /*!<Data byte 5 */ #define CAN_RDH0R_DATA6_Pos (16U) #define CAN_RDH0R_DATA6_Msk (0xFFU << CAN_RDH0R_DATA6_Pos) /*!< 0x00FF0000 */ #define CAN_RDH0R_DATA6 CAN_RDH0R_DATA6_Msk /*!<Data byte 6 */ #define CAN_RDH0R_DATA7_Pos (24U) #define CAN_RDH0R_DATA7_Msk (0xFFU << CAN_RDH0R_DATA7_Pos) /*!< 0xFF000000 */ #define CAN_RDH0R_DATA7 CAN_RDH0R_DATA7_Msk /*!<Data byte 7 */ /******************* Bit definition for CAN_RI1R register *******************/ #define CAN_RI1R_RTR_Pos (1U) #define CAN_RI1R_RTR_Msk (0x1U << CAN_RI1R_RTR_Pos) /*!< 0x00000002 */ #define CAN_RI1R_RTR CAN_RI1R_RTR_Msk /*!<Remote Transmission Request */ #define CAN_RI1R_IDE_Pos (2U) #define CAN_RI1R_IDE_Msk (0x1U << CAN_RI1R_IDE_Pos) /*!< 0x00000004 */ #define CAN_RI1R_IDE CAN_RI1R_IDE_Msk /*!<Identifier Extension */ #define CAN_RI1R_EXID_Pos (3U) #define CAN_RI1R_EXID_Msk (0x3FFFFU << CAN_RI1R_EXID_Pos) /*!< 0x001FFFF8 */ #define CAN_RI1R_EXID CAN_RI1R_EXID_Msk /*!<Extended identifier */ #define CAN_RI1R_STID_Pos (21U) #define CAN_RI1R_STID_Msk (0x7FFU << CAN_RI1R_STID_Pos) /*!< 0xFFE00000 */ #define CAN_RI1R_STID CAN_RI1R_STID_Msk /*!<Standard Identifier or Extended Identifier */ /******************* Bit definition for CAN_RDT1R register ******************/ #define CAN_RDT1R_DLC_Pos (0U) #define CAN_RDT1R_DLC_Msk (0xFU << CAN_RDT1R_DLC_Pos) /*!< 0x0000000F */ #define CAN_RDT1R_DLC CAN_RDT1R_DLC_Msk /*!<Data Length Code */ #define CAN_RDT1R_FMI_Pos (8U) #define CAN_RDT1R_FMI_Msk (0xFFU << CAN_RDT1R_FMI_Pos) /*!< 0x0000FF00 */ #define CAN_RDT1R_FMI CAN_RDT1R_FMI_Msk /*!<Filter Match Index */ #define CAN_RDT1R_TIME_Pos (16U) #define CAN_RDT1R_TIME_Msk (0xFFFFU << CAN_RDT1R_TIME_Pos) /*!< 0xFFFF0000 */ #define CAN_RDT1R_TIME CAN_RDT1R_TIME_Msk /*!<Message Time Stamp */ /******************* Bit definition for CAN_RDL1R register ******************/ #define CAN_RDL1R_DATA0_Pos (0U) #define CAN_RDL1R_DATA0_Msk (0xFFU << CAN_RDL1R_DATA0_Pos) /*!< 0x000000FF */ #define CAN_RDL1R_DATA0 CAN_RDL1R_DATA0_Msk /*!<Data byte 0 */ #define CAN_RDL1R_DATA1_Pos (8U) #define CAN_RDL1R_DATA1_Msk (0xFFU << CAN_RDL1R_DATA1_Pos) /*!< 0x0000FF00 */ #define CAN_RDL1R_DATA1 CAN_RDL1R_DATA1_Msk /*!<Data byte 1 */ #define CAN_RDL1R_DATA2_Pos (16U) #define CAN_RDL1R_DATA2_Msk (0xFFU << CAN_RDL1R_DATA2_Pos) /*!< 0x00FF0000 */ #define CAN_RDL1R_DATA2 CAN_RDL1R_DATA2_Msk /*!<Data byte 2 */ #define CAN_RDL1R_DATA3_Pos (24U) #define CAN_RDL1R_DATA3_Msk (0xFFU << CAN_RDL1R_DATA3_Pos) /*!< 0xFF000000 */ #define CAN_RDL1R_DATA3 CAN_RDL1R_DATA3_Msk /*!<Data byte 3 */ /******************* Bit definition for CAN_RDH1R register ******************/ #define CAN_RDH1R_DATA4_Pos (0U) #define CAN_RDH1R_DATA4_Msk (0xFFU << CAN_RDH1R_DATA4_Pos) /*!< 0x000000FF */ #define CAN_RDH1R_DATA4 CAN_RDH1R_DATA4_Msk /*!<Data byte 4 */ #define CAN_RDH1R_DATA5_Pos (8U) #define CAN_RDH1R_DATA5_Msk (0xFFU << CAN_RDH1R_DATA5_Pos) /*!< 0x0000FF00 */ #define CAN_RDH1R_DATA5 CAN_RDH1R_DATA5_Msk /*!<Data byte 5 */ #define CAN_RDH1R_DATA6_Pos (16U) #define CAN_RDH1R_DATA6_Msk (0xFFU << CAN_RDH1R_DATA6_Pos) /*!< 0x00FF0000 */ #define CAN_RDH1R_DATA6 CAN_RDH1R_DATA6_Msk /*!<Data byte 6 */ #define CAN_RDH1R_DATA7_Pos (24U) #define CAN_RDH1R_DATA7_Msk (0xFFU << CAN_RDH1R_DATA7_Pos) /*!< 0xFF000000 */ #define CAN_RDH1R_DATA7 CAN_RDH1R_DATA7_Msk /*!<Data byte 7 */ /*!<CAN filter registers */ /******************* Bit definition for CAN_FMR register ********************/ #define CAN_FMR_FINIT_Pos (0U) #define CAN_FMR_FINIT_Msk (0x1U << CAN_FMR_FINIT_Pos) /*!< 0x00000001 */ #define CAN_FMR_FINIT CAN_FMR_FINIT_Msk /*!<Filter Init Mode */ #define CAN_FMR_CAN2SB_Pos (8U) #define CAN_FMR_CAN2SB_Msk (0x3FU << CAN_FMR_CAN2SB_Pos) /*!< 0x00003F00 */ #define CAN_FMR_CAN2SB CAN_FMR_CAN2SB_Msk /*!<CAN2 start bank */ /******************* Bit definition for CAN_FM1R register *******************/ #define CAN_FM1R_FBM_Pos (0U) #define CAN_FM1R_FBM_Msk (0xFFFFFFFU << CAN_FM1R_FBM_Pos) /*!< 0x0FFFFFFF */ #define CAN_FM1R_FBM CAN_FM1R_FBM_Msk /*!<Filter Mode */ #define CAN_FM1R_FBM0_Pos (0U) #define CAN_FM1R_FBM0_Msk (0x1U << CAN_FM1R_FBM0_Pos) /*!< 0x00000001 */ #define CAN_FM1R_FBM0 CAN_FM1R_FBM0_Msk /*!<Filter Init Mode bit 0 */ #define CAN_FM1R_FBM1_Pos (1U) #define CAN_FM1R_FBM1_Msk (0x1U << CAN_FM1R_FBM1_Pos) /*!< 0x00000002 */ #define CAN_FM1R_FBM1 CAN_FM1R_FBM1_Msk /*!<Filter Init Mode bit 1 */ #define CAN_FM1R_FBM2_Pos (2U) #define CAN_FM1R_FBM2_Msk (0x1U << CAN_FM1R_FBM2_Pos) /*!< 0x00000004 */ #define CAN_FM1R_FBM2 CAN_FM1R_FBM2_Msk /*!<Filter Init Mode bit 2 */ #define CAN_FM1R_FBM3_Pos (3U) #define CAN_FM1R_FBM3_Msk (0x1U << CAN_FM1R_FBM3_Pos) /*!< 0x00000008 */ #define CAN_FM1R_FBM3 CAN_FM1R_FBM3_Msk /*!<Filter Init Mode bit 3 */ #define CAN_FM1R_FBM4_Pos (4U) #define CAN_FM1R_FBM4_Msk (0x1U << CAN_FM1R_FBM4_Pos) /*!< 0x00000010 */ #define CAN_FM1R_FBM4 CAN_FM1R_FBM4_Msk /*!<Filter Init Mode bit 4 */ #define CAN_FM1R_FBM5_Pos (5U) #define CAN_FM1R_FBM5_Msk (0x1U << CAN_FM1R_FBM5_Pos) /*!< 0x00000020 */ #define CAN_FM1R_FBM5 CAN_FM1R_FBM5_Msk /*!<Filter Init Mode bit 5 */ #define CAN_FM1R_FBM6_Pos (6U) #define CAN_FM1R_FBM6_Msk (0x1U << CAN_FM1R_FBM6_Pos) /*!< 0x00000040 */ #define CAN_FM1R_FBM6 CAN_FM1R_FBM6_Msk /*!<Filter Init Mode bit 6 */ #define CAN_FM1R_FBM7_Pos (7U) #define CAN_FM1R_FBM7_Msk (0x1U << CAN_FM1R_FBM7_Pos) /*!< 0x00000080 */ #define CAN_FM1R_FBM7 CAN_FM1R_FBM7_Msk /*!<Filter Init Mode bit 7 */ #define CAN_FM1R_FBM8_Pos (8U) #define CAN_FM1R_FBM8_Msk (0x1U << CAN_FM1R_FBM8_Pos) /*!< 0x00000100 */ #define CAN_FM1R_FBM8 CAN_FM1R_FBM8_Msk /*!<Filter Init Mode bit 8 */ #define CAN_FM1R_FBM9_Pos (9U) #define CAN_FM1R_FBM9_Msk (0x1U << CAN_FM1R_FBM9_Pos) /*!< 0x00000200 */ #define CAN_FM1R_FBM9 CAN_FM1R_FBM9_Msk /*!<Filter Init Mode bit 9 */ #define CAN_FM1R_FBM10_Pos (10U) #define CAN_FM1R_FBM10_Msk (0x1U << CAN_FM1R_FBM10_Pos) /*!< 0x00000400 */ #define CAN_FM1R_FBM10 CAN_FM1R_FBM10_Msk /*!<Filter Init Mode bit 10 */ #define CAN_FM1R_FBM11_Pos (11U) #define CAN_FM1R_FBM11_Msk (0x1U << CAN_FM1R_FBM11_Pos) /*!< 0x00000800 */ #define CAN_FM1R_FBM11 CAN_FM1R_FBM11_Msk /*!<Filter Init Mode bit 11 */ #define CAN_FM1R_FBM12_Pos (12U) #define CAN_FM1R_FBM12_Msk (0x1U << CAN_FM1R_FBM12_Pos) /*!< 0x00001000 */ #define CAN_FM1R_FBM12 CAN_FM1R_FBM12_Msk /*!<Filter Init Mode bit 12 */ #define CAN_FM1R_FBM13_Pos (13U) #define CAN_FM1R_FBM13_Msk (0x1U << CAN_FM1R_FBM13_Pos) /*!< 0x00002000 */ #define CAN_FM1R_FBM13 CAN_FM1R_FBM13_Msk /*!<Filter Init Mode bit 13 */ #define CAN_FM1R_FBM14_Pos (14U) #define CAN_FM1R_FBM14_Msk (0x1U << CAN_FM1R_FBM14_Pos) /*!< 0x00004000 */ #define CAN_FM1R_FBM14 CAN_FM1R_FBM14_Msk /*!<Filter Init Mode bit 14 */ #define CAN_FM1R_FBM15_Pos (15U) #define CAN_FM1R_FBM15_Msk (0x1U << CAN_FM1R_FBM15_Pos) /*!< 0x00008000 */ #define CAN_FM1R_FBM15 CAN_FM1R_FBM15_Msk /*!<Filter Init Mode bit 15 */ #define CAN_FM1R_FBM16_Pos (16U) #define CAN_FM1R_FBM16_Msk (0x1U << CAN_FM1R_FBM16_Pos) /*!< 0x00010000 */ #define CAN_FM1R_FBM16 CAN_FM1R_FBM16_Msk /*!<Filter Init Mode bit 16 */ #define CAN_FM1R_FBM17_Pos (17U) #define CAN_FM1R_FBM17_Msk (0x1U << CAN_FM1R_FBM17_Pos) /*!< 0x00020000 */ #define CAN_FM1R_FBM17 CAN_FM1R_FBM17_Msk /*!<Filter Init Mode bit 17 */ #define CAN_FM1R_FBM18_Pos (18U) #define CAN_FM1R_FBM18_Msk (0x1U << CAN_FM1R_FBM18_Pos) /*!< 0x00040000 */ #define CAN_FM1R_FBM18 CAN_FM1R_FBM18_Msk /*!<Filter Init Mode bit 18 */ #define CAN_FM1R_FBM19_Pos (19U) #define CAN_FM1R_FBM19_Msk (0x1U << CAN_FM1R_FBM19_Pos) /*!< 0x00080000 */ #define CAN_FM1R_FBM19 CAN_FM1R_FBM19_Msk /*!<Filter Init Mode bit 19 */ #define CAN_FM1R_FBM20_Pos (20U) #define CAN_FM1R_FBM20_Msk (0x1U << CAN_FM1R_FBM20_Pos) /*!< 0x00100000 */ #define CAN_FM1R_FBM20 CAN_FM1R_FBM20_Msk /*!<Filter Init Mode bit 20 */ #define CAN_FM1R_FBM21_Pos (21U) #define CAN_FM1R_FBM21_Msk (0x1U << CAN_FM1R_FBM21_Pos) /*!< 0x00200000 */ #define CAN_FM1R_FBM21 CAN_FM1R_FBM21_Msk /*!<Filter Init Mode bit 21 */ #define CAN_FM1R_FBM22_Pos (22U) #define CAN_FM1R_FBM22_Msk (0x1U << CAN_FM1R_FBM22_Pos) /*!< 0x00400000 */ #define CAN_FM1R_FBM22 CAN_FM1R_FBM22_Msk /*!<Filter Init Mode bit 22 */ #define CAN_FM1R_FBM23_Pos (23U) #define CAN_FM1R_FBM23_Msk (0x1U << CAN_FM1R_FBM23_Pos) /*!< 0x00800000 */ #define CAN_FM1R_FBM23 CAN_FM1R_FBM23_Msk /*!<Filter Init Mode bit 23 */ #define CAN_FM1R_FBM24_Pos (24U) #define CAN_FM1R_FBM24_Msk (0x1U << CAN_FM1R_FBM24_Pos) /*!< 0x01000000 */ #define CAN_FM1R_FBM24 CAN_FM1R_FBM24_Msk /*!<Filter Init Mode bit 24 */ #define CAN_FM1R_FBM25_Pos (25U) #define CAN_FM1R_FBM25_Msk (0x1U << CAN_FM1R_FBM25_Pos) /*!< 0x02000000 */ #define CAN_FM1R_FBM25 CAN_FM1R_FBM25_Msk /*!<Filter Init Mode bit 25 */ #define CAN_FM1R_FBM26_Pos (26U) #define CAN_FM1R_FBM26_Msk (0x1U << CAN_FM1R_FBM26_Pos) /*!< 0x04000000 */ #define CAN_FM1R_FBM26 CAN_FM1R_FBM26_Msk /*!<Filter Init Mode bit 26 */ #define CAN_FM1R_FBM27_Pos (27U) #define CAN_FM1R_FBM27_Msk (0x1U << CAN_FM1R_FBM27_Pos) /*!< 0x08000000 */ #define CAN_FM1R_FBM27 CAN_FM1R_FBM27_Msk /*!<Filter Init Mode bit 27 */ /******************* Bit definition for CAN_FS1R register *******************/ #define CAN_FS1R_FSC_Pos (0U) #define CAN_FS1R_FSC_Msk (0xFFFFFFFU << CAN_FS1R_FSC_Pos) /*!< 0x0FFFFFFF */ #define CAN_FS1R_FSC CAN_FS1R_FSC_Msk /*!<Filter Scale Configuration */ #define CAN_FS1R_FSC0_Pos (0U) #define CAN_FS1R_FSC0_Msk (0x1U << CAN_FS1R_FSC0_Pos) /*!< 0x00000001 */ #define CAN_FS1R_FSC0 CAN_FS1R_FSC0_Msk /*!<Filter Scale Configuration bit 0 */ #define CAN_FS1R_FSC1_Pos (1U) #define CAN_FS1R_FSC1_Msk (0x1U << CAN_FS1R_FSC1_Pos) /*!< 0x00000002 */ #define CAN_FS1R_FSC1 CAN_FS1R_FSC1_Msk /*!<Filter Scale Configuration bit 1 */ #define CAN_FS1R_FSC2_Pos (2U) #define CAN_FS1R_FSC2_Msk (0x1U << CAN_FS1R_FSC2_Pos) /*!< 0x00000004 */ #define CAN_FS1R_FSC2 CAN_FS1R_FSC2_Msk /*!<Filter Scale Configuration bit 2 */ #define CAN_FS1R_FSC3_Pos (3U) #define CAN_FS1R_FSC3_Msk (0x1U << CAN_FS1R_FSC3_Pos) /*!< 0x00000008 */ #define CAN_FS1R_FSC3 CAN_FS1R_FSC3_Msk /*!<Filter Scale Configuration bit 3 */ #define CAN_FS1R_FSC4_Pos (4U) #define CAN_FS1R_FSC4_Msk (0x1U << CAN_FS1R_FSC4_Pos) /*!< 0x00000010 */ #define CAN_FS1R_FSC4 CAN_FS1R_FSC4_Msk /*!<Filter Scale Configuration bit 4 */ #define CAN_FS1R_FSC5_Pos (5U) #define CAN_FS1R_FSC5_Msk (0x1U << CAN_FS1R_FSC5_Pos) /*!< 0x00000020 */ #define CAN_FS1R_FSC5 CAN_FS1R_FSC5_Msk /*!<Filter Scale Configuration bit 5 */ #define CAN_FS1R_FSC6_Pos (6U) #define CAN_FS1R_FSC6_Msk (0x1U << CAN_FS1R_FSC6_Pos) /*!< 0x00000040 */ #define CAN_FS1R_FSC6 CAN_FS1R_FSC6_Msk /*!<Filter Scale Configuration bit 6 */ #define CAN_FS1R_FSC7_Pos (7U) #define CAN_FS1R_FSC7_Msk (0x1U << CAN_FS1R_FSC7_Pos) /*!< 0x00000080 */ #define CAN_FS1R_FSC7 CAN_FS1R_FSC7_Msk /*!<Filter Scale Configuration bit 7 */ #define CAN_FS1R_FSC8_Pos (8U) #define CAN_FS1R_FSC8_Msk (0x1U << CAN_FS1R_FSC8_Pos) /*!< 0x00000100 */ #define CAN_FS1R_FSC8 CAN_FS1R_FSC8_Msk /*!<Filter Scale Configuration bit 8 */ #define CAN_FS1R_FSC9_Pos (9U) #define CAN_FS1R_FSC9_Msk (0x1U << CAN_FS1R_FSC9_Pos) /*!< 0x00000200 */ #define CAN_FS1R_FSC9 CAN_FS1R_FSC9_Msk /*!<Filter Scale Configuration bit 9 */ #define CAN_FS1R_FSC10_Pos (10U) #define CAN_FS1R_FSC10_Msk (0x1U << CAN_FS1R_FSC10_Pos) /*!< 0x00000400 */ #define CAN_FS1R_FSC10 CAN_FS1R_FSC10_Msk /*!<Filter Scale Configuration bit 10 */ #define CAN_FS1R_FSC11_Pos (11U) #define CAN_FS1R_FSC11_Msk (0x1U << CAN_FS1R_FSC11_Pos) /*!< 0x00000800 */ #define CAN_FS1R_FSC11 CAN_FS1R_FSC11_Msk /*!<Filter Scale Configuration bit 11 */ #define CAN_FS1R_FSC12_Pos (12U) #define CAN_FS1R_FSC12_Msk (0x1U << CAN_FS1R_FSC12_Pos) /*!< 0x00001000 */ #define CAN_FS1R_FSC12 CAN_FS1R_FSC12_Msk /*!<Filter Scale Configuration bit 12 */ #define CAN_FS1R_FSC13_Pos (13U) #define CAN_FS1R_FSC13_Msk (0x1U << CAN_FS1R_FSC13_Pos) /*!< 0x00002000 */ #define CAN_FS1R_FSC13 CAN_FS1R_FSC13_Msk /*!<Filter Scale Configuration bit 13 */ #define CAN_FS1R_FSC14_Pos (14U) #define CAN_FS1R_FSC14_Msk (0x1U << CAN_FS1R_FSC14_Pos) /*!< 0x00004000 */ #define CAN_FS1R_FSC14 CAN_FS1R_FSC14_Msk /*!<Filter Scale Configuration bit 14 */ #define CAN_FS1R_FSC15_Pos (15U) #define CAN_FS1R_FSC15_Msk (0x1U << CAN_FS1R_FSC15_Pos) /*!< 0x00008000 */ #define CAN_FS1R_FSC15 CAN_FS1R_FSC15_Msk /*!<Filter Scale Configuration bit 15 */ #define CAN_FS1R_FSC16_Pos (16U) #define CAN_FS1R_FSC16_Msk (0x1U << CAN_FS1R_FSC16_Pos) /*!< 0x00010000 */ #define CAN_FS1R_FSC16 CAN_FS1R_FSC16_Msk /*!<Filter Scale Configuration bit 16 */ #define CAN_FS1R_FSC17_Pos (17U) #define CAN_FS1R_FSC17_Msk (0x1U << CAN_FS1R_FSC17_Pos) /*!< 0x00020000 */ #define CAN_FS1R_FSC17 CAN_FS1R_FSC17_Msk /*!<Filter Scale Configuration bit 17 */ #define CAN_FS1R_FSC18_Pos (18U) #define CAN_FS1R_FSC18_Msk (0x1U << CAN_FS1R_FSC18_Pos) /*!< 0x00040000 */ #define CAN_FS1R_FSC18 CAN_FS1R_FSC18_Msk /*!<Filter Scale Configuration bit 18 */ #define CAN_FS1R_FSC19_Pos (19U) #define CAN_FS1R_FSC19_Msk (0x1U << CAN_FS1R_FSC19_Pos) /*!< 0x00080000 */ #define CAN_FS1R_FSC19 CAN_FS1R_FSC19_Msk /*!<Filter Scale Configuration bit 19 */ #define CAN_FS1R_FSC20_Pos (20U) #define CAN_FS1R_FSC20_Msk (0x1U << CAN_FS1R_FSC20_Pos) /*!< 0x00100000 */ #define CAN_FS1R_FSC20 CAN_FS1R_FSC20_Msk /*!<Filter Scale Configuration bit 20 */ #define CAN_FS1R_FSC21_Pos (21U) #define CAN_FS1R_FSC21_Msk (0x1U << CAN_FS1R_FSC21_Pos) /*!< 0x00200000 */ #define CAN_FS1R_FSC21 CAN_FS1R_FSC21_Msk /*!<Filter Scale Configuration bit 21 */ #define CAN_FS1R_FSC22_Pos (22U) #define CAN_FS1R_FSC22_Msk (0x1U << CAN_FS1R_FSC22_Pos) /*!< 0x00400000 */ #define CAN_FS1R_FSC22 CAN_FS1R_FSC22_Msk /*!<Filter Scale Configuration bit 22 */ #define CAN_FS1R_FSC23_Pos (23U) #define CAN_FS1R_FSC23_Msk (0x1U << CAN_FS1R_FSC23_Pos) /*!< 0x00800000 */ #define CAN_FS1R_FSC23 CAN_FS1R_FSC23_Msk /*!<Filter Scale Configuration bit 23 */ #define CAN_FS1R_FSC24_Pos (24U) #define CAN_FS1R_FSC24_Msk (0x1U << CAN_FS1R_FSC24_Pos) /*!< 0x01000000 */ #define CAN_FS1R_FSC24 CAN_FS1R_FSC24_Msk /*!<Filter Scale Configuration bit 24 */ #define CAN_FS1R_FSC25_Pos (25U) #define CAN_FS1R_FSC25_Msk (0x1U << CAN_FS1R_FSC25_Pos) /*!< 0x02000000 */ #define CAN_FS1R_FSC25 CAN_FS1R_FSC25_Msk /*!<Filter Scale Configuration bit 25 */ #define CAN_FS1R_FSC26_Pos (26U) #define CAN_FS1R_FSC26_Msk (0x1U << CAN_FS1R_FSC26_Pos) /*!< 0x04000000 */ #define CAN_FS1R_FSC26 CAN_FS1R_FSC26_Msk /*!<Filter Scale Configuration bit 26 */ #define CAN_FS1R_FSC27_Pos (27U) #define CAN_FS1R_FSC27_Msk (0x1U << CAN_FS1R_FSC27_Pos) /*!< 0x08000000 */ #define CAN_FS1R_FSC27 CAN_FS1R_FSC27_Msk /*!<Filter Scale Configuration bit 27 */ /****************** Bit definition for CAN_FFA1R register *******************/ #define CAN_FFA1R_FFA_Pos (0U) #define CAN_FFA1R_FFA_Msk (0xFFFFFFFU << CAN_FFA1R_FFA_Pos) /*!< 0x0FFFFFFF */ #define CAN_FFA1R_FFA CAN_FFA1R_FFA_Msk /*!<Filter FIFO Assignment */ #define CAN_FFA1R_FFA0_Pos (0U) #define CAN_FFA1R_FFA0_Msk (0x1U << CAN_FFA1R_FFA0_Pos) /*!< 0x00000001 */ #define CAN_FFA1R_FFA0 CAN_FFA1R_FFA0_Msk /*!<Filter FIFO Assignment bit 0 */ #define CAN_FFA1R_FFA1_Pos (1U) #define CAN_FFA1R_FFA1_Msk (0x1U << CAN_FFA1R_FFA1_Pos) /*!< 0x00000002 */ #define CAN_FFA1R_FFA1 CAN_FFA1R_FFA1_Msk /*!<Filter FIFO Assignment bit 1 */ #define CAN_FFA1R_FFA2_Pos (2U) #define CAN_FFA1R_FFA2_Msk (0x1U << CAN_FFA1R_FFA2_Pos) /*!< 0x00000004 */ #define CAN_FFA1R_FFA2 CAN_FFA1R_FFA2_Msk /*!<Filter FIFO Assignment bit 2 */ #define CAN_FFA1R_FFA3_Pos (3U) #define CAN_FFA1R_FFA3_Msk (0x1U << CAN_FFA1R_FFA3_Pos) /*!< 0x00000008 */ #define CAN_FFA1R_FFA3 CAN_FFA1R_FFA3_Msk /*!<Filter FIFO Assignment bit 3 */ #define CAN_FFA1R_FFA4_Pos (4U) #define CAN_FFA1R_FFA4_Msk (0x1U << CAN_FFA1R_FFA4_Pos) /*!< 0x00000010 */ #define CAN_FFA1R_FFA4 CAN_FFA1R_FFA4_Msk /*!<Filter FIFO Assignment bit 4 */ #define CAN_FFA1R_FFA5_Pos (5U) #define CAN_FFA1R_FFA5_Msk (0x1U << CAN_FFA1R_FFA5_Pos) /*!< 0x00000020 */ #define CAN_FFA1R_FFA5 CAN_FFA1R_FFA5_Msk /*!<Filter FIFO Assignment bit 5 */ #define CAN_FFA1R_FFA6_Pos (6U) #define CAN_FFA1R_FFA6_Msk (0x1U << CAN_FFA1R_FFA6_Pos) /*!< 0x00000040 */ #define CAN_FFA1R_FFA6 CAN_FFA1R_FFA6_Msk /*!<Filter FIFO Assignment bit 6 */ #define CAN_FFA1R_FFA7_Pos (7U) #define CAN_FFA1R_FFA7_Msk (0x1U << CAN_FFA1R_FFA7_Pos) /*!< 0x00000080 */ #define CAN_FFA1R_FFA7 CAN_FFA1R_FFA7_Msk /*!<Filter FIFO Assignment bit 7 */ #define CAN_FFA1R_FFA8_Pos (8U) #define CAN_FFA1R_FFA8_Msk (0x1U << CAN_FFA1R_FFA8_Pos) /*!< 0x00000100 */ #define CAN_FFA1R_FFA8 CAN_FFA1R_FFA8_Msk /*!<Filter FIFO Assignment bit 8 */ #define CAN_FFA1R_FFA9_Pos (9U) #define CAN_FFA1R_FFA9_Msk (0x1U << CAN_FFA1R_FFA9_Pos) /*!< 0x00000200 */ #define CAN_FFA1R_FFA9 CAN_FFA1R_FFA9_Msk /*!<Filter FIFO Assignment bit 9 */ #define CAN_FFA1R_FFA10_Pos (10U) #define CAN_FFA1R_FFA10_Msk (0x1U << CAN_FFA1R_FFA10_Pos) /*!< 0x00000400 */ #define CAN_FFA1R_FFA10 CAN_FFA1R_FFA10_Msk /*!<Filter FIFO Assignment bit 10 */ #define CAN_FFA1R_FFA11_Pos (11U) #define CAN_FFA1R_FFA11_Msk (0x1U << CAN_FFA1R_FFA11_Pos) /*!< 0x00000800 */ #define CAN_FFA1R_FFA11 CAN_FFA1R_FFA11_Msk /*!<Filter FIFO Assignment bit 11 */ #define CAN_FFA1R_FFA12_Pos (12U) #define CAN_FFA1R_FFA12_Msk (0x1U << CAN_FFA1R_FFA12_Pos) /*!< 0x00001000 */ #define CAN_FFA1R_FFA12 CAN_FFA1R_FFA12_Msk /*!<Filter FIFO Assignment bit 12 */ #define CAN_FFA1R_FFA13_Pos (13U) #define CAN_FFA1R_FFA13_Msk (0x1U << CAN_FFA1R_FFA13_Pos) /*!< 0x00002000 */ #define CAN_FFA1R_FFA13 CAN_FFA1R_FFA13_Msk /*!<Filter FIFO Assignment bit 13 */ #define CAN_FFA1R_FFA14_Pos (14U) #define CAN_FFA1R_FFA14_Msk (0x1U << CAN_FFA1R_FFA14_Pos) /*!< 0x00004000 */ #define CAN_FFA1R_FFA14 CAN_FFA1R_FFA14_Msk /*!<Filter FIFO Assignment bit 14 */ #define CAN_FFA1R_FFA15_Pos (15U) #define CAN_FFA1R_FFA15_Msk (0x1U << CAN_FFA1R_FFA15_Pos) /*!< 0x00008000 */ #define CAN_FFA1R_FFA15 CAN_FFA1R_FFA15_Msk /*!<Filter FIFO Assignment bit 15 */ #define CAN_FFA1R_FFA16_Pos (16U) #define CAN_FFA1R_FFA16_Msk (0x1U << CAN_FFA1R_FFA16_Pos) /*!< 0x00010000 */ #define CAN_FFA1R_FFA16 CAN_FFA1R_FFA16_Msk /*!<Filter FIFO Assignment bit 16 */ #define CAN_FFA1R_FFA17_Pos (17U) #define CAN_FFA1R_FFA17_Msk (0x1U << CAN_FFA1R_FFA17_Pos) /*!< 0x00020000 */ #define CAN_FFA1R_FFA17 CAN_FFA1R_FFA17_Msk /*!<Filter FIFO Assignment bit 17 */ #define CAN_FFA1R_FFA18_Pos (18U) #define CAN_FFA1R_FFA18_Msk (0x1U << CAN_FFA1R_FFA18_Pos) /*!< 0x00040000 */ #define CAN_FFA1R_FFA18 CAN_FFA1R_FFA18_Msk /*!<Filter FIFO Assignment bit 18 */ #define CAN_FFA1R_FFA19_Pos (19U) #define CAN_FFA1R_FFA19_Msk (0x1U << CAN_FFA1R_FFA19_Pos) /*!< 0x00080000 */ #define CAN_FFA1R_FFA19 CAN_FFA1R_FFA19_Msk /*!<Filter FIFO Assignment bit 19 */ #define CAN_FFA1R_FFA20_Pos (20U) #define CAN_FFA1R_FFA20_Msk (0x1U << CAN_FFA1R_FFA20_Pos) /*!< 0x00100000 */ #define CAN_FFA1R_FFA20 CAN_FFA1R_FFA20_Msk /*!<Filter FIFO Assignment bit 20 */ #define CAN_FFA1R_FFA21_Pos (21U) #define CAN_FFA1R_FFA21_Msk (0x1U << CAN_FFA1R_FFA21_Pos) /*!< 0x00200000 */ #define CAN_FFA1R_FFA21 CAN_FFA1R_FFA21_Msk /*!<Filter FIFO Assignment bit 21 */ #define CAN_FFA1R_FFA22_Pos (22U) #define CAN_FFA1R_FFA22_Msk (0x1U << CAN_FFA1R_FFA22_Pos) /*!< 0x00400000 */ #define CAN_FFA1R_FFA22 CAN_FFA1R_FFA22_Msk /*!<Filter FIFO Assignment bit 22 */ #define CAN_FFA1R_FFA23_Pos (23U) #define CAN_FFA1R_FFA23_Msk (0x1U << CAN_FFA1R_FFA23_Pos) /*!< 0x00800000 */ #define CAN_FFA1R_FFA23 CAN_FFA1R_FFA23_Msk /*!<Filter FIFO Assignment bit 23 */ #define CAN_FFA1R_FFA24_Pos (24U) #define CAN_FFA1R_FFA24_Msk (0x1U << CAN_FFA1R_FFA24_Pos) /*!< 0x01000000 */ #define CAN_FFA1R_FFA24 CAN_FFA1R_FFA24_Msk /*!<Filter FIFO Assignment bit 24 */ #define CAN_FFA1R_FFA25_Pos (25U) #define CAN_FFA1R_FFA25_Msk (0x1U << CAN_FFA1R_FFA25_Pos) /*!< 0x02000000 */ #define CAN_FFA1R_FFA25 CAN_FFA1R_FFA25_Msk /*!<Filter FIFO Assignment bit 25 */ #define CAN_FFA1R_FFA26_Pos (26U) #define CAN_FFA1R_FFA26_Msk (0x1U << CAN_FFA1R_FFA26_Pos) /*!< 0x04000000 */ #define CAN_FFA1R_FFA26 CAN_FFA1R_FFA26_Msk /*!<Filter FIFO Assignment bit 26 */ #define CAN_FFA1R_FFA27_Pos (27U) #define CAN_FFA1R_FFA27_Msk (0x1U << CAN_FFA1R_FFA27_Pos) /*!< 0x08000000 */ #define CAN_FFA1R_FFA27 CAN_FFA1R_FFA27_Msk /*!<Filter FIFO Assignment bit 27 */ /******************* Bit definition for CAN_FA1R register *******************/ #define CAN_FA1R_FACT_Pos (0U) #define CAN_FA1R_FACT_Msk (0xFFFFFFFU << CAN_FA1R_FACT_Pos) /*!< 0x0FFFFFFF */ #define CAN_FA1R_FACT CAN_FA1R_FACT_Msk /*!<Filter Active */ #define CAN_FA1R_FACT0_Pos (0U) #define CAN_FA1R_FACT0_Msk (0x1U << CAN_FA1R_FACT0_Pos) /*!< 0x00000001 */ #define CAN_FA1R_FACT0 CAN_FA1R_FACT0_Msk /*!<Filter Active bit 0 */ #define CAN_FA1R_FACT1_Pos (1U) #define CAN_FA1R_FACT1_Msk (0x1U << CAN_FA1R_FACT1_Pos) /*!< 0x00000002 */ #define CAN_FA1R_FACT1 CAN_FA1R_FACT1_Msk /*!<Filter Active bit 1 */ #define CAN_FA1R_FACT2_Pos (2U) #define CAN_FA1R_FACT2_Msk (0x1U << CAN_FA1R_FACT2_Pos) /*!< 0x00000004 */ #define CAN_FA1R_FACT2 CAN_FA1R_FACT2_Msk /*!<Filter Active bit 2 */ #define CAN_FA1R_FACT3_Pos (3U) #define CAN_FA1R_FACT3_Msk (0x1U << CAN_FA1R_FACT3_Pos) /*!< 0x00000008 */ #define CAN_FA1R_FACT3 CAN_FA1R_FACT3_Msk /*!<Filter Active bit 3 */ #define CAN_FA1R_FACT4_Pos (4U) #define CAN_FA1R_FACT4_Msk (0x1U << CAN_FA1R_FACT4_Pos) /*!< 0x00000010 */ #define CAN_FA1R_FACT4 CAN_FA1R_FACT4_Msk /*!<Filter Active bit 4 */ #define CAN_FA1R_FACT5_Pos (5U) #define CAN_FA1R_FACT5_Msk (0x1U << CAN_FA1R_FACT5_Pos) /*!< 0x00000020 */ #define CAN_FA1R_FACT5 CAN_FA1R_FACT5_Msk /*!<Filter Active bit 5 */ #define CAN_FA1R_FACT6_Pos (6U) #define CAN_FA1R_FACT6_Msk (0x1U << CAN_FA1R_FACT6_Pos) /*!< 0x00000040 */ #define CAN_FA1R_FACT6 CAN_FA1R_FACT6_Msk /*!<Filter Active bit 6 */ #define CAN_FA1R_FACT7_Pos (7U) #define CAN_FA1R_FACT7_Msk (0x1U << CAN_FA1R_FACT7_Pos) /*!< 0x00000080 */ #define CAN_FA1R_FACT7 CAN_FA1R_FACT7_Msk /*!<Filter Active bit 7 */ #define CAN_FA1R_FACT8_Pos (8U) #define CAN_FA1R_FACT8_Msk (0x1U << CAN_FA1R_FACT8_Pos) /*!< 0x00000100 */ #define CAN_FA1R_FACT8 CAN_FA1R_FACT8_Msk /*!<Filter Active bit 8 */ #define CAN_FA1R_FACT9_Pos (9U) #define CAN_FA1R_FACT9_Msk (0x1U << CAN_FA1R_FACT9_Pos) /*!< 0x00000200 */ #define CAN_FA1R_FACT9 CAN_FA1R_FACT9_Msk /*!<Filter Active bit 9 */ #define CAN_FA1R_FACT10_Pos (10U) #define CAN_FA1R_FACT10_Msk (0x1U << CAN_FA1R_FACT10_Pos) /*!< 0x00000400 */ #define CAN_FA1R_FACT10 CAN_FA1R_FACT10_Msk /*!<Filter Active bit 10 */ #define CAN_FA1R_FACT11_Pos (11U) #define CAN_FA1R_FACT11_Msk (0x1U << CAN_FA1R_FACT11_Pos) /*!< 0x00000800 */ #define CAN_FA1R_FACT11 CAN_FA1R_FACT11_Msk /*!<Filter Active bit 11 */ #define CAN_FA1R_FACT12_Pos (12U) #define CAN_FA1R_FACT12_Msk (0x1U << CAN_FA1R_FACT12_Pos) /*!< 0x00001000 */ #define CAN_FA1R_FACT12 CAN_FA1R_FACT12_Msk /*!<Filter Active bit 12 */ #define CAN_FA1R_FACT13_Pos (13U) #define CAN_FA1R_FACT13_Msk (0x1U << CAN_FA1R_FACT13_Pos) /*!< 0x00002000 */ #define CAN_FA1R_FACT13 CAN_FA1R_FACT13_Msk /*!<Filter Active bit 13 */ #define CAN_FA1R_FACT14_Pos (14U) #define CAN_FA1R_FACT14_Msk (0x1U << CAN_FA1R_FACT14_Pos) /*!< 0x00004000 */ #define CAN_FA1R_FACT14 CAN_FA1R_FACT14_Msk /*!<Filter Active bit 14 */ #define CAN_FA1R_FACT15_Pos (15U) #define CAN_FA1R_FACT15_Msk (0x1U << CAN_FA1R_FACT15_Pos) /*!< 0x00008000 */ #define CAN_FA1R_FACT15 CAN_FA1R_FACT15_Msk /*!<Filter Active bit 15 */ #define CAN_FA1R_FACT16_Pos (16U) #define CAN_FA1R_FACT16_Msk (0x1U << CAN_FA1R_FACT16_Pos) /*!< 0x00010000 */ #define CAN_FA1R_FACT16 CAN_FA1R_FACT16_Msk /*!<Filter Active bit 16 */ #define CAN_FA1R_FACT17_Pos (17U) #define CAN_FA1R_FACT17_Msk (0x1U << CAN_FA1R_FACT17_Pos) /*!< 0x00020000 */ #define CAN_FA1R_FACT17 CAN_FA1R_FACT17_Msk /*!<Filter Active bit 17 */ #define CAN_FA1R_FACT18_Pos (18U) #define CAN_FA1R_FACT18_Msk (0x1U << CAN_FA1R_FACT18_Pos) /*!< 0x00040000 */ #define CAN_FA1R_FACT18 CAN_FA1R_FACT18_Msk /*!<Filter Active bit 18 */ #define CAN_FA1R_FACT19_Pos (19U) #define CAN_FA1R_FACT19_Msk (0x1U << CAN_FA1R_FACT19_Pos) /*!< 0x00080000 */ #define CAN_FA1R_FACT19 CAN_FA1R_FACT19_Msk /*!<Filter Active bit 19 */ #define CAN_FA1R_FACT20_Pos (20U) #define CAN_FA1R_FACT20_Msk (0x1U << CAN_FA1R_FACT20_Pos) /*!< 0x00100000 */ #define CAN_FA1R_FACT20 CAN_FA1R_FACT20_Msk /*!<Filter Active bit 20 */ #define CAN_FA1R_FACT21_Pos (21U) #define CAN_FA1R_FACT21_Msk (0x1U << CAN_FA1R_FACT21_Pos) /*!< 0x00200000 */ #define CAN_FA1R_FACT21 CAN_FA1R_FACT21_Msk /*!<Filter Active bit 21 */ #define CAN_FA1R_FACT22_Pos (22U) #define CAN_FA1R_FACT22_Msk (0x1U << CAN_FA1R_FACT22_Pos) /*!< 0x00400000 */ #define CAN_FA1R_FACT22 CAN_FA1R_FACT22_Msk /*!<Filter Active bit 22 */ #define CAN_FA1R_FACT23_Pos (23U) #define CAN_FA1R_FACT23_Msk (0x1U << CAN_FA1R_FACT23_Pos) /*!< 0x00800000 */ #define CAN_FA1R_FACT23 CAN_FA1R_FACT23_Msk /*!<Filter Active bit 23 */ #define CAN_FA1R_FACT24_Pos (24U) #define CAN_FA1R_FACT24_Msk (0x1U << CAN_FA1R_FACT24_Pos) /*!< 0x01000000 */ #define CAN_FA1R_FACT24 CAN_FA1R_FACT24_Msk /*!<Filter Active bit 24 */ #define CAN_FA1R_FACT25_Pos (25U) #define CAN_FA1R_FACT25_Msk (0x1U << CAN_FA1R_FACT25_Pos) /*!< 0x02000000 */ #define CAN_FA1R_FACT25 CAN_FA1R_FACT25_Msk /*!<Filter Active bit 25 */ #define CAN_FA1R_FACT26_Pos (26U) #define CAN_FA1R_FACT26_Msk (0x1U << CAN_FA1R_FACT26_Pos) /*!< 0x04000000 */ #define CAN_FA1R_FACT26 CAN_FA1R_FACT26_Msk /*!<Filter Active bit 26 */ #define CAN_FA1R_FACT27_Pos (27U) #define CAN_FA1R_FACT27_Msk (0x1U << CAN_FA1R_FACT27_Pos) /*!< 0x08000000 */ #define CAN_FA1R_FACT27 CAN_FA1R_FACT27_Msk /*!<Filter Active bit 27 */ /******************* Bit definition for CAN_F0R1 register *******************/ #define CAN_F0R1_FB0_Pos (0U) #define CAN_F0R1_FB0_Msk (0x1U << CAN_F0R1_FB0_Pos) /*!< 0x00000001 */ #define CAN_F0R1_FB0 CAN_F0R1_FB0_Msk /*!<Filter bit 0 */ #define CAN_F0R1_FB1_Pos (1U) #define CAN_F0R1_FB1_Msk (0x1U << CAN_F0R1_FB1_Pos) /*!< 0x00000002 */ #define CAN_F0R1_FB1 CAN_F0R1_FB1_Msk /*!<Filter bit 1 */ #define CAN_F0R1_FB2_Pos (2U) #define CAN_F0R1_FB2_Msk (0x1U << CAN_F0R1_FB2_Pos) /*!< 0x00000004 */ #define CAN_F0R1_FB2 CAN_F0R1_FB2_Msk /*!<Filter bit 2 */ #define CAN_F0R1_FB3_Pos (3U) #define CAN_F0R1_FB3_Msk (0x1U << CAN_F0R1_FB3_Pos) /*!< 0x00000008 */ #define CAN_F0R1_FB3 CAN_F0R1_FB3_Msk /*!<Filter bit 3 */ #define CAN_F0R1_FB4_Pos (4U) #define CAN_F0R1_FB4_Msk (0x1U << CAN_F0R1_FB4_Pos) /*!< 0x00000010 */ #define CAN_F0R1_FB4 CAN_F0R1_FB4_Msk /*!<Filter bit 4 */ #define CAN_F0R1_FB5_Pos (5U) #define CAN_F0R1_FB5_Msk (0x1U << CAN_F0R1_FB5_Pos) /*!< 0x00000020 */ #define CAN_F0R1_FB5 CAN_F0R1_FB5_Msk /*!<Filter bit 5 */ #define CAN_F0R1_FB6_Pos (6U) #define CAN_F0R1_FB6_Msk (0x1U << CAN_F0R1_FB6_Pos) /*!< 0x00000040 */ #define CAN_F0R1_FB6 CAN_F0R1_FB6_Msk /*!<Filter bit 6 */ #define CAN_F0R1_FB7_Pos (7U) #define CAN_F0R1_FB7_Msk (0x1U << CAN_F0R1_FB7_Pos) /*!< 0x00000080 */ #define CAN_F0R1_FB7 CAN_F0R1_FB7_Msk /*!<Filter bit 7 */ #define CAN_F0R1_FB8_Pos (8U) #define CAN_F0R1_FB8_Msk (0x1U << CAN_F0R1_FB8_Pos) /*!< 0x00000100 */ #define CAN_F0R1_FB8 CAN_F0R1_FB8_Msk /*!<Filter bit 8 */ #define CAN_F0R1_FB9_Pos (9U) #define CAN_F0R1_FB9_Msk (0x1U << CAN_F0R1_FB9_Pos) /*!< 0x00000200 */ #define CAN_F0R1_FB9 CAN_F0R1_FB9_Msk /*!<Filter bit 9 */ #define CAN_F0R1_FB10_Pos (10U) #define CAN_F0R1_FB10_Msk (0x1U << CAN_F0R1_FB10_Pos) /*!< 0x00000400 */ #define CAN_F0R1_FB10 CAN_F0R1_FB10_Msk /*!<Filter bit 10 */ #define CAN_F0R1_FB11_Pos (11U) #define CAN_F0R1_FB11_Msk (0x1U << CAN_F0R1_FB11_Pos) /*!< 0x00000800 */ #define CAN_F0R1_FB11 CAN_F0R1_FB11_Msk /*!<Filter bit 11 */ #define CAN_F0R1_FB12_Pos (12U) #define CAN_F0R1_FB12_Msk (0x1U << CAN_F0R1_FB12_Pos) /*!< 0x00001000 */ #define CAN_F0R1_FB12 CAN_F0R1_FB12_Msk /*!<Filter bit 12 */ #define CAN_F0R1_FB13_Pos (13U) #define CAN_F0R1_FB13_Msk (0x1U << CAN_F0R1_FB13_Pos) /*!< 0x00002000 */ #define CAN_F0R1_FB13 CAN_F0R1_FB13_Msk /*!<Filter bit 13 */ #define CAN_F0R1_FB14_Pos (14U) #define CAN_F0R1_FB14_Msk (0x1U << CAN_F0R1_FB14_Pos) /*!< 0x00004000 */ #define CAN_F0R1_FB14 CAN_F0R1_FB14_Msk /*!<Filter bit 14 */ #define CAN_F0R1_FB15_Pos (15U) #define CAN_F0R1_FB15_Msk (0x1U << CAN_F0R1_FB15_Pos) /*!< 0x00008000 */ #define CAN_F0R1_FB15 CAN_F0R1_FB15_Msk /*!<Filter bit 15 */ #define CAN_F0R1_FB16_Pos (16U) #define CAN_F0R1_FB16_Msk (0x1U << CAN_F0R1_FB16_Pos) /*!< 0x00010000 */ #define CAN_F0R1_FB16 CAN_F0R1_FB16_Msk /*!<Filter bit 16 */ #define CAN_F0R1_FB17_Pos (17U) #define CAN_F0R1_FB17_Msk (0x1U << CAN_F0R1_FB17_Pos) /*!< 0x00020000 */ #define CAN_F0R1_FB17 CAN_F0R1_FB17_Msk /*!<Filter bit 17 */ #define CAN_F0R1_FB18_Pos (18U) #define CAN_F0R1_FB18_Msk (0x1U << CAN_F0R1_FB18_Pos) /*!< 0x00040000 */ #define CAN_F0R1_FB18 CAN_F0R1_FB18_Msk /*!<Filter bit 18 */ #define CAN_F0R1_FB19_Pos (19U) #define CAN_F0R1_FB19_Msk (0x1U << CAN_F0R1_FB19_Pos) /*!< 0x00080000 */ #define CAN_F0R1_FB19 CAN_F0R1_FB19_Msk /*!<Filter bit 19 */ #define CAN_F0R1_FB20_Pos (20U) #define CAN_F0R1_FB20_Msk (0x1U << CAN_F0R1_FB20_Pos) /*!< 0x00100000 */ #define CAN_F0R1_FB20 CAN_F0R1_FB20_Msk /*!<Filter bit 20 */ #define CAN_F0R1_FB21_Pos (21U) #define CAN_F0R1_FB21_Msk (0x1U << CAN_F0R1_FB21_Pos) /*!< 0x00200000 */ #define CAN_F0R1_FB21 CAN_F0R1_FB21_Msk /*!<Filter bit 21 */ #define CAN_F0R1_FB22_Pos (22U) #define CAN_F0R1_FB22_Msk (0x1U << CAN_F0R1_FB22_Pos) /*!< 0x00400000 */ #define CAN_F0R1_FB22 CAN_F0R1_FB22_Msk /*!<Filter bit 22 */ #define CAN_F0R1_FB23_Pos (23U) #define CAN_F0R1_FB23_Msk (0x1U << CAN_F0R1_FB23_Pos) /*!< 0x00800000 */ #define CAN_F0R1_FB23 CAN_F0R1_FB23_Msk /*!<Filter bit 23 */ #define CAN_F0R1_FB24_Pos (24U) #define CAN_F0R1_FB24_Msk (0x1U << CAN_F0R1_FB24_Pos) /*!< 0x01000000 */ #define CAN_F0R1_FB24 CAN_F0R1_FB24_Msk /*!<Filter bit 24 */ #define CAN_F0R1_FB25_Pos (25U) #define CAN_F0R1_FB25_Msk (0x1U << CAN_F0R1_FB25_Pos) /*!< 0x02000000 */ #define CAN_F0R1_FB25 CAN_F0R1_FB25_Msk /*!<Filter bit 25 */ #define CAN_F0R1_FB26_Pos (26U) #define CAN_F0R1_FB26_Msk (0x1U << CAN_F0R1_FB26_Pos) /*!< 0x04000000 */ #define CAN_F0R1_FB26 CAN_F0R1_FB26_Msk /*!<Filter bit 26 */ #define CAN_F0R1_FB27_Pos (27U) #define CAN_F0R1_FB27_Msk (0x1U << CAN_F0R1_FB27_Pos) /*!< 0x08000000 */ #define CAN_F0R1_FB27 CAN_F0R1_FB27_Msk /*!<Filter bit 27 */ #define CAN_F0R1_FB28_Pos (28U) #define CAN_F0R1_FB28_Msk (0x1U << CAN_F0R1_FB28_Pos) /*!< 0x10000000 */ #define CAN_F0R1_FB28 CAN_F0R1_FB28_Msk /*!<Filter bit 28 */ #define CAN_F0R1_FB29_Pos (29U) #define CAN_F0R1_FB29_Msk (0x1U << CAN_F0R1_FB29_Pos) /*!< 0x20000000 */ #define CAN_F0R1_FB29 CAN_F0R1_FB29_Msk /*!<Filter bit 29 */ #define CAN_F0R1_FB30_Pos (30U) #define CAN_F0R1_FB30_Msk (0x1U << CAN_F0R1_FB30_Pos) /*!< 0x40000000 */ #define CAN_F0R1_FB30 CAN_F0R1_FB30_Msk /*!<Filter bit 30 */ #define CAN_F0R1_FB31_Pos (31U) #define CAN_F0R1_FB31_Msk (0x1U << CAN_F0R1_FB31_Pos) /*!< 0x80000000 */ #define CAN_F0R1_FB31 CAN_F0R1_FB31_Msk /*!<Filter bit 31 */ /******************* Bit definition for CAN_F1R1 register *******************/ #define CAN_F1R1_FB0_Pos (0U) #define CAN_F1R1_FB0_Msk (0x1U << CAN_F1R1_FB0_Pos) /*!< 0x00000001 */ #define CAN_F1R1_FB0 CAN_F1R1_FB0_Msk /*!<Filter bit 0 */ #define CAN_F1R1_FB1_Pos (1U) #define CAN_F1R1_FB1_Msk (0x1U << CAN_F1R1_FB1_Pos) /*!< 0x00000002 */ #define CAN_F1R1_FB1 CAN_F1R1_FB1_Msk /*!<Filter bit 1 */ #define CAN_F1R1_FB2_Pos (2U) #define CAN_F1R1_FB2_Msk (0x1U << CAN_F1R1_FB2_Pos) /*!< 0x00000004 */ #define CAN_F1R1_FB2 CAN_F1R1_FB2_Msk /*!<Filter bit 2 */ #define CAN_F1R1_FB3_Pos (3U) #define CAN_F1R1_FB3_Msk (0x1U << CAN_F1R1_FB3_Pos) /*!< 0x00000008 */ #define CAN_F1R1_FB3 CAN_F1R1_FB3_Msk /*!<Filter bit 3 */ #define CAN_F1R1_FB4_Pos (4U) #define CAN_F1R1_FB4_Msk (0x1U << CAN_F1R1_FB4_Pos) /*!< 0x00000010 */ #define CAN_F1R1_FB4 CAN_F1R1_FB4_Msk /*!<Filter bit 4 */ #define CAN_F1R1_FB5_Pos (5U) #define CAN_F1R1_FB5_Msk (0x1U << CAN_F1R1_FB5_Pos) /*!< 0x00000020 */ #define CAN_F1R1_FB5 CAN_F1R1_FB5_Msk /*!<Filter bit 5 */ #define CAN_F1R1_FB6_Pos (6U) #define CAN_F1R1_FB6_Msk (0x1U << CAN_F1R1_FB6_Pos) /*!< 0x00000040 */ #define CAN_F1R1_FB6 CAN_F1R1_FB6_Msk /*!<Filter bit 6 */ #define CAN_F1R1_FB7_Pos (7U) #define CAN_F1R1_FB7_Msk (0x1U << CAN_F1R1_FB7_Pos) /*!< 0x00000080 */ #define CAN_F1R1_FB7 CAN_F1R1_FB7_Msk /*!<Filter bit 7 */ #define CAN_F1R1_FB8_Pos (8U) #define CAN_F1R1_FB8_Msk (0x1U << CAN_F1R1_FB8_Pos) /*!< 0x00000100 */ #define CAN_F1R1_FB8 CAN_F1R1_FB8_Msk /*!<Filter bit 8 */ #define CAN_F1R1_FB9_Pos (9U) #define CAN_F1R1_FB9_Msk (0x1U << CAN_F1R1_FB9_Pos) /*!< 0x00000200 */ #define CAN_F1R1_FB9 CAN_F1R1_FB9_Msk /*!<Filter bit 9 */ #define CAN_F1R1_FB10_Pos (10U) #define CAN_F1R1_FB10_Msk (0x1U << CAN_F1R1_FB10_Pos) /*!< 0x00000400 */ #define CAN_F1R1_FB10 CAN_F1R1_FB10_Msk /*!<Filter bit 10 */ #define CAN_F1R1_FB11_Pos (11U) #define CAN_F1R1_FB11_Msk (0x1U << CAN_F1R1_FB11_Pos) /*!< 0x00000800 */ #define CAN_F1R1_FB11 CAN_F1R1_FB11_Msk /*!<Filter bit 11 */ #define CAN_F1R1_FB12_Pos (12U) #define CAN_F1R1_FB12_Msk (0x1U << CAN_F1R1_FB12_Pos) /*!< 0x00001000 */ #define CAN_F1R1_FB12 CAN_F1R1_FB12_Msk /*!<Filter bit 12 */ #define CAN_F1R1_FB13_Pos (13U) #define CAN_F1R1_FB13_Msk (0x1U << CAN_F1R1_FB13_Pos) /*!< 0x00002000 */ #define CAN_F1R1_FB13 CAN_F1R1_FB13_Msk /*!<Filter bit 13 */ #define CAN_F1R1_FB14_Pos (14U) #define CAN_F1R1_FB14_Msk (0x1U << CAN_F1R1_FB14_Pos) /*!< 0x00004000 */ #define CAN_F1R1_FB14 CAN_F1R1_FB14_Msk /*!<Filter bit 14 */ #define CAN_F1R1_FB15_Pos (15U) #define CAN_F1R1_FB15_Msk (0x1U << CAN_F1R1_FB15_Pos) /*!< 0x00008000 */ #define CAN_F1R1_FB15 CAN_F1R1_FB15_Msk /*!<Filter bit 15 */ #define CAN_F1R1_FB16_Pos (16U) #define CAN_F1R1_FB16_Msk (0x1U << CAN_F1R1_FB16_Pos) /*!< 0x00010000 */ #define CAN_F1R1_FB16 CAN_F1R1_FB16_Msk /*!<Filter bit 16 */ #define CAN_F1R1_FB17_Pos (17U) #define CAN_F1R1_FB17_Msk (0x1U << CAN_F1R1_FB17_Pos) /*!< 0x00020000 */ #define CAN_F1R1_FB17 CAN_F1R1_FB17_Msk /*!<Filter bit 17 */ #define CAN_F1R1_FB18_Pos (18U) #define CAN_F1R1_FB18_Msk (0x1U << CAN_F1R1_FB18_Pos) /*!< 0x00040000 */ #define CAN_F1R1_FB18 CAN_F1R1_FB18_Msk /*!<Filter bit 18 */ #define CAN_F1R1_FB19_Pos (19U) #define CAN_F1R1_FB19_Msk (0x1U << CAN_F1R1_FB19_Pos) /*!< 0x00080000 */ #define CAN_F1R1_FB19 CAN_F1R1_FB19_Msk /*!<Filter bit 19 */ #define CAN_F1R1_FB20_Pos (20U) #define CAN_F1R1_FB20_Msk (0x1U << CAN_F1R1_FB20_Pos) /*!< 0x00100000 */ #define CAN_F1R1_FB20 CAN_F1R1_FB20_Msk /*!<Filter bit 20 */ #define CAN_F1R1_FB21_Pos (21U) #define CAN_F1R1_FB21_Msk (0x1U << CAN_F1R1_FB21_Pos) /*!< 0x00200000 */ #define CAN_F1R1_FB21 CAN_F1R1_FB21_Msk /*!<Filter bit 21 */ #define CAN_F1R1_FB22_Pos (22U) #define CAN_F1R1_FB22_Msk (0x1U << CAN_F1R1_FB22_Pos) /*!< 0x00400000 */ #define CAN_F1R1_FB22 CAN_F1R1_FB22_Msk /*!<Filter bit 22 */ #define CAN_F1R1_FB23_Pos (23U) #define CAN_F1R1_FB23_Msk (0x1U << CAN_F1R1_FB23_Pos) /*!< 0x00800000 */ #define CAN_F1R1_FB23 CAN_F1R1_FB23_Msk /*!<Filter bit 23 */ #define CAN_F1R1_FB24_Pos (24U) #define CAN_F1R1_FB24_Msk (0x1U << CAN_F1R1_FB24_Pos) /*!< 0x01000000 */ #define CAN_F1R1_FB24 CAN_F1R1_FB24_Msk /*!<Filter bit 24 */ #define CAN_F1R1_FB25_Pos (25U) #define CAN_F1R1_FB25_Msk (0x1U << CAN_F1R1_FB25_Pos) /*!< 0x02000000 */ #define CAN_F1R1_FB25 CAN_F1R1_FB25_Msk /*!<Filter bit 25 */ #define CAN_F1R1_FB26_Pos (26U) #define CAN_F1R1_FB26_Msk (0x1U << CAN_F1R1_FB26_Pos) /*!< 0x04000000 */ #define CAN_F1R1_FB26 CAN_F1R1_FB26_Msk /*!<Filter bit 26 */ #define CAN_F1R1_FB27_Pos (27U) #define CAN_F1R1_FB27_Msk (0x1U << CAN_F1R1_FB27_Pos) /*!< 0x08000000 */ #define CAN_F1R1_FB27 CAN_F1R1_FB27_Msk /*!<Filter bit 27 */ #define CAN_F1R1_FB28_Pos (28U) #define CAN_F1R1_FB28_Msk (0x1U << CAN_F1R1_FB28_Pos) /*!< 0x10000000 */ #define CAN_F1R1_FB28 CAN_F1R1_FB28_Msk /*!<Filter bit 28 */ #define CAN_F1R1_FB29_Pos (29U) #define CAN_F1R1_FB29_Msk (0x1U << CAN_F1R1_FB29_Pos) /*!< 0x20000000 */ #define CAN_F1R1_FB29 CAN_F1R1_FB29_Msk /*!<Filter bit 29 */ #define CAN_F1R1_FB30_Pos (30U) #define CAN_F1R1_FB30_Msk (0x1U << CAN_F1R1_FB30_Pos) /*!< 0x40000000 */ #define CAN_F1R1_FB30 CAN_F1R1_FB30_Msk /*!<Filter bit 30 */ #define CAN_F1R1_FB31_Pos (31U) #define CAN_F1R1_FB31_Msk (0x1U << CAN_F1R1_FB31_Pos) /*!< 0x80000000 */ #define CAN_F1R1_FB31 CAN_F1R1_FB31_Msk /*!<Filter bit 31 */ /******************* Bit definition for CAN_F2R1 register *******************/ #define CAN_F2R1_FB0_Pos (0U) #define CAN_F2R1_FB0_Msk (0x1U << CAN_F2R1_FB0_Pos) /*!< 0x00000001 */ #define CAN_F2R1_FB0 CAN_F2R1_FB0_Msk /*!<Filter bit 0 */ #define CAN_F2R1_FB1_Pos (1U) #define CAN_F2R1_FB1_Msk (0x1U << CAN_F2R1_FB1_Pos) /*!< 0x00000002 */ #define CAN_F2R1_FB1 CAN_F2R1_FB1_Msk /*!<Filter bit 1 */ #define CAN_F2R1_FB2_Pos (2U) #define CAN_F2R1_FB2_Msk (0x1U << CAN_F2R1_FB2_Pos) /*!< 0x00000004 */ #define CAN_F2R1_FB2 CAN_F2R1_FB2_Msk /*!<Filter bit 2 */ #define CAN_F2R1_FB3_Pos (3U) #define CAN_F2R1_FB3_Msk (0x1U << CAN_F2R1_FB3_Pos) /*!< 0x00000008 */ #define CAN_F2R1_FB3 CAN_F2R1_FB3_Msk /*!<Filter bit 3 */ #define CAN_F2R1_FB4_Pos (4U) #define CAN_F2R1_FB4_Msk (0x1U << CAN_F2R1_FB4_Pos) /*!< 0x00000010 */ #define CAN_F2R1_FB4 CAN_F2R1_FB4_Msk /*!<Filter bit 4 */ #define CAN_F2R1_FB5_Pos (5U) #define CAN_F2R1_FB5_Msk (0x1U << CAN_F2R1_FB5_Pos) /*!< 0x00000020 */ #define CAN_F2R1_FB5 CAN_F2R1_FB5_Msk /*!<Filter bit 5 */ #define CAN_F2R1_FB6_Pos (6U) #define CAN_F2R1_FB6_Msk (0x1U << CAN_F2R1_FB6_Pos) /*!< 0x00000040 */ #define CAN_F2R1_FB6 CAN_F2R1_FB6_Msk /*!<Filter bit 6 */ #define CAN_F2R1_FB7_Pos (7U) #define CAN_F2R1_FB7_Msk (0x1U << CAN_F2R1_FB7_Pos) /*!< 0x00000080 */ #define CAN_F2R1_FB7 CAN_F2R1_FB7_Msk /*!<Filter bit 7 */ #define CAN_F2R1_FB8_Pos (8U) #define CAN_F2R1_FB8_Msk (0x1U << CAN_F2R1_FB8_Pos) /*!< 0x00000100 */ #define CAN_F2R1_FB8 CAN_F2R1_FB8_Msk /*!<Filter bit 8 */ #define CAN_F2R1_FB9_Pos (9U) #define CAN_F2R1_FB9_Msk (0x1U << CAN_F2R1_FB9_Pos) /*!< 0x00000200 */ #define CAN_F2R1_FB9 CAN_F2R1_FB9_Msk /*!<Filter bit 9 */ #define CAN_F2R1_FB10_Pos (10U) #define CAN_F2R1_FB10_Msk (0x1U << CAN_F2R1_FB10_Pos) /*!< 0x00000400 */ #define CAN_F2R1_FB10 CAN_F2R1_FB10_Msk /*!<Filter bit 10 */ #define CAN_F2R1_FB11_Pos (11U) #define CAN_F2R1_FB11_Msk (0x1U << CAN_F2R1_FB11_Pos) /*!< 0x00000800 */ #define CAN_F2R1_FB11 CAN_F2R1_FB11_Msk /*!<Filter bit 11 */ #define CAN_F2R1_FB12_Pos (12U) #define CAN_F2R1_FB12_Msk (0x1U << CAN_F2R1_FB12_Pos) /*!< 0x00001000 */ #define CAN_F2R1_FB12 CAN_F2R1_FB12_Msk /*!<Filter bit 12 */ #define CAN_F2R1_FB13_Pos (13U) #define CAN_F2R1_FB13_Msk (0x1U << CAN_F2R1_FB13_Pos) /*!< 0x00002000 */ #define CAN_F2R1_FB13 CAN_F2R1_FB13_Msk /*!<Filter bit 13 */ #define CAN_F2R1_FB14_Pos (14U) #define CAN_F2R1_FB14_Msk (0x1U << CAN_F2R1_FB14_Pos) /*!< 0x00004000 */ #define CAN_F2R1_FB14 CAN_F2R1_FB14_Msk /*!<Filter bit 14 */ #define CAN_F2R1_FB15_Pos (15U) #define CAN_F2R1_FB15_Msk (0x1U << CAN_F2R1_FB15_Pos) /*!< 0x00008000 */ #define CAN_F2R1_FB15 CAN_F2R1_FB15_Msk /*!<Filter bit 15 */ #define CAN_F2R1_FB16_Pos (16U) #define CAN_F2R1_FB16_Msk (0x1U << CAN_F2R1_FB16_Pos) /*!< 0x00010000 */ #define CAN_F2R1_FB16 CAN_F2R1_FB16_Msk /*!<Filter bit 16 */ #define CAN_F2R1_FB17_Pos (17U) #define CAN_F2R1_FB17_Msk (0x1U << CAN_F2R1_FB17_Pos) /*!< 0x00020000 */ #define CAN_F2R1_FB17 CAN_F2R1_FB17_Msk /*!<Filter bit 17 */ #define CAN_F2R1_FB18_Pos (18U) #define CAN_F2R1_FB18_Msk (0x1U << CAN_F2R1_FB18_Pos) /*!< 0x00040000 */ #define CAN_F2R1_FB18 CAN_F2R1_FB18_Msk /*!<Filter bit 18 */ #define CAN_F2R1_FB19_Pos (19U) #define CAN_F2R1_FB19_Msk (0x1U << CAN_F2R1_FB19_Pos) /*!< 0x00080000 */ #define CAN_F2R1_FB19 CAN_F2R1_FB19_Msk /*!<Filter bit 19 */ #define CAN_F2R1_FB20_Pos (20U) #define CAN_F2R1_FB20_Msk (0x1U << CAN_F2R1_FB20_Pos) /*!< 0x00100000 */ #define CAN_F2R1_FB20 CAN_F2R1_FB20_Msk /*!<Filter bit 20 */ #define CAN_F2R1_FB21_Pos (21U) #define CAN_F2R1_FB21_Msk (0x1U << CAN_F2R1_FB21_Pos) /*!< 0x00200000 */ #define CAN_F2R1_FB21 CAN_F2R1_FB21_Msk /*!<Filter bit 21 */ #define CAN_F2R1_FB22_Pos (22U) #define CAN_F2R1_FB22_Msk (0x1U << CAN_F2R1_FB22_Pos) /*!< 0x00400000 */ #define CAN_F2R1_FB22 CAN_F2R1_FB22_Msk /*!<Filter bit 22 */ #define CAN_F2R1_FB23_Pos (23U) #define CAN_F2R1_FB23_Msk (0x1U << CAN_F2R1_FB23_Pos) /*!< 0x00800000 */ #define CAN_F2R1_FB23 CAN_F2R1_FB23_Msk /*!<Filter bit 23 */ #define CAN_F2R1_FB24_Pos (24U) #define CAN_F2R1_FB24_Msk (0x1U << CAN_F2R1_FB24_Pos) /*!< 0x01000000 */ #define CAN_F2R1_FB24 CAN_F2R1_FB24_Msk /*!<Filter bit 24 */ #define CAN_F2R1_FB25_Pos (25U) #define CAN_F2R1_FB25_Msk (0x1U << CAN_F2R1_FB25_Pos) /*!< 0x02000000 */ #define CAN_F2R1_FB25 CAN_F2R1_FB25_Msk /*!<Filter bit 25 */ #define CAN_F2R1_FB26_Pos (26U) #define CAN_F2R1_FB26_Msk (0x1U << CAN_F2R1_FB26_Pos) /*!< 0x04000000 */ #define CAN_F2R1_FB26 CAN_F2R1_FB26_Msk /*!<Filter bit 26 */ #define CAN_F2R1_FB27_Pos (27U) #define CAN_F2R1_FB27_Msk (0x1U << CAN_F2R1_FB27_Pos) /*!< 0x08000000 */ #define CAN_F2R1_FB27 CAN_F2R1_FB27_Msk /*!<Filter bit 27 */ #define CAN_F2R1_FB28_Pos (28U) #define CAN_F2R1_FB28_Msk (0x1U << CAN_F2R1_FB28_Pos) /*!< 0x10000000 */ #define CAN_F2R1_FB28 CAN_F2R1_FB28_Msk /*!<Filter bit 28 */ #define CAN_F2R1_FB29_Pos (29U) #define CAN_F2R1_FB29_Msk (0x1U << CAN_F2R1_FB29_Pos) /*!< 0x20000000 */ #define CAN_F2R1_FB29 CAN_F2R1_FB29_Msk /*!<Filter bit 29 */ #define CAN_F2R1_FB30_Pos (30U) #define CAN_F2R1_FB30_Msk (0x1U << CAN_F2R1_FB30_Pos) /*!< 0x40000000 */ #define CAN_F2R1_FB30 CAN_F2R1_FB30_Msk /*!<Filter bit 30 */ #define CAN_F2R1_FB31_Pos (31U) #define CAN_F2R1_FB31_Msk (0x1U << CAN_F2R1_FB31_Pos) /*!< 0x80000000 */ #define CAN_F2R1_FB31 CAN_F2R1_FB31_Msk /*!<Filter bit 31 */ /******************* Bit definition for CAN_F3R1 register *******************/ #define CAN_F3R1_FB0_Pos (0U) #define CAN_F3R1_FB0_Msk (0x1U << CAN_F3R1_FB0_Pos) /*!< 0x00000001 */ #define CAN_F3R1_FB0 CAN_F3R1_FB0_Msk /*!<Filter bit 0 */ #define CAN_F3R1_FB1_Pos (1U) #define CAN_F3R1_FB1_Msk (0x1U << CAN_F3R1_FB1_Pos) /*!< 0x00000002 */ #define CAN_F3R1_FB1 CAN_F3R1_FB1_Msk /*!<Filter bit 1 */ #define CAN_F3R1_FB2_Pos (2U) #define CAN_F3R1_FB2_Msk (0x1U << CAN_F3R1_FB2_Pos) /*!< 0x00000004 */ #define CAN_F3R1_FB2 CAN_F3R1_FB2_Msk /*!<Filter bit 2 */ #define CAN_F3R1_FB3_Pos (3U) #define CAN_F3R1_FB3_Msk (0x1U << CAN_F3R1_FB3_Pos) /*!< 0x00000008 */ #define CAN_F3R1_FB3 CAN_F3R1_FB3_Msk /*!<Filter bit 3 */ #define CAN_F3R1_FB4_Pos (4U) #define CAN_F3R1_FB4_Msk (0x1U << CAN_F3R1_FB4_Pos) /*!< 0x00000010 */ #define CAN_F3R1_FB4 CAN_F3R1_FB4_Msk /*!<Filter bit 4 */ #define CAN_F3R1_FB5_Pos (5U) #define CAN_F3R1_FB5_Msk (0x1U << CAN_F3R1_FB5_Pos) /*!< 0x00000020 */ #define CAN_F3R1_FB5 CAN_F3R1_FB5_Msk /*!<Filter bit 5 */ #define CAN_F3R1_FB6_Pos (6U) #define CAN_F3R1_FB6_Msk (0x1U << CAN_F3R1_FB6_Pos) /*!< 0x00000040 */ #define CAN_F3R1_FB6 CAN_F3R1_FB6_Msk /*!<Filter bit 6 */ #define CAN_F3R1_FB7_Pos (7U) #define CAN_F3R1_FB7_Msk (0x1U << CAN_F3R1_FB7_Pos) /*!< 0x00000080 */ #define CAN_F3R1_FB7 CAN_F3R1_FB7_Msk /*!<Filter bit 7 */ #define CAN_F3R1_FB8_Pos (8U) #define CAN_F3R1_FB8_Msk (0x1U << CAN_F3R1_FB8_Pos) /*!< 0x00000100 */ #define CAN_F3R1_FB8 CAN_F3R1_FB8_Msk /*!<Filter bit 8 */ #define CAN_F3R1_FB9_Pos (9U) #define CAN_F3R1_FB9_Msk (0x1U << CAN_F3R1_FB9_Pos) /*!< 0x00000200 */ #define CAN_F3R1_FB9 CAN_F3R1_FB9_Msk /*!<Filter bit 9 */ #define CAN_F3R1_FB10_Pos (10U) #define CAN_F3R1_FB10_Msk (0x1U << CAN_F3R1_FB10_Pos) /*!< 0x00000400 */ #define CAN_F3R1_FB10 CAN_F3R1_FB10_Msk /*!<Filter bit 10 */ #define CAN_F3R1_FB11_Pos (11U) #define CAN_F3R1_FB11_Msk (0x1U << CAN_F3R1_FB11_Pos) /*!< 0x00000800 */ #define CAN_F3R1_FB11 CAN_F3R1_FB11_Msk /*!<Filter bit 11 */ #define CAN_F3R1_FB12_Pos (12U) #define CAN_F3R1_FB12_Msk (0x1U << CAN_F3R1_FB12_Pos) /*!< 0x00001000 */ #define CAN_F3R1_FB12 CAN_F3R1_FB12_Msk /*!<Filter bit 12 */ #define CAN_F3R1_FB13_Pos (13U) #define CAN_F3R1_FB13_Msk (0x1U << CAN_F3R1_FB13_Pos) /*!< 0x00002000 */ #define CAN_F3R1_FB13 CAN_F3R1_FB13_Msk /*!<Filter bit 13 */ #define CAN_F3R1_FB14_Pos (14U) #define CAN_F3R1_FB14_Msk (0x1U << CAN_F3R1_FB14_Pos) /*!< 0x00004000 */ #define CAN_F3R1_FB14 CAN_F3R1_FB14_Msk /*!<Filter bit 14 */ #define CAN_F3R1_FB15_Pos (15U) #define CAN_F3R1_FB15_Msk (0x1U << CAN_F3R1_FB15_Pos) /*!< 0x00008000 */ #define CAN_F3R1_FB15 CAN_F3R1_FB15_Msk /*!<Filter bit 15 */ #define CAN_F3R1_FB16_Pos (16U) #define CAN_F3R1_FB16_Msk (0x1U << CAN_F3R1_FB16_Pos) /*!< 0x00010000 */ #define CAN_F3R1_FB16 CAN_F3R1_FB16_Msk /*!<Filter bit 16 */ #define CAN_F3R1_FB17_Pos (17U) #define CAN_F3R1_FB17_Msk (0x1U << CAN_F3R1_FB17_Pos) /*!< 0x00020000 */ #define CAN_F3R1_FB17 CAN_F3R1_FB17_Msk /*!<Filter bit 17 */ #define CAN_F3R1_FB18_Pos (18U) #define CAN_F3R1_FB18_Msk (0x1U << CAN_F3R1_FB18_Pos) /*!< 0x00040000 */ #define CAN_F3R1_FB18 CAN_F3R1_FB18_Msk /*!<Filter bit 18 */ #define CAN_F3R1_FB19_Pos (19U) #define CAN_F3R1_FB19_Msk (0x1U << CAN_F3R1_FB19_Pos) /*!< 0x00080000 */ #define CAN_F3R1_FB19 CAN_F3R1_FB19_Msk /*!<Filter bit 19 */ #define CAN_F3R1_FB20_Pos (20U) #define CAN_F3R1_FB20_Msk (0x1U << CAN_F3R1_FB20_Pos) /*!< 0x00100000 */ #define CAN_F3R1_FB20 CAN_F3R1_FB20_Msk /*!<Filter bit 20 */ #define CAN_F3R1_FB21_Pos (21U) #define CAN_F3R1_FB21_Msk (0x1U << CAN_F3R1_FB21_Pos) /*!< 0x00200000 */ #define CAN_F3R1_FB21 CAN_F3R1_FB21_Msk /*!<Filter bit 21 */ #define CAN_F3R1_FB22_Pos (22U) #define CAN_F3R1_FB22_Msk (0x1U << CAN_F3R1_FB22_Pos) /*!< 0x00400000 */ #define CAN_F3R1_FB22 CAN_F3R1_FB22_Msk /*!<Filter bit 22 */ #define CAN_F3R1_FB23_Pos (23U) #define CAN_F3R1_FB23_Msk (0x1U << CAN_F3R1_FB23_Pos) /*!< 0x00800000 */ #define CAN_F3R1_FB23 CAN_F3R1_FB23_Msk /*!<Filter bit 23 */ #define CAN_F3R1_FB24_Pos (24U) #define CAN_F3R1_FB24_Msk (0x1U << CAN_F3R1_FB24_Pos) /*!< 0x01000000 */ #define CAN_F3R1_FB24 CAN_F3R1_FB24_Msk /*!<Filter bit 24 */ #define CAN_F3R1_FB25_Pos (25U) #define CAN_F3R1_FB25_Msk (0x1U << CAN_F3R1_FB25_Pos) /*!< 0x02000000 */ #define CAN_F3R1_FB25 CAN_F3R1_FB25_Msk /*!<Filter bit 25 */ #define CAN_F3R1_FB26_Pos (26U) #define CAN_F3R1_FB26_Msk (0x1U << CAN_F3R1_FB26_Pos) /*!< 0x04000000 */ #define CAN_F3R1_FB26 CAN_F3R1_FB26_Msk /*!<Filter bit 26 */ #define CAN_F3R1_FB27_Pos (27U) #define CAN_F3R1_FB27_Msk (0x1U << CAN_F3R1_FB27_Pos) /*!< 0x08000000 */ #define CAN_F3R1_FB27 CAN_F3R1_FB27_Msk /*!<Filter bit 27 */ #define CAN_F3R1_FB28_Pos (28U) #define CAN_F3R1_FB28_Msk (0x1U << CAN_F3R1_FB28_Pos) /*!< 0x10000000 */ #define CAN_F3R1_FB28 CAN_F3R1_FB28_Msk /*!<Filter bit 28 */ #define CAN_F3R1_FB29_Pos (29U) #define CAN_F3R1_FB29_Msk (0x1U << CAN_F3R1_FB29_Pos) /*!< 0x20000000 */ #define CAN_F3R1_FB29 CAN_F3R1_FB29_Msk /*!<Filter bit 29 */ #define CAN_F3R1_FB30_Pos (30U) #define CAN_F3R1_FB30_Msk (0x1U << CAN_F3R1_FB30_Pos) /*!< 0x40000000 */ #define CAN_F3R1_FB30 CAN_F3R1_FB30_Msk /*!<Filter bit 30 */ #define CAN_F3R1_FB31_Pos (31U) #define CAN_F3R1_FB31_Msk (0x1U << CAN_F3R1_FB31_Pos) /*!< 0x80000000 */ #define CAN_F3R1_FB31 CAN_F3R1_FB31_Msk /*!<Filter bit 31 */ /******************* Bit definition for CAN_F4R1 register *******************/ #define CAN_F4R1_FB0_Pos (0U) #define CAN_F4R1_FB0_Msk (0x1U << CAN_F4R1_FB0_Pos) /*!< 0x00000001 */ #define CAN_F4R1_FB0 CAN_F4R1_FB0_Msk /*!<Filter bit 0 */ #define CAN_F4R1_FB1_Pos (1U) #define CAN_F4R1_FB1_Msk (0x1U << CAN_F4R1_FB1_Pos) /*!< 0x00000002 */ #define CAN_F4R1_FB1 CAN_F4R1_FB1_Msk /*!<Filter bit 1 */ #define CAN_F4R1_FB2_Pos (2U) #define CAN_F4R1_FB2_Msk (0x1U << CAN_F4R1_FB2_Pos) /*!< 0x00000004 */ #define CAN_F4R1_FB2 CAN_F4R1_FB2_Msk /*!<Filter bit 2 */ #define CAN_F4R1_FB3_Pos (3U) #define CAN_F4R1_FB3_Msk (0x1U << CAN_F4R1_FB3_Pos) /*!< 0x00000008 */ #define CAN_F4R1_FB3 CAN_F4R1_FB3_Msk /*!<Filter bit 3 */ #define CAN_F4R1_FB4_Pos (4U) #define CAN_F4R1_FB4_Msk (0x1U << CAN_F4R1_FB4_Pos) /*!< 0x00000010 */ #define CAN_F4R1_FB4 CAN_F4R1_FB4_Msk /*!<Filter bit 4 */ #define CAN_F4R1_FB5_Pos (5U) #define CAN_F4R1_FB5_Msk (0x1U << CAN_F4R1_FB5_Pos) /*!< 0x00000020 */ #define CAN_F4R1_FB5 CAN_F4R1_FB5_Msk /*!<Filter bit 5 */ #define CAN_F4R1_FB6_Pos (6U) #define CAN_F4R1_FB6_Msk (0x1U << CAN_F4R1_FB6_Pos) /*!< 0x00000040 */ #define CAN_F4R1_FB6 CAN_F4R1_FB6_Msk /*!<Filter bit 6 */ #define CAN_F4R1_FB7_Pos (7U) #define CAN_F4R1_FB7_Msk (0x1U << CAN_F4R1_FB7_Pos) /*!< 0x00000080 */ #define CAN_F4R1_FB7 CAN_F4R1_FB7_Msk /*!<Filter bit 7 */ #define CAN_F4R1_FB8_Pos (8U) #define CAN_F4R1_FB8_Msk (0x1U << CAN_F4R1_FB8_Pos) /*!< 0x00000100 */ #define CAN_F4R1_FB8 CAN_F4R1_FB8_Msk /*!<Filter bit 8 */ #define CAN_F4R1_FB9_Pos (9U) #define CAN_F4R1_FB9_Msk (0x1U << CAN_F4R1_FB9_Pos) /*!< 0x00000200 */ #define CAN_F4R1_FB9 CAN_F4R1_FB9_Msk /*!<Filter bit 9 */ #define CAN_F4R1_FB10_Pos (10U) #define CAN_F4R1_FB10_Msk (0x1U << CAN_F4R1_FB10_Pos) /*!< 0x00000400 */ #define CAN_F4R1_FB10 CAN_F4R1_FB10_Msk /*!<Filter bit 10 */ #define CAN_F4R1_FB11_Pos (11U) #define CAN_F4R1_FB11_Msk (0x1U << CAN_F4R1_FB11_Pos) /*!< 0x00000800 */ #define CAN_F4R1_FB11 CAN_F4R1_FB11_Msk /*!<Filter bit 11 */ #define CAN_F4R1_FB12_Pos (12U) #define CAN_F4R1_FB12_Msk (0x1U << CAN_F4R1_FB12_Pos) /*!< 0x00001000 */ #define CAN_F4R1_FB12 CAN_F4R1_FB12_Msk /*!<Filter bit 12 */ #define CAN_F4R1_FB13_Pos (13U) #define CAN_F4R1_FB13_Msk (0x1U << CAN_F4R1_FB13_Pos) /*!< 0x00002000 */ #define CAN_F4R1_FB13 CAN_F4R1_FB13_Msk /*!<Filter bit 13 */ #define CAN_F4R1_FB14_Pos (14U) #define CAN_F4R1_FB14_Msk (0x1U << CAN_F4R1_FB14_Pos) /*!< 0x00004000 */ #define CAN_F4R1_FB14 CAN_F4R1_FB14_Msk /*!<Filter bit 14 */ #define CAN_F4R1_FB15_Pos (15U) #define CAN_F4R1_FB15_Msk (0x1U << CAN_F4R1_FB15_Pos) /*!< 0x00008000 */ #define CAN_F4R1_FB15 CAN_F4R1_FB15_Msk /*!<Filter bit 15 */ #define CAN_F4R1_FB16_Pos (16U) #define CAN_F4R1_FB16_Msk (0x1U << CAN_F4R1_FB16_Pos) /*!< 0x00010000 */ #define CAN_F4R1_FB16 CAN_F4R1_FB16_Msk /*!<Filter bit 16 */ #define CAN_F4R1_FB17_Pos (17U) #define CAN_F4R1_FB17_Msk (0x1U << CAN_F4R1_FB17_Pos) /*!< 0x00020000 */ #define CAN_F4R1_FB17 CAN_F4R1_FB17_Msk /*!<Filter bit 17 */ #define CAN_F4R1_FB18_Pos (18U) #define CAN_F4R1_FB18_Msk (0x1U << CAN_F4R1_FB18_Pos) /*!< 0x00040000 */ #define CAN_F4R1_FB18 CAN_F4R1_FB18_Msk /*!<Filter bit 18 */ #define CAN_F4R1_FB19_Pos (19U) #define CAN_F4R1_FB19_Msk (0x1U << CAN_F4R1_FB19_Pos) /*!< 0x00080000 */ #define CAN_F4R1_FB19 CAN_F4R1_FB19_Msk /*!<Filter bit 19 */ #define CAN_F4R1_FB20_Pos (20U) #define CAN_F4R1_FB20_Msk (0x1U << CAN_F4R1_FB20_Pos) /*!< 0x00100000 */ #define CAN_F4R1_FB20 CAN_F4R1_FB20_Msk /*!<Filter bit 20 */ #define CAN_F4R1_FB21_Pos (21U) #define CAN_F4R1_FB21_Msk (0x1U << CAN_F4R1_FB21_Pos) /*!< 0x00200000 */ #define CAN_F4R1_FB21 CAN_F4R1_FB21_Msk /*!<Filter bit 21 */ #define CAN_F4R1_FB22_Pos (22U) #define CAN_F4R1_FB22_Msk (0x1U << CAN_F4R1_FB22_Pos) /*!< 0x00400000 */ #define CAN_F4R1_FB22 CAN_F4R1_FB22_Msk /*!<Filter bit 22 */ #define CAN_F4R1_FB23_Pos (23U) #define CAN_F4R1_FB23_Msk (0x1U << CAN_F4R1_FB23_Pos) /*!< 0x00800000 */ #define CAN_F4R1_FB23 CAN_F4R1_FB23_Msk /*!<Filter bit 23 */ #define CAN_F4R1_FB24_Pos (24U) #define CAN_F4R1_FB24_Msk (0x1U << CAN_F4R1_FB24_Pos) /*!< 0x01000000 */ #define CAN_F4R1_FB24 CAN_F4R1_FB24_Msk /*!<Filter bit 24 */ #define CAN_F4R1_FB25_Pos (25U) #define CAN_F4R1_FB25_Msk (0x1U << CAN_F4R1_FB25_Pos) /*!< 0x02000000 */ #define CAN_F4R1_FB25 CAN_F4R1_FB25_Msk /*!<Filter bit 25 */ #define CAN_F4R1_FB26_Pos (26U) #define CAN_F4R1_FB26_Msk (0x1U << CAN_F4R1_FB26_Pos) /*!< 0x04000000 */ #define CAN_F4R1_FB26 CAN_F4R1_FB26_Msk /*!<Filter bit 26 */ #define CAN_F4R1_FB27_Pos (27U) #define CAN_F4R1_FB27_Msk (0x1U << CAN_F4R1_FB27_Pos) /*!< 0x08000000 */ #define CAN_F4R1_FB27 CAN_F4R1_FB27_Msk /*!<Filter bit 27 */ #define CAN_F4R1_FB28_Pos (28U) #define CAN_F4R1_FB28_Msk (0x1U << CAN_F4R1_FB28_Pos) /*!< 0x10000000 */ #define CAN_F4R1_FB28 CAN_F4R1_FB28_Msk /*!<Filter bit 28 */ #define CAN_F4R1_FB29_Pos (29U) #define CAN_F4R1_FB29_Msk (0x1U << CAN_F4R1_FB29_Pos) /*!< 0x20000000 */ #define CAN_F4R1_FB29 CAN_F4R1_FB29_Msk /*!<Filter bit 29 */ #define CAN_F4R1_FB30_Pos (30U) #define CAN_F4R1_FB30_Msk (0x1U << CAN_F4R1_FB30_Pos) /*!< 0x40000000 */ #define CAN_F4R1_FB30 CAN_F4R1_FB30_Msk /*!<Filter bit 30 */ #define CAN_F4R1_FB31_Pos (31U) #define CAN_F4R1_FB31_Msk (0x1U << CAN_F4R1_FB31_Pos) /*!< 0x80000000 */ #define CAN_F4R1_FB31 CAN_F4R1_FB31_Msk /*!<Filter bit 31 */ /******************* Bit definition for CAN_F5R1 register *******************/ #define CAN_F5R1_FB0_Pos (0U) #define CAN_F5R1_FB0_Msk (0x1U << CAN_F5R1_FB0_Pos) /*!< 0x00000001 */ #define CAN_F5R1_FB0 CAN_F5R1_FB0_Msk /*!<Filter bit 0 */ #define CAN_F5R1_FB1_Pos (1U) #define CAN_F5R1_FB1_Msk (0x1U << CAN_F5R1_FB1_Pos) /*!< 0x00000002 */ #define CAN_F5R1_FB1 CAN_F5R1_FB1_Msk /*!<Filter bit 1 */ #define CAN_F5R1_FB2_Pos (2U) #define CAN_F5R1_FB2_Msk (0x1U << CAN_F5R1_FB2_Pos) /*!< 0x00000004 */ #define CAN_F5R1_FB2 CAN_F5R1_FB2_Msk /*!<Filter bit 2 */ #define CAN_F5R1_FB3_Pos (3U) #define CAN_F5R1_FB3_Msk (0x1U << CAN_F5R1_FB3_Pos) /*!< 0x00000008 */ #define CAN_F5R1_FB3 CAN_F5R1_FB3_Msk /*!<Filter bit 3 */ #define CAN_F5R1_FB4_Pos (4U) #define CAN_F5R1_FB4_Msk (0x1U << CAN_F5R1_FB4_Pos) /*!< 0x00000010 */ #define CAN_F5R1_FB4 CAN_F5R1_FB4_Msk /*!<Filter bit 4 */ #define CAN_F5R1_FB5_Pos (5U) #define CAN_F5R1_FB5_Msk (0x1U << CAN_F5R1_FB5_Pos) /*!< 0x00000020 */ #define CAN_F5R1_FB5 CAN_F5R1_FB5_Msk /*!<Filter bit 5 */ #define CAN_F5R1_FB6_Pos (6U) #define CAN_F5R1_FB6_Msk (0x1U << CAN_F5R1_FB6_Pos) /*!< 0x00000040 */ #define CAN_F5R1_FB6 CAN_F5R1_FB6_Msk /*!<Filter bit 6 */ #define CAN_F5R1_FB7_Pos (7U) #define CAN_F5R1_FB7_Msk (0x1U << CAN_F5R1_FB7_Pos) /*!< 0x00000080 */ #define CAN_F5R1_FB7 CAN_F5R1_FB7_Msk /*!<Filter bit 7 */ #define CAN_F5R1_FB8_Pos (8U) #define CAN_F5R1_FB8_Msk (0x1U << CAN_F5R1_FB8_Pos) /*!< 0x00000100 */ #define CAN_F5R1_FB8 CAN_F5R1_FB8_Msk /*!<Filter bit 8 */ #define CAN_F5R1_FB9_Pos (9U) #define CAN_F5R1_FB9_Msk (0x1U << CAN_F5R1_FB9_Pos) /*!< 0x00000200 */ #define CAN_F5R1_FB9 CAN_F5R1_FB9_Msk /*!<Filter bit 9 */ #define CAN_F5R1_FB10_Pos (10U) #define CAN_F5R1_FB10_Msk (0x1U << CAN_F5R1_FB10_Pos) /*!< 0x00000400 */ #define CAN_F5R1_FB10 CAN_F5R1_FB10_Msk /*!<Filter bit 10 */ #define CAN_F5R1_FB11_Pos (11U) #define CAN_F5R1_FB11_Msk (0x1U << CAN_F5R1_FB11_Pos) /*!< 0x00000800 */ #define CAN_F5R1_FB11 CAN_F5R1_FB11_Msk /*!<Filter bit 11 */ #define CAN_F5R1_FB12_Pos (12U) #define CAN_F5R1_FB12_Msk (0x1U << CAN_F5R1_FB12_Pos) /*!< 0x00001000 */ #define CAN_F5R1_FB12 CAN_F5R1_FB12_Msk /*!<Filter bit 12 */ #define CAN_F5R1_FB13_Pos (13U) #define CAN_F5R1_FB13_Msk (0x1U << CAN_F5R1_FB13_Pos) /*!< 0x00002000 */ #define CAN_F5R1_FB13 CAN_F5R1_FB13_Msk /*!<Filter bit 13 */ #define CAN_F5R1_FB14_Pos (14U) #define CAN_F5R1_FB14_Msk (0x1U << CAN_F5R1_FB14_Pos) /*!< 0x00004000 */ #define CAN_F5R1_FB14 CAN_F5R1_FB14_Msk /*!<Filter bit 14 */ #define CAN_F5R1_FB15_Pos (15U) #define CAN_F5R1_FB15_Msk (0x1U << CAN_F5R1_FB15_Pos) /*!< 0x00008000 */ #define CAN_F5R1_FB15 CAN_F5R1_FB15_Msk /*!<Filter bit 15 */ #define CAN_F5R1_FB16_Pos (16U) #define CAN_F5R1_FB16_Msk (0x1U << CAN_F5R1_FB16_Pos) /*!< 0x00010000 */ #define CAN_F5R1_FB16 CAN_F5R1_FB16_Msk /*!<Filter bit 16 */ #define CAN_F5R1_FB17_Pos (17U) #define CAN_F5R1_FB17_Msk (0x1U << CAN_F5R1_FB17_Pos) /*!< 0x00020000 */ #define CAN_F5R1_FB17 CAN_F5R1_FB17_Msk /*!<Filter bit 17 */ #define CAN_F5R1_FB18_Pos (18U) #define CAN_F5R1_FB18_Msk (0x1U << CAN_F5R1_FB18_Pos) /*!< 0x00040000 */ #define CAN_F5R1_FB18 CAN_F5R1_FB18_Msk /*!<Filter bit 18 */ #define CAN_F5R1_FB19_Pos (19U) #define CAN_F5R1_FB19_Msk (0x1U << CAN_F5R1_FB19_Pos) /*!< 0x00080000 */ #define CAN_F5R1_FB19 CAN_F5R1_FB19_Msk /*!<Filter bit 19 */ #define CAN_F5R1_FB20_Pos (20U) #define CAN_F5R1_FB20_Msk (0x1U << CAN_F5R1_FB20_Pos) /*!< 0x00100000 */ #define CAN_F5R1_FB20 CAN_F5R1_FB20_Msk /*!<Filter bit 20 */ #define CAN_F5R1_FB21_Pos (21U) #define CAN_F5R1_FB21_Msk (0x1U << CAN_F5R1_FB21_Pos) /*!< 0x00200000 */ #define CAN_F5R1_FB21 CAN_F5R1_FB21_Msk /*!<Filter bit 21 */ #define CAN_F5R1_FB22_Pos (22U) #define CAN_F5R1_FB22_Msk (0x1U << CAN_F5R1_FB22_Pos) /*!< 0x00400000 */ #define CAN_F5R1_FB22 CAN_F5R1_FB22_Msk /*!<Filter bit 22 */ #define CAN_F5R1_FB23_Pos (23U) #define CAN_F5R1_FB23_Msk (0x1U << CAN_F5R1_FB23_Pos) /*!< 0x00800000 */ #define CAN_F5R1_FB23 CAN_F5R1_FB23_Msk /*!<Filter bit 23 */ #define CAN_F5R1_FB24_Pos (24U) #define CAN_F5R1_FB24_Msk (0x1U << CAN_F5R1_FB24_Pos) /*!< 0x01000000 */ #define CAN_F5R1_FB24 CAN_F5R1_FB24_Msk /*!<Filter bit 24 */ #define CAN_F5R1_FB25_Pos (25U) #define CAN_F5R1_FB25_Msk (0x1U << CAN_F5R1_FB25_Pos) /*!< 0x02000000 */ #define CAN_F5R1_FB25 CAN_F5R1_FB25_Msk /*!<Filter bit 25 */ #define CAN_F5R1_FB26_Pos (26U) #define CAN_F5R1_FB26_Msk (0x1U << CAN_F5R1_FB26_Pos) /*!< 0x04000000 */ #define CAN_F5R1_FB26 CAN_F5R1_FB26_Msk /*!<Filter bit 26 */ #define CAN_F5R1_FB27_Pos (27U) #define CAN_F5R1_FB27_Msk (0x1U << CAN_F5R1_FB27_Pos) /*!< 0x08000000 */ #define CAN_F5R1_FB27 CAN_F5R1_FB27_Msk /*!<Filter bit 27 */ #define CAN_F5R1_FB28_Pos (28U) #define CAN_F5R1_FB28_Msk (0x1U << CAN_F5R1_FB28_Pos) /*!< 0x10000000 */ #define CAN_F5R1_FB28 CAN_F5R1_FB28_Msk /*!<Filter bit 28 */ #define CAN_F5R1_FB29_Pos (29U) #define CAN_F5R1_FB29_Msk (0x1U << CAN_F5R1_FB29_Pos) /*!< 0x20000000 */ #define CAN_F5R1_FB29 CAN_F5R1_FB29_Msk /*!<Filter bit 29 */ #define CAN_F5R1_FB30_Pos (30U) #define CAN_F5R1_FB30_Msk (0x1U << CAN_F5R1_FB30_Pos) /*!< 0x40000000 */ #define CAN_F5R1_FB30 CAN_F5R1_FB30_Msk /*!<Filter bit 30 */ #define CAN_F5R1_FB31_Pos (31U) #define CAN_F5R1_FB31_Msk (0x1U << CAN_F5R1_FB31_Pos) /*!< 0x80000000 */ #define CAN_F5R1_FB31 CAN_F5R1_FB31_Msk /*!<Filter bit 31 */ /******************* Bit definition for CAN_F6R1 register *******************/ #define CAN_F6R1_FB0_Pos (0U) #define CAN_F6R1_FB0_Msk (0x1U << CAN_F6R1_FB0_Pos) /*!< 0x00000001 */ #define CAN_F6R1_FB0 CAN_F6R1_FB0_Msk /*!<Filter bit 0 */ #define CAN_F6R1_FB1_Pos (1U) #define CAN_F6R1_FB1_Msk (0x1U << CAN_F6R1_FB1_Pos) /*!< 0x00000002 */ #define CAN_F6R1_FB1 CAN_F6R1_FB1_Msk /*!<Filter bit 1 */ #define CAN_F6R1_FB2_Pos (2U) #define CAN_F6R1_FB2_Msk (0x1U << CAN_F6R1_FB2_Pos) /*!< 0x00000004 */ #define CAN_F6R1_FB2 CAN_F6R1_FB2_Msk /*!<Filter bit 2 */ #define CAN_F6R1_FB3_Pos (3U) #define CAN_F6R1_FB3_Msk (0x1U << CAN_F6R1_FB3_Pos) /*!< 0x00000008 */ #define CAN_F6R1_FB3 CAN_F6R1_FB3_Msk /*!<Filter bit 3 */ #define CAN_F6R1_FB4_Pos (4U) #define CAN_F6R1_FB4_Msk (0x1U << CAN_F6R1_FB4_Pos) /*!< 0x00000010 */ #define CAN_F6R1_FB4 CAN_F6R1_FB4_Msk /*!<Filter bit 4 */ #define CAN_F6R1_FB5_Pos (5U) #define CAN_F6R1_FB5_Msk (0x1U << CAN_F6R1_FB5_Pos) /*!< 0x00000020 */ #define CAN_F6R1_FB5 CAN_F6R1_FB5_Msk /*!<Filter bit 5 */ #define CAN_F6R1_FB6_Pos (6U) #define CAN_F6R1_FB6_Msk (0x1U << CAN_F6R1_FB6_Pos) /*!< 0x00000040 */ #define CAN_F6R1_FB6 CAN_F6R1_FB6_Msk /*!<Filter bit 6 */ #define CAN_F6R1_FB7_Pos (7U) #define CAN_F6R1_FB7_Msk (0x1U << CAN_F6R1_FB7_Pos) /*!< 0x00000080 */ #define CAN_F6R1_FB7 CAN_F6R1_FB7_Msk /*!<Filter bit 7 */ #define CAN_F6R1_FB8_Pos (8U) #define CAN_F6R1_FB8_Msk (0x1U << CAN_F6R1_FB8_Pos) /*!< 0x00000100 */ #define CAN_F6R1_FB8 CAN_F6R1_FB8_Msk /*!<Filter bit 8 */ #define CAN_F6R1_FB9_Pos (9U) #define CAN_F6R1_FB9_Msk (0x1U << CAN_F6R1_FB9_Pos) /*!< 0x00000200 */ #define CAN_F6R1_FB9 CAN_F6R1_FB9_Msk /*!<Filter bit 9 */ #define CAN_F6R1_FB10_Pos (10U) #define CAN_F6R1_FB10_Msk (0x1U << CAN_F6R1_FB10_Pos) /*!< 0x00000400 */ #define CAN_F6R1_FB10 CAN_F6R1_FB10_Msk /*!<Filter bit 10 */ #define CAN_F6R1_FB11_Pos (11U) #define CAN_F6R1_FB11_Msk (0x1U << CAN_F6R1_FB11_Pos) /*!< 0x00000800 */ #define CAN_F6R1_FB11 CAN_F6R1_FB11_Msk /*!<Filter bit 11 */ #define CAN_F6R1_FB12_Pos (12U) #define CAN_F6R1_FB12_Msk (0x1U << CAN_F6R1_FB12_Pos) /*!< 0x00001000 */ #define CAN_F6R1_FB12 CAN_F6R1_FB12_Msk /*!<Filter bit 12 */ #define CAN_F6R1_FB13_Pos (13U) #define CAN_F6R1_FB13_Msk (0x1U << CAN_F6R1_FB13_Pos) /*!< 0x00002000 */ #define CAN_F6R1_FB13 CAN_F6R1_FB13_Msk /*!<Filter bit 13 */ #define CAN_F6R1_FB14_Pos (14U) #define CAN_F6R1_FB14_Msk (0x1U << CAN_F6R1_FB14_Pos) /*!< 0x00004000 */ #define CAN_F6R1_FB14 CAN_F6R1_FB14_Msk /*!<Filter bit 14 */ #define CAN_F6R1_FB15_Pos (15U) #define CAN_F6R1_FB15_Msk (0x1U << CAN_F6R1_FB15_Pos) /*!< 0x00008000 */ #define CAN_F6R1_FB15 CAN_F6R1_FB15_Msk /*!<Filter bit 15 */ #define CAN_F6R1_FB16_Pos (16U) #define CAN_F6R1_FB16_Msk (0x1U << CAN_F6R1_FB16_Pos) /*!< 0x00010000 */ #define CAN_F6R1_FB16 CAN_F6R1_FB16_Msk /*!<Filter bit 16 */ #define CAN_F6R1_FB17_Pos (17U) #define CAN_F6R1_FB17_Msk (0x1U << CAN_F6R1_FB17_Pos) /*!< 0x00020000 */ #define CAN_F6R1_FB17 CAN_F6R1_FB17_Msk /*!<Filter bit 17 */ #define CAN_F6R1_FB18_Pos (18U) #define CAN_F6R1_FB18_Msk (0x1U << CAN_F6R1_FB18_Pos) /*!< 0x00040000 */ #define CAN_F6R1_FB18 CAN_F6R1_FB18_Msk /*!<Filter bit 18 */ #define CAN_F6R1_FB19_Pos (19U) #define CAN_F6R1_FB19_Msk (0x1U << CAN_F6R1_FB19_Pos) /*!< 0x00080000 */ #define CAN_F6R1_FB19 CAN_F6R1_FB19_Msk /*!<Filter bit 19 */ #define CAN_F6R1_FB20_Pos (20U) #define CAN_F6R1_FB20_Msk (0x1U << CAN_F6R1_FB20_Pos) /*!< 0x00100000 */ #define CAN_F6R1_FB20 CAN_F6R1_FB20_Msk /*!<Filter bit 20 */ #define CAN_F6R1_FB21_Pos (21U) #define CAN_F6R1_FB21_Msk (0x1U << CAN_F6R1_FB21_Pos) /*!< 0x00200000 */ #define CAN_F6R1_FB21 CAN_F6R1_FB21_Msk /*!<Filter bit 21 */ #define CAN_F6R1_FB22_Pos (22U) #define CAN_F6R1_FB22_Msk (0x1U << CAN_F6R1_FB22_Pos) /*!< 0x00400000 */ #define CAN_F6R1_FB22 CAN_F6R1_FB22_Msk /*!<Filter bit 22 */ #define CAN_F6R1_FB23_Pos (23U) #define CAN_F6R1_FB23_Msk (0x1U << CAN_F6R1_FB23_Pos) /*!< 0x00800000 */ #define CAN_F6R1_FB23 CAN_F6R1_FB23_Msk /*!<Filter bit 23 */ #define CAN_F6R1_FB24_Pos (24U) #define CAN_F6R1_FB24_Msk (0x1U << CAN_F6R1_FB24_Pos) /*!< 0x01000000 */ #define CAN_F6R1_FB24 CAN_F6R1_FB24_Msk /*!<Filter bit 24 */ #define CAN_F6R1_FB25_Pos (25U) #define CAN_F6R1_FB25_Msk (0x1U << CAN_F6R1_FB25_Pos) /*!< 0x02000000 */ #define CAN_F6R1_FB25 CAN_F6R1_FB25_Msk /*!<Filter bit 25 */ #define CAN_F6R1_FB26_Pos (26U) #define CAN_F6R1_FB26_Msk (0x1U << CAN_F6R1_FB26_Pos) /*!< 0x04000000 */ #define CAN_F6R1_FB26 CAN_F6R1_FB26_Msk /*!<Filter bit 26 */ #define CAN_F6R1_FB27_Pos (27U) #define CAN_F6R1_FB27_Msk (0x1U << CAN_F6R1_FB27_Pos) /*!< 0x08000000 */ #define CAN_F6R1_FB27 CAN_F6R1_FB27_Msk /*!<Filter bit 27 */ #define CAN_F6R1_FB28_Pos (28U) #define CAN_F6R1_FB28_Msk (0x1U << CAN_F6R1_FB28_Pos) /*!< 0x10000000 */ #define CAN_F6R1_FB28 CAN_F6R1_FB28_Msk /*!<Filter bit 28 */ #define CAN_F6R1_FB29_Pos (29U) #define CAN_F6R1_FB29_Msk (0x1U << CAN_F6R1_FB29_Pos) /*!< 0x20000000 */ #define CAN_F6R1_FB29 CAN_F6R1_FB29_Msk /*!<Filter bit 29 */ #define CAN_F6R1_FB30_Pos (30U) #define CAN_F6R1_FB30_Msk (0x1U << CAN_F6R1_FB30_Pos) /*!< 0x40000000 */ #define CAN_F6R1_FB30 CAN_F6R1_FB30_Msk /*!<Filter bit 30 */ #define CAN_F6R1_FB31_Pos (31U) #define CAN_F6R1_FB31_Msk (0x1U << CAN_F6R1_FB31_Pos) /*!< 0x80000000 */ #define CAN_F6R1_FB31 CAN_F6R1_FB31_Msk /*!<Filter bit 31 */ /******************* Bit definition for CAN_F7R1 register *******************/ #define CAN_F7R1_FB0_Pos (0U) #define CAN_F7R1_FB0_Msk (0x1U << CAN_F7R1_FB0_Pos) /*!< 0x00000001 */ #define CAN_F7R1_FB0 CAN_F7R1_FB0_Msk /*!<Filter bit 0 */ #define CAN_F7R1_FB1_Pos (1U) #define CAN_F7R1_FB1_Msk (0x1U << CAN_F7R1_FB1_Pos) /*!< 0x00000002 */ #define CAN_F7R1_FB1 CAN_F7R1_FB1_Msk /*!<Filter bit 1 */ #define CAN_F7R1_FB2_Pos (2U) #define CAN_F7R1_FB2_Msk (0x1U << CAN_F7R1_FB2_Pos) /*!< 0x00000004 */ #define CAN_F7R1_FB2 CAN_F7R1_FB2_Msk /*!<Filter bit 2 */ #define CAN_F7R1_FB3_Pos (3U) #define CAN_F7R1_FB3_Msk (0x1U << CAN_F7R1_FB3_Pos) /*!< 0x00000008 */ #define CAN_F7R1_FB3 CAN_F7R1_FB3_Msk /*!<Filter bit 3 */ #define CAN_F7R1_FB4_Pos (4U) #define CAN_F7R1_FB4_Msk (0x1U << CAN_F7R1_FB4_Pos) /*!< 0x00000010 */ #define CAN_F7R1_FB4 CAN_F7R1_FB4_Msk /*!<Filter bit 4 */ #define CAN_F7R1_FB5_Pos (5U) #define CAN_F7R1_FB5_Msk (0x1U << CAN_F7R1_FB5_Pos) /*!< 0x00000020 */ #define CAN_F7R1_FB5 CAN_F7R1_FB5_Msk /*!<Filter bit 5 */ #define CAN_F7R1_FB6_Pos (6U) #define CAN_F7R1_FB6_Msk (0x1U << CAN_F7R1_FB6_Pos) /*!< 0x00000040 */ #define CAN_F7R1_FB6 CAN_F7R1_FB6_Msk /*!<Filter bit 6 */ #define CAN_F7R1_FB7_Pos (7U) #define CAN_F7R1_FB7_Msk (0x1U << CAN_F7R1_FB7_Pos) /*!< 0x00000080 */ #define CAN_F7R1_FB7 CAN_F7R1_FB7_Msk /*!<Filter bit 7 */ #define CAN_F7R1_FB8_Pos (8U) #define CAN_F7R1_FB8_Msk (0x1U << CAN_F7R1_FB8_Pos) /*!< 0x00000100 */ #define CAN_F7R1_FB8 CAN_F7R1_FB8_Msk /*!<Filter bit 8 */ #define CAN_F7R1_FB9_Pos (9U) #define CAN_F7R1_FB9_Msk (0x1U << CAN_F7R1_FB9_Pos) /*!< 0x00000200 */ #define CAN_F7R1_FB9 CAN_F7R1_FB9_Msk /*!<Filter bit 9 */ #define CAN_F7R1_FB10_Pos (10U) #define CAN_F7R1_FB10_Msk (0x1U << CAN_F7R1_FB10_Pos) /*!< 0x00000400 */ #define CAN_F7R1_FB10 CAN_F7R1_FB10_Msk /*!<Filter bit 10 */ #define CAN_F7R1_FB11_Pos (11U) #define CAN_F7R1_FB11_Msk (0x1U << CAN_F7R1_FB11_Pos) /*!< 0x00000800 */ #define CAN_F7R1_FB11 CAN_F7R1_FB11_Msk /*!<Filter bit 11 */ #define CAN_F7R1_FB12_Pos (12U) #define CAN_F7R1_FB12_Msk (0x1U << CAN_F7R1_FB12_Pos) /*!< 0x00001000 */ #define CAN_F7R1_FB12 CAN_F7R1_FB12_Msk /*!<Filter bit 12 */ #define CAN_F7R1_FB13_Pos (13U) #define CAN_F7R1_FB13_Msk (0x1U << CAN_F7R1_FB13_Pos) /*!< 0x00002000 */ #define CAN_F7R1_FB13 CAN_F7R1_FB13_Msk /*!<Filter bit 13 */ #define CAN_F7R1_FB14_Pos (14U) #define CAN_F7R1_FB14_Msk (0x1U << CAN_F7R1_FB14_Pos) /*!< 0x00004000 */ #define CAN_F7R1_FB14 CAN_F7R1_FB14_Msk /*!<Filter bit 14 */ #define CAN_F7R1_FB15_Pos (15U) #define CAN_F7R1_FB15_Msk (0x1U << CAN_F7R1_FB15_Pos) /*!< 0x00008000 */ #define CAN_F7R1_FB15 CAN_F7R1_FB15_Msk /*!<Filter bit 15 */ #define CAN_F7R1_FB16_Pos (16U) #define CAN_F7R1_FB16_Msk (0x1U << CAN_F7R1_FB16_Pos) /*!< 0x00010000 */ #define CAN_F7R1_FB16 CAN_F7R1_FB16_Msk /*!<Filter bit 16 */ #define CAN_F7R1_FB17_Pos (17U) #define CAN_F7R1_FB17_Msk (0x1U << CAN_F7R1_FB17_Pos) /*!< 0x00020000 */ #define CAN_F7R1_FB17 CAN_F7R1_FB17_Msk /*!<Filter bit 17 */ #define CAN_F7R1_FB18_Pos (18U) #define CAN_F7R1_FB18_Msk (0x1U << CAN_F7R1_FB18_Pos) /*!< 0x00040000 */ #define CAN_F7R1_FB18 CAN_F7R1_FB18_Msk /*!<Filter bit 18 */ #define CAN_F7R1_FB19_Pos (19U) #define CAN_F7R1_FB19_Msk (0x1U << CAN_F7R1_FB19_Pos) /*!< 0x00080000 */ #define CAN_F7R1_FB19 CAN_F7R1_FB19_Msk /*!<Filter bit 19 */ #define CAN_F7R1_FB20_Pos (20U) #define CAN_F7R1_FB20_Msk (0x1U << CAN_F7R1_FB20_Pos) /*!< 0x00100000 */ #define CAN_F7R1_FB20 CAN_F7R1_FB20_Msk /*!<Filter bit 20 */ #define CAN_F7R1_FB21_Pos (21U) #define CAN_F7R1_FB21_Msk (0x1U << CAN_F7R1_FB21_Pos) /*!< 0x00200000 */ #define CAN_F7R1_FB21 CAN_F7R1_FB21_Msk /*!<Filter bit 21 */ #define CAN_F7R1_FB22_Pos (22U) #define CAN_F7R1_FB22_Msk (0x1U << CAN_F7R1_FB22_Pos) /*!< 0x00400000 */ #define CAN_F7R1_FB22 CAN_F7R1_FB22_Msk /*!<Filter bit 22 */ #define CAN_F7R1_FB23_Pos (23U) #define CAN_F7R1_FB23_Msk (0x1U << CAN_F7R1_FB23_Pos) /*!< 0x00800000 */ #define CAN_F7R1_FB23 CAN_F7R1_FB23_Msk /*!<Filter bit 23 */ #define CAN_F7R1_FB24_Pos (24U) #define CAN_F7R1_FB24_Msk (0x1U << CAN_F7R1_FB24_Pos) /*!< 0x01000000 */ #define CAN_F7R1_FB24 CAN_F7R1_FB24_Msk /*!<Filter bit 24 */ #define CAN_F7R1_FB25_Pos (25U) #define CAN_F7R1_FB25_Msk (0x1U << CAN_F7R1_FB25_Pos) /*!< 0x02000000 */ #define CAN_F7R1_FB25 CAN_F7R1_FB25_Msk /*!<Filter bit 25 */ #define CAN_F7R1_FB26_Pos (26U) #define CAN_F7R1_FB26_Msk (0x1U << CAN_F7R1_FB26_Pos) /*!< 0x04000000 */ #define CAN_F7R1_FB26 CAN_F7R1_FB26_Msk /*!<Filter bit 26 */ #define CAN_F7R1_FB27_Pos (27U) #define CAN_F7R1_FB27_Msk (0x1U << CAN_F7R1_FB27_Pos) /*!< 0x08000000 */ #define CAN_F7R1_FB27 CAN_F7R1_FB27_Msk /*!<Filter bit 27 */ #define CAN_F7R1_FB28_Pos (28U) #define CAN_F7R1_FB28_Msk (0x1U << CAN_F7R1_FB28_Pos) /*!< 0x10000000 */ #define CAN_F7R1_FB28 CAN_F7R1_FB28_Msk /*!<Filter bit 28 */ #define CAN_F7R1_FB29_Pos (29U) #define CAN_F7R1_FB29_Msk (0x1U << CAN_F7R1_FB29_Pos) /*!< 0x20000000 */ #define CAN_F7R1_FB29 CAN_F7R1_FB29_Msk /*!<Filter bit 29 */ #define CAN_F7R1_FB30_Pos (30U) #define CAN_F7R1_FB30_Msk (0x1U << CAN_F7R1_FB30_Pos) /*!< 0x40000000 */ #define CAN_F7R1_FB30 CAN_F7R1_FB30_Msk /*!<Filter bit 30 */ #define CAN_F7R1_FB31_Pos (31U) #define CAN_F7R1_FB31_Msk (0x1U << CAN_F7R1_FB31_Pos) /*!< 0x80000000 */ #define CAN_F7R1_FB31 CAN_F7R1_FB31_Msk /*!<Filter bit 31 */ /******************* Bit definition for CAN_F8R1 register *******************/ #define CAN_F8R1_FB0_Pos (0U) #define CAN_F8R1_FB0_Msk (0x1U << CAN_F8R1_FB0_Pos) /*!< 0x00000001 */ #define CAN_F8R1_FB0 CAN_F8R1_FB0_Msk /*!<Filter bit 0 */ #define CAN_F8R1_FB1_Pos (1U) #define CAN_F8R1_FB1_Msk (0x1U << CAN_F8R1_FB1_Pos) /*!< 0x00000002 */ #define CAN_F8R1_FB1 CAN_F8R1_FB1_Msk /*!<Filter bit 1 */ #define CAN_F8R1_FB2_Pos (2U) #define CAN_F8R1_FB2_Msk (0x1U << CAN_F8R1_FB2_Pos) /*!< 0x00000004 */ #define CAN_F8R1_FB2 CAN_F8R1_FB2_Msk /*!<Filter bit 2 */ #define CAN_F8R1_FB3_Pos (3U) #define CAN_F8R1_FB3_Msk (0x1U << CAN_F8R1_FB3_Pos) /*!< 0x00000008 */ #define CAN_F8R1_FB3 CAN_F8R1_FB3_Msk /*!<Filter bit 3 */ #define CAN_F8R1_FB4_Pos (4U) #define CAN_F8R1_FB4_Msk (0x1U << CAN_F8R1_FB4_Pos) /*!< 0x00000010 */ #define CAN_F8R1_FB4 CAN_F8R1_FB4_Msk /*!<Filter bit 4 */ #define CAN_F8R1_FB5_Pos (5U) #define CAN_F8R1_FB5_Msk (0x1U << CAN_F8R1_FB5_Pos) /*!< 0x00000020 */ #define CAN_F8R1_FB5 CAN_F8R1_FB5_Msk /*!<Filter bit 5 */ #define CAN_F8R1_FB6_Pos (6U) #define CAN_F8R1_FB6_Msk (0x1U << CAN_F8R1_FB6_Pos) /*!< 0x00000040 */ #define CAN_F8R1_FB6 CAN_F8R1_FB6_Msk /*!<Filter bit 6 */ #define CAN_F8R1_FB7_Pos (7U) #define CAN_F8R1_FB7_Msk (0x1U << CAN_F8R1_FB7_Pos) /*!< 0x00000080 */ #define CAN_F8R1_FB7 CAN_F8R1_FB7_Msk /*!<Filter bit 7 */ #define CAN_F8R1_FB8_Pos (8U) #define CAN_F8R1_FB8_Msk (0x1U << CAN_F8R1_FB8_Pos) /*!< 0x00000100 */ #define CAN_F8R1_FB8 CAN_F8R1_FB8_Msk /*!<Filter bit 8 */ #define CAN_F8R1_FB9_Pos (9U) #define CAN_F8R1_FB9_Msk (0x1U << CAN_F8R1_FB9_Pos) /*!< 0x00000200 */ #define CAN_F8R1_FB9 CAN_F8R1_FB9_Msk /*!<Filter bit 9 */ #define CAN_F8R1_FB10_Pos (10U) #define CAN_F8R1_FB10_Msk (0x1U << CAN_F8R1_FB10_Pos) /*!< 0x00000400 */ #define CAN_F8R1_FB10 CAN_F8R1_FB10_Msk /*!<Filter bit 10 */ #define CAN_F8R1_FB11_Pos (11U) #define CAN_F8R1_FB11_Msk (0x1U << CAN_F8R1_FB11_Pos) /*!< 0x00000800 */ #define CAN_F8R1_FB11 CAN_F8R1_FB11_Msk /*!<Filter bit 11 */ #define CAN_F8R1_FB12_Pos (12U) #define CAN_F8R1_FB12_Msk (0x1U << CAN_F8R1_FB12_Pos) /*!< 0x00001000 */ #define CAN_F8R1_FB12 CAN_F8R1_FB12_Msk /*!<Filter bit 12 */ #define CAN_F8R1_FB13_Pos (13U) #define CAN_F8R1_FB13_Msk (0x1U << CAN_F8R1_FB13_Pos) /*!< 0x00002000 */ #define CAN_F8R1_FB13 CAN_F8R1_FB13_Msk /*!<Filter bit 13 */ #define CAN_F8R1_FB14_Pos (14U) #define CAN_F8R1_FB14_Msk (0x1U << CAN_F8R1_FB14_Pos) /*!< 0x00004000 */ #define CAN_F8R1_FB14 CAN_F8R1_FB14_Msk /*!<Filter bit 14 */ #define CAN_F8R1_FB15_Pos (15U) #define CAN_F8R1_FB15_Msk (0x1U << CAN_F8R1_FB15_Pos) /*!< 0x00008000 */ #define CAN_F8R1_FB15 CAN_F8R1_FB15_Msk /*!<Filter bit 15 */ #define CAN_F8R1_FB16_Pos (16U) #define CAN_F8R1_FB16_Msk (0x1U << CAN_F8R1_FB16_Pos) /*!< 0x00010000 */ #define CAN_F8R1_FB16 CAN_F8R1_FB16_Msk /*!<Filter bit 16 */ #define CAN_F8R1_FB17_Pos (17U) #define CAN_F8R1_FB17_Msk (0x1U << CAN_F8R1_FB17_Pos) /*!< 0x00020000 */ #define CAN_F8R1_FB17 CAN_F8R1_FB17_Msk /*!<Filter bit 17 */ #define CAN_F8R1_FB18_Pos (18U) #define CAN_F8R1_FB18_Msk (0x1U << CAN_F8R1_FB18_Pos) /*!< 0x00040000 */ #define CAN_F8R1_FB18 CAN_F8R1_FB18_Msk /*!<Filter bit 18 */ #define CAN_F8R1_FB19_Pos (19U) #define CAN_F8R1_FB19_Msk (0x1U << CAN_F8R1_FB19_Pos) /*!< 0x00080000 */ #define CAN_F8R1_FB19 CAN_F8R1_FB19_Msk /*!<Filter bit 19 */ #define CAN_F8R1_FB20_Pos (20U) #define CAN_F8R1_FB20_Msk (0x1U << CAN_F8R1_FB20_Pos) /*!< 0x00100000 */ #define CAN_F8R1_FB20 CAN_F8R1_FB20_Msk /*!<Filter bit 20 */ #define CAN_F8R1_FB21_Pos (21U) #define CAN_F8R1_FB21_Msk (0x1U << CAN_F8R1_FB21_Pos) /*!< 0x00200000 */ #define CAN_F8R1_FB21 CAN_F8R1_FB21_Msk /*!<Filter bit 21 */ #define CAN_F8R1_FB22_Pos (22U) #define CAN_F8R1_FB22_Msk (0x1U << CAN_F8R1_FB22_Pos) /*!< 0x00400000 */ #define CAN_F8R1_FB22 CAN_F8R1_FB22_Msk /*!<Filter bit 22 */ #define CAN_F8R1_FB23_Pos (23U) #define CAN_F8R1_FB23_Msk (0x1U << CAN_F8R1_FB23_Pos) /*!< 0x00800000 */ #define CAN_F8R1_FB23 CAN_F8R1_FB23_Msk /*!<Filter bit 23 */ #define CAN_F8R1_FB24_Pos (24U) #define CAN_F8R1_FB24_Msk (0x1U << CAN_F8R1_FB24_Pos) /*!< 0x01000000 */ #define CAN_F8R1_FB24 CAN_F8R1_FB24_Msk /*!<Filter bit 24 */ #define CAN_F8R1_FB25_Pos (25U) #define CAN_F8R1_FB25_Msk (0x1U << CAN_F8R1_FB25_Pos) /*!< 0x02000000 */ #define CAN_F8R1_FB25 CAN_F8R1_FB25_Msk /*!<Filter bit 25 */ #define CAN_F8R1_FB26_Pos (26U) #define CAN_F8R1_FB26_Msk (0x1U << CAN_F8R1_FB26_Pos) /*!< 0x04000000 */ #define CAN_F8R1_FB26 CAN_F8R1_FB26_Msk /*!<Filter bit 26 */ #define CAN_F8R1_FB27_Pos (27U) #define CAN_F8R1_FB27_Msk (0x1U << CAN_F8R1_FB27_Pos) /*!< 0x08000000 */ #define CAN_F8R1_FB27 CAN_F8R1_FB27_Msk /*!<Filter bit 27 */ #define CAN_F8R1_FB28_Pos (28U) #define CAN_F8R1_FB28_Msk (0x1U << CAN_F8R1_FB28_Pos) /*!< 0x10000000 */ #define CAN_F8R1_FB28 CAN_F8R1_FB28_Msk /*!<Filter bit 28 */ #define CAN_F8R1_FB29_Pos (29U) #define CAN_F8R1_FB29_Msk (0x1U << CAN_F8R1_FB29_Pos) /*!< 0x20000000 */ #define CAN_F8R1_FB29 CAN_F8R1_FB29_Msk /*!<Filter bit 29 */ #define CAN_F8R1_FB30_Pos (30U) #define CAN_F8R1_FB30_Msk (0x1U << CAN_F8R1_FB30_Pos) /*!< 0x40000000 */ #define CAN_F8R1_FB30 CAN_F8R1_FB30_Msk /*!<Filter bit 30 */ #define CAN_F8R1_FB31_Pos (31U) #define CAN_F8R1_FB31_Msk (0x1U << CAN_F8R1_FB31_Pos) /*!< 0x80000000 */ #define CAN_F8R1_FB31 CAN_F8R1_FB31_Msk /*!<Filter bit 31 */ /******************* Bit definition for CAN_F9R1 register *******************/ #define CAN_F9R1_FB0_Pos (0U) #define CAN_F9R1_FB0_Msk (0x1U << CAN_F9R1_FB0_Pos) /*!< 0x00000001 */ #define CAN_F9R1_FB0 CAN_F9R1_FB0_Msk /*!<Filter bit 0 */ #define CAN_F9R1_FB1_Pos (1U) #define CAN_F9R1_FB1_Msk (0x1U << CAN_F9R1_FB1_Pos) /*!< 0x00000002 */ #define CAN_F9R1_FB1 CAN_F9R1_FB1_Msk /*!<Filter bit 1 */ #define CAN_F9R1_FB2_Pos (2U) #define CAN_F9R1_FB2_Msk (0x1U << CAN_F9R1_FB2_Pos) /*!< 0x00000004 */ #define CAN_F9R1_FB2 CAN_F9R1_FB2_Msk /*!<Filter bit 2 */ #define CAN_F9R1_FB3_Pos (3U) #define CAN_F9R1_FB3_Msk (0x1U << CAN_F9R1_FB3_Pos) /*!< 0x00000008 */ #define CAN_F9R1_FB3 CAN_F9R1_FB3_Msk /*!<Filter bit 3 */ #define CAN_F9R1_FB4_Pos (4U) #define CAN_F9R1_FB4_Msk (0x1U << CAN_F9R1_FB4_Pos) /*!< 0x00000010 */ #define CAN_F9R1_FB4 CAN_F9R1_FB4_Msk /*!<Filter bit 4 */ #define CAN_F9R1_FB5_Pos (5U) #define CAN_F9R1_FB5_Msk (0x1U << CAN_F9R1_FB5_Pos) /*!< 0x00000020 */ #define CAN_F9R1_FB5 CAN_F9R1_FB5_Msk /*!<Filter bit 5 */ #define CAN_F9R1_FB6_Pos (6U) #define CAN_F9R1_FB6_Msk (0x1U << CAN_F9R1_FB6_Pos) /*!< 0x00000040 */ #define CAN_F9R1_FB6 CAN_F9R1_FB6_Msk /*!<Filter bit 6 */ #define CAN_F9R1_FB7_Pos (7U) #define CAN_F9R1_FB7_Msk (0x1U << CAN_F9R1_FB7_Pos) /*!< 0x00000080 */ #define CAN_F9R1_FB7 CAN_F9R1_FB7_Msk /*!<Filter bit 7 */ #define CAN_F9R1_FB8_Pos (8U) #define CAN_F9R1_FB8_Msk (0x1U << CAN_F9R1_FB8_Pos) /*!< 0x00000100 */ #define CAN_F9R1_FB8 CAN_F9R1_FB8_Msk /*!<Filter bit 8 */ #define CAN_F9R1_FB9_Pos (9U) #define CAN_F9R1_FB9_Msk (0x1U << CAN_F9R1_FB9_Pos) /*!< 0x00000200 */ #define CAN_F9R1_FB9 CAN_F9R1_FB9_Msk /*!<Filter bit 9 */ #define CAN_F9R1_FB10_Pos (10U) #define CAN_F9R1_FB10_Msk (0x1U << CAN_F9R1_FB10_Pos) /*!< 0x00000400 */ #define CAN_F9R1_FB10 CAN_F9R1_FB10_Msk /*!<Filter bit 10 */ #define CAN_F9R1_FB11_Pos (11U) #define CAN_F9R1_FB11_Msk (0x1U << CAN_F9R1_FB11_Pos) /*!< 0x00000800 */ #define CAN_F9R1_FB11 CAN_F9R1_FB11_Msk /*!<Filter bit 11 */ #define CAN_F9R1_FB12_Pos (12U) #define CAN_F9R1_FB12_Msk (0x1U << CAN_F9R1_FB12_Pos) /*!< 0x00001000 */ #define CAN_F9R1_FB12 CAN_F9R1_FB12_Msk /*!<Filter bit 12 */ #define CAN_F9R1_FB13_Pos (13U) #define CAN_F9R1_FB13_Msk (0x1U << CAN_F9R1_FB13_Pos) /*!< 0x00002000 */ #define CAN_F9R1_FB13 CAN_F9R1_FB13_Msk /*!<Filter bit 13 */ #define CAN_F9R1_FB14_Pos (14U) #define CAN_F9R1_FB14_Msk (0x1U << CAN_F9R1_FB14_Pos) /*!< 0x00004000 */ #define CAN_F9R1_FB14 CAN_F9R1_FB14_Msk /*!<Filter bit 14 */ #define CAN_F9R1_FB15_Pos (15U) #define CAN_F9R1_FB15_Msk (0x1U << CAN_F9R1_FB15_Pos) /*!< 0x00008000 */ #define CAN_F9R1_FB15 CAN_F9R1_FB15_Msk /*!<Filter bit 15 */ #define CAN_F9R1_FB16_Pos (16U) #define CAN_F9R1_FB16_Msk (0x1U << CAN_F9R1_FB16_Pos) /*!< 0x00010000 */ #define CAN_F9R1_FB16 CAN_F9R1_FB16_Msk /*!<Filter bit 16 */ #define CAN_F9R1_FB17_Pos (17U) #define CAN_F9R1_FB17_Msk (0x1U << CAN_F9R1_FB17_Pos) /*!< 0x00020000 */ #define CAN_F9R1_FB17 CAN_F9R1_FB17_Msk /*!<Filter bit 17 */ #define CAN_F9R1_FB18_Pos (18U) #define CAN_F9R1_FB18_Msk (0x1U << CAN_F9R1_FB18_Pos) /*!< 0x00040000 */ #define CAN_F9R1_FB18 CAN_F9R1_FB18_Msk /*!<Filter bit 18 */ #define CAN_F9R1_FB19_Pos (19U) #define CAN_F9R1_FB19_Msk (0x1U << CAN_F9R1_FB19_Pos) /*!< 0x00080000 */ #define CAN_F9R1_FB19 CAN_F9R1_FB19_Msk /*!<Filter bit 19 */ #define CAN_F9R1_FB20_Pos (20U) #define CAN_F9R1_FB20_Msk (0x1U << CAN_F9R1_FB20_Pos) /*!< 0x00100000 */ #define CAN_F9R1_FB20 CAN_F9R1_FB20_Msk /*!<Filter bit 20 */ #define CAN_F9R1_FB21_Pos (21U) #define CAN_F9R1_FB21_Msk (0x1U << CAN_F9R1_FB21_Pos) /*!< 0x00200000 */ #define CAN_F9R1_FB21 CAN_F9R1_FB21_Msk /*!<Filter bit 21 */ #define CAN_F9R1_FB22_Pos (22U) #define CAN_F9R1_FB22_Msk (0x1U << CAN_F9R1_FB22_Pos) /*!< 0x00400000 */ #define CAN_F9R1_FB22 CAN_F9R1_FB22_Msk /*!<Filter bit 22 */ #define CAN_F9R1_FB23_Pos (23U) #define CAN_F9R1_FB23_Msk (0x1U << CAN_F9R1_FB23_Pos) /*!< 0x00800000 */ #define CAN_F9R1_FB23 CAN_F9R1_FB23_Msk /*!<Filter bit 23 */ #define CAN_F9R1_FB24_Pos (24U) #define CAN_F9R1_FB24_Msk (0x1U << CAN_F9R1_FB24_Pos) /*!< 0x01000000 */ #define CAN_F9R1_FB24 CAN_F9R1_FB24_Msk /*!<Filter bit 24 */ #define CAN_F9R1_FB25_Pos (25U) #define CAN_F9R1_FB25_Msk (0x1U << CAN_F9R1_FB25_Pos) /*!< 0x02000000 */ #define CAN_F9R1_FB25 CAN_F9R1_FB25_Msk /*!<Filter bit 25 */ #define CAN_F9R1_FB26_Pos (26U) #define CAN_F9R1_FB26_Msk (0x1U << CAN_F9R1_FB26_Pos) /*!< 0x04000000 */ #define CAN_F9R1_FB26 CAN_F9R1_FB26_Msk /*!<Filter bit 26 */ #define CAN_F9R1_FB27_Pos (27U) #define CAN_F9R1_FB27_Msk (0x1U << CAN_F9R1_FB27_Pos) /*!< 0x08000000 */ #define CAN_F9R1_FB27 CAN_F9R1_FB27_Msk /*!<Filter bit 27 */ #define CAN_F9R1_FB28_Pos (28U) #define CAN_F9R1_FB28_Msk (0x1U << CAN_F9R1_FB28_Pos) /*!< 0x10000000 */ #define CAN_F9R1_FB28 CAN_F9R1_FB28_Msk /*!<Filter bit 28 */ #define CAN_F9R1_FB29_Pos (29U) #define CAN_F9R1_FB29_Msk (0x1U << CAN_F9R1_FB29_Pos) /*!< 0x20000000 */ #define CAN_F9R1_FB29 CAN_F9R1_FB29_Msk /*!<Filter bit 29 */ #define CAN_F9R1_FB30_Pos (30U) #define CAN_F9R1_FB30_Msk (0x1U << CAN_F9R1_FB30_Pos) /*!< 0x40000000 */ #define CAN_F9R1_FB30 CAN_F9R1_FB30_Msk /*!<Filter bit 30 */ #define CAN_F9R1_FB31_Pos (31U) #define CAN_F9R1_FB31_Msk (0x1U << CAN_F9R1_FB31_Pos) /*!< 0x80000000 */ #define CAN_F9R1_FB31 CAN_F9R1_FB31_Msk /*!<Filter bit 31 */ /******************* Bit definition for CAN_F10R1 register ******************/ #define CAN_F10R1_FB0_Pos (0U) #define CAN_F10R1_FB0_Msk (0x1U << CAN_F10R1_FB0_Pos) /*!< 0x00000001 */ #define CAN_F10R1_FB0 CAN_F10R1_FB0_Msk /*!<Filter bit 0 */ #define CAN_F10R1_FB1_Pos (1U) #define CAN_F10R1_FB1_Msk (0x1U << CAN_F10R1_FB1_Pos) /*!< 0x00000002 */ #define CAN_F10R1_FB1 CAN_F10R1_FB1_Msk /*!<Filter bit 1 */ #define CAN_F10R1_FB2_Pos (2U) #define CAN_F10R1_FB2_Msk (0x1U << CAN_F10R1_FB2_Pos) /*!< 0x00000004 */ #define CAN_F10R1_FB2 CAN_F10R1_FB2_Msk /*!<Filter bit 2 */ #define CAN_F10R1_FB3_Pos (3U) #define CAN_F10R1_FB3_Msk (0x1U << CAN_F10R1_FB3_Pos) /*!< 0x00000008 */ #define CAN_F10R1_FB3 CAN_F10R1_FB3_Msk /*!<Filter bit 3 */ #define CAN_F10R1_FB4_Pos (4U) #define CAN_F10R1_FB4_Msk (0x1U << CAN_F10R1_FB4_Pos) /*!< 0x00000010 */ #define CAN_F10R1_FB4 CAN_F10R1_FB4_Msk /*!<Filter bit 4 */ #define CAN_F10R1_FB5_Pos (5U) #define CAN_F10R1_FB5_Msk (0x1U << CAN_F10R1_FB5_Pos) /*!< 0x00000020 */ #define CAN_F10R1_FB5 CAN_F10R1_FB5_Msk /*!<Filter bit 5 */ #define CAN_F10R1_FB6_Pos (6U) #define CAN_F10R1_FB6_Msk (0x1U << CAN_F10R1_FB6_Pos) /*!< 0x00000040 */ #define CAN_F10R1_FB6 CAN_F10R1_FB6_Msk /*!<Filter bit 6 */ #define CAN_F10R1_FB7_Pos (7U) #define CAN_F10R1_FB7_Msk (0x1U << CAN_F10R1_FB7_Pos) /*!< 0x00000080 */ #define CAN_F10R1_FB7 CAN_F10R1_FB7_Msk /*!<Filter bit 7 */ #define CAN_F10R1_FB8_Pos (8U) #define CAN_F10R1_FB8_Msk (0x1U << CAN_F10R1_FB8_Pos) /*!< 0x00000100 */ #define CAN_F10R1_FB8 CAN_F10R1_FB8_Msk /*!<Filter bit 8 */ #define CAN_F10R1_FB9_Pos (9U) #define CAN_F10R1_FB9_Msk (0x1U << CAN_F10R1_FB9_Pos) /*!< 0x00000200 */ #define CAN_F10R1_FB9 CAN_F10R1_FB9_Msk /*!<Filter bit 9 */ #define CAN_F10R1_FB10_Pos (10U) #define CAN_F10R1_FB10_Msk (0x1U << CAN_F10R1_FB10_Pos) /*!< 0x00000400 */ #define CAN_F10R1_FB10 CAN_F10R1_FB10_Msk /*!<Filter bit 10 */ #define CAN_F10R1_FB11_Pos (11U) #define CAN_F10R1_FB11_Msk (0x1U << CAN_F10R1_FB11_Pos) /*!< 0x00000800 */ #define CAN_F10R1_FB11 CAN_F10R1_FB11_Msk /*!<Filter bit 11 */ #define CAN_F10R1_FB12_Pos (12U) #define CAN_F10R1_FB12_Msk (0x1U << CAN_F10R1_FB12_Pos) /*!< 0x00001000 */ #define CAN_F10R1_FB12 CAN_F10R1_FB12_Msk /*!<Filter bit 12 */ #define CAN_F10R1_FB13_Pos (13U) #define CAN_F10R1_FB13_Msk (0x1U << CAN_F10R1_FB13_Pos) /*!< 0x00002000 */ #define CAN_F10R1_FB13 CAN_F10R1_FB13_Msk /*!<Filter bit 13 */ #define CAN_F10R1_FB14_Pos (14U) #define CAN_F10R1_FB14_Msk (0x1U << CAN_F10R1_FB14_Pos) /*!< 0x00004000 */ #define CAN_F10R1_FB14 CAN_F10R1_FB14_Msk /*!<Filter bit 14 */ #define CAN_F10R1_FB15_Pos (15U) #define CAN_F10R1_FB15_Msk (0x1U << CAN_F10R1_FB15_Pos) /*!< 0x00008000 */ #define CAN_F10R1_FB15 CAN_F10R1_FB15_Msk /*!<Filter bit 15 */ #define CAN_F10R1_FB16_Pos (16U) #define CAN_F10R1_FB16_Msk (0x1U << CAN_F10R1_FB16_Pos) /*!< 0x00010000 */ #define CAN_F10R1_FB16 CAN_F10R1_FB16_Msk /*!<Filter bit 16 */ #define CAN_F10R1_FB17_Pos (17U) #define CAN_F10R1_FB17_Msk (0x1U << CAN_F10R1_FB17_Pos) /*!< 0x00020000 */ #define CAN_F10R1_FB17 CAN_F10R1_FB17_Msk /*!<Filter bit 17 */ #define CAN_F10R1_FB18_Pos (18U) #define CAN_F10R1_FB18_Msk (0x1U << CAN_F10R1_FB18_Pos) /*!< 0x00040000 */ #define CAN_F10R1_FB18 CAN_F10R1_FB18_Msk /*!<Filter bit 18 */ #define CAN_F10R1_FB19_Pos (19U) #define CAN_F10R1_FB19_Msk (0x1U << CAN_F10R1_FB19_Pos) /*!< 0x00080000 */ #define CAN_F10R1_FB19 CAN_F10R1_FB19_Msk /*!<Filter bit 19 */ #define CAN_F10R1_FB20_Pos (20U) #define CAN_F10R1_FB20_Msk (0x1U << CAN_F10R1_FB20_Pos) /*!< 0x00100000 */ #define CAN_F10R1_FB20 CAN_F10R1_FB20_Msk /*!<Filter bit 20 */ #define CAN_F10R1_FB21_Pos (21U) #define CAN_F10R1_FB21_Msk (0x1U << CAN_F10R1_FB21_Pos) /*!< 0x00200000 */ #define CAN_F10R1_FB21 CAN_F10R1_FB21_Msk /*!<Filter bit 21 */ #define CAN_F10R1_FB22_Pos (22U) #define CAN_F10R1_FB22_Msk (0x1U << CAN_F10R1_FB22_Pos) /*!< 0x00400000 */ #define CAN_F10R1_FB22 CAN_F10R1_FB22_Msk /*!<Filter bit 22 */ #define CAN_F10R1_FB23_Pos (23U) #define CAN_F10R1_FB23_Msk (0x1U << CAN_F10R1_FB23_Pos) /*!< 0x00800000 */ #define CAN_F10R1_FB23 CAN_F10R1_FB23_Msk /*!<Filter bit 23 */ #define CAN_F10R1_FB24_Pos (24U) #define CAN_F10R1_FB24_Msk (0x1U << CAN_F10R1_FB24_Pos) /*!< 0x01000000 */ #define CAN_F10R1_FB24 CAN_F10R1_FB24_Msk /*!<Filter bit 24 */ #define CAN_F10R1_FB25_Pos (25U) #define CAN_F10R1_FB25_Msk (0x1U << CAN_F10R1_FB25_Pos) /*!< 0x02000000 */ #define CAN_F10R1_FB25 CAN_F10R1_FB25_Msk /*!<Filter bit 25 */ #define CAN_F10R1_FB26_Pos (26U) #define CAN_F10R1_FB26_Msk (0x1U << CAN_F10R1_FB26_Pos) /*!< 0x04000000 */ #define CAN_F10R1_FB26 CAN_F10R1_FB26_Msk /*!<Filter bit 26 */ #define CAN_F10R1_FB27_Pos (27U) #define CAN_F10R1_FB27_Msk (0x1U << CAN_F10R1_FB27_Pos) /*!< 0x08000000 */ #define CAN_F10R1_FB27 CAN_F10R1_FB27_Msk /*!<Filter bit 27 */ #define CAN_F10R1_FB28_Pos (28U) #define CAN_F10R1_FB28_Msk (0x1U << CAN_F10R1_FB28_Pos) /*!< 0x10000000 */ #define CAN_F10R1_FB28 CAN_F10R1_FB28_Msk /*!<Filter bit 28 */ #define CAN_F10R1_FB29_Pos (29U) #define CAN_F10R1_FB29_Msk (0x1U << CAN_F10R1_FB29_Pos) /*!< 0x20000000 */ #define CAN_F10R1_FB29 CAN_F10R1_FB29_Msk /*!<Filter bit 29 */ #define CAN_F10R1_FB30_Pos (30U) #define CAN_F10R1_FB30_Msk (0x1U << CAN_F10R1_FB30_Pos) /*!< 0x40000000 */ #define CAN_F10R1_FB30 CAN_F10R1_FB30_Msk /*!<Filter bit 30 */ #define CAN_F10R1_FB31_Pos (31U) #define CAN_F10R1_FB31_Msk (0x1U << CAN_F10R1_FB31_Pos) /*!< 0x80000000 */ #define CAN_F10R1_FB31 CAN_F10R1_FB31_Msk /*!<Filter bit 31 */ /******************* Bit definition for CAN_F11R1 register ******************/ #define CAN_F11R1_FB0_Pos (0U) #define CAN_F11R1_FB0_Msk (0x1U << CAN_F11R1_FB0_Pos) /*!< 0x00000001 */ #define CAN_F11R1_FB0 CAN_F11R1_FB0_Msk /*!<Filter bit 0 */ #define CAN_F11R1_FB1_Pos (1U) #define CAN_F11R1_FB1_Msk (0x1U << CAN_F11R1_FB1_Pos) /*!< 0x00000002 */ #define CAN_F11R1_FB1 CAN_F11R1_FB1_Msk /*!<Filter bit 1 */ #define CAN_F11R1_FB2_Pos (2U) #define CAN_F11R1_FB2_Msk (0x1U << CAN_F11R1_FB2_Pos) /*!< 0x00000004 */ #define CAN_F11R1_FB2 CAN_F11R1_FB2_Msk /*!<Filter bit 2 */ #define CAN_F11R1_FB3_Pos (3U) #define CAN_F11R1_FB3_Msk (0x1U << CAN_F11R1_FB3_Pos) /*!< 0x00000008 */ #define CAN_F11R1_FB3 CAN_F11R1_FB3_Msk /*!<Filter bit 3 */ #define CAN_F11R1_FB4_Pos (4U) #define CAN_F11R1_FB4_Msk (0x1U << CAN_F11R1_FB4_Pos) /*!< 0x00000010 */ #define CAN_F11R1_FB4 CAN_F11R1_FB4_Msk /*!<Filter bit 4 */ #define CAN_F11R1_FB5_Pos (5U) #define CAN_F11R1_FB5_Msk (0x1U << CAN_F11R1_FB5_Pos) /*!< 0x00000020 */ #define CAN_F11R1_FB5 CAN_F11R1_FB5_Msk /*!<Filter bit 5 */ #define CAN_F11R1_FB6_Pos (6U) #define CAN_F11R1_FB6_Msk (0x1U << CAN_F11R1_FB6_Pos) /*!< 0x00000040 */ #define CAN_F11R1_FB6 CAN_F11R1_FB6_Msk /*!<Filter bit 6 */ #define CAN_F11R1_FB7_Pos (7U) #define CAN_F11R1_FB7_Msk (0x1U << CAN_F11R1_FB7_Pos) /*!< 0x00000080 */ #define CAN_F11R1_FB7 CAN_F11R1_FB7_Msk /*!<Filter bit 7 */ #define CAN_F11R1_FB8_Pos (8U) #define CAN_F11R1_FB8_Msk (0x1U << CAN_F11R1_FB8_Pos) /*!< 0x00000100 */ #define CAN_F11R1_FB8 CAN_F11R1_FB8_Msk /*!<Filter bit 8 */ #define CAN_F11R1_FB9_Pos (9U) #define CAN_F11R1_FB9_Msk (0x1U << CAN_F11R1_FB9_Pos) /*!< 0x00000200 */ #define CAN_F11R1_FB9 CAN_F11R1_FB9_Msk /*!<Filter bit 9 */ #define CAN_F11R1_FB10_Pos (10U) #define CAN_F11R1_FB10_Msk (0x1U << CAN_F11R1_FB10_Pos) /*!< 0x00000400 */ #define CAN_F11R1_FB10 CAN_F11R1_FB10_Msk /*!<Filter bit 10 */ #define CAN_F11R1_FB11_Pos (11U) #define CAN_F11R1_FB11_Msk (0x1U << CAN_F11R1_FB11_Pos) /*!< 0x00000800 */ #define CAN_F11R1_FB11 CAN_F11R1_FB11_Msk /*!<Filter bit 11 */ #define CAN_F11R1_FB12_Pos (12U) #define CAN_F11R1_FB12_Msk (0x1U << CAN_F11R1_FB12_Pos) /*!< 0x00001000 */ #define CAN_F11R1_FB12 CAN_F11R1_FB12_Msk /*!<Filter bit 12 */ #define CAN_F11R1_FB13_Pos (13U) #define CAN_F11R1_FB13_Msk (0x1U << CAN_F11R1_FB13_Pos) /*!< 0x00002000 */ #define CAN_F11R1_FB13 CAN_F11R1_FB13_Msk /*!<Filter bit 13 */ #define CAN_F11R1_FB14_Pos (14U) #define CAN_F11R1_FB14_Msk (0x1U << CAN_F11R1_FB14_Pos) /*!< 0x00004000 */ #define CAN_F11R1_FB14 CAN_F11R1_FB14_Msk /*!<Filter bit 14 */ #define CAN_F11R1_FB15_Pos (15U) #define CAN_F11R1_FB15_Msk (0x1U << CAN_F11R1_FB15_Pos) /*!< 0x00008000 */ #define CAN_F11R1_FB15 CAN_F11R1_FB15_Msk /*!<Filter bit 15 */ #define CAN_F11R1_FB16_Pos (16U) #define CAN_F11R1_FB16_Msk (0x1U << CAN_F11R1_FB16_Pos) /*!< 0x00010000 */ #define CAN_F11R1_FB16 CAN_F11R1_FB16_Msk /*!<Filter bit 16 */ #define CAN_F11R1_FB17_Pos (17U) #define CAN_F11R1_FB17_Msk (0x1U << CAN_F11R1_FB17_Pos) /*!< 0x00020000 */ #define CAN_F11R1_FB17 CAN_F11R1_FB17_Msk /*!<Filter bit 17 */ #define CAN_F11R1_FB18_Pos (18U) #define CAN_F11R1_FB18_Msk (0x1U << CAN_F11R1_FB18_Pos) /*!< 0x00040000 */ #define CAN_F11R1_FB18 CAN_F11R1_FB18_Msk /*!<Filter bit 18 */ #define CAN_F11R1_FB19_Pos (19U) #define CAN_F11R1_FB19_Msk (0x1U << CAN_F11R1_FB19_Pos) /*!< 0x00080000 */ #define CAN_F11R1_FB19 CAN_F11R1_FB19_Msk /*!<Filter bit 19 */ #define CAN_F11R1_FB20_Pos (20U) #define CAN_F11R1_FB20_Msk (0x1U << CAN_F11R1_FB20_Pos) /*!< 0x00100000 */ #define CAN_F11R1_FB20 CAN_F11R1_FB20_Msk /*!<Filter bit 20 */ #define CAN_F11R1_FB21_Pos (21U) #define CAN_F11R1_FB21_Msk (0x1U << CAN_F11R1_FB21_Pos) /*!< 0x00200000 */ #define CAN_F11R1_FB21 CAN_F11R1_FB21_Msk /*!<Filter bit 21 */ #define CAN_F11R1_FB22_Pos (22U) #define CAN_F11R1_FB22_Msk (0x1U << CAN_F11R1_FB22_Pos) /*!< 0x00400000 */ #define CAN_F11R1_FB22 CAN_F11R1_FB22_Msk /*!<Filter bit 22 */ #define CAN_F11R1_FB23_Pos (23U) #define CAN_F11R1_FB23_Msk (0x1U << CAN_F11R1_FB23_Pos) /*!< 0x00800000 */ #define CAN_F11R1_FB23 CAN_F11R1_FB23_Msk /*!<Filter bit 23 */ #define CAN_F11R1_FB24_Pos (24U) #define CAN_F11R1_FB24_Msk (0x1U << CAN_F11R1_FB24_Pos) /*!< 0x01000000 */ #define CAN_F11R1_FB24 CAN_F11R1_FB24_Msk /*!<Filter bit 24 */ #define CAN_F11R1_FB25_Pos (25U) #define CAN_F11R1_FB25_Msk (0x1U << CAN_F11R1_FB25_Pos) /*!< 0x02000000 */ #define CAN_F11R1_FB25 CAN_F11R1_FB25_Msk /*!<Filter bit 25 */ #define CAN_F11R1_FB26_Pos (26U) #define CAN_F11R1_FB26_Msk (0x1U << CAN_F11R1_FB26_Pos) /*!< 0x04000000 */ #define CAN_F11R1_FB26 CAN_F11R1_FB26_Msk /*!<Filter bit 26 */ #define CAN_F11R1_FB27_Pos (27U) #define CAN_F11R1_FB27_Msk (0x1U << CAN_F11R1_FB27_Pos) /*!< 0x08000000 */ #define CAN_F11R1_FB27 CAN_F11R1_FB27_Msk /*!<Filter bit 27 */ #define CAN_F11R1_FB28_Pos (28U) #define CAN_F11R1_FB28_Msk (0x1U << CAN_F11R1_FB28_Pos) /*!< 0x10000000 */ #define CAN_F11R1_FB28 CAN_F11R1_FB28_Msk /*!<Filter bit 28 */ #define CAN_F11R1_FB29_Pos (29U) #define CAN_F11R1_FB29_Msk (0x1U << CAN_F11R1_FB29_Pos) /*!< 0x20000000 */ #define CAN_F11R1_FB29 CAN_F11R1_FB29_Msk /*!<Filter bit 29 */ #define CAN_F11R1_FB30_Pos (30U) #define CAN_F11R1_FB30_Msk (0x1U << CAN_F11R1_FB30_Pos) /*!< 0x40000000 */ #define CAN_F11R1_FB30 CAN_F11R1_FB30_Msk /*!<Filter bit 30 */ #define CAN_F11R1_FB31_Pos (31U) #define CAN_F11R1_FB31_Msk (0x1U << CAN_F11R1_FB31_Pos) /*!< 0x80000000 */ #define CAN_F11R1_FB31 CAN_F11R1_FB31_Msk /*!<Filter bit 31 */ /******************* Bit definition for CAN_F12R1 register ******************/ #define CAN_F12R1_FB0_Pos (0U) #define CAN_F12R1_FB0_Msk (0x1U << CAN_F12R1_FB0_Pos) /*!< 0x00000001 */ #define CAN_F12R1_FB0 CAN_F12R1_FB0_Msk /*!<Filter bit 0 */ #define CAN_F12R1_FB1_Pos (1U) #define CAN_F12R1_FB1_Msk (0x1U << CAN_F12R1_FB1_Pos) /*!< 0x00000002 */ #define CAN_F12R1_FB1 CAN_F12R1_FB1_Msk /*!<Filter bit 1 */ #define CAN_F12R1_FB2_Pos (2U) #define CAN_F12R1_FB2_Msk (0x1U << CAN_F12R1_FB2_Pos) /*!< 0x00000004 */ #define CAN_F12R1_FB2 CAN_F12R1_FB2_Msk /*!<Filter bit 2 */ #define CAN_F12R1_FB3_Pos (3U) #define CAN_F12R1_FB3_Msk (0x1U << CAN_F12R1_FB3_Pos) /*!< 0x00000008 */ #define CAN_F12R1_FB3 CAN_F12R1_FB3_Msk /*!<Filter bit 3 */ #define CAN_F12R1_FB4_Pos (4U) #define CAN_F12R1_FB4_Msk (0x1U << CAN_F12R1_FB4_Pos) /*!< 0x00000010 */ #define CAN_F12R1_FB4 CAN_F12R1_FB4_Msk /*!<Filter bit 4 */ #define CAN_F12R1_FB5_Pos (5U) #define CAN_F12R1_FB5_Msk (0x1U << CAN_F12R1_FB5_Pos) /*!< 0x00000020 */ #define CAN_F12R1_FB5 CAN_F12R1_FB5_Msk /*!<Filter bit 5 */ #define CAN_F12R1_FB6_Pos (6U) #define CAN_F12R1_FB6_Msk (0x1U << CAN_F12R1_FB6_Pos) /*!< 0x00000040 */ #define CAN_F12R1_FB6 CAN_F12R1_FB6_Msk /*!<Filter bit 6 */ #define CAN_F12R1_FB7_Pos (7U) #define CAN_F12R1_FB7_Msk (0x1U << CAN_F12R1_FB7_Pos) /*!< 0x00000080 */ #define CAN_F12R1_FB7 CAN_F12R1_FB7_Msk /*!<Filter bit 7 */ #define CAN_F12R1_FB8_Pos (8U) #define CAN_F12R1_FB8_Msk (0x1U << CAN_F12R1_FB8_Pos) /*!< 0x00000100 */ #define CAN_F12R1_FB8 CAN_F12R1_FB8_Msk /*!<Filter bit 8 */ #define CAN_F12R1_FB9_Pos (9U) #define CAN_F12R1_FB9_Msk (0x1U << CAN_F12R1_FB9_Pos) /*!< 0x00000200 */ #define CAN_F12R1_FB9 CAN_F12R1_FB9_Msk /*!<Filter bit 9 */ #define CAN_F12R1_FB10_Pos (10U) #define CAN_F12R1_FB10_Msk (0x1U << CAN_F12R1_FB10_Pos) /*!< 0x00000400 */ #define CAN_F12R1_FB10 CAN_F12R1_FB10_Msk /*!<Filter bit 10 */ #define CAN_F12R1_FB11_Pos (11U) #define CAN_F12R1_FB11_Msk (0x1U << CAN_F12R1_FB11_Pos) /*!< 0x00000800 */ #define CAN_F12R1_FB11 CAN_F12R1_FB11_Msk /*!<Filter bit 11 */ #define CAN_F12R1_FB12_Pos (12U) #define CAN_F12R1_FB12_Msk (0x1U << CAN_F12R1_FB12_Pos) /*!< 0x00001000 */ #define CAN_F12R1_FB12 CAN_F12R1_FB12_Msk /*!<Filter bit 12 */ #define CAN_F12R1_FB13_Pos (13U) #define CAN_F12R1_FB13_Msk (0x1U << CAN_F12R1_FB13_Pos) /*!< 0x00002000 */ #define CAN_F12R1_FB13 CAN_F12R1_FB13_Msk /*!<Filter bit 13 */ #define CAN_F12R1_FB14_Pos (14U) #define CAN_F12R1_FB14_Msk (0x1U << CAN_F12R1_FB14_Pos) /*!< 0x00004000 */ #define CAN_F12R1_FB14 CAN_F12R1_FB14_Msk /*!<Filter bit 14 */ #define CAN_F12R1_FB15_Pos (15U) #define CAN_F12R1_FB15_Msk (0x1U << CAN_F12R1_FB15_Pos) /*!< 0x00008000 */ #define CAN_F12R1_FB15 CAN_F12R1_FB15_Msk /*!<Filter bit 15 */ #define CAN_F12R1_FB16_Pos (16U) #define CAN_F12R1_FB16_Msk (0x1U << CAN_F12R1_FB16_Pos) /*!< 0x00010000 */ #define CAN_F12R1_FB16 CAN_F12R1_FB16_Msk /*!<Filter bit 16 */ #define CAN_F12R1_FB17_Pos (17U) #define CAN_F12R1_FB17_Msk (0x1U << CAN_F12R1_FB17_Pos) /*!< 0x00020000 */ #define CAN_F12R1_FB17 CAN_F12R1_FB17_Msk /*!<Filter bit 17 */ #define CAN_F12R1_FB18_Pos (18U) #define CAN_F12R1_FB18_Msk (0x1U << CAN_F12R1_FB18_Pos) /*!< 0x00040000 */ #define CAN_F12R1_FB18 CAN_F12R1_FB18_Msk /*!<Filter bit 18 */ #define CAN_F12R1_FB19_Pos (19U) #define CAN_F12R1_FB19_Msk (0x1U << CAN_F12R1_FB19_Pos) /*!< 0x00080000 */ #define CAN_F12R1_FB19 CAN_F12R1_FB19_Msk /*!<Filter bit 19 */ #define CAN_F12R1_FB20_Pos (20U) #define CAN_F12R1_FB20_Msk (0x1U << CAN_F12R1_FB20_Pos) /*!< 0x00100000 */ #define CAN_F12R1_FB20 CAN_F12R1_FB20_Msk /*!<Filter bit 20 */ #define CAN_F12R1_FB21_Pos (21U) #define CAN_F12R1_FB21_Msk (0x1U << CAN_F12R1_FB21_Pos) /*!< 0x00200000 */ #define CAN_F12R1_FB21 CAN_F12R1_FB21_Msk /*!<Filter bit 21 */ #define CAN_F12R1_FB22_Pos (22U) #define CAN_F12R1_FB22_Msk (0x1U << CAN_F12R1_FB22_Pos) /*!< 0x00400000 */ #define CAN_F12R1_FB22 CAN_F12R1_FB22_Msk /*!<Filter bit 22 */ #define CAN_F12R1_FB23_Pos (23U) #define CAN_F12R1_FB23_Msk (0x1U << CAN_F12R1_FB23_Pos) /*!< 0x00800000 */ #define CAN_F12R1_FB23 CAN_F12R1_FB23_Msk /*!<Filter bit 23 */ #define CAN_F12R1_FB24_Pos (24U) #define CAN_F12R1_FB24_Msk (0x1U << CAN_F12R1_FB24_Pos) /*!< 0x01000000 */ #define CAN_F12R1_FB24 CAN_F12R1_FB24_Msk /*!<Filter bit 24 */ #define CAN_F12R1_FB25_Pos (25U) #define CAN_F12R1_FB25_Msk (0x1U << CAN_F12R1_FB25_Pos) /*!< 0x02000000 */ #define CAN_F12R1_FB25 CAN_F12R1_FB25_Msk /*!<Filter bit 25 */ #define CAN_F12R1_FB26_Pos (26U) #define CAN_F12R1_FB26_Msk (0x1U << CAN_F12R1_FB26_Pos) /*!< 0x04000000 */ #define CAN_F12R1_FB26 CAN_F12R1_FB26_Msk /*!<Filter bit 26 */ #define CAN_F12R1_FB27_Pos (27U) #define CAN_F12R1_FB27_Msk (0x1U << CAN_F12R1_FB27_Pos) /*!< 0x08000000 */ #define CAN_F12R1_FB27 CAN_F12R1_FB27_Msk /*!<Filter bit 27 */ #define CAN_F12R1_FB28_Pos (28U) #define CAN_F12R1_FB28_Msk (0x1U << CAN_F12R1_FB28_Pos) /*!< 0x10000000 */ #define CAN_F12R1_FB28 CAN_F12R1_FB28_Msk /*!<Filter bit 28 */ #define CAN_F12R1_FB29_Pos (29U) #define CAN_F12R1_FB29_Msk (0x1U << CAN_F12R1_FB29_Pos) /*!< 0x20000000 */ #define CAN_F12R1_FB29 CAN_F12R1_FB29_Msk /*!<Filter bit 29 */ #define CAN_F12R1_FB30_Pos (30U) #define CAN_F12R1_FB30_Msk (0x1U << CAN_F12R1_FB30_Pos) /*!< 0x40000000 */ #define CAN_F12R1_FB30 CAN_F12R1_FB30_Msk /*!<Filter bit 30 */ #define CAN_F12R1_FB31_Pos (31U) #define CAN_F12R1_FB31_Msk (0x1U << CAN_F12R1_FB31_Pos) /*!< 0x80000000 */ #define CAN_F12R1_FB31 CAN_F12R1_FB31_Msk /*!<Filter bit 31 */ /******************* Bit definition for CAN_F13R1 register ******************/ #define CAN_F13R1_FB0_Pos (0U) #define CAN_F13R1_FB0_Msk (0x1U << CAN_F13R1_FB0_Pos) /*!< 0x00000001 */ #define CAN_F13R1_FB0 CAN_F13R1_FB0_Msk /*!<Filter bit 0 */ #define CAN_F13R1_FB1_Pos (1U) #define CAN_F13R1_FB1_Msk (0x1U << CAN_F13R1_FB1_Pos) /*!< 0x00000002 */ #define CAN_F13R1_FB1 CAN_F13R1_FB1_Msk /*!<Filter bit 1 */ #define CAN_F13R1_FB2_Pos (2U) #define CAN_F13R1_FB2_Msk (0x1U << CAN_F13R1_FB2_Pos) /*!< 0x00000004 */ #define CAN_F13R1_FB2 CAN_F13R1_FB2_Msk /*!<Filter bit 2 */ #define CAN_F13R1_FB3_Pos (3U) #define CAN_F13R1_FB3_Msk (0x1U << CAN_F13R1_FB3_Pos) /*!< 0x00000008 */ #define CAN_F13R1_FB3 CAN_F13R1_FB3_Msk /*!<Filter bit 3 */ #define CAN_F13R1_FB4_Pos (4U) #define CAN_F13R1_FB4_Msk (0x1U << CAN_F13R1_FB4_Pos) /*!< 0x00000010 */ #define CAN_F13R1_FB4 CAN_F13R1_FB4_Msk /*!<Filter bit 4 */ #define CAN_F13R1_FB5_Pos (5U) #define CAN_F13R1_FB5_Msk (0x1U << CAN_F13R1_FB5_Pos) /*!< 0x00000020 */ #define CAN_F13R1_FB5 CAN_F13R1_FB5_Msk /*!<Filter bit 5 */ #define CAN_F13R1_FB6_Pos (6U) #define CAN_F13R1_FB6_Msk (0x1U << CAN_F13R1_FB6_Pos) /*!< 0x00000040 */ #define CAN_F13R1_FB6 CAN_F13R1_FB6_Msk /*!<Filter bit 6 */ #define CAN_F13R1_FB7_Pos (7U) #define CAN_F13R1_FB7_Msk (0x1U << CAN_F13R1_FB7_Pos) /*!< 0x00000080 */ #define CAN_F13R1_FB7 CAN_F13R1_FB7_Msk /*!<Filter bit 7 */ #define CAN_F13R1_FB8_Pos (8U) #define CAN_F13R1_FB8_Msk (0x1U << CAN_F13R1_FB8_Pos) /*!< 0x00000100 */ #define CAN_F13R1_FB8 CAN_F13R1_FB8_Msk /*!<Filter bit 8 */ #define CAN_F13R1_FB9_Pos (9U) #define CAN_F13R1_FB9_Msk (0x1U << CAN_F13R1_FB9_Pos) /*!< 0x00000200 */ #define CAN_F13R1_FB9 CAN_F13R1_FB9_Msk /*!<Filter bit 9 */ #define CAN_F13R1_FB10_Pos (10U) #define CAN_F13R1_FB10_Msk (0x1U << CAN_F13R1_FB10_Pos) /*!< 0x00000400 */ #define CAN_F13R1_FB10 CAN_F13R1_FB10_Msk /*!<Filter bit 10 */ #define CAN_F13R1_FB11_Pos (11U) #define CAN_F13R1_FB11_Msk (0x1U << CAN_F13R1_FB11_Pos) /*!< 0x00000800 */ #define CAN_F13R1_FB11 CAN_F13R1_FB11_Msk /*!<Filter bit 11 */ #define CAN_F13R1_FB12_Pos (12U) #define CAN_F13R1_FB12_Msk (0x1U << CAN_F13R1_FB12_Pos) /*!< 0x00001000 */ #define CAN_F13R1_FB12 CAN_F13R1_FB12_Msk /*!<Filter bit 12 */ #define CAN_F13R1_FB13_Pos (13U) #define CAN_F13R1_FB13_Msk (0x1U << CAN_F13R1_FB13_Pos) /*!< 0x00002000 */ #define CAN_F13R1_FB13 CAN_F13R1_FB13_Msk /*!<Filter bit 13 */ #define CAN_F13R1_FB14_Pos (14U) #define CAN_F13R1_FB14_Msk (0x1U << CAN_F13R1_FB14_Pos) /*!< 0x00004000 */ #define CAN_F13R1_FB14 CAN_F13R1_FB14_Msk /*!<Filter bit 14 */ #define CAN_F13R1_FB15_Pos (15U) #define CAN_F13R1_FB15_Msk (0x1U << CAN_F13R1_FB15_Pos) /*!< 0x00008000 */ #define CAN_F13R1_FB15 CAN_F13R1_FB15_Msk /*!<Filter bit 15 */ #define CAN_F13R1_FB16_Pos (16U) #define CAN_F13R1_FB16_Msk (0x1U << CAN_F13R1_FB16_Pos) /*!< 0x00010000 */ #define CAN_F13R1_FB16 CAN_F13R1_FB16_Msk /*!<Filter bit 16 */ #define CAN_F13R1_FB17_Pos (17U) #define CAN_F13R1_FB17_Msk (0x1U << CAN_F13R1_FB17_Pos) /*!< 0x00020000 */ #define CAN_F13R1_FB17 CAN_F13R1_FB17_Msk /*!<Filter bit 17 */ #define CAN_F13R1_FB18_Pos (18U) #define CAN_F13R1_FB18_Msk (0x1U << CAN_F13R1_FB18_Pos) /*!< 0x00040000 */ #define CAN_F13R1_FB18 CAN_F13R1_FB18_Msk /*!<Filter bit 18 */ #define CAN_F13R1_FB19_Pos (19U) #define CAN_F13R1_FB19_Msk (0x1U << CAN_F13R1_FB19_Pos) /*!< 0x00080000 */ #define CAN_F13R1_FB19 CAN_F13R1_FB19_Msk /*!<Filter bit 19 */ #define CAN_F13R1_FB20_Pos (20U) #define CAN_F13R1_FB20_Msk (0x1U << CAN_F13R1_FB20_Pos) /*!< 0x00100000 */ #define CAN_F13R1_FB20 CAN_F13R1_FB20_Msk /*!<Filter bit 20 */ #define CAN_F13R1_FB21_Pos (21U) #define CAN_F13R1_FB21_Msk (0x1U << CAN_F13R1_FB21_Pos) /*!< 0x00200000 */ #define CAN_F13R1_FB21 CAN_F13R1_FB21_Msk /*!<Filter bit 21 */ #define CAN_F13R1_FB22_Pos (22U) #define CAN_F13R1_FB22_Msk (0x1U << CAN_F13R1_FB22_Pos) /*!< 0x00400000 */ #define CAN_F13R1_FB22 CAN_F13R1_FB22_Msk /*!<Filter bit 22 */ #define CAN_F13R1_FB23_Pos (23U) #define CAN_F13R1_FB23_Msk (0x1U << CAN_F13R1_FB23_Pos) /*!< 0x00800000 */ #define CAN_F13R1_FB23 CAN_F13R1_FB23_Msk /*!<Filter bit 23 */ #define CAN_F13R1_FB24_Pos (24U) #define CAN_F13R1_FB24_Msk (0x1U << CAN_F13R1_FB24_Pos) /*!< 0x01000000 */ #define CAN_F13R1_FB24 CAN_F13R1_FB24_Msk /*!<Filter bit 24 */ #define CAN_F13R1_FB25_Pos (25U) #define CAN_F13R1_FB25_Msk (0x1U << CAN_F13R1_FB25_Pos) /*!< 0x02000000 */ #define CAN_F13R1_FB25 CAN_F13R1_FB25_Msk /*!<Filter bit 25 */ #define CAN_F13R1_FB26_Pos (26U) #define CAN_F13R1_FB26_Msk (0x1U << CAN_F13R1_FB26_Pos) /*!< 0x04000000 */ #define CAN_F13R1_FB26 CAN_F13R1_FB26_Msk /*!<Filter bit 26 */ #define CAN_F13R1_FB27_Pos (27U) #define CAN_F13R1_FB27_Msk (0x1U << CAN_F13R1_FB27_Pos) /*!< 0x08000000 */ #define CAN_F13R1_FB27 CAN_F13R1_FB27_Msk /*!<Filter bit 27 */ #define CAN_F13R1_FB28_Pos (28U) #define CAN_F13R1_FB28_Msk (0x1U << CAN_F13R1_FB28_Pos) /*!< 0x10000000 */ #define CAN_F13R1_FB28 CAN_F13R1_FB28_Msk /*!<Filter bit 28 */ #define CAN_F13R1_FB29_Pos (29U) #define CAN_F13R1_FB29_Msk (0x1U << CAN_F13R1_FB29_Pos) /*!< 0x20000000 */ #define CAN_F13R1_FB29 CAN_F13R1_FB29_Msk /*!<Filter bit 29 */ #define CAN_F13R1_FB30_Pos (30U) #define CAN_F13R1_FB30_Msk (0x1U << CAN_F13R1_FB30_Pos) /*!< 0x40000000 */ #define CAN_F13R1_FB30 CAN_F13R1_FB30_Msk /*!<Filter bit 30 */ #define CAN_F13R1_FB31_Pos (31U) #define CAN_F13R1_FB31_Msk (0x1U << CAN_F13R1_FB31_Pos) /*!< 0x80000000 */ #define CAN_F13R1_FB31 CAN_F13R1_FB31_Msk /*!<Filter bit 31 */ /******************* Bit definition for CAN_F0R2 register *******************/ #define CAN_F0R2_FB0_Pos (0U) #define CAN_F0R2_FB0_Msk (0x1U << CAN_F0R2_FB0_Pos) /*!< 0x00000001 */ #define CAN_F0R2_FB0 CAN_F0R2_FB0_Msk /*!<Filter bit 0 */ #define CAN_F0R2_FB1_Pos (1U) #define CAN_F0R2_FB1_Msk (0x1U << CAN_F0R2_FB1_Pos) /*!< 0x00000002 */ #define CAN_F0R2_FB1 CAN_F0R2_FB1_Msk /*!<Filter bit 1 */ #define CAN_F0R2_FB2_Pos (2U) #define CAN_F0R2_FB2_Msk (0x1U << CAN_F0R2_FB2_Pos) /*!< 0x00000004 */ #define CAN_F0R2_FB2 CAN_F0R2_FB2_Msk /*!<Filter bit 2 */ #define CAN_F0R2_FB3_Pos (3U) #define CAN_F0R2_FB3_Msk (0x1U << CAN_F0R2_FB3_Pos) /*!< 0x00000008 */ #define CAN_F0R2_FB3 CAN_F0R2_FB3_Msk /*!<Filter bit 3 */ #define CAN_F0R2_FB4_Pos (4U) #define CAN_F0R2_FB4_Msk (0x1U << CAN_F0R2_FB4_Pos) /*!< 0x00000010 */ #define CAN_F0R2_FB4 CAN_F0R2_FB4_Msk /*!<Filter bit 4 */ #define CAN_F0R2_FB5_Pos (5U) #define CAN_F0R2_FB5_Msk (0x1U << CAN_F0R2_FB5_Pos) /*!< 0x00000020 */ #define CAN_F0R2_FB5 CAN_F0R2_FB5_Msk /*!<Filter bit 5 */ #define CAN_F0R2_FB6_Pos (6U) #define CAN_F0R2_FB6_Msk (0x1U << CAN_F0R2_FB6_Pos) /*!< 0x00000040 */ #define CAN_F0R2_FB6 CAN_F0R2_FB6_Msk /*!<Filter bit 6 */ #define CAN_F0R2_FB7_Pos (7U) #define CAN_F0R2_FB7_Msk (0x1U << CAN_F0R2_FB7_Pos) /*!< 0x00000080 */ #define CAN_F0R2_FB7 CAN_F0R2_FB7_Msk /*!<Filter bit 7 */ #define CAN_F0R2_FB8_Pos (8U) #define CAN_F0R2_FB8_Msk (0x1U << CAN_F0R2_FB8_Pos) /*!< 0x00000100 */ #define CAN_F0R2_FB8 CAN_F0R2_FB8_Msk /*!<Filter bit 8 */ #define CAN_F0R2_FB9_Pos (9U) #define CAN_F0R2_FB9_Msk (0x1U << CAN_F0R2_FB9_Pos) /*!< 0x00000200 */ #define CAN_F0R2_FB9 CAN_F0R2_FB9_Msk /*!<Filter bit 9 */ #define CAN_F0R2_FB10_Pos (10U) #define CAN_F0R2_FB10_Msk (0x1U << CAN_F0R2_FB10_Pos) /*!< 0x00000400 */ #define CAN_F0R2_FB10 CAN_F0R2_FB10_Msk /*!<Filter bit 10 */ #define CAN_F0R2_FB11_Pos (11U) #define CAN_F0R2_FB11_Msk (0x1U << CAN_F0R2_FB11_Pos) /*!< 0x00000800 */ #define CAN_F0R2_FB11 CAN_F0R2_FB11_Msk /*!<Filter bit 11 */ #define CAN_F0R2_FB12_Pos (12U) #define CAN_F0R2_FB12_Msk (0x1U << CAN_F0R2_FB12_Pos) /*!< 0x00001000 */ #define CAN_F0R2_FB12 CAN_F0R2_FB12_Msk /*!<Filter bit 12 */ #define CAN_F0R2_FB13_Pos (13U) #define CAN_F0R2_FB13_Msk (0x1U << CAN_F0R2_FB13_Pos) /*!< 0x00002000 */ #define CAN_F0R2_FB13 CAN_F0R2_FB13_Msk /*!<Filter bit 13 */ #define CAN_F0R2_FB14_Pos (14U) #define CAN_F0R2_FB14_Msk (0x1U << CAN_F0R2_FB14_Pos) /*!< 0x00004000 */ #define CAN_F0R2_FB14 CAN_F0R2_FB14_Msk /*!<Filter bit 14 */ #define CAN_F0R2_FB15_Pos (15U) #define CAN_F0R2_FB15_Msk (0x1U << CAN_F0R2_FB15_Pos) /*!< 0x00008000 */ #define CAN_F0R2_FB15 CAN_F0R2_FB15_Msk /*!<Filter bit 15 */ #define CAN_F0R2_FB16_Pos (16U) #define CAN_F0R2_FB16_Msk (0x1U << CAN_F0R2_FB16_Pos) /*!< 0x00010000 */ #define CAN_F0R2_FB16 CAN_F0R2_FB16_Msk /*!<Filter bit 16 */ #define CAN_F0R2_FB17_Pos (17U) #define CAN_F0R2_FB17_Msk (0x1U << CAN_F0R2_FB17_Pos) /*!< 0x00020000 */ #define CAN_F0R2_FB17 CAN_F0R2_FB17_Msk /*!<Filter bit 17 */ #define CAN_F0R2_FB18_Pos (18U) #define CAN_F0R2_FB18_Msk (0x1U << CAN_F0R2_FB18_Pos) /*!< 0x00040000 */ #define CAN_F0R2_FB18 CAN_F0R2_FB18_Msk /*!<Filter bit 18 */ #define CAN_F0R2_FB19_Pos (19U) #define CAN_F0R2_FB19_Msk (0x1U << CAN_F0R2_FB19_Pos) /*!< 0x00080000 */ #define CAN_F0R2_FB19 CAN_F0R2_FB19_Msk /*!<Filter bit 19 */ #define CAN_F0R2_FB20_Pos (20U) #define CAN_F0R2_FB20_Msk (0x1U << CAN_F0R2_FB20_Pos) /*!< 0x00100000 */ #define CAN_F0R2_FB20 CAN_F0R2_FB20_Msk /*!<Filter bit 20 */ #define CAN_F0R2_FB21_Pos (21U) #define CAN_F0R2_FB21_Msk (0x1U << CAN_F0R2_FB21_Pos) /*!< 0x00200000 */ #define CAN_F0R2_FB21 CAN_F0R2_FB21_Msk /*!<Filter bit 21 */ #define CAN_F0R2_FB22_Pos (22U) #define CAN_F0R2_FB22_Msk (0x1U << CAN_F0R2_FB22_Pos) /*!< 0x00400000 */ #define CAN_F0R2_FB22 CAN_F0R2_FB22_Msk /*!<Filter bit 22 */ #define CAN_F0R2_FB23_Pos (23U) #define CAN_F0R2_FB23_Msk (0x1U << CAN_F0R2_FB23_Pos) /*!< 0x00800000 */ #define CAN_F0R2_FB23 CAN_F0R2_FB23_Msk /*!<Filter bit 23 */ #define CAN_F0R2_FB24_Pos (24U) #define CAN_F0R2_FB24_Msk (0x1U << CAN_F0R2_FB24_Pos) /*!< 0x01000000 */ #define CAN_F0R2_FB24 CAN_F0R2_FB24_Msk /*!<Filter bit 24 */ #define CAN_F0R2_FB25_Pos (25U) #define CAN_F0R2_FB25_Msk (0x1U << CAN_F0R2_FB25_Pos) /*!< 0x02000000 */ #define CAN_F0R2_FB25 CAN_F0R2_FB25_Msk /*!<Filter bit 25 */ #define CAN_F0R2_FB26_Pos (26U) #define CAN_F0R2_FB26_Msk (0x1U << CAN_F0R2_FB26_Pos) /*!< 0x04000000 */ #define CAN_F0R2_FB26 CAN_F0R2_FB26_Msk /*!<Filter bit 26 */ #define CAN_F0R2_FB27_Pos (27U) #define CAN_F0R2_FB27_Msk (0x1U << CAN_F0R2_FB27_Pos) /*!< 0x08000000 */ #define CAN_F0R2_FB27 CAN_F0R2_FB27_Msk /*!<Filter bit 27 */ #define CAN_F0R2_FB28_Pos (28U) #define CAN_F0R2_FB28_Msk (0x1U << CAN_F0R2_FB28_Pos) /*!< 0x10000000 */ #define CAN_F0R2_FB28 CAN_F0R2_FB28_Msk /*!<Filter bit 28 */ #define CAN_F0R2_FB29_Pos (29U) #define CAN_F0R2_FB29_Msk (0x1U << CAN_F0R2_FB29_Pos) /*!< 0x20000000 */ #define CAN_F0R2_FB29 CAN_F0R2_FB29_Msk /*!<Filter bit 29 */ #define CAN_F0R2_FB30_Pos (30U) #define CAN_F0R2_FB30_Msk (0x1U << CAN_F0R2_FB30_Pos) /*!< 0x40000000 */ #define CAN_F0R2_FB30 CAN_F0R2_FB30_Msk /*!<Filter bit 30 */ #define CAN_F0R2_FB31_Pos (31U) #define CAN_F0R2_FB31_Msk (0x1U << CAN_F0R2_FB31_Pos) /*!< 0x80000000 */ #define CAN_F0R2_FB31 CAN_F0R2_FB31_Msk /*!<Filter bit 31 */ /******************* Bit definition for CAN_F1R2 register *******************/ #define CAN_F1R2_FB0_Pos (0U) #define CAN_F1R2_FB0_Msk (0x1U << CAN_F1R2_FB0_Pos) /*!< 0x00000001 */ #define CAN_F1R2_FB0 CAN_F1R2_FB0_Msk /*!<Filter bit 0 */ #define CAN_F1R2_FB1_Pos (1U) #define CAN_F1R2_FB1_Msk (0x1U << CAN_F1R2_FB1_Pos) /*!< 0x00000002 */ #define CAN_F1R2_FB1 CAN_F1R2_FB1_Msk /*!<Filter bit 1 */ #define CAN_F1R2_FB2_Pos (2U) #define CAN_F1R2_FB2_Msk (0x1U << CAN_F1R2_FB2_Pos) /*!< 0x00000004 */ #define CAN_F1R2_FB2 CAN_F1R2_FB2_Msk /*!<Filter bit 2 */ #define CAN_F1R2_FB3_Pos (3U) #define CAN_F1R2_FB3_Msk (0x1U << CAN_F1R2_FB3_Pos) /*!< 0x00000008 */ #define CAN_F1R2_FB3 CAN_F1R2_FB3_Msk /*!<Filter bit 3 */ #define CAN_F1R2_FB4_Pos (4U) #define CAN_F1R2_FB4_Msk (0x1U << CAN_F1R2_FB4_Pos) /*!< 0x00000010 */ #define CAN_F1R2_FB4 CAN_F1R2_FB4_Msk /*!<Filter bit 4 */ #define CAN_F1R2_FB5_Pos (5U) #define CAN_F1R2_FB5_Msk (0x1U << CAN_F1R2_FB5_Pos) /*!< 0x00000020 */ #define CAN_F1R2_FB5 CAN_F1R2_FB5_Msk /*!<Filter bit 5 */ #define CAN_F1R2_FB6_Pos (6U) #define CAN_F1R2_FB6_Msk (0x1U << CAN_F1R2_FB6_Pos) /*!< 0x00000040 */ #define CAN_F1R2_FB6 CAN_F1R2_FB6_Msk /*!<Filter bit 6 */ #define CAN_F1R2_FB7_Pos (7U) #define CAN_F1R2_FB7_Msk (0x1U << CAN_F1R2_FB7_Pos) /*!< 0x00000080 */ #define CAN_F1R2_FB7 CAN_F1R2_FB7_Msk /*!<Filter bit 7 */ #define CAN_F1R2_FB8_Pos (8U) #define CAN_F1R2_FB8_Msk (0x1U << CAN_F1R2_FB8_Pos) /*!< 0x00000100 */ #define CAN_F1R2_FB8 CAN_F1R2_FB8_Msk /*!<Filter bit 8 */ #define CAN_F1R2_FB9_Pos (9U) #define CAN_F1R2_FB9_Msk (0x1U << CAN_F1R2_FB9_Pos) /*!< 0x00000200 */ #define CAN_F1R2_FB9 CAN_F1R2_FB9_Msk /*!<Filter bit 9 */ #define CAN_F1R2_FB10_Pos (10U) #define CAN_F1R2_FB10_Msk (0x1U << CAN_F1R2_FB10_Pos) /*!< 0x00000400 */ #define CAN_F1R2_FB10 CAN_F1R2_FB10_Msk /*!<Filter bit 10 */ #define CAN_F1R2_FB11_Pos (11U) #define CAN_F1R2_FB11_Msk (0x1U << CAN_F1R2_FB11_Pos) /*!< 0x00000800 */ #define CAN_F1R2_FB11 CAN_F1R2_FB11_Msk /*!<Filter bit 11 */ #define CAN_F1R2_FB12_Pos (12U) #define CAN_F1R2_FB12_Msk (0x1U << CAN_F1R2_FB12_Pos) /*!< 0x00001000 */ #define CAN_F1R2_FB12 CAN_F1R2_FB12_Msk /*!<Filter bit 12 */ #define CAN_F1R2_FB13_Pos (13U) #define CAN_F1R2_FB13_Msk (0x1U << CAN_F1R2_FB13_Pos) /*!< 0x00002000 */ #define CAN_F1R2_FB13 CAN_F1R2_FB13_Msk /*!<Filter bit 13 */ #define CAN_F1R2_FB14_Pos (14U) #define CAN_F1R2_FB14_Msk (0x1U << CAN_F1R2_FB14_Pos) /*!< 0x00004000 */ #define CAN_F1R2_FB14 CAN_F1R2_FB14_Msk /*!<Filter bit 14 */ #define CAN_F1R2_FB15_Pos (15U) #define CAN_F1R2_FB15_Msk (0x1U << CAN_F1R2_FB15_Pos) /*!< 0x00008000 */ #define CAN_F1R2_FB15 CAN_F1R2_FB15_Msk /*!<Filter bit 15 */ #define CAN_F1R2_FB16_Pos (16U) #define CAN_F1R2_FB16_Msk (0x1U << CAN_F1R2_FB16_Pos) /*!< 0x00010000 */ #define CAN_F1R2_FB16 CAN_F1R2_FB16_Msk /*!<Filter bit 16 */ #define CAN_F1R2_FB17_Pos (17U) #define CAN_F1R2_FB17_Msk (0x1U << CAN_F1R2_FB17_Pos) /*!< 0x00020000 */ #define CAN_F1R2_FB17 CAN_F1R2_FB17_Msk /*!<Filter bit 17 */ #define CAN_F1R2_FB18_Pos (18U) #define CAN_F1R2_FB18_Msk (0x1U << CAN_F1R2_FB18_Pos) /*!< 0x00040000 */ #define CAN_F1R2_FB18 CAN_F1R2_FB18_Msk /*!<Filter bit 18 */ #define CAN_F1R2_FB19_Pos (19U) #define CAN_F1R2_FB19_Msk (0x1U << CAN_F1R2_FB19_Pos) /*!< 0x00080000 */ #define CAN_F1R2_FB19 CAN_F1R2_FB19_Msk /*!<Filter bit 19 */ #define CAN_F1R2_FB20_Pos (20U) #define CAN_F1R2_FB20_Msk (0x1U << CAN_F1R2_FB20_Pos) /*!< 0x00100000 */ #define CAN_F1R2_FB20 CAN_F1R2_FB20_Msk /*!<Filter bit 20 */ #define CAN_F1R2_FB21_Pos (21U) #define CAN_F1R2_FB21_Msk (0x1U << CAN_F1R2_FB21_Pos) /*!< 0x00200000 */ #define CAN_F1R2_FB21 CAN_F1R2_FB21_Msk /*!<Filter bit 21 */ #define CAN_F1R2_FB22_Pos (22U) #define CAN_F1R2_FB22_Msk (0x1U << CAN_F1R2_FB22_Pos) /*!< 0x00400000 */ #define CAN_F1R2_FB22 CAN_F1R2_FB22_Msk /*!<Filter bit 22 */ #define CAN_F1R2_FB23_Pos (23U) #define CAN_F1R2_FB23_Msk (0x1U << CAN_F1R2_FB23_Pos) /*!< 0x00800000 */ #define CAN_F1R2_FB23 CAN_F1R2_FB23_Msk /*!<Filter bit 23 */ #define CAN_F1R2_FB24_Pos (24U) #define CAN_F1R2_FB24_Msk (0x1U << CAN_F1R2_FB24_Pos) /*!< 0x01000000 */ #define CAN_F1R2_FB24 CAN_F1R2_FB24_Msk /*!<Filter bit 24 */ #define CAN_F1R2_FB25_Pos (25U) #define CAN_F1R2_FB25_Msk (0x1U << CAN_F1R2_FB25_Pos) /*!< 0x02000000 */ #define CAN_F1R2_FB25 CAN_F1R2_FB25_Msk /*!<Filter bit 25 */ #define CAN_F1R2_FB26_Pos (26U) #define CAN_F1R2_FB26_Msk (0x1U << CAN_F1R2_FB26_Pos) /*!< 0x04000000 */ #define CAN_F1R2_FB26 CAN_F1R2_FB26_Msk /*!<Filter bit 26 */ #define CAN_F1R2_FB27_Pos (27U) #define CAN_F1R2_FB27_Msk (0x1U << CAN_F1R2_FB27_Pos) /*!< 0x08000000 */ #define CAN_F1R2_FB27 CAN_F1R2_FB27_Msk /*!<Filter bit 27 */ #define CAN_F1R2_FB28_Pos (28U) #define CAN_F1R2_FB28_Msk (0x1U << CAN_F1R2_FB28_Pos) /*!< 0x10000000 */ #define CAN_F1R2_FB28 CAN_F1R2_FB28_Msk /*!<Filter bit 28 */ #define CAN_F1R2_FB29_Pos (29U) #define CAN_F1R2_FB29_Msk (0x1U << CAN_F1R2_FB29_Pos) /*!< 0x20000000 */ #define CAN_F1R2_FB29 CAN_F1R2_FB29_Msk /*!<Filter bit 29 */ #define CAN_F1R2_FB30_Pos (30U) #define CAN_F1R2_FB30_Msk (0x1U << CAN_F1R2_FB30_Pos) /*!< 0x40000000 */ #define CAN_F1R2_FB30 CAN_F1R2_FB30_Msk /*!<Filter bit 30 */ #define CAN_F1R2_FB31_Pos (31U) #define CAN_F1R2_FB31_Msk (0x1U << CAN_F1R2_FB31_Pos) /*!< 0x80000000 */ #define CAN_F1R2_FB31 CAN_F1R2_FB31_Msk /*!<Filter bit 31 */ /******************* Bit definition for CAN_F2R2 register *******************/ #define CAN_F2R2_FB0_Pos (0U) #define CAN_F2R2_FB0_Msk (0x1U << CAN_F2R2_FB0_Pos) /*!< 0x00000001 */ #define CAN_F2R2_FB0 CAN_F2R2_FB0_Msk /*!<Filter bit 0 */ #define CAN_F2R2_FB1_Pos (1U) #define CAN_F2R2_FB1_Msk (0x1U << CAN_F2R2_FB1_Pos) /*!< 0x00000002 */ #define CAN_F2R2_FB1 CAN_F2R2_FB1_Msk /*!<Filter bit 1 */ #define CAN_F2R2_FB2_Pos (2U) #define CAN_F2R2_FB2_Msk (0x1U << CAN_F2R2_FB2_Pos) /*!< 0x00000004 */ #define CAN_F2R2_FB2 CAN_F2R2_FB2_Msk /*!<Filter bit 2 */ #define CAN_F2R2_FB3_Pos (3U) #define CAN_F2R2_FB3_Msk (0x1U << CAN_F2R2_FB3_Pos) /*!< 0x00000008 */ #define CAN_F2R2_FB3 CAN_F2R2_FB3_Msk /*!<Filter bit 3 */ #define CAN_F2R2_FB4_Pos (4U) #define CAN_F2R2_FB4_Msk (0x1U << CAN_F2R2_FB4_Pos) /*!< 0x00000010 */ #define CAN_F2R2_FB4 CAN_F2R2_FB4_Msk /*!<Filter bit 4 */ #define CAN_F2R2_FB5_Pos (5U) #define CAN_F2R2_FB5_Msk (0x1U << CAN_F2R2_FB5_Pos) /*!< 0x00000020 */ #define CAN_F2R2_FB5 CAN_F2R2_FB5_Msk /*!<Filter bit 5 */ #define CAN_F2R2_FB6_Pos (6U) #define CAN_F2R2_FB6_Msk (0x1U << CAN_F2R2_FB6_Pos) /*!< 0x00000040 */ #define CAN_F2R2_FB6 CAN_F2R2_FB6_Msk /*!<Filter bit 6 */ #define CAN_F2R2_FB7_Pos (7U) #define CAN_F2R2_FB7_Msk (0x1U << CAN_F2R2_FB7_Pos) /*!< 0x00000080 */ #define CAN_F2R2_FB7 CAN_F2R2_FB7_Msk /*!<Filter bit 7 */ #define CAN_F2R2_FB8_Pos (8U) #define CAN_F2R2_FB8_Msk (0x1U << CAN_F2R2_FB8_Pos) /*!< 0x00000100 */ #define CAN_F2R2_FB8 CAN_F2R2_FB8_Msk /*!<Filter bit 8 */ #define CAN_F2R2_FB9_Pos (9U) #define CAN_F2R2_FB9_Msk (0x1U << CAN_F2R2_FB9_Pos) /*!< 0x00000200 */ #define CAN_F2R2_FB9 CAN_F2R2_FB9_Msk /*!<Filter bit 9 */ #define CAN_F2R2_FB10_Pos (10U) #define CAN_F2R2_FB10_Msk (0x1U << CAN_F2R2_FB10_Pos) /*!< 0x00000400 */ #define CAN_F2R2_FB10 CAN_F2R2_FB10_Msk /*!<Filter bit 10 */ #define CAN_F2R2_FB11_Pos (11U) #define CAN_F2R2_FB11_Msk (0x1U << CAN_F2R2_FB11_Pos) /*!< 0x00000800 */ #define CAN_F2R2_FB11 CAN_F2R2_FB11_Msk /*!<Filter bit 11 */ #define CAN_F2R2_FB12_Pos (12U) #define CAN_F2R2_FB12_Msk (0x1U << CAN_F2R2_FB12_Pos) /*!< 0x00001000 */ #define CAN_F2R2_FB12 CAN_F2R2_FB12_Msk /*!<Filter bit 12 */ #define CAN_F2R2_FB13_Pos (13U) #define CAN_F2R2_FB13_Msk (0x1U << CAN_F2R2_FB13_Pos) /*!< 0x00002000 */ #define CAN_F2R2_FB13 CAN_F2R2_FB13_Msk /*!<Filter bit 13 */ #define CAN_F2R2_FB14_Pos (14U) #define CAN_F2R2_FB14_Msk (0x1U << CAN_F2R2_FB14_Pos) /*!< 0x00004000 */ #define CAN_F2R2_FB14 CAN_F2R2_FB14_Msk /*!<Filter bit 14 */ #define CAN_F2R2_FB15_Pos (15U) #define CAN_F2R2_FB15_Msk (0x1U << CAN_F2R2_FB15_Pos) /*!< 0x00008000 */ #define CAN_F2R2_FB15 CAN_F2R2_FB15_Msk /*!<Filter bit 15 */ #define CAN_F2R2_FB16_Pos (16U) #define CAN_F2R2_FB16_Msk (0x1U << CAN_F2R2_FB16_Pos) /*!< 0x00010000 */ #define CAN_F2R2_FB16 CAN_F2R2_FB16_Msk /*!<Filter bit 16 */ #define CAN_F2R2_FB17_Pos (17U) #define CAN_F2R2_FB17_Msk (0x1U << CAN_F2R2_FB17_Pos) /*!< 0x00020000 */ #define CAN_F2R2_FB17 CAN_F2R2_FB17_Msk /*!<Filter bit 17 */ #define CAN_F2R2_FB18_Pos (18U) #define CAN_F2R2_FB18_Msk (0x1U << CAN_F2R2_FB18_Pos) /*!< 0x00040000 */ #define CAN_F2R2_FB18 CAN_F2R2_FB18_Msk /*!<Filter bit 18 */ #define CAN_F2R2_FB19_Pos (19U) #define CAN_F2R2_FB19_Msk (0x1U << CAN_F2R2_FB19_Pos) /*!< 0x00080000 */ #define CAN_F2R2_FB19 CAN_F2R2_FB19_Msk /*!<Filter bit 19 */ #define CAN_F2R2_FB20_Pos (20U) #define CAN_F2R2_FB20_Msk (0x1U << CAN_F2R2_FB20_Pos) /*!< 0x00100000 */ #define CAN_F2R2_FB20 CAN_F2R2_FB20_Msk /*!<Filter bit 20 */ #define CAN_F2R2_FB21_Pos (21U) #define CAN_F2R2_FB21_Msk (0x1U << CAN_F2R2_FB21_Pos) /*!< 0x00200000 */ #define CAN_F2R2_FB21 CAN_F2R2_FB21_Msk /*!<Filter bit 21 */ #define CAN_F2R2_FB22_Pos (22U) #define CAN_F2R2_FB22_Msk (0x1U << CAN_F2R2_FB22_Pos) /*!< 0x00400000 */ #define CAN_F2R2_FB22 CAN_F2R2_FB22_Msk /*!<Filter bit 22 */ #define CAN_F2R2_FB23_Pos (23U) #define CAN_F2R2_FB23_Msk (0x1U << CAN_F2R2_FB23_Pos) /*!< 0x00800000 */ #define CAN_F2R2_FB23 CAN_F2R2_FB23_Msk /*!<Filter bit 23 */ #define CAN_F2R2_FB24_Pos (24U) #define CAN_F2R2_FB24_Msk (0x1U << CAN_F2R2_FB24_Pos) /*!< 0x01000000 */ #define CAN_F2R2_FB24 CAN_F2R2_FB24_Msk /*!<Filter bit 24 */ #define CAN_F2R2_FB25_Pos (25U) #define CAN_F2R2_FB25_Msk (0x1U << CAN_F2R2_FB25_Pos) /*!< 0x02000000 */ #define CAN_F2R2_FB25 CAN_F2R2_FB25_Msk /*!<Filter bit 25 */ #define CAN_F2R2_FB26_Pos (26U) #define CAN_F2R2_FB26_Msk (0x1U << CAN_F2R2_FB26_Pos) /*!< 0x04000000 */ #define CAN_F2R2_FB26 CAN_F2R2_FB26_Msk /*!<Filter bit 26 */ #define CAN_F2R2_FB27_Pos (27U) #define CAN_F2R2_FB27_Msk (0x1U << CAN_F2R2_FB27_Pos) /*!< 0x08000000 */ #define CAN_F2R2_FB27 CAN_F2R2_FB27_Msk /*!<Filter bit 27 */ #define CAN_F2R2_FB28_Pos (28U) #define CAN_F2R2_FB28_Msk (0x1U << CAN_F2R2_FB28_Pos) /*!< 0x10000000 */ #define CAN_F2R2_FB28 CAN_F2R2_FB28_Msk /*!<Filter bit 28 */ #define CAN_F2R2_FB29_Pos (29U) #define CAN_F2R2_FB29_Msk (0x1U << CAN_F2R2_FB29_Pos) /*!< 0x20000000 */ #define CAN_F2R2_FB29 CAN_F2R2_FB29_Msk /*!<Filter bit 29 */ #define CAN_F2R2_FB30_Pos (30U) #define CAN_F2R2_FB30_Msk (0x1U << CAN_F2R2_FB30_Pos) /*!< 0x40000000 */ #define CAN_F2R2_FB30 CAN_F2R2_FB30_Msk /*!<Filter bit 30 */ #define CAN_F2R2_FB31_Pos (31U) #define CAN_F2R2_FB31_Msk (0x1U << CAN_F2R2_FB31_Pos) /*!< 0x80000000 */ #define CAN_F2R2_FB31 CAN_F2R2_FB31_Msk /*!<Filter bit 31 */ /******************* Bit definition for CAN_F3R2 register *******************/ #define CAN_F3R2_FB0_Pos (0U) #define CAN_F3R2_FB0_Msk (0x1U << CAN_F3R2_FB0_Pos) /*!< 0x00000001 */ #define CAN_F3R2_FB0 CAN_F3R2_FB0_Msk /*!<Filter bit 0 */ #define CAN_F3R2_FB1_Pos (1U) #define CAN_F3R2_FB1_Msk (0x1U << CAN_F3R2_FB1_Pos) /*!< 0x00000002 */ #define CAN_F3R2_FB1 CAN_F3R2_FB1_Msk /*!<Filter bit 1 */ #define CAN_F3R2_FB2_Pos (2U) #define CAN_F3R2_FB2_Msk (0x1U << CAN_F3R2_FB2_Pos) /*!< 0x00000004 */ #define CAN_F3R2_FB2 CAN_F3R2_FB2_Msk /*!<Filter bit 2 */ #define CAN_F3R2_FB3_Pos (3U) #define CAN_F3R2_FB3_Msk (0x1U << CAN_F3R2_FB3_Pos) /*!< 0x00000008 */ #define CAN_F3R2_FB3 CAN_F3R2_FB3_Msk /*!<Filter bit 3 */ #define CAN_F3R2_FB4_Pos (4U) #define CAN_F3R2_FB4_Msk (0x1U << CAN_F3R2_FB4_Pos) /*!< 0x00000010 */ #define CAN_F3R2_FB4 CAN_F3R2_FB4_Msk /*!<Filter bit 4 */ #define CAN_F3R2_FB5_Pos (5U) #define CAN_F3R2_FB5_Msk (0x1U << CAN_F3R2_FB5_Pos) /*!< 0x00000020 */ #define CAN_F3R2_FB5 CAN_F3R2_FB5_Msk /*!<Filter bit 5 */ #define CAN_F3R2_FB6_Pos (6U) #define CAN_F3R2_FB6_Msk (0x1U << CAN_F3R2_FB6_Pos) /*!< 0x00000040 */ #define CAN_F3R2_FB6 CAN_F3R2_FB6_Msk /*!<Filter bit 6 */ #define CAN_F3R2_FB7_Pos (7U) #define CAN_F3R2_FB7_Msk (0x1U << CAN_F3R2_FB7_Pos) /*!< 0x00000080 */ #define CAN_F3R2_FB7 CAN_F3R2_FB7_Msk /*!<Filter bit 7 */ #define CAN_F3R2_FB8_Pos (8U) #define CAN_F3R2_FB8_Msk (0x1U << CAN_F3R2_FB8_Pos) /*!< 0x00000100 */ #define CAN_F3R2_FB8 CAN_F3R2_FB8_Msk /*!<Filter bit 8 */ #define CAN_F3R2_FB9_Pos (9U) #define CAN_F3R2_FB9_Msk (0x1U << CAN_F3R2_FB9_Pos) /*!< 0x00000200 */ #define CAN_F3R2_FB9 CAN_F3R2_FB9_Msk /*!<Filter bit 9 */ #define CAN_F3R2_FB10_Pos (10U) #define CAN_F3R2_FB10_Msk (0x1U << CAN_F3R2_FB10_Pos) /*!< 0x00000400 */ #define CAN_F3R2_FB10 CAN_F3R2_FB10_Msk /*!<Filter bit 10 */ #define CAN_F3R2_FB11_Pos (11U) #define CAN_F3R2_FB11_Msk (0x1U << CAN_F3R2_FB11_Pos) /*!< 0x00000800 */ #define CAN_F3R2_FB11 CAN_F3R2_FB11_Msk /*!<Filter bit 11 */ #define CAN_F3R2_FB12_Pos (12U) #define CAN_F3R2_FB12_Msk (0x1U << CAN_F3R2_FB12_Pos) /*!< 0x00001000 */ #define CAN_F3R2_FB12 CAN_F3R2_FB12_Msk /*!<Filter bit 12 */ #define CAN_F3R2_FB13_Pos (13U) #define CAN_F3R2_FB13_Msk (0x1U << CAN_F3R2_FB13_Pos) /*!< 0x00002000 */ #define CAN_F3R2_FB13 CAN_F3R2_FB13_Msk /*!<Filter bit 13 */ #define CAN_F3R2_FB14_Pos (14U) #define CAN_F3R2_FB14_Msk (0x1U << CAN_F3R2_FB14_Pos) /*!< 0x00004000 */ #define CAN_F3R2_FB14 CAN_F3R2_FB14_Msk /*!<Filter bit 14 */ #define CAN_F3R2_FB15_Pos (15U) #define CAN_F3R2_FB15_Msk (0x1U << CAN_F3R2_FB15_Pos) /*!< 0x00008000 */ #define CAN_F3R2_FB15 CAN_F3R2_FB15_Msk /*!<Filter bit 15 */ #define CAN_F3R2_FB16_Pos (16U) #define CAN_F3R2_FB16_Msk (0x1U << CAN_F3R2_FB16_Pos) /*!< 0x00010000 */ #define CAN_F3R2_FB16 CAN_F3R2_FB16_Msk /*!<Filter bit 16 */ #define CAN_F3R2_FB17_Pos (17U) #define CAN_F3R2_FB17_Msk (0x1U << CAN_F3R2_FB17_Pos) /*!< 0x00020000 */ #define CAN_F3R2_FB17 CAN_F3R2_FB17_Msk /*!<Filter bit 17 */ #define CAN_F3R2_FB18_Pos (18U) #define CAN_F3R2_FB18_Msk (0x1U << CAN_F3R2_FB18_Pos) /*!< 0x00040000 */ #define CAN_F3R2_FB18 CAN_F3R2_FB18_Msk /*!<Filter bit 18 */ #define CAN_F3R2_FB19_Pos (19U) #define CAN_F3R2_FB19_Msk (0x1U << CAN_F3R2_FB19_Pos) /*!< 0x00080000 */ #define CAN_F3R2_FB19 CAN_F3R2_FB19_Msk /*!<Filter bit 19 */ #define CAN_F3R2_FB20_Pos (20U) #define CAN_F3R2_FB20_Msk (0x1U << CAN_F3R2_FB20_Pos) /*!< 0x00100000 */ #define CAN_F3R2_FB20 CAN_F3R2_FB20_Msk /*!<Filter bit 20 */ #define CAN_F3R2_FB21_Pos (21U) #define CAN_F3R2_FB21_Msk (0x1U << CAN_F3R2_FB21_Pos) /*!< 0x00200000 */ #define CAN_F3R2_FB21 CAN_F3R2_FB21_Msk /*!<Filter bit 21 */ #define CAN_F3R2_FB22_Pos (22U) #define CAN_F3R2_FB22_Msk (0x1U << CAN_F3R2_FB22_Pos) /*!< 0x00400000 */ #define CAN_F3R2_FB22 CAN_F3R2_FB22_Msk /*!<Filter bit 22 */ #define CAN_F3R2_FB23_Pos (23U) #define CAN_F3R2_FB23_Msk (0x1U << CAN_F3R2_FB23_Pos) /*!< 0x00800000 */ #define CAN_F3R2_FB23 CAN_F3R2_FB23_Msk /*!<Filter bit 23 */ #define CAN_F3R2_FB24_Pos (24U) #define CAN_F3R2_FB24_Msk (0x1U << CAN_F3R2_FB24_Pos) /*!< 0x01000000 */ #define CAN_F3R2_FB24 CAN_F3R2_FB24_Msk /*!<Filter bit 24 */ #define CAN_F3R2_FB25_Pos (25U) #define CAN_F3R2_FB25_Msk (0x1U << CAN_F3R2_FB25_Pos) /*!< 0x02000000 */ #define CAN_F3R2_FB25 CAN_F3R2_FB25_Msk /*!<Filter bit 25 */ #define CAN_F3R2_FB26_Pos (26U) #define CAN_F3R2_FB26_Msk (0x1U << CAN_F3R2_FB26_Pos) /*!< 0x04000000 */ #define CAN_F3R2_FB26 CAN_F3R2_FB26_Msk /*!<Filter bit 26 */ #define CAN_F3R2_FB27_Pos (27U) #define CAN_F3R2_FB27_Msk (0x1U << CAN_F3R2_FB27_Pos) /*!< 0x08000000 */ #define CAN_F3R2_FB27 CAN_F3R2_FB27_Msk /*!<Filter bit 27 */ #define CAN_F3R2_FB28_Pos (28U) #define CAN_F3R2_FB28_Msk (0x1U << CAN_F3R2_FB28_Pos) /*!< 0x10000000 */ #define CAN_F3R2_FB28 CAN_F3R2_FB28_Msk /*!<Filter bit 28 */ #define CAN_F3R2_FB29_Pos (29U) #define CAN_F3R2_FB29_Msk (0x1U << CAN_F3R2_FB29_Pos) /*!< 0x20000000 */ #define CAN_F3R2_FB29 CAN_F3R2_FB29_Msk /*!<Filter bit 29 */ #define CAN_F3R2_FB30_Pos (30U) #define CAN_F3R2_FB30_Msk (0x1U << CAN_F3R2_FB30_Pos) /*!< 0x40000000 */ #define CAN_F3R2_FB30 CAN_F3R2_FB30_Msk /*!<Filter bit 30 */ #define CAN_F3R2_FB31_Pos (31U) #define CAN_F3R2_FB31_Msk (0x1U << CAN_F3R2_FB31_Pos) /*!< 0x80000000 */ #define CAN_F3R2_FB31 CAN_F3R2_FB31_Msk /*!<Filter bit 31 */ /******************* Bit definition for CAN_F4R2 register *******************/ #define CAN_F4R2_FB0_Pos (0U) #define CAN_F4R2_FB0_Msk (0x1U << CAN_F4R2_FB0_Pos) /*!< 0x00000001 */ #define CAN_F4R2_FB0 CAN_F4R2_FB0_Msk /*!<Filter bit 0 */ #define CAN_F4R2_FB1_Pos (1U) #define CAN_F4R2_FB1_Msk (0x1U << CAN_F4R2_FB1_Pos) /*!< 0x00000002 */ #define CAN_F4R2_FB1 CAN_F4R2_FB1_Msk /*!<Filter bit 1 */ #define CAN_F4R2_FB2_Pos (2U) #define CAN_F4R2_FB2_Msk (0x1U << CAN_F4R2_FB2_Pos) /*!< 0x00000004 */ #define CAN_F4R2_FB2 CAN_F4R2_FB2_Msk /*!<Filter bit 2 */ #define CAN_F4R2_FB3_Pos (3U) #define CAN_F4R2_FB3_Msk (0x1U << CAN_F4R2_FB3_Pos) /*!< 0x00000008 */ #define CAN_F4R2_FB3 CAN_F4R2_FB3_Msk /*!<Filter bit 3 */ #define CAN_F4R2_FB4_Pos (4U) #define CAN_F4R2_FB4_Msk (0x1U << CAN_F4R2_FB4_Pos) /*!< 0x00000010 */ #define CAN_F4R2_FB4 CAN_F4R2_FB4_Msk /*!<Filter bit 4 */ #define CAN_F4R2_FB5_Pos (5U) #define CAN_F4R2_FB5_Msk (0x1U << CAN_F4R2_FB5_Pos) /*!< 0x00000020 */ #define CAN_F4R2_FB5 CAN_F4R2_FB5_Msk /*!<Filter bit 5 */ #define CAN_F4R2_FB6_Pos (6U) #define CAN_F4R2_FB6_Msk (0x1U << CAN_F4R2_FB6_Pos) /*!< 0x00000040 */ #define CAN_F4R2_FB6 CAN_F4R2_FB6_Msk /*!<Filter bit 6 */ #define CAN_F4R2_FB7_Pos (7U) #define CAN_F4R2_FB7_Msk (0x1U << CAN_F4R2_FB7_Pos) /*!< 0x00000080 */ #define CAN_F4R2_FB7 CAN_F4R2_FB7_Msk /*!<Filter bit 7 */ #define CAN_F4R2_FB8_Pos (8U) #define CAN_F4R2_FB8_Msk (0x1U << CAN_F4R2_FB8_Pos) /*!< 0x00000100 */ #define CAN_F4R2_FB8 CAN_F4R2_FB8_Msk /*!<Filter bit 8 */ #define CAN_F4R2_FB9_Pos (9U) #define CAN_F4R2_FB9_Msk (0x1U << CAN_F4R2_FB9_Pos) /*!< 0x00000200 */ #define CAN_F4R2_FB9 CAN_F4R2_FB9_Msk /*!<Filter bit 9 */ #define CAN_F4R2_FB10_Pos (10U) #define CAN_F4R2_FB10_Msk (0x1U << CAN_F4R2_FB10_Pos) /*!< 0x00000400 */ #define CAN_F4R2_FB10 CAN_F4R2_FB10_Msk /*!<Filter bit 10 */ #define CAN_F4R2_FB11_Pos (11U) #define CAN_F4R2_FB11_Msk (0x1U << CAN_F4R2_FB11_Pos) /*!< 0x00000800 */ #define CAN_F4R2_FB11 CAN_F4R2_FB11_Msk /*!<Filter bit 11 */ #define CAN_F4R2_FB12_Pos (12U) #define CAN_F4R2_FB12_Msk (0x1U << CAN_F4R2_FB12_Pos) /*!< 0x00001000 */ #define CAN_F4R2_FB12 CAN_F4R2_FB12_Msk /*!<Filter bit 12 */ #define CAN_F4R2_FB13_Pos (13U) #define CAN_F4R2_FB13_Msk (0x1U << CAN_F4R2_FB13_Pos) /*!< 0x00002000 */ #define CAN_F4R2_FB13 CAN_F4R2_FB13_Msk /*!<Filter bit 13 */ #define CAN_F4R2_FB14_Pos (14U) #define CAN_F4R2_FB14_Msk (0x1U << CAN_F4R2_FB14_Pos) /*!< 0x00004000 */ #define CAN_F4R2_FB14 CAN_F4R2_FB14_Msk /*!<Filter bit 14 */ #define CAN_F4R2_FB15_Pos (15U) #define CAN_F4R2_FB15_Msk (0x1U << CAN_F4R2_FB15_Pos) /*!< 0x00008000 */ #define CAN_F4R2_FB15 CAN_F4R2_FB15_Msk /*!<Filter bit 15 */ #define CAN_F4R2_FB16_Pos (16U) #define CAN_F4R2_FB16_Msk (0x1U << CAN_F4R2_FB16_Pos) /*!< 0x00010000 */ #define CAN_F4R2_FB16 CAN_F4R2_FB16_Msk /*!<Filter bit 16 */ #define CAN_F4R2_FB17_Pos (17U) #define CAN_F4R2_FB17_Msk (0x1U << CAN_F4R2_FB17_Pos) /*!< 0x00020000 */ #define CAN_F4R2_FB17 CAN_F4R2_FB17_Msk /*!<Filter bit 17 */ #define CAN_F4R2_FB18_Pos (18U) #define CAN_F4R2_FB18_Msk (0x1U << CAN_F4R2_FB18_Pos) /*!< 0x00040000 */ #define CAN_F4R2_FB18 CAN_F4R2_FB18_Msk /*!<Filter bit 18 */ #define CAN_F4R2_FB19_Pos (19U) #define CAN_F4R2_FB19_Msk (0x1U << CAN_F4R2_FB19_Pos) /*!< 0x00080000 */ #define CAN_F4R2_FB19 CAN_F4R2_FB19_Msk /*!<Filter bit 19 */ #define CAN_F4R2_FB20_Pos (20U) #define CAN_F4R2_FB20_Msk (0x1U << CAN_F4R2_FB20_Pos) /*!< 0x00100000 */ #define CAN_F4R2_FB20 CAN_F4R2_FB20_Msk /*!<Filter bit 20 */ #define CAN_F4R2_FB21_Pos (21U) #define CAN_F4R2_FB21_Msk (0x1U << CAN_F4R2_FB21_Pos) /*!< 0x00200000 */ #define CAN_F4R2_FB21 CAN_F4R2_FB21_Msk /*!<Filter bit 21 */ #define CAN_F4R2_FB22_Pos (22U) #define CAN_F4R2_FB22_Msk (0x1U << CAN_F4R2_FB22_Pos) /*!< 0x00400000 */ #define CAN_F4R2_FB22 CAN_F4R2_FB22_Msk /*!<Filter bit 22 */ #define CAN_F4R2_FB23_Pos (23U) #define CAN_F4R2_FB23_Msk (0x1U << CAN_F4R2_FB23_Pos) /*!< 0x00800000 */ #define CAN_F4R2_FB23 CAN_F4R2_FB23_Msk /*!<Filter bit 23 */ #define CAN_F4R2_FB24_Pos (24U) #define CAN_F4R2_FB24_Msk (0x1U << CAN_F4R2_FB24_Pos) /*!< 0x01000000 */ #define CAN_F4R2_FB24 CAN_F4R2_FB24_Msk /*!<Filter bit 24 */ #define CAN_F4R2_FB25_Pos (25U) #define CAN_F4R2_FB25_Msk (0x1U << CAN_F4R2_FB25_Pos) /*!< 0x02000000 */ #define CAN_F4R2_FB25 CAN_F4R2_FB25_Msk /*!<Filter bit 25 */ #define CAN_F4R2_FB26_Pos (26U) #define CAN_F4R2_FB26_Msk (0x1U << CAN_F4R2_FB26_Pos) /*!< 0x04000000 */ #define CAN_F4R2_FB26 CAN_F4R2_FB26_Msk /*!<Filter bit 26 */ #define CAN_F4R2_FB27_Pos (27U) #define CAN_F4R2_FB27_Msk (0x1U << CAN_F4R2_FB27_Pos) /*!< 0x08000000 */ #define CAN_F4R2_FB27 CAN_F4R2_FB27_Msk /*!<Filter bit 27 */ #define CAN_F4R2_FB28_Pos (28U) #define CAN_F4R2_FB28_Msk (0x1U << CAN_F4R2_FB28_Pos) /*!< 0x10000000 */ #define CAN_F4R2_FB28 CAN_F4R2_FB28_Msk /*!<Filter bit 28 */ #define CAN_F4R2_FB29_Pos (29U) #define CAN_F4R2_FB29_Msk (0x1U << CAN_F4R2_FB29_Pos) /*!< 0x20000000 */ #define CAN_F4R2_FB29 CAN_F4R2_FB29_Msk /*!<Filter bit 29 */ #define CAN_F4R2_FB30_Pos (30U) #define CAN_F4R2_FB30_Msk (0x1U << CAN_F4R2_FB30_Pos) /*!< 0x40000000 */ #define CAN_F4R2_FB30 CAN_F4R2_FB30_Msk /*!<Filter bit 30 */ #define CAN_F4R2_FB31_Pos (31U) #define CAN_F4R2_FB31_Msk (0x1U << CAN_F4R2_FB31_Pos) /*!< 0x80000000 */ #define CAN_F4R2_FB31 CAN_F4R2_FB31_Msk /*!<Filter bit 31 */ /******************* Bit definition for CAN_F5R2 register *******************/ #define CAN_F5R2_FB0_Pos (0U) #define CAN_F5R2_FB0_Msk (0x1U << CAN_F5R2_FB0_Pos) /*!< 0x00000001 */ #define CAN_F5R2_FB0 CAN_F5R2_FB0_Msk /*!<Filter bit 0 */ #define CAN_F5R2_FB1_Pos (1U) #define CAN_F5R2_FB1_Msk (0x1U << CAN_F5R2_FB1_Pos) /*!< 0x00000002 */ #define CAN_F5R2_FB1 CAN_F5R2_FB1_Msk /*!<Filter bit 1 */ #define CAN_F5R2_FB2_Pos (2U) #define CAN_F5R2_FB2_Msk (0x1U << CAN_F5R2_FB2_Pos) /*!< 0x00000004 */ #define CAN_F5R2_FB2 CAN_F5R2_FB2_Msk /*!<Filter bit 2 */ #define CAN_F5R2_FB3_Pos (3U) #define CAN_F5R2_FB3_Msk (0x1U << CAN_F5R2_FB3_Pos) /*!< 0x00000008 */ #define CAN_F5R2_FB3 CAN_F5R2_FB3_Msk /*!<Filter bit 3 */ #define CAN_F5R2_FB4_Pos (4U) #define CAN_F5R2_FB4_Msk (0x1U << CAN_F5R2_FB4_Pos) /*!< 0x00000010 */ #define CAN_F5R2_FB4 CAN_F5R2_FB4_Msk /*!<Filter bit 4 */ #define CAN_F5R2_FB5_Pos (5U) #define CAN_F5R2_FB5_Msk (0x1U << CAN_F5R2_FB5_Pos) /*!< 0x00000020 */ #define CAN_F5R2_FB5 CAN_F5R2_FB5_Msk /*!<Filter bit 5 */ #define CAN_F5R2_FB6_Pos (6U) #define CAN_F5R2_FB6_Msk (0x1U << CAN_F5R2_FB6_Pos) /*!< 0x00000040 */ #define CAN_F5R2_FB6 CAN_F5R2_FB6_Msk /*!<Filter bit 6 */ #define CAN_F5R2_FB7_Pos (7U) #define CAN_F5R2_FB7_Msk (0x1U << CAN_F5R2_FB7_Pos) /*!< 0x00000080 */ #define CAN_F5R2_FB7 CAN_F5R2_FB7_Msk /*!<Filter bit 7 */ #define CAN_F5R2_FB8_Pos (8U) #define CAN_F5R2_FB8_Msk (0x1U << CAN_F5R2_FB8_Pos) /*!< 0x00000100 */ #define CAN_F5R2_FB8 CAN_F5R2_FB8_Msk /*!<Filter bit 8 */ #define CAN_F5R2_FB9_Pos (9U) #define CAN_F5R2_FB9_Msk (0x1U << CAN_F5R2_FB9_Pos) /*!< 0x00000200 */ #define CAN_F5R2_FB9 CAN_F5R2_FB9_Msk /*!<Filter bit 9 */ #define CAN_F5R2_FB10_Pos (10U) #define CAN_F5R2_FB10_Msk (0x1U << CAN_F5R2_FB10_Pos) /*!< 0x00000400 */ #define CAN_F5R2_FB10 CAN_F5R2_FB10_Msk /*!<Filter bit 10 */ #define CAN_F5R2_FB11_Pos (11U) #define CAN_F5R2_FB11_Msk (0x1U << CAN_F5R2_FB11_Pos) /*!< 0x00000800 */ #define CAN_F5R2_FB11 CAN_F5R2_FB11_Msk /*!<Filter bit 11 */ #define CAN_F5R2_FB12_Pos (12U) #define CAN_F5R2_FB12_Msk (0x1U << CAN_F5R2_FB12_Pos) /*!< 0x00001000 */ #define CAN_F5R2_FB12 CAN_F5R2_FB12_Msk /*!<Filter bit 12 */ #define CAN_F5R2_FB13_Pos (13U) #define CAN_F5R2_FB13_Msk (0x1U << CAN_F5R2_FB13_Pos) /*!< 0x00002000 */ #define CAN_F5R2_FB13 CAN_F5R2_FB13_Msk /*!<Filter bit 13 */ #define CAN_F5R2_FB14_Pos (14U) #define CAN_F5R2_FB14_Msk (0x1U << CAN_F5R2_FB14_Pos) /*!< 0x00004000 */ #define CAN_F5R2_FB14 CAN_F5R2_FB14_Msk /*!<Filter bit 14 */ #define CAN_F5R2_FB15_Pos (15U) #define CAN_F5R2_FB15_Msk (0x1U << CAN_F5R2_FB15_Pos) /*!< 0x00008000 */ #define CAN_F5R2_FB15 CAN_F5R2_FB15_Msk /*!<Filter bit 15 */ #define CAN_F5R2_FB16_Pos (16U) #define CAN_F5R2_FB16_Msk (0x1U << CAN_F5R2_FB16_Pos) /*!< 0x00010000 */ #define CAN_F5R2_FB16 CAN_F5R2_FB16_Msk /*!<Filter bit 16 */ #define CAN_F5R2_FB17_Pos (17U) #define CAN_F5R2_FB17_Msk (0x1U << CAN_F5R2_FB17_Pos) /*!< 0x00020000 */ #define CAN_F5R2_FB17 CAN_F5R2_FB17_Msk /*!<Filter bit 17 */ #define CAN_F5R2_FB18_Pos (18U) #define CAN_F5R2_FB18_Msk (0x1U << CAN_F5R2_FB18_Pos) /*!< 0x00040000 */ #define CAN_F5R2_FB18 CAN_F5R2_FB18_Msk /*!<Filter bit 18 */ #define CAN_F5R2_FB19_Pos (19U) #define CAN_F5R2_FB19_Msk (0x1U << CAN_F5R2_FB19_Pos) /*!< 0x00080000 */ #define CAN_F5R2_FB19 CAN_F5R2_FB19_Msk /*!<Filter bit 19 */ #define CAN_F5R2_FB20_Pos (20U) #define CAN_F5R2_FB20_Msk (0x1U << CAN_F5R2_FB20_Pos) /*!< 0x00100000 */ #define CAN_F5R2_FB20 CAN_F5R2_FB20_Msk /*!<Filter bit 20 */ #define CAN_F5R2_FB21_Pos (21U) #define CAN_F5R2_FB21_Msk (0x1U << CAN_F5R2_FB21_Pos) /*!< 0x00200000 */ #define CAN_F5R2_FB21 CAN_F5R2_FB21_Msk /*!<Filter bit 21 */ #define CAN_F5R2_FB22_Pos (22U) #define CAN_F5R2_FB22_Msk (0x1U << CAN_F5R2_FB22_Pos) /*!< 0x00400000 */ #define CAN_F5R2_FB22 CAN_F5R2_FB22_Msk /*!<Filter bit 22 */ #define CAN_F5R2_FB23_Pos (23U) #define CAN_F5R2_FB23_Msk (0x1U << CAN_F5R2_FB23_Pos) /*!< 0x00800000 */ #define CAN_F5R2_FB23 CAN_F5R2_FB23_Msk /*!<Filter bit 23 */ #define CAN_F5R2_FB24_Pos (24U) #define CAN_F5R2_FB24_Msk (0x1U << CAN_F5R2_FB24_Pos) /*!< 0x01000000 */ #define CAN_F5R2_FB24 CAN_F5R2_FB24_Msk /*!<Filter bit 24 */ #define CAN_F5R2_FB25_Pos (25U) #define CAN_F5R2_FB25_Msk (0x1U << CAN_F5R2_FB25_Pos) /*!< 0x02000000 */ #define CAN_F5R2_FB25 CAN_F5R2_FB25_Msk /*!<Filter bit 25 */ #define CAN_F5R2_FB26_Pos (26U) #define CAN_F5R2_FB26_Msk (0x1U << CAN_F5R2_FB26_Pos) /*!< 0x04000000 */ #define CAN_F5R2_FB26 CAN_F5R2_FB26_Msk /*!<Filter bit 26 */ #define CAN_F5R2_FB27_Pos (27U) #define CAN_F5R2_FB27_Msk (0x1U << CAN_F5R2_FB27_Pos) /*!< 0x08000000 */ #define CAN_F5R2_FB27 CAN_F5R2_FB27_Msk /*!<Filter bit 27 */ #define CAN_F5R2_FB28_Pos (28U) #define CAN_F5R2_FB28_Msk (0x1U << CAN_F5R2_FB28_Pos) /*!< 0x10000000 */ #define CAN_F5R2_FB28 CAN_F5R2_FB28_Msk /*!<Filter bit 28 */ #define CAN_F5R2_FB29_Pos (29U) #define CAN_F5R2_FB29_Msk (0x1U << CAN_F5R2_FB29_Pos) /*!< 0x20000000 */ #define CAN_F5R2_FB29 CAN_F5R2_FB29_Msk /*!<Filter bit 29 */ #define CAN_F5R2_FB30_Pos (30U) #define CAN_F5R2_FB30_Msk (0x1U << CAN_F5R2_FB30_Pos) /*!< 0x40000000 */ #define CAN_F5R2_FB30 CAN_F5R2_FB30_Msk /*!<Filter bit 30 */ #define CAN_F5R2_FB31_Pos (31U) #define CAN_F5R2_FB31_Msk (0x1U << CAN_F5R2_FB31_Pos) /*!< 0x80000000 */ #define CAN_F5R2_FB31 CAN_F5R2_FB31_Msk /*!<Filter bit 31 */ /******************* Bit definition for CAN_F6R2 register *******************/ #define CAN_F6R2_FB0_Pos (0U) #define CAN_F6R2_FB0_Msk (0x1U << CAN_F6R2_FB0_Pos) /*!< 0x00000001 */ #define CAN_F6R2_FB0 CAN_F6R2_FB0_Msk /*!<Filter bit 0 */ #define CAN_F6R2_FB1_Pos (1U) #define CAN_F6R2_FB1_Msk (0x1U << CAN_F6R2_FB1_Pos) /*!< 0x00000002 */ #define CAN_F6R2_FB1 CAN_F6R2_FB1_Msk /*!<Filter bit 1 */ #define CAN_F6R2_FB2_Pos (2U) #define CAN_F6R2_FB2_Msk (0x1U << CAN_F6R2_FB2_Pos) /*!< 0x00000004 */ #define CAN_F6R2_FB2 CAN_F6R2_FB2_Msk /*!<Filter bit 2 */ #define CAN_F6R2_FB3_Pos (3U) #define CAN_F6R2_FB3_Msk (0x1U << CAN_F6R2_FB3_Pos) /*!< 0x00000008 */ #define CAN_F6R2_FB3 CAN_F6R2_FB3_Msk /*!<Filter bit 3 */ #define CAN_F6R2_FB4_Pos (4U) #define CAN_F6R2_FB4_Msk (0x1U << CAN_F6R2_FB4_Pos) /*!< 0x00000010 */ #define CAN_F6R2_FB4 CAN_F6R2_FB4_Msk /*!<Filter bit 4 */ #define CAN_F6R2_FB5_Pos (5U) #define CAN_F6R2_FB5_Msk (0x1U << CAN_F6R2_FB5_Pos) /*!< 0x00000020 */ #define CAN_F6R2_FB5 CAN_F6R2_FB5_Msk /*!<Filter bit 5 */ #define CAN_F6R2_FB6_Pos (6U) #define CAN_F6R2_FB6_Msk (0x1U << CAN_F6R2_FB6_Pos) /*!< 0x00000040 */ #define CAN_F6R2_FB6 CAN_F6R2_FB6_Msk /*!<Filter bit 6 */ #define CAN_F6R2_FB7_Pos (7U) #define CAN_F6R2_FB7_Msk (0x1U << CAN_F6R2_FB7_Pos) /*!< 0x00000080 */ #define CAN_F6R2_FB7 CAN_F6R2_FB7_Msk /*!<Filter bit 7 */ #define CAN_F6R2_FB8_Pos (8U) #define CAN_F6R2_FB8_Msk (0x1U << CAN_F6R2_FB8_Pos) /*!< 0x00000100 */ #define CAN_F6R2_FB8 CAN_F6R2_FB8_Msk /*!<Filter bit 8 */ #define CAN_F6R2_FB9_Pos (9U) #define CAN_F6R2_FB9_Msk (0x1U << CAN_F6R2_FB9_Pos) /*!< 0x00000200 */ #define CAN_F6R2_FB9 CAN_F6R2_FB9_Msk /*!<Filter bit 9 */ #define CAN_F6R2_FB10_Pos (10U) #define CAN_F6R2_FB10_Msk (0x1U << CAN_F6R2_FB10_Pos) /*!< 0x00000400 */ #define CAN_F6R2_FB10 CAN_F6R2_FB10_Msk /*!<Filter bit 10 */ #define CAN_F6R2_FB11_Pos (11U) #define CAN_F6R2_FB11_Msk (0x1U << CAN_F6R2_FB11_Pos) /*!< 0x00000800 */ #define CAN_F6R2_FB11 CAN_F6R2_FB11_Msk /*!<Filter bit 11 */ #define CAN_F6R2_FB12_Pos (12U) #define CAN_F6R2_FB12_Msk (0x1U << CAN_F6R2_FB12_Pos) /*!< 0x00001000 */ #define CAN_F6R2_FB12 CAN_F6R2_FB12_Msk /*!<Filter bit 12 */ #define CAN_F6R2_FB13_Pos (13U) #define CAN_F6R2_FB13_Msk (0x1U << CAN_F6R2_FB13_Pos) /*!< 0x00002000 */ #define CAN_F6R2_FB13 CAN_F6R2_FB13_Msk /*!<Filter bit 13 */ #define CAN_F6R2_FB14_Pos (14U) #define CAN_F6R2_FB14_Msk (0x1U << CAN_F6R2_FB14_Pos) /*!< 0x00004000 */ #define CAN_F6R2_FB14 CAN_F6R2_FB14_Msk /*!<Filter bit 14 */ #define CAN_F6R2_FB15_Pos (15U) #define CAN_F6R2_FB15_Msk (0x1U << CAN_F6R2_FB15_Pos) /*!< 0x00008000 */ #define CAN_F6R2_FB15 CAN_F6R2_FB15_Msk /*!<Filter bit 15 */ #define CAN_F6R2_FB16_Pos (16U) #define CAN_F6R2_FB16_Msk (0x1U << CAN_F6R2_FB16_Pos) /*!< 0x00010000 */ #define CAN_F6R2_FB16 CAN_F6R2_FB16_Msk /*!<Filter bit 16 */ #define CAN_F6R2_FB17_Pos (17U) #define CAN_F6R2_FB17_Msk (0x1U << CAN_F6R2_FB17_Pos) /*!< 0x00020000 */ #define CAN_F6R2_FB17 CAN_F6R2_FB17_Msk /*!<Filter bit 17 */ #define CAN_F6R2_FB18_Pos (18U) #define CAN_F6R2_FB18_Msk (0x1U << CAN_F6R2_FB18_Pos) /*!< 0x00040000 */ #define CAN_F6R2_FB18 CAN_F6R2_FB18_Msk /*!<Filter bit 18 */ #define CAN_F6R2_FB19_Pos (19U) #define CAN_F6R2_FB19_Msk (0x1U << CAN_F6R2_FB19_Pos) /*!< 0x00080000 */ #define CAN_F6R2_FB19 CAN_F6R2_FB19_Msk /*!<Filter bit 19 */ #define CAN_F6R2_FB20_Pos (20U) #define CAN_F6R2_FB20_Msk (0x1U << CAN_F6R2_FB20_Pos) /*!< 0x00100000 */ #define CAN_F6R2_FB20 CAN_F6R2_FB20_Msk /*!<Filter bit 20 */ #define CAN_F6R2_FB21_Pos (21U) #define CAN_F6R2_FB21_Msk (0x1U << CAN_F6R2_FB21_Pos) /*!< 0x00200000 */ #define CAN_F6R2_FB21 CAN_F6R2_FB21_Msk /*!<Filter bit 21 */ #define CAN_F6R2_FB22_Pos (22U) #define CAN_F6R2_FB22_Msk (0x1U << CAN_F6R2_FB22_Pos) /*!< 0x00400000 */ #define CAN_F6R2_FB22 CAN_F6R2_FB22_Msk /*!<Filter bit 22 */ #define CAN_F6R2_FB23_Pos (23U) #define CAN_F6R2_FB23_Msk (0x1U << CAN_F6R2_FB23_Pos) /*!< 0x00800000 */ #define CAN_F6R2_FB23 CAN_F6R2_FB23_Msk /*!<Filter bit 23 */ #define CAN_F6R2_FB24_Pos (24U) #define CAN_F6R2_FB24_Msk (0x1U << CAN_F6R2_FB24_Pos) /*!< 0x01000000 */ #define CAN_F6R2_FB24 CAN_F6R2_FB24_Msk /*!<Filter bit 24 */ #define CAN_F6R2_FB25_Pos (25U) #define CAN_F6R2_FB25_Msk (0x1U << CAN_F6R2_FB25_Pos) /*!< 0x02000000 */ #define CAN_F6R2_FB25 CAN_F6R2_FB25_Msk /*!<Filter bit 25 */ #define CAN_F6R2_FB26_Pos (26U) #define CAN_F6R2_FB26_Msk (0x1U << CAN_F6R2_FB26_Pos) /*!< 0x04000000 */ #define CAN_F6R2_FB26 CAN_F6R2_FB26_Msk /*!<Filter bit 26 */ #define CAN_F6R2_FB27_Pos (27U) #define CAN_F6R2_FB27_Msk (0x1U << CAN_F6R2_FB27_Pos) /*!< 0x08000000 */ #define CAN_F6R2_FB27 CAN_F6R2_FB27_Msk /*!<Filter bit 27 */ #define CAN_F6R2_FB28_Pos (28U) #define CAN_F6R2_FB28_Msk (0x1U << CAN_F6R2_FB28_Pos) /*!< 0x10000000 */ #define CAN_F6R2_FB28 CAN_F6R2_FB28_Msk /*!<Filter bit 28 */ #define CAN_F6R2_FB29_Pos (29U) #define CAN_F6R2_FB29_Msk (0x1U << CAN_F6R2_FB29_Pos) /*!< 0x20000000 */ #define CAN_F6R2_FB29 CAN_F6R2_FB29_Msk /*!<Filter bit 29 */ #define CAN_F6R2_FB30_Pos (30U) #define CAN_F6R2_FB30_Msk (0x1U << CAN_F6R2_FB30_Pos) /*!< 0x40000000 */ #define CAN_F6R2_FB30 CAN_F6R2_FB30_Msk /*!<Filter bit 30 */ #define CAN_F6R2_FB31_Pos (31U) #define CAN_F6R2_FB31_Msk (0x1U << CAN_F6R2_FB31_Pos) /*!< 0x80000000 */ #define CAN_F6R2_FB31 CAN_F6R2_FB31_Msk /*!<Filter bit 31 */ /******************* Bit definition for CAN_F7R2 register *******************/ #define CAN_F7R2_FB0_Pos (0U) #define CAN_F7R2_FB0_Msk (0x1U << CAN_F7R2_FB0_Pos) /*!< 0x00000001 */ #define CAN_F7R2_FB0 CAN_F7R2_FB0_Msk /*!<Filter bit 0 */ #define CAN_F7R2_FB1_Pos (1U) #define CAN_F7R2_FB1_Msk (0x1U << CAN_F7R2_FB1_Pos) /*!< 0x00000002 */ #define CAN_F7R2_FB1 CAN_F7R2_FB1_Msk /*!<Filter bit 1 */ #define CAN_F7R2_FB2_Pos (2U) #define CAN_F7R2_FB2_Msk (0x1U << CAN_F7R2_FB2_Pos) /*!< 0x00000004 */ #define CAN_F7R2_FB2 CAN_F7R2_FB2_Msk /*!<Filter bit 2 */ #define CAN_F7R2_FB3_Pos (3U) #define CAN_F7R2_FB3_Msk (0x1U << CAN_F7R2_FB3_Pos) /*!< 0x00000008 */ #define CAN_F7R2_FB3 CAN_F7R2_FB3_Msk /*!<Filter bit 3 */ #define CAN_F7R2_FB4_Pos (4U) #define CAN_F7R2_FB4_Msk (0x1U << CAN_F7R2_FB4_Pos) /*!< 0x00000010 */ #define CAN_F7R2_FB4 CAN_F7R2_FB4_Msk /*!<Filter bit 4 */ #define CAN_F7R2_FB5_Pos (5U) #define CAN_F7R2_FB5_Msk (0x1U << CAN_F7R2_FB5_Pos) /*!< 0x00000020 */ #define CAN_F7R2_FB5 CAN_F7R2_FB5_Msk /*!<Filter bit 5 */ #define CAN_F7R2_FB6_Pos (6U) #define CAN_F7R2_FB6_Msk (0x1U << CAN_F7R2_FB6_Pos) /*!< 0x00000040 */ #define CAN_F7R2_FB6 CAN_F7R2_FB6_Msk /*!<Filter bit 6 */ #define CAN_F7R2_FB7_Pos (7U) #define CAN_F7R2_FB7_Msk (0x1U << CAN_F7R2_FB7_Pos) /*!< 0x00000080 */ #define CAN_F7R2_FB7 CAN_F7R2_FB7_Msk /*!<Filter bit 7 */ #define CAN_F7R2_FB8_Pos (8U) #define CAN_F7R2_FB8_Msk (0x1U << CAN_F7R2_FB8_Pos) /*!< 0x00000100 */ #define CAN_F7R2_FB8 CAN_F7R2_FB8_Msk /*!<Filter bit 8 */ #define CAN_F7R2_FB9_Pos (9U) #define CAN_F7R2_FB9_Msk (0x1U << CAN_F7R2_FB9_Pos) /*!< 0x00000200 */ #define CAN_F7R2_FB9 CAN_F7R2_FB9_Msk /*!<Filter bit 9 */ #define CAN_F7R2_FB10_Pos (10U) #define CAN_F7R2_FB10_Msk (0x1U << CAN_F7R2_FB10_Pos) /*!< 0x00000400 */ #define CAN_F7R2_FB10 CAN_F7R2_FB10_Msk /*!<Filter bit 10 */ #define CAN_F7R2_FB11_Pos (11U) #define CAN_F7R2_FB11_Msk (0x1U << CAN_F7R2_FB11_Pos) /*!< 0x00000800 */ #define CAN_F7R2_FB11 CAN_F7R2_FB11_Msk /*!<Filter bit 11 */ #define CAN_F7R2_FB12_Pos (12U) #define CAN_F7R2_FB12_Msk (0x1U << CAN_F7R2_FB12_Pos) /*!< 0x00001000 */ #define CAN_F7R2_FB12 CAN_F7R2_FB12_Msk /*!<Filter bit 12 */ #define CAN_F7R2_FB13_Pos (13U) #define CAN_F7R2_FB13_Msk (0x1U << CAN_F7R2_FB13_Pos) /*!< 0x00002000 */ #define CAN_F7R2_FB13 CAN_F7R2_FB13_Msk /*!<Filter bit 13 */ #define CAN_F7R2_FB14_Pos (14U) #define CAN_F7R2_FB14_Msk (0x1U << CAN_F7R2_FB14_Pos) /*!< 0x00004000 */ #define CAN_F7R2_FB14 CAN_F7R2_FB14_Msk /*!<Filter bit 14 */ #define CAN_F7R2_FB15_Pos (15U) #define CAN_F7R2_FB15_Msk (0x1U << CAN_F7R2_FB15_Pos) /*!< 0x00008000 */ #define CAN_F7R2_FB15 CAN_F7R2_FB15_Msk /*!<Filter bit 15 */ #define CAN_F7R2_FB16_Pos (16U) #define CAN_F7R2_FB16_Msk (0x1U << CAN_F7R2_FB16_Pos) /*!< 0x00010000 */ #define CAN_F7R2_FB16 CAN_F7R2_FB16_Msk /*!<Filter bit 16 */ #define CAN_F7R2_FB17_Pos (17U) #define CAN_F7R2_FB17_Msk (0x1U << CAN_F7R2_FB17_Pos) /*!< 0x00020000 */ #define CAN_F7R2_FB17 CAN_F7R2_FB17_Msk /*!<Filter bit 17 */ #define CAN_F7R2_FB18_Pos (18U) #define CAN_F7R2_FB18_Msk (0x1U << CAN_F7R2_FB18_Pos) /*!< 0x00040000 */ #define CAN_F7R2_FB18 CAN_F7R2_FB18_Msk /*!<Filter bit 18 */ #define CAN_F7R2_FB19_Pos (19U) #define CAN_F7R2_FB19_Msk (0x1U << CAN_F7R2_FB19_Pos) /*!< 0x00080000 */ #define CAN_F7R2_FB19 CAN_F7R2_FB19_Msk /*!<Filter bit 19 */ #define CAN_F7R2_FB20_Pos (20U) #define CAN_F7R2_FB20_Msk (0x1U << CAN_F7R2_FB20_Pos) /*!< 0x00100000 */ #define CAN_F7R2_FB20 CAN_F7R2_FB20_Msk /*!<Filter bit 20 */ #define CAN_F7R2_FB21_Pos (21U) #define CAN_F7R2_FB21_Msk (0x1U << CAN_F7R2_FB21_Pos) /*!< 0x00200000 */ #define CAN_F7R2_FB21 CAN_F7R2_FB21_Msk /*!<Filter bit 21 */ #define CAN_F7R2_FB22_Pos (22U) #define CAN_F7R2_FB22_Msk (0x1U << CAN_F7R2_FB22_Pos) /*!< 0x00400000 */ #define CAN_F7R2_FB22 CAN_F7R2_FB22_Msk /*!<Filter bit 22 */ #define CAN_F7R2_FB23_Pos (23U) #define CAN_F7R2_FB23_Msk (0x1U << CAN_F7R2_FB23_Pos) /*!< 0x00800000 */ #define CAN_F7R2_FB23 CAN_F7R2_FB23_Msk /*!<Filter bit 23 */ #define CAN_F7R2_FB24_Pos (24U) #define CAN_F7R2_FB24_Msk (0x1U << CAN_F7R2_FB24_Pos) /*!< 0x01000000 */ #define CAN_F7R2_FB24 CAN_F7R2_FB24_Msk /*!<Filter bit 24 */ #define CAN_F7R2_FB25_Pos (25U) #define CAN_F7R2_FB25_Msk (0x1U << CAN_F7R2_FB25_Pos) /*!< 0x02000000 */ #define CAN_F7R2_FB25 CAN_F7R2_FB25_Msk /*!<Filter bit 25 */ #define CAN_F7R2_FB26_Pos (26U) #define CAN_F7R2_FB26_Msk (0x1U << CAN_F7R2_FB26_Pos) /*!< 0x04000000 */ #define CAN_F7R2_FB26 CAN_F7R2_FB26_Msk /*!<Filter bit 26 */ #define CAN_F7R2_FB27_Pos (27U) #define CAN_F7R2_FB27_Msk (0x1U << CAN_F7R2_FB27_Pos) /*!< 0x08000000 */ #define CAN_F7R2_FB27 CAN_F7R2_FB27_Msk /*!<Filter bit 27 */ #define CAN_F7R2_FB28_Pos (28U) #define CAN_F7R2_FB28_Msk (0x1U << CAN_F7R2_FB28_Pos) /*!< 0x10000000 */ #define CAN_F7R2_FB28 CAN_F7R2_FB28_Msk /*!<Filter bit 28 */ #define CAN_F7R2_FB29_Pos (29U) #define CAN_F7R2_FB29_Msk (0x1U << CAN_F7R2_FB29_Pos) /*!< 0x20000000 */ #define CAN_F7R2_FB29 CAN_F7R2_FB29_Msk /*!<Filter bit 29 */ #define CAN_F7R2_FB30_Pos (30U) #define CAN_F7R2_FB30_Msk (0x1U << CAN_F7R2_FB30_Pos) /*!< 0x40000000 */ #define CAN_F7R2_FB30 CAN_F7R2_FB30_Msk /*!<Filter bit 30 */ #define CAN_F7R2_FB31_Pos (31U) #define CAN_F7R2_FB31_Msk (0x1U << CAN_F7R2_FB31_Pos) /*!< 0x80000000 */ #define CAN_F7R2_FB31 CAN_F7R2_FB31_Msk /*!<Filter bit 31 */ /******************* Bit definition for CAN_F8R2 register *******************/ #define CAN_F8R2_FB0_Pos (0U) #define CAN_F8R2_FB0_Msk (0x1U << CAN_F8R2_FB0_Pos) /*!< 0x00000001 */ #define CAN_F8R2_FB0 CAN_F8R2_FB0_Msk /*!<Filter bit 0 */ #define CAN_F8R2_FB1_Pos (1U) #define CAN_F8R2_FB1_Msk (0x1U << CAN_F8R2_FB1_Pos) /*!< 0x00000002 */ #define CAN_F8R2_FB1 CAN_F8R2_FB1_Msk /*!<Filter bit 1 */ #define CAN_F8R2_FB2_Pos (2U) #define CAN_F8R2_FB2_Msk (0x1U << CAN_F8R2_FB2_Pos) /*!< 0x00000004 */ #define CAN_F8R2_FB2 CAN_F8R2_FB2_Msk /*!<Filter bit 2 */ #define CAN_F8R2_FB3_Pos (3U) #define CAN_F8R2_FB3_Msk (0x1U << CAN_F8R2_FB3_Pos) /*!< 0x00000008 */ #define CAN_F8R2_FB3 CAN_F8R2_FB3_Msk /*!<Filter bit 3 */ #define CAN_F8R2_FB4_Pos (4U) #define CAN_F8R2_FB4_Msk (0x1U << CAN_F8R2_FB4_Pos) /*!< 0x00000010 */ #define CAN_F8R2_FB4 CAN_F8R2_FB4_Msk /*!<Filter bit 4 */ #define CAN_F8R2_FB5_Pos (5U) #define CAN_F8R2_FB5_Msk (0x1U << CAN_F8R2_FB5_Pos) /*!< 0x00000020 */ #define CAN_F8R2_FB5 CAN_F8R2_FB5_Msk /*!<Filter bit 5 */ #define CAN_F8R2_FB6_Pos (6U) #define CAN_F8R2_FB6_Msk (0x1U << CAN_F8R2_FB6_Pos) /*!< 0x00000040 */ #define CAN_F8R2_FB6 CAN_F8R2_FB6_Msk /*!<Filter bit 6 */ #define CAN_F8R2_FB7_Pos (7U) #define CAN_F8R2_FB7_Msk (0x1U << CAN_F8R2_FB7_Pos) /*!< 0x00000080 */ #define CAN_F8R2_FB7 CAN_F8R2_FB7_Msk /*!<Filter bit 7 */ #define CAN_F8R2_FB8_Pos (8U) #define CAN_F8R2_FB8_Msk (0x1U << CAN_F8R2_FB8_Pos) /*!< 0x00000100 */ #define CAN_F8R2_FB8 CAN_F8R2_FB8_Msk /*!<Filter bit 8 */ #define CAN_F8R2_FB9_Pos (9U) #define CAN_F8R2_FB9_Msk (0x1U << CAN_F8R2_FB9_Pos) /*!< 0x00000200 */ #define CAN_F8R2_FB9 CAN_F8R2_FB9_Msk /*!<Filter bit 9 */ #define CAN_F8R2_FB10_Pos (10U) #define CAN_F8R2_FB10_Msk (0x1U << CAN_F8R2_FB10_Pos) /*!< 0x00000400 */ #define CAN_F8R2_FB10 CAN_F8R2_FB10_Msk /*!<Filter bit 10 */ #define CAN_F8R2_FB11_Pos (11U) #define CAN_F8R2_FB11_Msk (0x1U << CAN_F8R2_FB11_Pos) /*!< 0x00000800 */ #define CAN_F8R2_FB11 CAN_F8R2_FB11_Msk /*!<Filter bit 11 */ #define CAN_F8R2_FB12_Pos (12U) #define CAN_F8R2_FB12_Msk (0x1U << CAN_F8R2_FB12_Pos) /*!< 0x00001000 */ #define CAN_F8R2_FB12 CAN_F8R2_FB12_Msk /*!<Filter bit 12 */ #define CAN_F8R2_FB13_Pos (13U) #define CAN_F8R2_FB13_Msk (0x1U << CAN_F8R2_FB13_Pos) /*!< 0x00002000 */ #define CAN_F8R2_FB13 CAN_F8R2_FB13_Msk /*!<Filter bit 13 */ #define CAN_F8R2_FB14_Pos (14U) #define CAN_F8R2_FB14_Msk (0x1U << CAN_F8R2_FB14_Pos) /*!< 0x00004000 */ #define CAN_F8R2_FB14 CAN_F8R2_FB14_Msk /*!<Filter bit 14 */ #define CAN_F8R2_FB15_Pos (15U) #define CAN_F8R2_FB15_Msk (0x1U << CAN_F8R2_FB15_Pos) /*!< 0x00008000 */ #define CAN_F8R2_FB15 CAN_F8R2_FB15_Msk /*!<Filter bit 15 */ #define CAN_F8R2_FB16_Pos (16U) #define CAN_F8R2_FB16_Msk (0x1U << CAN_F8R2_FB16_Pos) /*!< 0x00010000 */ #define CAN_F8R2_FB16 CAN_F8R2_FB16_Msk /*!<Filter bit 16 */ #define CAN_F8R2_FB17_Pos (17U) #define CAN_F8R2_FB17_Msk (0x1U << CAN_F8R2_FB17_Pos) /*!< 0x00020000 */ #define CAN_F8R2_FB17 CAN_F8R2_FB17_Msk /*!<Filter bit 17 */ #define CAN_F8R2_FB18_Pos (18U) #define CAN_F8R2_FB18_Msk (0x1U << CAN_F8R2_FB18_Pos) /*!< 0x00040000 */ #define CAN_F8R2_FB18 CAN_F8R2_FB18_Msk /*!<Filter bit 18 */ #define CAN_F8R2_FB19_Pos (19U) #define CAN_F8R2_FB19_Msk (0x1U << CAN_F8R2_FB19_Pos) /*!< 0x00080000 */ #define CAN_F8R2_FB19 CAN_F8R2_FB19_Msk /*!<Filter bit 19 */ #define CAN_F8R2_FB20_Pos (20U) #define CAN_F8R2_FB20_Msk (0x1U << CAN_F8R2_FB20_Pos) /*!< 0x00100000 */ #define CAN_F8R2_FB20 CAN_F8R2_FB20_Msk /*!<Filter bit 20 */ #define CAN_F8R2_FB21_Pos (21U) #define CAN_F8R2_FB21_Msk (0x1U << CAN_F8R2_FB21_Pos) /*!< 0x00200000 */ #define CAN_F8R2_FB21 CAN_F8R2_FB21_Msk /*!<Filter bit 21 */ #define CAN_F8R2_FB22_Pos (22U) #define CAN_F8R2_FB22_Msk (0x1U << CAN_F8R2_FB22_Pos) /*!< 0x00400000 */ #define CAN_F8R2_FB22 CAN_F8R2_FB22_Msk /*!<Filter bit 22 */ #define CAN_F8R2_FB23_Pos (23U) #define CAN_F8R2_FB23_Msk (0x1U << CAN_F8R2_FB23_Pos) /*!< 0x00800000 */ #define CAN_F8R2_FB23 CAN_F8R2_FB23_Msk /*!<Filter bit 23 */ #define CAN_F8R2_FB24_Pos (24U) #define CAN_F8R2_FB24_Msk (0x1U << CAN_F8R2_FB24_Pos) /*!< 0x01000000 */ #define CAN_F8R2_FB24 CAN_F8R2_FB24_Msk /*!<Filter bit 24 */ #define CAN_F8R2_FB25_Pos (25U) #define CAN_F8R2_FB25_Msk (0x1U << CAN_F8R2_FB25_Pos) /*!< 0x02000000 */ #define CAN_F8R2_FB25 CAN_F8R2_FB25_Msk /*!<Filter bit 25 */ #define CAN_F8R2_FB26_Pos (26U) #define CAN_F8R2_FB26_Msk (0x1U << CAN_F8R2_FB26_Pos) /*!< 0x04000000 */ #define CAN_F8R2_FB26 CAN_F8R2_FB26_Msk /*!<Filter bit 26 */ #define CAN_F8R2_FB27_Pos (27U) #define CAN_F8R2_FB27_Msk (0x1U << CAN_F8R2_FB27_Pos) /*!< 0x08000000 */ #define CAN_F8R2_FB27 CAN_F8R2_FB27_Msk /*!<Filter bit 27 */ #define CAN_F8R2_FB28_Pos (28U) #define CAN_F8R2_FB28_Msk (0x1U << CAN_F8R2_FB28_Pos) /*!< 0x10000000 */ #define CAN_F8R2_FB28 CAN_F8R2_FB28_Msk /*!<Filter bit 28 */ #define CAN_F8R2_FB29_Pos (29U) #define CAN_F8R2_FB29_Msk (0x1U << CAN_F8R2_FB29_Pos) /*!< 0x20000000 */ #define CAN_F8R2_FB29 CAN_F8R2_FB29_Msk /*!<Filter bit 29 */ #define CAN_F8R2_FB30_Pos (30U) #define CAN_F8R2_FB30_Msk (0x1U << CAN_F8R2_FB30_Pos) /*!< 0x40000000 */ #define CAN_F8R2_FB30 CAN_F8R2_FB30_Msk /*!<Filter bit 30 */ #define CAN_F8R2_FB31_Pos (31U) #define CAN_F8R2_FB31_Msk (0x1U << CAN_F8R2_FB31_Pos) /*!< 0x80000000 */ #define CAN_F8R2_FB31 CAN_F8R2_FB31_Msk /*!<Filter bit 31 */ /******************* Bit definition for CAN_F9R2 register *******************/ #define CAN_F9R2_FB0_Pos (0U) #define CAN_F9R2_FB0_Msk (0x1U << CAN_F9R2_FB0_Pos) /*!< 0x00000001 */ #define CAN_F9R2_FB0 CAN_F9R2_FB0_Msk /*!<Filter bit 0 */ #define CAN_F9R2_FB1_Pos (1U) #define CAN_F9R2_FB1_Msk (0x1U << CAN_F9R2_FB1_Pos) /*!< 0x00000002 */ #define CAN_F9R2_FB1 CAN_F9R2_FB1_Msk /*!<Filter bit 1 */ #define CAN_F9R2_FB2_Pos (2U) #define CAN_F9R2_FB2_Msk (0x1U << CAN_F9R2_FB2_Pos) /*!< 0x00000004 */ #define CAN_F9R2_FB2 CAN_F9R2_FB2_Msk /*!<Filter bit 2 */ #define CAN_F9R2_FB3_Pos (3U) #define CAN_F9R2_FB3_Msk (0x1U << CAN_F9R2_FB3_Pos) /*!< 0x00000008 */ #define CAN_F9R2_FB3 CAN_F9R2_FB3_Msk /*!<Filter bit 3 */ #define CAN_F9R2_FB4_Pos (4U) #define CAN_F9R2_FB4_Msk (0x1U << CAN_F9R2_FB4_Pos) /*!< 0x00000010 */ #define CAN_F9R2_FB4 CAN_F9R2_FB4_Msk /*!<Filter bit 4 */ #define CAN_F9R2_FB5_Pos (5U) #define CAN_F9R2_FB5_Msk (0x1U << CAN_F9R2_FB5_Pos) /*!< 0x00000020 */ #define CAN_F9R2_FB5 CAN_F9R2_FB5_Msk /*!<Filter bit 5 */ #define CAN_F9R2_FB6_Pos (6U) #define CAN_F9R2_FB6_Msk (0x1U << CAN_F9R2_FB6_Pos) /*!< 0x00000040 */ #define CAN_F9R2_FB6 CAN_F9R2_FB6_Msk /*!<Filter bit 6 */ #define CAN_F9R2_FB7_Pos (7U) #define CAN_F9R2_FB7_Msk (0x1U << CAN_F9R2_FB7_Pos) /*!< 0x00000080 */ #define CAN_F9R2_FB7 CAN_F9R2_FB7_Msk /*!<Filter bit 7 */ #define CAN_F9R2_FB8_Pos (8U) #define CAN_F9R2_FB8_Msk (0x1U << CAN_F9R2_FB8_Pos) /*!< 0x00000100 */ #define CAN_F9R2_FB8 CAN_F9R2_FB8_Msk /*!<Filter bit 8 */ #define CAN_F9R2_FB9_Pos (9U) #define CAN_F9R2_FB9_Msk (0x1U << CAN_F9R2_FB9_Pos) /*!< 0x00000200 */ #define CAN_F9R2_FB9 CAN_F9R2_FB9_Msk /*!<Filter bit 9 */ #define CAN_F9R2_FB10_Pos (10U) #define CAN_F9R2_FB10_Msk (0x1U << CAN_F9R2_FB10_Pos) /*!< 0x00000400 */ #define CAN_F9R2_FB10 CAN_F9R2_FB10_Msk /*!<Filter bit 10 */ #define CAN_F9R2_FB11_Pos (11U) #define CAN_F9R2_FB11_Msk (0x1U << CAN_F9R2_FB11_Pos) /*!< 0x00000800 */ #define CAN_F9R2_FB11 CAN_F9R2_FB11_Msk /*!<Filter bit 11 */ #define CAN_F9R2_FB12_Pos (12U) #define CAN_F9R2_FB12_Msk (0x1U << CAN_F9R2_FB12_Pos) /*!< 0x00001000 */ #define CAN_F9R2_FB12 CAN_F9R2_FB12_Msk /*!<Filter bit 12 */ #define CAN_F9R2_FB13_Pos (13U) #define CAN_F9R2_FB13_Msk (0x1U << CAN_F9R2_FB13_Pos) /*!< 0x00002000 */ #define CAN_F9R2_FB13 CAN_F9R2_FB13_Msk /*!<Filter bit 13 */ #define CAN_F9R2_FB14_Pos (14U) #define CAN_F9R2_FB14_Msk (0x1U << CAN_F9R2_FB14_Pos) /*!< 0x00004000 */ #define CAN_F9R2_FB14 CAN_F9R2_FB14_Msk /*!<Filter bit 14 */ #define CAN_F9R2_FB15_Pos (15U) #define CAN_F9R2_FB15_Msk (0x1U << CAN_F9R2_FB15_Pos) /*!< 0x00008000 */ #define CAN_F9R2_FB15 CAN_F9R2_FB15_Msk /*!<Filter bit 15 */ #define CAN_F9R2_FB16_Pos (16U) #define CAN_F9R2_FB16_Msk (0x1U << CAN_F9R2_FB16_Pos) /*!< 0x00010000 */ #define CAN_F9R2_FB16 CAN_F9R2_FB16_Msk /*!<Filter bit 16 */ #define CAN_F9R2_FB17_Pos (17U) #define CAN_F9R2_FB17_Msk (0x1U << CAN_F9R2_FB17_Pos) /*!< 0x00020000 */ #define CAN_F9R2_FB17 CAN_F9R2_FB17_Msk /*!<Filter bit 17 */ #define CAN_F9R2_FB18_Pos (18U) #define CAN_F9R2_FB18_Msk (0x1U << CAN_F9R2_FB18_Pos) /*!< 0x00040000 */ #define CAN_F9R2_FB18 CAN_F9R2_FB18_Msk /*!<Filter bit 18 */ #define CAN_F9R2_FB19_Pos (19U) #define CAN_F9R2_FB19_Msk (0x1U << CAN_F9R2_FB19_Pos) /*!< 0x00080000 */ #define CAN_F9R2_FB19 CAN_F9R2_FB19_Msk /*!<Filter bit 19 */ #define CAN_F9R2_FB20_Pos (20U) #define CAN_F9R2_FB20_Msk (0x1U << CAN_F9R2_FB20_Pos) /*!< 0x00100000 */ #define CAN_F9R2_FB20 CAN_F9R2_FB20_Msk /*!<Filter bit 20 */ #define CAN_F9R2_FB21_Pos (21U) #define CAN_F9R2_FB21_Msk (0x1U << CAN_F9R2_FB21_Pos) /*!< 0x00200000 */ #define CAN_F9R2_FB21 CAN_F9R2_FB21_Msk /*!<Filter bit 21 */ #define CAN_F9R2_FB22_Pos (22U) #define CAN_F9R2_FB22_Msk (0x1U << CAN_F9R2_FB22_Pos) /*!< 0x00400000 */ #define CAN_F9R2_FB22 CAN_F9R2_FB22_Msk /*!<Filter bit 22 */ #define CAN_F9R2_FB23_Pos (23U) #define CAN_F9R2_FB23_Msk (0x1U << CAN_F9R2_FB23_Pos) /*!< 0x00800000 */ #define CAN_F9R2_FB23 CAN_F9R2_FB23_Msk /*!<Filter bit 23 */ #define CAN_F9R2_FB24_Pos (24U) #define CAN_F9R2_FB24_Msk (0x1U << CAN_F9R2_FB24_Pos) /*!< 0x01000000 */ #define CAN_F9R2_FB24 CAN_F9R2_FB24_Msk /*!<Filter bit 24 */ #define CAN_F9R2_FB25_Pos (25U) #define CAN_F9R2_FB25_Msk (0x1U << CAN_F9R2_FB25_Pos) /*!< 0x02000000 */ #define CAN_F9R2_FB25 CAN_F9R2_FB25_Msk /*!<Filter bit 25 */ #define CAN_F9R2_FB26_Pos (26U) #define CAN_F9R2_FB26_Msk (0x1U << CAN_F9R2_FB26_Pos) /*!< 0x04000000 */ #define CAN_F9R2_FB26 CAN_F9R2_FB26_Msk /*!<Filter bit 26 */ #define CAN_F9R2_FB27_Pos (27U) #define CAN_F9R2_FB27_Msk (0x1U << CAN_F9R2_FB27_Pos) /*!< 0x08000000 */ #define CAN_F9R2_FB27 CAN_F9R2_FB27_Msk /*!<Filter bit 27 */ #define CAN_F9R2_FB28_Pos (28U) #define CAN_F9R2_FB28_Msk (0x1U << CAN_F9R2_FB28_Pos) /*!< 0x10000000 */ #define CAN_F9R2_FB28 CAN_F9R2_FB28_Msk /*!<Filter bit 28 */ #define CAN_F9R2_FB29_Pos (29U) #define CAN_F9R2_FB29_Msk (0x1U << CAN_F9R2_FB29_Pos) /*!< 0x20000000 */ #define CAN_F9R2_FB29 CAN_F9R2_FB29_Msk /*!<Filter bit 29 */ #define CAN_F9R2_FB30_Pos (30U) #define CAN_F9R2_FB30_Msk (0x1U << CAN_F9R2_FB30_Pos) /*!< 0x40000000 */ #define CAN_F9R2_FB30 CAN_F9R2_FB30_Msk /*!<Filter bit 30 */ #define CAN_F9R2_FB31_Pos (31U) #define CAN_F9R2_FB31_Msk (0x1U << CAN_F9R2_FB31_Pos) /*!< 0x80000000 */ #define CAN_F9R2_FB31 CAN_F9R2_FB31_Msk /*!<Filter bit 31 */ /******************* Bit definition for CAN_F10R2 register ******************/ #define CAN_F10R2_FB0_Pos (0U) #define CAN_F10R2_FB0_Msk (0x1U << CAN_F10R2_FB0_Pos) /*!< 0x00000001 */ #define CAN_F10R2_FB0 CAN_F10R2_FB0_Msk /*!<Filter bit 0 */ #define CAN_F10R2_FB1_Pos (1U) #define CAN_F10R2_FB1_Msk (0x1U << CAN_F10R2_FB1_Pos) /*!< 0x00000002 */ #define CAN_F10R2_FB1 CAN_F10R2_FB1_Msk /*!<Filter bit 1 */ #define CAN_F10R2_FB2_Pos (2U) #define CAN_F10R2_FB2_Msk (0x1U << CAN_F10R2_FB2_Pos) /*!< 0x00000004 */ #define CAN_F10R2_FB2 CAN_F10R2_FB2_Msk /*!<Filter bit 2 */ #define CAN_F10R2_FB3_Pos (3U) #define CAN_F10R2_FB3_Msk (0x1U << CAN_F10R2_FB3_Pos) /*!< 0x00000008 */ #define CAN_F10R2_FB3 CAN_F10R2_FB3_Msk /*!<Filter bit 3 */ #define CAN_F10R2_FB4_Pos (4U) #define CAN_F10R2_FB4_Msk (0x1U << CAN_F10R2_FB4_Pos) /*!< 0x00000010 */ #define CAN_F10R2_FB4 CAN_F10R2_FB4_Msk /*!<Filter bit 4 */ #define CAN_F10R2_FB5_Pos (5U) #define CAN_F10R2_FB5_Msk (0x1U << CAN_F10R2_FB5_Pos) /*!< 0x00000020 */ #define CAN_F10R2_FB5 CAN_F10R2_FB5_Msk /*!<Filter bit 5 */ #define CAN_F10R2_FB6_Pos (6U) #define CAN_F10R2_FB6_Msk (0x1U << CAN_F10R2_FB6_Pos) /*!< 0x00000040 */ #define CAN_F10R2_FB6 CAN_F10R2_FB6_Msk /*!<Filter bit 6 */ #define CAN_F10R2_FB7_Pos (7U) #define CAN_F10R2_FB7_Msk (0x1U << CAN_F10R2_FB7_Pos) /*!< 0x00000080 */ #define CAN_F10R2_FB7 CAN_F10R2_FB7_Msk /*!<Filter bit 7 */ #define CAN_F10R2_FB8_Pos (8U) #define CAN_F10R2_FB8_Msk (0x1U << CAN_F10R2_FB8_Pos) /*!< 0x00000100 */ #define CAN_F10R2_FB8 CAN_F10R2_FB8_Msk /*!<Filter bit 8 */ #define CAN_F10R2_FB9_Pos (9U) #define CAN_F10R2_FB9_Msk (0x1U << CAN_F10R2_FB9_Pos) /*!< 0x00000200 */ #define CAN_F10R2_FB9 CAN_F10R2_FB9_Msk /*!<Filter bit 9 */ #define CAN_F10R2_FB10_Pos (10U) #define CAN_F10R2_FB10_Msk (0x1U << CAN_F10R2_FB10_Pos) /*!< 0x00000400 */ #define CAN_F10R2_FB10 CAN_F10R2_FB10_Msk /*!<Filter bit 10 */ #define CAN_F10R2_FB11_Pos (11U) #define CAN_F10R2_FB11_Msk (0x1U << CAN_F10R2_FB11_Pos) /*!< 0x00000800 */ #define CAN_F10R2_FB11 CAN_F10R2_FB11_Msk /*!<Filter bit 11 */ #define CAN_F10R2_FB12_Pos (12U) #define CAN_F10R2_FB12_Msk (0x1U << CAN_F10R2_FB12_Pos) /*!< 0x00001000 */ #define CAN_F10R2_FB12 CAN_F10R2_FB12_Msk /*!<Filter bit 12 */ #define CAN_F10R2_FB13_Pos (13U) #define CAN_F10R2_FB13_Msk (0x1U << CAN_F10R2_FB13_Pos) /*!< 0x00002000 */ #define CAN_F10R2_FB13 CAN_F10R2_FB13_Msk /*!<Filter bit 13 */ #define CAN_F10R2_FB14_Pos (14U) #define CAN_F10R2_FB14_Msk (0x1U << CAN_F10R2_FB14_Pos) /*!< 0x00004000 */ #define CAN_F10R2_FB14 CAN_F10R2_FB14_Msk /*!<Filter bit 14 */ #define CAN_F10R2_FB15_Pos (15U) #define CAN_F10R2_FB15_Msk (0x1U << CAN_F10R2_FB15_Pos) /*!< 0x00008000 */ #define CAN_F10R2_FB15 CAN_F10R2_FB15_Msk /*!<Filter bit 15 */ #define CAN_F10R2_FB16_Pos (16U) #define CAN_F10R2_FB16_Msk (0x1U << CAN_F10R2_FB16_Pos) /*!< 0x00010000 */ #define CAN_F10R2_FB16 CAN_F10R2_FB16_Msk /*!<Filter bit 16 */ #define CAN_F10R2_FB17_Pos (17U) #define CAN_F10R2_FB17_Msk (0x1U << CAN_F10R2_FB17_Pos) /*!< 0x00020000 */ #define CAN_F10R2_FB17 CAN_F10R2_FB17_Msk /*!<Filter bit 17 */ #define CAN_F10R2_FB18_Pos (18U) #define CAN_F10R2_FB18_Msk (0x1U << CAN_F10R2_FB18_Pos) /*!< 0x00040000 */ #define CAN_F10R2_FB18 CAN_F10R2_FB18_Msk /*!<Filter bit 18 */ #define CAN_F10R2_FB19_Pos (19U) #define CAN_F10R2_FB19_Msk (0x1U << CAN_F10R2_FB19_Pos) /*!< 0x00080000 */ #define CAN_F10R2_FB19 CAN_F10R2_FB19_Msk /*!<Filter bit 19 */ #define CAN_F10R2_FB20_Pos (20U) #define CAN_F10R2_FB20_Msk (0x1U << CAN_F10R2_FB20_Pos) /*!< 0x00100000 */ #define CAN_F10R2_FB20 CAN_F10R2_FB20_Msk /*!<Filter bit 20 */ #define CAN_F10R2_FB21_Pos (21U) #define CAN_F10R2_FB21_Msk (0x1U << CAN_F10R2_FB21_Pos) /*!< 0x00200000 */ #define CAN_F10R2_FB21 CAN_F10R2_FB21_Msk /*!<Filter bit 21 */ #define CAN_F10R2_FB22_Pos (22U) #define CAN_F10R2_FB22_Msk (0x1U << CAN_F10R2_FB22_Pos) /*!< 0x00400000 */ #define CAN_F10R2_FB22 CAN_F10R2_FB22_Msk /*!<Filter bit 22 */ #define CAN_F10R2_FB23_Pos (23U) #define CAN_F10R2_FB23_Msk (0x1U << CAN_F10R2_FB23_Pos) /*!< 0x00800000 */ #define CAN_F10R2_FB23 CAN_F10R2_FB23_Msk /*!<Filter bit 23 */ #define CAN_F10R2_FB24_Pos (24U) #define CAN_F10R2_FB24_Msk (0x1U << CAN_F10R2_FB24_Pos) /*!< 0x01000000 */ #define CAN_F10R2_FB24 CAN_F10R2_FB24_Msk /*!<Filter bit 24 */ #define CAN_F10R2_FB25_Pos (25U) #define CAN_F10R2_FB25_Msk (0x1U << CAN_F10R2_FB25_Pos) /*!< 0x02000000 */ #define CAN_F10R2_FB25 CAN_F10R2_FB25_Msk /*!<Filter bit 25 */ #define CAN_F10R2_FB26_Pos (26U) #define CAN_F10R2_FB26_Msk (0x1U << CAN_F10R2_FB26_Pos) /*!< 0x04000000 */ #define CAN_F10R2_FB26 CAN_F10R2_FB26_Msk /*!<Filter bit 26 */ #define CAN_F10R2_FB27_Pos (27U) #define CAN_F10R2_FB27_Msk (0x1U << CAN_F10R2_FB27_Pos) /*!< 0x08000000 */ #define CAN_F10R2_FB27 CAN_F10R2_FB27_Msk /*!<Filter bit 27 */ #define CAN_F10R2_FB28_Pos (28U) #define CAN_F10R2_FB28_Msk (0x1U << CAN_F10R2_FB28_Pos) /*!< 0x10000000 */ #define CAN_F10R2_FB28 CAN_F10R2_FB28_Msk /*!<Filter bit 28 */ #define CAN_F10R2_FB29_Pos (29U) #define CAN_F10R2_FB29_Msk (0x1U << CAN_F10R2_FB29_Pos) /*!< 0x20000000 */ #define CAN_F10R2_FB29 CAN_F10R2_FB29_Msk /*!<Filter bit 29 */ #define CAN_F10R2_FB30_Pos (30U) #define CAN_F10R2_FB30_Msk (0x1U << CAN_F10R2_FB30_Pos) /*!< 0x40000000 */ #define CAN_F10R2_FB30 CAN_F10R2_FB30_Msk /*!<Filter bit 30 */ #define CAN_F10R2_FB31_Pos (31U) #define CAN_F10R2_FB31_Msk (0x1U << CAN_F10R2_FB31_Pos) /*!< 0x80000000 */ #define CAN_F10R2_FB31 CAN_F10R2_FB31_Msk /*!<Filter bit 31 */ /******************* Bit definition for CAN_F11R2 register ******************/ #define CAN_F11R2_FB0_Pos (0U) #define CAN_F11R2_FB0_Msk (0x1U << CAN_F11R2_FB0_Pos) /*!< 0x00000001 */ #define CAN_F11R2_FB0 CAN_F11R2_FB0_Msk /*!<Filter bit 0 */ #define CAN_F11R2_FB1_Pos (1U) #define CAN_F11R2_FB1_Msk (0x1U << CAN_F11R2_FB1_Pos) /*!< 0x00000002 */ #define CAN_F11R2_FB1 CAN_F11R2_FB1_Msk /*!<Filter bit 1 */ #define CAN_F11R2_FB2_Pos (2U) #define CAN_F11R2_FB2_Msk (0x1U << CAN_F11R2_FB2_Pos) /*!< 0x00000004 */ #define CAN_F11R2_FB2 CAN_F11R2_FB2_Msk /*!<Filter bit 2 */ #define CAN_F11R2_FB3_Pos (3U) #define CAN_F11R2_FB3_Msk (0x1U << CAN_F11R2_FB3_Pos) /*!< 0x00000008 */ #define CAN_F11R2_FB3 CAN_F11R2_FB3_Msk /*!<Filter bit 3 */ #define CAN_F11R2_FB4_Pos (4U) #define CAN_F11R2_FB4_Msk (0x1U << CAN_F11R2_FB4_Pos) /*!< 0x00000010 */ #define CAN_F11R2_FB4 CAN_F11R2_FB4_Msk /*!<Filter bit 4 */ #define CAN_F11R2_FB5_Pos (5U) #define CAN_F11R2_FB5_Msk (0x1U << CAN_F11R2_FB5_Pos) /*!< 0x00000020 */ #define CAN_F11R2_FB5 CAN_F11R2_FB5_Msk /*!<Filter bit 5 */ #define CAN_F11R2_FB6_Pos (6U) #define CAN_F11R2_FB6_Msk (0x1U << CAN_F11R2_FB6_Pos) /*!< 0x00000040 */ #define CAN_F11R2_FB6 CAN_F11R2_FB6_Msk /*!<Filter bit 6 */ #define CAN_F11R2_FB7_Pos (7U) #define CAN_F11R2_FB7_Msk (0x1U << CAN_F11R2_FB7_Pos) /*!< 0x00000080 */ #define CAN_F11R2_FB7 CAN_F11R2_FB7_Msk /*!<Filter bit 7 */ #define CAN_F11R2_FB8_Pos (8U) #define CAN_F11R2_FB8_Msk (0x1U << CAN_F11R2_FB8_Pos) /*!< 0x00000100 */ #define CAN_F11R2_FB8 CAN_F11R2_FB8_Msk /*!<Filter bit 8 */ #define CAN_F11R2_FB9_Pos (9U) #define CAN_F11R2_FB9_Msk (0x1U << CAN_F11R2_FB9_Pos) /*!< 0x00000200 */ #define CAN_F11R2_FB9 CAN_F11R2_FB9_Msk /*!<Filter bit 9 */ #define CAN_F11R2_FB10_Pos (10U) #define CAN_F11R2_FB10_Msk (0x1U << CAN_F11R2_FB10_Pos) /*!< 0x00000400 */ #define CAN_F11R2_FB10 CAN_F11R2_FB10_Msk /*!<Filter bit 10 */ #define CAN_F11R2_FB11_Pos (11U) #define CAN_F11R2_FB11_Msk (0x1U << CAN_F11R2_FB11_Pos) /*!< 0x00000800 */ #define CAN_F11R2_FB11 CAN_F11R2_FB11_Msk /*!<Filter bit 11 */ #define CAN_F11R2_FB12_Pos (12U) #define CAN_F11R2_FB12_Msk (0x1U << CAN_F11R2_FB12_Pos) /*!< 0x00001000 */ #define CAN_F11R2_FB12 CAN_F11R2_FB12_Msk /*!<Filter bit 12 */ #define CAN_F11R2_FB13_Pos (13U) #define CAN_F11R2_FB13_Msk (0x1U << CAN_F11R2_FB13_Pos) /*!< 0x00002000 */ #define CAN_F11R2_FB13 CAN_F11R2_FB13_Msk /*!<Filter bit 13 */ #define CAN_F11R2_FB14_Pos (14U) #define CAN_F11R2_FB14_Msk (0x1U << CAN_F11R2_FB14_Pos) /*!< 0x00004000 */ #define CAN_F11R2_FB14 CAN_F11R2_FB14_Msk /*!<Filter bit 14 */ #define CAN_F11R2_FB15_Pos (15U) #define CAN_F11R2_FB15_Msk (0x1U << CAN_F11R2_FB15_Pos) /*!< 0x00008000 */ #define CAN_F11R2_FB15 CAN_F11R2_FB15_Msk /*!<Filter bit 15 */ #define CAN_F11R2_FB16_Pos (16U) #define CAN_F11R2_FB16_Msk (0x1U << CAN_F11R2_FB16_Pos) /*!< 0x00010000 */ #define CAN_F11R2_FB16 CAN_F11R2_FB16_Msk /*!<Filter bit 16 */ #define CAN_F11R2_FB17_Pos (17U) #define CAN_F11R2_FB17_Msk (0x1U << CAN_F11R2_FB17_Pos) /*!< 0x00020000 */ #define CAN_F11R2_FB17 CAN_F11R2_FB17_Msk /*!<Filter bit 17 */ #define CAN_F11R2_FB18_Pos (18U) #define CAN_F11R2_FB18_Msk (0x1U << CAN_F11R2_FB18_Pos) /*!< 0x00040000 */ #define CAN_F11R2_FB18 CAN_F11R2_FB18_Msk /*!<Filter bit 18 */ #define CAN_F11R2_FB19_Pos (19U) #define CAN_F11R2_FB19_Msk (0x1U << CAN_F11R2_FB19_Pos) /*!< 0x00080000 */ #define CAN_F11R2_FB19 CAN_F11R2_FB19_Msk /*!<Filter bit 19 */ #define CAN_F11R2_FB20_Pos (20U) #define CAN_F11R2_FB20_Msk (0x1U << CAN_F11R2_FB20_Pos) /*!< 0x00100000 */ #define CAN_F11R2_FB20 CAN_F11R2_FB20_Msk /*!<Filter bit 20 */ #define CAN_F11R2_FB21_Pos (21U) #define CAN_F11R2_FB21_Msk (0x1U << CAN_F11R2_FB21_Pos) /*!< 0x00200000 */ #define CAN_F11R2_FB21 CAN_F11R2_FB21_Msk /*!<Filter bit 21 */ #define CAN_F11R2_FB22_Pos (22U) #define CAN_F11R2_FB22_Msk (0x1U << CAN_F11R2_FB22_Pos) /*!< 0x00400000 */ #define CAN_F11R2_FB22 CAN_F11R2_FB22_Msk /*!<Filter bit 22 */ #define CAN_F11R2_FB23_Pos (23U) #define CAN_F11R2_FB23_Msk (0x1U << CAN_F11R2_FB23_Pos) /*!< 0x00800000 */ #define CAN_F11R2_FB23 CAN_F11R2_FB23_Msk /*!<Filter bit 23 */ #define CAN_F11R2_FB24_Pos (24U) #define CAN_F11R2_FB24_Msk (0x1U << CAN_F11R2_FB24_Pos) /*!< 0x01000000 */ #define CAN_F11R2_FB24 CAN_F11R2_FB24_Msk /*!<Filter bit 24 */ #define CAN_F11R2_FB25_Pos (25U) #define CAN_F11R2_FB25_Msk (0x1U << CAN_F11R2_FB25_Pos) /*!< 0x02000000 */ #define CAN_F11R2_FB25 CAN_F11R2_FB25_Msk /*!<Filter bit 25 */ #define CAN_F11R2_FB26_Pos (26U) #define CAN_F11R2_FB26_Msk (0x1U << CAN_F11R2_FB26_Pos) /*!< 0x04000000 */ #define CAN_F11R2_FB26 CAN_F11R2_FB26_Msk /*!<Filter bit 26 */ #define CAN_F11R2_FB27_Pos (27U) #define CAN_F11R2_FB27_Msk (0x1U << CAN_F11R2_FB27_Pos) /*!< 0x08000000 */ #define CAN_F11R2_FB27 CAN_F11R2_FB27_Msk /*!<Filter bit 27 */ #define CAN_F11R2_FB28_Pos (28U) #define CAN_F11R2_FB28_Msk (0x1U << CAN_F11R2_FB28_Pos) /*!< 0x10000000 */ #define CAN_F11R2_FB28 CAN_F11R2_FB28_Msk /*!<Filter bit 28 */ #define CAN_F11R2_FB29_Pos (29U) #define CAN_F11R2_FB29_Msk (0x1U << CAN_F11R2_FB29_Pos) /*!< 0x20000000 */ #define CAN_F11R2_FB29 CAN_F11R2_FB29_Msk /*!<Filter bit 29 */ #define CAN_F11R2_FB30_Pos (30U) #define CAN_F11R2_FB30_Msk (0x1U << CAN_F11R2_FB30_Pos) /*!< 0x40000000 */ #define CAN_F11R2_FB30 CAN_F11R2_FB30_Msk /*!<Filter bit 30 */ #define CAN_F11R2_FB31_Pos (31U) #define CAN_F11R2_FB31_Msk (0x1U << CAN_F11R2_FB31_Pos) /*!< 0x80000000 */ #define CAN_F11R2_FB31 CAN_F11R2_FB31_Msk /*!<Filter bit 31 */ /******************* Bit definition for CAN_F12R2 register ******************/ #define CAN_F12R2_FB0_Pos (0U) #define CAN_F12R2_FB0_Msk (0x1U << CAN_F12R2_FB0_Pos) /*!< 0x00000001 */ #define CAN_F12R2_FB0 CAN_F12R2_FB0_Msk /*!<Filter bit 0 */ #define CAN_F12R2_FB1_Pos (1U) #define CAN_F12R2_FB1_Msk (0x1U << CAN_F12R2_FB1_Pos) /*!< 0x00000002 */ #define CAN_F12R2_FB1 CAN_F12R2_FB1_Msk /*!<Filter bit 1 */ #define CAN_F12R2_FB2_Pos (2U) #define CAN_F12R2_FB2_Msk (0x1U << CAN_F12R2_FB2_Pos) /*!< 0x00000004 */ #define CAN_F12R2_FB2 CAN_F12R2_FB2_Msk /*!<Filter bit 2 */ #define CAN_F12R2_FB3_Pos (3U) #define CAN_F12R2_FB3_Msk (0x1U << CAN_F12R2_FB3_Pos) /*!< 0x00000008 */ #define CAN_F12R2_FB3 CAN_F12R2_FB3_Msk /*!<Filter bit 3 */ #define CAN_F12R2_FB4_Pos (4U) #define CAN_F12R2_FB4_Msk (0x1U << CAN_F12R2_FB4_Pos) /*!< 0x00000010 */ #define CAN_F12R2_FB4 CAN_F12R2_FB4_Msk /*!<Filter bit 4 */ #define CAN_F12R2_FB5_Pos (5U) #define CAN_F12R2_FB5_Msk (0x1U << CAN_F12R2_FB5_Pos) /*!< 0x00000020 */ #define CAN_F12R2_FB5 CAN_F12R2_FB5_Msk /*!<Filter bit 5 */ #define CAN_F12R2_FB6_Pos (6U) #define CAN_F12R2_FB6_Msk (0x1U << CAN_F12R2_FB6_Pos) /*!< 0x00000040 */ #define CAN_F12R2_FB6 CAN_F12R2_FB6_Msk /*!<Filter bit 6 */ #define CAN_F12R2_FB7_Pos (7U) #define CAN_F12R2_FB7_Msk (0x1U << CAN_F12R2_FB7_Pos) /*!< 0x00000080 */ #define CAN_F12R2_FB7 CAN_F12R2_FB7_Msk /*!<Filter bit 7 */ #define CAN_F12R2_FB8_Pos (8U) #define CAN_F12R2_FB8_Msk (0x1U << CAN_F12R2_FB8_Pos) /*!< 0x00000100 */ #define CAN_F12R2_FB8 CAN_F12R2_FB8_Msk /*!<Filter bit 8 */ #define CAN_F12R2_FB9_Pos (9U) #define CAN_F12R2_FB9_Msk (0x1U << CAN_F12R2_FB9_Pos) /*!< 0x00000200 */ #define CAN_F12R2_FB9 CAN_F12R2_FB9_Msk /*!<Filter bit 9 */ #define CAN_F12R2_FB10_Pos (10U) #define CAN_F12R2_FB10_Msk (0x1U << CAN_F12R2_FB10_Pos) /*!< 0x00000400 */ #define CAN_F12R2_FB10 CAN_F12R2_FB10_Msk /*!<Filter bit 10 */ #define CAN_F12R2_FB11_Pos (11U) #define CAN_F12R2_FB11_Msk (0x1U << CAN_F12R2_FB11_Pos) /*!< 0x00000800 */ #define CAN_F12R2_FB11 CAN_F12R2_FB11_Msk /*!<Filter bit 11 */ #define CAN_F12R2_FB12_Pos (12U) #define CAN_F12R2_FB12_Msk (0x1U << CAN_F12R2_FB12_Pos) /*!< 0x00001000 */ #define CAN_F12R2_FB12 CAN_F12R2_FB12_Msk /*!<Filter bit 12 */ #define CAN_F12R2_FB13_Pos (13U) #define CAN_F12R2_FB13_Msk (0x1U << CAN_F12R2_FB13_Pos) /*!< 0x00002000 */ #define CAN_F12R2_FB13 CAN_F12R2_FB13_Msk /*!<Filter bit 13 */ #define CAN_F12R2_FB14_Pos (14U) #define CAN_F12R2_FB14_Msk (0x1U << CAN_F12R2_FB14_Pos) /*!< 0x00004000 */ #define CAN_F12R2_FB14 CAN_F12R2_FB14_Msk /*!<Filter bit 14 */ #define CAN_F12R2_FB15_Pos (15U) #define CAN_F12R2_FB15_Msk (0x1U << CAN_F12R2_FB15_Pos) /*!< 0x00008000 */ #define CAN_F12R2_FB15 CAN_F12R2_FB15_Msk /*!<Filter bit 15 */ #define CAN_F12R2_FB16_Pos (16U) #define CAN_F12R2_FB16_Msk (0x1U << CAN_F12R2_FB16_Pos) /*!< 0x00010000 */ #define CAN_F12R2_FB16 CAN_F12R2_FB16_Msk /*!<Filter bit 16 */ #define CAN_F12R2_FB17_Pos (17U) #define CAN_F12R2_FB17_Msk (0x1U << CAN_F12R2_FB17_Pos) /*!< 0x00020000 */ #define CAN_F12R2_FB17 CAN_F12R2_FB17_Msk /*!<Filter bit 17 */ #define CAN_F12R2_FB18_Pos (18U) #define CAN_F12R2_FB18_Msk (0x1U << CAN_F12R2_FB18_Pos) /*!< 0x00040000 */ #define CAN_F12R2_FB18 CAN_F12R2_FB18_Msk /*!<Filter bit 18 */ #define CAN_F12R2_FB19_Pos (19U) #define CAN_F12R2_FB19_Msk (0x1U << CAN_F12R2_FB19_Pos) /*!< 0x00080000 */ #define CAN_F12R2_FB19 CAN_F12R2_FB19_Msk /*!<Filter bit 19 */ #define CAN_F12R2_FB20_Pos (20U) #define CAN_F12R2_FB20_Msk (0x1U << CAN_F12R2_FB20_Pos) /*!< 0x00100000 */ #define CAN_F12R2_FB20 CAN_F12R2_FB20_Msk /*!<Filter bit 20 */ #define CAN_F12R2_FB21_Pos (21U) #define CAN_F12R2_FB21_Msk (0x1U << CAN_F12R2_FB21_Pos) /*!< 0x00200000 */ #define CAN_F12R2_FB21 CAN_F12R2_FB21_Msk /*!<Filter bit 21 */ #define CAN_F12R2_FB22_Pos (22U) #define CAN_F12R2_FB22_Msk (0x1U << CAN_F12R2_FB22_Pos) /*!< 0x00400000 */ #define CAN_F12R2_FB22 CAN_F12R2_FB22_Msk /*!<Filter bit 22 */ #define CAN_F12R2_FB23_Pos (23U) #define CAN_F12R2_FB23_Msk (0x1U << CAN_F12R2_FB23_Pos) /*!< 0x00800000 */ #define CAN_F12R2_FB23 CAN_F12R2_FB23_Msk /*!<Filter bit 23 */ #define CAN_F12R2_FB24_Pos (24U) #define CAN_F12R2_FB24_Msk (0x1U << CAN_F12R2_FB24_Pos) /*!< 0x01000000 */ #define CAN_F12R2_FB24 CAN_F12R2_FB24_Msk /*!<Filter bit 24 */ #define CAN_F12R2_FB25_Pos (25U) #define CAN_F12R2_FB25_Msk (0x1U << CAN_F12R2_FB25_Pos) /*!< 0x02000000 */ #define CAN_F12R2_FB25 CAN_F12R2_FB25_Msk /*!<Filter bit 25 */ #define CAN_F12R2_FB26_Pos (26U) #define CAN_F12R2_FB26_Msk (0x1U << CAN_F12R2_FB26_Pos) /*!< 0x04000000 */ #define CAN_F12R2_FB26 CAN_F12R2_FB26_Msk /*!<Filter bit 26 */ #define CAN_F12R2_FB27_Pos (27U) #define CAN_F12R2_FB27_Msk (0x1U << CAN_F12R2_FB27_Pos) /*!< 0x08000000 */ #define CAN_F12R2_FB27 CAN_F12R2_FB27_Msk /*!<Filter bit 27 */ #define CAN_F12R2_FB28_Pos (28U) #define CAN_F12R2_FB28_Msk (0x1U << CAN_F12R2_FB28_Pos) /*!< 0x10000000 */ #define CAN_F12R2_FB28 CAN_F12R2_FB28_Msk /*!<Filter bit 28 */ #define CAN_F12R2_FB29_Pos (29U) #define CAN_F12R2_FB29_Msk (0x1U << CAN_F12R2_FB29_Pos) /*!< 0x20000000 */ #define CAN_F12R2_FB29 CAN_F12R2_FB29_Msk /*!<Filter bit 29 */ #define CAN_F12R2_FB30_Pos (30U) #define CAN_F12R2_FB30_Msk (0x1U << CAN_F12R2_FB30_Pos) /*!< 0x40000000 */ #define CAN_F12R2_FB30 CAN_F12R2_FB30_Msk /*!<Filter bit 30 */ #define CAN_F12R2_FB31_Pos (31U) #define CAN_F12R2_FB31_Msk (0x1U << CAN_F12R2_FB31_Pos) /*!< 0x80000000 */ #define CAN_F12R2_FB31 CAN_F12R2_FB31_Msk /*!<Filter bit 31 */ /******************* Bit definition for CAN_F13R2 register ******************/ #define CAN_F13R2_FB0_Pos (0U) #define CAN_F13R2_FB0_Msk (0x1U << CAN_F13R2_FB0_Pos) /*!< 0x00000001 */ #define CAN_F13R2_FB0 CAN_F13R2_FB0_Msk /*!<Filter bit 0 */ #define CAN_F13R2_FB1_Pos (1U) #define CAN_F13R2_FB1_Msk (0x1U << CAN_F13R2_FB1_Pos) /*!< 0x00000002 */ #define CAN_F13R2_FB1 CAN_F13R2_FB1_Msk /*!<Filter bit 1 */ #define CAN_F13R2_FB2_Pos (2U) #define CAN_F13R2_FB2_Msk (0x1U << CAN_F13R2_FB2_Pos) /*!< 0x00000004 */ #define CAN_F13R2_FB2 CAN_F13R2_FB2_Msk /*!<Filter bit 2 */ #define CAN_F13R2_FB3_Pos (3U) #define CAN_F13R2_FB3_Msk (0x1U << CAN_F13R2_FB3_Pos) /*!< 0x00000008 */ #define CAN_F13R2_FB3 CAN_F13R2_FB3_Msk /*!<Filter bit 3 */ #define CAN_F13R2_FB4_Pos (4U) #define CAN_F13R2_FB4_Msk (0x1U << CAN_F13R2_FB4_Pos) /*!< 0x00000010 */ #define CAN_F13R2_FB4 CAN_F13R2_FB4_Msk /*!<Filter bit 4 */ #define CAN_F13R2_FB5_Pos (5U) #define CAN_F13R2_FB5_Msk (0x1U << CAN_F13R2_FB5_Pos) /*!< 0x00000020 */ #define CAN_F13R2_FB5 CAN_F13R2_FB5_Msk /*!<Filter bit 5 */ #define CAN_F13R2_FB6_Pos (6U) #define CAN_F13R2_FB6_Msk (0x1U << CAN_F13R2_FB6_Pos) /*!< 0x00000040 */ #define CAN_F13R2_FB6 CAN_F13R2_FB6_Msk /*!<Filter bit 6 */ #define CAN_F13R2_FB7_Pos (7U) #define CAN_F13R2_FB7_Msk (0x1U << CAN_F13R2_FB7_Pos) /*!< 0x00000080 */ #define CAN_F13R2_FB7 CAN_F13R2_FB7_Msk /*!<Filter bit 7 */ #define CAN_F13R2_FB8_Pos (8U) #define CAN_F13R2_FB8_Msk (0x1U << CAN_F13R2_FB8_Pos) /*!< 0x00000100 */ #define CAN_F13R2_FB8 CAN_F13R2_FB8_Msk /*!<Filter bit 8 */ #define CAN_F13R2_FB9_Pos (9U) #define CAN_F13R2_FB9_Msk (0x1U << CAN_F13R2_FB9_Pos) /*!< 0x00000200 */ #define CAN_F13R2_FB9 CAN_F13R2_FB9_Msk /*!<Filter bit 9 */ #define CAN_F13R2_FB10_Pos (10U) #define CAN_F13R2_FB10_Msk (0x1U << CAN_F13R2_FB10_Pos) /*!< 0x00000400 */ #define CAN_F13R2_FB10 CAN_F13R2_FB10_Msk /*!<Filter bit 10 */ #define CAN_F13R2_FB11_Pos (11U) #define CAN_F13R2_FB11_Msk (0x1U << CAN_F13R2_FB11_Pos) /*!< 0x00000800 */ #define CAN_F13R2_FB11 CAN_F13R2_FB11_Msk /*!<Filter bit 11 */ #define CAN_F13R2_FB12_Pos (12U) #define CAN_F13R2_FB12_Msk (0x1U << CAN_F13R2_FB12_Pos) /*!< 0x00001000 */ #define CAN_F13R2_FB12 CAN_F13R2_FB12_Msk /*!<Filter bit 12 */ #define CAN_F13R2_FB13_Pos (13U) #define CAN_F13R2_FB13_Msk (0x1U << CAN_F13R2_FB13_Pos) /*!< 0x00002000 */ #define CAN_F13R2_FB13 CAN_F13R2_FB13_Msk /*!<Filter bit 13 */ #define CAN_F13R2_FB14_Pos (14U) #define CAN_F13R2_FB14_Msk (0x1U << CAN_F13R2_FB14_Pos) /*!< 0x00004000 */ #define CAN_F13R2_FB14 CAN_F13R2_FB14_Msk /*!<Filter bit 14 */ #define CAN_F13R2_FB15_Pos (15U) #define CAN_F13R2_FB15_Msk (0x1U << CAN_F13R2_FB15_Pos) /*!< 0x00008000 */ #define CAN_F13R2_FB15 CAN_F13R2_FB15_Msk /*!<Filter bit 15 */ #define CAN_F13R2_FB16_Pos (16U) #define CAN_F13R2_FB16_Msk (0x1U << CAN_F13R2_FB16_Pos) /*!< 0x00010000 */ #define CAN_F13R2_FB16 CAN_F13R2_FB16_Msk /*!<Filter bit 16 */ #define CAN_F13R2_FB17_Pos (17U) #define CAN_F13R2_FB17_Msk (0x1U << CAN_F13R2_FB17_Pos) /*!< 0x00020000 */ #define CAN_F13R2_FB17 CAN_F13R2_FB17_Msk /*!<Filter bit 17 */ #define CAN_F13R2_FB18_Pos (18U) #define CAN_F13R2_FB18_Msk (0x1U << CAN_F13R2_FB18_Pos) /*!< 0x00040000 */ #define CAN_F13R2_FB18 CAN_F13R2_FB18_Msk /*!<Filter bit 18 */ #define CAN_F13R2_FB19_Pos (19U) #define CAN_F13R2_FB19_Msk (0x1U << CAN_F13R2_FB19_Pos) /*!< 0x00080000 */ #define CAN_F13R2_FB19 CAN_F13R2_FB19_Msk /*!<Filter bit 19 */ #define CAN_F13R2_FB20_Pos (20U) #define CAN_F13R2_FB20_Msk (0x1U << CAN_F13R2_FB20_Pos) /*!< 0x00100000 */ #define CAN_F13R2_FB20 CAN_F13R2_FB20_Msk /*!<Filter bit 20 */ #define CAN_F13R2_FB21_Pos (21U) #define CAN_F13R2_FB21_Msk (0x1U << CAN_F13R2_FB21_Pos) /*!< 0x00200000 */ #define CAN_F13R2_FB21 CAN_F13R2_FB21_Msk /*!<Filter bit 21 */ #define CAN_F13R2_FB22_Pos (22U) #define CAN_F13R2_FB22_Msk (0x1U << CAN_F13R2_FB22_Pos) /*!< 0x00400000 */ #define CAN_F13R2_FB22 CAN_F13R2_FB22_Msk /*!<Filter bit 22 */ #define CAN_F13R2_FB23_Pos (23U) #define CAN_F13R2_FB23_Msk (0x1U << CAN_F13R2_FB23_Pos) /*!< 0x00800000 */ #define CAN_F13R2_FB23 CAN_F13R2_FB23_Msk /*!<Filter bit 23 */ #define CAN_F13R2_FB24_Pos (24U) #define CAN_F13R2_FB24_Msk (0x1U << CAN_F13R2_FB24_Pos) /*!< 0x01000000 */ #define CAN_F13R2_FB24 CAN_F13R2_FB24_Msk /*!<Filter bit 24 */ #define CAN_F13R2_FB25_Pos (25U) #define CAN_F13R2_FB25_Msk (0x1U << CAN_F13R2_FB25_Pos) /*!< 0x02000000 */ #define CAN_F13R2_FB25 CAN_F13R2_FB25_Msk /*!<Filter bit 25 */ #define CAN_F13R2_FB26_Pos (26U) #define CAN_F13R2_FB26_Msk (0x1U << CAN_F13R2_FB26_Pos) /*!< 0x04000000 */ #define CAN_F13R2_FB26 CAN_F13R2_FB26_Msk /*!<Filter bit 26 */ #define CAN_F13R2_FB27_Pos (27U) #define CAN_F13R2_FB27_Msk (0x1U << CAN_F13R2_FB27_Pos) /*!< 0x08000000 */ #define CAN_F13R2_FB27 CAN_F13R2_FB27_Msk /*!<Filter bit 27 */ #define CAN_F13R2_FB28_Pos (28U) #define CAN_F13R2_FB28_Msk (0x1U << CAN_F13R2_FB28_Pos) /*!< 0x10000000 */ #define CAN_F13R2_FB28 CAN_F13R2_FB28_Msk /*!<Filter bit 28 */ #define CAN_F13R2_FB29_Pos (29U) #define CAN_F13R2_FB29_Msk (0x1U << CAN_F13R2_FB29_Pos) /*!< 0x20000000 */ #define CAN_F13R2_FB29 CAN_F13R2_FB29_Msk /*!<Filter bit 29 */ #define CAN_F13R2_FB30_Pos (30U) #define CAN_F13R2_FB30_Msk (0x1U << CAN_F13R2_FB30_Pos) /*!< 0x40000000 */ #define CAN_F13R2_FB30 CAN_F13R2_FB30_Msk /*!<Filter bit 30 */ #define CAN_F13R2_FB31_Pos (31U) #define CAN_F13R2_FB31_Msk (0x1U << CAN_F13R2_FB31_Pos) /*!< 0x80000000 */ #define CAN_F13R2_FB31 CAN_F13R2_FB31_Msk /*!<Filter bit 31 */ /******************************************************************************/ /* */ /* CRC calculation unit */ /* */ /******************************************************************************/ /******************* Bit definition for CRC_DR register *********************/ #define CRC_DR_DR_Pos (0U) #define CRC_DR_DR_Msk (0xFFFFFFFFU << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */ #define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */ /******************* Bit definition for CRC_IDR register ********************/ #define CRC_IDR_IDR_Pos (0U) #define CRC_IDR_IDR_Msk (0xFFU << CRC_IDR_IDR_Pos) /*!< 0x000000FF */ #define CRC_IDR_IDR CRC_IDR_IDR_Msk /*!< General-purpose 8-bit data register bits */ /******************** Bit definition for CRC_CR register ********************/ #define CRC_CR_RESET_Pos (0U) #define CRC_CR_RESET_Msk (0x1U << CRC_CR_RESET_Pos) /*!< 0x00000001 */ #define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET bit */ /******************************************************************************/ /* */ /* Digital to Analog Converter */ /* */ /******************************************************************************/ /* * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie) */ #define DAC_CHANNEL2_SUPPORT /*!< DAC feature available only on specific devices: availability of DAC channel 2 */ /******************** Bit definition for DAC_CR register ********************/ #define DAC_CR_EN1_Pos (0U) #define DAC_CR_EN1_Msk (0x1U << DAC_CR_EN1_Pos) /*!< 0x00000001 */ #define DAC_CR_EN1 DAC_CR_EN1_Msk /*!<DAC channel1 enable */ #define DAC_CR_BOFF1_Pos (1U) #define DAC_CR_BOFF1_Msk (0x1U << DAC_CR_BOFF1_Pos) /*!< 0x00000002 */ #define DAC_CR_BOFF1 DAC_CR_BOFF1_Msk /*!<DAC channel1 output buffer disable */ #define DAC_CR_TEN1_Pos (2U) #define DAC_CR_TEN1_Msk (0x1U << DAC_CR_TEN1_Pos) /*!< 0x00000004 */ #define DAC_CR_TEN1 DAC_CR_TEN1_Msk /*!<DAC channel1 Trigger enable */ #define DAC_CR_TSEL1_Pos (3U) #define DAC_CR_TSEL1_Msk (0x7U << DAC_CR_TSEL1_Pos) /*!< 0x00000038 */ #define DAC_CR_TSEL1 DAC_CR_TSEL1_Msk /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */ #define DAC_CR_TSEL1_0 (0x1U << DAC_CR_TSEL1_Pos) /*!< 0x00000008 */ #define DAC_CR_TSEL1_1 (0x2U << DAC_CR_TSEL1_Pos) /*!< 0x00000010 */ #define DAC_CR_TSEL1_2 (0x4U << DAC_CR_TSEL1_Pos) /*!< 0x00000020 */ #define DAC_CR_WAVE1_Pos (6U) #define DAC_CR_WAVE1_Msk (0x3U << DAC_CR_WAVE1_Pos) /*!< 0x000000C0 */ #define DAC_CR_WAVE1 DAC_CR_WAVE1_Msk /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */ #define DAC_CR_WAVE1_0 (0x1U << DAC_CR_WAVE1_Pos) /*!< 0x00000040 */ #define DAC_CR_WAVE1_1 (0x2U << DAC_CR_WAVE1_Pos) /*!< 0x00000080 */ #define DAC_CR_MAMP1_Pos (8U) #define DAC_CR_MAMP1_Msk (0xFU << DAC_CR_MAMP1_Pos) /*!< 0x00000F00 */ #define DAC_CR_MAMP1 DAC_CR_MAMP1_Msk /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */ #define DAC_CR_MAMP1_0 (0x1U << DAC_CR_MAMP1_Pos) /*!< 0x00000100 */ #define DAC_CR_MAMP1_1 (0x2U << DAC_CR_MAMP1_Pos) /*!< 0x00000200 */ #define DAC_CR_MAMP1_2 (0x4U << DAC_CR_MAMP1_Pos) /*!< 0x00000400 */ #define DAC_CR_MAMP1_3 (0x8U << DAC_CR_MAMP1_Pos) /*!< 0x00000800 */ #define DAC_CR_DMAEN1_Pos (12U) #define DAC_CR_DMAEN1_Msk (0x1U << DAC_CR_DMAEN1_Pos) /*!< 0x00001000 */ #define DAC_CR_DMAEN1 DAC_CR_DMAEN1_Msk /*!<DAC channel1 DMA enable */ #define DAC_CR_DMAUDRIE1_Pos (13U) #define DAC_CR_DMAUDRIE1_Msk (0x1U << DAC_CR_DMAUDRIE1_Pos) /*!< 0x00002000 */ #define DAC_CR_DMAUDRIE1 DAC_CR_DMAUDRIE1_Msk /*!<DAC channel1 DMA underrun interrupt enable*/ #define DAC_CR_EN2_Pos (16U) #define DAC_CR_EN2_Msk (0x1U << DAC_CR_EN2_Pos) /*!< 0x00010000 */ #define DAC_CR_EN2 DAC_CR_EN2_Msk /*!<DAC channel2 enable */ #define DAC_CR_BOFF2_Pos (17U) #define DAC_CR_BOFF2_Msk (0x1U << DAC_CR_BOFF2_Pos) /*!< 0x00020000 */ #define DAC_CR_BOFF2 DAC_CR_BOFF2_Msk /*!<DAC channel2 output buffer disable */ #define DAC_CR_TEN2_Pos (18U) #define DAC_CR_TEN2_Msk (0x1U << DAC_CR_TEN2_Pos) /*!< 0x00040000 */ #define DAC_CR_TEN2 DAC_CR_TEN2_Msk /*!<DAC channel2 Trigger enable */ #define DAC_CR_TSEL2_Pos (19U) #define DAC_CR_TSEL2_Msk (0x7U << DAC_CR_TSEL2_Pos) /*!< 0x00380000 */ #define DAC_CR_TSEL2 DAC_CR_TSEL2_Msk /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */ #define DAC_CR_TSEL2_0 (0x1U << DAC_CR_TSEL2_Pos) /*!< 0x00080000 */ #define DAC_CR_TSEL2_1 (0x2U << DAC_CR_TSEL2_Pos) /*!< 0x00100000 */ #define DAC_CR_TSEL2_2 (0x4U << DAC_CR_TSEL2_Pos) /*!< 0x00200000 */ #define DAC_CR_WAVE2_Pos (22U) #define DAC_CR_WAVE2_Msk (0x3U << DAC_CR_WAVE2_Pos) /*!< 0x00C00000 */ #define DAC_CR_WAVE2 DAC_CR_WAVE2_Msk /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */ #define DAC_CR_WAVE2_0 (0x1U << DAC_CR_WAVE2_Pos) /*!< 0x00400000 */ #define DAC_CR_WAVE2_1 (0x2U << DAC_CR_WAVE2_Pos) /*!< 0x00800000 */ #define DAC_CR_MAMP2_Pos (24U) #define DAC_CR_MAMP2_Msk (0xFU << DAC_CR_MAMP2_Pos) /*!< 0x0F000000 */ #define DAC_CR_MAMP2 DAC_CR_MAMP2_Msk /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */ #define DAC_CR_MAMP2_0 (0x1U << DAC_CR_MAMP2_Pos) /*!< 0x01000000 */ #define DAC_CR_MAMP2_1 (0x2U << DAC_CR_MAMP2_Pos) /*!< 0x02000000 */ #define DAC_CR_MAMP2_2 (0x4U << DAC_CR_MAMP2_Pos) /*!< 0x04000000 */ #define DAC_CR_MAMP2_3 (0x8U << DAC_CR_MAMP2_Pos) /*!< 0x08000000 */ #define DAC_CR_DMAEN2_Pos (28U) #define DAC_CR_DMAEN2_Msk (0x1U << DAC_CR_DMAEN2_Pos) /*!< 0x10000000 */ #define DAC_CR_DMAEN2 DAC_CR_DMAEN2_Msk /*!<DAC channel2 DMA enabled */ #define DAC_CR_DMAUDRIE2_Pos (29U) #define DAC_CR_DMAUDRIE2_Msk (0x1U << DAC_CR_DMAUDRIE2_Pos) /*!< 0x20000000 */ #define DAC_CR_DMAUDRIE2 DAC_CR_DMAUDRIE2_Msk /*!<DAC channel2 DMA underrun interrupt enable*/ /***************** Bit definition for DAC_SWTRIGR register ******************/ #define DAC_SWTRIGR_SWTRIG1_Pos (0U) #define DAC_SWTRIGR_SWTRIG1_Msk (0x1U << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */ #define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk /*!<DAC channel1 software trigger */ #define DAC_SWTRIGR_SWTRIG2_Pos (1U) #define DAC_SWTRIGR_SWTRIG2_Msk (0x1U << DAC_SWTRIGR_SWTRIG2_Pos) /*!< 0x00000002 */ #define DAC_SWTRIGR_SWTRIG2 DAC_SWTRIGR_SWTRIG2_Msk /*!<DAC channel2 software trigger */ /***************** Bit definition for DAC_DHR12R1 register ******************/ #define DAC_DHR12R1_DACC1DHR_Pos (0U) #define DAC_DHR12R1_DACC1DHR_Msk (0xFFFU << DAC_DHR12R1_DACC1DHR_Pos) /*!< 0x00000FFF */ #define DAC_DHR12R1_DACC1DHR DAC_DHR12R1_DACC1DHR_Msk /*!<DAC channel1 12-bit Right aligned data */ /***************** Bit definition for DAC_DHR12L1 register ******************/ #define DAC_DHR12L1_DACC1DHR_Pos (4U) #define DAC_DHR12L1_DACC1DHR_Msk (0xFFFU << DAC_DHR12L1_DACC1DHR_Pos) /*!< 0x0000FFF0 */ #define DAC_DHR12L1_DACC1DHR DAC_DHR12L1_DACC1DHR_Msk /*!<DAC channel1 12-bit Left aligned data */ /****************** Bit definition for DAC_DHR8R1 register ******************/ #define DAC_DHR8R1_DACC1DHR_Pos (0U) #define DAC_DHR8R1_DACC1DHR_Msk (0xFFU << DAC_DHR8R1_DACC1DHR_Pos) /*!< 0x000000FF */ #define DAC_DHR8R1_DACC1DHR DAC_DHR8R1_DACC1DHR_Msk /*!<DAC channel1 8-bit Right aligned data */ /***************** Bit definition for DAC_DHR12R2 register ******************/ #define DAC_DHR12R2_DACC2DHR_Pos (0U) #define DAC_DHR12R2_DACC2DHR_Msk (0xFFFU << DAC_DHR12R2_DACC2DHR_Pos) /*!< 0x00000FFF */ #define DAC_DHR12R2_DACC2DHR DAC_DHR12R2_DACC2DHR_Msk /*!<DAC channel2 12-bit Right aligned data */ /***************** Bit definition for DAC_DHR12L2 register ******************/ #define DAC_DHR12L2_DACC2DHR_Pos (4U) #define DAC_DHR12L2_DACC2DHR_Msk (0xFFFU << DAC_DHR12L2_DACC2DHR_Pos) /*!< 0x0000FFF0 */ #define DAC_DHR12L2_DACC2DHR DAC_DHR12L2_DACC2DHR_Msk /*!<DAC channel2 12-bit Left aligned data */ /****************** Bit definition for DAC_DHR8R2 register ******************/ #define DAC_DHR8R2_DACC2DHR_Pos (0U) #define DAC_DHR8R2_DACC2DHR_Msk (0xFFU << DAC_DHR8R2_DACC2DHR_Pos) /*!< 0x000000FF */ #define DAC_DHR8R2_DACC2DHR DAC_DHR8R2_DACC2DHR_Msk /*!<DAC channel2 8-bit Right aligned data */ /***************** Bit definition for DAC_DHR12RD register ******************/ #define DAC_DHR12RD_DACC1DHR_Pos (0U) #define DAC_DHR12RD_DACC1DHR_Msk (0xFFFU << DAC_DHR12RD_DACC1DHR_Pos) /*!< 0x00000FFF */ #define DAC_DHR12RD_DACC1DHR DAC_DHR12RD_DACC1DHR_Msk /*!<DAC channel1 12-bit Right aligned data */ #define DAC_DHR12RD_DACC2DHR_Pos (16U) #define DAC_DHR12RD_DACC2DHR_Msk (0xFFFU << DAC_DHR12RD_DACC2DHR_Pos) /*!< 0x0FFF0000 */ #define DAC_DHR12RD_DACC2DHR DAC_DHR12RD_DACC2DHR_Msk /*!<DAC channel2 12-bit Right aligned data */ /***************** Bit definition for DAC_DHR12LD register ******************/ #define DAC_DHR12LD_DACC1DHR_Pos (4U) #define DAC_DHR12LD_DACC1DHR_Msk (0xFFFU << DAC_DHR12LD_DACC1DHR_Pos) /*!< 0x0000FFF0 */ #define DAC_DHR12LD_DACC1DHR DAC_DHR12LD_DACC1DHR_Msk /*!<DAC channel1 12-bit Left aligned data */ #define DAC_DHR12LD_DACC2DHR_Pos (20U) #define DAC_DHR12LD_DACC2DHR_Msk (0xFFFU << DAC_DHR12LD_DACC2DHR_Pos) /*!< 0xFFF00000 */ #define DAC_DHR12LD_DACC2DHR DAC_DHR12LD_DACC2DHR_Msk /*!<DAC channel2 12-bit Left aligned data */ /****************** Bit definition for DAC_DHR8RD register ******************/ #define DAC_DHR8RD_DACC1DHR_Pos (0U) #define DAC_DHR8RD_DACC1DHR_Msk (0xFFU << DAC_DHR8RD_DACC1DHR_Pos) /*!< 0x000000FF */ #define DAC_DHR8RD_DACC1DHR DAC_DHR8RD_DACC1DHR_Msk /*!<DAC channel1 8-bit Right aligned data */ #define DAC_DHR8RD_DACC2DHR_Pos (8U) #define DAC_DHR8RD_DACC2DHR_Msk (0xFFU << DAC_DHR8RD_DACC2DHR_Pos) /*!< 0x0000FF00 */ #define DAC_DHR8RD_DACC2DHR DAC_DHR8RD_DACC2DHR_Msk /*!<DAC channel2 8-bit Right aligned data */ /******************* Bit definition for DAC_DOR1 register *******************/ #define DAC_DOR1_DACC1DOR_Pos (0U) #define DAC_DOR1_DACC1DOR_Msk (0xFFFU << DAC_DOR1_DACC1DOR_Pos) /*!< 0x00000FFF */ #define DAC_DOR1_DACC1DOR DAC_DOR1_DACC1DOR_Msk /*!<DAC channel1 data output */ /******************* Bit definition for DAC_DOR2 register *******************/ #define DAC_DOR2_DACC2DOR_Pos (0U) #define DAC_DOR2_DACC2DOR_Msk (0xFFFU << DAC_DOR2_DACC2DOR_Pos) /*!< 0x00000FFF */ #define DAC_DOR2_DACC2DOR DAC_DOR2_DACC2DOR_Msk /*!<DAC channel2 data output */ /******************** Bit definition for DAC_SR register ********************/ #define DAC_SR_DMAUDR1_Pos (13U) #define DAC_SR_DMAUDR1_Msk (0x1U << DAC_SR_DMAUDR1_Pos) /*!< 0x00002000 */ #define DAC_SR_DMAUDR1 DAC_SR_DMAUDR1_Msk /*!<DAC channel1 DMA underrun flag */ #define DAC_SR_DMAUDR2_Pos (29U) #define DAC_SR_DMAUDR2_Msk (0x1U << DAC_SR_DMAUDR2_Pos) /*!< 0x20000000 */ #define DAC_SR_DMAUDR2 DAC_SR_DMAUDR2_Msk /*!<DAC channel2 DMA underrun flag */ /******************************************************************************/ /* */ /* DCMI */ /* */ /******************************************************************************/ /******************** Bits definition for DCMI_CR register ******************/ #define DCMI_CR_CAPTURE_Pos (0U) #define DCMI_CR_CAPTURE_Msk (0x1U << DCMI_CR_CAPTURE_Pos) /*!< 0x00000001 */ #define DCMI_CR_CAPTURE DCMI_CR_CAPTURE_Msk #define DCMI_CR_CM_Pos (1U) #define DCMI_CR_CM_Msk (0x1U << DCMI_CR_CM_Pos) /*!< 0x00000002 */ #define DCMI_CR_CM DCMI_CR_CM_Msk #define DCMI_CR_CROP_Pos (2U) #define DCMI_CR_CROP_Msk (0x1U << DCMI_CR_CROP_Pos) /*!< 0x00000004 */ #define DCMI_CR_CROP DCMI_CR_CROP_Msk #define DCMI_CR_JPEG_Pos (3U) #define DCMI_CR_JPEG_Msk (0x1U << DCMI_CR_JPEG_Pos) /*!< 0x00000008 */ #define DCMI_CR_JPEG DCMI_CR_JPEG_Msk #define DCMI_CR_ESS_Pos (4U) #define DCMI_CR_ESS_Msk (0x1U << DCMI_CR_ESS_Pos) /*!< 0x00000010 */ #define DCMI_CR_ESS DCMI_CR_ESS_Msk #define DCMI_CR_PCKPOL_Pos (5U) #define DCMI_CR_PCKPOL_Msk (0x1U << DCMI_CR_PCKPOL_Pos) /*!< 0x00000020 */ #define DCMI_CR_PCKPOL DCMI_CR_PCKPOL_Msk #define DCMI_CR_HSPOL_Pos (6U) #define DCMI_CR_HSPOL_Msk (0x1U << DCMI_CR_HSPOL_Pos) /*!< 0x00000040 */ #define DCMI_CR_HSPOL DCMI_CR_HSPOL_Msk #define DCMI_CR_VSPOL_Pos (7U) #define DCMI_CR_VSPOL_Msk (0x1U << DCMI_CR_VSPOL_Pos) /*!< 0x00000080 */ #define DCMI_CR_VSPOL DCMI_CR_VSPOL_Msk #define DCMI_CR_FCRC_0 0x00000100U #define DCMI_CR_FCRC_1 0x00000200U #define DCMI_CR_EDM_0 0x00000400U #define DCMI_CR_EDM_1 0x00000800U #define DCMI_CR_OUTEN_Pos (13U) #define DCMI_CR_OUTEN_Msk (0x1U << DCMI_CR_OUTEN_Pos) /*!< 0x00002000 */ #define DCMI_CR_OUTEN DCMI_CR_OUTEN_Msk #define DCMI_CR_ENABLE_Pos (14U) #define DCMI_CR_ENABLE_Msk (0x1U << DCMI_CR_ENABLE_Pos) /*!< 0x00004000 */ #define DCMI_CR_ENABLE DCMI_CR_ENABLE_Msk #define DCMI_CR_BSM_0 0x00010000U #define DCMI_CR_BSM_1 0x00020000U #define DCMI_CR_OEBS_Pos (18U) #define DCMI_CR_OEBS_Msk (0x1U << DCMI_CR_OEBS_Pos) /*!< 0x00040000 */ #define DCMI_CR_OEBS DCMI_CR_OEBS_Msk #define DCMI_CR_LSM_Pos (19U) #define DCMI_CR_LSM_Msk (0x1U << DCMI_CR_LSM_Pos) /*!< 0x00080000 */ #define DCMI_CR_LSM DCMI_CR_LSM_Msk #define DCMI_CR_OELS_Pos (20U) #define DCMI_CR_OELS_Msk (0x1U << DCMI_CR_OELS_Pos) /*!< 0x00100000 */ #define DCMI_CR_OELS DCMI_CR_OELS_Msk /******************** Bits definition for DCMI_SR register ******************/ #define DCMI_SR_HSYNC_Pos (0U) #define DCMI_SR_HSYNC_Msk (0x1U << DCMI_SR_HSYNC_Pos) /*!< 0x00000001 */ #define DCMI_SR_HSYNC DCMI_SR_HSYNC_Msk #define DCMI_SR_VSYNC_Pos (1U) #define DCMI_SR_VSYNC_Msk (0x1U << DCMI_SR_VSYNC_Pos) /*!< 0x00000002 */ #define DCMI_SR_VSYNC DCMI_SR_VSYNC_Msk #define DCMI_SR_FNE_Pos (2U) #define DCMI_SR_FNE_Msk (0x1U << DCMI_SR_FNE_Pos) /*!< 0x00000004 */ #define DCMI_SR_FNE DCMI_SR_FNE_Msk /******************** Bits definition for DCMI_RIS register *****************/ #define DCMI_RIS_FRAME_RIS_Pos (0U) #define DCMI_RIS_FRAME_RIS_Msk (0x1U << DCMI_RIS_FRAME_RIS_Pos) /*!< 0x00000001 */ #define DCMI_RIS_FRAME_RIS DCMI_RIS_FRAME_RIS_Msk #define DCMI_RIS_OVR_RIS_Pos (1U) #define DCMI_RIS_OVR_RIS_Msk (0x1U << DCMI_RIS_OVR_RIS_Pos) /*!< 0x00000002 */ #define DCMI_RIS_OVR_RIS DCMI_RIS_OVR_RIS_Msk #define DCMI_RIS_ERR_RIS_Pos (2U) #define DCMI_RIS_ERR_RIS_Msk (0x1U << DCMI_RIS_ERR_RIS_Pos) /*!< 0x00000004 */ #define DCMI_RIS_ERR_RIS DCMI_RIS_ERR_RIS_Msk #define DCMI_RIS_VSYNC_RIS_Pos (3U) #define DCMI_RIS_VSYNC_RIS_Msk (0x1U << DCMI_RIS_VSYNC_RIS_Pos) /*!< 0x00000008 */ #define DCMI_RIS_VSYNC_RIS DCMI_RIS_VSYNC_RIS_Msk #define DCMI_RIS_LINE_RIS_Pos (4U) #define DCMI_RIS_LINE_RIS_Msk (0x1U << DCMI_RIS_LINE_RIS_Pos) /*!< 0x00000010 */ #define DCMI_RIS_LINE_RIS DCMI_RIS_LINE_RIS_Msk /* Legacy defines */ #define DCMI_RISR_FRAME_RIS DCMI_RIS_FRAME_RIS #define DCMI_RISR_OVR_RIS DCMI_RIS_OVR_RIS #define DCMI_RISR_ERR_RIS DCMI_RIS_ERR_RIS #define DCMI_RISR_VSYNC_RIS DCMI_RIS_VSYNC_RIS #define DCMI_RISR_LINE_RIS DCMI_RIS_LINE_RIS #define DCMI_RISR_OVF_RIS DCMI_RIS_OVR_RIS /******************** Bits definition for DCMI_IER register *****************/ #define DCMI_IER_FRAME_IE_Pos (0U) #define DCMI_IER_FRAME_IE_Msk (0x1U << DCMI_IER_FRAME_IE_Pos) /*!< 0x00000001 */ #define DCMI_IER_FRAME_IE DCMI_IER_FRAME_IE_Msk #define DCMI_IER_OVR_IE_Pos (1U) #define DCMI_IER_OVR_IE_Msk (0x1U << DCMI_IER_OVR_IE_Pos) /*!< 0x00000002 */ #define DCMI_IER_OVR_IE DCMI_IER_OVR_IE_Msk #define DCMI_IER_ERR_IE_Pos (2U) #define DCMI_IER_ERR_IE_Msk (0x1U << DCMI_IER_ERR_IE_Pos) /*!< 0x00000004 */ #define DCMI_IER_ERR_IE DCMI_IER_ERR_IE_Msk #define DCMI_IER_VSYNC_IE_Pos (3U) #define DCMI_IER_VSYNC_IE_Msk (0x1U << DCMI_IER_VSYNC_IE_Pos) /*!< 0x00000008 */ #define DCMI_IER_VSYNC_IE DCMI_IER_VSYNC_IE_Msk #define DCMI_IER_LINE_IE_Pos (4U) #define DCMI_IER_LINE_IE_Msk (0x1U << DCMI_IER_LINE_IE_Pos) /*!< 0x00000010 */ #define DCMI_IER_LINE_IE DCMI_IER_LINE_IE_Msk /* Legacy defines */ #define DCMI_IER_OVF_IE DCMI_IER_OVR_IE /******************** Bits definition for DCMI_MIS register *****************/ #define DCMI_MIS_FRAME_MIS_Pos (0U) #define DCMI_MIS_FRAME_MIS_Msk (0x1U << DCMI_MIS_FRAME_MIS_Pos) /*!< 0x00000001 */ #define DCMI_MIS_FRAME_MIS DCMI_MIS_FRAME_MIS_Msk #define DCMI_MIS_OVR_MIS_Pos (1U) #define DCMI_MIS_OVR_MIS_Msk (0x1U << DCMI_MIS_OVR_MIS_Pos) /*!< 0x00000002 */ #define DCMI_MIS_OVR_MIS DCMI_MIS_OVR_MIS_Msk #define DCMI_MIS_ERR_MIS_Pos (2U) #define DCMI_MIS_ERR_MIS_Msk (0x1U << DCMI_MIS_ERR_MIS_Pos) /*!< 0x00000004 */ #define DCMI_MIS_ERR_MIS DCMI_MIS_ERR_MIS_Msk #define DCMI_MIS_VSYNC_MIS_Pos (3U) #define DCMI_MIS_VSYNC_MIS_Msk (0x1U << DCMI_MIS_VSYNC_MIS_Pos) /*!< 0x00000008 */ #define DCMI_MIS_VSYNC_MIS DCMI_MIS_VSYNC_MIS_Msk #define DCMI_MIS_LINE_MIS_Pos (4U) #define DCMI_MIS_LINE_MIS_Msk (0x1U << DCMI_MIS_LINE_MIS_Pos) /*!< 0x00000010 */ #define DCMI_MIS_LINE_MIS DCMI_MIS_LINE_MIS_Msk /* Legacy defines */ #define DCMI_MISR_FRAME_MIS DCMI_MIS_FRAME_MIS #define DCMI_MISR_OVF_MIS DCMI_MIS_OVR_MIS #define DCMI_MISR_ERR_MIS DCMI_MIS_ERR_MIS #define DCMI_MISR_VSYNC_MIS DCMI_MIS_VSYNC_MIS #define DCMI_MISR_LINE_MIS DCMI_MIS_LINE_MIS /******************** Bits definition for DCMI_ICR register *****************/ #define DCMI_ICR_FRAME_ISC_Pos (0U) #define DCMI_ICR_FRAME_ISC_Msk (0x1U << DCMI_ICR_FRAME_ISC_Pos) /*!< 0x00000001 */ #define DCMI_ICR_FRAME_ISC DCMI_ICR_FRAME_ISC_Msk #define DCMI_ICR_OVR_ISC_Pos (1U) #define DCMI_ICR_OVR_ISC_Msk (0x1U << DCMI_ICR_OVR_ISC_Pos) /*!< 0x00000002 */ #define DCMI_ICR_OVR_ISC DCMI_ICR_OVR_ISC_Msk #define DCMI_ICR_ERR_ISC_Pos (2U) #define DCMI_ICR_ERR_ISC_Msk (0x1U << DCMI_ICR_ERR_ISC_Pos) /*!< 0x00000004 */ #define DCMI_ICR_ERR_ISC DCMI_ICR_ERR_ISC_Msk #define DCMI_ICR_VSYNC_ISC_Pos (3U) #define DCMI_ICR_VSYNC_ISC_Msk (0x1U << DCMI_ICR_VSYNC_ISC_Pos) /*!< 0x00000008 */ #define DCMI_ICR_VSYNC_ISC DCMI_ICR_VSYNC_ISC_Msk #define DCMI_ICR_LINE_ISC_Pos (4U) #define DCMI_ICR_LINE_ISC_Msk (0x1U << DCMI_ICR_LINE_ISC_Pos) /*!< 0x00000010 */ #define DCMI_ICR_LINE_ISC DCMI_ICR_LINE_ISC_Msk /* Legacy defines */ #define DCMI_ICR_OVF_ISC DCMI_ICR_OVR_ISC /******************** Bits definition for DCMI_ESCR register ******************/ #define DCMI_ESCR_FSC_Pos (0U) #define DCMI_ESCR_FSC_Msk (0xFFU << DCMI_ESCR_FSC_Pos) /*!< 0x000000FF */ #define DCMI_ESCR_FSC DCMI_ESCR_FSC_Msk #define DCMI_ESCR_LSC_Pos (8U) #define DCMI_ESCR_LSC_Msk (0xFFU << DCMI_ESCR_LSC_Pos) /*!< 0x0000FF00 */ #define DCMI_ESCR_LSC DCMI_ESCR_LSC_Msk #define DCMI_ESCR_LEC_Pos (16U) #define DCMI_ESCR_LEC_Msk (0xFFU << DCMI_ESCR_LEC_Pos) /*!< 0x00FF0000 */ #define DCMI_ESCR_LEC DCMI_ESCR_LEC_Msk #define DCMI_ESCR_FEC_Pos (24U) #define DCMI_ESCR_FEC_Msk (0xFFU << DCMI_ESCR_FEC_Pos) /*!< 0xFF000000 */ #define DCMI_ESCR_FEC DCMI_ESCR_FEC_Msk /******************** Bits definition for DCMI_ESUR register ******************/ #define DCMI_ESUR_FSU_Pos (0U) #define DCMI_ESUR_FSU_Msk (0xFFU << DCMI_ESUR_FSU_Pos) /*!< 0x000000FF */ #define DCMI_ESUR_FSU DCMI_ESUR_FSU_Msk #define DCMI_ESUR_LSU_Pos (8U) #define DCMI_ESUR_LSU_Msk (0xFFU << DCMI_ESUR_LSU_Pos) /*!< 0x0000FF00 */ #define DCMI_ESUR_LSU DCMI_ESUR_LSU_Msk #define DCMI_ESUR_LEU_Pos (16U) #define DCMI_ESUR_LEU_Msk (0xFFU << DCMI_ESUR_LEU_Pos) /*!< 0x00FF0000 */ #define DCMI_ESUR_LEU DCMI_ESUR_LEU_Msk #define DCMI_ESUR_FEU_Pos (24U) #define DCMI_ESUR_FEU_Msk (0xFFU << DCMI_ESUR_FEU_Pos) /*!< 0xFF000000 */ #define DCMI_ESUR_FEU DCMI_ESUR_FEU_Msk /******************** Bits definition for DCMI_CWSTRT register ******************/ #define DCMI_CWSTRT_HOFFCNT_Pos (0U) #define DCMI_CWSTRT_HOFFCNT_Msk (0x3FFFU << DCMI_CWSTRT_HOFFCNT_Pos) /*!< 0x00003FFF */ #define DCMI_CWSTRT_HOFFCNT DCMI_CWSTRT_HOFFCNT_Msk #define DCMI_CWSTRT_VST_Pos (16U) #define DCMI_CWSTRT_VST_Msk (0x1FFFU << DCMI_CWSTRT_VST_Pos) /*!< 0x1FFF0000 */ #define DCMI_CWSTRT_VST DCMI_CWSTRT_VST_Msk /******************** Bits definition for DCMI_CWSIZE register ******************/ #define DCMI_CWSIZE_CAPCNT_Pos (0U) #define DCMI_CWSIZE_CAPCNT_Msk (0x3FFFU << DCMI_CWSIZE_CAPCNT_Pos) /*!< 0x00003FFF */ #define DCMI_CWSIZE_CAPCNT DCMI_CWSIZE_CAPCNT_Msk #define DCMI_CWSIZE_VLINE_Pos (16U) #define DCMI_CWSIZE_VLINE_Msk (0x3FFFU << DCMI_CWSIZE_VLINE_Pos) /*!< 0x3FFF0000 */ #define DCMI_CWSIZE_VLINE DCMI_CWSIZE_VLINE_Msk /******************** Bits definition for DCMI_DR register *********************/ #define DCMI_DR_BYTE0_Pos (0U) #define DCMI_DR_BYTE0_Msk (0xFFU << DCMI_DR_BYTE0_Pos) /*!< 0x000000FF */ #define DCMI_DR_BYTE0 DCMI_DR_BYTE0_Msk #define DCMI_DR_BYTE1_Pos (8U) #define DCMI_DR_BYTE1_Msk (0xFFU << DCMI_DR_BYTE1_Pos) /*!< 0x0000FF00 */ #define DCMI_DR_BYTE1 DCMI_DR_BYTE1_Msk #define DCMI_DR_BYTE2_Pos (16U) #define DCMI_DR_BYTE2_Msk (0xFFU << DCMI_DR_BYTE2_Pos) /*!< 0x00FF0000 */ #define DCMI_DR_BYTE2 DCMI_DR_BYTE2_Msk #define DCMI_DR_BYTE3_Pos (24U) #define DCMI_DR_BYTE3_Msk (0xFFU << DCMI_DR_BYTE3_Pos) /*!< 0xFF000000 */ #define DCMI_DR_BYTE3 DCMI_DR_BYTE3_Msk /******************************************************************************/ /* */ /* DMA Controller */ /* */ /******************************************************************************/ /******************** Bits definition for DMA_SxCR register *****************/ #define DMA_SxCR_CHSEL_Pos (25U) #define DMA_SxCR_CHSEL_Msk (0x7U << DMA_SxCR_CHSEL_Pos) /*!< 0x0E000000 */ #define DMA_SxCR_CHSEL DMA_SxCR_CHSEL_Msk #define DMA_SxCR_CHSEL_0 0x02000000U #define DMA_SxCR_CHSEL_1 0x04000000U #define DMA_SxCR_CHSEL_2 0x08000000U #define DMA_SxCR_MBURST_Pos (23U) #define DMA_SxCR_MBURST_Msk (0x3U << DMA_SxCR_MBURST_Pos) /*!< 0x01800000 */ #define DMA_SxCR_MBURST DMA_SxCR_MBURST_Msk #define DMA_SxCR_MBURST_0 (0x1U << DMA_SxCR_MBURST_Pos) /*!< 0x00800000 */ #define DMA_SxCR_MBURST_1 (0x2U << DMA_SxCR_MBURST_Pos) /*!< 0x01000000 */ #define DMA_SxCR_PBURST_Pos (21U) #define DMA_SxCR_PBURST_Msk (0x3U << DMA_SxCR_PBURST_Pos) /*!< 0x00600000 */ #define DMA_SxCR_PBURST DMA_SxCR_PBURST_Msk #define DMA_SxCR_PBURST_0 (0x1U << DMA_SxCR_PBURST_Pos) /*!< 0x00200000 */ #define DMA_SxCR_PBURST_1 (0x2U << DMA_SxCR_PBURST_Pos) /*!< 0x00400000 */ #define DMA_SxCR_CT_Pos (19U) #define DMA_SxCR_CT_Msk (0x1U << DMA_SxCR_CT_Pos) /*!< 0x00080000 */ #define DMA_SxCR_CT DMA_SxCR_CT_Msk #define DMA_SxCR_DBM_Pos (18U) #define DMA_SxCR_DBM_Msk (0x1U << DMA_SxCR_DBM_Pos) /*!< 0x00040000 */ #define DMA_SxCR_DBM DMA_SxCR_DBM_Msk #define DMA_SxCR_PL_Pos (16U) #define DMA_SxCR_PL_Msk (0x3U << DMA_SxCR_PL_Pos) /*!< 0x00030000 */ #define DMA_SxCR_PL DMA_SxCR_PL_Msk #define DMA_SxCR_PL_0 (0x1U << DMA_SxCR_PL_Pos) /*!< 0x00010000 */ #define DMA_SxCR_PL_1 (0x2U << DMA_SxCR_PL_Pos) /*!< 0x00020000 */ #define DMA_SxCR_PINCOS_Pos (15U) #define DMA_SxCR_PINCOS_Msk (0x1U << DMA_SxCR_PINCOS_Pos) /*!< 0x00008000 */ #define DMA_SxCR_PINCOS DMA_SxCR_PINCOS_Msk #define DMA_SxCR_MSIZE_Pos (13U) #define DMA_SxCR_MSIZE_Msk (0x3U << DMA_SxCR_MSIZE_Pos) /*!< 0x00006000 */ #define DMA_SxCR_MSIZE DMA_SxCR_MSIZE_Msk #define DMA_SxCR_MSIZE_0 (0x1U << DMA_SxCR_MSIZE_Pos) /*!< 0x00002000 */ #define DMA_SxCR_MSIZE_1 (0x2U << DMA_SxCR_MSIZE_Pos) /*!< 0x00004000 */ #define DMA_SxCR_PSIZE_Pos (11U) #define DMA_SxCR_PSIZE_Msk (0x3U << DMA_SxCR_PSIZE_Pos) /*!< 0x00001800 */ #define DMA_SxCR_PSIZE DMA_SxCR_PSIZE_Msk #define DMA_SxCR_PSIZE_0 (0x1U << DMA_SxCR_PSIZE_Pos) /*!< 0x00000800 */ #define DMA_SxCR_PSIZE_1 (0x2U << DMA_SxCR_PSIZE_Pos) /*!< 0x00001000 */ #define DMA_SxCR_MINC_Pos (10U) #define DMA_SxCR_MINC_Msk (0x1U << DMA_SxCR_MINC_Pos) /*!< 0x00000400 */ #define DMA_SxCR_MINC DMA_SxCR_MINC_Msk #define DMA_SxCR_PINC_Pos (9U) #define DMA_SxCR_PINC_Msk (0x1U << DMA_SxCR_PINC_Pos) /*!< 0x00000200 */ #define DMA_SxCR_PINC DMA_SxCR_PINC_Msk #define DMA_SxCR_CIRC_Pos (8U) #define DMA_SxCR_CIRC_Msk (0x1U << DMA_SxCR_CIRC_Pos) /*!< 0x00000100 */ #define DMA_SxCR_CIRC DMA_SxCR_CIRC_Msk #define DMA_SxCR_DIR_Pos (6U) #define DMA_SxCR_DIR_Msk (0x3U << DMA_SxCR_DIR_Pos) /*!< 0x000000C0 */ #define DMA_SxCR_DIR DMA_SxCR_DIR_Msk #define DMA_SxCR_DIR_0 (0x1U << DMA_SxCR_DIR_Pos) /*!< 0x00000040 */ #define DMA_SxCR_DIR_1 (0x2U << DMA_SxCR_DIR_Pos) /*!< 0x00000080 */ #define DMA_SxCR_PFCTRL_Pos (5U) #define DMA_SxCR_PFCTRL_Msk (0x1U << DMA_SxCR_PFCTRL_Pos) /*!< 0x00000020 */ #define DMA_SxCR_PFCTRL DMA_SxCR_PFCTRL_Msk #define DMA_SxCR_TCIE_Pos (4U) #define DMA_SxCR_TCIE_Msk (0x1U << DMA_SxCR_TCIE_Pos) /*!< 0x00000010 */ #define DMA_SxCR_TCIE DMA_SxCR_TCIE_Msk #define DMA_SxCR_HTIE_Pos (3U) #define DMA_SxCR_HTIE_Msk (0x1U << DMA_SxCR_HTIE_Pos) /*!< 0x00000008 */ #define DMA_SxCR_HTIE DMA_SxCR_HTIE_Msk #define DMA_SxCR_TEIE_Pos (2U) #define DMA_SxCR_TEIE_Msk (0x1U << DMA_SxCR_TEIE_Pos) /*!< 0x00000004 */ #define DMA_SxCR_TEIE DMA_SxCR_TEIE_Msk #define DMA_SxCR_DMEIE_Pos (1U) #define DMA_SxCR_DMEIE_Msk (0x1U << DMA_SxCR_DMEIE_Pos) /*!< 0x00000002 */ #define DMA_SxCR_DMEIE DMA_SxCR_DMEIE_Msk #define DMA_SxCR_EN_Pos (0U) #define DMA_SxCR_EN_Msk (0x1U << DMA_SxCR_EN_Pos) /*!< 0x00000001 */ #define DMA_SxCR_EN DMA_SxCR_EN_Msk /* Legacy defines */ #define DMA_SxCR_ACK_Pos (20U) #define DMA_SxCR_ACK_Msk (0x1U << DMA_SxCR_ACK_Pos) /*!< 0x00100000 */ #define DMA_SxCR_ACK DMA_SxCR_ACK_Msk /******************** Bits definition for DMA_SxCNDTR register **************/ #define DMA_SxNDT_Pos (0U) #define DMA_SxNDT_Msk (0xFFFFU << DMA_SxNDT_Pos) /*!< 0x0000FFFF */ #define DMA_SxNDT DMA_SxNDT_Msk #define DMA_SxNDT_0 (0x0001U << DMA_SxNDT_Pos) /*!< 0x00000001 */ #define DMA_SxNDT_1 (0x0002U << DMA_SxNDT_Pos) /*!< 0x00000002 */ #define DMA_SxNDT_2 (0x0004U << DMA_SxNDT_Pos) /*!< 0x00000004 */ #define DMA_SxNDT_3 (0x0008U << DMA_SxNDT_Pos) /*!< 0x00000008 */ #define DMA_SxNDT_4 (0x0010U << DMA_SxNDT_Pos) /*!< 0x00000010 */ #define DMA_SxNDT_5 (0x0020U << DMA_SxNDT_Pos) /*!< 0x00000020 */ #define DMA_SxNDT_6 (0x0040U << DMA_SxNDT_Pos) /*!< 0x00000040 */ #define DMA_SxNDT_7 (0x0080U << DMA_SxNDT_Pos) /*!< 0x00000080 */ #define DMA_SxNDT_8 (0x0100U << DMA_SxNDT_Pos) /*!< 0x00000100 */ #define DMA_SxNDT_9 (0x0200U << DMA_SxNDT_Pos) /*!< 0x00000200 */ #define DMA_SxNDT_10 (0x0400U << DMA_SxNDT_Pos) /*!< 0x00000400 */ #define DMA_SxNDT_11 (0x0800U << DMA_SxNDT_Pos) /*!< 0x00000800 */ #define DMA_SxNDT_12 (0x1000U << DMA_SxNDT_Pos) /*!< 0x00001000 */ #define DMA_SxNDT_13 (0x2000U << DMA_SxNDT_Pos) /*!< 0x00002000 */ #define DMA_SxNDT_14 (0x4000U << DMA_SxNDT_Pos) /*!< 0x00004000 */ #define DMA_SxNDT_15 (0x8000U << DMA_SxNDT_Pos) /*!< 0x00008000 */ /******************** Bits definition for DMA_SxFCR register ****************/ #define DMA_SxFCR_FEIE_Pos (7U) #define DMA_SxFCR_FEIE_Msk (0x1U << DMA_SxFCR_FEIE_Pos) /*!< 0x00000080 */ #define DMA_SxFCR_FEIE DMA_SxFCR_FEIE_Msk #define DMA_SxFCR_FS_Pos (3U) #define DMA_SxFCR_FS_Msk (0x7U << DMA_SxFCR_FS_Pos) /*!< 0x00000038 */ #define DMA_SxFCR_FS DMA_SxFCR_FS_Msk #define DMA_SxFCR_FS_0 (0x1U << DMA_SxFCR_FS_Pos) /*!< 0x00000008 */ #define DMA_SxFCR_FS_1 (0x2U << DMA_SxFCR_FS_Pos) /*!< 0x00000010 */ #define DMA_SxFCR_FS_2 (0x4U << DMA_SxFCR_FS_Pos) /*!< 0x00000020 */ #define DMA_SxFCR_DMDIS_Pos (2U) #define DMA_SxFCR_DMDIS_Msk (0x1U << DMA_SxFCR_DMDIS_Pos) /*!< 0x00000004 */ #define DMA_SxFCR_DMDIS DMA_SxFCR_DMDIS_Msk #define DMA_SxFCR_FTH_Pos (0U) #define DMA_SxFCR_FTH_Msk (0x3U << DMA_SxFCR_FTH_Pos) /*!< 0x00000003 */ #define DMA_SxFCR_FTH DMA_SxFCR_FTH_Msk #define DMA_SxFCR_FTH_0 (0x1U << DMA_SxFCR_FTH_Pos) /*!< 0x00000001 */ #define DMA_SxFCR_FTH_1 (0x2U << DMA_SxFCR_FTH_Pos) /*!< 0x00000002 */ /******************** Bits definition for DMA_LISR register *****************/ #define DMA_LISR_TCIF3_Pos (27U) #define DMA_LISR_TCIF3_Msk (0x1U << DMA_LISR_TCIF3_Pos) /*!< 0x08000000 */ #define DMA_LISR_TCIF3 DMA_LISR_TCIF3_Msk #define DMA_LISR_HTIF3_Pos (26U) #define DMA_LISR_HTIF3_Msk (0x1U << DMA_LISR_HTIF3_Pos) /*!< 0x04000000 */ #define DMA_LISR_HTIF3 DMA_LISR_HTIF3_Msk #define DMA_LISR_TEIF3_Pos (25U) #define DMA_LISR_TEIF3_Msk (0x1U << DMA_LISR_TEIF3_Pos) /*!< 0x02000000 */ #define DMA_LISR_TEIF3 DMA_LISR_TEIF3_Msk #define DMA_LISR_DMEIF3_Pos (24U) #define DMA_LISR_DMEIF3_Msk (0x1U << DMA_LISR_DMEIF3_Pos) /*!< 0x01000000 */ #define DMA_LISR_DMEIF3 DMA_LISR_DMEIF3_Msk #define DMA_LISR_FEIF3_Pos (22U) #define DMA_LISR_FEIF3_Msk (0x1U << DMA_LISR_FEIF3_Pos) /*!< 0x00400000 */ #define DMA_LISR_FEIF3 DMA_LISR_FEIF3_Msk #define DMA_LISR_TCIF2_Pos (21U) #define DMA_LISR_TCIF2_Msk (0x1U << DMA_LISR_TCIF2_Pos) /*!< 0x00200000 */ #define DMA_LISR_TCIF2 DMA_LISR_TCIF2_Msk #define DMA_LISR_HTIF2_Pos (20U) #define DMA_LISR_HTIF2_Msk (0x1U << DMA_LISR_HTIF2_Pos) /*!< 0x00100000 */ #define DMA_LISR_HTIF2 DMA_LISR_HTIF2_Msk #define DMA_LISR_TEIF2_Pos (19U) #define DMA_LISR_TEIF2_Msk (0x1U << DMA_LISR_TEIF2_Pos) /*!< 0x00080000 */ #define DMA_LISR_TEIF2 DMA_LISR_TEIF2_Msk #define DMA_LISR_DMEIF2_Pos (18U) #define DMA_LISR_DMEIF2_Msk (0x1U << DMA_LISR_DMEIF2_Pos) /*!< 0x00040000 */ #define DMA_LISR_DMEIF2 DMA_LISR_DMEIF2_Msk #define DMA_LISR_FEIF2_Pos (16U) #define DMA_LISR_FEIF2_Msk (0x1U << DMA_LISR_FEIF2_Pos) /*!< 0x00010000 */ #define DMA_LISR_FEIF2 DMA_LISR_FEIF2_Msk #define DMA_LISR_TCIF1_Pos (11U) #define DMA_LISR_TCIF1_Msk (0x1U << DMA_LISR_TCIF1_Pos) /*!< 0x00000800 */ #define DMA_LISR_TCIF1 DMA_LISR_TCIF1_Msk #define DMA_LISR_HTIF1_Pos (10U) #define DMA_LISR_HTIF1_Msk (0x1U << DMA_LISR_HTIF1_Pos) /*!< 0x00000400 */ #define DMA_LISR_HTIF1 DMA_LISR_HTIF1_Msk #define DMA_LISR_TEIF1_Pos (9U) #define DMA_LISR_TEIF1_Msk (0x1U << DMA_LISR_TEIF1_Pos) /*!< 0x00000200 */ #define DMA_LISR_TEIF1 DMA_LISR_TEIF1_Msk #define DMA_LISR_DMEIF1_Pos (8U) #define DMA_LISR_DMEIF1_Msk (0x1U << DMA_LISR_DMEIF1_Pos) /*!< 0x00000100 */ #define DMA_LISR_DMEIF1 DMA_LISR_DMEIF1_Msk #define DMA_LISR_FEIF1_Pos (6U) #define DMA_LISR_FEIF1_Msk (0x1U << DMA_LISR_FEIF1_Pos) /*!< 0x00000040 */ #define DMA_LISR_FEIF1 DMA_LISR_FEIF1_Msk #define DMA_LISR_TCIF0_Pos (5U) #define DMA_LISR_TCIF0_Msk (0x1U << DMA_LISR_TCIF0_Pos) /*!< 0x00000020 */ #define DMA_LISR_TCIF0 DMA_LISR_TCIF0_Msk #define DMA_LISR_HTIF0_Pos (4U) #define DMA_LISR_HTIF0_Msk (0x1U << DMA_LISR_HTIF0_Pos) /*!< 0x00000010 */ #define DMA_LISR_HTIF0 DMA_LISR_HTIF0_Msk #define DMA_LISR_TEIF0_Pos (3U) #define DMA_LISR_TEIF0_Msk (0x1U << DMA_LISR_TEIF0_Pos) /*!< 0x00000008 */ #define DMA_LISR_TEIF0 DMA_LISR_TEIF0_Msk #define DMA_LISR_DMEIF0_Pos (2U) #define DMA_LISR_DMEIF0_Msk (0x1U << DMA_LISR_DMEIF0_Pos) /*!< 0x00000004 */ #define DMA_LISR_DMEIF0 DMA_LISR_DMEIF0_Msk #define DMA_LISR_FEIF0_Pos (0U) #define DMA_LISR_FEIF0_Msk (0x1U << DMA_LISR_FEIF0_Pos) /*!< 0x00000001 */ #define DMA_LISR_FEIF0 DMA_LISR_FEIF0_Msk /******************** Bits definition for DMA_HISR register *****************/ #define DMA_HISR_TCIF7_Pos (27U) #define DMA_HISR_TCIF7_Msk (0x1U << DMA_HISR_TCIF7_Pos) /*!< 0x08000000 */ #define DMA_HISR_TCIF7 DMA_HISR_TCIF7_Msk #define DMA_HISR_HTIF7_Pos (26U) #define DMA_HISR_HTIF7_Msk (0x1U << DMA_HISR_HTIF7_Pos) /*!< 0x04000000 */ #define DMA_HISR_HTIF7 DMA_HISR_HTIF7_Msk #define DMA_HISR_TEIF7_Pos (25U) #define DMA_HISR_TEIF7_Msk (0x1U << DMA_HISR_TEIF7_Pos) /*!< 0x02000000 */ #define DMA_HISR_TEIF7 DMA_HISR_TEIF7_Msk #define DMA_HISR_DMEIF7_Pos (24U) #define DMA_HISR_DMEIF7_Msk (0x1U << DMA_HISR_DMEIF7_Pos) /*!< 0x01000000 */ #define DMA_HISR_DMEIF7 DMA_HISR_DMEIF7_Msk #define DMA_HISR_FEIF7_Pos (22U) #define DMA_HISR_FEIF7_Msk (0x1U << DMA_HISR_FEIF7_Pos) /*!< 0x00400000 */ #define DMA_HISR_FEIF7 DMA_HISR_FEIF7_Msk #define DMA_HISR_TCIF6_Pos (21U) #define DMA_HISR_TCIF6_Msk (0x1U << DMA_HISR_TCIF6_Pos) /*!< 0x00200000 */ #define DMA_HISR_TCIF6 DMA_HISR_TCIF6_Msk #define DMA_HISR_HTIF6_Pos (20U) #define DMA_HISR_HTIF6_Msk (0x1U << DMA_HISR_HTIF6_Pos) /*!< 0x00100000 */ #define DMA_HISR_HTIF6 DMA_HISR_HTIF6_Msk #define DMA_HISR_TEIF6_Pos (19U) #define DMA_HISR_TEIF6_Msk (0x1U << DMA_HISR_TEIF6_Pos) /*!< 0x00080000 */ #define DMA_HISR_TEIF6 DMA_HISR_TEIF6_Msk #define DMA_HISR_DMEIF6_Pos (18U) #define DMA_HISR_DMEIF6_Msk (0x1U << DMA_HISR_DMEIF6_Pos) /*!< 0x00040000 */ #define DMA_HISR_DMEIF6 DMA_HISR_DMEIF6_Msk #define DMA_HISR_FEIF6_Pos (16U) #define DMA_HISR_FEIF6_Msk (0x1U << DMA_HISR_FEIF6_Pos) /*!< 0x00010000 */ #define DMA_HISR_FEIF6 DMA_HISR_FEIF6_Msk #define DMA_HISR_TCIF5_Pos (11U) #define DMA_HISR_TCIF5_Msk (0x1U << DMA_HISR_TCIF5_Pos) /*!< 0x00000800 */ #define DMA_HISR_TCIF5 DMA_HISR_TCIF5_Msk #define DMA_HISR_HTIF5_Pos (10U) #define DMA_HISR_HTIF5_Msk (0x1U << DMA_HISR_HTIF5_Pos) /*!< 0x00000400 */ #define DMA_HISR_HTIF5 DMA_HISR_HTIF5_Msk #define DMA_HISR_TEIF5_Pos (9U) #define DMA_HISR_TEIF5_Msk (0x1U << DMA_HISR_TEIF5_Pos) /*!< 0x00000200 */ #define DMA_HISR_TEIF5 DMA_HISR_TEIF5_Msk #define DMA_HISR_DMEIF5_Pos (8U) #define DMA_HISR_DMEIF5_Msk (0x1U << DMA_HISR_DMEIF5_Pos) /*!< 0x00000100 */ #define DMA_HISR_DMEIF5 DMA_HISR_DMEIF5_Msk #define DMA_HISR_FEIF5_Pos (6U) #define DMA_HISR_FEIF5_Msk (0x1U << DMA_HISR_FEIF5_Pos) /*!< 0x00000040 */ #define DMA_HISR_FEIF5 DMA_HISR_FEIF5_Msk #define DMA_HISR_TCIF4_Pos (5U) #define DMA_HISR_TCIF4_Msk (0x1U << DMA_HISR_TCIF4_Pos) /*!< 0x00000020 */ #define DMA_HISR_TCIF4 DMA_HISR_TCIF4_Msk #define DMA_HISR_HTIF4_Pos (4U) #define DMA_HISR_HTIF4_Msk (0x1U << DMA_HISR_HTIF4_Pos) /*!< 0x00000010 */ #define DMA_HISR_HTIF4 DMA_HISR_HTIF4_Msk #define DMA_HISR_TEIF4_Pos (3U) #define DMA_HISR_TEIF4_Msk (0x1U << DMA_HISR_TEIF4_Pos) /*!< 0x00000008 */ #define DMA_HISR_TEIF4 DMA_HISR_TEIF4_Msk #define DMA_HISR_DMEIF4_Pos (2U) #define DMA_HISR_DMEIF4_Msk (0x1U << DMA_HISR_DMEIF4_Pos) /*!< 0x00000004 */ #define DMA_HISR_DMEIF4 DMA_HISR_DMEIF4_Msk #define DMA_HISR_FEIF4_Pos (0U) #define DMA_HISR_FEIF4_Msk (0x1U << DMA_HISR_FEIF4_Pos) /*!< 0x00000001 */ #define DMA_HISR_FEIF4 DMA_HISR_FEIF4_Msk /******************** Bits definition for DMA_LIFCR register ****************/ #define DMA_LIFCR_CTCIF3_Pos (27U) #define DMA_LIFCR_CTCIF3_Msk (0x1U << DMA_LIFCR_CTCIF3_Pos) /*!< 0x08000000 */ #define DMA_LIFCR_CTCIF3 DMA_LIFCR_CTCIF3_Msk #define DMA_LIFCR_CHTIF3_Pos (26U) #define DMA_LIFCR_CHTIF3_Msk (0x1U << DMA_LIFCR_CHTIF3_Pos) /*!< 0x04000000 */ #define DMA_LIFCR_CHTIF3 DMA_LIFCR_CHTIF3_Msk #define DMA_LIFCR_CTEIF3_Pos (25U) #define DMA_LIFCR_CTEIF3_Msk (0x1U << DMA_LIFCR_CTEIF3_Pos) /*!< 0x02000000 */ #define DMA_LIFCR_CTEIF3 DMA_LIFCR_CTEIF3_Msk #define DMA_LIFCR_CDMEIF3_Pos (24U) #define DMA_LIFCR_CDMEIF3_Msk (0x1U << DMA_LIFCR_CDMEIF3_Pos) /*!< 0x01000000 */ #define DMA_LIFCR_CDMEIF3 DMA_LIFCR_CDMEIF3_Msk #define DMA_LIFCR_CFEIF3_Pos (22U) #define DMA_LIFCR_CFEIF3_Msk (0x1U << DMA_LIFCR_CFEIF3_Pos) /*!< 0x00400000 */ #define DMA_LIFCR_CFEIF3 DMA_LIFCR_CFEIF3_Msk #define DMA_LIFCR_CTCIF2_Pos (21U) #define DMA_LIFCR_CTCIF2_Msk (0x1U << DMA_LIFCR_CTCIF2_Pos) /*!< 0x00200000 */ #define DMA_LIFCR_CTCIF2 DMA_LIFCR_CTCIF2_Msk #define DMA_LIFCR_CHTIF2_Pos (20U) #define DMA_LIFCR_CHTIF2_Msk (0x1U << DMA_LIFCR_CHTIF2_Pos) /*!< 0x00100000 */ #define DMA_LIFCR_CHTIF2 DMA_LIFCR_CHTIF2_Msk #define DMA_LIFCR_CTEIF2_Pos (19U) #define DMA_LIFCR_CTEIF2_Msk (0x1U << DMA_LIFCR_CTEIF2_Pos) /*!< 0x00080000 */ #define DMA_LIFCR_CTEIF2 DMA_LIFCR_CTEIF2_Msk #define DMA_LIFCR_CDMEIF2_Pos (18U) #define DMA_LIFCR_CDMEIF2_Msk (0x1U << DMA_LIFCR_CDMEIF2_Pos) /*!< 0x00040000 */ #define DMA_LIFCR_CDMEIF2 DMA_LIFCR_CDMEIF2_Msk #define DMA_LIFCR_CFEIF2_Pos (16U) #define DMA_LIFCR_CFEIF2_Msk (0x1U << DMA_LIFCR_CFEIF2_Pos) /*!< 0x00010000 */ #define DMA_LIFCR_CFEIF2 DMA_LIFCR_CFEIF2_Msk #define DMA_LIFCR_CTCIF1_Pos (11U) #define DMA_LIFCR_CTCIF1_Msk (0x1U << DMA_LIFCR_CTCIF1_Pos) /*!< 0x00000800 */ #define DMA_LIFCR_CTCIF1 DMA_LIFCR_CTCIF1_Msk #define DMA_LIFCR_CHTIF1_Pos (10U) #define DMA_LIFCR_CHTIF1_Msk (0x1U << DMA_LIFCR_CHTIF1_Pos) /*!< 0x00000400 */ #define DMA_LIFCR_CHTIF1 DMA_LIFCR_CHTIF1_Msk #define DMA_LIFCR_CTEIF1_Pos (9U) #define DMA_LIFCR_CTEIF1_Msk (0x1U << DMA_LIFCR_CTEIF1_Pos) /*!< 0x00000200 */ #define DMA_LIFCR_CTEIF1 DMA_LIFCR_CTEIF1_Msk #define DMA_LIFCR_CDMEIF1_Pos (8U) #define DMA_LIFCR_CDMEIF1_Msk (0x1U << DMA_LIFCR_CDMEIF1_Pos) /*!< 0x00000100 */ #define DMA_LIFCR_CDMEIF1 DMA_LIFCR_CDMEIF1_Msk #define DMA_LIFCR_CFEIF1_Pos (6U) #define DMA_LIFCR_CFEIF1_Msk (0x1U << DMA_LIFCR_CFEIF1_Pos) /*!< 0x00000040 */ #define DMA_LIFCR_CFEIF1 DMA_LIFCR_CFEIF1_Msk #define DMA_LIFCR_CTCIF0_Pos (5U) #define DMA_LIFCR_CTCIF0_Msk (0x1U << DMA_LIFCR_CTCIF0_Pos) /*!< 0x00000020 */ #define DMA_LIFCR_CTCIF0 DMA_LIFCR_CTCIF0_Msk #define DMA_LIFCR_CHTIF0_Pos (4U) #define DMA_LIFCR_CHTIF0_Msk (0x1U << DMA_LIFCR_CHTIF0_Pos) /*!< 0x00000010 */ #define DMA_LIFCR_CHTIF0 DMA_LIFCR_CHTIF0_Msk #define DMA_LIFCR_CTEIF0_Pos (3U) #define DMA_LIFCR_CTEIF0_Msk (0x1U << DMA_LIFCR_CTEIF0_Pos) /*!< 0x00000008 */ #define DMA_LIFCR_CTEIF0 DMA_LIFCR_CTEIF0_Msk #define DMA_LIFCR_CDMEIF0_Pos (2U) #define DMA_LIFCR_CDMEIF0_Msk (0x1U << DMA_LIFCR_CDMEIF0_Pos) /*!< 0x00000004 */ #define DMA_LIFCR_CDMEIF0 DMA_LIFCR_CDMEIF0_Msk #define DMA_LIFCR_CFEIF0_Pos (0U) #define DMA_LIFCR_CFEIF0_Msk (0x1U << DMA_LIFCR_CFEIF0_Pos) /*!< 0x00000001 */ #define DMA_LIFCR_CFEIF0 DMA_LIFCR_CFEIF0_Msk /******************** Bits definition for DMA_HIFCR register ****************/ #define DMA_HIFCR_CTCIF7_Pos (27U) #define DMA_HIFCR_CTCIF7_Msk (0x1U << DMA_HIFCR_CTCIF7_Pos) /*!< 0x08000000 */ #define DMA_HIFCR_CTCIF7 DMA_HIFCR_CTCIF7_Msk #define DMA_HIFCR_CHTIF7_Pos (26U) #define DMA_HIFCR_CHTIF7_Msk (0x1U << DMA_HIFCR_CHTIF7_Pos) /*!< 0x04000000 */ #define DMA_HIFCR_CHTIF7 DMA_HIFCR_CHTIF7_Msk #define DMA_HIFCR_CTEIF7_Pos (25U) #define DMA_HIFCR_CTEIF7_Msk (0x1U << DMA_HIFCR_CTEIF7_Pos) /*!< 0x02000000 */ #define DMA_HIFCR_CTEIF7 DMA_HIFCR_CTEIF7_Msk #define DMA_HIFCR_CDMEIF7_Pos (24U) #define DMA_HIFCR_CDMEIF7_Msk (0x1U << DMA_HIFCR_CDMEIF7_Pos) /*!< 0x01000000 */ #define DMA_HIFCR_CDMEIF7 DMA_HIFCR_CDMEIF7_Msk #define DMA_HIFCR_CFEIF7_Pos (22U) #define DMA_HIFCR_CFEIF7_Msk (0x1U << DMA_HIFCR_CFEIF7_Pos) /*!< 0x00400000 */ #define DMA_HIFCR_CFEIF7 DMA_HIFCR_CFEIF7_Msk #define DMA_HIFCR_CTCIF6_Pos (21U) #define DMA_HIFCR_CTCIF6_Msk (0x1U << DMA_HIFCR_CTCIF6_Pos) /*!< 0x00200000 */ #define DMA_HIFCR_CTCIF6 DMA_HIFCR_CTCIF6_Msk #define DMA_HIFCR_CHTIF6_Pos (20U) #define DMA_HIFCR_CHTIF6_Msk (0x1U << DMA_HIFCR_CHTIF6_Pos) /*!< 0x00100000 */ #define DMA_HIFCR_CHTIF6 DMA_HIFCR_CHTIF6_Msk #define DMA_HIFCR_CTEIF6_Pos (19U) #define DMA_HIFCR_CTEIF6_Msk (0x1U << DMA_HIFCR_CTEIF6_Pos) /*!< 0x00080000 */ #define DMA_HIFCR_CTEIF6 DMA_HIFCR_CTEIF6_Msk #define DMA_HIFCR_CDMEIF6_Pos (18U) #define DMA_HIFCR_CDMEIF6_Msk (0x1U << DMA_HIFCR_CDMEIF6_Pos) /*!< 0x00040000 */ #define DMA_HIFCR_CDMEIF6 DMA_HIFCR_CDMEIF6_Msk #define DMA_HIFCR_CFEIF6_Pos (16U) #define DMA_HIFCR_CFEIF6_Msk (0x1U << DMA_HIFCR_CFEIF6_Pos) /*!< 0x00010000 */ #define DMA_HIFCR_CFEIF6 DMA_HIFCR_CFEIF6_Msk #define DMA_HIFCR_CTCIF5_Pos (11U) #define DMA_HIFCR_CTCIF5_Msk (0x1U << DMA_HIFCR_CTCIF5_Pos) /*!< 0x00000800 */ #define DMA_HIFCR_CTCIF5 DMA_HIFCR_CTCIF5_Msk #define DMA_HIFCR_CHTIF5_Pos (10U) #define DMA_HIFCR_CHTIF5_Msk (0x1U << DMA_HIFCR_CHTIF5_Pos) /*!< 0x00000400 */ #define DMA_HIFCR_CHTIF5 DMA_HIFCR_CHTIF5_Msk #define DMA_HIFCR_CTEIF5_Pos (9U) #define DMA_HIFCR_CTEIF5_Msk (0x1U << DMA_HIFCR_CTEIF5_Pos) /*!< 0x00000200 */ #define DMA_HIFCR_CTEIF5 DMA_HIFCR_CTEIF5_Msk #define DMA_HIFCR_CDMEIF5_Pos (8U) #define DMA_HIFCR_CDMEIF5_Msk (0x1U << DMA_HIFCR_CDMEIF5_Pos) /*!< 0x00000100 */ #define DMA_HIFCR_CDMEIF5 DMA_HIFCR_CDMEIF5_Msk #define DMA_HIFCR_CFEIF5_Pos (6U) #define DMA_HIFCR_CFEIF5_Msk (0x1U << DMA_HIFCR_CFEIF5_Pos) /*!< 0x00000040 */ #define DMA_HIFCR_CFEIF5 DMA_HIFCR_CFEIF5_Msk #define DMA_HIFCR_CTCIF4_Pos (5U) #define DMA_HIFCR_CTCIF4_Msk (0x1U << DMA_HIFCR_CTCIF4_Pos) /*!< 0x00000020 */ #define DMA_HIFCR_CTCIF4 DMA_HIFCR_CTCIF4_Msk #define DMA_HIFCR_CHTIF4_Pos (4U) #define DMA_HIFCR_CHTIF4_Msk (0x1U << DMA_HIFCR_CHTIF4_Pos) /*!< 0x00000010 */ #define DMA_HIFCR_CHTIF4 DMA_HIFCR_CHTIF4_Msk #define DMA_HIFCR_CTEIF4_Pos (3U) #define DMA_HIFCR_CTEIF4_Msk (0x1U << DMA_HIFCR_CTEIF4_Pos) /*!< 0x00000008 */ #define DMA_HIFCR_CTEIF4 DMA_HIFCR_CTEIF4_Msk #define DMA_HIFCR_CDMEIF4_Pos (2U) #define DMA_HIFCR_CDMEIF4_Msk (0x1U << DMA_HIFCR_CDMEIF4_Pos) /*!< 0x00000004 */ #define DMA_HIFCR_CDMEIF4 DMA_HIFCR_CDMEIF4_Msk #define DMA_HIFCR_CFEIF4_Pos (0U) #define DMA_HIFCR_CFEIF4_Msk (0x1U << DMA_HIFCR_CFEIF4_Pos) /*!< 0x00000001 */ #define DMA_HIFCR_CFEIF4 DMA_HIFCR_CFEIF4_Msk /****************** Bit definition for DMA_SxPAR register ********************/ #define DMA_SxPAR_PA_Pos (0U) #define DMA_SxPAR_PA_Msk (0xFFFFFFFFU << DMA_SxPAR_PA_Pos) /*!< 0xFFFFFFFF */ #define DMA_SxPAR_PA DMA_SxPAR_PA_Msk /*!< Peripheral Address */ /****************** Bit definition for DMA_SxM0AR register ********************/ #define DMA_SxM0AR_M0A_Pos (0U) #define DMA_SxM0AR_M0A_Msk (0xFFFFFFFFU << DMA_SxM0AR_M0A_Pos) /*!< 0xFFFFFFFF */ #define DMA_SxM0AR_M0A DMA_SxM0AR_M0A_Msk /*!< Memory Address */ /****************** Bit definition for DMA_SxM1AR register ********************/ #define DMA_SxM1AR_M1A_Pos (0U) #define DMA_SxM1AR_M1A_Msk (0xFFFFFFFFU << DMA_SxM1AR_M1A_Pos) /*!< 0xFFFFFFFF */ #define DMA_SxM1AR_M1A DMA_SxM1AR_M1A_Msk /*!< Memory Address */ /******************************************************************************/ /* */ /* AHB Master DMA2D Controller (DMA2D) */ /* */ /******************************************************************************/ /******************** Bit definition for DMA2D_CR register ******************/ #define DMA2D_CR_START_Pos (0U) #define DMA2D_CR_START_Msk (0x1U << DMA2D_CR_START_Pos) /*!< 0x00000001 */ #define DMA2D_CR_START DMA2D_CR_START_Msk /*!< Start transfer */ #define DMA2D_CR_SUSP_Pos (1U) #define DMA2D_CR_SUSP_Msk (0x1U << DMA2D_CR_SUSP_Pos) /*!< 0x00000002 */ #define DMA2D_CR_SUSP DMA2D_CR_SUSP_Msk /*!< Suspend transfer */ #define DMA2D_CR_ABORT_Pos (2U) #define DMA2D_CR_ABORT_Msk (0x1U << DMA2D_CR_ABORT_Pos) /*!< 0x00000004 */ #define DMA2D_CR_ABORT DMA2D_CR_ABORT_Msk /*!< Abort transfer */ #define DMA2D_CR_TEIE_Pos (8U) #define DMA2D_CR_TEIE_Msk (0x1U << DMA2D_CR_TEIE_Pos) /*!< 0x00000100 */ #define DMA2D_CR_TEIE DMA2D_CR_TEIE_Msk /*!< Transfer Error Interrupt Enable */ #define DMA2D_CR_TCIE_Pos (9U) #define DMA2D_CR_TCIE_Msk (0x1U << DMA2D_CR_TCIE_Pos) /*!< 0x00000200 */ #define DMA2D_CR_TCIE DMA2D_CR_TCIE_Msk /*!< Transfer Complete Interrupt Enable */ #define DMA2D_CR_TWIE_Pos (10U) #define DMA2D_CR_TWIE_Msk (0x1U << DMA2D_CR_TWIE_Pos) /*!< 0x00000400 */ #define DMA2D_CR_TWIE DMA2D_CR_TWIE_Msk /*!< Transfer Watermark Interrupt Enable */ #define DMA2D_CR_CAEIE_Pos (11U) #define DMA2D_CR_CAEIE_Msk (0x1U << DMA2D_CR_CAEIE_Pos) /*!< 0x00000800 */ #define DMA2D_CR_CAEIE DMA2D_CR_CAEIE_Msk /*!< CLUT Access Error Interrupt Enable */ #define DMA2D_CR_CTCIE_Pos (12U) #define DMA2D_CR_CTCIE_Msk (0x1U << DMA2D_CR_CTCIE_Pos) /*!< 0x00001000 */ #define DMA2D_CR_CTCIE DMA2D_CR_CTCIE_Msk /*!< CLUT Transfer Complete Interrupt Enable */ #define DMA2D_CR_CEIE_Pos (13U) #define DMA2D_CR_CEIE_Msk (0x1U << DMA2D_CR_CEIE_Pos) /*!< 0x00002000 */ #define DMA2D_CR_CEIE DMA2D_CR_CEIE_Msk /*!< Configuration Error Interrupt Enable */ #define DMA2D_CR_MODE_Pos (16U) #define DMA2D_CR_MODE_Msk (0x3U << DMA2D_CR_MODE_Pos) /*!< 0x00030000 */ #define DMA2D_CR_MODE DMA2D_CR_MODE_Msk /*!< DMA2D Mode[1:0] */ #define DMA2D_CR_MODE_0 (0x1U << DMA2D_CR_MODE_Pos) /*!< 0x00010000 */ #define DMA2D_CR_MODE_1 (0x2U << DMA2D_CR_MODE_Pos) /*!< 0x00020000 */ /******************** Bit definition for DMA2D_ISR register *****************/ #define DMA2D_ISR_TEIF_Pos (0U) #define DMA2D_ISR_TEIF_Msk (0x1U << DMA2D_ISR_TEIF_Pos) /*!< 0x00000001 */ #define DMA2D_ISR_TEIF DMA2D_ISR_TEIF_Msk /*!< Transfer Error Interrupt Flag */ #define DMA2D_ISR_TCIF_Pos (1U) #define DMA2D_ISR_TCIF_Msk (0x1U << DMA2D_ISR_TCIF_Pos) /*!< 0x00000002 */ #define DMA2D_ISR_TCIF DMA2D_ISR_TCIF_Msk /*!< Transfer Complete Interrupt Flag */ #define DMA2D_ISR_TWIF_Pos (2U) #define DMA2D_ISR_TWIF_Msk (0x1U << DMA2D_ISR_TWIF_Pos) /*!< 0x00000004 */ #define DMA2D_ISR_TWIF DMA2D_ISR_TWIF_Msk /*!< Transfer Watermark Interrupt Flag */ #define DMA2D_ISR_CAEIF_Pos (3U) #define DMA2D_ISR_CAEIF_Msk (0x1U << DMA2D_ISR_CAEIF_Pos) /*!< 0x00000008 */ #define DMA2D_ISR_CAEIF DMA2D_ISR_CAEIF_Msk /*!< CLUT Access Error Interrupt Flag */ #define DMA2D_ISR_CTCIF_Pos (4U) #define DMA2D_ISR_CTCIF_Msk (0x1U << DMA2D_ISR_CTCIF_Pos) /*!< 0x00000010 */ #define DMA2D_ISR_CTCIF DMA2D_ISR_CTCIF_Msk /*!< CLUT Transfer Complete Interrupt Flag */ #define DMA2D_ISR_CEIF_Pos (5U) #define DMA2D_ISR_CEIF_Msk (0x1U << DMA2D_ISR_CEIF_Pos) /*!< 0x00000020 */ #define DMA2D_ISR_CEIF DMA2D_ISR_CEIF_Msk /*!< Configuration Error Interrupt Flag */ /******************** Bit definition for DMA2D_IFCR register ****************/ #define DMA2D_IFCR_CTEIF_Pos (0U) #define DMA2D_IFCR_CTEIF_Msk (0x1U << DMA2D_IFCR_CTEIF_Pos) /*!< 0x00000001 */ #define DMA2D_IFCR_CTEIF DMA2D_IFCR_CTEIF_Msk /*!< Clears Transfer Error Interrupt Flag */ #define DMA2D_IFCR_CTCIF_Pos (1U) #define DMA2D_IFCR_CTCIF_Msk (0x1U << DMA2D_IFCR_CTCIF_Pos) /*!< 0x00000002 */ #define DMA2D_IFCR_CTCIF DMA2D_IFCR_CTCIF_Msk /*!< Clears Transfer Complete Interrupt Flag */ #define DMA2D_IFCR_CTWIF_Pos (2U) #define DMA2D_IFCR_CTWIF_Msk (0x1U << DMA2D_IFCR_CTWIF_Pos) /*!< 0x00000004 */ #define DMA2D_IFCR_CTWIF DMA2D_IFCR_CTWIF_Msk /*!< Clears Transfer Watermark Interrupt Flag */ #define DMA2D_IFCR_CAECIF_Pos (3U) #define DMA2D_IFCR_CAECIF_Msk (0x1U << DMA2D_IFCR_CAECIF_Pos) /*!< 0x00000008 */ #define DMA2D_IFCR_CAECIF DMA2D_IFCR_CAECIF_Msk /*!< Clears CLUT Access Error Interrupt Flag */ #define DMA2D_IFCR_CCTCIF_Pos (4U) #define DMA2D_IFCR_CCTCIF_Msk (0x1U << DMA2D_IFCR_CCTCIF_Pos) /*!< 0x00000010 */ #define DMA2D_IFCR_CCTCIF DMA2D_IFCR_CCTCIF_Msk /*!< Clears CLUT Transfer Complete Interrupt Flag */ #define DMA2D_IFCR_CCEIF_Pos (5U) #define DMA2D_IFCR_CCEIF_Msk (0x1U << DMA2D_IFCR_CCEIF_Pos) /*!< 0x00000020 */ #define DMA2D_IFCR_CCEIF DMA2D_IFCR_CCEIF_Msk /*!< Clears Configuration Error Interrupt Flag */ /* Legacy defines */ #define DMA2D_IFSR_CTEIF DMA2D_IFCR_CTEIF /*!< Clears Transfer Error Interrupt Flag */ #define DMA2D_IFSR_CTCIF DMA2D_IFCR_CTCIF /*!< Clears Transfer Complete Interrupt Flag */ #define DMA2D_IFSR_CTWIF DMA2D_IFCR_CTWIF /*!< Clears Transfer Watermark Interrupt Flag */ #define DMA2D_IFSR_CCAEIF DMA2D_IFCR_CAECIF /*!< Clears CLUT Access Error Interrupt Flag */ #define DMA2D_IFSR_CCTCIF DMA2D_IFCR_CCTCIF /*!< Clears CLUT Transfer Complete Interrupt Flag */ #define DMA2D_IFSR_CCEIF DMA2D_IFCR_CCEIF /*!< Clears Configuration Error Interrupt Flag */ /******************** Bit definition for DMA2D_FGMAR register ***************/ #define DMA2D_FGMAR_MA_Pos (0U) #define DMA2D_FGMAR_MA_Msk (0xFFFFFFFFU << DMA2D_FGMAR_MA_Pos) /*!< 0xFFFFFFFF */ #define DMA2D_FGMAR_MA DMA2D_FGMAR_MA_Msk /*!< Memory Address */ /******************** Bit definition for DMA2D_FGOR register ****************/ #define DMA2D_FGOR_LO_Pos (0U) #define DMA2D_FGOR_LO_Msk (0x3FFFU << DMA2D_FGOR_LO_Pos) /*!< 0x00003FFF */ #define DMA2D_FGOR_LO DMA2D_FGOR_LO_Msk /*!< Line Offset */ /******************** Bit definition for DMA2D_BGMAR register ***************/ #define DMA2D_BGMAR_MA_Pos (0U) #define DMA2D_BGMAR_MA_Msk (0xFFFFFFFFU << DMA2D_BGMAR_MA_Pos) /*!< 0xFFFFFFFF */ #define DMA2D_BGMAR_MA DMA2D_BGMAR_MA_Msk /*!< Memory Address */ /******************** Bit definition for DMA2D_BGOR register ****************/ #define DMA2D_BGOR_LO_Pos (0U) #define DMA2D_BGOR_LO_Msk (0x3FFFU << DMA2D_BGOR_LO_Pos) /*!< 0x00003FFF */ #define DMA2D_BGOR_LO DMA2D_BGOR_LO_Msk /*!< Line Offset */ /******************** Bit definition for DMA2D_FGPFCCR register *************/ #define DMA2D_FGPFCCR_CM_Pos (0U) #define DMA2D_FGPFCCR_CM_Msk (0xFU << DMA2D_FGPFCCR_CM_Pos) /*!< 0x0000000F */ #define DMA2D_FGPFCCR_CM DMA2D_FGPFCCR_CM_Msk /*!< Input color mode CM[3:0] */ #define DMA2D_FGPFCCR_CM_0 (0x1U << DMA2D_FGPFCCR_CM_Pos) /*!< 0x00000001 */ #define DMA2D_FGPFCCR_CM_1 (0x2U << DMA2D_FGPFCCR_CM_Pos) /*!< 0x00000002 */ #define DMA2D_FGPFCCR_CM_2 (0x4U << DMA2D_FGPFCCR_CM_Pos) /*!< 0x00000004 */ #define DMA2D_FGPFCCR_CM_3 (0x8U << DMA2D_FGPFCCR_CM_Pos) /*!< 0x00000008 */ #define DMA2D_FGPFCCR_CCM_Pos (4U) #define DMA2D_FGPFCCR_CCM_Msk (0x1U << DMA2D_FGPFCCR_CCM_Pos) /*!< 0x00000010 */ #define DMA2D_FGPFCCR_CCM DMA2D_FGPFCCR_CCM_Msk /*!< CLUT Color mode */ #define DMA2D_FGPFCCR_START_Pos (5U) #define DMA2D_FGPFCCR_START_Msk (0x1U << DMA2D_FGPFCCR_START_Pos) /*!< 0x00000020 */ #define DMA2D_FGPFCCR_START DMA2D_FGPFCCR_START_Msk /*!< Start */ #define DMA2D_FGPFCCR_CS_Pos (8U) #define DMA2D_FGPFCCR_CS_Msk (0xFFU << DMA2D_FGPFCCR_CS_Pos) /*!< 0x0000FF00 */ #define DMA2D_FGPFCCR_CS DMA2D_FGPFCCR_CS_Msk /*!< CLUT size */ #define DMA2D_FGPFCCR_AM_Pos (16U) #define DMA2D_FGPFCCR_AM_Msk (0x3U << DMA2D_FGPFCCR_AM_Pos) /*!< 0x00030000 */ #define DMA2D_FGPFCCR_AM DMA2D_FGPFCCR_AM_Msk /*!< Alpha mode AM[1:0] */ #define DMA2D_FGPFCCR_AM_0 (0x1U << DMA2D_FGPFCCR_AM_Pos) /*!< 0x00010000 */ #define DMA2D_FGPFCCR_AM_1 (0x2U << DMA2D_FGPFCCR_AM_Pos) /*!< 0x00020000 */ #define DMA2D_FGPFCCR_ALPHA_Pos (24U) #define DMA2D_FGPFCCR_ALPHA_Msk (0xFFU << DMA2D_FGPFCCR_ALPHA_Pos) /*!< 0xFF000000 */ #define DMA2D_FGPFCCR_ALPHA DMA2D_FGPFCCR_ALPHA_Msk /*!< Alpha value */ /******************** Bit definition for DMA2D_FGCOLR register **************/ #define DMA2D_FGCOLR_BLUE_Pos (0U) #define DMA2D_FGCOLR_BLUE_Msk (0xFFU << DMA2D_FGCOLR_BLUE_Pos) /*!< 0x000000FF */ #define DMA2D_FGCOLR_BLUE DMA2D_FGCOLR_BLUE_Msk /*!< Blue Value */ #define DMA2D_FGCOLR_GREEN_Pos (8U) #define DMA2D_FGCOLR_GREEN_Msk (0xFFU << DMA2D_FGCOLR_GREEN_Pos) /*!< 0x0000FF00 */ #define DMA2D_FGCOLR_GREEN DMA2D_FGCOLR_GREEN_Msk /*!< Green Value */ #define DMA2D_FGCOLR_RED_Pos (16U) #define DMA2D_FGCOLR_RED_Msk (0xFFU << DMA2D_FGCOLR_RED_Pos) /*!< 0x00FF0000 */ #define DMA2D_FGCOLR_RED DMA2D_FGCOLR_RED_Msk /*!< Red Value */ /******************** Bit definition for DMA2D_BGPFCCR register *************/ #define DMA2D_BGPFCCR_CM_Pos (0U) #define DMA2D_BGPFCCR_CM_Msk (0xFU << DMA2D_BGPFCCR_CM_Pos) /*!< 0x0000000F */ #define DMA2D_BGPFCCR_CM DMA2D_BGPFCCR_CM_Msk /*!< Input color mode CM[3:0] */ #define DMA2D_BGPFCCR_CM_0 (0x1U << DMA2D_BGPFCCR_CM_Pos) /*!< 0x00000001 */ #define DMA2D_BGPFCCR_CM_1 (0x2U << DMA2D_BGPFCCR_CM_Pos) /*!< 0x00000002 */ #define DMA2D_BGPFCCR_CM_2 (0x4U << DMA2D_BGPFCCR_CM_Pos) /*!< 0x00000004 */ #define DMA2D_BGPFCCR_CM_3 0x00000008U /*!< Input color mode CM bit 3 */ #define DMA2D_BGPFCCR_CCM_Pos (4U) #define DMA2D_BGPFCCR_CCM_Msk (0x1U << DMA2D_BGPFCCR_CCM_Pos) /*!< 0x00000010 */ #define DMA2D_BGPFCCR_CCM DMA2D_BGPFCCR_CCM_Msk /*!< CLUT Color mode */ #define DMA2D_BGPFCCR_START_Pos (5U) #define DMA2D_BGPFCCR_START_Msk (0x1U << DMA2D_BGPFCCR_START_Pos) /*!< 0x00000020 */ #define DMA2D_BGPFCCR_START DMA2D_BGPFCCR_START_Msk /*!< Start */ #define DMA2D_BGPFCCR_CS_Pos (8U) #define DMA2D_BGPFCCR_CS_Msk (0xFFU << DMA2D_BGPFCCR_CS_Pos) /*!< 0x0000FF00 */ #define DMA2D_BGPFCCR_CS DMA2D_BGPFCCR_CS_Msk /*!< CLUT size */ #define DMA2D_BGPFCCR_AM_Pos (16U) #define DMA2D_BGPFCCR_AM_Msk (0x3U << DMA2D_BGPFCCR_AM_Pos) /*!< 0x00030000 */ #define DMA2D_BGPFCCR_AM DMA2D_BGPFCCR_AM_Msk /*!< Alpha mode AM[1:0] */ #define DMA2D_BGPFCCR_AM_0 (0x1U << DMA2D_BGPFCCR_AM_Pos) /*!< 0x00010000 */ #define DMA2D_BGPFCCR_AM_1 (0x2U << DMA2D_BGPFCCR_AM_Pos) /*!< 0x00020000 */ #define DMA2D_BGPFCCR_ALPHA_Pos (24U) #define DMA2D_BGPFCCR_ALPHA_Msk (0xFFU << DMA2D_BGPFCCR_ALPHA_Pos) /*!< 0xFF000000 */ #define DMA2D_BGPFCCR_ALPHA DMA2D_BGPFCCR_ALPHA_Msk /*!< background Input Alpha value */ /******************** Bit definition for DMA2D_BGCOLR register **************/ #define DMA2D_BGCOLR_BLUE_Pos (0U) #define DMA2D_BGCOLR_BLUE_Msk (0xFFU << DMA2D_BGCOLR_BLUE_Pos) /*!< 0x000000FF */ #define DMA2D_BGCOLR_BLUE DMA2D_BGCOLR_BLUE_Msk /*!< Blue Value */ #define DMA2D_BGCOLR_GREEN_Pos (8U) #define DMA2D_BGCOLR_GREEN_Msk (0xFFU << DMA2D_BGCOLR_GREEN_Pos) /*!< 0x0000FF00 */ #define DMA2D_BGCOLR_GREEN DMA2D_BGCOLR_GREEN_Msk /*!< Green Value */ #define DMA2D_BGCOLR_RED_Pos (16U) #define DMA2D_BGCOLR_RED_Msk (0xFFU << DMA2D_BGCOLR_RED_Pos) /*!< 0x00FF0000 */ #define DMA2D_BGCOLR_RED DMA2D_BGCOLR_RED_Msk /*!< Red Value */ /******************** Bit definition for DMA2D_FGCMAR register **************/ #define DMA2D_FGCMAR_MA_Pos (0U) #define DMA2D_FGCMAR_MA_Msk (0xFFFFFFFFU << DMA2D_FGCMAR_MA_Pos) /*!< 0xFFFFFFFF */ #define DMA2D_FGCMAR_MA DMA2D_FGCMAR_MA_Msk /*!< Memory Address */ /******************** Bit definition for DMA2D_BGCMAR register **************/ #define DMA2D_BGCMAR_MA_Pos (0U) #define DMA2D_BGCMAR_MA_Msk (0xFFFFFFFFU << DMA2D_BGCMAR_MA_Pos) /*!< 0xFFFFFFFF */ #define DMA2D_BGCMAR_MA DMA2D_BGCMAR_MA_Msk /*!< Memory Address */ /******************** Bit definition for DMA2D_OPFCCR register **************/ #define DMA2D_OPFCCR_CM_Pos (0U) #define DMA2D_OPFCCR_CM_Msk (0x7U << DMA2D_OPFCCR_CM_Pos) /*!< 0x00000007 */ #define DMA2D_OPFCCR_CM DMA2D_OPFCCR_CM_Msk /*!< Color mode CM[2:0] */ #define DMA2D_OPFCCR_CM_0 (0x1U << DMA2D_OPFCCR_CM_Pos) /*!< 0x00000001 */ #define DMA2D_OPFCCR_CM_1 (0x2U << DMA2D_OPFCCR_CM_Pos) /*!< 0x00000002 */ #define DMA2D_OPFCCR_CM_2 (0x4U << DMA2D_OPFCCR_CM_Pos) /*!< 0x00000004 */ /******************** Bit definition for DMA2D_OCOLR register ***************/ /*!<Mode_ARGB8888/RGB888 */ #define DMA2D_OCOLR_BLUE_1 0x000000FFU /*!< BLUE Value */ #define DMA2D_OCOLR_GREEN_1 0x0000FF00U /*!< GREEN Value */ #define DMA2D_OCOLR_RED_1 0x00FF0000U /*!< Red Value */ #define DMA2D_OCOLR_ALPHA_1 0xFF000000U /*!< Alpha Channel Value */ /*!<Mode_RGB565 */ #define DMA2D_OCOLR_BLUE_2 0x0000001FU /*!< BLUE Value */ #define DMA2D_OCOLR_GREEN_2 0x000007E0U /*!< GREEN Value */ #define DMA2D_OCOLR_RED_2 0x0000F800U /*!< Red Value */ /*!<Mode_ARGB1555 */ #define DMA2D_OCOLR_BLUE_3 0x0000001FU /*!< BLUE Value */ #define DMA2D_OCOLR_GREEN_3 0x000003E0U /*!< GREEN Value */ #define DMA2D_OCOLR_RED_3 0x00007C00U /*!< Red Value */ #define DMA2D_OCOLR_ALPHA_3 0x00008000U /*!< Alpha Channel Value */ /*!<Mode_ARGB4444 */ #define DMA2D_OCOLR_BLUE_4 0x0000000FU /*!< BLUE Value */ #define DMA2D_OCOLR_GREEN_4 0x000000F0U /*!< GREEN Value */ #define DMA2D_OCOLR_RED_4 0x00000F00U /*!< Red Value */ #define DMA2D_OCOLR_ALPHA_4 0x0000F000U /*!< Alpha Channel Value */ /******************** Bit definition for DMA2D_OMAR register ****************/ #define DMA2D_OMAR_MA_Pos (0U) #define DMA2D_OMAR_MA_Msk (0xFFFFFFFFU << DMA2D_OMAR_MA_Pos) /*!< 0xFFFFFFFF */ #define DMA2D_OMAR_MA DMA2D_OMAR_MA_Msk /*!< Memory Address */ /******************** Bit definition for DMA2D_OOR register *****************/ #define DMA2D_OOR_LO_Pos (0U) #define DMA2D_OOR_LO_Msk (0x3FFFU << DMA2D_OOR_LO_Pos) /*!< 0x00003FFF */ #define DMA2D_OOR_LO DMA2D_OOR_LO_Msk /*!< Line Offset */ /******************** Bit definition for DMA2D_NLR register *****************/ #define DMA2D_NLR_NL_Pos (0U) #define DMA2D_NLR_NL_Msk (0xFFFFU << DMA2D_NLR_NL_Pos) /*!< 0x0000FFFF */ #define DMA2D_NLR_NL DMA2D_NLR_NL_Msk /*!< Number of Lines */ #define DMA2D_NLR_PL_Pos (16U) #define DMA2D_NLR_PL_Msk (0x3FFFU << DMA2D_NLR_PL_Pos) /*!< 0x3FFF0000 */ #define DMA2D_NLR_PL DMA2D_NLR_PL_Msk /*!< Pixel per Lines */ /******************** Bit definition for DMA2D_LWR register *****************/ #define DMA2D_LWR_LW_Pos (0U) #define DMA2D_LWR_LW_Msk (0xFFFFU << DMA2D_LWR_LW_Pos) /*!< 0x0000FFFF */ #define DMA2D_LWR_LW DMA2D_LWR_LW_Msk /*!< Line Watermark */ /******************** Bit definition for DMA2D_AMTCR register ***************/ #define DMA2D_AMTCR_EN_Pos (0U) #define DMA2D_AMTCR_EN_Msk (0x1U << DMA2D_AMTCR_EN_Pos) /*!< 0x00000001 */ #define DMA2D_AMTCR_EN DMA2D_AMTCR_EN_Msk /*!< Enable */ #define DMA2D_AMTCR_DT_Pos (8U) #define DMA2D_AMTCR_DT_Msk (0xFFU << DMA2D_AMTCR_DT_Pos) /*!< 0x0000FF00 */ #define DMA2D_AMTCR_DT DMA2D_AMTCR_DT_Msk /*!< Dead Time */ /******************** Bit definition for DMA2D_FGCLUT register **************/ /******************** Bit definition for DMA2D_BGCLUT register **************/ /******************************************************************************/ /* */ /* Display Serial Interface (DSI) */ /* */ /******************************************************************************/ /******************* Bit definition for DSI_VR register *****************/ #define DSI_VR_Pos (1U) #define DSI_VR_Msk (0x18999815U << DSI_VR_Pos) /*!< 0x3133302A */ #define DSI_VR DSI_VR_Msk /*!< DSI Host Version */ /******************* Bit definition for DSI_CR register *****************/ #define DSI_CR_EN_Pos (0U) #define DSI_CR_EN_Msk (0x1U << DSI_CR_EN_Pos) /*!< 0x00000001 */ #define DSI_CR_EN DSI_CR_EN_Msk /*!< DSI Host power up and reset */ /******************* Bit definition for DSI_CCR register ****************/ #define DSI_CCR_TXECKDIV_Pos (0U) #define DSI_CCR_TXECKDIV_Msk (0xFFU << DSI_CCR_TXECKDIV_Pos) /*!< 0x000000FF */ #define DSI_CCR_TXECKDIV DSI_CCR_TXECKDIV_Msk /*!< TX Escape Clock Division */ #define DSI_CCR_TXECKDIV0_Pos (0U) #define DSI_CCR_TXECKDIV0_Msk (0x1U << DSI_CCR_TXECKDIV0_Pos) /*!< 0x00000001 */ #define DSI_CCR_TXECKDIV0 DSI_CCR_TXECKDIV0_Msk #define DSI_CCR_TXECKDIV1_Pos (1U) #define DSI_CCR_TXECKDIV1_Msk (0x1U << DSI_CCR_TXECKDIV1_Pos) /*!< 0x00000002 */ #define DSI_CCR_TXECKDIV1 DSI_CCR_TXECKDIV1_Msk #define DSI_CCR_TXECKDIV2_Pos (2U) #define DSI_CCR_TXECKDIV2_Msk (0x1U << DSI_CCR_TXECKDIV2_Pos) /*!< 0x00000004 */ #define DSI_CCR_TXECKDIV2 DSI_CCR_TXECKDIV2_Msk #define DSI_CCR_TXECKDIV3_Pos (3U) #define DSI_CCR_TXECKDIV3_Msk (0x1U << DSI_CCR_TXECKDIV3_Pos) /*!< 0x00000008 */ #define DSI_CCR_TXECKDIV3 DSI_CCR_TXECKDIV3_Msk #define DSI_CCR_TXECKDIV4_Pos (4U) #define DSI_CCR_TXECKDIV4_Msk (0x1U << DSI_CCR_TXECKDIV4_Pos) /*!< 0x00000010 */ #define DSI_CCR_TXECKDIV4 DSI_CCR_TXECKDIV4_Msk #define DSI_CCR_TXECKDIV5_Pos (5U) #define DSI_CCR_TXECKDIV5_Msk (0x1U << DSI_CCR_TXECKDIV5_Pos) /*!< 0x00000020 */ #define DSI_CCR_TXECKDIV5 DSI_CCR_TXECKDIV5_Msk #define DSI_CCR_TXECKDIV6_Pos (6U) #define DSI_CCR_TXECKDIV6_Msk (0x1U << DSI_CCR_TXECKDIV6_Pos) /*!< 0x00000040 */ #define DSI_CCR_TXECKDIV6 DSI_CCR_TXECKDIV6_Msk #define DSI_CCR_TXECKDIV7_Pos (7U) #define DSI_CCR_TXECKDIV7_Msk (0x1U << DSI_CCR_TXECKDIV7_Pos) /*!< 0x00000080 */ #define DSI_CCR_TXECKDIV7 DSI_CCR_TXECKDIV7_Msk #define DSI_CCR_TOCKDIV_Pos (8U) #define DSI_CCR_TOCKDIV_Msk (0xFFU << DSI_CCR_TOCKDIV_Pos) /*!< 0x0000FF00 */ #define DSI_CCR_TOCKDIV DSI_CCR_TOCKDIV_Msk /*!< Timeout Clock Division */ #define DSI_CCR_TOCKDIV0_Pos (8U) #define DSI_CCR_TOCKDIV0_Msk (0x1U << DSI_CCR_TOCKDIV0_Pos) /*!< 0x00000100 */ #define DSI_CCR_TOCKDIV0 DSI_CCR_TOCKDIV0_Msk #define DSI_CCR_TOCKDIV1_Pos (9U) #define DSI_CCR_TOCKDIV1_Msk (0x1U << DSI_CCR_TOCKDIV1_Pos) /*!< 0x00000200 */ #define DSI_CCR_TOCKDIV1 DSI_CCR_TOCKDIV1_Msk #define DSI_CCR_TOCKDIV2_Pos (10U) #define DSI_CCR_TOCKDIV2_Msk (0x1U << DSI_CCR_TOCKDIV2_Pos) /*!< 0x00000400 */ #define DSI_CCR_TOCKDIV2 DSI_CCR_TOCKDIV2_Msk #define DSI_CCR_TOCKDIV3_Pos (11U) #define DSI_CCR_TOCKDIV3_Msk (0x1U << DSI_CCR_TOCKDIV3_Pos) /*!< 0x00000800 */ #define DSI_CCR_TOCKDIV3 DSI_CCR_TOCKDIV3_Msk #define DSI_CCR_TOCKDIV4_Pos (12U) #define DSI_CCR_TOCKDIV4_Msk (0x1U << DSI_CCR_TOCKDIV4_Pos) /*!< 0x00001000 */ #define DSI_CCR_TOCKDIV4 DSI_CCR_TOCKDIV4_Msk #define DSI_CCR_TOCKDIV5_Pos (13U) #define DSI_CCR_TOCKDIV5_Msk (0x1U << DSI_CCR_TOCKDIV5_Pos) /*!< 0x00002000 */ #define DSI_CCR_TOCKDIV5 DSI_CCR_TOCKDIV5_Msk #define DSI_CCR_TOCKDIV6_Pos (14U) #define DSI_CCR_TOCKDIV6_Msk (0x1U << DSI_CCR_TOCKDIV6_Pos) /*!< 0x00004000 */ #define DSI_CCR_TOCKDIV6 DSI_CCR_TOCKDIV6_Msk #define DSI_CCR_TOCKDIV7_Pos (15U) #define DSI_CCR_TOCKDIV7_Msk (0x1U << DSI_CCR_TOCKDIV7_Pos) /*!< 0x00008000 */ #define DSI_CCR_TOCKDIV7 DSI_CCR_TOCKDIV7_Msk /******************* Bit definition for DSI_LVCIDR register *************/ #define DSI_LVCIDR_VCID_Pos (0U) #define DSI_LVCIDR_VCID_Msk (0x3U << DSI_LVCIDR_VCID_Pos) /*!< 0x00000003 */ #define DSI_LVCIDR_VCID DSI_LVCIDR_VCID_Msk /*!< Virtual Channel ID */ #define DSI_LVCIDR_VCID0_Pos (0U) #define DSI_LVCIDR_VCID0_Msk (0x1U << DSI_LVCIDR_VCID0_Pos) /*!< 0x00000001 */ #define DSI_LVCIDR_VCID0 DSI_LVCIDR_VCID0_Msk #define DSI_LVCIDR_VCID1_Pos (1U) #define DSI_LVCIDR_VCID1_Msk (0x1U << DSI_LVCIDR_VCID1_Pos) /*!< 0x00000002 */ #define DSI_LVCIDR_VCID1 DSI_LVCIDR_VCID1_Msk /******************* Bit definition for DSI_LCOLCR register *************/ #define DSI_LCOLCR_COLC_Pos (0U) #define DSI_LCOLCR_COLC_Msk (0xFU << DSI_LCOLCR_COLC_Pos) /*!< 0x0000000F */ #define DSI_LCOLCR_COLC DSI_LCOLCR_COLC_Msk /*!< Color Coding */ #define DSI_LCOLCR_COLC0_Pos (0U) #define DSI_LCOLCR_COLC0_Msk (0x1U << DSI_LCOLCR_COLC0_Pos) /*!< 0x00000001 */ #define DSI_LCOLCR_COLC0 DSI_LCOLCR_COLC0_Msk #define DSI_LCOLCR_COLC1_Pos (5U) #define DSI_LCOLCR_COLC1_Msk (0x1U << DSI_LCOLCR_COLC1_Pos) /*!< 0x00000020 */ #define DSI_LCOLCR_COLC1 DSI_LCOLCR_COLC1_Msk #define DSI_LCOLCR_COLC2_Pos (6U) #define DSI_LCOLCR_COLC2_Msk (0x1U << DSI_LCOLCR_COLC2_Pos) /*!< 0x00000040 */ #define DSI_LCOLCR_COLC2 DSI_LCOLCR_COLC2_Msk #define DSI_LCOLCR_COLC3_Pos (7U) #define DSI_LCOLCR_COLC3_Msk (0x1U << DSI_LCOLCR_COLC3_Pos) /*!< 0x00000080 */ #define DSI_LCOLCR_COLC3 DSI_LCOLCR_COLC3_Msk #define DSI_LCOLCR_LPE_Pos (8U) #define DSI_LCOLCR_LPE_Msk (0x1U << DSI_LCOLCR_LPE_Pos) /*!< 0x00000100 */ #define DSI_LCOLCR_LPE DSI_LCOLCR_LPE_Msk /*!< Loosly Packet Enable */ /******************* Bit definition for DSI_LPCR register ***************/ #define DSI_LPCR_DEP_Pos (0U) #define DSI_LPCR_DEP_Msk (0x1U << DSI_LPCR_DEP_Pos) /*!< 0x00000001 */ #define DSI_LPCR_DEP DSI_LPCR_DEP_Msk /*!< Data Enable Polarity */ #define DSI_LPCR_VSP_Pos (1U) #define DSI_LPCR_VSP_Msk (0x1U << DSI_LPCR_VSP_Pos) /*!< 0x00000002 */ #define DSI_LPCR_VSP DSI_LPCR_VSP_Msk /*!< VSYNC Polarity */ #define DSI_LPCR_HSP_Pos (2U) #define DSI_LPCR_HSP_Msk (0x1U << DSI_LPCR_HSP_Pos) /*!< 0x00000004 */ #define DSI_LPCR_HSP DSI_LPCR_HSP_Msk /*!< HSYNC Polarity */ /******************* Bit definition for DSI_LPMCR register **************/ #define DSI_LPMCR_VLPSIZE_Pos (0U) #define DSI_LPMCR_VLPSIZE_Msk (0xFFU << DSI_LPMCR_VLPSIZE_Pos) /*!< 0x000000FF */ #define DSI_LPMCR_VLPSIZE DSI_LPMCR_VLPSIZE_Msk /*!< VACT Largest Packet Size */ #define DSI_LPMCR_VLPSIZE0_Pos (0U) #define DSI_LPMCR_VLPSIZE0_Msk (0x1U << DSI_LPMCR_VLPSIZE0_Pos) /*!< 0x00000001 */ #define DSI_LPMCR_VLPSIZE0 DSI_LPMCR_VLPSIZE0_Msk #define DSI_LPMCR_VLPSIZE1_Pos (1U) #define DSI_LPMCR_VLPSIZE1_Msk (0x1U << DSI_LPMCR_VLPSIZE1_Pos) /*!< 0x00000002 */ #define DSI_LPMCR_VLPSIZE1 DSI_LPMCR_VLPSIZE1_Msk #define DSI_LPMCR_VLPSIZE2_Pos (2U) #define DSI_LPMCR_VLPSIZE2_Msk (0x1U << DSI_LPMCR_VLPSIZE2_Pos) /*!< 0x00000004 */ #define DSI_LPMCR_VLPSIZE2 DSI_LPMCR_VLPSIZE2_Msk #define DSI_LPMCR_VLPSIZE3_Pos (3U) #define DSI_LPMCR_VLPSIZE3_Msk (0x1U << DSI_LPMCR_VLPSIZE3_Pos) /*!< 0x00000008 */ #define DSI_LPMCR_VLPSIZE3 DSI_LPMCR_VLPSIZE3_Msk #define DSI_LPMCR_VLPSIZE4_Pos (4U) #define DSI_LPMCR_VLPSIZE4_Msk (0x1U << DSI_LPMCR_VLPSIZE4_Pos) /*!< 0x00000010 */ #define DSI_LPMCR_VLPSIZE4 DSI_LPMCR_VLPSIZE4_Msk #define DSI_LPMCR_VLPSIZE5_Pos (5U) #define DSI_LPMCR_VLPSIZE5_Msk (0x1U << DSI_LPMCR_VLPSIZE5_Pos) /*!< 0x00000020 */ #define DSI_LPMCR_VLPSIZE5 DSI_LPMCR_VLPSIZE5_Msk #define DSI_LPMCR_VLPSIZE6_Pos (6U) #define DSI_LPMCR_VLPSIZE6_Msk (0x1U << DSI_LPMCR_VLPSIZE6_Pos) /*!< 0x00000040 */ #define DSI_LPMCR_VLPSIZE6 DSI_LPMCR_VLPSIZE6_Msk #define DSI_LPMCR_VLPSIZE7_Pos (7U) #define DSI_LPMCR_VLPSIZE7_Msk (0x1U << DSI_LPMCR_VLPSIZE7_Pos) /*!< 0x00000080 */ #define DSI_LPMCR_VLPSIZE7 DSI_LPMCR_VLPSIZE7_Msk #define DSI_LPMCR_LPSIZE_Pos (16U) #define DSI_LPMCR_LPSIZE_Msk (0xFFU << DSI_LPMCR_LPSIZE_Pos) /*!< 0x00FF0000 */ #define DSI_LPMCR_LPSIZE DSI_LPMCR_LPSIZE_Msk /*!< Largest Packet Size */ #define DSI_LPMCR_LPSIZE0_Pos (16U) #define DSI_LPMCR_LPSIZE0_Msk (0x1U << DSI_LPMCR_LPSIZE0_Pos) /*!< 0x00010000 */ #define DSI_LPMCR_LPSIZE0 DSI_LPMCR_LPSIZE0_Msk #define DSI_LPMCR_LPSIZE1_Pos (17U) #define DSI_LPMCR_LPSIZE1_Msk (0x1U << DSI_LPMCR_LPSIZE1_Pos) /*!< 0x00020000 */ #define DSI_LPMCR_LPSIZE1 DSI_LPMCR_LPSIZE1_Msk #define DSI_LPMCR_LPSIZE2_Pos (18U) #define DSI_LPMCR_LPSIZE2_Msk (0x1U << DSI_LPMCR_LPSIZE2_Pos) /*!< 0x00040000 */ #define DSI_LPMCR_LPSIZE2 DSI_LPMCR_LPSIZE2_Msk #define DSI_LPMCR_LPSIZE3_Pos (19U) #define DSI_LPMCR_LPSIZE3_Msk (0x1U << DSI_LPMCR_LPSIZE3_Pos) /*!< 0x00080000 */ #define DSI_LPMCR_LPSIZE3 DSI_LPMCR_LPSIZE3_Msk #define DSI_LPMCR_LPSIZE4_Pos (20U) #define DSI_LPMCR_LPSIZE4_Msk (0x1U << DSI_LPMCR_LPSIZE4_Pos) /*!< 0x00100000 */ #define DSI_LPMCR_LPSIZE4 DSI_LPMCR_LPSIZE4_Msk #define DSI_LPMCR_LPSIZE5_Pos (21U) #define DSI_LPMCR_LPSIZE5_Msk (0x1U << DSI_LPMCR_LPSIZE5_Pos) /*!< 0x00200000 */ #define DSI_LPMCR_LPSIZE5 DSI_LPMCR_LPSIZE5_Msk #define DSI_LPMCR_LPSIZE6_Pos (22U) #define DSI_LPMCR_LPSIZE6_Msk (0x1U << DSI_LPMCR_LPSIZE6_Pos) /*!< 0x00400000 */ #define DSI_LPMCR_LPSIZE6 DSI_LPMCR_LPSIZE6_Msk #define DSI_LPMCR_LPSIZE7_Pos (23U) #define DSI_LPMCR_LPSIZE7_Msk (0x1U << DSI_LPMCR_LPSIZE7_Pos) /*!< 0x00800000 */ #define DSI_LPMCR_LPSIZE7 DSI_LPMCR_LPSIZE7_Msk /******************* Bit definition for DSI_PCR register ****************/ #define DSI_PCR_ETTXE_Pos (0U) #define DSI_PCR_ETTXE_Msk (0x1U << DSI_PCR_ETTXE_Pos) /*!< 0x00000001 */ #define DSI_PCR_ETTXE DSI_PCR_ETTXE_Msk /*!< EoTp Transmission Enable */ #define DSI_PCR_ETRXE_Pos (1U) #define DSI_PCR_ETRXE_Msk (0x1U << DSI_PCR_ETRXE_Pos) /*!< 0x00000002 */ #define DSI_PCR_ETRXE DSI_PCR_ETRXE_Msk /*!< EoTp Reception Enable */ #define DSI_PCR_BTAE_Pos (2U) #define DSI_PCR_BTAE_Msk (0x1U << DSI_PCR_BTAE_Pos) /*!< 0x00000004 */ #define DSI_PCR_BTAE DSI_PCR_BTAE_Msk /*!< Bus Turn Around Enable */ #define DSI_PCR_ECCRXE_Pos (3U) #define DSI_PCR_ECCRXE_Msk (0x1U << DSI_PCR_ECCRXE_Pos) /*!< 0x00000008 */ #define DSI_PCR_ECCRXE DSI_PCR_ECCRXE_Msk /*!< ECC Reception Enable */ #define DSI_PCR_CRCRXE_Pos (4U) #define DSI_PCR_CRCRXE_Msk (0x1U << DSI_PCR_CRCRXE_Pos) /*!< 0x00000010 */ #define DSI_PCR_CRCRXE DSI_PCR_CRCRXE_Msk /*!< CRC Reception Enable */ /******************* Bit definition for DSI_GVCIDR register *************/ #define DSI_GVCIDR_VCID_Pos (0U) #define DSI_GVCIDR_VCID_Msk (0x3U << DSI_GVCIDR_VCID_Pos) /*!< 0x00000003 */ #define DSI_GVCIDR_VCID DSI_GVCIDR_VCID_Msk /*!< Virtual Channel ID */ #define DSI_GVCIDR_VCID0_Pos (0U) #define DSI_GVCIDR_VCID0_Msk (0x1U << DSI_GVCIDR_VCID0_Pos) /*!< 0x00000001 */ #define DSI_GVCIDR_VCID0 DSI_GVCIDR_VCID0_Msk #define DSI_GVCIDR_VCID1_Pos (1U) #define DSI_GVCIDR_VCID1_Msk (0x1U << DSI_GVCIDR_VCID1_Pos) /*!< 0x00000002 */ #define DSI_GVCIDR_VCID1 DSI_GVCIDR_VCID1_Msk /******************* Bit definition for DSI_MCR register ****************/ #define DSI_MCR_CMDM_Pos (0U) #define DSI_MCR_CMDM_Msk (0x1U << DSI_MCR_CMDM_Pos) /*!< 0x00000001 */ #define DSI_MCR_CMDM DSI_MCR_CMDM_Msk /*!< Command Mode */ /******************* Bit definition for DSI_VMCR register ***************/ #define DSI_VMCR_VMT_Pos (0U) #define DSI_VMCR_VMT_Msk (0x3U << DSI_VMCR_VMT_Pos) /*!< 0x00000003 */ #define DSI_VMCR_VMT DSI_VMCR_VMT_Msk /*!< Video Mode Type */ #define DSI_VMCR_VMT0_Pos (0U) #define DSI_VMCR_VMT0_Msk (0x1U << DSI_VMCR_VMT0_Pos) /*!< 0x00000001 */ #define DSI_VMCR_VMT0 DSI_VMCR_VMT0_Msk #define DSI_VMCR_VMT1_Pos (1U) #define DSI_VMCR_VMT1_Msk (0x1U << DSI_VMCR_VMT1_Pos) /*!< 0x00000002 */ #define DSI_VMCR_VMT1 DSI_VMCR_VMT1_Msk #define DSI_VMCR_LPVSAE_Pos (8U) #define DSI_VMCR_LPVSAE_Msk (0x1U << DSI_VMCR_LPVSAE_Pos) /*!< 0x00000100 */ #define DSI_VMCR_LPVSAE DSI_VMCR_LPVSAE_Msk /*!< Low-Power Vertical Sync Active Enable */ #define DSI_VMCR_LPVBPE_Pos (9U) #define DSI_VMCR_LPVBPE_Msk (0x1U << DSI_VMCR_LPVBPE_Pos) /*!< 0x00000200 */ #define DSI_VMCR_LPVBPE DSI_VMCR_LPVBPE_Msk /*!< Low-power Vertical Back-Porch Enable */ #define DSI_VMCR_LPVFPE_Pos (10U) #define DSI_VMCR_LPVFPE_Msk (0x1U << DSI_VMCR_LPVFPE_Pos) /*!< 0x00000400 */ #define DSI_VMCR_LPVFPE DSI_VMCR_LPVFPE_Msk /*!< Low-power Vertical Front-porch Enable */ #define DSI_VMCR_LPVAE_Pos (11U) #define DSI_VMCR_LPVAE_Msk (0x1U << DSI_VMCR_LPVAE_Pos) /*!< 0x00000800 */ #define DSI_VMCR_LPVAE DSI_VMCR_LPVAE_Msk /*!< Low-Power Vertical Active Enable */ #define DSI_VMCR_LPHBPE_Pos (12U) #define DSI_VMCR_LPHBPE_Msk (0x1U << DSI_VMCR_LPHBPE_Pos) /*!< 0x00001000 */ #define DSI_VMCR_LPHBPE DSI_VMCR_LPHBPE_Msk /*!< Low-Power Horizontal Back-Porch Enable */ #define DSI_VMCR_LPHFPE_Pos (13U) #define DSI_VMCR_LPHFPE_Msk (0x1U << DSI_VMCR_LPHFPE_Pos) /*!< 0x00002000 */ #define DSI_VMCR_LPHFPE DSI_VMCR_LPHFPE_Msk /*!< Low-Power Horizontal Front-Porch Enable */ #define DSI_VMCR_FBTAAE_Pos (14U) #define DSI_VMCR_FBTAAE_Msk (0x1U << DSI_VMCR_FBTAAE_Pos) /*!< 0x00004000 */ #define DSI_VMCR_FBTAAE DSI_VMCR_FBTAAE_Msk /*!< Frame Bus-Turn-Around Acknowledge Enable */ #define DSI_VMCR_LPCE_Pos (15U) #define DSI_VMCR_LPCE_Msk (0x1U << DSI_VMCR_LPCE_Pos) /*!< 0x00008000 */ #define DSI_VMCR_LPCE DSI_VMCR_LPCE_Msk /*!< Low-Power Command Enable */ #define DSI_VMCR_PGE_Pos (16U) #define DSI_VMCR_PGE_Msk (0x1U << DSI_VMCR_PGE_Pos) /*!< 0x00010000 */ #define DSI_VMCR_PGE DSI_VMCR_PGE_Msk /*!< Pattern Generator Enable */ #define DSI_VMCR_PGM_Pos (20U) #define DSI_VMCR_PGM_Msk (0x1U << DSI_VMCR_PGM_Pos) /*!< 0x00100000 */ #define DSI_VMCR_PGM DSI_VMCR_PGM_Msk /*!< Pattern Generator Mode */ #define DSI_VMCR_PGO_Pos (24U) #define DSI_VMCR_PGO_Msk (0x1U << DSI_VMCR_PGO_Pos) /*!< 0x01000000 */ #define DSI_VMCR_PGO DSI_VMCR_PGO_Msk /*!< Pattern Generator Orientation */ /******************* Bit definition for DSI_VPCR register ***************/ #define DSI_VPCR_VPSIZE_Pos (0U) #define DSI_VPCR_VPSIZE_Msk (0x3FFFU << DSI_VPCR_VPSIZE_Pos) /*!< 0x00003FFF */ #define DSI_VPCR_VPSIZE DSI_VPCR_VPSIZE_Msk /*!< Video Packet Size */ #define DSI_VPCR_VPSIZE0_Pos (0U) #define DSI_VPCR_VPSIZE0_Msk (0x1U << DSI_VPCR_VPSIZE0_Pos) /*!< 0x00000001 */ #define DSI_VPCR_VPSIZE0 DSI_VPCR_VPSIZE0_Msk #define DSI_VPCR_VPSIZE1_Pos (1U) #define DSI_VPCR_VPSIZE1_Msk (0x1U << DSI_VPCR_VPSIZE1_Pos) /*!< 0x00000002 */ #define DSI_VPCR_VPSIZE1 DSI_VPCR_VPSIZE1_Msk #define DSI_VPCR_VPSIZE2_Pos (2U) #define DSI_VPCR_VPSIZE2_Msk (0x1U << DSI_VPCR_VPSIZE2_Pos) /*!< 0x00000004 */ #define DSI_VPCR_VPSIZE2 DSI_VPCR_VPSIZE2_Msk #define DSI_VPCR_VPSIZE3_Pos (3U) #define DSI_VPCR_VPSIZE3_Msk (0x1U << DSI_VPCR_VPSIZE3_Pos) /*!< 0x00000008 */ #define DSI_VPCR_VPSIZE3 DSI_VPCR_VPSIZE3_Msk #define DSI_VPCR_VPSIZE4_Pos (4U) #define DSI_VPCR_VPSIZE4_Msk (0x1U << DSI_VPCR_VPSIZE4_Pos) /*!< 0x00000010 */ #define DSI_VPCR_VPSIZE4 DSI_VPCR_VPSIZE4_Msk #define DSI_VPCR_VPSIZE5_Pos (5U) #define DSI_VPCR_VPSIZE5_Msk (0x1U << DSI_VPCR_VPSIZE5_Pos) /*!< 0x00000020 */ #define DSI_VPCR_VPSIZE5 DSI_VPCR_VPSIZE5_Msk #define DSI_VPCR_VPSIZE6_Pos (6U) #define DSI_VPCR_VPSIZE6_Msk (0x1U << DSI_VPCR_VPSIZE6_Pos) /*!< 0x00000040 */ #define DSI_VPCR_VPSIZE6 DSI_VPCR_VPSIZE6_Msk #define DSI_VPCR_VPSIZE7_Pos (7U) #define DSI_VPCR_VPSIZE7_Msk (0x1U << DSI_VPCR_VPSIZE7_Pos) /*!< 0x00000080 */ #define DSI_VPCR_VPSIZE7 DSI_VPCR_VPSIZE7_Msk #define DSI_VPCR_VPSIZE8_Pos (8U) #define DSI_VPCR_VPSIZE8_Msk (0x1U << DSI_VPCR_VPSIZE8_Pos) /*!< 0x00000100 */ #define DSI_VPCR_VPSIZE8 DSI_VPCR_VPSIZE8_Msk #define DSI_VPCR_VPSIZE9_Pos (9U) #define DSI_VPCR_VPSIZE9_Msk (0x1U << DSI_VPCR_VPSIZE9_Pos) /*!< 0x00000200 */ #define DSI_VPCR_VPSIZE9 DSI_VPCR_VPSIZE9_Msk #define DSI_VPCR_VPSIZE10_Pos (10U) #define DSI_VPCR_VPSIZE10_Msk (0x1U << DSI_VPCR_VPSIZE10_Pos) /*!< 0x00000400 */ #define DSI_VPCR_VPSIZE10 DSI_VPCR_VPSIZE10_Msk #define DSI_VPCR_VPSIZE11_Pos (11U) #define DSI_VPCR_VPSIZE11_Msk (0x1U << DSI_VPCR_VPSIZE11_Pos) /*!< 0x00000800 */ #define DSI_VPCR_VPSIZE11 DSI_VPCR_VPSIZE11_Msk #define DSI_VPCR_VPSIZE12_Pos (12U) #define DSI_VPCR_VPSIZE12_Msk (0x1U << DSI_VPCR_VPSIZE12_Pos) /*!< 0x00001000 */ #define DSI_VPCR_VPSIZE12 DSI_VPCR_VPSIZE12_Msk #define DSI_VPCR_VPSIZE13_Pos (13U) #define DSI_VPCR_VPSIZE13_Msk (0x1U << DSI_VPCR_VPSIZE13_Pos) /*!< 0x00002000 */ #define DSI_VPCR_VPSIZE13 DSI_VPCR_VPSIZE13_Msk /******************* Bit definition for DSI_VCCR register ***************/ #define DSI_VCCR_NUMC_Pos (0U) #define DSI_VCCR_NUMC_Msk (0x1FFFU << DSI_VCCR_NUMC_Pos) /*!< 0x00001FFF */ #define DSI_VCCR_NUMC DSI_VCCR_NUMC_Msk /*!< Number of Chunks */ #define DSI_VCCR_NUMC0_Pos (0U) #define DSI_VCCR_NUMC0_Msk (0x1U << DSI_VCCR_NUMC0_Pos) /*!< 0x00000001 */ #define DSI_VCCR_NUMC0 DSI_VCCR_NUMC0_Msk #define DSI_VCCR_NUMC1_Pos (1U) #define DSI_VCCR_NUMC1_Msk (0x1U << DSI_VCCR_NUMC1_Pos) /*!< 0x00000002 */ #define DSI_VCCR_NUMC1 DSI_VCCR_NUMC1_Msk #define DSI_VCCR_NUMC2_Pos (2U) #define DSI_VCCR_NUMC2_Msk (0x1U << DSI_VCCR_NUMC2_Pos) /*!< 0x00000004 */ #define DSI_VCCR_NUMC2 DSI_VCCR_NUMC2_Msk #define DSI_VCCR_NUMC3_Pos (3U) #define DSI_VCCR_NUMC3_Msk (0x1U << DSI_VCCR_NUMC3_Pos) /*!< 0x00000008 */ #define DSI_VCCR_NUMC3 DSI_VCCR_NUMC3_Msk #define DSI_VCCR_NUMC4_Pos (4U) #define DSI_VCCR_NUMC4_Msk (0x1U << DSI_VCCR_NUMC4_Pos) /*!< 0x00000010 */ #define DSI_VCCR_NUMC4 DSI_VCCR_NUMC4_Msk #define DSI_VCCR_NUMC5_Pos (5U) #define DSI_VCCR_NUMC5_Msk (0x1U << DSI_VCCR_NUMC5_Pos) /*!< 0x00000020 */ #define DSI_VCCR_NUMC5 DSI_VCCR_NUMC5_Msk #define DSI_VCCR_NUMC6_Pos (6U) #define DSI_VCCR_NUMC6_Msk (0x1U << DSI_VCCR_NUMC6_Pos) /*!< 0x00000040 */ #define DSI_VCCR_NUMC6 DSI_VCCR_NUMC6_Msk #define DSI_VCCR_NUMC7_Pos (7U) #define DSI_VCCR_NUMC7_Msk (0x1U << DSI_VCCR_NUMC7_Pos) /*!< 0x00000080 */ #define DSI_VCCR_NUMC7 DSI_VCCR_NUMC7_Msk #define DSI_VCCR_NUMC8_Pos (8U) #define DSI_VCCR_NUMC8_Msk (0x1U << DSI_VCCR_NUMC8_Pos) /*!< 0x00000100 */ #define DSI_VCCR_NUMC8 DSI_VCCR_NUMC8_Msk #define DSI_VCCR_NUMC9_Pos (9U) #define DSI_VCCR_NUMC9_Msk (0x1U << DSI_VCCR_NUMC9_Pos) /*!< 0x00000200 */ #define DSI_VCCR_NUMC9 DSI_VCCR_NUMC9_Msk #define DSI_VCCR_NUMC10_Pos (10U) #define DSI_VCCR_NUMC10_Msk (0x1U << DSI_VCCR_NUMC10_Pos) /*!< 0x00000400 */ #define DSI_VCCR_NUMC10 DSI_VCCR_NUMC10_Msk #define DSI_VCCR_NUMC11_Pos (11U) #define DSI_VCCR_NUMC11_Msk (0x1U << DSI_VCCR_NUMC11_Pos) /*!< 0x00000800 */ #define DSI_VCCR_NUMC11 DSI_VCCR_NUMC11_Msk #define DSI_VCCR_NUMC12_Pos (12U) #define DSI_VCCR_NUMC12_Msk (0x1U << DSI_VCCR_NUMC12_Pos) /*!< 0x00001000 */ #define DSI_VCCR_NUMC12 DSI_VCCR_NUMC12_Msk /******************* Bit definition for DSI_VNPCR register **************/ #define DSI_VNPCR_NPSIZE_Pos (0U) #define DSI_VNPCR_NPSIZE_Msk (0x1FFFU << DSI_VNPCR_NPSIZE_Pos) /*!< 0x00001FFF */ #define DSI_VNPCR_NPSIZE DSI_VNPCR_NPSIZE_Msk /*!< Null Packet Size */ #define DSI_VNPCR_NPSIZE0_Pos (0U) #define DSI_VNPCR_NPSIZE0_Msk (0x1U << DSI_VNPCR_NPSIZE0_Pos) /*!< 0x00000001 */ #define DSI_VNPCR_NPSIZE0 DSI_VNPCR_NPSIZE0_Msk #define DSI_VNPCR_NPSIZE1_Pos (1U) #define DSI_VNPCR_NPSIZE1_Msk (0x1U << DSI_VNPCR_NPSIZE1_Pos) /*!< 0x00000002 */ #define DSI_VNPCR_NPSIZE1 DSI_VNPCR_NPSIZE1_Msk #define DSI_VNPCR_NPSIZE2_Pos (2U) #define DSI_VNPCR_NPSIZE2_Msk (0x1U << DSI_VNPCR_NPSIZE2_Pos) /*!< 0x00000004 */ #define DSI_VNPCR_NPSIZE2 DSI_VNPCR_NPSIZE2_Msk #define DSI_VNPCR_NPSIZE3_Pos (3U) #define DSI_VNPCR_NPSIZE3_Msk (0x1U << DSI_VNPCR_NPSIZE3_Pos) /*!< 0x00000008 */ #define DSI_VNPCR_NPSIZE3 DSI_VNPCR_NPSIZE3_Msk #define DSI_VNPCR_NPSIZE4_Pos (4U) #define DSI_VNPCR_NPSIZE4_Msk (0x1U << DSI_VNPCR_NPSIZE4_Pos) /*!< 0x00000010 */ #define DSI_VNPCR_NPSIZE4 DSI_VNPCR_NPSIZE4_Msk #define DSI_VNPCR_NPSIZE5_Pos (5U) #define DSI_VNPCR_NPSIZE5_Msk (0x1U << DSI_VNPCR_NPSIZE5_Pos) /*!< 0x00000020 */ #define DSI_VNPCR_NPSIZE5 DSI_VNPCR_NPSIZE5_Msk #define DSI_VNPCR_NPSIZE6_Pos (6U) #define DSI_VNPCR_NPSIZE6_Msk (0x1U << DSI_VNPCR_NPSIZE6_Pos) /*!< 0x00000040 */ #define DSI_VNPCR_NPSIZE6 DSI_VNPCR_NPSIZE6_Msk #define DSI_VNPCR_NPSIZE7_Pos (7U) #define DSI_VNPCR_NPSIZE7_Msk (0x1U << DSI_VNPCR_NPSIZE7_Pos) /*!< 0x00000080 */ #define DSI_VNPCR_NPSIZE7 DSI_VNPCR_NPSIZE7_Msk #define DSI_VNPCR_NPSIZE8_Pos (8U) #define DSI_VNPCR_NPSIZE8_Msk (0x1U << DSI_VNPCR_NPSIZE8_Pos) /*!< 0x00000100 */ #define DSI_VNPCR_NPSIZE8 DSI_VNPCR_NPSIZE8_Msk #define DSI_VNPCR_NPSIZE9_Pos (9U) #define DSI_VNPCR_NPSIZE9_Msk (0x1U << DSI_VNPCR_NPSIZE9_Pos) /*!< 0x00000200 */ #define DSI_VNPCR_NPSIZE9 DSI_VNPCR_NPSIZE9_Msk #define DSI_VNPCR_NPSIZE10_Pos (10U) #define DSI_VNPCR_NPSIZE10_Msk (0x1U << DSI_VNPCR_NPSIZE10_Pos) /*!< 0x00000400 */ #define DSI_VNPCR_NPSIZE10 DSI_VNPCR_NPSIZE10_Msk #define DSI_VNPCR_NPSIZE11_Pos (11U) #define DSI_VNPCR_NPSIZE11_Msk (0x1U << DSI_VNPCR_NPSIZE11_Pos) /*!< 0x00000800 */ #define DSI_VNPCR_NPSIZE11 DSI_VNPCR_NPSIZE11_Msk #define DSI_VNPCR_NPSIZE12_Pos (12U) #define DSI_VNPCR_NPSIZE12_Msk (0x1U << DSI_VNPCR_NPSIZE12_Pos) /*!< 0x00001000 */ #define DSI_VNPCR_NPSIZE12 DSI_VNPCR_NPSIZE12_Msk /******************* Bit definition for DSI_VHSACR register *************/ #define DSI_VHSACR_HSA_Pos (0U) #define DSI_VHSACR_HSA_Msk (0xFFFU << DSI_VHSACR_HSA_Pos) /*!< 0x00000FFF */ #define DSI_VHSACR_HSA DSI_VHSACR_HSA_Msk /*!< Horizontal Synchronism Active duration */ #define DSI_VHSACR_HSA0_Pos (0U) #define DSI_VHSACR_HSA0_Msk (0x1U << DSI_VHSACR_HSA0_Pos) /*!< 0x00000001 */ #define DSI_VHSACR_HSA0 DSI_VHSACR_HSA0_Msk #define DSI_VHSACR_HSA1_Pos (1U) #define DSI_VHSACR_HSA1_Msk (0x1U << DSI_VHSACR_HSA1_Pos) /*!< 0x00000002 */ #define DSI_VHSACR_HSA1 DSI_VHSACR_HSA1_Msk #define DSI_VHSACR_HSA2_Pos (2U) #define DSI_VHSACR_HSA2_Msk (0x1U << DSI_VHSACR_HSA2_Pos) /*!< 0x00000004 */ #define DSI_VHSACR_HSA2 DSI_VHSACR_HSA2_Msk #define DSI_VHSACR_HSA3_Pos (3U) #define DSI_VHSACR_HSA3_Msk (0x1U << DSI_VHSACR_HSA3_Pos) /*!< 0x00000008 */ #define DSI_VHSACR_HSA3 DSI_VHSACR_HSA3_Msk #define DSI_VHSACR_HSA4_Pos (4U) #define DSI_VHSACR_HSA4_Msk (0x1U << DSI_VHSACR_HSA4_Pos) /*!< 0x00000010 */ #define DSI_VHSACR_HSA4 DSI_VHSACR_HSA4_Msk #define DSI_VHSACR_HSA5_Pos (5U) #define DSI_VHSACR_HSA5_Msk (0x1U << DSI_VHSACR_HSA5_Pos) /*!< 0x00000020 */ #define DSI_VHSACR_HSA5 DSI_VHSACR_HSA5_Msk #define DSI_VHSACR_HSA6_Pos (6U) #define DSI_VHSACR_HSA6_Msk (0x1U << DSI_VHSACR_HSA6_Pos) /*!< 0x00000040 */ #define DSI_VHSACR_HSA6 DSI_VHSACR_HSA6_Msk #define DSI_VHSACR_HSA7_Pos (7U) #define DSI_VHSACR_HSA7_Msk (0x1U << DSI_VHSACR_HSA7_Pos) /*!< 0x00000080 */ #define DSI_VHSACR_HSA7 DSI_VHSACR_HSA7_Msk #define DSI_VHSACR_HSA8_Pos (8U) #define DSI_VHSACR_HSA8_Msk (0x1U << DSI_VHSACR_HSA8_Pos) /*!< 0x00000100 */ #define DSI_VHSACR_HSA8 DSI_VHSACR_HSA8_Msk #define DSI_VHSACR_HSA9_Pos (9U) #define DSI_VHSACR_HSA9_Msk (0x1U << DSI_VHSACR_HSA9_Pos) /*!< 0x00000200 */ #define DSI_VHSACR_HSA9 DSI_VHSACR_HSA9_Msk #define DSI_VHSACR_HSA10_Pos (10U) #define DSI_VHSACR_HSA10_Msk (0x1U << DSI_VHSACR_HSA10_Pos) /*!< 0x00000400 */ #define DSI_VHSACR_HSA10 DSI_VHSACR_HSA10_Msk #define DSI_VHSACR_HSA11_Pos (11U) #define DSI_VHSACR_HSA11_Msk (0x1U << DSI_VHSACR_HSA11_Pos) /*!< 0x00000800 */ #define DSI_VHSACR_HSA11 DSI_VHSACR_HSA11_Msk /******************* Bit definition for DSI_VHBPCR register *************/ #define DSI_VHBPCR_HBP_Pos (0U) #define DSI_VHBPCR_HBP_Msk (0xFFFU << DSI_VHBPCR_HBP_Pos) /*!< 0x00000FFF */ #define DSI_VHBPCR_HBP DSI_VHBPCR_HBP_Msk /*!< Horizontal Back-Porch duration */ #define DSI_VHBPCR_HBP0_Pos (0U) #define DSI_VHBPCR_HBP0_Msk (0x1U << DSI_VHBPCR_HBP0_Pos) /*!< 0x00000001 */ #define DSI_VHBPCR_HBP0 DSI_VHBPCR_HBP0_Msk #define DSI_VHBPCR_HBP1_Pos (1U) #define DSI_VHBPCR_HBP1_Msk (0x1U << DSI_VHBPCR_HBP1_Pos) /*!< 0x00000002 */ #define DSI_VHBPCR_HBP1 DSI_VHBPCR_HBP1_Msk #define DSI_VHBPCR_HBP2_Pos (2U) #define DSI_VHBPCR_HBP2_Msk (0x1U << DSI_VHBPCR_HBP2_Pos) /*!< 0x00000004 */ #define DSI_VHBPCR_HBP2 DSI_VHBPCR_HBP2_Msk #define DSI_VHBPCR_HBP3_Pos (3U) #define DSI_VHBPCR_HBP3_Msk (0x1U << DSI_VHBPCR_HBP3_Pos) /*!< 0x00000008 */ #define DSI_VHBPCR_HBP3 DSI_VHBPCR_HBP3_Msk #define DSI_VHBPCR_HBP4_Pos (4U) #define DSI_VHBPCR_HBP4_Msk (0x1U << DSI_VHBPCR_HBP4_Pos) /*!< 0x00000010 */ #define DSI_VHBPCR_HBP4 DSI_VHBPCR_HBP4_Msk #define DSI_VHBPCR_HBP5_Pos (5U) #define DSI_VHBPCR_HBP5_Msk (0x1U << DSI_VHBPCR_HBP5_Pos) /*!< 0x00000020 */ #define DSI_VHBPCR_HBP5 DSI_VHBPCR_HBP5_Msk #define DSI_VHBPCR_HBP6_Pos (6U) #define DSI_VHBPCR_HBP6_Msk (0x1U << DSI_VHBPCR_HBP6_Pos) /*!< 0x00000040 */ #define DSI_VHBPCR_HBP6 DSI_VHBPCR_HBP6_Msk #define DSI_VHBPCR_HBP7_Pos (7U) #define DSI_VHBPCR_HBP7_Msk (0x1U << DSI_VHBPCR_HBP7_Pos) /*!< 0x00000080 */ #define DSI_VHBPCR_HBP7 DSI_VHBPCR_HBP7_Msk #define DSI_VHBPCR_HBP8_Pos (8U) #define DSI_VHBPCR_HBP8_Msk (0x1U << DSI_VHBPCR_HBP8_Pos) /*!< 0x00000100 */ #define DSI_VHBPCR_HBP8 DSI_VHBPCR_HBP8_Msk #define DSI_VHBPCR_HBP9_Pos (9U) #define DSI_VHBPCR_HBP9_Msk (0x1U << DSI_VHBPCR_HBP9_Pos) /*!< 0x00000200 */ #define DSI_VHBPCR_HBP9 DSI_VHBPCR_HBP9_Msk #define DSI_VHBPCR_HBP10_Pos (10U) #define DSI_VHBPCR_HBP10_Msk (0x1U << DSI_VHBPCR_HBP10_Pos) /*!< 0x00000400 */ #define DSI_VHBPCR_HBP10 DSI_VHBPCR_HBP10_Msk #define DSI_VHBPCR_HBP11_Pos (11U) #define DSI_VHBPCR_HBP11_Msk (0x1U << DSI_VHBPCR_HBP11_Pos) /*!< 0x00000800 */ #define DSI_VHBPCR_HBP11 DSI_VHBPCR_HBP11_Msk /******************* Bit definition for DSI_VLCR register ***************/ #define DSI_VLCR_HLINE_Pos (0U) #define DSI_VLCR_HLINE_Msk (0x7FFFU << DSI_VLCR_HLINE_Pos) /*!< 0x00007FFF */ #define DSI_VLCR_HLINE DSI_VLCR_HLINE_Msk /*!< Horizontal Line duration */ #define DSI_VLCR_HLINE0_Pos (0U) #define DSI_VLCR_HLINE0_Msk (0x1U << DSI_VLCR_HLINE0_Pos) /*!< 0x00000001 */ #define DSI_VLCR_HLINE0 DSI_VLCR_HLINE0_Msk #define DSI_VLCR_HLINE1_Pos (1U) #define DSI_VLCR_HLINE1_Msk (0x1U << DSI_VLCR_HLINE1_Pos) /*!< 0x00000002 */ #define DSI_VLCR_HLINE1 DSI_VLCR_HLINE1_Msk #define DSI_VLCR_HLINE2_Pos (2U) #define DSI_VLCR_HLINE2_Msk (0x1U << DSI_VLCR_HLINE2_Pos) /*!< 0x00000004 */ #define DSI_VLCR_HLINE2 DSI_VLCR_HLINE2_Msk #define DSI_VLCR_HLINE3_Pos (3U) #define DSI_VLCR_HLINE3_Msk (0x1U << DSI_VLCR_HLINE3_Pos) /*!< 0x00000008 */ #define DSI_VLCR_HLINE3 DSI_VLCR_HLINE3_Msk #define DSI_VLCR_HLINE4_Pos (4U) #define DSI_VLCR_HLINE4_Msk (0x1U << DSI_VLCR_HLINE4_Pos) /*!< 0x00000010 */ #define DSI_VLCR_HLINE4 DSI_VLCR_HLINE4_Msk #define DSI_VLCR_HLINE5_Pos (5U) #define DSI_VLCR_HLINE5_Msk (0x1U << DSI_VLCR_HLINE5_Pos) /*!< 0x00000020 */ #define DSI_VLCR_HLINE5 DSI_VLCR_HLINE5_Msk #define DSI_VLCR_HLINE6_Pos (6U) #define DSI_VLCR_HLINE6_Msk (0x1U << DSI_VLCR_HLINE6_Pos) /*!< 0x00000040 */ #define DSI_VLCR_HLINE6 DSI_VLCR_HLINE6_Msk #define DSI_VLCR_HLINE7_Pos (7U) #define DSI_VLCR_HLINE7_Msk (0x1U << DSI_VLCR_HLINE7_Pos) /*!< 0x00000080 */ #define DSI_VLCR_HLINE7 DSI_VLCR_HLINE7_Msk #define DSI_VLCR_HLINE8_Pos (8U) #define DSI_VLCR_HLINE8_Msk (0x1U << DSI_VLCR_HLINE8_Pos) /*!< 0x00000100 */ #define DSI_VLCR_HLINE8 DSI_VLCR_HLINE8_Msk #define DSI_VLCR_HLINE9_Pos (9U) #define DSI_VLCR_HLINE9_Msk (0x1U << DSI_VLCR_HLINE9_Pos) /*!< 0x00000200 */ #define DSI_VLCR_HLINE9 DSI_VLCR_HLINE9_Msk #define DSI_VLCR_HLINE10_Pos (10U) #define DSI_VLCR_HLINE10_Msk (0x1U << DSI_VLCR_HLINE10_Pos) /*!< 0x00000400 */ #define DSI_VLCR_HLINE10 DSI_VLCR_HLINE10_Msk #define DSI_VLCR_HLINE11_Pos (11U) #define DSI_VLCR_HLINE11_Msk (0x1U << DSI_VLCR_HLINE11_Pos) /*!< 0x00000800 */ #define DSI_VLCR_HLINE11 DSI_VLCR_HLINE11_Msk #define DSI_VLCR_HLINE12_Pos (12U) #define DSI_VLCR_HLINE12_Msk (0x1U << DSI_VLCR_HLINE12_Pos) /*!< 0x00001000 */ #define DSI_VLCR_HLINE12 DSI_VLCR_HLINE12_Msk #define DSI_VLCR_HLINE13_Pos (13U) #define DSI_VLCR_HLINE13_Msk (0x1U << DSI_VLCR_HLINE13_Pos) /*!< 0x00002000 */ #define DSI_VLCR_HLINE13 DSI_VLCR_HLINE13_Msk #define DSI_VLCR_HLINE14_Pos (14U) #define DSI_VLCR_HLINE14_Msk (0x1U << DSI_VLCR_HLINE14_Pos) /*!< 0x00004000 */ #define DSI_VLCR_HLINE14 DSI_VLCR_HLINE14_Msk /******************* Bit definition for DSI_VVSACR register *************/ #define DSI_VVSACR_VSA_Pos (0U) #define DSI_VVSACR_VSA_Msk (0x3FFU << DSI_VVSACR_VSA_Pos) /*!< 0x000003FF */ #define DSI_VVSACR_VSA DSI_VVSACR_VSA_Msk /*!< Vertical Synchronism Active duration */ #define DSI_VVSACR_VSA0_Pos (0U) #define DSI_VVSACR_VSA0_Msk (0x1U << DSI_VVSACR_VSA0_Pos) /*!< 0x00000001 */ #define DSI_VVSACR_VSA0 DSI_VVSACR_VSA0_Msk #define DSI_VVSACR_VSA1_Pos (1U) #define DSI_VVSACR_VSA1_Msk (0x1U << DSI_VVSACR_VSA1_Pos) /*!< 0x00000002 */ #define DSI_VVSACR_VSA1 DSI_VVSACR_VSA1_Msk #define DSI_VVSACR_VSA2_Pos (2U) #define DSI_VVSACR_VSA2_Msk (0x1U << DSI_VVSACR_VSA2_Pos) /*!< 0x00000004 */ #define DSI_VVSACR_VSA2 DSI_VVSACR_VSA2_Msk #define DSI_VVSACR_VSA3_Pos (3U) #define DSI_VVSACR_VSA3_Msk (0x1U << DSI_VVSACR_VSA3_Pos) /*!< 0x00000008 */ #define DSI_VVSACR_VSA3 DSI_VVSACR_VSA3_Msk #define DSI_VVSACR_VSA4_Pos (4U) #define DSI_VVSACR_VSA4_Msk (0x1U << DSI_VVSACR_VSA4_Pos) /*!< 0x00000010 */ #define DSI_VVSACR_VSA4 DSI_VVSACR_VSA4_Msk #define DSI_VVSACR_VSA5_Pos (5U) #define DSI_VVSACR_VSA5_Msk (0x1U << DSI_VVSACR_VSA5_Pos) /*!< 0x00000020 */ #define DSI_VVSACR_VSA5 DSI_VVSACR_VSA5_Msk #define DSI_VVSACR_VSA6_Pos (6U) #define DSI_VVSACR_VSA6_Msk (0x1U << DSI_VVSACR_VSA6_Pos) /*!< 0x00000040 */ #define DSI_VVSACR_VSA6 DSI_VVSACR_VSA6_Msk #define DSI_VVSACR_VSA7_Pos (7U) #define DSI_VVSACR_VSA7_Msk (0x1U << DSI_VVSACR_VSA7_Pos) /*!< 0x00000080 */ #define DSI_VVSACR_VSA7 DSI_VVSACR_VSA7_Msk #define DSI_VVSACR_VSA8_Pos (8U) #define DSI_VVSACR_VSA8_Msk (0x1U << DSI_VVSACR_VSA8_Pos) /*!< 0x00000100 */ #define DSI_VVSACR_VSA8 DSI_VVSACR_VSA8_Msk #define DSI_VVSACR_VSA9_Pos (9U) #define DSI_VVSACR_VSA9_Msk (0x1U << DSI_VVSACR_VSA9_Pos) /*!< 0x00000200 */ #define DSI_VVSACR_VSA9 DSI_VVSACR_VSA9_Msk /******************* Bit definition for DSI_VVBPCR register *************/ #define DSI_VVBPCR_VBP_Pos (0U) #define DSI_VVBPCR_VBP_Msk (0x3FFU << DSI_VVBPCR_VBP_Pos) /*!< 0x000003FF */ #define DSI_VVBPCR_VBP DSI_VVBPCR_VBP_Msk /*!< Vertical Back-Porch duration */ #define DSI_VVBPCR_VBP0_Pos (0U) #define DSI_VVBPCR_VBP0_Msk (0x1U << DSI_VVBPCR_VBP0_Pos) /*!< 0x00000001 */ #define DSI_VVBPCR_VBP0 DSI_VVBPCR_VBP0_Msk #define DSI_VVBPCR_VBP1_Pos (1U) #define DSI_VVBPCR_VBP1_Msk (0x1U << DSI_VVBPCR_VBP1_Pos) /*!< 0x00000002 */ #define DSI_VVBPCR_VBP1 DSI_VVBPCR_VBP1_Msk #define DSI_VVBPCR_VBP2_Pos (2U) #define DSI_VVBPCR_VBP2_Msk (0x1U << DSI_VVBPCR_VBP2_Pos) /*!< 0x00000004 */ #define DSI_VVBPCR_VBP2 DSI_VVBPCR_VBP2_Msk #define DSI_VVBPCR_VBP3_Pos (3U) #define DSI_VVBPCR_VBP3_Msk (0x1U << DSI_VVBPCR_VBP3_Pos) /*!< 0x00000008 */ #define DSI_VVBPCR_VBP3 DSI_VVBPCR_VBP3_Msk #define DSI_VVBPCR_VBP4_Pos (4U) #define DSI_VVBPCR_VBP4_Msk (0x1U << DSI_VVBPCR_VBP4_Pos) /*!< 0x00000010 */ #define DSI_VVBPCR_VBP4 DSI_VVBPCR_VBP4_Msk #define DSI_VVBPCR_VBP5_Pos (5U) #define DSI_VVBPCR_VBP5_Msk (0x1U << DSI_VVBPCR_VBP5_Pos) /*!< 0x00000020 */ #define DSI_VVBPCR_VBP5 DSI_VVBPCR_VBP5_Msk #define DSI_VVBPCR_VBP6_Pos (6U) #define DSI_VVBPCR_VBP6_Msk (0x1U << DSI_VVBPCR_VBP6_Pos) /*!< 0x00000040 */ #define DSI_VVBPCR_VBP6 DSI_VVBPCR_VBP6_Msk #define DSI_VVBPCR_VBP7_Pos (7U) #define DSI_VVBPCR_VBP7_Msk (0x1U << DSI_VVBPCR_VBP7_Pos) /*!< 0x00000080 */ #define DSI_VVBPCR_VBP7 DSI_VVBPCR_VBP7_Msk #define DSI_VVBPCR_VBP8_Pos (8U) #define DSI_VVBPCR_VBP8_Msk (0x1U << DSI_VVBPCR_VBP8_Pos) /*!< 0x00000100 */ #define DSI_VVBPCR_VBP8 DSI_VVBPCR_VBP8_Msk #define DSI_VVBPCR_VBP9_Pos (9U) #define DSI_VVBPCR_VBP9_Msk (0x1U << DSI_VVBPCR_VBP9_Pos) /*!< 0x00000200 */ #define DSI_VVBPCR_VBP9 DSI_VVBPCR_VBP9_Msk /******************* Bit definition for DSI_VVFPCR register *************/ #define DSI_VVFPCR_VFP_Pos (0U) #define DSI_VVFPCR_VFP_Msk (0x3FFU << DSI_VVFPCR_VFP_Pos) /*!< 0x000003FF */ #define DSI_VVFPCR_VFP DSI_VVFPCR_VFP_Msk /*!< Vertical Front-Porch duration */ #define DSI_VVFPCR_VFP0_Pos (0U) #define DSI_VVFPCR_VFP0_Msk (0x1U << DSI_VVFPCR_VFP0_Pos) /*!< 0x00000001 */ #define DSI_VVFPCR_VFP0 DSI_VVFPCR_VFP0_Msk #define DSI_VVFPCR_VFP1_Pos (1U) #define DSI_VVFPCR_VFP1_Msk (0x1U << DSI_VVFPCR_VFP1_Pos) /*!< 0x00000002 */ #define DSI_VVFPCR_VFP1 DSI_VVFPCR_VFP1_Msk #define DSI_VVFPCR_VFP2_Pos (2U) #define DSI_VVFPCR_VFP2_Msk (0x1U << DSI_VVFPCR_VFP2_Pos) /*!< 0x00000004 */ #define DSI_VVFPCR_VFP2 DSI_VVFPCR_VFP2_Msk #define DSI_VVFPCR_VFP3_Pos (3U) #define DSI_VVFPCR_VFP3_Msk (0x1U << DSI_VVFPCR_VFP3_Pos) /*!< 0x00000008 */ #define DSI_VVFPCR_VFP3 DSI_VVFPCR_VFP3_Msk #define DSI_VVFPCR_VFP4_Pos (4U) #define DSI_VVFPCR_VFP4_Msk (0x1U << DSI_VVFPCR_VFP4_Pos) /*!< 0x00000010 */ #define DSI_VVFPCR_VFP4 DSI_VVFPCR_VFP4_Msk #define DSI_VVFPCR_VFP5_Pos (5U) #define DSI_VVFPCR_VFP5_Msk (0x1U << DSI_VVFPCR_VFP5_Pos) /*!< 0x00000020 */ #define DSI_VVFPCR_VFP5 DSI_VVFPCR_VFP5_Msk #define DSI_VVFPCR_VFP6_Pos (6U) #define DSI_VVFPCR_VFP6_Msk (0x1U << DSI_VVFPCR_VFP6_Pos) /*!< 0x00000040 */ #define DSI_VVFPCR_VFP6 DSI_VVFPCR_VFP6_Msk #define DSI_VVFPCR_VFP7_Pos (7U) #define DSI_VVFPCR_VFP7_Msk (0x1U << DSI_VVFPCR_VFP7_Pos) /*!< 0x00000080 */ #define DSI_VVFPCR_VFP7 DSI_VVFPCR_VFP7_Msk #define DSI_VVFPCR_VFP8_Pos (8U) #define DSI_VVFPCR_VFP8_Msk (0x1U << DSI_VVFPCR_VFP8_Pos) /*!< 0x00000100 */ #define DSI_VVFPCR_VFP8 DSI_VVFPCR_VFP8_Msk #define DSI_VVFPCR_VFP9_Pos (9U) #define DSI_VVFPCR_VFP9_Msk (0x1U << DSI_VVFPCR_VFP9_Pos) /*!< 0x00000200 */ #define DSI_VVFPCR_VFP9 DSI_VVFPCR_VFP9_Msk /******************* Bit definition for DSI_VVACR register **************/ #define DSI_VVACR_VA_Pos (0U) #define DSI_VVACR_VA_Msk (0x3FFFU << DSI_VVACR_VA_Pos) /*!< 0x00003FFF */ #define DSI_VVACR_VA DSI_VVACR_VA_Msk /*!< Vertical Active duration */ #define DSI_VVACR_VA0_Pos (0U) #define DSI_VVACR_VA0_Msk (0x1U << DSI_VVACR_VA0_Pos) /*!< 0x00000001 */ #define DSI_VVACR_VA0 DSI_VVACR_VA0_Msk #define DSI_VVACR_VA1_Pos (1U) #define DSI_VVACR_VA1_Msk (0x1U << DSI_VVACR_VA1_Pos) /*!< 0x00000002 */ #define DSI_VVACR_VA1 DSI_VVACR_VA1_Msk #define DSI_VVACR_VA2_Pos (2U) #define DSI_VVACR_VA2_Msk (0x1U << DSI_VVACR_VA2_Pos) /*!< 0x00000004 */ #define DSI_VVACR_VA2 DSI_VVACR_VA2_Msk #define DSI_VVACR_VA3_Pos (3U) #define DSI_VVACR_VA3_Msk (0x1U << DSI_VVACR_VA3_Pos) /*!< 0x00000008 */ #define DSI_VVACR_VA3 DSI_VVACR_VA3_Msk #define DSI_VVACR_VA4_Pos (4U) #define DSI_VVACR_VA4_Msk (0x1U << DSI_VVACR_VA4_Pos) /*!< 0x00000010 */ #define DSI_VVACR_VA4 DSI_VVACR_VA4_Msk #define DSI_VVACR_VA5_Pos (5U) #define DSI_VVACR_VA5_Msk (0x1U << DSI_VVACR_VA5_Pos) /*!< 0x00000020 */ #define DSI_VVACR_VA5 DSI_VVACR_VA5_Msk #define DSI_VVACR_VA6_Pos (6U) #define DSI_VVACR_VA6_Msk (0x1U << DSI_VVACR_VA6_Pos) /*!< 0x00000040 */ #define DSI_VVACR_VA6 DSI_VVACR_VA6_Msk #define DSI_VVACR_VA7_Pos (7U) #define DSI_VVACR_VA7_Msk (0x1U << DSI_VVACR_VA7_Pos) /*!< 0x00000080 */ #define DSI_VVACR_VA7 DSI_VVACR_VA7_Msk #define DSI_VVACR_VA8_Pos (8U) #define DSI_VVACR_VA8_Msk (0x1U << DSI_VVACR_VA8_Pos) /*!< 0x00000100 */ #define DSI_VVACR_VA8 DSI_VVACR_VA8_Msk #define DSI_VVACR_VA9_Pos (9U) #define DSI_VVACR_VA9_Msk (0x1U << DSI_VVACR_VA9_Pos) /*!< 0x00000200 */ #define DSI_VVACR_VA9 DSI_VVACR_VA9_Msk #define DSI_VVACR_VA10_Pos (10U) #define DSI_VVACR_VA10_Msk (0x1U << DSI_VVACR_VA10_Pos) /*!< 0x00000400 */ #define DSI_VVACR_VA10 DSI_VVACR_VA10_Msk #define DSI_VVACR_VA11_Pos (11U) #define DSI_VVACR_VA11_Msk (0x1U << DSI_VVACR_VA11_Pos) /*!< 0x00000800 */ #define DSI_VVACR_VA11 DSI_VVACR_VA11_Msk #define DSI_VVACR_VA12_Pos (12U) #define DSI_VVACR_VA12_Msk (0x1U << DSI_VVACR_VA12_Pos) /*!< 0x00001000 */ #define DSI_VVACR_VA12 DSI_VVACR_VA12_Msk #define DSI_VVACR_VA13_Pos (13U) #define DSI_VVACR_VA13_Msk (0x1U << DSI_VVACR_VA13_Pos) /*!< 0x00002000 */ #define DSI_VVACR_VA13 DSI_VVACR_VA13_Msk /******************* Bit definition for DSI_LCCR register ***************/ #define DSI_LCCR_CMDSIZE_Pos (0U) #define DSI_LCCR_CMDSIZE_Msk (0xFFFFU << DSI_LCCR_CMDSIZE_Pos) /*!< 0x0000FFFF */ #define DSI_LCCR_CMDSIZE DSI_LCCR_CMDSIZE_Msk /*!< Command Size */ #define DSI_LCCR_CMDSIZE0_Pos (0U) #define DSI_LCCR_CMDSIZE0_Msk (0x1U << DSI_LCCR_CMDSIZE0_Pos) /*!< 0x00000001 */ #define DSI_LCCR_CMDSIZE0 DSI_LCCR_CMDSIZE0_Msk #define DSI_LCCR_CMDSIZE1_Pos (1U) #define DSI_LCCR_CMDSIZE1_Msk (0x1U << DSI_LCCR_CMDSIZE1_Pos) /*!< 0x00000002 */ #define DSI_LCCR_CMDSIZE1 DSI_LCCR_CMDSIZE1_Msk #define DSI_LCCR_CMDSIZE2_Pos (2U) #define DSI_LCCR_CMDSIZE2_Msk (0x1U << DSI_LCCR_CMDSIZE2_Pos) /*!< 0x00000004 */ #define DSI_LCCR_CMDSIZE2 DSI_LCCR_CMDSIZE2_Msk #define DSI_LCCR_CMDSIZE3_Pos (3U) #define DSI_LCCR_CMDSIZE3_Msk (0x1U << DSI_LCCR_CMDSIZE3_Pos) /*!< 0x00000008 */ #define DSI_LCCR_CMDSIZE3 DSI_LCCR_CMDSIZE3_Msk #define DSI_LCCR_CMDSIZE4_Pos (4U) #define DSI_LCCR_CMDSIZE4_Msk (0x1U << DSI_LCCR_CMDSIZE4_Pos) /*!< 0x00000010 */ #define DSI_LCCR_CMDSIZE4 DSI_LCCR_CMDSIZE4_Msk #define DSI_LCCR_CMDSIZE5_Pos (5U) #define DSI_LCCR_CMDSIZE5_Msk (0x1U << DSI_LCCR_CMDSIZE5_Pos) /*!< 0x00000020 */ #define DSI_LCCR_CMDSIZE5 DSI_LCCR_CMDSIZE5_Msk #define DSI_LCCR_CMDSIZE6_Pos (6U) #define DSI_LCCR_CMDSIZE6_Msk (0x1U << DSI_LCCR_CMDSIZE6_Pos) /*!< 0x00000040 */ #define DSI_LCCR_CMDSIZE6 DSI_LCCR_CMDSIZE6_Msk #define DSI_LCCR_CMDSIZE7_Pos (7U) #define DSI_LCCR_CMDSIZE7_Msk (0x1U << DSI_LCCR_CMDSIZE7_Pos) /*!< 0x00000080 */ #define DSI_LCCR_CMDSIZE7 DSI_LCCR_CMDSIZE7_Msk #define DSI_LCCR_CMDSIZE8_Pos (8U) #define DSI_LCCR_CMDSIZE8_Msk (0x1U << DSI_LCCR_CMDSIZE8_Pos) /*!< 0x00000100 */ #define DSI_LCCR_CMDSIZE8 DSI_LCCR_CMDSIZE8_Msk #define DSI_LCCR_CMDSIZE9_Pos (9U) #define DSI_LCCR_CMDSIZE9_Msk (0x1U << DSI_LCCR_CMDSIZE9_Pos) /*!< 0x00000200 */ #define DSI_LCCR_CMDSIZE9 DSI_LCCR_CMDSIZE9_Msk #define DSI_LCCR_CMDSIZE10_Pos (10U) #define DSI_LCCR_CMDSIZE10_Msk (0x1U << DSI_LCCR_CMDSIZE10_Pos) /*!< 0x00000400 */ #define DSI_LCCR_CMDSIZE10 DSI_LCCR_CMDSIZE10_Msk #define DSI_LCCR_CMDSIZE11_Pos (11U) #define DSI_LCCR_CMDSIZE11_Msk (0x1U << DSI_LCCR_CMDSIZE11_Pos) /*!< 0x00000800 */ #define DSI_LCCR_CMDSIZE11 DSI_LCCR_CMDSIZE11_Msk #define DSI_LCCR_CMDSIZE12_Pos (12U) #define DSI_LCCR_CMDSIZE12_Msk (0x1U << DSI_LCCR_CMDSIZE12_Pos) /*!< 0x00001000 */ #define DSI_LCCR_CMDSIZE12 DSI_LCCR_CMDSIZE12_Msk #define DSI_LCCR_CMDSIZE13_Pos (13U) #define DSI_LCCR_CMDSIZE13_Msk (0x1U << DSI_LCCR_CMDSIZE13_Pos) /*!< 0x00002000 */ #define DSI_LCCR_CMDSIZE13 DSI_LCCR_CMDSIZE13_Msk #define DSI_LCCR_CMDSIZE14_Pos (14U) #define DSI_LCCR_CMDSIZE14_Msk (0x1U << DSI_LCCR_CMDSIZE14_Pos) /*!< 0x00004000 */ #define DSI_LCCR_CMDSIZE14 DSI_LCCR_CMDSIZE14_Msk #define DSI_LCCR_CMDSIZE15_Pos (15U) #define DSI_LCCR_CMDSIZE15_Msk (0x1U << DSI_LCCR_CMDSIZE15_Pos) /*!< 0x00008000 */ #define DSI_LCCR_CMDSIZE15 DSI_LCCR_CMDSIZE15_Msk /******************* Bit definition for DSI_CMCR register ***************/ #define DSI_CMCR_TEARE_Pos (0U) #define DSI_CMCR_TEARE_Msk (0x1U << DSI_CMCR_TEARE_Pos) /*!< 0x00000001 */ #define DSI_CMCR_TEARE DSI_CMCR_TEARE_Msk /*!< Tearing Effect Acknowledge Request Enable */ #define DSI_CMCR_ARE_Pos (1U) #define DSI_CMCR_ARE_Msk (0x1U << DSI_CMCR_ARE_Pos) /*!< 0x00000002 */ #define DSI_CMCR_ARE DSI_CMCR_ARE_Msk /*!< Acknowledge Request Enable */ #define DSI_CMCR_GSW0TX_Pos (8U) #define DSI_CMCR_GSW0TX_Msk (0x1U << DSI_CMCR_GSW0TX_Pos) /*!< 0x00000100 */ #define DSI_CMCR_GSW0TX DSI_CMCR_GSW0TX_Msk /*!< Generic Short Write Zero parameters Transmission */ #define DSI_CMCR_GSW1TX_Pos (9U) #define DSI_CMCR_GSW1TX_Msk (0x1U << DSI_CMCR_GSW1TX_Pos) /*!< 0x00000200 */ #define DSI_CMCR_GSW1TX DSI_CMCR_GSW1TX_Msk /*!< Generic Short Write One parameters Transmission */ #define DSI_CMCR_GSW2TX_Pos (10U) #define DSI_CMCR_GSW2TX_Msk (0x1U << DSI_CMCR_GSW2TX_Pos) /*!< 0x00000400 */ #define DSI_CMCR_GSW2TX DSI_CMCR_GSW2TX_Msk /*!< Generic Short Write Two parameters Transmission */ #define DSI_CMCR_GSR0TX_Pos (11U) #define DSI_CMCR_GSR0TX_Msk (0x1U << DSI_CMCR_GSR0TX_Pos) /*!< 0x00000800 */ #define DSI_CMCR_GSR0TX DSI_CMCR_GSR0TX_Msk /*!< Generic Short Read Zero parameters Transmission */ #define DSI_CMCR_GSR1TX_Pos (12U) #define DSI_CMCR_GSR1TX_Msk (0x1U << DSI_CMCR_GSR1TX_Pos) /*!< 0x00001000 */ #define DSI_CMCR_GSR1TX DSI_CMCR_GSR1TX_Msk /*!< Generic Short Read One parameters Transmission */ #define DSI_CMCR_GSR2TX_Pos (13U) #define DSI_CMCR_GSR2TX_Msk (0x1U << DSI_CMCR_GSR2TX_Pos) /*!< 0x00002000 */ #define DSI_CMCR_GSR2TX DSI_CMCR_GSR2TX_Msk /*!< Generic Short Read Two parameters Transmission */ #define DSI_CMCR_GLWTX_Pos (14U) #define DSI_CMCR_GLWTX_Msk (0x1U << DSI_CMCR_GLWTX_Pos) /*!< 0x00004000 */ #define DSI_CMCR_GLWTX DSI_CMCR_GLWTX_Msk /*!< Generic Long Write Transmission */ #define DSI_CMCR_DSW0TX_Pos (16U) #define DSI_CMCR_DSW0TX_Msk (0x1U << DSI_CMCR_DSW0TX_Pos) /*!< 0x00010000 */ #define DSI_CMCR_DSW0TX DSI_CMCR_DSW0TX_Msk /*!< DCS Short Write Zero parameter Transmission */ #define DSI_CMCR_DSW1TX_Pos (17U) #define DSI_CMCR_DSW1TX_Msk (0x1U << DSI_CMCR_DSW1TX_Pos) /*!< 0x00020000 */ #define DSI_CMCR_DSW1TX DSI_CMCR_DSW1TX_Msk /*!< DCS Short Read One parameter Transmission */ #define DSI_CMCR_DSR0TX_Pos (18U) #define DSI_CMCR_DSR0TX_Msk (0x1U << DSI_CMCR_DSR0TX_Pos) /*!< 0x00040000 */ #define DSI_CMCR_DSR0TX DSI_CMCR_DSR0TX_Msk /*!< DCS Short Read Zero parameter Transmission */ #define DSI_CMCR_DLWTX_Pos (19U) #define DSI_CMCR_DLWTX_Msk (0x1U << DSI_CMCR_DLWTX_Pos) /*!< 0x00080000 */ #define DSI_CMCR_DLWTX DSI_CMCR_DLWTX_Msk /*!< DCS Long Write Transmission */ #define DSI_CMCR_MRDPS_Pos (24U) #define DSI_CMCR_MRDPS_Msk (0x1U << DSI_CMCR_MRDPS_Pos) /*!< 0x01000000 */ #define DSI_CMCR_MRDPS DSI_CMCR_MRDPS_Msk /*!< Maximum Read Packet Size */ /******************* Bit definition for DSI_GHCR register ***************/ #define DSI_GHCR_DT_Pos (0U) #define DSI_GHCR_DT_Msk (0x3FU << DSI_GHCR_DT_Pos) /*!< 0x0000003F */ #define DSI_GHCR_DT DSI_GHCR_DT_Msk /*!< Type */ #define DSI_GHCR_DT0_Pos (0U) #define DSI_GHCR_DT0_Msk (0x1U << DSI_GHCR_DT0_Pos) /*!< 0x00000001 */ #define DSI_GHCR_DT0 DSI_GHCR_DT0_Msk #define DSI_GHCR_DT1_Pos (1U) #define DSI_GHCR_DT1_Msk (0x1U << DSI_GHCR_DT1_Pos) /*!< 0x00000002 */ #define DSI_GHCR_DT1 DSI_GHCR_DT1_Msk #define DSI_GHCR_DT2_Pos (2U) #define DSI_GHCR_DT2_Msk (0x1U << DSI_GHCR_DT2_Pos) /*!< 0x00000004 */ #define DSI_GHCR_DT2 DSI_GHCR_DT2_Msk #define DSI_GHCR_DT3_Pos (3U) #define DSI_GHCR_DT3_Msk (0x1U << DSI_GHCR_DT3_Pos) /*!< 0x00000008 */ #define DSI_GHCR_DT3 DSI_GHCR_DT3_Msk #define DSI_GHCR_DT4_Pos (4U) #define DSI_GHCR_DT4_Msk (0x1U << DSI_GHCR_DT4_Pos) /*!< 0x00000010 */ #define DSI_GHCR_DT4 DSI_GHCR_DT4_Msk #define DSI_GHCR_DT5_Pos (5U) #define DSI_GHCR_DT5_Msk (0x1U << DSI_GHCR_DT5_Pos) /*!< 0x00000020 */ #define DSI_GHCR_DT5 DSI_GHCR_DT5_Msk #define DSI_GHCR_VCID_Pos (6U) #define DSI_GHCR_VCID_Msk (0x3U << DSI_GHCR_VCID_Pos) /*!< 0x000000C0 */ #define DSI_GHCR_VCID DSI_GHCR_VCID_Msk /*!< Channel */ #define DSI_GHCR_VCID0_Pos (6U) #define DSI_GHCR_VCID0_Msk (0x1U << DSI_GHCR_VCID0_Pos) /*!< 0x00000040 */ #define DSI_GHCR_VCID0 DSI_GHCR_VCID0_Msk #define DSI_GHCR_VCID1_Pos (7U) #define DSI_GHCR_VCID1_Msk (0x1U << DSI_GHCR_VCID1_Pos) /*!< 0x00000080 */ #define DSI_GHCR_VCID1 DSI_GHCR_VCID1_Msk #define DSI_GHCR_WCLSB_Pos (8U) #define DSI_GHCR_WCLSB_Msk (0xFFU << DSI_GHCR_WCLSB_Pos) /*!< 0x0000FF00 */ #define DSI_GHCR_WCLSB DSI_GHCR_WCLSB_Msk /*!< WordCount LSB */ #define DSI_GHCR_WCLSB0_Pos (8U) #define DSI_GHCR_WCLSB0_Msk (0x1U << DSI_GHCR_WCLSB0_Pos) /*!< 0x00000100 */ #define DSI_GHCR_WCLSB0 DSI_GHCR_WCLSB0_Msk #define DSI_GHCR_WCLSB1_Pos (9U) #define DSI_GHCR_WCLSB1_Msk (0x1U << DSI_GHCR_WCLSB1_Pos) /*!< 0x00000200 */ #define DSI_GHCR_WCLSB1 DSI_GHCR_WCLSB1_Msk #define DSI_GHCR_WCLSB2_Pos (10U) #define DSI_GHCR_WCLSB2_Msk (0x1U << DSI_GHCR_WCLSB2_Pos) /*!< 0x00000400 */ #define DSI_GHCR_WCLSB2 DSI_GHCR_WCLSB2_Msk #define DSI_GHCR_WCLSB3_Pos (11U) #define DSI_GHCR_WCLSB3_Msk (0x1U << DSI_GHCR_WCLSB3_Pos) /*!< 0x00000800 */ #define DSI_GHCR_WCLSB3 DSI_GHCR_WCLSB3_Msk #define DSI_GHCR_WCLSB4_Pos (12U) #define DSI_GHCR_WCLSB4_Msk (0x1U << DSI_GHCR_WCLSB4_Pos) /*!< 0x00001000 */ #define DSI_GHCR_WCLSB4 DSI_GHCR_WCLSB4_Msk #define DSI_GHCR_WCLSB5_Pos (13U) #define DSI_GHCR_WCLSB5_Msk (0x1U << DSI_GHCR_WCLSB5_Pos) /*!< 0x00002000 */ #define DSI_GHCR_WCLSB5 DSI_GHCR_WCLSB5_Msk #define DSI_GHCR_WCLSB6_Pos (14U) #define DSI_GHCR_WCLSB6_Msk (0x1U << DSI_GHCR_WCLSB6_Pos) /*!< 0x00004000 */ #define DSI_GHCR_WCLSB6 DSI_GHCR_WCLSB6_Msk #define DSI_GHCR_WCLSB7_Pos (15U) #define DSI_GHCR_WCLSB7_Msk (0x1U << DSI_GHCR_WCLSB7_Pos) /*!< 0x00008000 */ #define DSI_GHCR_WCLSB7 DSI_GHCR_WCLSB7_Msk #define DSI_GHCR_WCMSB_Pos (16U) #define DSI_GHCR_WCMSB_Msk (0xFFU << DSI_GHCR_WCMSB_Pos) /*!< 0x00FF0000 */ #define DSI_GHCR_WCMSB DSI_GHCR_WCMSB_Msk /*!< WordCount MSB */ #define DSI_GHCR_WCMSB0_Pos (16U) #define DSI_GHCR_WCMSB0_Msk (0x1U << DSI_GHCR_WCMSB0_Pos) /*!< 0x00010000 */ #define DSI_GHCR_WCMSB0 DSI_GHCR_WCMSB0_Msk #define DSI_GHCR_WCMSB1_Pos (17U) #define DSI_GHCR_WCMSB1_Msk (0x1U << DSI_GHCR_WCMSB1_Pos) /*!< 0x00020000 */ #define DSI_GHCR_WCMSB1 DSI_GHCR_WCMSB1_Msk #define DSI_GHCR_WCMSB2_Pos (18U) #define DSI_GHCR_WCMSB2_Msk (0x1U << DSI_GHCR_WCMSB2_Pos) /*!< 0x00040000 */ #define DSI_GHCR_WCMSB2 DSI_GHCR_WCMSB2_Msk #define DSI_GHCR_WCMSB3_Pos (19U) #define DSI_GHCR_WCMSB3_Msk (0x1U << DSI_GHCR_WCMSB3_Pos) /*!< 0x00080000 */ #define DSI_GHCR_WCMSB3 DSI_GHCR_WCMSB3_Msk #define DSI_GHCR_WCMSB4_Pos (20U) #define DSI_GHCR_WCMSB4_Msk (0x1U << DSI_GHCR_WCMSB4_Pos) /*!< 0x00100000 */ #define DSI_GHCR_WCMSB4 DSI_GHCR_WCMSB4_Msk #define DSI_GHCR_WCMSB5_Pos (21U) #define DSI_GHCR_WCMSB5_Msk (0x1U << DSI_GHCR_WCMSB5_Pos) /*!< 0x00200000 */ #define DSI_GHCR_WCMSB5 DSI_GHCR_WCMSB5_Msk #define DSI_GHCR_WCMSB6_Pos (22U) #define DSI_GHCR_WCMSB6_Msk (0x1U << DSI_GHCR_WCMSB6_Pos) /*!< 0x00400000 */ #define DSI_GHCR_WCMSB6 DSI_GHCR_WCMSB6_Msk #define DSI_GHCR_WCMSB7_Pos (23U) #define DSI_GHCR_WCMSB7_Msk (0x1U << DSI_GHCR_WCMSB7_Pos) /*!< 0x00800000 */ #define DSI_GHCR_WCMSB7 DSI_GHCR_WCMSB7_Msk /******************* Bit definition for DSI_GPDR register ***************/ #define DSI_GPDR_DATA1_Pos (0U) #define DSI_GPDR_DATA1_Msk (0xFFU << DSI_GPDR_DATA1_Pos) /*!< 0x000000FF */ #define DSI_GPDR_DATA1 DSI_GPDR_DATA1_Msk /*!< Payload Byte 1 */ #define DSI_GPDR_DATA1_0 (0x01U << DSI_GPDR_DATA1_Pos) /*!< 0x00000001 */ #define DSI_GPDR_DATA1_1 (0x02U << DSI_GPDR_DATA1_Pos) /*!< 0x00000002 */ #define DSI_GPDR_DATA1_2 (0x04U << DSI_GPDR_DATA1_Pos) /*!< 0x00000004 */ #define DSI_GPDR_DATA1_3 (0x08U << DSI_GPDR_DATA1_Pos) /*!< 0x00000008 */ #define DSI_GPDR_DATA1_4 (0x10U << DSI_GPDR_DATA1_Pos) /*!< 0x00000010 */ #define DSI_GPDR_DATA1_5 (0x20U << DSI_GPDR_DATA1_Pos) /*!< 0x00000020 */ #define DSI_GPDR_DATA1_6 (0x40U << DSI_GPDR_DATA1_Pos) /*!< 0x00000040 */ #define DSI_GPDR_DATA1_7 (0x80U << DSI_GPDR_DATA1_Pos) /*!< 0x00000080 */ #define DSI_GPDR_DATA2_Pos (8U) #define DSI_GPDR_DATA2_Msk (0xFFU << DSI_GPDR_DATA2_Pos) /*!< 0x0000FF00 */ #define DSI_GPDR_DATA2 DSI_GPDR_DATA2_Msk /*!< Payload Byte 2 */ #define DSI_GPDR_DATA2_0 (0x01U << DSI_GPDR_DATA2_Pos) /*!< 0x00000100 */ #define DSI_GPDR_DATA2_1 (0x02U << DSI_GPDR_DATA2_Pos) /*!< 0x00000200 */ #define DSI_GPDR_DATA2_2 (0x04U << DSI_GPDR_DATA2_Pos) /*!< 0x00000400 */ #define DSI_GPDR_DATA2_3 (0x08U << DSI_GPDR_DATA2_Pos) /*!< 0x00000800 */ #define DSI_GPDR_DATA2_4 (0x10U << DSI_GPDR_DATA2_Pos) /*!< 0x00001000 */ #define DSI_GPDR_DATA2_5 (0x20U << DSI_GPDR_DATA2_Pos) /*!< 0x00002000 */ #define DSI_GPDR_DATA2_6 (0x40U << DSI_GPDR_DATA2_Pos) /*!< 0x00004000 */ #define DSI_GPDR_DATA2_7 (0x80U << DSI_GPDR_DATA2_Pos) /*!< 0x00008000 */ #define DSI_GPDR_DATA3_Pos (16U) #define DSI_GPDR_DATA3_Msk (0xFFU << DSI_GPDR_DATA3_Pos) /*!< 0x00FF0000 */ #define DSI_GPDR_DATA3 DSI_GPDR_DATA3_Msk /*!< Payload Byte 3 */ #define DSI_GPDR_DATA3_0 (0x01U << DSI_GPDR_DATA3_Pos) /*!< 0x00010000 */ #define DSI_GPDR_DATA3_1 (0x02U << DSI_GPDR_DATA3_Pos) /*!< 0x00020000 */ #define DSI_GPDR_DATA3_2 (0x04U << DSI_GPDR_DATA3_Pos) /*!< 0x00040000 */ #define DSI_GPDR_DATA3_3 (0x08U << DSI_GPDR_DATA3_Pos) /*!< 0x00080000 */ #define DSI_GPDR_DATA3_4 (0x10U << DSI_GPDR_DATA3_Pos) /*!< 0x00100000 */ #define DSI_GPDR_DATA3_5 (0x20U << DSI_GPDR_DATA3_Pos) /*!< 0x00200000 */ #define DSI_GPDR_DATA3_6 (0x40U << DSI_GPDR_DATA3_Pos) /*!< 0x00400000 */ #define DSI_GPDR_DATA3_7 (0x80U << DSI_GPDR_DATA3_Pos) /*!< 0x00800000 */ #define DSI_GPDR_DATA4_Pos (24U) #define DSI_GPDR_DATA4_Msk (0xFFU << DSI_GPDR_DATA4_Pos) /*!< 0xFF000000 */ #define DSI_GPDR_DATA4 DSI_GPDR_DATA4_Msk /*!< Payload Byte 4 */ #define DSI_GPDR_DATA4_0 (0x01U << DSI_GPDR_DATA4_Pos) /*!< 0x01000000 */ #define DSI_GPDR_DATA4_1 (0x02U << DSI_GPDR_DATA4_Pos) /*!< 0x02000000 */ #define DSI_GPDR_DATA4_2 (0x04U << DSI_GPDR_DATA4_Pos) /*!< 0x04000000 */ #define DSI_GPDR_DATA4_3 (0x08U << DSI_GPDR_DATA4_Pos) /*!< 0x08000000 */ #define DSI_GPDR_DATA4_4 (0x10U << DSI_GPDR_DATA4_Pos) /*!< 0x10000000 */ #define DSI_GPDR_DATA4_5 (0x20U << DSI_GPDR_DATA4_Pos) /*!< 0x20000000 */ #define DSI_GPDR_DATA4_6 (0x40U << DSI_GPDR_DATA4_Pos) /*!< 0x40000000 */ #define DSI_GPDR_DATA4_7 (0x80U << DSI_GPDR_DATA4_Pos) /*!< 0x80000000 */ /******************* Bit definition for DSI_GPSR register ***************/ #define DSI_GPSR_CMDFE_Pos (0U) #define DSI_GPSR_CMDFE_Msk (0x1U << DSI_GPSR_CMDFE_Pos) /*!< 0x00000001 */ #define DSI_GPSR_CMDFE DSI_GPSR_CMDFE_Msk /*!< Command FIFO Empty */ #define DSI_GPSR_CMDFF_Pos (1U) #define DSI_GPSR_CMDFF_Msk (0x1U << DSI_GPSR_CMDFF_Pos) /*!< 0x00000002 */ #define DSI_GPSR_CMDFF DSI_GPSR_CMDFF_Msk /*!< Command FIFO Full */ #define DSI_GPSR_PWRFE_Pos (2U) #define DSI_GPSR_PWRFE_Msk (0x1U << DSI_GPSR_PWRFE_Pos) /*!< 0x00000004 */ #define DSI_GPSR_PWRFE DSI_GPSR_PWRFE_Msk /*!< Payload Write FIFO Empty */ #define DSI_GPSR_PWRFF_Pos (3U) #define DSI_GPSR_PWRFF_Msk (0x1U << DSI_GPSR_PWRFF_Pos) /*!< 0x00000008 */ #define DSI_GPSR_PWRFF DSI_GPSR_PWRFF_Msk /*!< Payload Write FIFO Full */ #define DSI_GPSR_PRDFE_Pos (4U) #define DSI_GPSR_PRDFE_Msk (0x1U << DSI_GPSR_PRDFE_Pos) /*!< 0x00000010 */ #define DSI_GPSR_PRDFE DSI_GPSR_PRDFE_Msk /*!< Payload Read FIFO Empty */ #define DSI_GPSR_PRDFF_Pos (5U) #define DSI_GPSR_PRDFF_Msk (0x1U << DSI_GPSR_PRDFF_Pos) /*!< 0x00000020 */ #define DSI_GPSR_PRDFF DSI_GPSR_PRDFF_Msk /*!< Payload Read FIFO Full */ #define DSI_GPSR_RCB_Pos (6U) #define DSI_GPSR_RCB_Msk (0x1U << DSI_GPSR_RCB_Pos) /*!< 0x00000040 */ #define DSI_GPSR_RCB DSI_GPSR_RCB_Msk /*!< Read Command Busy */ /******************* Bit definition for DSI_TCCR0 register **************/ #define DSI_TCCR0_LPRX_TOCNT_Pos (0U) #define DSI_TCCR0_LPRX_TOCNT_Msk (0xFFFFU << DSI_TCCR0_LPRX_TOCNT_Pos) /*!< 0x0000FFFF */ #define DSI_TCCR0_LPRX_TOCNT DSI_TCCR0_LPRX_TOCNT_Msk /*!< Low-power Reception Timeout Counter */ #define DSI_TCCR0_LPRX_TOCNT0_Pos (0U) #define DSI_TCCR0_LPRX_TOCNT0_Msk (0x1U << DSI_TCCR0_LPRX_TOCNT0_Pos) /*!< 0x00000001 */ #define DSI_TCCR0_LPRX_TOCNT0 DSI_TCCR0_LPRX_TOCNT0_Msk #define DSI_TCCR0_LPRX_TOCNT1_Pos (1U) #define DSI_TCCR0_LPRX_TOCNT1_Msk (0x1U << DSI_TCCR0_LPRX_TOCNT1_Pos) /*!< 0x00000002 */ #define DSI_TCCR0_LPRX_TOCNT1 DSI_TCCR0_LPRX_TOCNT1_Msk #define DSI_TCCR0_LPRX_TOCNT2_Pos (2U) #define DSI_TCCR0_LPRX_TOCNT2_Msk (0x1U << DSI_TCCR0_LPRX_TOCNT2_Pos) /*!< 0x00000004 */ #define DSI_TCCR0_LPRX_TOCNT2 DSI_TCCR0_LPRX_TOCNT2_Msk #define DSI_TCCR0_LPRX_TOCNT3_Pos (3U) #define DSI_TCCR0_LPRX_TOCNT3_Msk (0x1U << DSI_TCCR0_LPRX_TOCNT3_Pos) /*!< 0x00000008 */ #define DSI_TCCR0_LPRX_TOCNT3 DSI_TCCR0_LPRX_TOCNT3_Msk #define DSI_TCCR0_LPRX_TOCNT4_Pos (4U) #define DSI_TCCR0_LPRX_TOCNT4_Msk (0x1U << DSI_TCCR0_LPRX_TOCNT4_Pos) /*!< 0x00000010 */ #define DSI_TCCR0_LPRX_TOCNT4 DSI_TCCR0_LPRX_TOCNT4_Msk #define DSI_TCCR0_LPRX_TOCNT5_Pos (5U) #define DSI_TCCR0_LPRX_TOCNT5_Msk (0x1U << DSI_TCCR0_LPRX_TOCNT5_Pos) /*!< 0x00000020 */ #define DSI_TCCR0_LPRX_TOCNT5 DSI_TCCR0_LPRX_TOCNT5_Msk #define DSI_TCCR0_LPRX_TOCNT6_Pos (6U) #define DSI_TCCR0_LPRX_TOCNT6_Msk (0x1U << DSI_TCCR0_LPRX_TOCNT6_Pos) /*!< 0x00000040 */ #define DSI_TCCR0_LPRX_TOCNT6 DSI_TCCR0_LPRX_TOCNT6_Msk #define DSI_TCCR0_LPRX_TOCNT7_Pos (7U) #define DSI_TCCR0_LPRX_TOCNT7_Msk (0x1U << DSI_TCCR0_LPRX_TOCNT7_Pos) /*!< 0x00000080 */ #define DSI_TCCR0_LPRX_TOCNT7 DSI_TCCR0_LPRX_TOCNT7_Msk #define DSI_TCCR0_LPRX_TOCNT8_Pos (8U) #define DSI_TCCR0_LPRX_TOCNT8_Msk (0x1U << DSI_TCCR0_LPRX_TOCNT8_Pos) /*!< 0x00000100 */ #define DSI_TCCR0_LPRX_TOCNT8 DSI_TCCR0_LPRX_TOCNT8_Msk #define DSI_TCCR0_LPRX_TOCNT9_Pos (9U) #define DSI_TCCR0_LPRX_TOCNT9_Msk (0x1U << DSI_TCCR0_LPRX_TOCNT9_Pos) /*!< 0x00000200 */ #define DSI_TCCR0_LPRX_TOCNT9 DSI_TCCR0_LPRX_TOCNT9_Msk #define DSI_TCCR0_LPRX_TOCNT10_Pos (10U) #define DSI_TCCR0_LPRX_TOCNT10_Msk (0x1U << DSI_TCCR0_LPRX_TOCNT10_Pos) /*!< 0x00000400 */ #define DSI_TCCR0_LPRX_TOCNT10 DSI_TCCR0_LPRX_TOCNT10_Msk #define DSI_TCCR0_LPRX_TOCNT11_Pos (11U) #define DSI_TCCR0_LPRX_TOCNT11_Msk (0x1U << DSI_TCCR0_LPRX_TOCNT11_Pos) /*!< 0x00000800 */ #define DSI_TCCR0_LPRX_TOCNT11 DSI_TCCR0_LPRX_TOCNT11_Msk #define DSI_TCCR0_LPRX_TOCNT12_Pos (12U) #define DSI_TCCR0_LPRX_TOCNT12_Msk (0x1U << DSI_TCCR0_LPRX_TOCNT12_Pos) /*!< 0x00001000 */ #define DSI_TCCR0_LPRX_TOCNT12 DSI_TCCR0_LPRX_TOCNT12_Msk #define DSI_TCCR0_LPRX_TOCNT13_Pos (13U) #define DSI_TCCR0_LPRX_TOCNT13_Msk (0x1U << DSI_TCCR0_LPRX_TOCNT13_Pos) /*!< 0x00002000 */ #define DSI_TCCR0_LPRX_TOCNT13 DSI_TCCR0_LPRX_TOCNT13_Msk #define DSI_TCCR0_LPRX_TOCNT14_Pos (14U) #define DSI_TCCR0_LPRX_TOCNT14_Msk (0x1U << DSI_TCCR0_LPRX_TOCNT14_Pos) /*!< 0x00004000 */ #define DSI_TCCR0_LPRX_TOCNT14 DSI_TCCR0_LPRX_TOCNT14_Msk #define DSI_TCCR0_LPRX_TOCNT15_Pos (15U) #define DSI_TCCR0_LPRX_TOCNT15_Msk (0x1U << DSI_TCCR0_LPRX_TOCNT15_Pos) /*!< 0x00008000 */ #define DSI_TCCR0_LPRX_TOCNT15 DSI_TCCR0_LPRX_TOCNT15_Msk #define DSI_TCCR0_HSTX_TOCNT_Pos (16U) #define DSI_TCCR0_HSTX_TOCNT_Msk (0xFFFFU << DSI_TCCR0_HSTX_TOCNT_Pos) /*!< 0xFFFF0000 */ #define DSI_TCCR0_HSTX_TOCNT DSI_TCCR0_HSTX_TOCNT_Msk /*!< High-Speed Transmission Timeout Counter */ #define DSI_TCCR0_HSTX_TOCNT0_Pos (16U) #define DSI_TCCR0_HSTX_TOCNT0_Msk (0x1U << DSI_TCCR0_HSTX_TOCNT0_Pos) /*!< 0x00010000 */ #define DSI_TCCR0_HSTX_TOCNT0 DSI_TCCR0_HSTX_TOCNT0_Msk #define DSI_TCCR0_HSTX_TOCNT1_Pos (17U) #define DSI_TCCR0_HSTX_TOCNT1_Msk (0x1U << DSI_TCCR0_HSTX_TOCNT1_Pos) /*!< 0x00020000 */ #define DSI_TCCR0_HSTX_TOCNT1 DSI_TCCR0_HSTX_TOCNT1_Msk #define DSI_TCCR0_HSTX_TOCNT2_Pos (18U) #define DSI_TCCR0_HSTX_TOCNT2_Msk (0x1U << DSI_TCCR0_HSTX_TOCNT2_Pos) /*!< 0x00040000 */ #define DSI_TCCR0_HSTX_TOCNT2 DSI_TCCR0_HSTX_TOCNT2_Msk #define DSI_TCCR0_HSTX_TOCNT3_Pos (19U) #define DSI_TCCR0_HSTX_TOCNT3_Msk (0x1U << DSI_TCCR0_HSTX_TOCNT3_Pos) /*!< 0x00080000 */ #define DSI_TCCR0_HSTX_TOCNT3 DSI_TCCR0_HSTX_TOCNT3_Msk #define DSI_TCCR0_HSTX_TOCNT4_Pos (20U) #define DSI_TCCR0_HSTX_TOCNT4_Msk (0x1U << DSI_TCCR0_HSTX_TOCNT4_Pos) /*!< 0x00100000 */ #define DSI_TCCR0_HSTX_TOCNT4 DSI_TCCR0_HSTX_TOCNT4_Msk #define DSI_TCCR0_HSTX_TOCNT5_Pos (21U) #define DSI_TCCR0_HSTX_TOCNT5_Msk (0x1U << DSI_TCCR0_HSTX_TOCNT5_Pos) /*!< 0x00200000 */ #define DSI_TCCR0_HSTX_TOCNT5 DSI_TCCR0_HSTX_TOCNT5_Msk #define DSI_TCCR0_HSTX_TOCNT6_Pos (22U) #define DSI_TCCR0_HSTX_TOCNT6_Msk (0x1U << DSI_TCCR0_HSTX_TOCNT6_Pos) /*!< 0x00400000 */ #define DSI_TCCR0_HSTX_TOCNT6 DSI_TCCR0_HSTX_TOCNT6_Msk #define DSI_TCCR0_HSTX_TOCNT7_Pos (23U) #define DSI_TCCR0_HSTX_TOCNT7_Msk (0x1U << DSI_TCCR0_HSTX_TOCNT7_Pos) /*!< 0x00800000 */ #define DSI_TCCR0_HSTX_TOCNT7 DSI_TCCR0_HSTX_TOCNT7_Msk #define DSI_TCCR0_HSTX_TOCNT8_Pos (24U) #define DSI_TCCR0_HSTX_TOCNT8_Msk (0x1U << DSI_TCCR0_HSTX_TOCNT8_Pos) /*!< 0x01000000 */ #define DSI_TCCR0_HSTX_TOCNT8 DSI_TCCR0_HSTX_TOCNT8_Msk #define DSI_TCCR0_HSTX_TOCNT9_Pos (25U) #define DSI_TCCR0_HSTX_TOCNT9_Msk (0x1U << DSI_TCCR0_HSTX_TOCNT9_Pos) /*!< 0x02000000 */ #define DSI_TCCR0_HSTX_TOCNT9 DSI_TCCR0_HSTX_TOCNT9_Msk #define DSI_TCCR0_HSTX_TOCNT10_Pos (26U) #define DSI_TCCR0_HSTX_TOCNT10_Msk (0x1U << DSI_TCCR0_HSTX_TOCNT10_Pos) /*!< 0x04000000 */ #define DSI_TCCR0_HSTX_TOCNT10 DSI_TCCR0_HSTX_TOCNT10_Msk #define DSI_TCCR0_HSTX_TOCNT11_Pos (27U) #define DSI_TCCR0_HSTX_TOCNT11_Msk (0x1U << DSI_TCCR0_HSTX_TOCNT11_Pos) /*!< 0x08000000 */ #define DSI_TCCR0_HSTX_TOCNT11 DSI_TCCR0_HSTX_TOCNT11_Msk #define DSI_TCCR0_HSTX_TOCNT12_Pos (28U) #define DSI_TCCR0_HSTX_TOCNT12_Msk (0x1U << DSI_TCCR0_HSTX_TOCNT12_Pos) /*!< 0x10000000 */ #define DSI_TCCR0_HSTX_TOCNT12 DSI_TCCR0_HSTX_TOCNT12_Msk #define DSI_TCCR0_HSTX_TOCNT13_Pos (29U) #define DSI_TCCR0_HSTX_TOCNT13_Msk (0x1U << DSI_TCCR0_HSTX_TOCNT13_Pos) /*!< 0x20000000 */ #define DSI_TCCR0_HSTX_TOCNT13 DSI_TCCR0_HSTX_TOCNT13_Msk #define DSI_TCCR0_HSTX_TOCNT14_Pos (30U) #define DSI_TCCR0_HSTX_TOCNT14_Msk (0x1U << DSI_TCCR0_HSTX_TOCNT14_Pos) /*!< 0x40000000 */ #define DSI_TCCR0_HSTX_TOCNT14 DSI_TCCR0_HSTX_TOCNT14_Msk #define DSI_TCCR0_HSTX_TOCNT15_Pos (31U) #define DSI_TCCR0_HSTX_TOCNT15_Msk (0x1U << DSI_TCCR0_HSTX_TOCNT15_Pos) /*!< 0x80000000 */ #define DSI_TCCR0_HSTX_TOCNT15 DSI_TCCR0_HSTX_TOCNT15_Msk /******************* Bit definition for DSI_TCCR1 register **************/ #define DSI_TCCR1_HSRD_TOCNT_Pos (0U) #define DSI_TCCR1_HSRD_TOCNT_Msk (0xFFFFU << DSI_TCCR1_HSRD_TOCNT_Pos) /*!< 0x0000FFFF */ #define DSI_TCCR1_HSRD_TOCNT DSI_TCCR1_HSRD_TOCNT_Msk /*!< High-Speed Read Timeout Counter */ #define DSI_TCCR1_HSRD_TOCNT0_Pos (0U) #define DSI_TCCR1_HSRD_TOCNT0_Msk (0x1U << DSI_TCCR1_HSRD_TOCNT0_Pos) /*!< 0x00000001 */ #define DSI_TCCR1_HSRD_TOCNT0 DSI_TCCR1_HSRD_TOCNT0_Msk #define DSI_TCCR1_HSRD_TOCNT1_Pos (1U) #define DSI_TCCR1_HSRD_TOCNT1_Msk (0x1U << DSI_TCCR1_HSRD_TOCNT1_Pos) /*!< 0x00000002 */ #define DSI_TCCR1_HSRD_TOCNT1 DSI_TCCR1_HSRD_TOCNT1_Msk #define DSI_TCCR1_HSRD_TOCNT2_Pos (2U) #define DSI_TCCR1_HSRD_TOCNT2_Msk (0x1U << DSI_TCCR1_HSRD_TOCNT2_Pos) /*!< 0x00000004 */ #define DSI_TCCR1_HSRD_TOCNT2 DSI_TCCR1_HSRD_TOCNT2_Msk #define DSI_TCCR1_HSRD_TOCNT3_Pos (3U) #define DSI_TCCR1_HSRD_TOCNT3_Msk (0x1U << DSI_TCCR1_HSRD_TOCNT3_Pos) /*!< 0x00000008 */ #define DSI_TCCR1_HSRD_TOCNT3 DSI_TCCR1_HSRD_TOCNT3_Msk #define DSI_TCCR1_HSRD_TOCNT4_Pos (4U) #define DSI_TCCR1_HSRD_TOCNT4_Msk (0x1U << DSI_TCCR1_HSRD_TOCNT4_Pos) /*!< 0x00000010 */ #define DSI_TCCR1_HSRD_TOCNT4 DSI_TCCR1_HSRD_TOCNT4_Msk #define DSI_TCCR1_HSRD_TOCNT5_Pos (5U) #define DSI_TCCR1_HSRD_TOCNT5_Msk (0x1U << DSI_TCCR1_HSRD_TOCNT5_Pos) /*!< 0x00000020 */ #define DSI_TCCR1_HSRD_TOCNT5 DSI_TCCR1_HSRD_TOCNT5_Msk #define DSI_TCCR1_HSRD_TOCNT6_Pos (6U) #define DSI_TCCR1_HSRD_TOCNT6_Msk (0x1U << DSI_TCCR1_HSRD_TOCNT6_Pos) /*!< 0x00000040 */ #define DSI_TCCR1_HSRD_TOCNT6 DSI_TCCR1_HSRD_TOCNT6_Msk #define DSI_TCCR1_HSRD_TOCNT7_Pos (7U) #define DSI_TCCR1_HSRD_TOCNT7_Msk (0x1U << DSI_TCCR1_HSRD_TOCNT7_Pos) /*!< 0x00000080 */ #define DSI_TCCR1_HSRD_TOCNT7 DSI_TCCR1_HSRD_TOCNT7_Msk #define DSI_TCCR1_HSRD_TOCNT8_Pos (8U) #define DSI_TCCR1_HSRD_TOCNT8_Msk (0x1U << DSI_TCCR1_HSRD_TOCNT8_Pos) /*!< 0x00000100 */ #define DSI_TCCR1_HSRD_TOCNT8 DSI_TCCR1_HSRD_TOCNT8_Msk #define DSI_TCCR1_HSRD_TOCNT9_Pos (9U) #define DSI_TCCR1_HSRD_TOCNT9_Msk (0x1U << DSI_TCCR1_HSRD_TOCNT9_Pos) /*!< 0x00000200 */ #define DSI_TCCR1_HSRD_TOCNT9 DSI_TCCR1_HSRD_TOCNT9_Msk #define DSI_TCCR1_HSRD_TOCNT10_Pos (10U) #define DSI_TCCR1_HSRD_TOCNT10_Msk (0x1U << DSI_TCCR1_HSRD_TOCNT10_Pos) /*!< 0x00000400 */ #define DSI_TCCR1_HSRD_TOCNT10 DSI_TCCR1_HSRD_TOCNT10_Msk #define DSI_TCCR1_HSRD_TOCNT11_Pos (11U) #define DSI_TCCR1_HSRD_TOCNT11_Msk (0x1U << DSI_TCCR1_HSRD_TOCNT11_Pos) /*!< 0x00000800 */ #define DSI_TCCR1_HSRD_TOCNT11 DSI_TCCR1_HSRD_TOCNT11_Msk #define DSI_TCCR1_HSRD_TOCNT12_Pos (12U) #define DSI_TCCR1_HSRD_TOCNT12_Msk (0x1U << DSI_TCCR1_HSRD_TOCNT12_Pos) /*!< 0x00001000 */ #define DSI_TCCR1_HSRD_TOCNT12 DSI_TCCR1_HSRD_TOCNT12_Msk #define DSI_TCCR1_HSRD_TOCNT13_Pos (13U) #define DSI_TCCR1_HSRD_TOCNT13_Msk (0x1U << DSI_TCCR1_HSRD_TOCNT13_Pos) /*!< 0x00002000 */ #define DSI_TCCR1_HSRD_TOCNT13 DSI_TCCR1_HSRD_TOCNT13_Msk #define DSI_TCCR1_HSRD_TOCNT14_Pos (14U) #define DSI_TCCR1_HSRD_TOCNT14_Msk (0x1U << DSI_TCCR1_HSRD_TOCNT14_Pos) /*!< 0x00004000 */ #define DSI_TCCR1_HSRD_TOCNT14 DSI_TCCR1_HSRD_TOCNT14_Msk #define DSI_TCCR1_HSRD_TOCNT15_Pos (15U) #define DSI_TCCR1_HSRD_TOCNT15_Msk (0x1U << DSI_TCCR1_HSRD_TOCNT15_Pos) /*!< 0x00008000 */ #define DSI_TCCR1_HSRD_TOCNT15 DSI_TCCR1_HSRD_TOCNT15_Msk /******************* Bit definition for DSI_TCCR2 register **************/ #define DSI_TCCR2_LPRD_TOCNT_Pos (0U) #define DSI_TCCR2_LPRD_TOCNT_Msk (0xFFFFU << DSI_TCCR2_LPRD_TOCNT_Pos) /*!< 0x0000FFFF */ #define DSI_TCCR2_LPRD_TOCNT DSI_TCCR2_LPRD_TOCNT_Msk /*!< Low-Power Read Timeout Counter */ #define DSI_TCCR2_LPRD_TOCNT0_Pos (0U) #define DSI_TCCR2_LPRD_TOCNT0_Msk (0x1U << DSI_TCCR2_LPRD_TOCNT0_Pos) /*!< 0x00000001 */ #define DSI_TCCR2_LPRD_TOCNT0 DSI_TCCR2_LPRD_TOCNT0_Msk #define DSI_TCCR2_LPRD_TOCNT1_Pos (1U) #define DSI_TCCR2_LPRD_TOCNT1_Msk (0x1U << DSI_TCCR2_LPRD_TOCNT1_Pos) /*!< 0x00000002 */ #define DSI_TCCR2_LPRD_TOCNT1 DSI_TCCR2_LPRD_TOCNT1_Msk #define DSI_TCCR2_LPRD_TOCNT2_Pos (2U) #define DSI_TCCR2_LPRD_TOCNT2_Msk (0x1U << DSI_TCCR2_LPRD_TOCNT2_Pos) /*!< 0x00000004 */ #define DSI_TCCR2_LPRD_TOCNT2 DSI_TCCR2_LPRD_TOCNT2_Msk #define DSI_TCCR2_LPRD_TOCNT3_Pos (3U) #define DSI_TCCR2_LPRD_TOCNT3_Msk (0x1U << DSI_TCCR2_LPRD_TOCNT3_Pos) /*!< 0x00000008 */ #define DSI_TCCR2_LPRD_TOCNT3 DSI_TCCR2_LPRD_TOCNT3_Msk #define DSI_TCCR2_LPRD_TOCNT4_Pos (4U) #define DSI_TCCR2_LPRD_TOCNT4_Msk (0x1U << DSI_TCCR2_LPRD_TOCNT4_Pos) /*!< 0x00000010 */ #define DSI_TCCR2_LPRD_TOCNT4 DSI_TCCR2_LPRD_TOCNT4_Msk #define DSI_TCCR2_LPRD_TOCNT5_Pos (5U) #define DSI_TCCR2_LPRD_TOCNT5_Msk (0x1U << DSI_TCCR2_LPRD_TOCNT5_Pos) /*!< 0x00000020 */ #define DSI_TCCR2_LPRD_TOCNT5 DSI_TCCR2_LPRD_TOCNT5_Msk #define DSI_TCCR2_LPRD_TOCNT6_Pos (6U) #define DSI_TCCR2_LPRD_TOCNT6_Msk (0x1U << DSI_TCCR2_LPRD_TOCNT6_Pos) /*!< 0x00000040 */ #define DSI_TCCR2_LPRD_TOCNT6 DSI_TCCR2_LPRD_TOCNT6_Msk #define DSI_TCCR2_LPRD_TOCNT7_Pos (7U) #define DSI_TCCR2_LPRD_TOCNT7_Msk (0x1U << DSI_TCCR2_LPRD_TOCNT7_Pos) /*!< 0x00000080 */ #define DSI_TCCR2_LPRD_TOCNT7 DSI_TCCR2_LPRD_TOCNT7_Msk #define DSI_TCCR2_LPRD_TOCNT8_Pos (8U) #define DSI_TCCR2_LPRD_TOCNT8_Msk (0x1U << DSI_TCCR2_LPRD_TOCNT8_Pos) /*!< 0x00000100 */ #define DSI_TCCR2_LPRD_TOCNT8 DSI_TCCR2_LPRD_TOCNT8_Msk #define DSI_TCCR2_LPRD_TOCNT9_Pos (9U) #define DSI_TCCR2_LPRD_TOCNT9_Msk (0x1U << DSI_TCCR2_LPRD_TOCNT9_Pos) /*!< 0x00000200 */ #define DSI_TCCR2_LPRD_TOCNT9 DSI_TCCR2_LPRD_TOCNT9_Msk #define DSI_TCCR2_LPRD_TOCNT10_Pos (10U) #define DSI_TCCR2_LPRD_TOCNT10_Msk (0x1U << DSI_TCCR2_LPRD_TOCNT10_Pos) /*!< 0x00000400 */ #define DSI_TCCR2_LPRD_TOCNT10 DSI_TCCR2_LPRD_TOCNT10_Msk #define DSI_TCCR2_LPRD_TOCNT11_Pos (11U) #define DSI_TCCR2_LPRD_TOCNT11_Msk (0x1U << DSI_TCCR2_LPRD_TOCNT11_Pos) /*!< 0x00000800 */ #define DSI_TCCR2_LPRD_TOCNT11 DSI_TCCR2_LPRD_TOCNT11_Msk #define DSI_TCCR2_LPRD_TOCNT12_Pos (12U) #define DSI_TCCR2_LPRD_TOCNT12_Msk (0x1U << DSI_TCCR2_LPRD_TOCNT12_Pos) /*!< 0x00001000 */ #define DSI_TCCR2_LPRD_TOCNT12 DSI_TCCR2_LPRD_TOCNT12_Msk #define DSI_TCCR2_LPRD_TOCNT13_Pos (13U) #define DSI_TCCR2_LPRD_TOCNT13_Msk (0x1U << DSI_TCCR2_LPRD_TOCNT13_Pos) /*!< 0x00002000 */ #define DSI_TCCR2_LPRD_TOCNT13 DSI_TCCR2_LPRD_TOCNT13_Msk #define DSI_TCCR2_LPRD_TOCNT14_Pos (14U) #define DSI_TCCR2_LPRD_TOCNT14_Msk (0x1U << DSI_TCCR2_LPRD_TOCNT14_Pos) /*!< 0x00004000 */ #define DSI_TCCR2_LPRD_TOCNT14 DSI_TCCR2_LPRD_TOCNT14_Msk #define DSI_TCCR2_LPRD_TOCNT15_Pos (15U) #define DSI_TCCR2_LPRD_TOCNT15_Msk (0x1U << DSI_TCCR2_LPRD_TOCNT15_Pos) /*!< 0x00008000 */ #define DSI_TCCR2_LPRD_TOCNT15 DSI_TCCR2_LPRD_TOCNT15_Msk /******************* Bit definition for DSI_TCCR3 register **************/ #define DSI_TCCR3_HSWR_TOCNT_Pos (0U) #define DSI_TCCR3_HSWR_TOCNT_Msk (0xFFFFU << DSI_TCCR3_HSWR_TOCNT_Pos) /*!< 0x0000FFFF */ #define DSI_TCCR3_HSWR_TOCNT DSI_TCCR3_HSWR_TOCNT_Msk /*!< High-Speed Write Timeout Counter */ #define DSI_TCCR3_HSWR_TOCNT0_Pos (0U) #define DSI_TCCR3_HSWR_TOCNT0_Msk (0x1U << DSI_TCCR3_HSWR_TOCNT0_Pos) /*!< 0x00000001 */ #define DSI_TCCR3_HSWR_TOCNT0 DSI_TCCR3_HSWR_TOCNT0_Msk #define DSI_TCCR3_HSWR_TOCNT1_Pos (1U) #define DSI_TCCR3_HSWR_TOCNT1_Msk (0x1U << DSI_TCCR3_HSWR_TOCNT1_Pos) /*!< 0x00000002 */ #define DSI_TCCR3_HSWR_TOCNT1 DSI_TCCR3_HSWR_TOCNT1_Msk #define DSI_TCCR3_HSWR_TOCNT2_Pos (2U) #define DSI_TCCR3_HSWR_TOCNT2_Msk (0x1U << DSI_TCCR3_HSWR_TOCNT2_Pos) /*!< 0x00000004 */ #define DSI_TCCR3_HSWR_TOCNT2 DSI_TCCR3_HSWR_TOCNT2_Msk #define DSI_TCCR3_HSWR_TOCNT3_Pos (3U) #define DSI_TCCR3_HSWR_TOCNT3_Msk (0x1U << DSI_TCCR3_HSWR_TOCNT3_Pos) /*!< 0x00000008 */ #define DSI_TCCR3_HSWR_TOCNT3 DSI_TCCR3_HSWR_TOCNT3_Msk #define DSI_TCCR3_HSWR_TOCNT4_Pos (4U) #define DSI_TCCR3_HSWR_TOCNT4_Msk (0x1U << DSI_TCCR3_HSWR_TOCNT4_Pos) /*!< 0x00000010 */ #define DSI_TCCR3_HSWR_TOCNT4 DSI_TCCR3_HSWR_TOCNT4_Msk #define DSI_TCCR3_HSWR_TOCNT5_Pos (5U) #define DSI_TCCR3_HSWR_TOCNT5_Msk (0x1U << DSI_TCCR3_HSWR_TOCNT5_Pos) /*!< 0x00000020 */ #define DSI_TCCR3_HSWR_TOCNT5 DSI_TCCR3_HSWR_TOCNT5_Msk #define DSI_TCCR3_HSWR_TOCNT6_Pos (6U) #define DSI_TCCR3_HSWR_TOCNT6_Msk (0x1U << DSI_TCCR3_HSWR_TOCNT6_Pos) /*!< 0x00000040 */ #define DSI_TCCR3_HSWR_TOCNT6 DSI_TCCR3_HSWR_TOCNT6_Msk #define DSI_TCCR3_HSWR_TOCNT7_Pos (7U) #define DSI_TCCR3_HSWR_TOCNT7_Msk (0x1U << DSI_TCCR3_HSWR_TOCNT7_Pos) /*!< 0x00000080 */ #define DSI_TCCR3_HSWR_TOCNT7 DSI_TCCR3_HSWR_TOCNT7_Msk #define DSI_TCCR3_HSWR_TOCNT8_Pos (8U) #define DSI_TCCR3_HSWR_TOCNT8_Msk (0x1U << DSI_TCCR3_HSWR_TOCNT8_Pos) /*!< 0x00000100 */ #define DSI_TCCR3_HSWR_TOCNT8 DSI_TCCR3_HSWR_TOCNT8_Msk #define DSI_TCCR3_HSWR_TOCNT9_Pos (9U) #define DSI_TCCR3_HSWR_TOCNT9_Msk (0x1U << DSI_TCCR3_HSWR_TOCNT9_Pos) /*!< 0x00000200 */ #define DSI_TCCR3_HSWR_TOCNT9 DSI_TCCR3_HSWR_TOCNT9_Msk #define DSI_TCCR3_HSWR_TOCNT10_Pos (10U) #define DSI_TCCR3_HSWR_TOCNT10_Msk (0x1U << DSI_TCCR3_HSWR_TOCNT10_Pos) /*!< 0x00000400 */ #define DSI_TCCR3_HSWR_TOCNT10 DSI_TCCR3_HSWR_TOCNT10_Msk #define DSI_TCCR3_HSWR_TOCNT11_Pos (11U) #define DSI_TCCR3_HSWR_TOCNT11_Msk (0x1U << DSI_TCCR3_HSWR_TOCNT11_Pos) /*!< 0x00000800 */ #define DSI_TCCR3_HSWR_TOCNT11 DSI_TCCR3_HSWR_TOCNT11_Msk #define DSI_TCCR3_HSWR_TOCNT12_Pos (12U) #define DSI_TCCR3_HSWR_TOCNT12_Msk (0x1U << DSI_TCCR3_HSWR_TOCNT12_Pos) /*!< 0x00001000 */ #define DSI_TCCR3_HSWR_TOCNT12 DSI_TCCR3_HSWR_TOCNT12_Msk #define DSI_TCCR3_HSWR_TOCNT13_Pos (13U) #define DSI_TCCR3_HSWR_TOCNT13_Msk (0x1U << DSI_TCCR3_HSWR_TOCNT13_Pos) /*!< 0x00002000 */ #define DSI_TCCR3_HSWR_TOCNT13 DSI_TCCR3_HSWR_TOCNT13_Msk #define DSI_TCCR3_HSWR_TOCNT14_Pos (14U) #define DSI_TCCR3_HSWR_TOCNT14_Msk (0x1U << DSI_TCCR3_HSWR_TOCNT14_Pos) /*!< 0x00004000 */ #define DSI_TCCR3_HSWR_TOCNT14 DSI_TCCR3_HSWR_TOCNT14_Msk #define DSI_TCCR3_HSWR_TOCNT15_Pos (15U) #define DSI_TCCR3_HSWR_TOCNT15_Msk (0x1U << DSI_TCCR3_HSWR_TOCNT15_Pos) /*!< 0x00008000 */ #define DSI_TCCR3_HSWR_TOCNT15 DSI_TCCR3_HSWR_TOCNT15_Msk #define DSI_TCCR3_PM_Pos (24U) #define DSI_TCCR3_PM_Msk (0x1U << DSI_TCCR3_PM_Pos) /*!< 0x01000000 */ #define DSI_TCCR3_PM DSI_TCCR3_PM_Msk /*!< Presp Mode */ /******************* Bit definition for DSI_TCCR4 register **************/ #define DSI_TCCR4_LPWR_TOCNT_Pos (0U) #define DSI_TCCR4_LPWR_TOCNT_Msk (0xFFFFU << DSI_TCCR4_LPWR_TOCNT_Pos) /*!< 0x0000FFFF */ #define DSI_TCCR4_LPWR_TOCNT DSI_TCCR4_LPWR_TOCNT_Msk /*!< Low-Power Write Timeout Counter */ #define DSI_TCCR4_LPWR_TOCNT0_Pos (0U) #define DSI_TCCR4_LPWR_TOCNT0_Msk (0x1U << DSI_TCCR4_LPWR_TOCNT0_Pos) /*!< 0x00000001 */ #define DSI_TCCR4_LPWR_TOCNT0 DSI_TCCR4_LPWR_TOCNT0_Msk #define DSI_TCCR4_LPWR_TOCNT1_Pos (1U) #define DSI_TCCR4_LPWR_TOCNT1_Msk (0x1U << DSI_TCCR4_LPWR_TOCNT1_Pos) /*!< 0x00000002 */ #define DSI_TCCR4_LPWR_TOCNT1 DSI_TCCR4_LPWR_TOCNT1_Msk #define DSI_TCCR4_LPWR_TOCNT2_Pos (2U) #define DSI_TCCR4_LPWR_TOCNT2_Msk (0x1U << DSI_TCCR4_LPWR_TOCNT2_Pos) /*!< 0x00000004 */ #define DSI_TCCR4_LPWR_TOCNT2 DSI_TCCR4_LPWR_TOCNT2_Msk #define DSI_TCCR4_LPWR_TOCNT3_Pos (3U) #define DSI_TCCR4_LPWR_TOCNT3_Msk (0x1U << DSI_TCCR4_LPWR_TOCNT3_Pos) /*!< 0x00000008 */ #define DSI_TCCR4_LPWR_TOCNT3 DSI_TCCR4_LPWR_TOCNT3_Msk #define DSI_TCCR4_LPWR_TOCNT4_Pos (4U) #define DSI_TCCR4_LPWR_TOCNT4_Msk (0x1U << DSI_TCCR4_LPWR_TOCNT4_Pos) /*!< 0x00000010 */ #define DSI_TCCR4_LPWR_TOCNT4 DSI_TCCR4_LPWR_TOCNT4_Msk #define DSI_TCCR4_LPWR_TOCNT5_Pos (5U) #define DSI_TCCR4_LPWR_TOCNT5_Msk (0x1U << DSI_TCCR4_LPWR_TOCNT5_Pos) /*!< 0x00000020 */ #define DSI_TCCR4_LPWR_TOCNT5 DSI_TCCR4_LPWR_TOCNT5_Msk #define DSI_TCCR4_LPWR_TOCNT6_Pos (6U) #define DSI_TCCR4_LPWR_TOCNT6_Msk (0x1U << DSI_TCCR4_LPWR_TOCNT6_Pos) /*!< 0x00000040 */ #define DSI_TCCR4_LPWR_TOCNT6 DSI_TCCR4_LPWR_TOCNT6_Msk #define DSI_TCCR4_LPWR_TOCNT7_Pos (7U) #define DSI_TCCR4_LPWR_TOCNT7_Msk (0x1U << DSI_TCCR4_LPWR_TOCNT7_Pos) /*!< 0x00000080 */ #define DSI_TCCR4_LPWR_TOCNT7 DSI_TCCR4_LPWR_TOCNT7_Msk #define DSI_TCCR4_LPWR_TOCNT8_Pos (8U) #define DSI_TCCR4_LPWR_TOCNT8_Msk (0x1U << DSI_TCCR4_LPWR_TOCNT8_Pos) /*!< 0x00000100 */ #define DSI_TCCR4_LPWR_TOCNT8 DSI_TCCR4_LPWR_TOCNT8_Msk #define DSI_TCCR4_LPWR_TOCNT9_Pos (9U) #define DSI_TCCR4_LPWR_TOCNT9_Msk (0x1U << DSI_TCCR4_LPWR_TOCNT9_Pos) /*!< 0x00000200 */ #define DSI_TCCR4_LPWR_TOCNT9 DSI_TCCR4_LPWR_TOCNT9_Msk #define DSI_TCCR4_LPWR_TOCNT10_Pos (10U) #define DSI_TCCR4_LPWR_TOCNT10_Msk (0x1U << DSI_TCCR4_LPWR_TOCNT10_Pos) /*!< 0x00000400 */ #define DSI_TCCR4_LPWR_TOCNT10 DSI_TCCR4_LPWR_TOCNT10_Msk #define DSI_TCCR4_LPWR_TOCNT11_Pos (11U) #define DSI_TCCR4_LPWR_TOCNT11_Msk (0x1U << DSI_TCCR4_LPWR_TOCNT11_Pos) /*!< 0x00000800 */ #define DSI_TCCR4_LPWR_TOCNT11 DSI_TCCR4_LPWR_TOCNT11_Msk #define DSI_TCCR4_LPWR_TOCNT12_Pos (12U) #define DSI_TCCR4_LPWR_TOCNT12_Msk (0x1U << DSI_TCCR4_LPWR_TOCNT12_Pos) /*!< 0x00001000 */ #define DSI_TCCR4_LPWR_TOCNT12 DSI_TCCR4_LPWR_TOCNT12_Msk #define DSI_TCCR4_LPWR_TOCNT13_Pos (13U) #define DSI_TCCR4_LPWR_TOCNT13_Msk (0x1U << DSI_TCCR4_LPWR_TOCNT13_Pos) /*!< 0x00002000 */ #define DSI_TCCR4_LPWR_TOCNT13 DSI_TCCR4_LPWR_TOCNT13_Msk #define DSI_TCCR4_LPWR_TOCNT14_Pos (14U) #define DSI_TCCR4_LPWR_TOCNT14_Msk (0x1U << DSI_TCCR4_LPWR_TOCNT14_Pos) /*!< 0x00004000 */ #define DSI_TCCR4_LPWR_TOCNT14 DSI_TCCR4_LPWR_TOCNT14_Msk #define DSI_TCCR4_LPWR_TOCNT15_Pos (15U) #define DSI_TCCR4_LPWR_TOCNT15_Msk (0x1U << DSI_TCCR4_LPWR_TOCNT15_Pos) /*!< 0x00008000 */ #define DSI_TCCR4_LPWR_TOCNT15 DSI_TCCR4_LPWR_TOCNT15_Msk /******************* Bit definition for DSI_TCCR5 register **************/ #define DSI_TCCR5_BTA_TOCNT_Pos (0U) #define DSI_TCCR5_BTA_TOCNT_Msk (0xFFFFU << DSI_TCCR5_BTA_TOCNT_Pos) /*!< 0x0000FFFF */ #define DSI_TCCR5_BTA_TOCNT DSI_TCCR5_BTA_TOCNT_Msk /*!< Bus-Turn-Around Timeout Counter */ #define DSI_TCCR5_BTA_TOCNT0_Pos (0U) #define DSI_TCCR5_BTA_TOCNT0_Msk (0x1U << DSI_TCCR5_BTA_TOCNT0_Pos) /*!< 0x00000001 */ #define DSI_TCCR5_BTA_TOCNT0 DSI_TCCR5_BTA_TOCNT0_Msk #define DSI_TCCR5_BTA_TOCNT1_Pos (1U) #define DSI_TCCR5_BTA_TOCNT1_Msk (0x1U << DSI_TCCR5_BTA_TOCNT1_Pos) /*!< 0x00000002 */ #define DSI_TCCR5_BTA_TOCNT1 DSI_TCCR5_BTA_TOCNT1_Msk #define DSI_TCCR5_BTA_TOCNT2_Pos (2U) #define DSI_TCCR5_BTA_TOCNT2_Msk (0x1U << DSI_TCCR5_BTA_TOCNT2_Pos) /*!< 0x00000004 */ #define DSI_TCCR5_BTA_TOCNT2 DSI_TCCR5_BTA_TOCNT2_Msk #define DSI_TCCR5_BTA_TOCNT3_Pos (3U) #define DSI_TCCR5_BTA_TOCNT3_Msk (0x1U << DSI_TCCR5_BTA_TOCNT3_Pos) /*!< 0x00000008 */ #define DSI_TCCR5_BTA_TOCNT3 DSI_TCCR5_BTA_TOCNT3_Msk #define DSI_TCCR5_BTA_TOCNT4_Pos (4U) #define DSI_TCCR5_BTA_TOCNT4_Msk (0x1U << DSI_TCCR5_BTA_TOCNT4_Pos) /*!< 0x00000010 */ #define DSI_TCCR5_BTA_TOCNT4 DSI_TCCR5_BTA_TOCNT4_Msk #define DSI_TCCR5_BTA_TOCNT5_Pos (5U) #define DSI_TCCR5_BTA_TOCNT5_Msk (0x1U << DSI_TCCR5_BTA_TOCNT5_Pos) /*!< 0x00000020 */ #define DSI_TCCR5_BTA_TOCNT5 DSI_TCCR5_BTA_TOCNT5_Msk #define DSI_TCCR5_BTA_TOCNT6_Pos (6U) #define DSI_TCCR5_BTA_TOCNT6_Msk (0x1U << DSI_TCCR5_BTA_TOCNT6_Pos) /*!< 0x00000040 */ #define DSI_TCCR5_BTA_TOCNT6 DSI_TCCR5_BTA_TOCNT6_Msk #define DSI_TCCR5_BTA_TOCNT7_Pos (7U) #define DSI_TCCR5_BTA_TOCNT7_Msk (0x1U << DSI_TCCR5_BTA_TOCNT7_Pos) /*!< 0x00000080 */ #define DSI_TCCR5_BTA_TOCNT7 DSI_TCCR5_BTA_TOCNT7_Msk #define DSI_TCCR5_BTA_TOCNT8_Pos (8U) #define DSI_TCCR5_BTA_TOCNT8_Msk (0x1U << DSI_TCCR5_BTA_TOCNT8_Pos) /*!< 0x00000100 */ #define DSI_TCCR5_BTA_TOCNT8 DSI_TCCR5_BTA_TOCNT8_Msk #define DSI_TCCR5_BTA_TOCNT9_Pos (9U) #define DSI_TCCR5_BTA_TOCNT9_Msk (0x1U << DSI_TCCR5_BTA_TOCNT9_Pos) /*!< 0x00000200 */ #define DSI_TCCR5_BTA_TOCNT9 DSI_TCCR5_BTA_TOCNT9_Msk #define DSI_TCCR5_BTA_TOCNT10_Pos (10U) #define DSI_TCCR5_BTA_TOCNT10_Msk (0x1U << DSI_TCCR5_BTA_TOCNT10_Pos) /*!< 0x00000400 */ #define DSI_TCCR5_BTA_TOCNT10 DSI_TCCR5_BTA_TOCNT10_Msk #define DSI_TCCR5_BTA_TOCNT11_Pos (11U) #define DSI_TCCR5_BTA_TOCNT11_Msk (0x1U << DSI_TCCR5_BTA_TOCNT11_Pos) /*!< 0x00000800 */ #define DSI_TCCR5_BTA_TOCNT11 DSI_TCCR5_BTA_TOCNT11_Msk #define DSI_TCCR5_BTA_TOCNT12_Pos (12U) #define DSI_TCCR5_BTA_TOCNT12_Msk (0x1U << DSI_TCCR5_BTA_TOCNT12_Pos) /*!< 0x00001000 */ #define DSI_TCCR5_BTA_TOCNT12 DSI_TCCR5_BTA_TOCNT12_Msk #define DSI_TCCR5_BTA_TOCNT13_Pos (13U) #define DSI_TCCR5_BTA_TOCNT13_Msk (0x1U << DSI_TCCR5_BTA_TOCNT13_Pos) /*!< 0x00002000 */ #define DSI_TCCR5_BTA_TOCNT13 DSI_TCCR5_BTA_TOCNT13_Msk #define DSI_TCCR5_BTA_TOCNT14_Pos (14U) #define DSI_TCCR5_BTA_TOCNT14_Msk (0x1U << DSI_TCCR5_BTA_TOCNT14_Pos) /*!< 0x00004000 */ #define DSI_TCCR5_BTA_TOCNT14 DSI_TCCR5_BTA_TOCNT14_Msk #define DSI_TCCR5_BTA_TOCNT15_Pos (15U) #define DSI_TCCR5_BTA_TOCNT15_Msk (0x1U << DSI_TCCR5_BTA_TOCNT15_Pos) /*!< 0x00008000 */ #define DSI_TCCR5_BTA_TOCNT15 DSI_TCCR5_BTA_TOCNT15_Msk /******************* Bit definition for DSI_TDCR register ***************/ #define DSI_TDCR_3DM 0x00000003U /*!< 3D Mode */ #define DSI_TDCR_3DM0 0x00000001U #define DSI_TDCR_3DM1 0x00000002U #define DSI_TDCR_3DF 0x0000000CU /*!< 3D Format */ #define DSI_TDCR_3DF0 0x00000004U #define DSI_TDCR_3DF1 0x00000008U #define DSI_TDCR_SVS_Pos (4U) #define DSI_TDCR_SVS_Msk (0x1U << DSI_TDCR_SVS_Pos) /*!< 0x00000010 */ #define DSI_TDCR_SVS DSI_TDCR_SVS_Msk /*!< Second VSYNC */ #define DSI_TDCR_RF_Pos (5U) #define DSI_TDCR_RF_Msk (0x1U << DSI_TDCR_RF_Pos) /*!< 0x00000020 */ #define DSI_TDCR_RF DSI_TDCR_RF_Msk /*!< Right First */ #define DSI_TDCR_S3DC_Pos (16U) #define DSI_TDCR_S3DC_Msk (0x1U << DSI_TDCR_S3DC_Pos) /*!< 0x00010000 */ #define DSI_TDCR_S3DC DSI_TDCR_S3DC_Msk /*!< Send 3D Control */ /******************* Bit definition for DSI_CLCR register ***************/ #define DSI_CLCR_DPCC_Pos (0U) #define DSI_CLCR_DPCC_Msk (0x1U << DSI_CLCR_DPCC_Pos) /*!< 0x00000001 */ #define DSI_CLCR_DPCC DSI_CLCR_DPCC_Msk /*!< D-PHY Clock Control */ #define DSI_CLCR_ACR_Pos (1U) #define DSI_CLCR_ACR_Msk (0x1U << DSI_CLCR_ACR_Pos) /*!< 0x00000002 */ #define DSI_CLCR_ACR DSI_CLCR_ACR_Msk /*!< Automatic Clocklane Control */ /******************* Bit definition for DSI_CLTCR register **************/ #define DSI_CLTCR_LP2HS_TIME_Pos (0U) #define DSI_CLTCR_LP2HS_TIME_Msk (0x3FFU << DSI_CLTCR_LP2HS_TIME_Pos) /*!< 0x000003FF */ #define DSI_CLTCR_LP2HS_TIME DSI_CLTCR_LP2HS_TIME_Msk /*!< Low-Power to High-Speed Time */ #define DSI_CLTCR_LP2HS_TIME0_Pos (0U) #define DSI_CLTCR_LP2HS_TIME0_Msk (0x1U << DSI_CLTCR_LP2HS_TIME0_Pos) /*!< 0x00000001 */ #define DSI_CLTCR_LP2HS_TIME0 DSI_CLTCR_LP2HS_TIME0_Msk #define DSI_CLTCR_LP2HS_TIME1_Pos (1U) #define DSI_CLTCR_LP2HS_TIME1_Msk (0x1U << DSI_CLTCR_LP2HS_TIME1_Pos) /*!< 0x00000002 */ #define DSI_CLTCR_LP2HS_TIME1 DSI_CLTCR_LP2HS_TIME1_Msk #define DSI_CLTCR_LP2HS_TIME2_Pos (2U) #define DSI_CLTCR_LP2HS_TIME2_Msk (0x1U << DSI_CLTCR_LP2HS_TIME2_Pos) /*!< 0x00000004 */ #define DSI_CLTCR_LP2HS_TIME2 DSI_CLTCR_LP2HS_TIME2_Msk #define DSI_CLTCR_LP2HS_TIME3_Pos (3U) #define DSI_CLTCR_LP2HS_TIME3_Msk (0x1U << DSI_CLTCR_LP2HS_TIME3_Pos) /*!< 0x00000008 */ #define DSI_CLTCR_LP2HS_TIME3 DSI_CLTCR_LP2HS_TIME3_Msk #define DSI_CLTCR_LP2HS_TIME4_Pos (4U) #define DSI_CLTCR_LP2HS_TIME4_Msk (0x1U << DSI_CLTCR_LP2HS_TIME4_Pos) /*!< 0x00000010 */ #define DSI_CLTCR_LP2HS_TIME4 DSI_CLTCR_LP2HS_TIME4_Msk #define DSI_CLTCR_LP2HS_TIME5_Pos (5U) #define DSI_CLTCR_LP2HS_TIME5_Msk (0x1U << DSI_CLTCR_LP2HS_TIME5_Pos) /*!< 0x00000020 */ #define DSI_CLTCR_LP2HS_TIME5 DSI_CLTCR_LP2HS_TIME5_Msk #define DSI_CLTCR_LP2HS_TIME6_Pos (6U) #define DSI_CLTCR_LP2HS_TIME6_Msk (0x1U << DSI_CLTCR_LP2HS_TIME6_Pos) /*!< 0x00000040 */ #define DSI_CLTCR_LP2HS_TIME6 DSI_CLTCR_LP2HS_TIME6_Msk #define DSI_CLTCR_LP2HS_TIME7_Pos (7U) #define DSI_CLTCR_LP2HS_TIME7_Msk (0x1U << DSI_CLTCR_LP2HS_TIME7_Pos) /*!< 0x00000080 */ #define DSI_CLTCR_LP2HS_TIME7 DSI_CLTCR_LP2HS_TIME7_Msk #define DSI_CLTCR_LP2HS_TIME8_Pos (8U) #define DSI_CLTCR_LP2HS_TIME8_Msk (0x1U << DSI_CLTCR_LP2HS_TIME8_Pos) /*!< 0x00000100 */ #define DSI_CLTCR_LP2HS_TIME8 DSI_CLTCR_LP2HS_TIME8_Msk #define DSI_CLTCR_LP2HS_TIME9_Pos (9U) #define DSI_CLTCR_LP2HS_TIME9_Msk (0x1U << DSI_CLTCR_LP2HS_TIME9_Pos) /*!< 0x00000200 */ #define DSI_CLTCR_LP2HS_TIME9 DSI_CLTCR_LP2HS_TIME9_Msk #define DSI_CLTCR_HS2LP_TIME_Pos (16U) #define DSI_CLTCR_HS2LP_TIME_Msk (0x3FFU << DSI_CLTCR_HS2LP_TIME_Pos) /*!< 0x03FF0000 */ #define DSI_CLTCR_HS2LP_TIME DSI_CLTCR_HS2LP_TIME_Msk /*!< High-Speed to Low-Power Time */ #define DSI_CLTCR_HS2LP_TIME0_Pos (16U) #define DSI_CLTCR_HS2LP_TIME0_Msk (0x1U << DSI_CLTCR_HS2LP_TIME0_Pos) /*!< 0x00010000 */ #define DSI_CLTCR_HS2LP_TIME0 DSI_CLTCR_HS2LP_TIME0_Msk #define DSI_CLTCR_HS2LP_TIME1_Pos (17U) #define DSI_CLTCR_HS2LP_TIME1_Msk (0x1U << DSI_CLTCR_HS2LP_TIME1_Pos) /*!< 0x00020000 */ #define DSI_CLTCR_HS2LP_TIME1 DSI_CLTCR_HS2LP_TIME1_Msk #define DSI_CLTCR_HS2LP_TIME2_Pos (18U) #define DSI_CLTCR_HS2LP_TIME2_Msk (0x1U << DSI_CLTCR_HS2LP_TIME2_Pos) /*!< 0x00040000 */ #define DSI_CLTCR_HS2LP_TIME2 DSI_CLTCR_HS2LP_TIME2_Msk #define DSI_CLTCR_HS2LP_TIME3_Pos (19U) #define DSI_CLTCR_HS2LP_TIME3_Msk (0x1U << DSI_CLTCR_HS2LP_TIME3_Pos) /*!< 0x00080000 */ #define DSI_CLTCR_HS2LP_TIME3 DSI_CLTCR_HS2LP_TIME3_Msk #define DSI_CLTCR_HS2LP_TIME4_Pos (20U) #define DSI_CLTCR_HS2LP_TIME4_Msk (0x1U << DSI_CLTCR_HS2LP_TIME4_Pos) /*!< 0x00100000 */ #define DSI_CLTCR_HS2LP_TIME4 DSI_CLTCR_HS2LP_TIME4_Msk #define DSI_CLTCR_HS2LP_TIME5_Pos (21U) #define DSI_CLTCR_HS2LP_TIME5_Msk (0x1U << DSI_CLTCR_HS2LP_TIME5_Pos) /*!< 0x00200000 */ #define DSI_CLTCR_HS2LP_TIME5 DSI_CLTCR_HS2LP_TIME5_Msk #define DSI_CLTCR_HS2LP_TIME6_Pos (22U) #define DSI_CLTCR_HS2LP_TIME6_Msk (0x1U << DSI_CLTCR_HS2LP_TIME6_Pos) /*!< 0x00400000 */ #define DSI_CLTCR_HS2LP_TIME6 DSI_CLTCR_HS2LP_TIME6_Msk #define DSI_CLTCR_HS2LP_TIME7_Pos (23U) #define DSI_CLTCR_HS2LP_TIME7_Msk (0x1U << DSI_CLTCR_HS2LP_TIME7_Pos) /*!< 0x00800000 */ #define DSI_CLTCR_HS2LP_TIME7 DSI_CLTCR_HS2LP_TIME7_Msk #define DSI_CLTCR_HS2LP_TIME8_Pos (24U) #define DSI_CLTCR_HS2LP_TIME8_Msk (0x1U << DSI_CLTCR_HS2LP_TIME8_Pos) /*!< 0x01000000 */ #define DSI_CLTCR_HS2LP_TIME8 DSI_CLTCR_HS2LP_TIME8_Msk #define DSI_CLTCR_HS2LP_TIME9_Pos (25U) #define DSI_CLTCR_HS2LP_TIME9_Msk (0x1U << DSI_CLTCR_HS2LP_TIME9_Pos) /*!< 0x02000000 */ #define DSI_CLTCR_HS2LP_TIME9 DSI_CLTCR_HS2LP_TIME9_Msk /******************* Bit definition for DSI_DLTCR register **************/ #define DSI_DLTCR_MRD_TIME_Pos (0U) #define DSI_DLTCR_MRD_TIME_Msk (0x7FFFU << DSI_DLTCR_MRD_TIME_Pos) /*!< 0x00007FFF */ #define DSI_DLTCR_MRD_TIME DSI_DLTCR_MRD_TIME_Msk /*!< Maximum Read Time */ #define DSI_DLTCR_MRD_TIME0_Pos (0U) #define DSI_DLTCR_MRD_TIME0_Msk (0x1U << DSI_DLTCR_MRD_TIME0_Pos) /*!< 0x00000001 */ #define DSI_DLTCR_MRD_TIME0 DSI_DLTCR_MRD_TIME0_Msk #define DSI_DLTCR_MRD_TIME1_Pos (1U) #define DSI_DLTCR_MRD_TIME1_Msk (0x1U << DSI_DLTCR_MRD_TIME1_Pos) /*!< 0x00000002 */ #define DSI_DLTCR_MRD_TIME1 DSI_DLTCR_MRD_TIME1_Msk #define DSI_DLTCR_MRD_TIME2_Pos (2U) #define DSI_DLTCR_MRD_TIME2_Msk (0x1U << DSI_DLTCR_MRD_TIME2_Pos) /*!< 0x00000004 */ #define DSI_DLTCR_MRD_TIME2 DSI_DLTCR_MRD_TIME2_Msk #define DSI_DLTCR_MRD_TIME3_Pos (3U) #define DSI_DLTCR_MRD_TIME3_Msk (0x1U << DSI_DLTCR_MRD_TIME3_Pos) /*!< 0x00000008 */ #define DSI_DLTCR_MRD_TIME3 DSI_DLTCR_MRD_TIME3_Msk #define DSI_DLTCR_MRD_TIME4_Pos (4U) #define DSI_DLTCR_MRD_TIME4_Msk (0x1U << DSI_DLTCR_MRD_TIME4_Pos) /*!< 0x00000010 */ #define DSI_DLTCR_MRD_TIME4 DSI_DLTCR_MRD_TIME4_Msk #define DSI_DLTCR_MRD_TIME5_Pos (5U) #define DSI_DLTCR_MRD_TIME5_Msk (0x1U << DSI_DLTCR_MRD_TIME5_Pos) /*!< 0x00000020 */ #define DSI_DLTCR_MRD_TIME5 DSI_DLTCR_MRD_TIME5_Msk #define DSI_DLTCR_MRD_TIME6_Pos (6U) #define DSI_DLTCR_MRD_TIME6_Msk (0x1U << DSI_DLTCR_MRD_TIME6_Pos) /*!< 0x00000040 */ #define DSI_DLTCR_MRD_TIME6 DSI_DLTCR_MRD_TIME6_Msk #define DSI_DLTCR_MRD_TIME7_Pos (7U) #define DSI_DLTCR_MRD_TIME7_Msk (0x1U << DSI_DLTCR_MRD_TIME7_Pos) /*!< 0x00000080 */ #define DSI_DLTCR_MRD_TIME7 DSI_DLTCR_MRD_TIME7_Msk #define DSI_DLTCR_MRD_TIME8_Pos (8U) #define DSI_DLTCR_MRD_TIME8_Msk (0x1U << DSI_DLTCR_MRD_TIME8_Pos) /*!< 0x00000100 */ #define DSI_DLTCR_MRD_TIME8 DSI_DLTCR_MRD_TIME8_Msk #define DSI_DLTCR_MRD_TIME9_Pos (9U) #define DSI_DLTCR_MRD_TIME9_Msk (0x1U << DSI_DLTCR_MRD_TIME9_Pos) /*!< 0x00000200 */ #define DSI_DLTCR_MRD_TIME9 DSI_DLTCR_MRD_TIME9_Msk #define DSI_DLTCR_MRD_TIME10_Pos (10U) #define DSI_DLTCR_MRD_TIME10_Msk (0x1U << DSI_DLTCR_MRD_TIME10_Pos) /*!< 0x00000400 */ #define DSI_DLTCR_MRD_TIME10 DSI_DLTCR_MRD_TIME10_Msk #define DSI_DLTCR_MRD_TIME11_Pos (11U) #define DSI_DLTCR_MRD_TIME11_Msk (0x1U << DSI_DLTCR_MRD_TIME11_Pos) /*!< 0x00000800 */ #define DSI_DLTCR_MRD_TIME11 DSI_DLTCR_MRD_TIME11_Msk #define DSI_DLTCR_MRD_TIME12_Pos (12U) #define DSI_DLTCR_MRD_TIME12_Msk (0x1U << DSI_DLTCR_MRD_TIME12_Pos) /*!< 0x00001000 */ #define DSI_DLTCR_MRD_TIME12 DSI_DLTCR_MRD_TIME12_Msk #define DSI_DLTCR_MRD_TIME13_Pos (13U) #define DSI_DLTCR_MRD_TIME13_Msk (0x1U << DSI_DLTCR_MRD_TIME13_Pos) /*!< 0x00002000 */ #define DSI_DLTCR_MRD_TIME13 DSI_DLTCR_MRD_TIME13_Msk #define DSI_DLTCR_MRD_TIME14_Pos (14U) #define DSI_DLTCR_MRD_TIME14_Msk (0x1U << DSI_DLTCR_MRD_TIME14_Pos) /*!< 0x00004000 */ #define DSI_DLTCR_MRD_TIME14 DSI_DLTCR_MRD_TIME14_Msk #define DSI_DLTCR_LP2HS_TIME_Pos (16U) #define DSI_DLTCR_LP2HS_TIME_Msk (0xFFU << DSI_DLTCR_LP2HS_TIME_Pos) /*!< 0x00FF0000 */ #define DSI_DLTCR_LP2HS_TIME DSI_DLTCR_LP2HS_TIME_Msk /*!< Low-Power To High-Speed Time */ #define DSI_DLTCR_LP2HS_TIME0_Pos (16U) #define DSI_DLTCR_LP2HS_TIME0_Msk (0x1U << DSI_DLTCR_LP2HS_TIME0_Pos) /*!< 0x00010000 */ #define DSI_DLTCR_LP2HS_TIME0 DSI_DLTCR_LP2HS_TIME0_Msk #define DSI_DLTCR_LP2HS_TIME1_Pos (17U) #define DSI_DLTCR_LP2HS_TIME1_Msk (0x1U << DSI_DLTCR_LP2HS_TIME1_Pos) /*!< 0x00020000 */ #define DSI_DLTCR_LP2HS_TIME1 DSI_DLTCR_LP2HS_TIME1_Msk #define DSI_DLTCR_LP2HS_TIME2_Pos (18U) #define DSI_DLTCR_LP2HS_TIME2_Msk (0x1U << DSI_DLTCR_LP2HS_TIME2_Pos) /*!< 0x00040000 */ #define DSI_DLTCR_LP2HS_TIME2 DSI_DLTCR_LP2HS_TIME2_Msk #define DSI_DLTCR_LP2HS_TIME3_Pos (19U) #define DSI_DLTCR_LP2HS_TIME3_Msk (0x1U << DSI_DLTCR_LP2HS_TIME3_Pos) /*!< 0x00080000 */ #define DSI_DLTCR_LP2HS_TIME3 DSI_DLTCR_LP2HS_TIME3_Msk #define DSI_DLTCR_LP2HS_TIME4_Pos (20U) #define DSI_DLTCR_LP2HS_TIME4_Msk (0x1U << DSI_DLTCR_LP2HS_TIME4_Pos) /*!< 0x00100000 */ #define DSI_DLTCR_LP2HS_TIME4 DSI_DLTCR_LP2HS_TIME4_Msk #define DSI_DLTCR_LP2HS_TIME5_Pos (21U) #define DSI_DLTCR_LP2HS_TIME5_Msk (0x1U << DSI_DLTCR_LP2HS_TIME5_Pos) /*!< 0x00200000 */ #define DSI_DLTCR_LP2HS_TIME5 DSI_DLTCR_LP2HS_TIME5_Msk #define DSI_DLTCR_LP2HS_TIME6_Pos (22U) #define DSI_DLTCR_LP2HS_TIME6_Msk (0x1U << DSI_DLTCR_LP2HS_TIME6_Pos) /*!< 0x00400000 */ #define DSI_DLTCR_LP2HS_TIME6 DSI_DLTCR_LP2HS_TIME6_Msk #define DSI_DLTCR_LP2HS_TIME7_Pos (23U) #define DSI_DLTCR_LP2HS_TIME7_Msk (0x1U << DSI_DLTCR_LP2HS_TIME7_Pos) /*!< 0x00800000 */ #define DSI_DLTCR_LP2HS_TIME7 DSI_DLTCR_LP2HS_TIME7_Msk #define DSI_DLTCR_HS2LP_TIME_Pos (24U) #define DSI_DLTCR_HS2LP_TIME_Msk (0xFFU << DSI_DLTCR_HS2LP_TIME_Pos) /*!< 0xFF000000 */ #define DSI_DLTCR_HS2LP_TIME DSI_DLTCR_HS2LP_TIME_Msk /*!< High-Speed To Low-Power Time */ #define DSI_DLTCR_HS2LP_TIME0_Pos (24U) #define DSI_DLTCR_HS2LP_TIME0_Msk (0x1U << DSI_DLTCR_HS2LP_TIME0_Pos) /*!< 0x01000000 */ #define DSI_DLTCR_HS2LP_TIME0 DSI_DLTCR_HS2LP_TIME0_Msk #define DSI_DLTCR_HS2LP_TIME1_Pos (25U) #define DSI_DLTCR_HS2LP_TIME1_Msk (0x1U << DSI_DLTCR_HS2LP_TIME1_Pos) /*!< 0x02000000 */ #define DSI_DLTCR_HS2LP_TIME1 DSI_DLTCR_HS2LP_TIME1_Msk #define DSI_DLTCR_HS2LP_TIME2_Pos (26U) #define DSI_DLTCR_HS2LP_TIME2_Msk (0x1U << DSI_DLTCR_HS2LP_TIME2_Pos) /*!< 0x04000000 */ #define DSI_DLTCR_HS2LP_TIME2 DSI_DLTCR_HS2LP_TIME2_Msk #define DSI_DLTCR_HS2LP_TIME3_Pos (27U) #define DSI_DLTCR_HS2LP_TIME3_Msk (0x1U << DSI_DLTCR_HS2LP_TIME3_Pos) /*!< 0x08000000 */ #define DSI_DLTCR_HS2LP_TIME3 DSI_DLTCR_HS2LP_TIME3_Msk #define DSI_DLTCR_HS2LP_TIME4_Pos (28U) #define DSI_DLTCR_HS2LP_TIME4_Msk (0x1U << DSI_DLTCR_HS2LP_TIME4_Pos) /*!< 0x10000000 */ #define DSI_DLTCR_HS2LP_TIME4 DSI_DLTCR_HS2LP_TIME4_Msk #define DSI_DLTCR_HS2LP_TIME5_Pos (29U) #define DSI_DLTCR_HS2LP_TIME5_Msk (0x1U << DSI_DLTCR_HS2LP_TIME5_Pos) /*!< 0x20000000 */ #define DSI_DLTCR_HS2LP_TIME5 DSI_DLTCR_HS2LP_TIME5_Msk #define DSI_DLTCR_HS2LP_TIME6_Pos (30U) #define DSI_DLTCR_HS2LP_TIME6_Msk (0x1U << DSI_DLTCR_HS2LP_TIME6_Pos) /*!< 0x40000000 */ #define DSI_DLTCR_HS2LP_TIME6 DSI_DLTCR_HS2LP_TIME6_Msk #define DSI_DLTCR_HS2LP_TIME7_Pos (31U) #define DSI_DLTCR_HS2LP_TIME7_Msk (0x1U << DSI_DLTCR_HS2LP_TIME7_Pos) /*!< 0x80000000 */ #define DSI_DLTCR_HS2LP_TIME7 DSI_DLTCR_HS2LP_TIME7_Msk /******************* Bit definition for DSI_PCTLR register **************/ #define DSI_PCTLR_DEN_Pos (1U) #define DSI_PCTLR_DEN_Msk (0x1U << DSI_PCTLR_DEN_Pos) /*!< 0x00000002 */ #define DSI_PCTLR_DEN DSI_PCTLR_DEN_Msk /*!< Digital Enable */ #define DSI_PCTLR_CKE_Pos (2U) #define DSI_PCTLR_CKE_Msk (0x1U << DSI_PCTLR_CKE_Pos) /*!< 0x00000004 */ #define DSI_PCTLR_CKE DSI_PCTLR_CKE_Msk /*!< Clock Enable */ /******************* Bit definition for DSI_PCONFR register *************/ #define DSI_PCONFR_NL_Pos (0U) #define DSI_PCONFR_NL_Msk (0x3U << DSI_PCONFR_NL_Pos) /*!< 0x00000003 */ #define DSI_PCONFR_NL DSI_PCONFR_NL_Msk /*!< Number of Lanes */ #define DSI_PCONFR_NL0_Pos (0U) #define DSI_PCONFR_NL0_Msk (0x1U << DSI_PCONFR_NL0_Pos) /*!< 0x00000001 */ #define DSI_PCONFR_NL0 DSI_PCONFR_NL0_Msk #define DSI_PCONFR_NL1_Pos (1U) #define DSI_PCONFR_NL1_Msk (0x1U << DSI_PCONFR_NL1_Pos) /*!< 0x00000002 */ #define DSI_PCONFR_NL1 DSI_PCONFR_NL1_Msk #define DSI_PCONFR_SW_TIME_Pos (8U) #define DSI_PCONFR_SW_TIME_Msk (0xFFU << DSI_PCONFR_SW_TIME_Pos) /*!< 0x0000FF00 */ #define DSI_PCONFR_SW_TIME DSI_PCONFR_SW_TIME_Msk /*!< Stop Wait Time */ #define DSI_PCONFR_SW_TIME0_Pos (8U) #define DSI_PCONFR_SW_TIME0_Msk (0x1U << DSI_PCONFR_SW_TIME0_Pos) /*!< 0x00000100 */ #define DSI_PCONFR_SW_TIME0 DSI_PCONFR_SW_TIME0_Msk #define DSI_PCONFR_SW_TIME1_Pos (9U) #define DSI_PCONFR_SW_TIME1_Msk (0x1U << DSI_PCONFR_SW_TIME1_Pos) /*!< 0x00000200 */ #define DSI_PCONFR_SW_TIME1 DSI_PCONFR_SW_TIME1_Msk #define DSI_PCONFR_SW_TIME2_Pos (10U) #define DSI_PCONFR_SW_TIME2_Msk (0x1U << DSI_PCONFR_SW_TIME2_Pos) /*!< 0x00000400 */ #define DSI_PCONFR_SW_TIME2 DSI_PCONFR_SW_TIME2_Msk #define DSI_PCONFR_SW_TIME3_Pos (11U) #define DSI_PCONFR_SW_TIME3_Msk (0x1U << DSI_PCONFR_SW_TIME3_Pos) /*!< 0x00000800 */ #define DSI_PCONFR_SW_TIME3 DSI_PCONFR_SW_TIME3_Msk #define DSI_PCONFR_SW_TIME4_Pos (12U) #define DSI_PCONFR_SW_TIME4_Msk (0x1U << DSI_PCONFR_SW_TIME4_Pos) /*!< 0x00001000 */ #define DSI_PCONFR_SW_TIME4 DSI_PCONFR_SW_TIME4_Msk #define DSI_PCONFR_SW_TIME5_Pos (13U) #define DSI_PCONFR_SW_TIME5_Msk (0x1U << DSI_PCONFR_SW_TIME5_Pos) /*!< 0x00002000 */ #define DSI_PCONFR_SW_TIME5 DSI_PCONFR_SW_TIME5_Msk #define DSI_PCONFR_SW_TIME6_Pos (14U) #define DSI_PCONFR_SW_TIME6_Msk (0x1U << DSI_PCONFR_SW_TIME6_Pos) /*!< 0x00004000 */ #define DSI_PCONFR_SW_TIME6 DSI_PCONFR_SW_TIME6_Msk #define DSI_PCONFR_SW_TIME7_Pos (15U) #define DSI_PCONFR_SW_TIME7_Msk (0x1U << DSI_PCONFR_SW_TIME7_Pos) /*!< 0x00008000 */ #define DSI_PCONFR_SW_TIME7 DSI_PCONFR_SW_TIME7_Msk /******************* Bit definition for DSI_PUCR register ***************/ #define DSI_PUCR_URCL_Pos (0U) #define DSI_PUCR_URCL_Msk (0x1U << DSI_PUCR_URCL_Pos) /*!< 0x00000001 */ #define DSI_PUCR_URCL DSI_PUCR_URCL_Msk /*!< ULPS Request on Clock Lane */ #define DSI_PUCR_UECL_Pos (1U) #define DSI_PUCR_UECL_Msk (0x1U << DSI_PUCR_UECL_Pos) /*!< 0x00000002 */ #define DSI_PUCR_UECL DSI_PUCR_UECL_Msk /*!< ULPS Exit on Clock Lane */ #define DSI_PUCR_URDL_Pos (2U) #define DSI_PUCR_URDL_Msk (0x1U << DSI_PUCR_URDL_Pos) /*!< 0x00000004 */ #define DSI_PUCR_URDL DSI_PUCR_URDL_Msk /*!< ULPS Request on Data Lane */ #define DSI_PUCR_UEDL_Pos (3U) #define DSI_PUCR_UEDL_Msk (0x1U << DSI_PUCR_UEDL_Pos) /*!< 0x00000008 */ #define DSI_PUCR_UEDL DSI_PUCR_UEDL_Msk /*!< ULPS Exit on Data Lane */ /******************* Bit definition for DSI_PTTCR register **************/ #define DSI_PTTCR_TX_TRIG_Pos (0U) #define DSI_PTTCR_TX_TRIG_Msk (0xFU << DSI_PTTCR_TX_TRIG_Pos) /*!< 0x0000000F */ #define DSI_PTTCR_TX_TRIG DSI_PTTCR_TX_TRIG_Msk /*!< Transmission Trigger */ #define DSI_PTTCR_TX_TRIG0_Pos (0U) #define DSI_PTTCR_TX_TRIG0_Msk (0x1U << DSI_PTTCR_TX_TRIG0_Pos) /*!< 0x00000001 */ #define DSI_PTTCR_TX_TRIG0 DSI_PTTCR_TX_TRIG0_Msk #define DSI_PTTCR_TX_TRIG1_Pos (1U) #define DSI_PTTCR_TX_TRIG1_Msk (0x1U << DSI_PTTCR_TX_TRIG1_Pos) /*!< 0x00000002 */ #define DSI_PTTCR_TX_TRIG1 DSI_PTTCR_TX_TRIG1_Msk #define DSI_PTTCR_TX_TRIG2_Pos (2U) #define DSI_PTTCR_TX_TRIG2_Msk (0x1U << DSI_PTTCR_TX_TRIG2_Pos) /*!< 0x00000004 */ #define DSI_PTTCR_TX_TRIG2 DSI_PTTCR_TX_TRIG2_Msk #define DSI_PTTCR_TX_TRIG3_Pos (3U) #define DSI_PTTCR_TX_TRIG3_Msk (0x1U << DSI_PTTCR_TX_TRIG3_Pos) /*!< 0x00000008 */ #define DSI_PTTCR_TX_TRIG3 DSI_PTTCR_TX_TRIG3_Msk /******************* Bit definition for DSI_PSR register ****************/ #define DSI_PSR_PD_Pos (1U) #define DSI_PSR_PD_Msk (0x1U << DSI_PSR_PD_Pos) /*!< 0x00000002 */ #define DSI_PSR_PD DSI_PSR_PD_Msk /*!< PHY Direction */ #define DSI_PSR_PSSC_Pos (2U) #define DSI_PSR_PSSC_Msk (0x1U << DSI_PSR_PSSC_Pos) /*!< 0x00000004 */ #define DSI_PSR_PSSC DSI_PSR_PSSC_Msk /*!< PHY Stop State Clock lane */ #define DSI_PSR_UANC_Pos (3U) #define DSI_PSR_UANC_Msk (0x1U << DSI_PSR_UANC_Pos) /*!< 0x00000008 */ #define DSI_PSR_UANC DSI_PSR_UANC_Msk /*!< ULPS Active Not Clock lane */ #define DSI_PSR_PSS0_Pos (4U) #define DSI_PSR_PSS0_Msk (0x1U << DSI_PSR_PSS0_Pos) /*!< 0x00000010 */ #define DSI_PSR_PSS0 DSI_PSR_PSS0_Msk /*!< PHY Stop State lane 0 */ #define DSI_PSR_UAN0_Pos (5U) #define DSI_PSR_UAN0_Msk (0x1U << DSI_PSR_UAN0_Pos) /*!< 0x00000020 */ #define DSI_PSR_UAN0 DSI_PSR_UAN0_Msk /*!< ULPS Active Not lane 0 */ #define DSI_PSR_RUE0_Pos (6U) #define DSI_PSR_RUE0_Msk (0x1U << DSI_PSR_RUE0_Pos) /*!< 0x00000040 */ #define DSI_PSR_RUE0 DSI_PSR_RUE0_Msk /*!< RX ULPS Escape lane 0 */ #define DSI_PSR_PSS1_Pos (7U) #define DSI_PSR_PSS1_Msk (0x1U << DSI_PSR_PSS1_Pos) /*!< 0x00000080 */ #define DSI_PSR_PSS1 DSI_PSR_PSS1_Msk /*!< PHY Stop State lane 1 */ #define DSI_PSR_UAN1_Pos (8U) #define DSI_PSR_UAN1_Msk (0x1U << DSI_PSR_UAN1_Pos) /*!< 0x00000100 */ #define DSI_PSR_UAN1 DSI_PSR_UAN1_Msk /*!< ULPS Active Not lane 1 */ /******************* Bit definition for DSI_ISR0 register ***************/ #define DSI_ISR0_AE0_Pos (0U) #define DSI_ISR0_AE0_Msk (0x1U << DSI_ISR0_AE0_Pos) /*!< 0x00000001 */ #define DSI_ISR0_AE0 DSI_ISR0_AE0_Msk /*!< Acknowledge Error 0 */ #define DSI_ISR0_AE1_Pos (1U) #define DSI_ISR0_AE1_Msk (0x1U << DSI_ISR0_AE1_Pos) /*!< 0x00000002 */ #define DSI_ISR0_AE1 DSI_ISR0_AE1_Msk /*!< Acknowledge Error 1 */ #define DSI_ISR0_AE2_Pos (2U) #define DSI_ISR0_AE2_Msk (0x1U << DSI_ISR0_AE2_Pos) /*!< 0x00000004 */ #define DSI_ISR0_AE2 DSI_ISR0_AE2_Msk /*!< Acknowledge Error 2 */ #define DSI_ISR0_AE3_Pos (3U) #define DSI_ISR0_AE3_Msk (0x1U << DSI_ISR0_AE3_Pos) /*!< 0x00000008 */ #define DSI_ISR0_AE3 DSI_ISR0_AE3_Msk /*!< Acknowledge Error 3 */ #define DSI_ISR0_AE4_Pos (4U) #define DSI_ISR0_AE4_Msk (0x1U << DSI_ISR0_AE4_Pos) /*!< 0x00000010 */ #define DSI_ISR0_AE4 DSI_ISR0_AE4_Msk /*!< Acknowledge Error 4 */ #define DSI_ISR0_AE5_Pos (5U) #define DSI_ISR0_AE5_Msk (0x1U << DSI_ISR0_AE5_Pos) /*!< 0x00000020 */ #define DSI_ISR0_AE5 DSI_ISR0_AE5_Msk /*!< Acknowledge Error 5 */ #define DSI_ISR0_AE6_Pos (6U) #define DSI_ISR0_AE6_Msk (0x1U << DSI_ISR0_AE6_Pos) /*!< 0x00000040 */ #define DSI_ISR0_AE6 DSI_ISR0_AE6_Msk /*!< Acknowledge Error 6 */ #define DSI_ISR0_AE7_Pos (7U) #define DSI_ISR0_AE7_Msk (0x1U << DSI_ISR0_AE7_Pos) /*!< 0x00000080 */ #define DSI_ISR0_AE7 DSI_ISR0_AE7_Msk /*!< Acknowledge Error 7 */ #define DSI_ISR0_AE8_Pos (8U) #define DSI_ISR0_AE8_Msk (0x1U << DSI_ISR0_AE8_Pos) /*!< 0x00000100 */ #define DSI_ISR0_AE8 DSI_ISR0_AE8_Msk /*!< Acknowledge Error 8 */ #define DSI_ISR0_AE9_Pos (9U) #define DSI_ISR0_AE9_Msk (0x1U << DSI_ISR0_AE9_Pos) /*!< 0x00000200 */ #define DSI_ISR0_AE9 DSI_ISR0_AE9_Msk /*!< Acknowledge Error 9 */ #define DSI_ISR0_AE10_Pos (10U) #define DSI_ISR0_AE10_Msk (0x1U << DSI_ISR0_AE10_Pos) /*!< 0x00000400 */ #define DSI_ISR0_AE10 DSI_ISR0_AE10_Msk /*!< Acknowledge Error 10 */ #define DSI_ISR0_AE11_Pos (11U) #define DSI_ISR0_AE11_Msk (0x1U << DSI_ISR0_AE11_Pos) /*!< 0x00000800 */ #define DSI_ISR0_AE11 DSI_ISR0_AE11_Msk /*!< Acknowledge Error 11 */ #define DSI_ISR0_AE12_Pos (12U) #define DSI_ISR0_AE12_Msk (0x1U << DSI_ISR0_AE12_Pos) /*!< 0x00001000 */ #define DSI_ISR0_AE12 DSI_ISR0_AE12_Msk /*!< Acknowledge Error 12 */ #define DSI_ISR0_AE13_Pos (13U) #define DSI_ISR0_AE13_Msk (0x1U << DSI_ISR0_AE13_Pos) /*!< 0x00002000 */ #define DSI_ISR0_AE13 DSI_ISR0_AE13_Msk /*!< Acknowledge Error 13 */ #define DSI_ISR0_AE14_Pos (14U) #define DSI_ISR0_AE14_Msk (0x1U << DSI_ISR0_AE14_Pos) /*!< 0x00004000 */ #define DSI_ISR0_AE14 DSI_ISR0_AE14_Msk /*!< Acknowledge Error 14 */ #define DSI_ISR0_AE15_Pos (15U) #define DSI_ISR0_AE15_Msk (0x1U << DSI_ISR0_AE15_Pos) /*!< 0x00008000 */ #define DSI_ISR0_AE15 DSI_ISR0_AE15_Msk /*!< Acknowledge Error 15 */ #define DSI_ISR0_PE0_Pos (16U) #define DSI_ISR0_PE0_Msk (0x1U << DSI_ISR0_PE0_Pos) /*!< 0x00010000 */ #define DSI_ISR0_PE0 DSI_ISR0_PE0_Msk /*!< PHY Error 0 */ #define DSI_ISR0_PE1_Pos (17U) #define DSI_ISR0_PE1_Msk (0x1U << DSI_ISR0_PE1_Pos) /*!< 0x00020000 */ #define DSI_ISR0_PE1 DSI_ISR0_PE1_Msk /*!< PHY Error 1 */ #define DSI_ISR0_PE2_Pos (18U) #define DSI_ISR0_PE2_Msk (0x1U << DSI_ISR0_PE2_Pos) /*!< 0x00040000 */ #define DSI_ISR0_PE2 DSI_ISR0_PE2_Msk /*!< PHY Error 2 */ #define DSI_ISR0_PE3_Pos (19U) #define DSI_ISR0_PE3_Msk (0x1U << DSI_ISR0_PE3_Pos) /*!< 0x00080000 */ #define DSI_ISR0_PE3 DSI_ISR0_PE3_Msk /*!< PHY Error 3 */ #define DSI_ISR0_PE4_Pos (20U) #define DSI_ISR0_PE4_Msk (0x1U << DSI_ISR0_PE4_Pos) /*!< 0x00100000 */ #define DSI_ISR0_PE4 DSI_ISR0_PE4_Msk /*!< PHY Error 4 */ /******************* Bit definition for DSI_ISR1 register ***************/ #define DSI_ISR1_TOHSTX_Pos (0U) #define DSI_ISR1_TOHSTX_Msk (0x1U << DSI_ISR1_TOHSTX_Pos) /*!< 0x00000001 */ #define DSI_ISR1_TOHSTX DSI_ISR1_TOHSTX_Msk /*!< Timeout High-Speed Transmission */ #define DSI_ISR1_TOLPRX_Pos (1U) #define DSI_ISR1_TOLPRX_Msk (0x1U << DSI_ISR1_TOLPRX_Pos) /*!< 0x00000002 */ #define DSI_ISR1_TOLPRX DSI_ISR1_TOLPRX_Msk /*!< Timeout Low-Power Reception */ #define DSI_ISR1_ECCSE_Pos (2U) #define DSI_ISR1_ECCSE_Msk (0x1U << DSI_ISR1_ECCSE_Pos) /*!< 0x00000004 */ #define DSI_ISR1_ECCSE DSI_ISR1_ECCSE_Msk /*!< ECC Single-bit Error */ #define DSI_ISR1_ECCME_Pos (3U) #define DSI_ISR1_ECCME_Msk (0x1U << DSI_ISR1_ECCME_Pos) /*!< 0x00000008 */ #define DSI_ISR1_ECCME DSI_ISR1_ECCME_Msk /*!< ECC Multi-bit Error */ #define DSI_ISR1_CRCE_Pos (4U) #define DSI_ISR1_CRCE_Msk (0x1U << DSI_ISR1_CRCE_Pos) /*!< 0x00000010 */ #define DSI_ISR1_CRCE DSI_ISR1_CRCE_Msk /*!< CRC Error */ #define DSI_ISR1_PSE_Pos (5U) #define DSI_ISR1_PSE_Msk (0x1U << DSI_ISR1_PSE_Pos) /*!< 0x00000020 */ #define DSI_ISR1_PSE DSI_ISR1_PSE_Msk /*!< Packet Size Error */ #define DSI_ISR1_EOTPE_Pos (6U) #define DSI_ISR1_EOTPE_Msk (0x1U << DSI_ISR1_EOTPE_Pos) /*!< 0x00000040 */ #define DSI_ISR1_EOTPE DSI_ISR1_EOTPE_Msk /*!< EoTp Error */ #define DSI_ISR1_LPWRE_Pos (7U) #define DSI_ISR1_LPWRE_Msk (0x1U << DSI_ISR1_LPWRE_Pos) /*!< 0x00000080 */ #define DSI_ISR1_LPWRE DSI_ISR1_LPWRE_Msk /*!< LTDC Payload Write Error */ #define DSI_ISR1_GCWRE_Pos (8U) #define DSI_ISR1_GCWRE_Msk (0x1U << DSI_ISR1_GCWRE_Pos) /*!< 0x00000100 */ #define DSI_ISR1_GCWRE DSI_ISR1_GCWRE_Msk /*!< Generic Command Write Error */ #define DSI_ISR1_GPWRE_Pos (9U) #define DSI_ISR1_GPWRE_Msk (0x1U << DSI_ISR1_GPWRE_Pos) /*!< 0x00000200 */ #define DSI_ISR1_GPWRE DSI_ISR1_GPWRE_Msk /*!< Generic Payload Write Error */ #define DSI_ISR1_GPTXE_Pos (10U) #define DSI_ISR1_GPTXE_Msk (0x1U << DSI_ISR1_GPTXE_Pos) /*!< 0x00000400 */ #define DSI_ISR1_GPTXE DSI_ISR1_GPTXE_Msk /*!< Generic Payload Transmit Error */ #define DSI_ISR1_GPRDE_Pos (11U) #define DSI_ISR1_GPRDE_Msk (0x1U << DSI_ISR1_GPRDE_Pos) /*!< 0x00000800 */ #define DSI_ISR1_GPRDE DSI_ISR1_GPRDE_Msk /*!< Generic Payload Read Error */ #define DSI_ISR1_GPRXE_Pos (12U) #define DSI_ISR1_GPRXE_Msk (0x1U << DSI_ISR1_GPRXE_Pos) /*!< 0x00001000 */ #define DSI_ISR1_GPRXE DSI_ISR1_GPRXE_Msk /*!< Generic Payload Receive Error */ /******************* Bit definition for DSI_IER0 register ***************/ #define DSI_IER0_AE0IE_Pos (0U) #define DSI_IER0_AE0IE_Msk (0x1U << DSI_IER0_AE0IE_Pos) /*!< 0x00000001 */ #define DSI_IER0_AE0IE DSI_IER0_AE0IE_Msk /*!< Acknowledge Error 0 Interrupt Enable */ #define DSI_IER0_AE1IE_Pos (1U) #define DSI_IER0_AE1IE_Msk (0x1U << DSI_IER0_AE1IE_Pos) /*!< 0x00000002 */ #define DSI_IER0_AE1IE DSI_IER0_AE1IE_Msk /*!< Acknowledge Error 1 Interrupt Enable */ #define DSI_IER0_AE2IE_Pos (2U) #define DSI_IER0_AE2IE_Msk (0x1U << DSI_IER0_AE2IE_Pos) /*!< 0x00000004 */ #define DSI_IER0_AE2IE DSI_IER0_AE2IE_Msk /*!< Acknowledge Error 2 Interrupt Enable */ #define DSI_IER0_AE3IE_Pos (3U) #define DSI_IER0_AE3IE_Msk (0x1U << DSI_IER0_AE3IE_Pos) /*!< 0x00000008 */ #define DSI_IER0_AE3IE DSI_IER0_AE3IE_Msk /*!< Acknowledge Error 3 Interrupt Enable */ #define DSI_IER0_AE4IE_Pos (4U) #define DSI_IER0_AE4IE_Msk (0x1U << DSI_IER0_AE4IE_Pos) /*!< 0x00000010 */ #define DSI_IER0_AE4IE DSI_IER0_AE4IE_Msk /*!< Acknowledge Error 4 Interrupt Enable */ #define DSI_IER0_AE5IE_Pos (5U) #define DSI_IER0_AE5IE_Msk (0x1U << DSI_IER0_AE5IE_Pos) /*!< 0x00000020 */ #define DSI_IER0_AE5IE DSI_IER0_AE5IE_Msk /*!< Acknowledge Error 5 Interrupt Enable */ #define DSI_IER0_AE6IE_Pos (6U) #define DSI_IER0_AE6IE_Msk (0x1U << DSI_IER0_AE6IE_Pos) /*!< 0x00000040 */ #define DSI_IER0_AE6IE DSI_IER0_AE6IE_Msk /*!< Acknowledge Error 6 Interrupt Enable */ #define DSI_IER0_AE7IE_Pos (7U) #define DSI_IER0_AE7IE_Msk (0x1U << DSI_IER0_AE7IE_Pos) /*!< 0x00000080 */ #define DSI_IER0_AE7IE DSI_IER0_AE7IE_Msk /*!< Acknowledge Error 7 Interrupt Enable */ #define DSI_IER0_AE8IE_Pos (8U) #define DSI_IER0_AE8IE_Msk (0x1U << DSI_IER0_AE8IE_Pos) /*!< 0x00000100 */ #define DSI_IER0_AE8IE DSI_IER0_AE8IE_Msk /*!< Acknowledge Error 8 Interrupt Enable */ #define DSI_IER0_AE9IE_Pos (9U) #define DSI_IER0_AE9IE_Msk (0x1U << DSI_IER0_AE9IE_Pos) /*!< 0x00000200 */ #define DSI_IER0_AE9IE DSI_IER0_AE9IE_Msk /*!< Acknowledge Error 9 Interrupt Enable */ #define DSI_IER0_AE10IE_Pos (10U) #define DSI_IER0_AE10IE_Msk (0x1U << DSI_IER0_AE10IE_Pos) /*!< 0x00000400 */ #define DSI_IER0_AE10IE DSI_IER0_AE10IE_Msk /*!< Acknowledge Error 10 Interrupt Enable */ #define DSI_IER0_AE11IE_Pos (11U) #define DSI_IER0_AE11IE_Msk (0x1U << DSI_IER0_AE11IE_Pos) /*!< 0x00000800 */ #define DSI_IER0_AE11IE DSI_IER0_AE11IE_Msk /*!< Acknowledge Error 11 Interrupt Enable */ #define DSI_IER0_AE12IE_Pos (12U) #define DSI_IER0_AE12IE_Msk (0x1U << DSI_IER0_AE12IE_Pos) /*!< 0x00001000 */ #define DSI_IER0_AE12IE DSI_IER0_AE12IE_Msk /*!< Acknowledge Error 12 Interrupt Enable */ #define DSI_IER0_AE13IE_Pos (13U) #define DSI_IER0_AE13IE_Msk (0x1U << DSI_IER0_AE13IE_Pos) /*!< 0x00002000 */ #define DSI_IER0_AE13IE DSI_IER0_AE13IE_Msk /*!< Acknowledge Error 13 Interrupt Enable */ #define DSI_IER0_AE14IE_Pos (14U) #define DSI_IER0_AE14IE_Msk (0x1U << DSI_IER0_AE14IE_Pos) /*!< 0x00004000 */ #define DSI_IER0_AE14IE DSI_IER0_AE14IE_Msk /*!< Acknowledge Error 14 Interrupt Enable */ #define DSI_IER0_AE15IE_Pos (15U) #define DSI_IER0_AE15IE_Msk (0x1U << DSI_IER0_AE15IE_Pos) /*!< 0x00008000 */ #define DSI_IER0_AE15IE DSI_IER0_AE15IE_Msk /*!< Acknowledge Error 15 Interrupt Enable */ #define DSI_IER0_PE0IE_Pos (16U) #define DSI_IER0_PE0IE_Msk (0x1U << DSI_IER0_PE0IE_Pos) /*!< 0x00010000 */ #define DSI_IER0_PE0IE DSI_IER0_PE0IE_Msk /*!< PHY Error 0 Interrupt Enable */ #define DSI_IER0_PE1IE_Pos (17U) #define DSI_IER0_PE1IE_Msk (0x1U << DSI_IER0_PE1IE_Pos) /*!< 0x00020000 */ #define DSI_IER0_PE1IE DSI_IER0_PE1IE_Msk /*!< PHY Error 1 Interrupt Enable */ #define DSI_IER0_PE2IE_Pos (18U) #define DSI_IER0_PE2IE_Msk (0x1U << DSI_IER0_PE2IE_Pos) /*!< 0x00040000 */ #define DSI_IER0_PE2IE DSI_IER0_PE2IE_Msk /*!< PHY Error 2 Interrupt Enable */ #define DSI_IER0_PE3IE_Pos (19U) #define DSI_IER0_PE3IE_Msk (0x1U << DSI_IER0_PE3IE_Pos) /*!< 0x00080000 */ #define DSI_IER0_PE3IE DSI_IER0_PE3IE_Msk /*!< PHY Error 3 Interrupt Enable */ #define DSI_IER0_PE4IE_Pos (20U) #define DSI_IER0_PE4IE_Msk (0x1U << DSI_IER0_PE4IE_Pos) /*!< 0x00100000 */ #define DSI_IER0_PE4IE DSI_IER0_PE4IE_Msk /*!< PHY Error 4 Interrupt Enable */ /******************* Bit definition for DSI_IER1 register ***************/ #define DSI_IER1_TOHSTXIE_Pos (0U) #define DSI_IER1_TOHSTXIE_Msk (0x1U << DSI_IER1_TOHSTXIE_Pos) /*!< 0x00000001 */ #define DSI_IER1_TOHSTXIE DSI_IER1_TOHSTXIE_Msk /*!< Timeout High-Speed Transmission Interrupt Enable */ #define DSI_IER1_TOLPRXIE_Pos (1U) #define DSI_IER1_TOLPRXIE_Msk (0x1U << DSI_IER1_TOLPRXIE_Pos) /*!< 0x00000002 */ #define DSI_IER1_TOLPRXIE DSI_IER1_TOLPRXIE_Msk /*!< Timeout Low-Power Reception Interrupt Enable */ #define DSI_IER1_ECCSEIE_Pos (2U) #define DSI_IER1_ECCSEIE_Msk (0x1U << DSI_IER1_ECCSEIE_Pos) /*!< 0x00000004 */ #define DSI_IER1_ECCSEIE DSI_IER1_ECCSEIE_Msk /*!< ECC Single-bit Error Interrupt Enable */ #define DSI_IER1_ECCMEIE_Pos (3U) #define DSI_IER1_ECCMEIE_Msk (0x1U << DSI_IER1_ECCMEIE_Pos) /*!< 0x00000008 */ #define DSI_IER1_ECCMEIE DSI_IER1_ECCMEIE_Msk /*!< ECC Multi-bit Error Interrupt Enable */ #define DSI_IER1_CRCEIE_Pos (4U) #define DSI_IER1_CRCEIE_Msk (0x1U << DSI_IER1_CRCEIE_Pos) /*!< 0x00000010 */ #define DSI_IER1_CRCEIE DSI_IER1_CRCEIE_Msk /*!< CRC Error Interrupt Enable */ #define DSI_IER1_PSEIE_Pos (5U) #define DSI_IER1_PSEIE_Msk (0x1U << DSI_IER1_PSEIE_Pos) /*!< 0x00000020 */ #define DSI_IER1_PSEIE DSI_IER1_PSEIE_Msk /*!< Packet Size Error Interrupt Enable */ #define DSI_IER1_EOTPEIE_Pos (6U) #define DSI_IER1_EOTPEIE_Msk (0x1U << DSI_IER1_EOTPEIE_Pos) /*!< 0x00000040 */ #define DSI_IER1_EOTPEIE DSI_IER1_EOTPEIE_Msk /*!< EoTp Error Interrupt Enable */ #define DSI_IER1_LPWREIE_Pos (7U) #define DSI_IER1_LPWREIE_Msk (0x1U << DSI_IER1_LPWREIE_Pos) /*!< 0x00000080 */ #define DSI_IER1_LPWREIE DSI_IER1_LPWREIE_Msk /*!< LTDC Payload Write Error Interrupt Enable */ #define DSI_IER1_GCWREIE_Pos (8U) #define DSI_IER1_GCWREIE_Msk (0x1U << DSI_IER1_GCWREIE_Pos) /*!< 0x00000100 */ #define DSI_IER1_GCWREIE DSI_IER1_GCWREIE_Msk /*!< Generic Command Write Error Interrupt Enable */ #define DSI_IER1_GPWREIE_Pos (9U) #define DSI_IER1_GPWREIE_Msk (0x1U << DSI_IER1_GPWREIE_Pos) /*!< 0x00000200 */ #define DSI_IER1_GPWREIE DSI_IER1_GPWREIE_Msk /*!< Generic Payload Write Error Interrupt Enable */ #define DSI_IER1_GPTXEIE_Pos (10U) #define DSI_IER1_GPTXEIE_Msk (0x1U << DSI_IER1_GPTXEIE_Pos) /*!< 0x00000400 */ #define DSI_IER1_GPTXEIE DSI_IER1_GPTXEIE_Msk /*!< Generic Payload Transmit Error Interrupt Enable */ #define DSI_IER1_GPRDEIE_Pos (11U) #define DSI_IER1_GPRDEIE_Msk (0x1U << DSI_IER1_GPRDEIE_Pos) /*!< 0x00000800 */ #define DSI_IER1_GPRDEIE DSI_IER1_GPRDEIE_Msk /*!< Generic Payload Read Error Interrupt Enable */ #define DSI_IER1_GPRXEIE_Pos (12U) #define DSI_IER1_GPRXEIE_Msk (0x1U << DSI_IER1_GPRXEIE_Pos) /*!< 0x00001000 */ #define DSI_IER1_GPRXEIE DSI_IER1_GPRXEIE_Msk /*!< Generic Payload Receive Error Interrupt Enable */ /******************* Bit definition for DSI_FIR0 register ***************/ #define DSI_FIR0_FAE0_Pos (0U) #define DSI_FIR0_FAE0_Msk (0x1U << DSI_FIR0_FAE0_Pos) /*!< 0x00000001 */ #define DSI_FIR0_FAE0 DSI_FIR0_FAE0_Msk /*!< Force Acknowledge Error 0 */ #define DSI_FIR0_FAE1_Pos (1U) #define DSI_FIR0_FAE1_Msk (0x1U << DSI_FIR0_FAE1_Pos) /*!< 0x00000002 */ #define DSI_FIR0_FAE1 DSI_FIR0_FAE1_Msk /*!< Force Acknowledge Error 1 */ #define DSI_FIR0_FAE2_Pos (2U) #define DSI_FIR0_FAE2_Msk (0x1U << DSI_FIR0_FAE2_Pos) /*!< 0x00000004 */ #define DSI_FIR0_FAE2 DSI_FIR0_FAE2_Msk /*!< Force Acknowledge Error 2 */ #define DSI_FIR0_FAE3_Pos (3U) #define DSI_FIR0_FAE3_Msk (0x1U << DSI_FIR0_FAE3_Pos) /*!< 0x00000008 */ #define DSI_FIR0_FAE3 DSI_FIR0_FAE3_Msk /*!< Force Acknowledge Error 3 */ #define DSI_FIR0_FAE4_Pos (4U) #define DSI_FIR0_FAE4_Msk (0x1U << DSI_FIR0_FAE4_Pos) /*!< 0x00000010 */ #define DSI_FIR0_FAE4 DSI_FIR0_FAE4_Msk /*!< Force Acknowledge Error 4 */ #define DSI_FIR0_FAE5_Pos (5U) #define DSI_FIR0_FAE5_Msk (0x1U << DSI_FIR0_FAE5_Pos) /*!< 0x00000020 */ #define DSI_FIR0_FAE5 DSI_FIR0_FAE5_Msk /*!< Force Acknowledge Error 5 */ #define DSI_FIR0_FAE6_Pos (6U) #define DSI_FIR0_FAE6_Msk (0x1U << DSI_FIR0_FAE6_Pos) /*!< 0x00000040 */ #define DSI_FIR0_FAE6 DSI_FIR0_FAE6_Msk /*!< Force Acknowledge Error 6 */ #define DSI_FIR0_FAE7_Pos (7U) #define DSI_FIR0_FAE7_Msk (0x1U << DSI_FIR0_FAE7_Pos) /*!< 0x00000080 */ #define DSI_FIR0_FAE7 DSI_FIR0_FAE7_Msk /*!< Force Acknowledge Error 7 */ #define DSI_FIR0_FAE8_Pos (8U) #define DSI_FIR0_FAE8_Msk (0x1U << DSI_FIR0_FAE8_Pos) /*!< 0x00000100 */ #define DSI_FIR0_FAE8 DSI_FIR0_FAE8_Msk /*!< Force Acknowledge Error 8 */ #define DSI_FIR0_FAE9_Pos (9U) #define DSI_FIR0_FAE9_Msk (0x1U << DSI_FIR0_FAE9_Pos) /*!< 0x00000200 */ #define DSI_FIR0_FAE9 DSI_FIR0_FAE9_Msk /*!< Force Acknowledge Error 9 */ #define DSI_FIR0_FAE10_Pos (10U) #define DSI_FIR0_FAE10_Msk (0x1U << DSI_FIR0_FAE10_Pos) /*!< 0x00000400 */ #define DSI_FIR0_FAE10 DSI_FIR0_FAE10_Msk /*!< Force Acknowledge Error 10 */ #define DSI_FIR0_FAE11_Pos (11U) #define DSI_FIR0_FAE11_Msk (0x1U << DSI_FIR0_FAE11_Pos) /*!< 0x00000800 */ #define DSI_FIR0_FAE11 DSI_FIR0_FAE11_Msk /*!< Force Acknowledge Error 11 */ #define DSI_FIR0_FAE12_Pos (12U) #define DSI_FIR0_FAE12_Msk (0x1U << DSI_FIR0_FAE12_Pos) /*!< 0x00001000 */ #define DSI_FIR0_FAE12 DSI_FIR0_FAE12_Msk /*!< Force Acknowledge Error 12 */ #define DSI_FIR0_FAE13_Pos (13U) #define DSI_FIR0_FAE13_Msk (0x1U << DSI_FIR0_FAE13_Pos) /*!< 0x00002000 */ #define DSI_FIR0_FAE13 DSI_FIR0_FAE13_Msk /*!< Force Acknowledge Error 13 */ #define DSI_FIR0_FAE14_Pos (14U) #define DSI_FIR0_FAE14_Msk (0x1U << DSI_FIR0_FAE14_Pos) /*!< 0x00004000 */ #define DSI_FIR0_FAE14 DSI_FIR0_FAE14_Msk /*!< Force Acknowledge Error 14 */ #define DSI_FIR0_FAE15_Pos (15U) #define DSI_FIR0_FAE15_Msk (0x1U << DSI_FIR0_FAE15_Pos) /*!< 0x00008000 */ #define DSI_FIR0_FAE15 DSI_FIR0_FAE15_Msk /*!< Force Acknowledge Error 15 */ #define DSI_FIR0_FPE0_Pos (16U) #define DSI_FIR0_FPE0_Msk (0x1U << DSI_FIR0_FPE0_Pos) /*!< 0x00010000 */ #define DSI_FIR0_FPE0 DSI_FIR0_FPE0_Msk /*!< Force PHY Error 0 */ #define DSI_FIR0_FPE1_Pos (17U) #define DSI_FIR0_FPE1_Msk (0x1U << DSI_FIR0_FPE1_Pos) /*!< 0x00020000 */ #define DSI_FIR0_FPE1 DSI_FIR0_FPE1_Msk /*!< Force PHY Error 1 */ #define DSI_FIR0_FPE2_Pos (18U) #define DSI_FIR0_FPE2_Msk (0x1U << DSI_FIR0_FPE2_Pos) /*!< 0x00040000 */ #define DSI_FIR0_FPE2 DSI_FIR0_FPE2_Msk /*!< Force PHY Error 2 */ #define DSI_FIR0_FPE3_Pos (19U) #define DSI_FIR0_FPE3_Msk (0x1U << DSI_FIR0_FPE3_Pos) /*!< 0x00080000 */ #define DSI_FIR0_FPE3 DSI_FIR0_FPE3_Msk /*!< Force PHY Error 3 */ #define DSI_FIR0_FPE4_Pos (20U) #define DSI_FIR0_FPE4_Msk (0x1U << DSI_FIR0_FPE4_Pos) /*!< 0x00100000 */ #define DSI_FIR0_FPE4 DSI_FIR0_FPE4_Msk /*!< Force PHY Error 4 */ /******************* Bit definition for DSI_FIR1 register ***************/ #define DSI_FIR1_FTOHSTX_Pos (0U) #define DSI_FIR1_FTOHSTX_Msk (0x1U << DSI_FIR1_FTOHSTX_Pos) /*!< 0x00000001 */ #define DSI_FIR1_FTOHSTX DSI_FIR1_FTOHSTX_Msk /*!< Force Timeout High-Speed Transmission */ #define DSI_FIR1_FTOLPRX_Pos (1U) #define DSI_FIR1_FTOLPRX_Msk (0x1U << DSI_FIR1_FTOLPRX_Pos) /*!< 0x00000002 */ #define DSI_FIR1_FTOLPRX DSI_FIR1_FTOLPRX_Msk /*!< Force Timeout Low-Power Reception */ #define DSI_FIR1_FECCSE_Pos (2U) #define DSI_FIR1_FECCSE_Msk (0x1U << DSI_FIR1_FECCSE_Pos) /*!< 0x00000004 */ #define DSI_FIR1_FECCSE DSI_FIR1_FECCSE_Msk /*!< Force ECC Single-bit Error */ #define DSI_FIR1_FECCME_Pos (3U) #define DSI_FIR1_FECCME_Msk (0x1U << DSI_FIR1_FECCME_Pos) /*!< 0x00000008 */ #define DSI_FIR1_FECCME DSI_FIR1_FECCME_Msk /*!< Force ECC Multi-bit Error */ #define DSI_FIR1_FCRCE_Pos (4U) #define DSI_FIR1_FCRCE_Msk (0x1U << DSI_FIR1_FCRCE_Pos) /*!< 0x00000010 */ #define DSI_FIR1_FCRCE DSI_FIR1_FCRCE_Msk /*!< Force CRC Error */ #define DSI_FIR1_FPSE_Pos (5U) #define DSI_FIR1_FPSE_Msk (0x1U << DSI_FIR1_FPSE_Pos) /*!< 0x00000020 */ #define DSI_FIR1_FPSE DSI_FIR1_FPSE_Msk /*!< Force Packet Size Error */ #define DSI_FIR1_FEOTPE_Pos (6U) #define DSI_FIR1_FEOTPE_Msk (0x1U << DSI_FIR1_FEOTPE_Pos) /*!< 0x00000040 */ #define DSI_FIR1_FEOTPE DSI_FIR1_FEOTPE_Msk /*!< Force EoTp Error */ #define DSI_FIR1_FLPWRE_Pos (7U) #define DSI_FIR1_FLPWRE_Msk (0x1U << DSI_FIR1_FLPWRE_Pos) /*!< 0x00000080 */ #define DSI_FIR1_FLPWRE DSI_FIR1_FLPWRE_Msk /*!< Force LTDC Payload Write Error */ #define DSI_FIR1_FGCWRE_Pos (8U) #define DSI_FIR1_FGCWRE_Msk (0x1U << DSI_FIR1_FGCWRE_Pos) /*!< 0x00000100 */ #define DSI_FIR1_FGCWRE DSI_FIR1_FGCWRE_Msk /*!< Force Generic Command Write Error */ #define DSI_FIR1_FGPWRE_Pos (9U) #define DSI_FIR1_FGPWRE_Msk (0x1U << DSI_FIR1_FGPWRE_Pos) /*!< 0x00000200 */ #define DSI_FIR1_FGPWRE DSI_FIR1_FGPWRE_Msk /*!< Force Generic Payload Write Error */ #define DSI_FIR1_FGPTXE_Pos (10U) #define DSI_FIR1_FGPTXE_Msk (0x1U << DSI_FIR1_FGPTXE_Pos) /*!< 0x00000400 */ #define DSI_FIR1_FGPTXE DSI_FIR1_FGPTXE_Msk /*!< Force Generic Payload Transmit Error */ #define DSI_FIR1_FGPRDE_Pos (11U) #define DSI_FIR1_FGPRDE_Msk (0x1U << DSI_FIR1_FGPRDE_Pos) /*!< 0x00000800 */ #define DSI_FIR1_FGPRDE DSI_FIR1_FGPRDE_Msk /*!< Force Generic Payload Read Error */ #define DSI_FIR1_FGPRXE_Pos (12U) #define DSI_FIR1_FGPRXE_Msk (0x1U << DSI_FIR1_FGPRXE_Pos) /*!< 0x00001000 */ #define DSI_FIR1_FGPRXE DSI_FIR1_FGPRXE_Msk /*!< Force Generic Payload Receive Error */ /******************* Bit definition for DSI_VSCR register ***************/ #define DSI_VSCR_EN_Pos (0U) #define DSI_VSCR_EN_Msk (0x1U << DSI_VSCR_EN_Pos) /*!< 0x00000001 */ #define DSI_VSCR_EN DSI_VSCR_EN_Msk /*!< Enable */ #define DSI_VSCR_UR_Pos (8U) #define DSI_VSCR_UR_Msk (0x1U << DSI_VSCR_UR_Pos) /*!< 0x00000100 */ #define DSI_VSCR_UR DSI_VSCR_UR_Msk /*!< Update Register */ /******************* Bit definition for DSI_LCVCIDR register ************/ #define DSI_LCVCIDR_VCID_Pos (0U) #define DSI_LCVCIDR_VCID_Msk (0x3U << DSI_LCVCIDR_VCID_Pos) /*!< 0x00000003 */ #define DSI_LCVCIDR_VCID DSI_LCVCIDR_VCID_Msk /*!< Virtual Channel ID */ #define DSI_LCVCIDR_VCID0_Pos (0U) #define DSI_LCVCIDR_VCID0_Msk (0x1U << DSI_LCVCIDR_VCID0_Pos) /*!< 0x00000001 */ #define DSI_LCVCIDR_VCID0 DSI_LCVCIDR_VCID0_Msk #define DSI_LCVCIDR_VCID1_Pos (1U) #define DSI_LCVCIDR_VCID1_Msk (0x1U << DSI_LCVCIDR_VCID1_Pos) /*!< 0x00000002 */ #define DSI_LCVCIDR_VCID1 DSI_LCVCIDR_VCID1_Msk /******************* Bit definition for DSI_LCCCR register **************/ #define DSI_LCCCR_COLC_Pos (0U) #define DSI_LCCCR_COLC_Msk (0xFU << DSI_LCCCR_COLC_Pos) /*!< 0x0000000F */ #define DSI_LCCCR_COLC DSI_LCCCR_COLC_Msk /*!< Color Coding */ #define DSI_LCCCR_COLC0_Pos (0U) #define DSI_LCCCR_COLC0_Msk (0x1U << DSI_LCCCR_COLC0_Pos) /*!< 0x00000001 */ #define DSI_LCCCR_COLC0 DSI_LCCCR_COLC0_Msk #define DSI_LCCCR_COLC1_Pos (1U) #define DSI_LCCCR_COLC1_Msk (0x1U << DSI_LCCCR_COLC1_Pos) /*!< 0x00000002 */ #define DSI_LCCCR_COLC1 DSI_LCCCR_COLC1_Msk #define DSI_LCCCR_COLC2_Pos (2U) #define DSI_LCCCR_COLC2_Msk (0x1U << DSI_LCCCR_COLC2_Pos) /*!< 0x00000004 */ #define DSI_LCCCR_COLC2 DSI_LCCCR_COLC2_Msk #define DSI_LCCCR_COLC3_Pos (3U) #define DSI_LCCCR_COLC3_Msk (0x1U << DSI_LCCCR_COLC3_Pos) /*!< 0x00000008 */ #define DSI_LCCCR_COLC3 DSI_LCCCR_COLC3_Msk #define DSI_LCCCR_LPE_Pos (8U) #define DSI_LCCCR_LPE_Msk (0x1U << DSI_LCCCR_LPE_Pos) /*!< 0x00000100 */ #define DSI_LCCCR_LPE DSI_LCCCR_LPE_Msk /*!< Loosely Packed Enable */ /******************* Bit definition for DSI_LPMCCR register *************/ #define DSI_LPMCCR_VLPSIZE_Pos (0U) #define DSI_LPMCCR_VLPSIZE_Msk (0xFFU << DSI_LPMCCR_VLPSIZE_Pos) /*!< 0x000000FF */ #define DSI_LPMCCR_VLPSIZE DSI_LPMCCR_VLPSIZE_Msk /*!< VACT Largest Packet Size */ #define DSI_LPMCCR_VLPSIZE0_Pos (0U) #define DSI_LPMCCR_VLPSIZE0_Msk (0x1U << DSI_LPMCCR_VLPSIZE0_Pos) /*!< 0x00000001 */ #define DSI_LPMCCR_VLPSIZE0 DSI_LPMCCR_VLPSIZE0_Msk #define DSI_LPMCCR_VLPSIZE1_Pos (1U) #define DSI_LPMCCR_VLPSIZE1_Msk (0x1U << DSI_LPMCCR_VLPSIZE1_Pos) /*!< 0x00000002 */ #define DSI_LPMCCR_VLPSIZE1 DSI_LPMCCR_VLPSIZE1_Msk #define DSI_LPMCCR_VLPSIZE2_Pos (2U) #define DSI_LPMCCR_VLPSIZE2_Msk (0x1U << DSI_LPMCCR_VLPSIZE2_Pos) /*!< 0x00000004 */ #define DSI_LPMCCR_VLPSIZE2 DSI_LPMCCR_VLPSIZE2_Msk #define DSI_LPMCCR_VLPSIZE3_Pos (3U) #define DSI_LPMCCR_VLPSIZE3_Msk (0x1U << DSI_LPMCCR_VLPSIZE3_Pos) /*!< 0x00000008 */ #define DSI_LPMCCR_VLPSIZE3 DSI_LPMCCR_VLPSIZE3_Msk #define DSI_LPMCCR_VLPSIZE4_Pos (4U) #define DSI_LPMCCR_VLPSIZE4_Msk (0x1U << DSI_LPMCCR_VLPSIZE4_Pos) /*!< 0x00000010 */ #define DSI_LPMCCR_VLPSIZE4 DSI_LPMCCR_VLPSIZE4_Msk #define DSI_LPMCCR_VLPSIZE5_Pos (5U) #define DSI_LPMCCR_VLPSIZE5_Msk (0x1U << DSI_LPMCCR_VLPSIZE5_Pos) /*!< 0x00000020 */ #define DSI_LPMCCR_VLPSIZE5 DSI_LPMCCR_VLPSIZE5_Msk #define DSI_LPMCCR_VLPSIZE6_Pos (6U) #define DSI_LPMCCR_VLPSIZE6_Msk (0x1U << DSI_LPMCCR_VLPSIZE6_Pos) /*!< 0x00000040 */ #define DSI_LPMCCR_VLPSIZE6 DSI_LPMCCR_VLPSIZE6_Msk #define DSI_LPMCCR_VLPSIZE7_Pos (7U) #define DSI_LPMCCR_VLPSIZE7_Msk (0x1U << DSI_LPMCCR_VLPSIZE7_Pos) /*!< 0x00000080 */ #define DSI_LPMCCR_VLPSIZE7 DSI_LPMCCR_VLPSIZE7_Msk #define DSI_LPMCCR_LPSIZE_Pos (16U) #define DSI_LPMCCR_LPSIZE_Msk (0xFFU << DSI_LPMCCR_LPSIZE_Pos) /*!< 0x00FF0000 */ #define DSI_LPMCCR_LPSIZE DSI_LPMCCR_LPSIZE_Msk /*!< Largest Packet Size */ #define DSI_LPMCCR_LPSIZE0_Pos (16U) #define DSI_LPMCCR_LPSIZE0_Msk (0x1U << DSI_LPMCCR_LPSIZE0_Pos) /*!< 0x00010000 */ #define DSI_LPMCCR_LPSIZE0 DSI_LPMCCR_LPSIZE0_Msk #define DSI_LPMCCR_LPSIZE1_Pos (17U) #define DSI_LPMCCR_LPSIZE1_Msk (0x1U << DSI_LPMCCR_LPSIZE1_Pos) /*!< 0x00020000 */ #define DSI_LPMCCR_LPSIZE1 DSI_LPMCCR_LPSIZE1_Msk #define DSI_LPMCCR_LPSIZE2_Pos (18U) #define DSI_LPMCCR_LPSIZE2_Msk (0x1U << DSI_LPMCCR_LPSIZE2_Pos) /*!< 0x00040000 */ #define DSI_LPMCCR_LPSIZE2 DSI_LPMCCR_LPSIZE2_Msk #define DSI_LPMCCR_LPSIZE3_Pos (19U) #define DSI_LPMCCR_LPSIZE3_Msk (0x1U << DSI_LPMCCR_LPSIZE3_Pos) /*!< 0x00080000 */ #define DSI_LPMCCR_LPSIZE3 DSI_LPMCCR_LPSIZE3_Msk #define DSI_LPMCCR_LPSIZE4_Pos (20U) #define DSI_LPMCCR_LPSIZE4_Msk (0x1U << DSI_LPMCCR_LPSIZE4_Pos) /*!< 0x00100000 */ #define DSI_LPMCCR_LPSIZE4 DSI_LPMCCR_LPSIZE4_Msk #define DSI_LPMCCR_LPSIZE5_Pos (21U) #define DSI_LPMCCR_LPSIZE5_Msk (0x1U << DSI_LPMCCR_LPSIZE5_Pos) /*!< 0x00200000 */ #define DSI_LPMCCR_LPSIZE5 DSI_LPMCCR_LPSIZE5_Msk #define DSI_LPMCCR_LPSIZE6_Pos (22U) #define DSI_LPMCCR_LPSIZE6_Msk (0x1U << DSI_LPMCCR_LPSIZE6_Pos) /*!< 0x00400000 */ #define DSI_LPMCCR_LPSIZE6 DSI_LPMCCR_LPSIZE6_Msk #define DSI_LPMCCR_LPSIZE7_Pos (23U) #define DSI_LPMCCR_LPSIZE7_Msk (0x1U << DSI_LPMCCR_LPSIZE7_Pos) /*!< 0x00800000 */ #define DSI_LPMCCR_LPSIZE7 DSI_LPMCCR_LPSIZE7_Msk /******************* Bit definition for DSI_VMCCR register **************/ #define DSI_VMCCR_VMT_Pos (0U) #define DSI_VMCCR_VMT_Msk (0x3U << DSI_VMCCR_VMT_Pos) /*!< 0x00000003 */ #define DSI_VMCCR_VMT DSI_VMCCR_VMT_Msk /*!< Video Mode Type */ #define DSI_VMCCR_VMT0_Pos (0U) #define DSI_VMCCR_VMT0_Msk (0x1U << DSI_VMCCR_VMT0_Pos) /*!< 0x00000001 */ #define DSI_VMCCR_VMT0 DSI_VMCCR_VMT0_Msk #define DSI_VMCCR_VMT1_Pos (1U) #define DSI_VMCCR_VMT1_Msk (0x1U << DSI_VMCCR_VMT1_Pos) /*!< 0x00000002 */ #define DSI_VMCCR_VMT1 DSI_VMCCR_VMT1_Msk #define DSI_VMCCR_LPVSAE_Pos (8U) #define DSI_VMCCR_LPVSAE_Msk (0x1U << DSI_VMCCR_LPVSAE_Pos) /*!< 0x00000100 */ #define DSI_VMCCR_LPVSAE DSI_VMCCR_LPVSAE_Msk /*!< Low-power Vertical Sync time Enable */ #define DSI_VMCCR_LPVBPE_Pos (9U) #define DSI_VMCCR_LPVBPE_Msk (0x1U << DSI_VMCCR_LPVBPE_Pos) /*!< 0x00000200 */ #define DSI_VMCCR_LPVBPE DSI_VMCCR_LPVBPE_Msk /*!< Low-power Vertical Back-porch Enable */ #define DSI_VMCCR_LPVFPE_Pos (10U) #define DSI_VMCCR_LPVFPE_Msk (0x1U << DSI_VMCCR_LPVFPE_Pos) /*!< 0x00000400 */ #define DSI_VMCCR_LPVFPE DSI_VMCCR_LPVFPE_Msk /*!< Low-power Vertical Front-porch Enable */ #define DSI_VMCCR_LPVAE_Pos (11U) #define DSI_VMCCR_LPVAE_Msk (0x1U << DSI_VMCCR_LPVAE_Pos) /*!< 0x00000800 */ #define DSI_VMCCR_LPVAE DSI_VMCCR_LPVAE_Msk /*!< Low-power Vertical Active Enable */ #define DSI_VMCCR_LPHBPE_Pos (12U) #define DSI_VMCCR_LPHBPE_Msk (0x1U << DSI_VMCCR_LPHBPE_Pos) /*!< 0x00001000 */ #define DSI_VMCCR_LPHBPE DSI_VMCCR_LPHBPE_Msk /*!< Low-power Horizontal Back-porch Enable */ #define DSI_VMCCR_LPHFE_Pos (13U) #define DSI_VMCCR_LPHFE_Msk (0x1U << DSI_VMCCR_LPHFE_Pos) /*!< 0x00002000 */ #define DSI_VMCCR_LPHFE DSI_VMCCR_LPHFE_Msk /*!< Low-power Horizontal Front-porch Enable */ #define DSI_VMCCR_FBTAAE_Pos (14U) #define DSI_VMCCR_FBTAAE_Msk (0x1U << DSI_VMCCR_FBTAAE_Pos) /*!< 0x00004000 */ #define DSI_VMCCR_FBTAAE DSI_VMCCR_FBTAAE_Msk /*!< Frame BTA Acknowledge Enable */ #define DSI_VMCCR_LPCE_Pos (15U) #define DSI_VMCCR_LPCE_Msk (0x1U << DSI_VMCCR_LPCE_Pos) /*!< 0x00008000 */ #define DSI_VMCCR_LPCE DSI_VMCCR_LPCE_Msk /*!< Low-power Command Enable */ /******************* Bit definition for DSI_VPCCR register **************/ #define DSI_VPCCR_VPSIZE_Pos (0U) #define DSI_VPCCR_VPSIZE_Msk (0x3FFFU << DSI_VPCCR_VPSIZE_Pos) /*!< 0x00003FFF */ #define DSI_VPCCR_VPSIZE DSI_VPCCR_VPSIZE_Msk /*!< Video Packet Size */ #define DSI_VPCCR_VPSIZE0_Pos (0U) #define DSI_VPCCR_VPSIZE0_Msk (0x1U << DSI_VPCCR_VPSIZE0_Pos) /*!< 0x00000001 */ #define DSI_VPCCR_VPSIZE0 DSI_VPCCR_VPSIZE0_Msk #define DSI_VPCCR_VPSIZE1_Pos (1U) #define DSI_VPCCR_VPSIZE1_Msk (0x1U << DSI_VPCCR_VPSIZE1_Pos) /*!< 0x00000002 */ #define DSI_VPCCR_VPSIZE1 DSI_VPCCR_VPSIZE1_Msk #define DSI_VPCCR_VPSIZE2_Pos (2U) #define DSI_VPCCR_VPSIZE2_Msk (0x1U << DSI_VPCCR_VPSIZE2_Pos) /*!< 0x00000004 */ #define DSI_VPCCR_VPSIZE2 DSI_VPCCR_VPSIZE2_Msk #define DSI_VPCCR_VPSIZE3_Pos (3U) #define DSI_VPCCR_VPSIZE3_Msk (0x1U << DSI_VPCCR_VPSIZE3_Pos) /*!< 0x00000008 */ #define DSI_VPCCR_VPSIZE3 DSI_VPCCR_VPSIZE3_Msk #define DSI_VPCCR_VPSIZE4_Pos (4U) #define DSI_VPCCR_VPSIZE4_Msk (0x1U << DSI_VPCCR_VPSIZE4_Pos) /*!< 0x00000010 */ #define DSI_VPCCR_VPSIZE4 DSI_VPCCR_VPSIZE4_Msk #define DSI_VPCCR_VPSIZE5_Pos (5U) #define DSI_VPCCR_VPSIZE5_Msk (0x1U << DSI_VPCCR_VPSIZE5_Pos) /*!< 0x00000020 */ #define DSI_VPCCR_VPSIZE5 DSI_VPCCR_VPSIZE5_Msk #define DSI_VPCCR_VPSIZE6_Pos (6U) #define DSI_VPCCR_VPSIZE6_Msk (0x1U << DSI_VPCCR_VPSIZE6_Pos) /*!< 0x00000040 */ #define DSI_VPCCR_VPSIZE6 DSI_VPCCR_VPSIZE6_Msk #define DSI_VPCCR_VPSIZE7_Pos (7U) #define DSI_VPCCR_VPSIZE7_Msk (0x1U << DSI_VPCCR_VPSIZE7_Pos) /*!< 0x00000080 */ #define DSI_VPCCR_VPSIZE7 DSI_VPCCR_VPSIZE7_Msk #define DSI_VPCCR_VPSIZE8_Pos (8U) #define DSI_VPCCR_VPSIZE8_Msk (0x1U << DSI_VPCCR_VPSIZE8_Pos) /*!< 0x00000100 */ #define DSI_VPCCR_VPSIZE8 DSI_VPCCR_VPSIZE8_Msk #define DSI_VPCCR_VPSIZE9_Pos (9U) #define DSI_VPCCR_VPSIZE9_Msk (0x1U << DSI_VPCCR_VPSIZE9_Pos) /*!< 0x00000200 */ #define DSI_VPCCR_VPSIZE9 DSI_VPCCR_VPSIZE9_Msk #define DSI_VPCCR_VPSIZE10_Pos (10U) #define DSI_VPCCR_VPSIZE10_Msk (0x1U << DSI_VPCCR_VPSIZE10_Pos) /*!< 0x00000400 */ #define DSI_VPCCR_VPSIZE10 DSI_VPCCR_VPSIZE10_Msk #define DSI_VPCCR_VPSIZE11_Pos (11U) #define DSI_VPCCR_VPSIZE11_Msk (0x1U << DSI_VPCCR_VPSIZE11_Pos) /*!< 0x00000800 */ #define DSI_VPCCR_VPSIZE11 DSI_VPCCR_VPSIZE11_Msk #define DSI_VPCCR_VPSIZE12_Pos (12U) #define DSI_VPCCR_VPSIZE12_Msk (0x1U << DSI_VPCCR_VPSIZE12_Pos) /*!< 0x00001000 */ #define DSI_VPCCR_VPSIZE12 DSI_VPCCR_VPSIZE12_Msk #define DSI_VPCCR_VPSIZE13_Pos (13U) #define DSI_VPCCR_VPSIZE13_Msk (0x1U << DSI_VPCCR_VPSIZE13_Pos) /*!< 0x00002000 */ #define DSI_VPCCR_VPSIZE13 DSI_VPCCR_VPSIZE13_Msk /******************* Bit definition for DSI_VCCCR register **************/ #define DSI_VCCCR_NUMC_Pos (0U) #define DSI_VCCCR_NUMC_Msk (0x1FFFU << DSI_VCCCR_NUMC_Pos) /*!< 0x00001FFF */ #define DSI_VCCCR_NUMC DSI_VCCCR_NUMC_Msk /*!< Number of Chunks */ #define DSI_VCCCR_NUMC0_Pos (0U) #define DSI_VCCCR_NUMC0_Msk (0x1U << DSI_VCCCR_NUMC0_Pos) /*!< 0x00000001 */ #define DSI_VCCCR_NUMC0 DSI_VCCCR_NUMC0_Msk #define DSI_VCCCR_NUMC1_Pos (1U) #define DSI_VCCCR_NUMC1_Msk (0x1U << DSI_VCCCR_NUMC1_Pos) /*!< 0x00000002 */ #define DSI_VCCCR_NUMC1 DSI_VCCCR_NUMC1_Msk #define DSI_VCCCR_NUMC2_Pos (2U) #define DSI_VCCCR_NUMC2_Msk (0x1U << DSI_VCCCR_NUMC2_Pos) /*!< 0x00000004 */ #define DSI_VCCCR_NUMC2 DSI_VCCCR_NUMC2_Msk #define DSI_VCCCR_NUMC3_Pos (3U) #define DSI_VCCCR_NUMC3_Msk (0x1U << DSI_VCCCR_NUMC3_Pos) /*!< 0x00000008 */ #define DSI_VCCCR_NUMC3 DSI_VCCCR_NUMC3_Msk #define DSI_VCCCR_NUMC4_Pos (4U) #define DSI_VCCCR_NUMC4_Msk (0x1U << DSI_VCCCR_NUMC4_Pos) /*!< 0x00000010 */ #define DSI_VCCCR_NUMC4 DSI_VCCCR_NUMC4_Msk #define DSI_VCCCR_NUMC5_Pos (5U) #define DSI_VCCCR_NUMC5_Msk (0x1U << DSI_VCCCR_NUMC5_Pos) /*!< 0x00000020 */ #define DSI_VCCCR_NUMC5 DSI_VCCCR_NUMC5_Msk #define DSI_VCCCR_NUMC6_Pos (6U) #define DSI_VCCCR_NUMC6_Msk (0x1U << DSI_VCCCR_NUMC6_Pos) /*!< 0x00000040 */ #define DSI_VCCCR_NUMC6 DSI_VCCCR_NUMC6_Msk #define DSI_VCCCR_NUMC7_Pos (7U) #define DSI_VCCCR_NUMC7_Msk (0x1U << DSI_VCCCR_NUMC7_Pos) /*!< 0x00000080 */ #define DSI_VCCCR_NUMC7 DSI_VCCCR_NUMC7_Msk #define DSI_VCCCR_NUMC8_Pos (8U) #define DSI_VCCCR_NUMC8_Msk (0x1U << DSI_VCCCR_NUMC8_Pos) /*!< 0x00000100 */ #define DSI_VCCCR_NUMC8 DSI_VCCCR_NUMC8_Msk #define DSI_VCCCR_NUMC9_Pos (9U) #define DSI_VCCCR_NUMC9_Msk (0x1U << DSI_VCCCR_NUMC9_Pos) /*!< 0x00000200 */ #define DSI_VCCCR_NUMC9 DSI_VCCCR_NUMC9_Msk #define DSI_VCCCR_NUMC10_Pos (10U) #define DSI_VCCCR_NUMC10_Msk (0x1U << DSI_VCCCR_NUMC10_Pos) /*!< 0x00000400 */ #define DSI_VCCCR_NUMC10 DSI_VCCCR_NUMC10_Msk #define DSI_VCCCR_NUMC11_Pos (11U) #define DSI_VCCCR_NUMC11_Msk (0x1U << DSI_VCCCR_NUMC11_Pos) /*!< 0x00000800 */ #define DSI_VCCCR_NUMC11 DSI_VCCCR_NUMC11_Msk #define DSI_VCCCR_NUMC12_Pos (12U) #define DSI_VCCCR_NUMC12_Msk (0x1U << DSI_VCCCR_NUMC12_Pos) /*!< 0x00001000 */ #define DSI_VCCCR_NUMC12 DSI_VCCCR_NUMC12_Msk /******************* Bit definition for DSI_VNPCCR register *************/ #define DSI_VNPCCR_NPSIZE_Pos (0U) #define DSI_VNPCCR_NPSIZE_Msk (0x1FFFU << DSI_VNPCCR_NPSIZE_Pos) /*!< 0x00001FFF */ #define DSI_VNPCCR_NPSIZE DSI_VNPCCR_NPSIZE_Msk /*!< Number of Chunks */ #define DSI_VNPCCR_NPSIZE0_Pos (0U) #define DSI_VNPCCR_NPSIZE0_Msk (0x1U << DSI_VNPCCR_NPSIZE0_Pos) /*!< 0x00000001 */ #define DSI_VNPCCR_NPSIZE0 DSI_VNPCCR_NPSIZE0_Msk #define DSI_VNPCCR_NPSIZE1_Pos (1U) #define DSI_VNPCCR_NPSIZE1_Msk (0x1U << DSI_VNPCCR_NPSIZE1_Pos) /*!< 0x00000002 */ #define DSI_VNPCCR_NPSIZE1 DSI_VNPCCR_NPSIZE1_Msk #define DSI_VNPCCR_NPSIZE2_Pos (2U) #define DSI_VNPCCR_NPSIZE2_Msk (0x1U << DSI_VNPCCR_NPSIZE2_Pos) /*!< 0x00000004 */ #define DSI_VNPCCR_NPSIZE2 DSI_VNPCCR_NPSIZE2_Msk #define DSI_VNPCCR_NPSIZE3_Pos (3U) #define DSI_VNPCCR_NPSIZE3_Msk (0x1U << DSI_VNPCCR_NPSIZE3_Pos) /*!< 0x00000008 */ #define DSI_VNPCCR_NPSIZE3 DSI_VNPCCR_NPSIZE3_Msk #define DSI_VNPCCR_NPSIZE4_Pos (4U) #define DSI_VNPCCR_NPSIZE4_Msk (0x1U << DSI_VNPCCR_NPSIZE4_Pos) /*!< 0x00000010 */ #define DSI_VNPCCR_NPSIZE4 DSI_VNPCCR_NPSIZE4_Msk #define DSI_VNPCCR_NPSIZE5_Pos (5U) #define DSI_VNPCCR_NPSIZE5_Msk (0x1U << DSI_VNPCCR_NPSIZE5_Pos) /*!< 0x00000020 */ #define DSI_VNPCCR_NPSIZE5 DSI_VNPCCR_NPSIZE5_Msk #define DSI_VNPCCR_NPSIZE6_Pos (6U) #define DSI_VNPCCR_NPSIZE6_Msk (0x1U << DSI_VNPCCR_NPSIZE6_Pos) /*!< 0x00000040 */ #define DSI_VNPCCR_NPSIZE6 DSI_VNPCCR_NPSIZE6_Msk #define DSI_VNPCCR_NPSIZE7_Pos (7U) #define DSI_VNPCCR_NPSIZE7_Msk (0x1U << DSI_VNPCCR_NPSIZE7_Pos) /*!< 0x00000080 */ #define DSI_VNPCCR_NPSIZE7 DSI_VNPCCR_NPSIZE7_Msk #define DSI_VNPCCR_NPSIZE8_Pos (8U) #define DSI_VNPCCR_NPSIZE8_Msk (0x1U << DSI_VNPCCR_NPSIZE8_Pos) /*!< 0x00000100 */ #define DSI_VNPCCR_NPSIZE8 DSI_VNPCCR_NPSIZE8_Msk #define DSI_VNPCCR_NPSIZE9_Pos (9U) #define DSI_VNPCCR_NPSIZE9_Msk (0x1U << DSI_VNPCCR_NPSIZE9_Pos) /*!< 0x00000200 */ #define DSI_VNPCCR_NPSIZE9 DSI_VNPCCR_NPSIZE9_Msk #define DSI_VNPCCR_NPSIZE10_Pos (10U) #define DSI_VNPCCR_NPSIZE10_Msk (0x1U << DSI_VNPCCR_NPSIZE10_Pos) /*!< 0x00000400 */ #define DSI_VNPCCR_NPSIZE10 DSI_VNPCCR_NPSIZE10_Msk #define DSI_VNPCCR_NPSIZE11_Pos (11U) #define DSI_VNPCCR_NPSIZE11_Msk (0x1U << DSI_VNPCCR_NPSIZE11_Pos) /*!< 0x00000800 */ #define DSI_VNPCCR_NPSIZE11 DSI_VNPCCR_NPSIZE11_Msk #define DSI_VNPCCR_NPSIZE12_Pos (12U) #define DSI_VNPCCR_NPSIZE12_Msk (0x1U << DSI_VNPCCR_NPSIZE12_Pos) /*!< 0x00001000 */ #define DSI_VNPCCR_NPSIZE12 DSI_VNPCCR_NPSIZE12_Msk /******************* Bit definition for DSI_VHSACCR register ************/ #define DSI_VHSACCR_HSA_Pos (0U) #define DSI_VHSACCR_HSA_Msk (0xFFFU << DSI_VHSACCR_HSA_Pos) /*!< 0x00000FFF */ #define DSI_VHSACCR_HSA DSI_VHSACCR_HSA_Msk /*!< Horizontal Synchronism Active duration */ #define DSI_VHSACCR_HSA0_Pos (0U) #define DSI_VHSACCR_HSA0_Msk (0x1U << DSI_VHSACCR_HSA0_Pos) /*!< 0x00000001 */ #define DSI_VHSACCR_HSA0 DSI_VHSACCR_HSA0_Msk #define DSI_VHSACCR_HSA1_Pos (1U) #define DSI_VHSACCR_HSA1_Msk (0x1U << DSI_VHSACCR_HSA1_Pos) /*!< 0x00000002 */ #define DSI_VHSACCR_HSA1 DSI_VHSACCR_HSA1_Msk #define DSI_VHSACCR_HSA2_Pos (2U) #define DSI_VHSACCR_HSA2_Msk (0x1U << DSI_VHSACCR_HSA2_Pos) /*!< 0x00000004 */ #define DSI_VHSACCR_HSA2 DSI_VHSACCR_HSA2_Msk #define DSI_VHSACCR_HSA3_Pos (3U) #define DSI_VHSACCR_HSA3_Msk (0x1U << DSI_VHSACCR_HSA3_Pos) /*!< 0x00000008 */ #define DSI_VHSACCR_HSA3 DSI_VHSACCR_HSA3_Msk #define DSI_VHSACCR_HSA4_Pos (4U) #define DSI_VHSACCR_HSA4_Msk (0x1U << DSI_VHSACCR_HSA4_Pos) /*!< 0x00000010 */ #define DSI_VHSACCR_HSA4 DSI_VHSACCR_HSA4_Msk #define DSI_VHSACCR_HSA5_Pos (5U) #define DSI_VHSACCR_HSA5_Msk (0x1U << DSI_VHSACCR_HSA5_Pos) /*!< 0x00000020 */ #define DSI_VHSACCR_HSA5 DSI_VHSACCR_HSA5_Msk #define DSI_VHSACCR_HSA6_Pos (6U) #define DSI_VHSACCR_HSA6_Msk (0x1U << DSI_VHSACCR_HSA6_Pos) /*!< 0x00000040 */ #define DSI_VHSACCR_HSA6 DSI_VHSACCR_HSA6_Msk #define DSI_VHSACCR_HSA7_Pos (7U) #define DSI_VHSACCR_HSA7_Msk (0x1U << DSI_VHSACCR_HSA7_Pos) /*!< 0x00000080 */ #define DSI_VHSACCR_HSA7 DSI_VHSACCR_HSA7_Msk #define DSI_VHSACCR_HSA8_Pos (8U) #define DSI_VHSACCR_HSA8_Msk (0x1U << DSI_VHSACCR_HSA8_Pos) /*!< 0x00000100 */ #define DSI_VHSACCR_HSA8 DSI_VHSACCR_HSA8_Msk #define DSI_VHSACCR_HSA9_Pos (9U) #define DSI_VHSACCR_HSA9_Msk (0x1U << DSI_VHSACCR_HSA9_Pos) /*!< 0x00000200 */ #define DSI_VHSACCR_HSA9 DSI_VHSACCR_HSA9_Msk #define DSI_VHSACCR_HSA10_Pos (10U) #define DSI_VHSACCR_HSA10_Msk (0x1U << DSI_VHSACCR_HSA10_Pos) /*!< 0x00000400 */ #define DSI_VHSACCR_HSA10 DSI_VHSACCR_HSA10_Msk #define DSI_VHSACCR_HSA11_Pos (11U) #define DSI_VHSACCR_HSA11_Msk (0x1U << DSI_VHSACCR_HSA11_Pos) /*!< 0x00000800 */ #define DSI_VHSACCR_HSA11 DSI_VHSACCR_HSA11_Msk /******************* Bit definition for DSI_VHBPCCR register ************/ #define DSI_VHBPCCR_HBP_Pos (0U) #define DSI_VHBPCCR_HBP_Msk (0xFFFU << DSI_VHBPCCR_HBP_Pos) /*!< 0x00000FFF */ #define DSI_VHBPCCR_HBP DSI_VHBPCCR_HBP_Msk /*!< Horizontal Back-Porch duration */ #define DSI_VHBPCCR_HBP0_Pos (0U) #define DSI_VHBPCCR_HBP0_Msk (0x1U << DSI_VHBPCCR_HBP0_Pos) /*!< 0x00000001 */ #define DSI_VHBPCCR_HBP0 DSI_VHBPCCR_HBP0_Msk #define DSI_VHBPCCR_HBP1_Pos (1U) #define DSI_VHBPCCR_HBP1_Msk (0x1U << DSI_VHBPCCR_HBP1_Pos) /*!< 0x00000002 */ #define DSI_VHBPCCR_HBP1 DSI_VHBPCCR_HBP1_Msk #define DSI_VHBPCCR_HBP2_Pos (2U) #define DSI_VHBPCCR_HBP2_Msk (0x1U << DSI_VHBPCCR_HBP2_Pos) /*!< 0x00000004 */ #define DSI_VHBPCCR_HBP2 DSI_VHBPCCR_HBP2_Msk #define DSI_VHBPCCR_HBP3_Pos (3U) #define DSI_VHBPCCR_HBP3_Msk (0x1U << DSI_VHBPCCR_HBP3_Pos) /*!< 0x00000008 */ #define DSI_VHBPCCR_HBP3 DSI_VHBPCCR_HBP3_Msk #define DSI_VHBPCCR_HBP4_Pos (4U) #define DSI_VHBPCCR_HBP4_Msk (0x1U << DSI_VHBPCCR_HBP4_Pos) /*!< 0x00000010 */ #define DSI_VHBPCCR_HBP4 DSI_VHBPCCR_HBP4_Msk #define DSI_VHBPCCR_HBP5_Pos (5U) #define DSI_VHBPCCR_HBP5_Msk (0x1U << DSI_VHBPCCR_HBP5_Pos) /*!< 0x00000020 */ #define DSI_VHBPCCR_HBP5 DSI_VHBPCCR_HBP5_Msk #define DSI_VHBPCCR_HBP6_Pos (6U) #define DSI_VHBPCCR_HBP6_Msk (0x1U << DSI_VHBPCCR_HBP6_Pos) /*!< 0x00000040 */ #define DSI_VHBPCCR_HBP6 DSI_VHBPCCR_HBP6_Msk #define DSI_VHBPCCR_HBP7_Pos (7U) #define DSI_VHBPCCR_HBP7_Msk (0x1U << DSI_VHBPCCR_HBP7_Pos) /*!< 0x00000080 */ #define DSI_VHBPCCR_HBP7 DSI_VHBPCCR_HBP7_Msk #define DSI_VHBPCCR_HBP8_Pos (8U) #define DSI_VHBPCCR_HBP8_Msk (0x1U << DSI_VHBPCCR_HBP8_Pos) /*!< 0x00000100 */ #define DSI_VHBPCCR_HBP8 DSI_VHBPCCR_HBP8_Msk #define DSI_VHBPCCR_HBP9_Pos (9U) #define DSI_VHBPCCR_HBP9_Msk (0x1U << DSI_VHBPCCR_HBP9_Pos) /*!< 0x00000200 */ #define DSI_VHBPCCR_HBP9 DSI_VHBPCCR_HBP9_Msk #define DSI_VHBPCCR_HBP10_Pos (10U) #define DSI_VHBPCCR_HBP10_Msk (0x1U << DSI_VHBPCCR_HBP10_Pos) /*!< 0x00000400 */ #define DSI_VHBPCCR_HBP10 DSI_VHBPCCR_HBP10_Msk #define DSI_VHBPCCR_HBP11_Pos (11U) #define DSI_VHBPCCR_HBP11_Msk (0x1U << DSI_VHBPCCR_HBP11_Pos) /*!< 0x00000800 */ #define DSI_VHBPCCR_HBP11 DSI_VHBPCCR_HBP11_Msk /******************* Bit definition for DSI_VLCCR register **************/ #define DSI_VLCCR_HLINE_Pos (0U) #define DSI_VLCCR_HLINE_Msk (0x7FFFU << DSI_VLCCR_HLINE_Pos) /*!< 0x00007FFF */ #define DSI_VLCCR_HLINE DSI_VLCCR_HLINE_Msk /*!< Horizontal Line duration */ #define DSI_VLCCR_HLINE0_Pos (0U) #define DSI_VLCCR_HLINE0_Msk (0x1U << DSI_VLCCR_HLINE0_Pos) /*!< 0x00000001 */ #define DSI_VLCCR_HLINE0 DSI_VLCCR_HLINE0_Msk #define DSI_VLCCR_HLINE1_Pos (1U) #define DSI_VLCCR_HLINE1_Msk (0x1U << DSI_VLCCR_HLINE1_Pos) /*!< 0x00000002 */ #define DSI_VLCCR_HLINE1 DSI_VLCCR_HLINE1_Msk #define DSI_VLCCR_HLINE2_Pos (2U) #define DSI_VLCCR_HLINE2_Msk (0x1U << DSI_VLCCR_HLINE2_Pos) /*!< 0x00000004 */ #define DSI_VLCCR_HLINE2 DSI_VLCCR_HLINE2_Msk #define DSI_VLCCR_HLINE3_Pos (3U) #define DSI_VLCCR_HLINE3_Msk (0x1U << DSI_VLCCR_HLINE3_Pos) /*!< 0x00000008 */ #define DSI_VLCCR_HLINE3 DSI_VLCCR_HLINE3_Msk #define DSI_VLCCR_HLINE4_Pos (4U) #define DSI_VLCCR_HLINE4_Msk (0x1U << DSI_VLCCR_HLINE4_Pos) /*!< 0x00000010 */ #define DSI_VLCCR_HLINE4 DSI_VLCCR_HLINE4_Msk #define DSI_VLCCR_HLINE5_Pos (5U) #define DSI_VLCCR_HLINE5_Msk (0x1U << DSI_VLCCR_HLINE5_Pos) /*!< 0x00000020 */ #define DSI_VLCCR_HLINE5 DSI_VLCCR_HLINE5_Msk #define DSI_VLCCR_HLINE6_Pos (6U) #define DSI_VLCCR_HLINE6_Msk (0x1U << DSI_VLCCR_HLINE6_Pos) /*!< 0x00000040 */ #define DSI_VLCCR_HLINE6 DSI_VLCCR_HLINE6_Msk #define DSI_VLCCR_HLINE7_Pos (7U) #define DSI_VLCCR_HLINE7_Msk (0x1U << DSI_VLCCR_HLINE7_Pos) /*!< 0x00000080 */ #define DSI_VLCCR_HLINE7 DSI_VLCCR_HLINE7_Msk #define DSI_VLCCR_HLINE8_Pos (8U) #define DSI_VLCCR_HLINE8_Msk (0x1U << DSI_VLCCR_HLINE8_Pos) /*!< 0x00000100 */ #define DSI_VLCCR_HLINE8 DSI_VLCCR_HLINE8_Msk #define DSI_VLCCR_HLINE9_Pos (9U) #define DSI_VLCCR_HLINE9_Msk (0x1U << DSI_VLCCR_HLINE9_Pos) /*!< 0x00000200 */ #define DSI_VLCCR_HLINE9 DSI_VLCCR_HLINE9_Msk #define DSI_VLCCR_HLINE10_Pos (10U) #define DSI_VLCCR_HLINE10_Msk (0x1U << DSI_VLCCR_HLINE10_Pos) /*!< 0x00000400 */ #define DSI_VLCCR_HLINE10 DSI_VLCCR_HLINE10_Msk #define DSI_VLCCR_HLINE11_Pos (11U) #define DSI_VLCCR_HLINE11_Msk (0x1U << DSI_VLCCR_HLINE11_Pos) /*!< 0x00000800 */ #define DSI_VLCCR_HLINE11 DSI_VLCCR_HLINE11_Msk #define DSI_VLCCR_HLINE12_Pos (12U) #define DSI_VLCCR_HLINE12_Msk (0x1U << DSI_VLCCR_HLINE12_Pos) /*!< 0x00001000 */ #define DSI_VLCCR_HLINE12 DSI_VLCCR_HLINE12_Msk #define DSI_VLCCR_HLINE13_Pos (13U) #define DSI_VLCCR_HLINE13_Msk (0x1U << DSI_VLCCR_HLINE13_Pos) /*!< 0x00002000 */ #define DSI_VLCCR_HLINE13 DSI_VLCCR_HLINE13_Msk #define DSI_VLCCR_HLINE14_Pos (14U) #define DSI_VLCCR_HLINE14_Msk (0x1U << DSI_VLCCR_HLINE14_Pos) /*!< 0x00004000 */ #define DSI_VLCCR_HLINE14 DSI_VLCCR_HLINE14_Msk /******************* Bit definition for DSI_VVSACCR register ***************/ #define DSI_VVSACCR_VSA_Pos (0U) #define DSI_VVSACCR_VSA_Msk (0x3FFU << DSI_VVSACCR_VSA_Pos) /*!< 0x000003FF */ #define DSI_VVSACCR_VSA DSI_VVSACCR_VSA_Msk /*!< Vertical Synchronism Active duration */ #define DSI_VVSACCR_VSA0_Pos (0U) #define DSI_VVSACCR_VSA0_Msk (0x1U << DSI_VVSACCR_VSA0_Pos) /*!< 0x00000001 */ #define DSI_VVSACCR_VSA0 DSI_VVSACCR_VSA0_Msk #define DSI_VVSACCR_VSA1_Pos (1U) #define DSI_VVSACCR_VSA1_Msk (0x1U << DSI_VVSACCR_VSA1_Pos) /*!< 0x00000002 */ #define DSI_VVSACCR_VSA1 DSI_VVSACCR_VSA1_Msk #define DSI_VVSACCR_VSA2_Pos (2U) #define DSI_VVSACCR_VSA2_Msk (0x1U << DSI_VVSACCR_VSA2_Pos) /*!< 0x00000004 */ #define DSI_VVSACCR_VSA2 DSI_VVSACCR_VSA2_Msk #define DSI_VVSACCR_VSA3_Pos (3U) #define DSI_VVSACCR_VSA3_Msk (0x1U << DSI_VVSACCR_VSA3_Pos) /*!< 0x00000008 */ #define DSI_VVSACCR_VSA3 DSI_VVSACCR_VSA3_Msk #define DSI_VVSACCR_VSA4_Pos (4U) #define DSI_VVSACCR_VSA4_Msk (0x1U << DSI_VVSACCR_VSA4_Pos) /*!< 0x00000010 */ #define DSI_VVSACCR_VSA4 DSI_VVSACCR_VSA4_Msk #define DSI_VVSACCR_VSA5_Pos (5U) #define DSI_VVSACCR_VSA5_Msk (0x1U << DSI_VVSACCR_VSA5_Pos) /*!< 0x00000020 */ #define DSI_VVSACCR_VSA5 DSI_VVSACCR_VSA5_Msk #define DSI_VVSACCR_VSA6_Pos (6U) #define DSI_VVSACCR_VSA6_Msk (0x1U << DSI_VVSACCR_VSA6_Pos) /*!< 0x00000040 */ #define DSI_VVSACCR_VSA6 DSI_VVSACCR_VSA6_Msk #define DSI_VVSACCR_VSA7_Pos (7U) #define DSI_VVSACCR_VSA7_Msk (0x1U << DSI_VVSACCR_VSA7_Pos) /*!< 0x00000080 */ #define DSI_VVSACCR_VSA7 DSI_VVSACCR_VSA7_Msk #define DSI_VVSACCR_VSA8_Pos (8U) #define DSI_VVSACCR_VSA8_Msk (0x1U << DSI_VVSACCR_VSA8_Pos) /*!< 0x00000100 */ #define DSI_VVSACCR_VSA8 DSI_VVSACCR_VSA8_Msk #define DSI_VVSACCR_VSA9_Pos (9U) #define DSI_VVSACCR_VSA9_Msk (0x1U << DSI_VVSACCR_VSA9_Pos) /*!< 0x00000200 */ #define DSI_VVSACCR_VSA9 DSI_VVSACCR_VSA9_Msk /******************* Bit definition for DSI_VVBPCCR register ************/ #define DSI_VVBPCCR_VBP_Pos (0U) #define DSI_VVBPCCR_VBP_Msk (0x3FFU << DSI_VVBPCCR_VBP_Pos) /*!< 0x000003FF */ #define DSI_VVBPCCR_VBP DSI_VVBPCCR_VBP_Msk /*!< Vertical Back-Porch duration */ #define DSI_VVBPCCR_VBP0_Pos (0U) #define DSI_VVBPCCR_VBP0_Msk (0x1U << DSI_VVBPCCR_VBP0_Pos) /*!< 0x00000001 */ #define DSI_VVBPCCR_VBP0 DSI_VVBPCCR_VBP0_Msk #define DSI_VVBPCCR_VBP1_Pos (1U) #define DSI_VVBPCCR_VBP1_Msk (0x1U << DSI_VVBPCCR_VBP1_Pos) /*!< 0x00000002 */ #define DSI_VVBPCCR_VBP1 DSI_VVBPCCR_VBP1_Msk #define DSI_VVBPCCR_VBP2_Pos (2U) #define DSI_VVBPCCR_VBP2_Msk (0x1U << DSI_VVBPCCR_VBP2_Pos) /*!< 0x00000004 */ #define DSI_VVBPCCR_VBP2 DSI_VVBPCCR_VBP2_Msk #define DSI_VVBPCCR_VBP3_Pos (3U) #define DSI_VVBPCCR_VBP3_Msk (0x1U << DSI_VVBPCCR_VBP3_Pos) /*!< 0x00000008 */ #define DSI_VVBPCCR_VBP3 DSI_VVBPCCR_VBP3_Msk #define DSI_VVBPCCR_VBP4_Pos (4U) #define DSI_VVBPCCR_VBP4_Msk (0x1U << DSI_VVBPCCR_VBP4_Pos) /*!< 0x00000010 */ #define DSI_VVBPCCR_VBP4 DSI_VVBPCCR_VBP4_Msk #define DSI_VVBPCCR_VBP5_Pos (5U) #define DSI_VVBPCCR_VBP5_Msk (0x1U << DSI_VVBPCCR_VBP5_Pos) /*!< 0x00000020 */ #define DSI_VVBPCCR_VBP5 DSI_VVBPCCR_VBP5_Msk #define DSI_VVBPCCR_VBP6_Pos (6U) #define DSI_VVBPCCR_VBP6_Msk (0x1U << DSI_VVBPCCR_VBP6_Pos) /*!< 0x00000040 */ #define DSI_VVBPCCR_VBP6 DSI_VVBPCCR_VBP6_Msk #define DSI_VVBPCCR_VBP7_Pos (7U) #define DSI_VVBPCCR_VBP7_Msk (0x1U << DSI_VVBPCCR_VBP7_Pos) /*!< 0x00000080 */ #define DSI_VVBPCCR_VBP7 DSI_VVBPCCR_VBP7_Msk #define DSI_VVBPCCR_VBP8_Pos (8U) #define DSI_VVBPCCR_VBP8_Msk (0x1U << DSI_VVBPCCR_VBP8_Pos) /*!< 0x00000100 */ #define DSI_VVBPCCR_VBP8 DSI_VVBPCCR_VBP8_Msk #define DSI_VVBPCCR_VBP9_Pos (9U) #define DSI_VVBPCCR_VBP9_Msk (0x1U << DSI_VVBPCCR_VBP9_Pos) /*!< 0x00000200 */ #define DSI_VVBPCCR_VBP9 DSI_VVBPCCR_VBP9_Msk /******************* Bit definition for DSI_VVFPCCR register ************/ #define DSI_VVFPCCR_VFP_Pos (0U) #define DSI_VVFPCCR_VFP_Msk (0x3FFU << DSI_VVFPCCR_VFP_Pos) /*!< 0x000003FF */ #define DSI_VVFPCCR_VFP DSI_VVFPCCR_VFP_Msk /*!< Vertical Front-Porch duration */ #define DSI_VVFPCCR_VFP0_Pos (0U) #define DSI_VVFPCCR_VFP0_Msk (0x1U << DSI_VVFPCCR_VFP0_Pos) /*!< 0x00000001 */ #define DSI_VVFPCCR_VFP0 DSI_VVFPCCR_VFP0_Msk #define DSI_VVFPCCR_VFP1_Pos (1U) #define DSI_VVFPCCR_VFP1_Msk (0x1U << DSI_VVFPCCR_VFP1_Pos) /*!< 0x00000002 */ #define DSI_VVFPCCR_VFP1 DSI_VVFPCCR_VFP1_Msk #define DSI_VVFPCCR_VFP2_Pos (2U) #define DSI_VVFPCCR_VFP2_Msk (0x1U << DSI_VVFPCCR_VFP2_Pos) /*!< 0x00000004 */ #define DSI_VVFPCCR_VFP2 DSI_VVFPCCR_VFP2_Msk #define DSI_VVFPCCR_VFP3_Pos (3U) #define DSI_VVFPCCR_VFP3_Msk (0x1U << DSI_VVFPCCR_VFP3_Pos) /*!< 0x00000008 */ #define DSI_VVFPCCR_VFP3 DSI_VVFPCCR_VFP3_Msk #define DSI_VVFPCCR_VFP4_Pos (4U) #define DSI_VVFPCCR_VFP4_Msk (0x1U << DSI_VVFPCCR_VFP4_Pos) /*!< 0x00000010 */ #define DSI_VVFPCCR_VFP4 DSI_VVFPCCR_VFP4_Msk #define DSI_VVFPCCR_VFP5_Pos (5U) #define DSI_VVFPCCR_VFP5_Msk (0x1U << DSI_VVFPCCR_VFP5_Pos) /*!< 0x00000020 */ #define DSI_VVFPCCR_VFP5 DSI_VVFPCCR_VFP5_Msk #define DSI_VVFPCCR_VFP6_Pos (6U) #define DSI_VVFPCCR_VFP6_Msk (0x1U << DSI_VVFPCCR_VFP6_Pos) /*!< 0x00000040 */ #define DSI_VVFPCCR_VFP6 DSI_VVFPCCR_VFP6_Msk #define DSI_VVFPCCR_VFP7_Pos (7U) #define DSI_VVFPCCR_VFP7_Msk (0x1U << DSI_VVFPCCR_VFP7_Pos) /*!< 0x00000080 */ #define DSI_VVFPCCR_VFP7 DSI_VVFPCCR_VFP7_Msk #define DSI_VVFPCCR_VFP8_Pos (8U) #define DSI_VVFPCCR_VFP8_Msk (0x1U << DSI_VVFPCCR_VFP8_Pos) /*!< 0x00000100 */ #define DSI_VVFPCCR_VFP8 DSI_VVFPCCR_VFP8_Msk #define DSI_VVFPCCR_VFP9_Pos (9U) #define DSI_VVFPCCR_VFP9_Msk (0x1U << DSI_VVFPCCR_VFP9_Pos) /*!< 0x00000200 */ #define DSI_VVFPCCR_VFP9 DSI_VVFPCCR_VFP9_Msk /******************* Bit definition for DSI_VVACCR register *************/ #define DSI_VVACCR_VA_Pos (0U) #define DSI_VVACCR_VA_Msk (0x3FFFU << DSI_VVACCR_VA_Pos) /*!< 0x00003FFF */ #define DSI_VVACCR_VA DSI_VVACCR_VA_Msk /*!< Vertical Active duration */ #define DSI_VVACCR_VA0_Pos (0U) #define DSI_VVACCR_VA0_Msk (0x1U << DSI_VVACCR_VA0_Pos) /*!< 0x00000001 */ #define DSI_VVACCR_VA0 DSI_VVACCR_VA0_Msk #define DSI_VVACCR_VA1_Pos (1U) #define DSI_VVACCR_VA1_Msk (0x1U << DSI_VVACCR_VA1_Pos) /*!< 0x00000002 */ #define DSI_VVACCR_VA1 DSI_VVACCR_VA1_Msk #define DSI_VVACCR_VA2_Pos (2U) #define DSI_VVACCR_VA2_Msk (0x1U << DSI_VVACCR_VA2_Pos) /*!< 0x00000004 */ #define DSI_VVACCR_VA2 DSI_VVACCR_VA2_Msk #define DSI_VVACCR_VA3_Pos (3U) #define DSI_VVACCR_VA3_Msk (0x1U << DSI_VVACCR_VA3_Pos) /*!< 0x00000008 */ #define DSI_VVACCR_VA3 DSI_VVACCR_VA3_Msk #define DSI_VVACCR_VA4_Pos (4U) #define DSI_VVACCR_VA4_Msk (0x1U << DSI_VVACCR_VA4_Pos) /*!< 0x00000010 */ #define DSI_VVACCR_VA4 DSI_VVACCR_VA4_Msk #define DSI_VVACCR_VA5_Pos (5U) #define DSI_VVACCR_VA5_Msk (0x1U << DSI_VVACCR_VA5_Pos) /*!< 0x00000020 */ #define DSI_VVACCR_VA5 DSI_VVACCR_VA5_Msk #define DSI_VVACCR_VA6_Pos (6U) #define DSI_VVACCR_VA6_Msk (0x1U << DSI_VVACCR_VA6_Pos) /*!< 0x00000040 */ #define DSI_VVACCR_VA6 DSI_VVACCR_VA6_Msk #define DSI_VVACCR_VA7_Pos (7U) #define DSI_VVACCR_VA7_Msk (0x1U << DSI_VVACCR_VA7_Pos) /*!< 0x00000080 */ #define DSI_VVACCR_VA7 DSI_VVACCR_VA7_Msk #define DSI_VVACCR_VA8_Pos (8U) #define DSI_VVACCR_VA8_Msk (0x1U << DSI_VVACCR_VA8_Pos) /*!< 0x00000100 */ #define DSI_VVACCR_VA8 DSI_VVACCR_VA8_Msk #define DSI_VVACCR_VA9_Pos (9U) #define DSI_VVACCR_VA9_Msk (0x1U << DSI_VVACCR_VA9_Pos) /*!< 0x00000200 */ #define DSI_VVACCR_VA9 DSI_VVACCR_VA9_Msk #define DSI_VVACCR_VA10_Pos (10U) #define DSI_VVACCR_VA10_Msk (0x1U << DSI_VVACCR_VA10_Pos) /*!< 0x00000400 */ #define DSI_VVACCR_VA10 DSI_VVACCR_VA10_Msk #define DSI_VVACCR_VA11_Pos (11U) #define DSI_VVACCR_VA11_Msk (0x1U << DSI_VVACCR_VA11_Pos) /*!< 0x00000800 */ #define DSI_VVACCR_VA11 DSI_VVACCR_VA11_Msk #define DSI_VVACCR_VA12_Pos (12U) #define DSI_VVACCR_VA12_Msk (0x1U << DSI_VVACCR_VA12_Pos) /*!< 0x00001000 */ #define DSI_VVACCR_VA12 DSI_VVACCR_VA12_Msk #define DSI_VVACCR_VA13_Pos (13U) #define DSI_VVACCR_VA13_Msk (0x1U << DSI_VVACCR_VA13_Pos) /*!< 0x00002000 */ #define DSI_VVACCR_VA13 DSI_VVACCR_VA13_Msk /******************* Bit definition for DSI_TDCCR register **************/ #define DSI_TDCCR_3DM 0x00000003U /*!< 3D Mode */ #define DSI_TDCCR_3DM0 0x00000001U #define DSI_TDCCR_3DM1 0x00000002U #define DSI_TDCCR_3DF 0x0000000CU /*!< 3D Format */ #define DSI_TDCCR_3DF0 0x00000004U #define DSI_TDCCR_3DF1 0x00000008U #define DSI_TDCCR_SVS_Pos (4U) #define DSI_TDCCR_SVS_Msk (0x1U << DSI_TDCCR_SVS_Pos) /*!< 0x00000010 */ #define DSI_TDCCR_SVS DSI_TDCCR_SVS_Msk /*!< Second VSYNC */ #define DSI_TDCCR_RF_Pos (5U) #define DSI_TDCCR_RF_Msk (0x1U << DSI_TDCCR_RF_Pos) /*!< 0x00000020 */ #define DSI_TDCCR_RF DSI_TDCCR_RF_Msk /*!< Right First */ #define DSI_TDCCR_S3DC_Pos (16U) #define DSI_TDCCR_S3DC_Msk (0x1U << DSI_TDCCR_S3DC_Pos) /*!< 0x00010000 */ #define DSI_TDCCR_S3DC DSI_TDCCR_S3DC_Msk /*!< Send 3D Control */ /******************* Bit definition for DSI_WCFGR register ***************/ #define DSI_WCFGR_DSIM_Pos (0U) #define DSI_WCFGR_DSIM_Msk (0x1U << DSI_WCFGR_DSIM_Pos) /*!< 0x00000001 */ #define DSI_WCFGR_DSIM DSI_WCFGR_DSIM_Msk /*!< DSI Mode */ #define DSI_WCFGR_COLMUX_Pos (1U) #define DSI_WCFGR_COLMUX_Msk (0x7U << DSI_WCFGR_COLMUX_Pos) /*!< 0x0000000E */ #define DSI_WCFGR_COLMUX DSI_WCFGR_COLMUX_Msk /*!< Color Multiplexing */ #define DSI_WCFGR_COLMUX0_Pos (1U) #define DSI_WCFGR_COLMUX0_Msk (0x1U << DSI_WCFGR_COLMUX0_Pos) /*!< 0x00000002 */ #define DSI_WCFGR_COLMUX0 DSI_WCFGR_COLMUX0_Msk #define DSI_WCFGR_COLMUX1_Pos (2U) #define DSI_WCFGR_COLMUX1_Msk (0x1U << DSI_WCFGR_COLMUX1_Pos) /*!< 0x00000004 */ #define DSI_WCFGR_COLMUX1 DSI_WCFGR_COLMUX1_Msk #define DSI_WCFGR_COLMUX2_Pos (3U) #define DSI_WCFGR_COLMUX2_Msk (0x1U << DSI_WCFGR_COLMUX2_Pos) /*!< 0x00000008 */ #define DSI_WCFGR_COLMUX2 DSI_WCFGR_COLMUX2_Msk #define DSI_WCFGR_TESRC_Pos (4U) #define DSI_WCFGR_TESRC_Msk (0x1U << DSI_WCFGR_TESRC_Pos) /*!< 0x00000010 */ #define DSI_WCFGR_TESRC DSI_WCFGR_TESRC_Msk /*!< Tearing Effect Source */ #define DSI_WCFGR_TEPOL_Pos (5U) #define DSI_WCFGR_TEPOL_Msk (0x1U << DSI_WCFGR_TEPOL_Pos) /*!< 0x00000020 */ #define DSI_WCFGR_TEPOL DSI_WCFGR_TEPOL_Msk /*!< Tearing Effect Polarity */ #define DSI_WCFGR_AR_Pos (6U) #define DSI_WCFGR_AR_Msk (0x1U << DSI_WCFGR_AR_Pos) /*!< 0x00000040 */ #define DSI_WCFGR_AR DSI_WCFGR_AR_Msk /*!< Automatic Refresh */ #define DSI_WCFGR_VSPOL_Pos (7U) #define DSI_WCFGR_VSPOL_Msk (0x1U << DSI_WCFGR_VSPOL_Pos) /*!< 0x00000080 */ #define DSI_WCFGR_VSPOL DSI_WCFGR_VSPOL_Msk /*!< VSync Polarity */ /******************* Bit definition for DSI_WCR register *****************/ #define DSI_WCR_COLM_Pos (0U) #define DSI_WCR_COLM_Msk (0x1U << DSI_WCR_COLM_Pos) /*!< 0x00000001 */ #define DSI_WCR_COLM DSI_WCR_COLM_Msk /*!< Color Mode */ #define DSI_WCR_SHTDN_Pos (1U) #define DSI_WCR_SHTDN_Msk (0x1U << DSI_WCR_SHTDN_Pos) /*!< 0x00000002 */ #define DSI_WCR_SHTDN DSI_WCR_SHTDN_Msk /*!< Shutdown */ #define DSI_WCR_LTDCEN_Pos (2U) #define DSI_WCR_LTDCEN_Msk (0x1U << DSI_WCR_LTDCEN_Pos) /*!< 0x00000004 */ #define DSI_WCR_LTDCEN DSI_WCR_LTDCEN_Msk /*!< LTDC Enable */ #define DSI_WCR_DSIEN_Pos (3U) #define DSI_WCR_DSIEN_Msk (0x1U << DSI_WCR_DSIEN_Pos) /*!< 0x00000008 */ #define DSI_WCR_DSIEN DSI_WCR_DSIEN_Msk /*!< DSI Enable */ /******************* Bit definition for DSI_WIER register ****************/ #define DSI_WIER_TEIE_Pos (0U) #define DSI_WIER_TEIE_Msk (0x1U << DSI_WIER_TEIE_Pos) /*!< 0x00000001 */ #define DSI_WIER_TEIE DSI_WIER_TEIE_Msk /*!< Tearing Effect Interrupt Enable */ #define DSI_WIER_ERIE_Pos (1U) #define DSI_WIER_ERIE_Msk (0x1U << DSI_WIER_ERIE_Pos) /*!< 0x00000002 */ #define DSI_WIER_ERIE DSI_WIER_ERIE_Msk /*!< End of Refresh Interrupt Enable */ #define DSI_WIER_PLLLIE_Pos (9U) #define DSI_WIER_PLLLIE_Msk (0x1U << DSI_WIER_PLLLIE_Pos) /*!< 0x00000200 */ #define DSI_WIER_PLLLIE DSI_WIER_PLLLIE_Msk /*!< PLL Lock Interrupt Enable */ #define DSI_WIER_PLLUIE_Pos (10U) #define DSI_WIER_PLLUIE_Msk (0x1U << DSI_WIER_PLLUIE_Pos) /*!< 0x00000400 */ #define DSI_WIER_PLLUIE DSI_WIER_PLLUIE_Msk /*!< PLL Unlock Interrupt Enable */ #define DSI_WIER_RRIE_Pos (13U) #define DSI_WIER_RRIE_Msk (0x1U << DSI_WIER_RRIE_Pos) /*!< 0x00002000 */ #define DSI_WIER_RRIE DSI_WIER_RRIE_Msk /*!< Regulator Ready Interrupt Enable */ /******************* Bit definition for DSI_WISR register ****************/ #define DSI_WISR_TEIF_Pos (0U) #define DSI_WISR_TEIF_Msk (0x1U << DSI_WISR_TEIF_Pos) /*!< 0x00000001 */ #define DSI_WISR_TEIF DSI_WISR_TEIF_Msk /*!< Tearing Effect Interrupt Flag */ #define DSI_WISR_ERIF_Pos (1U) #define DSI_WISR_ERIF_Msk (0x1U << DSI_WISR_ERIF_Pos) /*!< 0x00000002 */ #define DSI_WISR_ERIF DSI_WISR_ERIF_Msk /*!< End of Refresh Interrupt Flag */ #define DSI_WISR_BUSY_Pos (2U) #define DSI_WISR_BUSY_Msk (0x1U << DSI_WISR_BUSY_Pos) /*!< 0x00000004 */ #define DSI_WISR_BUSY DSI_WISR_BUSY_Msk /*!< Busy Flag */ #define DSI_WISR_PLLLS_Pos (8U) #define DSI_WISR_PLLLS_Msk (0x1U << DSI_WISR_PLLLS_Pos) /*!< 0x00000100 */ #define DSI_WISR_PLLLS DSI_WISR_PLLLS_Msk /*!< PLL Lock Status */ #define DSI_WISR_PLLLIF_Pos (9U) #define DSI_WISR_PLLLIF_Msk (0x1U << DSI_WISR_PLLLIF_Pos) /*!< 0x00000200 */ #define DSI_WISR_PLLLIF DSI_WISR_PLLLIF_Msk /*!< PLL Lock Interrupt Flag */ #define DSI_WISR_PLLUIF_Pos (10U) #define DSI_WISR_PLLUIF_Msk (0x1U << DSI_WISR_PLLUIF_Pos) /*!< 0x00000400 */ #define DSI_WISR_PLLUIF DSI_WISR_PLLUIF_Msk /*!< PLL Unlock Interrupt Flag */ #define DSI_WISR_RRS_Pos (12U) #define DSI_WISR_RRS_Msk (0x1U << DSI_WISR_RRS_Pos) /*!< 0x00001000 */ #define DSI_WISR_RRS DSI_WISR_RRS_Msk /*!< Regulator Ready Flag */ #define DSI_WISR_RRIF_Pos (13U) #define DSI_WISR_RRIF_Msk (0x1U << DSI_WISR_RRIF_Pos) /*!< 0x00002000 */ #define DSI_WISR_RRIF DSI_WISR_RRIF_Msk /*!< Regulator Ready Interrupt Flag */ /******************* Bit definition for DSI_WIFCR register ***************/ #define DSI_WIFCR_CTEIF_Pos (0U) #define DSI_WIFCR_CTEIF_Msk (0x1U << DSI_WIFCR_CTEIF_Pos) /*!< 0x00000001 */ #define DSI_WIFCR_CTEIF DSI_WIFCR_CTEIF_Msk /*!< Clear Tearing Effect Interrupt Flag */ #define DSI_WIFCR_CERIF_Pos (1U) #define DSI_WIFCR_CERIF_Msk (0x1U << DSI_WIFCR_CERIF_Pos) /*!< 0x00000002 */ #define DSI_WIFCR_CERIF DSI_WIFCR_CERIF_Msk /*!< Clear End of Refresh Interrupt Flag */ #define DSI_WIFCR_CPLLLIF_Pos (9U) #define DSI_WIFCR_CPLLLIF_Msk (0x1U << DSI_WIFCR_CPLLLIF_Pos) /*!< 0x00000200 */ #define DSI_WIFCR_CPLLLIF DSI_WIFCR_CPLLLIF_Msk /*!< Clear PLL Lock Interrupt Flag */ #define DSI_WIFCR_CPLLUIF_Pos (10U) #define DSI_WIFCR_CPLLUIF_Msk (0x1U << DSI_WIFCR_CPLLUIF_Pos) /*!< 0x00000400 */ #define DSI_WIFCR_CPLLUIF DSI_WIFCR_CPLLUIF_Msk /*!< Clear PLL Unlock Interrupt Flag */ #define DSI_WIFCR_CRRIF_Pos (13U) #define DSI_WIFCR_CRRIF_Msk (0x1U << DSI_WIFCR_CRRIF_Pos) /*!< 0x00002000 */ #define DSI_WIFCR_CRRIF DSI_WIFCR_CRRIF_Msk /*!< Clear Regulator Ready Interrupt Flag */ /******************* Bit definition for DSI_WPCR0 register ***************/ #define DSI_WPCR0_UIX4_Pos (0U) #define DSI_WPCR0_UIX4_Msk (0x3FU << DSI_WPCR0_UIX4_Pos) /*!< 0x0000003F */ #define DSI_WPCR0_UIX4 DSI_WPCR0_UIX4_Msk /*!< Unit Interval multiplied by 4 */ #define DSI_WPCR0_UIX4_0 (0x01U << DSI_WPCR0_UIX4_Pos) /*!< 0x00000001 */ #define DSI_WPCR0_UIX4_1 (0x02U << DSI_WPCR0_UIX4_Pos) /*!< 0x00000002 */ #define DSI_WPCR0_UIX4_2 (0x04U << DSI_WPCR0_UIX4_Pos) /*!< 0x00000004 */ #define DSI_WPCR0_UIX4_3 (0x08U << DSI_WPCR0_UIX4_Pos) /*!< 0x00000008 */ #define DSI_WPCR0_UIX4_4 (0x10U << DSI_WPCR0_UIX4_Pos) /*!< 0x00000010 */ #define DSI_WPCR0_UIX4_5 (0x20U << DSI_WPCR0_UIX4_Pos) /*!< 0x00000020 */ #define DSI_WPCR0_SWCL_Pos (6U) #define DSI_WPCR0_SWCL_Msk (0x1U << DSI_WPCR0_SWCL_Pos) /*!< 0x00000040 */ #define DSI_WPCR0_SWCL DSI_WPCR0_SWCL_Msk /*!< Swap pins on clock lane */ #define DSI_WPCR0_SWDL0_Pos (7U) #define DSI_WPCR0_SWDL0_Msk (0x1U << DSI_WPCR0_SWDL0_Pos) /*!< 0x00000080 */ #define DSI_WPCR0_SWDL0 DSI_WPCR0_SWDL0_Msk /*!< Swap pins on data lane 1 */ #define DSI_WPCR0_SWDL1_Pos (8U) #define DSI_WPCR0_SWDL1_Msk (0x1U << DSI_WPCR0_SWDL1_Pos) /*!< 0x00000100 */ #define DSI_WPCR0_SWDL1 DSI_WPCR0_SWDL1_Msk /*!< Swap pins on data lane 2 */ #define DSI_WPCR0_HSICL_Pos (9U) #define DSI_WPCR0_HSICL_Msk (0x1U << DSI_WPCR0_HSICL_Pos) /*!< 0x00000200 */ #define DSI_WPCR0_HSICL DSI_WPCR0_HSICL_Msk /*!< Invert the high-speed data signal on clock lane */ #define DSI_WPCR0_HSIDL0_Pos (10U) #define DSI_WPCR0_HSIDL0_Msk (0x1U << DSI_WPCR0_HSIDL0_Pos) /*!< 0x00000400 */ #define DSI_WPCR0_HSIDL0 DSI_WPCR0_HSIDL0_Msk /*!< Invert the high-speed data signal on lane 1 */ #define DSI_WPCR0_HSIDL1_Pos (11U) #define DSI_WPCR0_HSIDL1_Msk (0x1U << DSI_WPCR0_HSIDL1_Pos) /*!< 0x00000800 */ #define DSI_WPCR0_HSIDL1 DSI_WPCR0_HSIDL1_Msk /*!< Invert the high-speed data signal on lane 2 */ #define DSI_WPCR0_FTXSMCL_Pos (12U) #define DSI_WPCR0_FTXSMCL_Msk (0x1U << DSI_WPCR0_FTXSMCL_Pos) /*!< 0x00001000 */ #define DSI_WPCR0_FTXSMCL DSI_WPCR0_FTXSMCL_Msk /*!< Force clock lane in TX stop mode */ #define DSI_WPCR0_FTXSMDL_Pos (13U) #define DSI_WPCR0_FTXSMDL_Msk (0x1U << DSI_WPCR0_FTXSMDL_Pos) /*!< 0x00002000 */ #define DSI_WPCR0_FTXSMDL DSI_WPCR0_FTXSMDL_Msk /*!< Force data lanes in TX stop mode */ #define DSI_WPCR0_CDOFFDL_Pos (14U) #define DSI_WPCR0_CDOFFDL_Msk (0x1U << DSI_WPCR0_CDOFFDL_Pos) /*!< 0x00004000 */ #define DSI_WPCR0_CDOFFDL DSI_WPCR0_CDOFFDL_Msk /*!< Contention detection OFF */ #define DSI_WPCR0_TDDL_Pos (16U) #define DSI_WPCR0_TDDL_Msk (0x1U << DSI_WPCR0_TDDL_Pos) /*!< 0x00010000 */ #define DSI_WPCR0_TDDL DSI_WPCR0_TDDL_Msk /*!< Turn Disable Data Lanes */ #define DSI_WPCR0_PDEN_Pos (18U) #define DSI_WPCR0_PDEN_Msk (0x1U << DSI_WPCR0_PDEN_Pos) /*!< 0x00040000 */ #define DSI_WPCR0_PDEN DSI_WPCR0_PDEN_Msk /*!< Pull-Down Enable */ #define DSI_WPCR0_TCLKPREPEN_Pos (19U) #define DSI_WPCR0_TCLKPREPEN_Msk (0x1U << DSI_WPCR0_TCLKPREPEN_Pos) /*!< 0x00080000 */ #define DSI_WPCR0_TCLKPREPEN DSI_WPCR0_TCLKPREPEN_Msk /*!< Timer for t-CLKPREP Enable */ #define DSI_WPCR0_TCLKZEROEN_Pos (20U) #define DSI_WPCR0_TCLKZEROEN_Msk (0x1U << DSI_WPCR0_TCLKZEROEN_Pos) /*!< 0x00100000 */ #define DSI_WPCR0_TCLKZEROEN DSI_WPCR0_TCLKZEROEN_Msk /*!< Timer for t-CLKZERO Enable */ #define DSI_WPCR0_THSPREPEN_Pos (21U) #define DSI_WPCR0_THSPREPEN_Msk (0x1U << DSI_WPCR0_THSPREPEN_Pos) /*!< 0x00200000 */ #define DSI_WPCR0_THSPREPEN DSI_WPCR0_THSPREPEN_Msk /*!< Timer for t-HSPREP Enable */ #define DSI_WPCR0_THSTRAILEN_Pos (22U) #define DSI_WPCR0_THSTRAILEN_Msk (0x1U << DSI_WPCR0_THSTRAILEN_Pos) /*!< 0x00400000 */ #define DSI_WPCR0_THSTRAILEN DSI_WPCR0_THSTRAILEN_Msk /*!< Timer for t-HSTRAIL Enable */ #define DSI_WPCR0_THSZEROEN_Pos (23U) #define DSI_WPCR0_THSZEROEN_Msk (0x1U << DSI_WPCR0_THSZEROEN_Pos) /*!< 0x00800000 */ #define DSI_WPCR0_THSZEROEN DSI_WPCR0_THSZEROEN_Msk /*!< Timer for t-HSZERO Enable */ #define DSI_WPCR0_TLPXDEN_Pos (24U) #define DSI_WPCR0_TLPXDEN_Msk (0x1U << DSI_WPCR0_TLPXDEN_Pos) /*!< 0x01000000 */ #define DSI_WPCR0_TLPXDEN DSI_WPCR0_TLPXDEN_Msk /*!< Timer for t-LPXD Enable */ #define DSI_WPCR0_THSEXITEN_Pos (25U) #define DSI_WPCR0_THSEXITEN_Msk (0x1U << DSI_WPCR0_THSEXITEN_Pos) /*!< 0x02000000 */ #define DSI_WPCR0_THSEXITEN DSI_WPCR0_THSEXITEN_Msk /*!< Timer for t-HSEXIT Enable */ #define DSI_WPCR0_TLPXCEN_Pos (26U) #define DSI_WPCR0_TLPXCEN_Msk (0x1U << DSI_WPCR0_TLPXCEN_Pos) /*!< 0x04000000 */ #define DSI_WPCR0_TLPXCEN DSI_WPCR0_TLPXCEN_Msk /*!< Timer for t-LPXC Enable */ #define DSI_WPCR0_TCLKPOSTEN_Pos (27U) #define DSI_WPCR0_TCLKPOSTEN_Msk (0x1U << DSI_WPCR0_TCLKPOSTEN_Pos) /*!< 0x08000000 */ #define DSI_WPCR0_TCLKPOSTEN DSI_WPCR0_TCLKPOSTEN_Msk /*!< Timer for t-CLKPOST Enable */ /******************* Bit definition for DSI_WPCR1 register ***************/ #define DSI_WPCR1_HSTXDCL_Pos (0U) #define DSI_WPCR1_HSTXDCL_Msk (0x3U << DSI_WPCR1_HSTXDCL_Pos) /*!< 0x00000003 */ #define DSI_WPCR1_HSTXDCL DSI_WPCR1_HSTXDCL_Msk /*!< High-Speed Transmission Delay on Clock Lane */ #define DSI_WPCR1_HSTXDCL0_Pos (0U) #define DSI_WPCR1_HSTXDCL0_Msk (0x1U << DSI_WPCR1_HSTXDCL0_Pos) /*!< 0x00000001 */ #define DSI_WPCR1_HSTXDCL0 DSI_WPCR1_HSTXDCL0_Msk #define DSI_WPCR1_HSTXDCL1_Pos (1U) #define DSI_WPCR1_HSTXDCL1_Msk (0x1U << DSI_WPCR1_HSTXDCL1_Pos) /*!< 0x00000002 */ #define DSI_WPCR1_HSTXDCL1 DSI_WPCR1_HSTXDCL1_Msk #define DSI_WPCR1_HSTXDDL_Pos (2U) #define DSI_WPCR1_HSTXDDL_Msk (0x3U << DSI_WPCR1_HSTXDDL_Pos) /*!< 0x0000000C */ #define DSI_WPCR1_HSTXDDL DSI_WPCR1_HSTXDDL_Msk /*!< High-Speed Transmission Delay on Data Lane */ #define DSI_WPCR1_HSTXDDL0_Pos (2U) #define DSI_WPCR1_HSTXDDL0_Msk (0x1U << DSI_WPCR1_HSTXDDL0_Pos) /*!< 0x00000004 */ #define DSI_WPCR1_HSTXDDL0 DSI_WPCR1_HSTXDDL0_Msk #define DSI_WPCR1_HSTXDDL1_Pos (3U) #define DSI_WPCR1_HSTXDDL1_Msk (0x1U << DSI_WPCR1_HSTXDDL1_Pos) /*!< 0x00000008 */ #define DSI_WPCR1_HSTXDDL1 DSI_WPCR1_HSTXDDL1_Msk #define DSI_WPCR1_LPSRCCL_Pos (6U) #define DSI_WPCR1_LPSRCCL_Msk (0x3U << DSI_WPCR1_LPSRCCL_Pos) /*!< 0x000000C0 */ #define DSI_WPCR1_LPSRCCL DSI_WPCR1_LPSRCCL_Msk /*!< Low-Power transmission Slew Rate Compensation on Clock Lane */ #define DSI_WPCR1_LPSRCCL0_Pos (6U) #define DSI_WPCR1_LPSRCCL0_Msk (0x1U << DSI_WPCR1_LPSRCCL0_Pos) /*!< 0x00000040 */ #define DSI_WPCR1_LPSRCCL0 DSI_WPCR1_LPSRCCL0_Msk #define DSI_WPCR1_LPSRCCL1_Pos (7U) #define DSI_WPCR1_LPSRCCL1_Msk (0x1U << DSI_WPCR1_LPSRCCL1_Pos) /*!< 0x00000080 */ #define DSI_WPCR1_LPSRCCL1 DSI_WPCR1_LPSRCCL1_Msk #define DSI_WPCR1_LPSRCDL_Pos (8U) #define DSI_WPCR1_LPSRCDL_Msk (0x3U << DSI_WPCR1_LPSRCDL_Pos) /*!< 0x00000300 */ #define DSI_WPCR1_LPSRCDL DSI_WPCR1_LPSRCDL_Msk /*!< Low-Power transmission Slew Rate Compensation on Data Lane */ #define DSI_WPCR1_LPSRCDL0_Pos (8U) #define DSI_WPCR1_LPSRCDL0_Msk (0x1U << DSI_WPCR1_LPSRCDL0_Pos) /*!< 0x00000100 */ #define DSI_WPCR1_LPSRCDL0 DSI_WPCR1_LPSRCDL0_Msk #define DSI_WPCR1_LPSRCDL1_Pos (9U) #define DSI_WPCR1_LPSRCDL1_Msk (0x1U << DSI_WPCR1_LPSRCDL1_Pos) /*!< 0x00000200 */ #define DSI_WPCR1_LPSRCDL1 DSI_WPCR1_LPSRCDL1_Msk #define DSI_WPCR1_SDDC_Pos (12U) #define DSI_WPCR1_SDDC_Msk (0x1U << DSI_WPCR1_SDDC_Pos) /*!< 0x00001000 */ #define DSI_WPCR1_SDDC DSI_WPCR1_SDDC_Msk /*!< SDD Control */ #define DSI_WPCR1_LPRXVCDL_Pos (14U) #define DSI_WPCR1_LPRXVCDL_Msk (0x3U << DSI_WPCR1_LPRXVCDL_Pos) /*!< 0x0000C000 */ #define DSI_WPCR1_LPRXVCDL DSI_WPCR1_LPRXVCDL_Msk /*!< Low-Power Reception V-IL Compensation on Data Lanes */ #define DSI_WPCR1_LPRXVCDL0_Pos (14U) #define DSI_WPCR1_LPRXVCDL0_Msk (0x1U << DSI_WPCR1_LPRXVCDL0_Pos) /*!< 0x00004000 */ #define DSI_WPCR1_LPRXVCDL0 DSI_WPCR1_LPRXVCDL0_Msk #define DSI_WPCR1_LPRXVCDL1_Pos (15U) #define DSI_WPCR1_LPRXVCDL1_Msk (0x1U << DSI_WPCR1_LPRXVCDL1_Pos) /*!< 0x00008000 */ #define DSI_WPCR1_LPRXVCDL1 DSI_WPCR1_LPRXVCDL1_Msk #define DSI_WPCR1_HSTXSRCCL_Pos (16U) #define DSI_WPCR1_HSTXSRCCL_Msk (0x3U << DSI_WPCR1_HSTXSRCCL_Pos) /*!< 0x00030000 */ #define DSI_WPCR1_HSTXSRCCL DSI_WPCR1_HSTXSRCCL_Msk /*!< High-Speed Transmission Delay on Clock Lane */ #define DSI_WPCR1_HSTXSRCCL0_Pos (16U) #define DSI_WPCR1_HSTXSRCCL0_Msk (0x1U << DSI_WPCR1_HSTXSRCCL0_Pos) /*!< 0x00010000 */ #define DSI_WPCR1_HSTXSRCCL0 DSI_WPCR1_HSTXSRCCL0_Msk #define DSI_WPCR1_HSTXSRCCL1_Pos (17U) #define DSI_WPCR1_HSTXSRCCL1_Msk (0x1U << DSI_WPCR1_HSTXSRCCL1_Pos) /*!< 0x00020000 */ #define DSI_WPCR1_HSTXSRCCL1 DSI_WPCR1_HSTXSRCCL1_Msk #define DSI_WPCR1_HSTXSRCDL_Pos (18U) #define DSI_WPCR1_HSTXSRCDL_Msk (0x3U << DSI_WPCR1_HSTXSRCDL_Pos) /*!< 0x000C0000 */ #define DSI_WPCR1_HSTXSRCDL DSI_WPCR1_HSTXSRCDL_Msk /*!< High-Speed Transmission Delay on Data Lane */ #define DSI_WPCR1_HSTXSRCDL0_Pos (18U) #define DSI_WPCR1_HSTXSRCDL0_Msk (0x1U << DSI_WPCR1_HSTXSRCDL0_Pos) /*!< 0x00040000 */ #define DSI_WPCR1_HSTXSRCDL0 DSI_WPCR1_HSTXSRCDL0_Msk #define DSI_WPCR1_HSTXSRCDL1_Pos (19U) #define DSI_WPCR1_HSTXSRCDL1_Msk (0x1U << DSI_WPCR1_HSTXSRCDL1_Pos) /*!< 0x00080000 */ #define DSI_WPCR1_HSTXSRCDL1 DSI_WPCR1_HSTXSRCDL1_Msk #define DSI_WPCR1_FLPRXLPM_Pos (22U) #define DSI_WPCR1_FLPRXLPM_Msk (0x1U << DSI_WPCR1_FLPRXLPM_Pos) /*!< 0x00400000 */ #define DSI_WPCR1_FLPRXLPM DSI_WPCR1_FLPRXLPM_Msk /*!< Forces LP Receiver in Low-Power Mode */ #define DSI_WPCR1_LPRXFT_Pos (25U) #define DSI_WPCR1_LPRXFT_Msk (0x3U << DSI_WPCR1_LPRXFT_Pos) /*!< 0x06000000 */ #define DSI_WPCR1_LPRXFT DSI_WPCR1_LPRXFT_Msk /*!< Low-Power RX low-pass Filtering Tuning */ #define DSI_WPCR1_LPRXFT0_Pos (25U) #define DSI_WPCR1_LPRXFT0_Msk (0x1U << DSI_WPCR1_LPRXFT0_Pos) /*!< 0x02000000 */ #define DSI_WPCR1_LPRXFT0 DSI_WPCR1_LPRXFT0_Msk #define DSI_WPCR1_LPRXFT1_Pos (26U) #define DSI_WPCR1_LPRXFT1_Msk (0x1U << DSI_WPCR1_LPRXFT1_Pos) /*!< 0x04000000 */ #define DSI_WPCR1_LPRXFT1 DSI_WPCR1_LPRXFT1_Msk /******************* Bit definition for DSI_WPCR2 register ***************/ #define DSI_WPCR2_TCLKPREP_Pos (0U) #define DSI_WPCR2_TCLKPREP_Msk (0xFFU << DSI_WPCR2_TCLKPREP_Pos) /*!< 0x000000FF */ #define DSI_WPCR2_TCLKPREP DSI_WPCR2_TCLKPREP_Msk /*!< t-CLKPREP */ #define DSI_WPCR2_TCLKPREP0_Pos (0U) #define DSI_WPCR2_TCLKPREP0_Msk (0x1U << DSI_WPCR2_TCLKPREP0_Pos) /*!< 0x00000001 */ #define DSI_WPCR2_TCLKPREP0 DSI_WPCR2_TCLKPREP0_Msk #define DSI_WPCR2_TCLKPREP1_Pos (1U) #define DSI_WPCR2_TCLKPREP1_Msk (0x1U << DSI_WPCR2_TCLKPREP1_Pos) /*!< 0x00000002 */ #define DSI_WPCR2_TCLKPREP1 DSI_WPCR2_TCLKPREP1_Msk #define DSI_WPCR2_TCLKPREP2_Pos (2U) #define DSI_WPCR2_TCLKPREP2_Msk (0x1U << DSI_WPCR2_TCLKPREP2_Pos) /*!< 0x00000004 */ #define DSI_WPCR2_TCLKPREP2 DSI_WPCR2_TCLKPREP2_Msk #define DSI_WPCR2_TCLKPREP3_Pos (3U) #define DSI_WPCR2_TCLKPREP3_Msk (0x1U << DSI_WPCR2_TCLKPREP3_Pos) /*!< 0x00000008 */ #define DSI_WPCR2_TCLKPREP3 DSI_WPCR2_TCLKPREP3_Msk #define DSI_WPCR2_TCLKPREP4_Pos (4U) #define DSI_WPCR2_TCLKPREP4_Msk (0x1U << DSI_WPCR2_TCLKPREP4_Pos) /*!< 0x00000010 */ #define DSI_WPCR2_TCLKPREP4 DSI_WPCR2_TCLKPREP4_Msk #define DSI_WPCR2_TCLKPREP5_Pos (5U) #define DSI_WPCR2_TCLKPREP5_Msk (0x1U << DSI_WPCR2_TCLKPREP5_Pos) /*!< 0x00000020 */ #define DSI_WPCR2_TCLKPREP5 DSI_WPCR2_TCLKPREP5_Msk #define DSI_WPCR2_TCLKPREP6_Pos (6U) #define DSI_WPCR2_TCLKPREP6_Msk (0x1U << DSI_WPCR2_TCLKPREP6_Pos) /*!< 0x00000040 */ #define DSI_WPCR2_TCLKPREP6 DSI_WPCR2_TCLKPREP6_Msk #define DSI_WPCR2_TCLKPREP7_Pos (7U) #define DSI_WPCR2_TCLKPREP7_Msk (0x1U << DSI_WPCR2_TCLKPREP7_Pos) /*!< 0x00000080 */ #define DSI_WPCR2_TCLKPREP7 DSI_WPCR2_TCLKPREP7_Msk #define DSI_WPCR2_TCLKZERO_Pos (8U) #define DSI_WPCR2_TCLKZERO_Msk (0xFFU << DSI_WPCR2_TCLKZERO_Pos) /*!< 0x0000FF00 */ #define DSI_WPCR2_TCLKZERO DSI_WPCR2_TCLKZERO_Msk /*!< t-CLKZERO */ #define DSI_WPCR2_TCLKZERO0_Pos (8U) #define DSI_WPCR2_TCLKZERO0_Msk (0x1U << DSI_WPCR2_TCLKZERO0_Pos) /*!< 0x00000100 */ #define DSI_WPCR2_TCLKZERO0 DSI_WPCR2_TCLKZERO0_Msk #define DSI_WPCR2_TCLKZERO1_Pos (9U) #define DSI_WPCR2_TCLKZERO1_Msk (0x1U << DSI_WPCR2_TCLKZERO1_Pos) /*!< 0x00000200 */ #define DSI_WPCR2_TCLKZERO1 DSI_WPCR2_TCLKZERO1_Msk #define DSI_WPCR2_TCLKZERO2_Pos (10U) #define DSI_WPCR2_TCLKZERO2_Msk (0x1U << DSI_WPCR2_TCLKZERO2_Pos) /*!< 0x00000400 */ #define DSI_WPCR2_TCLKZERO2 DSI_WPCR2_TCLKZERO2_Msk #define DSI_WPCR2_TCLKZERO3_Pos (11U) #define DSI_WPCR2_TCLKZERO3_Msk (0x1U << DSI_WPCR2_TCLKZERO3_Pos) /*!< 0x00000800 */ #define DSI_WPCR2_TCLKZERO3 DSI_WPCR2_TCLKZERO3_Msk #define DSI_WPCR2_TCLKZERO4_Pos (12U) #define DSI_WPCR2_TCLKZERO4_Msk (0x1U << DSI_WPCR2_TCLKZERO4_Pos) /*!< 0x00001000 */ #define DSI_WPCR2_TCLKZERO4 DSI_WPCR2_TCLKZERO4_Msk #define DSI_WPCR2_TCLKZERO5_Pos (13U) #define DSI_WPCR2_TCLKZERO5_Msk (0x1U << DSI_WPCR2_TCLKZERO5_Pos) /*!< 0x00002000 */ #define DSI_WPCR2_TCLKZERO5 DSI_WPCR2_TCLKZERO5_Msk #define DSI_WPCR2_TCLKZERO6_Pos (14U) #define DSI_WPCR2_TCLKZERO6_Msk (0x1U << DSI_WPCR2_TCLKZERO6_Pos) /*!< 0x00004000 */ #define DSI_WPCR2_TCLKZERO6 DSI_WPCR2_TCLKZERO6_Msk #define DSI_WPCR2_TCLKZERO7_Pos (15U) #define DSI_WPCR2_TCLKZERO7_Msk (0x1U << DSI_WPCR2_TCLKZERO7_Pos) /*!< 0x00008000 */ #define DSI_WPCR2_TCLKZERO7 DSI_WPCR2_TCLKZERO7_Msk #define DSI_WPCR2_THSPREP_Pos (16U) #define DSI_WPCR2_THSPREP_Msk (0xFFU << DSI_WPCR2_THSPREP_Pos) /*!< 0x00FF0000 */ #define DSI_WPCR2_THSPREP DSI_WPCR2_THSPREP_Msk /*!< t-HSPREP */ #define DSI_WPCR2_THSPREP0_Pos (16U) #define DSI_WPCR2_THSPREP0_Msk (0x1U << DSI_WPCR2_THSPREP0_Pos) /*!< 0x00010000 */ #define DSI_WPCR2_THSPREP0 DSI_WPCR2_THSPREP0_Msk #define DSI_WPCR2_THSPREP1_Pos (17U) #define DSI_WPCR2_THSPREP1_Msk (0x1U << DSI_WPCR2_THSPREP1_Pos) /*!< 0x00020000 */ #define DSI_WPCR2_THSPREP1 DSI_WPCR2_THSPREP1_Msk #define DSI_WPCR2_THSPREP2_Pos (18U) #define DSI_WPCR2_THSPREP2_Msk (0x1U << DSI_WPCR2_THSPREP2_Pos) /*!< 0x00040000 */ #define DSI_WPCR2_THSPREP2 DSI_WPCR2_THSPREP2_Msk #define DSI_WPCR2_THSPREP3_Pos (19U) #define DSI_WPCR2_THSPREP3_Msk (0x1U << DSI_WPCR2_THSPREP3_Pos) /*!< 0x00080000 */ #define DSI_WPCR2_THSPREP3 DSI_WPCR2_THSPREP3_Msk #define DSI_WPCR2_THSPREP4_Pos (20U) #define DSI_WPCR2_THSPREP4_Msk (0x1U << DSI_WPCR2_THSPREP4_Pos) /*!< 0x00100000 */ #define DSI_WPCR2_THSPREP4 DSI_WPCR2_THSPREP4_Msk #define DSI_WPCR2_THSPREP5_Pos (21U) #define DSI_WPCR2_THSPREP5_Msk (0x1U << DSI_WPCR2_THSPREP5_Pos) /*!< 0x00200000 */ #define DSI_WPCR2_THSPREP5 DSI_WPCR2_THSPREP5_Msk #define DSI_WPCR2_THSPREP6_Pos (22U) #define DSI_WPCR2_THSPREP6_Msk (0x1U << DSI_WPCR2_THSPREP6_Pos) /*!< 0x00400000 */ #define DSI_WPCR2_THSPREP6 DSI_WPCR2_THSPREP6_Msk #define DSI_WPCR2_THSPREP7_Pos (23U) #define DSI_WPCR2_THSPREP7_Msk (0x1U << DSI_WPCR2_THSPREP7_Pos) /*!< 0x00800000 */ #define DSI_WPCR2_THSPREP7 DSI_WPCR2_THSPREP7_Msk #define DSI_WPCR2_THSTRAIL_Pos (24U) #define DSI_WPCR2_THSTRAIL_Msk (0xFFU << DSI_WPCR2_THSTRAIL_Pos) /*!< 0xFF000000 */ #define DSI_WPCR2_THSTRAIL DSI_WPCR2_THSTRAIL_Msk /*!< t-HSTRAIL */ #define DSI_WPCR2_THSTRAIL0_Pos (24U) #define DSI_WPCR2_THSTRAIL0_Msk (0x1U << DSI_WPCR2_THSTRAIL0_Pos) /*!< 0x01000000 */ #define DSI_WPCR2_THSTRAIL0 DSI_WPCR2_THSTRAIL0_Msk #define DSI_WPCR2_THSTRAIL1_Pos (25U) #define DSI_WPCR2_THSTRAIL1_Msk (0x1U << DSI_WPCR2_THSTRAIL1_Pos) /*!< 0x02000000 */ #define DSI_WPCR2_THSTRAIL1 DSI_WPCR2_THSTRAIL1_Msk #define DSI_WPCR2_THSTRAIL2_Pos (26U) #define DSI_WPCR2_THSTRAIL2_Msk (0x1U << DSI_WPCR2_THSTRAIL2_Pos) /*!< 0x04000000 */ #define DSI_WPCR2_THSTRAIL2 DSI_WPCR2_THSTRAIL2_Msk #define DSI_WPCR2_THSTRAIL3_Pos (27U) #define DSI_WPCR2_THSTRAIL3_Msk (0x1U << DSI_WPCR2_THSTRAIL3_Pos) /*!< 0x08000000 */ #define DSI_WPCR2_THSTRAIL3 DSI_WPCR2_THSTRAIL3_Msk #define DSI_WPCR2_THSTRAIL4_Pos (28U) #define DSI_WPCR2_THSTRAIL4_Msk (0x1U << DSI_WPCR2_THSTRAIL4_Pos) /*!< 0x10000000 */ #define DSI_WPCR2_THSTRAIL4 DSI_WPCR2_THSTRAIL4_Msk #define DSI_WPCR2_THSTRAIL5_Pos (29U) #define DSI_WPCR2_THSTRAIL5_Msk (0x1U << DSI_WPCR2_THSTRAIL5_Pos) /*!< 0x20000000 */ #define DSI_WPCR2_THSTRAIL5 DSI_WPCR2_THSTRAIL5_Msk #define DSI_WPCR2_THSTRAIL6_Pos (30U) #define DSI_WPCR2_THSTRAIL6_Msk (0x1U << DSI_WPCR2_THSTRAIL6_Pos) /*!< 0x40000000 */ #define DSI_WPCR2_THSTRAIL6 DSI_WPCR2_THSTRAIL6_Msk #define DSI_WPCR2_THSTRAIL7_Pos (31U) #define DSI_WPCR2_THSTRAIL7_Msk (0x1U << DSI_WPCR2_THSTRAIL7_Pos) /*!< 0x80000000 */ #define DSI_WPCR2_THSTRAIL7 DSI_WPCR2_THSTRAIL7_Msk /******************* Bit definition for DSI_WPCR3 register ***************/ #define DSI_WPCR3_THSZERO_Pos (0U) #define DSI_WPCR3_THSZERO_Msk (0xFFU << DSI_WPCR3_THSZERO_Pos) /*!< 0x000000FF */ #define DSI_WPCR3_THSZERO DSI_WPCR3_THSZERO_Msk /*!< t-HSZERO */ #define DSI_WPCR3_THSZERO0_Pos (0U) #define DSI_WPCR3_THSZERO0_Msk (0x1U << DSI_WPCR3_THSZERO0_Pos) /*!< 0x00000001 */ #define DSI_WPCR3_THSZERO0 DSI_WPCR3_THSZERO0_Msk #define DSI_WPCR3_THSZERO1_Pos (1U) #define DSI_WPCR3_THSZERO1_Msk (0x1U << DSI_WPCR3_THSZERO1_Pos) /*!< 0x00000002 */ #define DSI_WPCR3_THSZERO1 DSI_WPCR3_THSZERO1_Msk #define DSI_WPCR3_THSZERO2_Pos (2U) #define DSI_WPCR3_THSZERO2_Msk (0x1U << DSI_WPCR3_THSZERO2_Pos) /*!< 0x00000004 */ #define DSI_WPCR3_THSZERO2 DSI_WPCR3_THSZERO2_Msk #define DSI_WPCR3_THSZERO3_Pos (3U) #define DSI_WPCR3_THSZERO3_Msk (0x1U << DSI_WPCR3_THSZERO3_Pos) /*!< 0x00000008 */ #define DSI_WPCR3_THSZERO3 DSI_WPCR3_THSZERO3_Msk #define DSI_WPCR3_THSZERO4_Pos (4U) #define DSI_WPCR3_THSZERO4_Msk (0x1U << DSI_WPCR3_THSZERO4_Pos) /*!< 0x00000010 */ #define DSI_WPCR3_THSZERO4 DSI_WPCR3_THSZERO4_Msk #define DSI_WPCR3_THSZERO5_Pos (5U) #define DSI_WPCR3_THSZERO5_Msk (0x1U << DSI_WPCR3_THSZERO5_Pos) /*!< 0x00000020 */ #define DSI_WPCR3_THSZERO5 DSI_WPCR3_THSZERO5_Msk #define DSI_WPCR3_THSZERO6_Pos (6U) #define DSI_WPCR3_THSZERO6_Msk (0x1U << DSI_WPCR3_THSZERO6_Pos) /*!< 0x00000040 */ #define DSI_WPCR3_THSZERO6 DSI_WPCR3_THSZERO6_Msk #define DSI_WPCR3_THSZERO7_Pos (7U) #define DSI_WPCR3_THSZERO7_Msk (0x1U << DSI_WPCR3_THSZERO7_Pos) /*!< 0x00000080 */ #define DSI_WPCR3_THSZERO7 DSI_WPCR3_THSZERO7_Msk #define DSI_WPCR3_TLPXD_Pos (8U) #define DSI_WPCR3_TLPXD_Msk (0xFFU << DSI_WPCR3_TLPXD_Pos) /*!< 0x0000FF00 */ #define DSI_WPCR3_TLPXD DSI_WPCR3_TLPXD_Msk /*!< t-LPXD */ #define DSI_WPCR3_TLPXD0_Pos (8U) #define DSI_WPCR3_TLPXD0_Msk (0x1U << DSI_WPCR3_TLPXD0_Pos) /*!< 0x00000100 */ #define DSI_WPCR3_TLPXD0 DSI_WPCR3_TLPXD0_Msk #define DSI_WPCR3_TLPXD1_Pos (9U) #define DSI_WPCR3_TLPXD1_Msk (0x1U << DSI_WPCR3_TLPXD1_Pos) /*!< 0x00000200 */ #define DSI_WPCR3_TLPXD1 DSI_WPCR3_TLPXD1_Msk #define DSI_WPCR3_TLPXD2_Pos (10U) #define DSI_WPCR3_TLPXD2_Msk (0x1U << DSI_WPCR3_TLPXD2_Pos) /*!< 0x00000400 */ #define DSI_WPCR3_TLPXD2 DSI_WPCR3_TLPXD2_Msk #define DSI_WPCR3_TLPXD3_Pos (11U) #define DSI_WPCR3_TLPXD3_Msk (0x1U << DSI_WPCR3_TLPXD3_Pos) /*!< 0x00000800 */ #define DSI_WPCR3_TLPXD3 DSI_WPCR3_TLPXD3_Msk #define DSI_WPCR3_TLPXD4_Pos (12U) #define DSI_WPCR3_TLPXD4_Msk (0x1U << DSI_WPCR3_TLPXD4_Pos) /*!< 0x00001000 */ #define DSI_WPCR3_TLPXD4 DSI_WPCR3_TLPXD4_Msk #define DSI_WPCR3_TLPXD5_Pos (13U) #define DSI_WPCR3_TLPXD5_Msk (0x1U << DSI_WPCR3_TLPXD5_Pos) /*!< 0x00002000 */ #define DSI_WPCR3_TLPXD5 DSI_WPCR3_TLPXD5_Msk #define DSI_WPCR3_TLPXD6_Pos (14U) #define DSI_WPCR3_TLPXD6_Msk (0x1U << DSI_WPCR3_TLPXD6_Pos) /*!< 0x00004000 */ #define DSI_WPCR3_TLPXD6 DSI_WPCR3_TLPXD6_Msk #define DSI_WPCR3_TLPXD7_Pos (15U) #define DSI_WPCR3_TLPXD7_Msk (0x1U << DSI_WPCR3_TLPXD7_Pos) /*!< 0x00008000 */ #define DSI_WPCR3_TLPXD7 DSI_WPCR3_TLPXD7_Msk #define DSI_WPCR3_THSEXIT_Pos (16U) #define DSI_WPCR3_THSEXIT_Msk (0xFFU << DSI_WPCR3_THSEXIT_Pos) /*!< 0x00FF0000 */ #define DSI_WPCR3_THSEXIT DSI_WPCR3_THSEXIT_Msk /*!< t-HSEXIT */ #define DSI_WPCR3_THSEXIT0_Pos (16U) #define DSI_WPCR3_THSEXIT0_Msk (0x1U << DSI_WPCR3_THSEXIT0_Pos) /*!< 0x00010000 */ #define DSI_WPCR3_THSEXIT0 DSI_WPCR3_THSEXIT0_Msk #define DSI_WPCR3_THSEXIT1_Pos (17U) #define DSI_WPCR3_THSEXIT1_Msk (0x1U << DSI_WPCR3_THSEXIT1_Pos) /*!< 0x00020000 */ #define DSI_WPCR3_THSEXIT1 DSI_WPCR3_THSEXIT1_Msk #define DSI_WPCR3_THSEXIT2_Pos (18U) #define DSI_WPCR3_THSEXIT2_Msk (0x1U << DSI_WPCR3_THSEXIT2_Pos) /*!< 0x00040000 */ #define DSI_WPCR3_THSEXIT2 DSI_WPCR3_THSEXIT2_Msk #define DSI_WPCR3_THSEXIT3_Pos (19U) #define DSI_WPCR3_THSEXIT3_Msk (0x1U << DSI_WPCR3_THSEXIT3_Pos) /*!< 0x00080000 */ #define DSI_WPCR3_THSEXIT3 DSI_WPCR3_THSEXIT3_Msk #define DSI_WPCR3_THSEXIT4_Pos (20U) #define DSI_WPCR3_THSEXIT4_Msk (0x1U << DSI_WPCR3_THSEXIT4_Pos) /*!< 0x00100000 */ #define DSI_WPCR3_THSEXIT4 DSI_WPCR3_THSEXIT4_Msk #define DSI_WPCR3_THSEXIT5_Pos (21U) #define DSI_WPCR3_THSEXIT5_Msk (0x1U << DSI_WPCR3_THSEXIT5_Pos) /*!< 0x00200000 */ #define DSI_WPCR3_THSEXIT5 DSI_WPCR3_THSEXIT5_Msk #define DSI_WPCR3_THSEXIT6_Pos (22U) #define DSI_WPCR3_THSEXIT6_Msk (0x1U << DSI_WPCR3_THSEXIT6_Pos) /*!< 0x00400000 */ #define DSI_WPCR3_THSEXIT6 DSI_WPCR3_THSEXIT6_Msk #define DSI_WPCR3_THSEXIT7_Pos (23U) #define DSI_WPCR3_THSEXIT7_Msk (0x1U << DSI_WPCR3_THSEXIT7_Pos) /*!< 0x00800000 */ #define DSI_WPCR3_THSEXIT7 DSI_WPCR3_THSEXIT7_Msk #define DSI_WPCR3_TLPXC_Pos (24U) #define DSI_WPCR3_TLPXC_Msk (0xFFU << DSI_WPCR3_TLPXC_Pos) /*!< 0xFF000000 */ #define DSI_WPCR3_TLPXC DSI_WPCR3_TLPXC_Msk /*!< t-LPXC */ #define DSI_WPCR3_TLPXC0_Pos (24U) #define DSI_WPCR3_TLPXC0_Msk (0x1U << DSI_WPCR3_TLPXC0_Pos) /*!< 0x01000000 */ #define DSI_WPCR3_TLPXC0 DSI_WPCR3_TLPXC0_Msk #define DSI_WPCR3_TLPXC1_Pos (25U) #define DSI_WPCR3_TLPXC1_Msk (0x1U << DSI_WPCR3_TLPXC1_Pos) /*!< 0x02000000 */ #define DSI_WPCR3_TLPXC1 DSI_WPCR3_TLPXC1_Msk #define DSI_WPCR3_TLPXC2_Pos (26U) #define DSI_WPCR3_TLPXC2_Msk (0x1U << DSI_WPCR3_TLPXC2_Pos) /*!< 0x04000000 */ #define DSI_WPCR3_TLPXC2 DSI_WPCR3_TLPXC2_Msk #define DSI_WPCR3_TLPXC3_Pos (27U) #define DSI_WPCR3_TLPXC3_Msk (0x1U << DSI_WPCR3_TLPXC3_Pos) /*!< 0x08000000 */ #define DSI_WPCR3_TLPXC3 DSI_WPCR3_TLPXC3_Msk #define DSI_WPCR3_TLPXC4_Pos (28U) #define DSI_WPCR3_TLPXC4_Msk (0x1U << DSI_WPCR3_TLPXC4_Pos) /*!< 0x10000000 */ #define DSI_WPCR3_TLPXC4 DSI_WPCR3_TLPXC4_Msk #define DSI_WPCR3_TLPXC5_Pos (29U) #define DSI_WPCR3_TLPXC5_Msk (0x1U << DSI_WPCR3_TLPXC5_Pos) /*!< 0x20000000 */ #define DSI_WPCR3_TLPXC5 DSI_WPCR3_TLPXC5_Msk #define DSI_WPCR3_TLPXC6_Pos (30U) #define DSI_WPCR3_TLPXC6_Msk (0x1U << DSI_WPCR3_TLPXC6_Pos) /*!< 0x40000000 */ #define DSI_WPCR3_TLPXC6 DSI_WPCR3_TLPXC6_Msk #define DSI_WPCR3_TLPXC7_Pos (31U) #define DSI_WPCR3_TLPXC7_Msk (0x1U << DSI_WPCR3_TLPXC7_Pos) /*!< 0x80000000 */ #define DSI_WPCR3_TLPXC7 DSI_WPCR3_TLPXC7_Msk /******************* Bit definition for DSI_WPCR4 register ***************/ #define DSI_WPCR4_TCLKPOST_Pos (0U) #define DSI_WPCR4_TCLKPOST_Msk (0xFFU << DSI_WPCR4_TCLKPOST_Pos) /*!< 0x000000FF */ #define DSI_WPCR4_TCLKPOST DSI_WPCR4_TCLKPOST_Msk /*!< t-CLKPOST */ #define DSI_WPCR4_TCLKPOST0_Pos (0U) #define DSI_WPCR4_TCLKPOST0_Msk (0x1U << DSI_WPCR4_TCLKPOST0_Pos) /*!< 0x00000001 */ #define DSI_WPCR4_TCLKPOST0 DSI_WPCR4_TCLKPOST0_Msk #define DSI_WPCR4_TCLKPOST1_Pos (1U) #define DSI_WPCR4_TCLKPOST1_Msk (0x1U << DSI_WPCR4_TCLKPOST1_Pos) /*!< 0x00000002 */ #define DSI_WPCR4_TCLKPOST1 DSI_WPCR4_TCLKPOST1_Msk #define DSI_WPCR4_TCLKPOST2_Pos (2U) #define DSI_WPCR4_TCLKPOST2_Msk (0x1U << DSI_WPCR4_TCLKPOST2_Pos) /*!< 0x00000004 */ #define DSI_WPCR4_TCLKPOST2 DSI_WPCR4_TCLKPOST2_Msk #define DSI_WPCR4_TCLKPOST3_Pos (3U) #define DSI_WPCR4_TCLKPOST3_Msk (0x1U << DSI_WPCR4_TCLKPOST3_Pos) /*!< 0x00000008 */ #define DSI_WPCR4_TCLKPOST3 DSI_WPCR4_TCLKPOST3_Msk #define DSI_WPCR4_TCLKPOST4_Pos (4U) #define DSI_WPCR4_TCLKPOST4_Msk (0x1U << DSI_WPCR4_TCLKPOST4_Pos) /*!< 0x00000010 */ #define DSI_WPCR4_TCLKPOST4 DSI_WPCR4_TCLKPOST4_Msk #define DSI_WPCR4_TCLKPOST5_Pos (5U) #define DSI_WPCR4_TCLKPOST5_Msk (0x1U << DSI_WPCR4_TCLKPOST5_Pos) /*!< 0x00000020 */ #define DSI_WPCR4_TCLKPOST5 DSI_WPCR4_TCLKPOST5_Msk #define DSI_WPCR4_TCLKPOST6_Pos (6U) #define DSI_WPCR4_TCLKPOST6_Msk (0x1U << DSI_WPCR4_TCLKPOST6_Pos) /*!< 0x00000040 */ #define DSI_WPCR4_TCLKPOST6 DSI_WPCR4_TCLKPOST6_Msk #define DSI_WPCR4_TCLKPOST7_Pos (7U) #define DSI_WPCR4_TCLKPOST7_Msk (0x1U << DSI_WPCR4_TCLKPOST7_Pos) /*!< 0x00000080 */ #define DSI_WPCR4_TCLKPOST7 DSI_WPCR4_TCLKPOST7_Msk /******************* Bit definition for DSI_WRPCR register ***************/ #define DSI_WRPCR_PLLEN_Pos (0U) #define DSI_WRPCR_PLLEN_Msk (0x1U << DSI_WRPCR_PLLEN_Pos) /*!< 0x00000001 */ #define DSI_WRPCR_PLLEN DSI_WRPCR_PLLEN_Msk /*!< PLL Enable */ #define DSI_WRPCR_PLL_NDIV_Pos (2U) #define DSI_WRPCR_PLL_NDIV_Msk (0x7FU << DSI_WRPCR_PLL_NDIV_Pos) /*!< 0x000001FC */ #define DSI_WRPCR_PLL_NDIV DSI_WRPCR_PLL_NDIV_Msk /*!< PLL Loop Division Factor */ #define DSI_WRPCR_PLL_NDIV0_Pos (2U) #define DSI_WRPCR_PLL_NDIV0_Msk (0x1U << DSI_WRPCR_PLL_NDIV0_Pos) /*!< 0x00000004 */ #define DSI_WRPCR_PLL_NDIV0 DSI_WRPCR_PLL_NDIV0_Msk #define DSI_WRPCR_PLL_NDIV1_Pos (3U) #define DSI_WRPCR_PLL_NDIV1_Msk (0x1U << DSI_WRPCR_PLL_NDIV1_Pos) /*!< 0x00000008 */ #define DSI_WRPCR_PLL_NDIV1 DSI_WRPCR_PLL_NDIV1_Msk #define DSI_WRPCR_PLL_NDIV2_Pos (4U) #define DSI_WRPCR_PLL_NDIV2_Msk (0x1U << DSI_WRPCR_PLL_NDIV2_Pos) /*!< 0x00000010 */ #define DSI_WRPCR_PLL_NDIV2 DSI_WRPCR_PLL_NDIV2_Msk #define DSI_WRPCR_PLL_NDIV3_Pos (5U) #define DSI_WRPCR_PLL_NDIV3_Msk (0x1U << DSI_WRPCR_PLL_NDIV3_Pos) /*!< 0x00000020 */ #define DSI_WRPCR_PLL_NDIV3 DSI_WRPCR_PLL_NDIV3_Msk #define DSI_WRPCR_PLL_NDIV4_Pos (6U) #define DSI_WRPCR_PLL_NDIV4_Msk (0x1U << DSI_WRPCR_PLL_NDIV4_Pos) /*!< 0x00000040 */ #define DSI_WRPCR_PLL_NDIV4 DSI_WRPCR_PLL_NDIV4_Msk #define DSI_WRPCR_PLL_NDIV5_Pos (7U) #define DSI_WRPCR_PLL_NDIV5_Msk (0x1U << DSI_WRPCR_PLL_NDIV5_Pos) /*!< 0x00000080 */ #define DSI_WRPCR_PLL_NDIV5 DSI_WRPCR_PLL_NDIV5_Msk #define DSI_WRPCR_PLL_NDIV6_Pos (8U) #define DSI_WRPCR_PLL_NDIV6_Msk (0x1U << DSI_WRPCR_PLL_NDIV6_Pos) /*!< 0x00000100 */ #define DSI_WRPCR_PLL_NDIV6 DSI_WRPCR_PLL_NDIV6_Msk #define DSI_WRPCR_PLL_IDF_Pos (11U) #define DSI_WRPCR_PLL_IDF_Msk (0xFU << DSI_WRPCR_PLL_IDF_Pos) /*!< 0x00007800 */ #define DSI_WRPCR_PLL_IDF DSI_WRPCR_PLL_IDF_Msk /*!< PLL Input Division Factor */ #define DSI_WRPCR_PLL_IDF0_Pos (11U) #define DSI_WRPCR_PLL_IDF0_Msk (0x1U << DSI_WRPCR_PLL_IDF0_Pos) /*!< 0x00000800 */ #define DSI_WRPCR_PLL_IDF0 DSI_WRPCR_PLL_IDF0_Msk #define DSI_WRPCR_PLL_IDF1_Pos (12U) #define DSI_WRPCR_PLL_IDF1_Msk (0x1U << DSI_WRPCR_PLL_IDF1_Pos) /*!< 0x00001000 */ #define DSI_WRPCR_PLL_IDF1 DSI_WRPCR_PLL_IDF1_Msk #define DSI_WRPCR_PLL_IDF2_Pos (13U) #define DSI_WRPCR_PLL_IDF2_Msk (0x1U << DSI_WRPCR_PLL_IDF2_Pos) /*!< 0x00002000 */ #define DSI_WRPCR_PLL_IDF2 DSI_WRPCR_PLL_IDF2_Msk #define DSI_WRPCR_PLL_IDF3_Pos (14U) #define DSI_WRPCR_PLL_IDF3_Msk (0x1U << DSI_WRPCR_PLL_IDF3_Pos) /*!< 0x00004000 */ #define DSI_WRPCR_PLL_IDF3 DSI_WRPCR_PLL_IDF3_Msk #define DSI_WRPCR_PLL_ODF_Pos (16U) #define DSI_WRPCR_PLL_ODF_Msk (0x3U << DSI_WRPCR_PLL_ODF_Pos) /*!< 0x00030000 */ #define DSI_WRPCR_PLL_ODF DSI_WRPCR_PLL_ODF_Msk /*!< PLL Output Division Factor */ #define DSI_WRPCR_PLL_ODF0_Pos (16U) #define DSI_WRPCR_PLL_ODF0_Msk (0x1U << DSI_WRPCR_PLL_ODF0_Pos) /*!< 0x00010000 */ #define DSI_WRPCR_PLL_ODF0 DSI_WRPCR_PLL_ODF0_Msk #define DSI_WRPCR_PLL_ODF1_Pos (17U) #define DSI_WRPCR_PLL_ODF1_Msk (0x1U << DSI_WRPCR_PLL_ODF1_Pos) /*!< 0x00020000 */ #define DSI_WRPCR_PLL_ODF1 DSI_WRPCR_PLL_ODF1_Msk #define DSI_WRPCR_REGEN_Pos (24U) #define DSI_WRPCR_REGEN_Msk (0x1U << DSI_WRPCR_REGEN_Pos) /*!< 0x01000000 */ #define DSI_WRPCR_REGEN DSI_WRPCR_REGEN_Msk /*!< Regulator Enable */ /******************************************************************************/ /* */ /* External Interrupt/Event Controller */ /* */ /******************************************************************************/ /******************* Bit definition for EXTI_IMR register *******************/ #define EXTI_IMR_MR0_Pos (0U) #define EXTI_IMR_MR0_Msk (0x1U << EXTI_IMR_MR0_Pos) /*!< 0x00000001 */ #define EXTI_IMR_MR0 EXTI_IMR_MR0_Msk /*!< Interrupt Mask on line 0 */ #define EXTI_IMR_MR1_Pos (1U) #define EXTI_IMR_MR1_Msk (0x1U << EXTI_IMR_MR1_Pos) /*!< 0x00000002 */ #define EXTI_IMR_MR1 EXTI_IMR_MR1_Msk /*!< Interrupt Mask on line 1 */ #define EXTI_IMR_MR2_Pos (2U) #define EXTI_IMR_MR2_Msk (0x1U << EXTI_IMR_MR2_Pos) /*!< 0x00000004 */ #define EXTI_IMR_MR2 EXTI_IMR_MR2_Msk /*!< Interrupt Mask on line 2 */ #define EXTI_IMR_MR3_Pos (3U) #define EXTI_IMR_MR3_Msk (0x1U << EXTI_IMR_MR3_Pos) /*!< 0x00000008 */ #define EXTI_IMR_MR3 EXTI_IMR_MR3_Msk /*!< Interrupt Mask on line 3 */ #define EXTI_IMR_MR4_Pos (4U) #define EXTI_IMR_MR4_Msk (0x1U << EXTI_IMR_MR4_Pos) /*!< 0x00000010 */ #define EXTI_IMR_MR4 EXTI_IMR_MR4_Msk /*!< Interrupt Mask on line 4 */ #define EXTI_IMR_MR5_Pos (5U) #define EXTI_IMR_MR5_Msk (0x1U << EXTI_IMR_MR5_Pos) /*!< 0x00000020 */ #define EXTI_IMR_MR5 EXTI_IMR_MR5_Msk /*!< Interrupt Mask on line 5 */ #define EXTI_IMR_MR6_Pos (6U) #define EXTI_IMR_MR6_Msk (0x1U << EXTI_IMR_MR6_Pos) /*!< 0x00000040 */ #define EXTI_IMR_MR6 EXTI_IMR_MR6_Msk /*!< Interrupt Mask on line 6 */ #define EXTI_IMR_MR7_Pos (7U) #define EXTI_IMR_MR7_Msk (0x1U << EXTI_IMR_MR7_Pos) /*!< 0x00000080 */ #define EXTI_IMR_MR7 EXTI_IMR_MR7_Msk /*!< Interrupt Mask on line 7 */ #define EXTI_IMR_MR8_Pos (8U) #define EXTI_IMR_MR8_Msk (0x1U << EXTI_IMR_MR8_Pos) /*!< 0x00000100 */ #define EXTI_IMR_MR8 EXTI_IMR_MR8_Msk /*!< Interrupt Mask on line 8 */ #define EXTI_IMR_MR9_Pos (9U) #define EXTI_IMR_MR9_Msk (0x1U << EXTI_IMR_MR9_Pos) /*!< 0x00000200 */ #define EXTI_IMR_MR9 EXTI_IMR_MR9_Msk /*!< Interrupt Mask on line 9 */ #define EXTI_IMR_MR10_Pos (10U) #define EXTI_IMR_MR10_Msk (0x1U << EXTI_IMR_MR10_Pos) /*!< 0x00000400 */ #define EXTI_IMR_MR10 EXTI_IMR_MR10_Msk /*!< Interrupt Mask on line 10 */ #define EXTI_IMR_MR11_Pos (11U) #define EXTI_IMR_MR11_Msk (0x1U << EXTI_IMR_MR11_Pos) /*!< 0x00000800 */ #define EXTI_IMR_MR11 EXTI_IMR_MR11_Msk /*!< Interrupt Mask on line 11 */ #define EXTI_IMR_MR12_Pos (12U) #define EXTI_IMR_MR12_Msk (0x1U << EXTI_IMR_MR12_Pos) /*!< 0x00001000 */ #define EXTI_IMR_MR12 EXTI_IMR_MR12_Msk /*!< Interrupt Mask on line 12 */ #define EXTI_IMR_MR13_Pos (13U) #define EXTI_IMR_MR13_Msk (0x1U << EXTI_IMR_MR13_Pos) /*!< 0x00002000 */ #define EXTI_IMR_MR13 EXTI_IMR_MR13_Msk /*!< Interrupt Mask on line 13 */ #define EXTI_IMR_MR14_Pos (14U) #define EXTI_IMR_MR14_Msk (0x1U << EXTI_IMR_MR14_Pos) /*!< 0x00004000 */ #define EXTI_IMR_MR14 EXTI_IMR_MR14_Msk /*!< Interrupt Mask on line 14 */ #define EXTI_IMR_MR15_Pos (15U) #define EXTI_IMR_MR15_Msk (0x1U << EXTI_IMR_MR15_Pos) /*!< 0x00008000 */ #define EXTI_IMR_MR15 EXTI_IMR_MR15_Msk /*!< Interrupt Mask on line 15 */ #define EXTI_IMR_MR16_Pos (16U) #define EXTI_IMR_MR16_Msk (0x1U << EXTI_IMR_MR16_Pos) /*!< 0x00010000 */ #define EXTI_IMR_MR16 EXTI_IMR_MR16_Msk /*!< Interrupt Mask on line 16 */ #define EXTI_IMR_MR17_Pos (17U) #define EXTI_IMR_MR17_Msk (0x1U << EXTI_IMR_MR17_Pos) /*!< 0x00020000 */ #define EXTI_IMR_MR17 EXTI_IMR_MR17_Msk /*!< Interrupt Mask on line 17 */ #define EXTI_IMR_MR18_Pos (18U) #define EXTI_IMR_MR18_Msk (0x1U << EXTI_IMR_MR18_Pos) /*!< 0x00040000 */ #define EXTI_IMR_MR18 EXTI_IMR_MR18_Msk /*!< Interrupt Mask on line 18 */ #define EXTI_IMR_MR19_Pos (19U) #define EXTI_IMR_MR19_Msk (0x1U << EXTI_IMR_MR19_Pos) /*!< 0x00080000 */ #define EXTI_IMR_MR19 EXTI_IMR_MR19_Msk /*!< Interrupt Mask on line 19 */ #define EXTI_IMR_MR20_Pos (20U) #define EXTI_IMR_MR20_Msk (0x1U << EXTI_IMR_MR20_Pos) /*!< 0x00100000 */ #define EXTI_IMR_MR20 EXTI_IMR_MR20_Msk /*!< Interrupt Mask on line 20 */ #define EXTI_IMR_MR21_Pos (21U) #define EXTI_IMR_MR21_Msk (0x1U << EXTI_IMR_MR21_Pos) /*!< 0x00200000 */ #define EXTI_IMR_MR21 EXTI_IMR_MR21_Msk /*!< Interrupt Mask on line 21 */ #define EXTI_IMR_MR22_Pos (22U) #define EXTI_IMR_MR22_Msk (0x1U << EXTI_IMR_MR22_Pos) /*!< 0x00400000 */ #define EXTI_IMR_MR22 EXTI_IMR_MR22_Msk /*!< Interrupt Mask on line 22 */ /* Reference Defines */ #define EXTI_IMR_IM0 EXTI_IMR_MR0 #define EXTI_IMR_IM1 EXTI_IMR_MR1 #define EXTI_IMR_IM2 EXTI_IMR_MR2 #define EXTI_IMR_IM3 EXTI_IMR_MR3 #define EXTI_IMR_IM4 EXTI_IMR_MR4 #define EXTI_IMR_IM5 EXTI_IMR_MR5 #define EXTI_IMR_IM6 EXTI_IMR_MR6 #define EXTI_IMR_IM7 EXTI_IMR_MR7 #define EXTI_IMR_IM8 EXTI_IMR_MR8 #define EXTI_IMR_IM9 EXTI_IMR_MR9 #define EXTI_IMR_IM10 EXTI_IMR_MR10 #define EXTI_IMR_IM11 EXTI_IMR_MR11 #define EXTI_IMR_IM12 EXTI_IMR_MR12 #define EXTI_IMR_IM13 EXTI_IMR_MR13 #define EXTI_IMR_IM14 EXTI_IMR_MR14 #define EXTI_IMR_IM15 EXTI_IMR_MR15 #define EXTI_IMR_IM16 EXTI_IMR_MR16 #define EXTI_IMR_IM17 EXTI_IMR_MR17 #define EXTI_IMR_IM18 EXTI_IMR_MR18 #define EXTI_IMR_IM19 EXTI_IMR_MR19 #define EXTI_IMR_IM20 EXTI_IMR_MR20 #define EXTI_IMR_IM21 EXTI_IMR_MR21 #define EXTI_IMR_IM22 EXTI_IMR_MR22 #define EXTI_IMR_IM_Pos (0U) #define EXTI_IMR_IM_Msk (0x7FFFFFU << EXTI_IMR_IM_Pos) /*!< 0x007FFFFF */ #define EXTI_IMR_IM EXTI_IMR_IM_Msk /*!< Interrupt Mask All */ /******************* Bit definition for EXTI_EMR register *******************/ #define EXTI_EMR_MR0_Pos (0U) #define EXTI_EMR_MR0_Msk (0x1U << EXTI_EMR_MR0_Pos) /*!< 0x00000001 */ #define EXTI_EMR_MR0 EXTI_EMR_MR0_Msk /*!< Event Mask on line 0 */ #define EXTI_EMR_MR1_Pos (1U) #define EXTI_EMR_MR1_Msk (0x1U << EXTI_EMR_MR1_Pos) /*!< 0x00000002 */ #define EXTI_EMR_MR1 EXTI_EMR_MR1_Msk /*!< Event Mask on line 1 */ #define EXTI_EMR_MR2_Pos (2U) #define EXTI_EMR_MR2_Msk (0x1U << EXTI_EMR_MR2_Pos) /*!< 0x00000004 */ #define EXTI_EMR_MR2 EXTI_EMR_MR2_Msk /*!< Event Mask on line 2 */ #define EXTI_EMR_MR3_Pos (3U) #define EXTI_EMR_MR3_Msk (0x1U << EXTI_EMR_MR3_Pos) /*!< 0x00000008 */ #define EXTI_EMR_MR3 EXTI_EMR_MR3_Msk /*!< Event Mask on line 3 */ #define EXTI_EMR_MR4_Pos (4U) #define EXTI_EMR_MR4_Msk (0x1U << EXTI_EMR_MR4_Pos) /*!< 0x00000010 */ #define EXTI_EMR_MR4 EXTI_EMR_MR4_Msk /*!< Event Mask on line 4 */ #define EXTI_EMR_MR5_Pos (5U) #define EXTI_EMR_MR5_Msk (0x1U << EXTI_EMR_MR5_Pos) /*!< 0x00000020 */ #define EXTI_EMR_MR5 EXTI_EMR_MR5_Msk /*!< Event Mask on line 5 */ #define EXTI_EMR_MR6_Pos (6U) #define EXTI_EMR_MR6_Msk (0x1U << EXTI_EMR_MR6_Pos) /*!< 0x00000040 */ #define EXTI_EMR_MR6 EXTI_EMR_MR6_Msk /*!< Event Mask on line 6 */ #define EXTI_EMR_MR7_Pos (7U) #define EXTI_EMR_MR7_Msk (0x1U << EXTI_EMR_MR7_Pos) /*!< 0x00000080 */ #define EXTI_EMR_MR7 EXTI_EMR_MR7_Msk /*!< Event Mask on line 7 */ #define EXTI_EMR_MR8_Pos (8U) #define EXTI_EMR_MR8_Msk (0x1U << EXTI_EMR_MR8_Pos) /*!< 0x00000100 */ #define EXTI_EMR_MR8 EXTI_EMR_MR8_Msk /*!< Event Mask on line 8 */ #define EXTI_EMR_MR9_Pos (9U) #define EXTI_EMR_MR9_Msk (0x1U << EXTI_EMR_MR9_Pos) /*!< 0x00000200 */ #define EXTI_EMR_MR9 EXTI_EMR_MR9_Msk /*!< Event Mask on line 9 */ #define EXTI_EMR_MR10_Pos (10U) #define EXTI_EMR_MR10_Msk (0x1U << EXTI_EMR_MR10_Pos) /*!< 0x00000400 */ #define EXTI_EMR_MR10 EXTI_EMR_MR10_Msk /*!< Event Mask on line 10 */ #define EXTI_EMR_MR11_Pos (11U) #define EXTI_EMR_MR11_Msk (0x1U << EXTI_EMR_MR11_Pos) /*!< 0x00000800 */ #define EXTI_EMR_MR11 EXTI_EMR_MR11_Msk /*!< Event Mask on line 11 */ #define EXTI_EMR_MR12_Pos (12U) #define EXTI_EMR_MR12_Msk (0x1U << EXTI_EMR_MR12_Pos) /*!< 0x00001000 */ #define EXTI_EMR_MR12 EXTI_EMR_MR12_Msk /*!< Event Mask on line 12 */ #define EXTI_EMR_MR13_Pos (13U) #define EXTI_EMR_MR13_Msk (0x1U << EXTI_EMR_MR13_Pos) /*!< 0x00002000 */ #define EXTI_EMR_MR13 EXTI_EMR_MR13_Msk /*!< Event Mask on line 13 */ #define EXTI_EMR_MR14_Pos (14U) #define EXTI_EMR_MR14_Msk (0x1U << EXTI_EMR_MR14_Pos) /*!< 0x00004000 */ #define EXTI_EMR_MR14 EXTI_EMR_MR14_Msk /*!< Event Mask on line 14 */ #define EXTI_EMR_MR15_Pos (15U) #define EXTI_EMR_MR15_Msk (0x1U << EXTI_EMR_MR15_Pos) /*!< 0x00008000 */ #define EXTI_EMR_MR15 EXTI_EMR_MR15_Msk /*!< Event Mask on line 15 */ #define EXTI_EMR_MR16_Pos (16U) #define EXTI_EMR_MR16_Msk (0x1U << EXTI_EMR_MR16_Pos) /*!< 0x00010000 */ #define EXTI_EMR_MR16 EXTI_EMR_MR16_Msk /*!< Event Mask on line 16 */ #define EXTI_EMR_MR17_Pos (17U) #define EXTI_EMR_MR17_Msk (0x1U << EXTI_EMR_MR17_Pos) /*!< 0x00020000 */ #define EXTI_EMR_MR17 EXTI_EMR_MR17_Msk /*!< Event Mask on line 17 */ #define EXTI_EMR_MR18_Pos (18U) #define EXTI_EMR_MR18_Msk (0x1U << EXTI_EMR_MR18_Pos) /*!< 0x00040000 */ #define EXTI_EMR_MR18 EXTI_EMR_MR18_Msk /*!< Event Mask on line 18 */ #define EXTI_EMR_MR19_Pos (19U) #define EXTI_EMR_MR19_Msk (0x1U << EXTI_EMR_MR19_Pos) /*!< 0x00080000 */ #define EXTI_EMR_MR19 EXTI_EMR_MR19_Msk /*!< Event Mask on line 19 */ #define EXTI_EMR_MR20_Pos (20U) #define EXTI_EMR_MR20_Msk (0x1U << EXTI_EMR_MR20_Pos) /*!< 0x00100000 */ #define EXTI_EMR_MR20 EXTI_EMR_MR20_Msk /*!< Event Mask on line 20 */ #define EXTI_EMR_MR21_Pos (21U) #define EXTI_EMR_MR21_Msk (0x1U << EXTI_EMR_MR21_Pos) /*!< 0x00200000 */ #define EXTI_EMR_MR21 EXTI_EMR_MR21_Msk /*!< Event Mask on line 21 */ #define EXTI_EMR_MR22_Pos (22U) #define EXTI_EMR_MR22_Msk (0x1U << EXTI_EMR_MR22_Pos) /*!< 0x00400000 */ #define EXTI_EMR_MR22 EXTI_EMR_MR22_Msk /*!< Event Mask on line 22 */ /* Reference Defines */ #define EXTI_EMR_EM0 EXTI_EMR_MR0 #define EXTI_EMR_EM1 EXTI_EMR_MR1 #define EXTI_EMR_EM2 EXTI_EMR_MR2 #define EXTI_EMR_EM3 EXTI_EMR_MR3 #define EXTI_EMR_EM4 EXTI_EMR_MR4 #define EXTI_EMR_EM5 EXTI_EMR_MR5 #define EXTI_EMR_EM6 EXTI_EMR_MR6 #define EXTI_EMR_EM7 EXTI_EMR_MR7 #define EXTI_EMR_EM8 EXTI_EMR_MR8 #define EXTI_EMR_EM9 EXTI_EMR_MR9 #define EXTI_EMR_EM10 EXTI_EMR_MR10 #define EXTI_EMR_EM11 EXTI_EMR_MR11 #define EXTI_EMR_EM12 EXTI_EMR_MR12 #define EXTI_EMR_EM13 EXTI_EMR_MR13 #define EXTI_EMR_EM14 EXTI_EMR_MR14 #define EXTI_EMR_EM15 EXTI_EMR_MR15 #define EXTI_EMR_EM16 EXTI_EMR_MR16 #define EXTI_EMR_EM17 EXTI_EMR_MR17 #define EXTI_EMR_EM18 EXTI_EMR_MR18 #define EXTI_EMR_EM19 EXTI_EMR_MR19 #define EXTI_EMR_EM20 EXTI_EMR_MR20 #define EXTI_EMR_EM21 EXTI_EMR_MR21 #define EXTI_EMR_EM22 EXTI_EMR_MR22 /****************** Bit definition for EXTI_RTSR register *******************/ #define EXTI_RTSR_TR0_Pos (0U) #define EXTI_RTSR_TR0_Msk (0x1U << EXTI_RTSR_TR0_Pos) /*!< 0x00000001 */ #define EXTI_RTSR_TR0 EXTI_RTSR_TR0_Msk /*!< Rising trigger event configuration bit of line 0 */ #define EXTI_RTSR_TR1_Pos (1U) #define EXTI_RTSR_TR1_Msk (0x1U << EXTI_RTSR_TR1_Pos) /*!< 0x00000002 */ #define EXTI_RTSR_TR1 EXTI_RTSR_TR1_Msk /*!< Rising trigger event configuration bit of line 1 */ #define EXTI_RTSR_TR2_Pos (2U) #define EXTI_RTSR_TR2_Msk (0x1U << EXTI_RTSR_TR2_Pos) /*!< 0x00000004 */ #define EXTI_RTSR_TR2 EXTI_RTSR_TR2_Msk /*!< Rising trigger event configuration bit of line 2 */ #define EXTI_RTSR_TR3_Pos (3U) #define EXTI_RTSR_TR3_Msk (0x1U << EXTI_RTSR_TR3_Pos) /*!< 0x00000008 */ #define EXTI_RTSR_TR3 EXTI_RTSR_TR3_Msk /*!< Rising trigger event configuration bit of line 3 */ #define EXTI_RTSR_TR4_Pos (4U) #define EXTI_RTSR_TR4_Msk (0x1U << EXTI_RTSR_TR4_Pos) /*!< 0x00000010 */ #define EXTI_RTSR_TR4 EXTI_RTSR_TR4_Msk /*!< Rising trigger event configuration bit of line 4 */ #define EXTI_RTSR_TR5_Pos (5U) #define EXTI_RTSR_TR5_Msk (0x1U << EXTI_RTSR_TR5_Pos) /*!< 0x00000020 */ #define EXTI_RTSR_TR5 EXTI_RTSR_TR5_Msk /*!< Rising trigger event configuration bit of line 5 */ #define EXTI_RTSR_TR6_Pos (6U) #define EXTI_RTSR_TR6_Msk (0x1U << EXTI_RTSR_TR6_Pos) /*!< 0x00000040 */ #define EXTI_RTSR_TR6 EXTI_RTSR_TR6_Msk /*!< Rising trigger event configuration bit of line 6 */ #define EXTI_RTSR_TR7_Pos (7U) #define EXTI_RTSR_TR7_Msk (0x1U << EXTI_RTSR_TR7_Pos) /*!< 0x00000080 */ #define EXTI_RTSR_TR7 EXTI_RTSR_TR7_Msk /*!< Rising trigger event configuration bit of line 7 */ #define EXTI_RTSR_TR8_Pos (8U) #define EXTI_RTSR_TR8_Msk (0x1U << EXTI_RTSR_TR8_Pos) /*!< 0x00000100 */ #define EXTI_RTSR_TR8 EXTI_RTSR_TR8_Msk /*!< Rising trigger event configuration bit of line 8 */ #define EXTI_RTSR_TR9_Pos (9U) #define EXTI_RTSR_TR9_Msk (0x1U << EXTI_RTSR_TR9_Pos) /*!< 0x00000200 */ #define EXTI_RTSR_TR9 EXTI_RTSR_TR9_Msk /*!< Rising trigger event configuration bit of line 9 */ #define EXTI_RTSR_TR10_Pos (10U) #define EXTI_RTSR_TR10_Msk (0x1U << EXTI_RTSR_TR10_Pos) /*!< 0x00000400 */ #define EXTI_RTSR_TR10 EXTI_RTSR_TR10_Msk /*!< Rising trigger event configuration bit of line 10 */ #define EXTI_RTSR_TR11_Pos (11U) #define EXTI_RTSR_TR11_Msk (0x1U << EXTI_RTSR_TR11_Pos) /*!< 0x00000800 */ #define EXTI_RTSR_TR11 EXTI_RTSR_TR11_Msk /*!< Rising trigger event configuration bit of line 11 */ #define EXTI_RTSR_TR12_Pos (12U) #define EXTI_RTSR_TR12_Msk (0x1U << EXTI_RTSR_TR12_Pos) /*!< 0x00001000 */ #define EXTI_RTSR_TR12 EXTI_RTSR_TR12_Msk /*!< Rising trigger event configuration bit of line 12 */ #define EXTI_RTSR_TR13_Pos (13U) #define EXTI_RTSR_TR13_Msk (0x1U << EXTI_RTSR_TR13_Pos) /*!< 0x00002000 */ #define EXTI_RTSR_TR13 EXTI_RTSR_TR13_Msk /*!< Rising trigger event configuration bit of line 13 */ #define EXTI_RTSR_TR14_Pos (14U) #define EXTI_RTSR_TR14_Msk (0x1U << EXTI_RTSR_TR14_Pos) /*!< 0x00004000 */ #define EXTI_RTSR_TR14 EXTI_RTSR_TR14_Msk /*!< Rising trigger event configuration bit of line 14 */ #define EXTI_RTSR_TR15_Pos (15U) #define EXTI_RTSR_TR15_Msk (0x1U << EXTI_RTSR_TR15_Pos) /*!< 0x00008000 */ #define EXTI_RTSR_TR15 EXTI_RTSR_TR15_Msk /*!< Rising trigger event configuration bit of line 15 */ #define EXTI_RTSR_TR16_Pos (16U) #define EXTI_RTSR_TR16_Msk (0x1U << EXTI_RTSR_TR16_Pos) /*!< 0x00010000 */ #define EXTI_RTSR_TR16 EXTI_RTSR_TR16_Msk /*!< Rising trigger event configuration bit of line 16 */ #define EXTI_RTSR_TR17_Pos (17U) #define EXTI_RTSR_TR17_Msk (0x1U << EXTI_RTSR_TR17_Pos) /*!< 0x00020000 */ #define EXTI_RTSR_TR17 EXTI_RTSR_TR17_Msk /*!< Rising trigger event configuration bit of line 17 */ #define EXTI_RTSR_TR18_Pos (18U) #define EXTI_RTSR_TR18_Msk (0x1U << EXTI_RTSR_TR18_Pos) /*!< 0x00040000 */ #define EXTI_RTSR_TR18 EXTI_RTSR_TR18_Msk /*!< Rising trigger event configuration bit of line 18 */ #define EXTI_RTSR_TR19_Pos (19U) #define EXTI_RTSR_TR19_Msk (0x1U << EXTI_RTSR_TR19_Pos) /*!< 0x00080000 */ #define EXTI_RTSR_TR19 EXTI_RTSR_TR19_Msk /*!< Rising trigger event configuration bit of line 19 */ #define EXTI_RTSR_TR20_Pos (20U) #define EXTI_RTSR_TR20_Msk (0x1U << EXTI_RTSR_TR20_Pos) /*!< 0x00100000 */ #define EXTI_RTSR_TR20 EXTI_RTSR_TR20_Msk /*!< Rising trigger event configuration bit of line 20 */ #define EXTI_RTSR_TR21_Pos (21U) #define EXTI_RTSR_TR21_Msk (0x1U << EXTI_RTSR_TR21_Pos) /*!< 0x00200000 */ #define EXTI_RTSR_TR21 EXTI_RTSR_TR21_Msk /*!< Rising trigger event configuration bit of line 21 */ #define EXTI_RTSR_TR22_Pos (22U) #define EXTI_RTSR_TR22_Msk (0x1U << EXTI_RTSR_TR22_Pos) /*!< 0x00400000 */ #define EXTI_RTSR_TR22 EXTI_RTSR_TR22_Msk /*!< Rising trigger event configuration bit of line 22 */ /****************** Bit definition for EXTI_FTSR register *******************/ #define EXTI_FTSR_TR0_Pos (0U) #define EXTI_FTSR_TR0_Msk (0x1U << EXTI_FTSR_TR0_Pos) /*!< 0x00000001 */ #define EXTI_FTSR_TR0 EXTI_FTSR_TR0_Msk /*!< Falling trigger event configuration bit of line 0 */ #define EXTI_FTSR_TR1_Pos (1U) #define EXTI_FTSR_TR1_Msk (0x1U << EXTI_FTSR_TR1_Pos) /*!< 0x00000002 */ #define EXTI_FTSR_TR1 EXTI_FTSR_TR1_Msk /*!< Falling trigger event configuration bit of line 1 */ #define EXTI_FTSR_TR2_Pos (2U) #define EXTI_FTSR_TR2_Msk (0x1U << EXTI_FTSR_TR2_Pos) /*!< 0x00000004 */ #define EXTI_FTSR_TR2 EXTI_FTSR_TR2_Msk /*!< Falling trigger event configuration bit of line 2 */ #define EXTI_FTSR_TR3_Pos (3U) #define EXTI_FTSR_TR3_Msk (0x1U << EXTI_FTSR_TR3_Pos) /*!< 0x00000008 */ #define EXTI_FTSR_TR3 EXTI_FTSR_TR3_Msk /*!< Falling trigger event configuration bit of line 3 */ #define EXTI_FTSR_TR4_Pos (4U) #define EXTI_FTSR_TR4_Msk (0x1U << EXTI_FTSR_TR4_Pos) /*!< 0x00000010 */ #define EXTI_FTSR_TR4 EXTI_FTSR_TR4_Msk /*!< Falling trigger event configuration bit of line 4 */ #define EXTI_FTSR_TR5_Pos (5U) #define EXTI_FTSR_TR5_Msk (0x1U << EXTI_FTSR_TR5_Pos) /*!< 0x00000020 */ #define EXTI_FTSR_TR5 EXTI_FTSR_TR5_Msk /*!< Falling trigger event configuration bit of line 5 */ #define EXTI_FTSR_TR6_Pos (6U) #define EXTI_FTSR_TR6_Msk (0x1U << EXTI_FTSR_TR6_Pos) /*!< 0x00000040 */ #define EXTI_FTSR_TR6 EXTI_FTSR_TR6_Msk /*!< Falling trigger event configuration bit of line 6 */ #define EXTI_FTSR_TR7_Pos (7U) #define EXTI_FTSR_TR7_Msk (0x1U << EXTI_FTSR_TR7_Pos) /*!< 0x00000080 */ #define EXTI_FTSR_TR7 EXTI_FTSR_TR7_Msk /*!< Falling trigger event configuration bit of line 7 */ #define EXTI_FTSR_TR8_Pos (8U) #define EXTI_FTSR_TR8_Msk (0x1U << EXTI_FTSR_TR8_Pos) /*!< 0x00000100 */ #define EXTI_FTSR_TR8 EXTI_FTSR_TR8_Msk /*!< Falling trigger event configuration bit of line 8 */ #define EXTI_FTSR_TR9_Pos (9U) #define EXTI_FTSR_TR9_Msk (0x1U << EXTI_FTSR_TR9_Pos) /*!< 0x00000200 */ #define EXTI_FTSR_TR9 EXTI_FTSR_TR9_Msk /*!< Falling trigger event configuration bit of line 9 */ #define EXTI_FTSR_TR10_Pos (10U) #define EXTI_FTSR_TR10_Msk (0x1U << EXTI_FTSR_TR10_Pos) /*!< 0x00000400 */ #define EXTI_FTSR_TR10 EXTI_FTSR_TR10_Msk /*!< Falling trigger event configuration bit of line 10 */ #define EXTI_FTSR_TR11_Pos (11U) #define EXTI_FTSR_TR11_Msk (0x1U << EXTI_FTSR_TR11_Pos) /*!< 0x00000800 */ #define EXTI_FTSR_TR11 EXTI_FTSR_TR11_Msk /*!< Falling trigger event configuration bit of line 11 */ #define EXTI_FTSR_TR12_Pos (12U) #define EXTI_FTSR_TR12_Msk (0x1U << EXTI_FTSR_TR12_Pos) /*!< 0x00001000 */ #define EXTI_FTSR_TR12 EXTI_FTSR_TR12_Msk /*!< Falling trigger event configuration bit of line 12 */ #define EXTI_FTSR_TR13_Pos (13U) #define EXTI_FTSR_TR13_Msk (0x1U << EXTI_FTSR_TR13_Pos) /*!< 0x00002000 */ #define EXTI_FTSR_TR13 EXTI_FTSR_TR13_Msk /*!< Falling trigger event configuration bit of line 13 */ #define EXTI_FTSR_TR14_Pos (14U) #define EXTI_FTSR_TR14_Msk (0x1U << EXTI_FTSR_TR14_Pos) /*!< 0x00004000 */ #define EXTI_FTSR_TR14 EXTI_FTSR_TR14_Msk /*!< Falling trigger event configuration bit of line 14 */ #define EXTI_FTSR_TR15_Pos (15U) #define EXTI_FTSR_TR15_Msk (0x1U << EXTI_FTSR_TR15_Pos) /*!< 0x00008000 */ #define EXTI_FTSR_TR15 EXTI_FTSR_TR15_Msk /*!< Falling trigger event configuration bit of line 15 */ #define EXTI_FTSR_TR16_Pos (16U) #define EXTI_FTSR_TR16_Msk (0x1U << EXTI_FTSR_TR16_Pos) /*!< 0x00010000 */ #define EXTI_FTSR_TR16 EXTI_FTSR_TR16_Msk /*!< Falling trigger event configuration bit of line 16 */ #define EXTI_FTSR_TR17_Pos (17U) #define EXTI_FTSR_TR17_Msk (0x1U << EXTI_FTSR_TR17_Pos) /*!< 0x00020000 */ #define EXTI_FTSR_TR17 EXTI_FTSR_TR17_Msk /*!< Falling trigger event configuration bit of line 17 */ #define EXTI_FTSR_TR18_Pos (18U) #define EXTI_FTSR_TR18_Msk (0x1U << EXTI_FTSR_TR18_Pos) /*!< 0x00040000 */ #define EXTI_FTSR_TR18 EXTI_FTSR_TR18_Msk /*!< Falling trigger event configuration bit of line 18 */ #define EXTI_FTSR_TR19_Pos (19U) #define EXTI_FTSR_TR19_Msk (0x1U << EXTI_FTSR_TR19_Pos) /*!< 0x00080000 */ #define EXTI_FTSR_TR19 EXTI_FTSR_TR19_Msk /*!< Falling trigger event configuration bit of line 19 */ #define EXTI_FTSR_TR20_Pos (20U) #define EXTI_FTSR_TR20_Msk (0x1U << EXTI_FTSR_TR20_Pos) /*!< 0x00100000 */ #define EXTI_FTSR_TR20 EXTI_FTSR_TR20_Msk /*!< Falling trigger event configuration bit of line 20 */ #define EXTI_FTSR_TR21_Pos (21U) #define EXTI_FTSR_TR21_Msk (0x1U << EXTI_FTSR_TR21_Pos) /*!< 0x00200000 */ #define EXTI_FTSR_TR21 EXTI_FTSR_TR21_Msk /*!< Falling trigger event configuration bit of line 21 */ #define EXTI_FTSR_TR22_Pos (22U) #define EXTI_FTSR_TR22_Msk (0x1U << EXTI_FTSR_TR22_Pos) /*!< 0x00400000 */ #define EXTI_FTSR_TR22 EXTI_FTSR_TR22_Msk /*!< Falling trigger event configuration bit of line 22 */ /****************** Bit definition for EXTI_SWIER register ******************/ #define EXTI_SWIER_SWIER0_Pos (0U) #define EXTI_SWIER_SWIER0_Msk (0x1U << EXTI_SWIER_SWIER0_Pos) /*!< 0x00000001 */ #define EXTI_SWIER_SWIER0 EXTI_SWIER_SWIER0_Msk /*!< Software Interrupt on line 0 */ #define EXTI_SWIER_SWIER1_Pos (1U) #define EXTI_SWIER_SWIER1_Msk (0x1U << EXTI_SWIER_SWIER1_Pos) /*!< 0x00000002 */ #define EXTI_SWIER_SWIER1 EXTI_SWIER_SWIER1_Msk /*!< Software Interrupt on line 1 */ #define EXTI_SWIER_SWIER2_Pos (2U) #define EXTI_SWIER_SWIER2_Msk (0x1U << EXTI_SWIER_SWIER2_Pos) /*!< 0x00000004 */ #define EXTI_SWIER_SWIER2 EXTI_SWIER_SWIER2_Msk /*!< Software Interrupt on line 2 */ #define EXTI_SWIER_SWIER3_Pos (3U) #define EXTI_SWIER_SWIER3_Msk (0x1U << EXTI_SWIER_SWIER3_Pos) /*!< 0x00000008 */ #define EXTI_SWIER_SWIER3 EXTI_SWIER_SWIER3_Msk /*!< Software Interrupt on line 3 */ #define EXTI_SWIER_SWIER4_Pos (4U) #define EXTI_SWIER_SWIER4_Msk (0x1U << EXTI_SWIER_SWIER4_Pos) /*!< 0x00000010 */ #define EXTI_SWIER_SWIER4 EXTI_SWIER_SWIER4_Msk /*!< Software Interrupt on line 4 */ #define EXTI_SWIER_SWIER5_Pos (5U) #define EXTI_SWIER_SWIER5_Msk (0x1U << EXTI_SWIER_SWIER5_Pos) /*!< 0x00000020 */ #define EXTI_SWIER_SWIER5 EXTI_SWIER_SWIER5_Msk /*!< Software Interrupt on line 5 */ #define EXTI_SWIER_SWIER6_Pos (6U) #define EXTI_SWIER_SWIER6_Msk (0x1U << EXTI_SWIER_SWIER6_Pos) /*!< 0x00000040 */ #define EXTI_SWIER_SWIER6 EXTI_SWIER_SWIER6_Msk /*!< Software Interrupt on line 6 */ #define EXTI_SWIER_SWIER7_Pos (7U) #define EXTI_SWIER_SWIER7_Msk (0x1U << EXTI_SWIER_SWIER7_Pos) /*!< 0x00000080 */ #define EXTI_SWIER_SWIER7 EXTI_SWIER_SWIER7_Msk /*!< Software Interrupt on line 7 */ #define EXTI_SWIER_SWIER8_Pos (8U) #define EXTI_SWIER_SWIER8_Msk (0x1U << EXTI_SWIER_SWIER8_Pos) /*!< 0x00000100 */ #define EXTI_SWIER_SWIER8 EXTI_SWIER_SWIER8_Msk /*!< Software Interrupt on line 8 */ #define EXTI_SWIER_SWIER9_Pos (9U) #define EXTI_SWIER_SWIER9_Msk (0x1U << EXTI_SWIER_SWIER9_Pos) /*!< 0x00000200 */ #define EXTI_SWIER_SWIER9 EXTI_SWIER_SWIER9_Msk /*!< Software Interrupt on line 9 */ #define EXTI_SWIER_SWIER10_Pos (10U) #define EXTI_SWIER_SWIER10_Msk (0x1U << EXTI_SWIER_SWIER10_Pos) /*!< 0x00000400 */ #define EXTI_SWIER_SWIER10 EXTI_SWIER_SWIER10_Msk /*!< Software Interrupt on line 10 */ #define EXTI_SWIER_SWIER11_Pos (11U) #define EXTI_SWIER_SWIER11_Msk (0x1U << EXTI_SWIER_SWIER11_Pos) /*!< 0x00000800 */ #define EXTI_SWIER_SWIER11 EXTI_SWIER_SWIER11_Msk /*!< Software Interrupt on line 11 */ #define EXTI_SWIER_SWIER12_Pos (12U) #define EXTI_SWIER_SWIER12_Msk (0x1U << EXTI_SWIER_SWIER12_Pos) /*!< 0x00001000 */ #define EXTI_SWIER_SWIER12 EXTI_SWIER_SWIER12_Msk /*!< Software Interrupt on line 12 */ #define EXTI_SWIER_SWIER13_Pos (13U) #define EXTI_SWIER_SWIER13_Msk (0x1U << EXTI_SWIER_SWIER13_Pos) /*!< 0x00002000 */ #define EXTI_SWIER_SWIER13 EXTI_SWIER_SWIER13_Msk /*!< Software Interrupt on line 13 */ #define EXTI_SWIER_SWIER14_Pos (14U) #define EXTI_SWIER_SWIER14_Msk (0x1U << EXTI_SWIER_SWIER14_Pos) /*!< 0x00004000 */ #define EXTI_SWIER_SWIER14 EXTI_SWIER_SWIER14_Msk /*!< Software Interrupt on line 14 */ #define EXTI_SWIER_SWIER15_Pos (15U) #define EXTI_SWIER_SWIER15_Msk (0x1U << EXTI_SWIER_SWIER15_Pos) /*!< 0x00008000 */ #define EXTI_SWIER_SWIER15 EXTI_SWIER_SWIER15_Msk /*!< Software Interrupt on line 15 */ #define EXTI_SWIER_SWIER16_Pos (16U) #define EXTI_SWIER_SWIER16_Msk (0x1U << EXTI_SWIER_SWIER16_Pos) /*!< 0x00010000 */ #define EXTI_SWIER_SWIER16 EXTI_SWIER_SWIER16_Msk /*!< Software Interrupt on line 16 */ #define EXTI_SWIER_SWIER17_Pos (17U) #define EXTI_SWIER_SWIER17_Msk (0x1U << EXTI_SWIER_SWIER17_Pos) /*!< 0x00020000 */ #define EXTI_SWIER_SWIER17 EXTI_SWIER_SWIER17_Msk /*!< Software Interrupt on line 17 */ #define EXTI_SWIER_SWIER18_Pos (18U) #define EXTI_SWIER_SWIER18_Msk (0x1U << EXTI_SWIER_SWIER18_Pos) /*!< 0x00040000 */ #define EXTI_SWIER_SWIER18 EXTI_SWIER_SWIER18_Msk /*!< Software Interrupt on line 18 */ #define EXTI_SWIER_SWIER19_Pos (19U) #define EXTI_SWIER_SWIER19_Msk (0x1U << EXTI_SWIER_SWIER19_Pos) /*!< 0x00080000 */ #define EXTI_SWIER_SWIER19 EXTI_SWIER_SWIER19_Msk /*!< Software Interrupt on line 19 */ #define EXTI_SWIER_SWIER20_Pos (20U) #define EXTI_SWIER_SWIER20_Msk (0x1U << EXTI_SWIER_SWIER20_Pos) /*!< 0x00100000 */ #define EXTI_SWIER_SWIER20 EXTI_SWIER_SWIER20_Msk /*!< Software Interrupt on line 20 */ #define EXTI_SWIER_SWIER21_Pos (21U) #define EXTI_SWIER_SWIER21_Msk (0x1U << EXTI_SWIER_SWIER21_Pos) /*!< 0x00200000 */ #define EXTI_SWIER_SWIER21 EXTI_SWIER_SWIER21_Msk /*!< Software Interrupt on line 21 */ #define EXTI_SWIER_SWIER22_Pos (22U) #define EXTI_SWIER_SWIER22_Msk (0x1U << EXTI_SWIER_SWIER22_Pos) /*!< 0x00400000 */ #define EXTI_SWIER_SWIER22 EXTI_SWIER_SWIER22_Msk /*!< Software Interrupt on line 22 */ /******************* Bit definition for EXTI_PR register ********************/ #define EXTI_PR_PR0_Pos (0U) #define EXTI_PR_PR0_Msk (0x1U << EXTI_PR_PR0_Pos) /*!< 0x00000001 */ #define EXTI_PR_PR0 EXTI_PR_PR0_Msk /*!< Pending bit for line 0 */ #define EXTI_PR_PR1_Pos (1U) #define EXTI_PR_PR1_Msk (0x1U << EXTI_PR_PR1_Pos) /*!< 0x00000002 */ #define EXTI_PR_PR1 EXTI_PR_PR1_Msk /*!< Pending bit for line 1 */ #define EXTI_PR_PR2_Pos (2U) #define EXTI_PR_PR2_Msk (0x1U << EXTI_PR_PR2_Pos) /*!< 0x00000004 */ #define EXTI_PR_PR2 EXTI_PR_PR2_Msk /*!< Pending bit for line 2 */ #define EXTI_PR_PR3_Pos (3U) #define EXTI_PR_PR3_Msk (0x1U << EXTI_PR_PR3_Pos) /*!< 0x00000008 */ #define EXTI_PR_PR3 EXTI_PR_PR3_Msk /*!< Pending bit for line 3 */ #define EXTI_PR_PR4_Pos (4U) #define EXTI_PR_PR4_Msk (0x1U << EXTI_PR_PR4_Pos) /*!< 0x00000010 */ #define EXTI_PR_PR4 EXTI_PR_PR4_Msk /*!< Pending bit for line 4 */ #define EXTI_PR_PR5_Pos (5U) #define EXTI_PR_PR5_Msk (0x1U << EXTI_PR_PR5_Pos) /*!< 0x00000020 */ #define EXTI_PR_PR5 EXTI_PR_PR5_Msk /*!< Pending bit for line 5 */ #define EXTI_PR_PR6_Pos (6U) #define EXTI_PR_PR6_Msk (0x1U << EXTI_PR_PR6_Pos) /*!< 0x00000040 */ #define EXTI_PR_PR6 EXTI_PR_PR6_Msk /*!< Pending bit for line 6 */ #define EXTI_PR_PR7_Pos (7U) #define EXTI_PR_PR7_Msk (0x1U << EXTI_PR_PR7_Pos) /*!< 0x00000080 */ #define EXTI_PR_PR7 EXTI_PR_PR7_Msk /*!< Pending bit for line 7 */ #define EXTI_PR_PR8_Pos (8U) #define EXTI_PR_PR8_Msk (0x1U << EXTI_PR_PR8_Pos) /*!< 0x00000100 */ #define EXTI_PR_PR8 EXTI_PR_PR8_Msk /*!< Pending bit for line 8 */ #define EXTI_PR_PR9_Pos (9U) #define EXTI_PR_PR9_Msk (0x1U << EXTI_PR_PR9_Pos) /*!< 0x00000200 */ #define EXTI_PR_PR9 EXTI_PR_PR9_Msk /*!< Pending bit for line 9 */ #define EXTI_PR_PR10_Pos (10U) #define EXTI_PR_PR10_Msk (0x1U << EXTI_PR_PR10_Pos) /*!< 0x00000400 */ #define EXTI_PR_PR10 EXTI_PR_PR10_Msk /*!< Pending bit for line 10 */ #define EXTI_PR_PR11_Pos (11U) #define EXTI_PR_PR11_Msk (0x1U << EXTI_PR_PR11_Pos) /*!< 0x00000800 */ #define EXTI_PR_PR11 EXTI_PR_PR11_Msk /*!< Pending bit for line 11 */ #define EXTI_PR_PR12_Pos (12U) #define EXTI_PR_PR12_Msk (0x1U << EXTI_PR_PR12_Pos) /*!< 0x00001000 */ #define EXTI_PR_PR12 EXTI_PR_PR12_Msk /*!< Pending bit for line 12 */ #define EXTI_PR_PR13_Pos (13U) #define EXTI_PR_PR13_Msk (0x1U << EXTI_PR_PR13_Pos) /*!< 0x00002000 */ #define EXTI_PR_PR13 EXTI_PR_PR13_Msk /*!< Pending bit for line 13 */ #define EXTI_PR_PR14_Pos (14U) #define EXTI_PR_PR14_Msk (0x1U << EXTI_PR_PR14_Pos) /*!< 0x00004000 */ #define EXTI_PR_PR14 EXTI_PR_PR14_Msk /*!< Pending bit for line 14 */ #define EXTI_PR_PR15_Pos (15U) #define EXTI_PR_PR15_Msk (0x1U << EXTI_PR_PR15_Pos) /*!< 0x00008000 */ #define EXTI_PR_PR15 EXTI_PR_PR15_Msk /*!< Pending bit for line 15 */ #define EXTI_PR_PR16_Pos (16U) #define EXTI_PR_PR16_Msk (0x1U << EXTI_PR_PR16_Pos) /*!< 0x00010000 */ #define EXTI_PR_PR16 EXTI_PR_PR16_Msk /*!< Pending bit for line 16 */ #define EXTI_PR_PR17_Pos (17U) #define EXTI_PR_PR17_Msk (0x1U << EXTI_PR_PR17_Pos) /*!< 0x00020000 */ #define EXTI_PR_PR17 EXTI_PR_PR17_Msk /*!< Pending bit for line 17 */ #define EXTI_PR_PR18_Pos (18U) #define EXTI_PR_PR18_Msk (0x1U << EXTI_PR_PR18_Pos) /*!< 0x00040000 */ #define EXTI_PR_PR18 EXTI_PR_PR18_Msk /*!< Pending bit for line 18 */ #define EXTI_PR_PR19_Pos (19U) #define EXTI_PR_PR19_Msk (0x1U << EXTI_PR_PR19_Pos) /*!< 0x00080000 */ #define EXTI_PR_PR19 EXTI_PR_PR19_Msk /*!< Pending bit for line 19 */ #define EXTI_PR_PR20_Pos (20U) #define EXTI_PR_PR20_Msk (0x1U << EXTI_PR_PR20_Pos) /*!< 0x00100000 */ #define EXTI_PR_PR20 EXTI_PR_PR20_Msk /*!< Pending bit for line 20 */ #define EXTI_PR_PR21_Pos (21U) #define EXTI_PR_PR21_Msk (0x1U << EXTI_PR_PR21_Pos) /*!< 0x00200000 */ #define EXTI_PR_PR21 EXTI_PR_PR21_Msk /*!< Pending bit for line 21 */ #define EXTI_PR_PR22_Pos (22U) #define EXTI_PR_PR22_Msk (0x1U << EXTI_PR_PR22_Pos) /*!< 0x00400000 */ #define EXTI_PR_PR22 EXTI_PR_PR22_Msk /*!< Pending bit for line 22 */ /******************************************************************************/ /* */ /* FLASH */ /* */ /******************************************************************************/ /******************* Bits definition for FLASH_ACR register *****************/ #define FLASH_ACR_LATENCY_Pos (0U) #define FLASH_ACR_LATENCY_Msk (0xFU << FLASH_ACR_LATENCY_Pos) /*!< 0x0000000F */ #define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk #define FLASH_ACR_LATENCY_0WS 0x00000000U #define FLASH_ACR_LATENCY_1WS 0x00000001U #define FLASH_ACR_LATENCY_2WS 0x00000002U #define FLASH_ACR_LATENCY_3WS 0x00000003U #define FLASH_ACR_LATENCY_4WS 0x00000004U #define FLASH_ACR_LATENCY_5WS 0x00000005U #define FLASH_ACR_LATENCY_6WS 0x00000006U #define FLASH_ACR_LATENCY_7WS 0x00000007U #define FLASH_ACR_LATENCY_8WS 0x00000008U #define FLASH_ACR_LATENCY_9WS 0x00000009U #define FLASH_ACR_LATENCY_10WS 0x0000000AU #define FLASH_ACR_LATENCY_11WS 0x0000000BU #define FLASH_ACR_LATENCY_12WS 0x0000000CU #define FLASH_ACR_LATENCY_13WS 0x0000000DU #define FLASH_ACR_LATENCY_14WS 0x0000000EU #define FLASH_ACR_LATENCY_15WS 0x0000000FU #define FLASH_ACR_PRFTEN_Pos (8U) #define FLASH_ACR_PRFTEN_Msk (0x1U << FLASH_ACR_PRFTEN_Pos) /*!< 0x00000100 */ #define FLASH_ACR_PRFTEN FLASH_ACR_PRFTEN_Msk #define FLASH_ACR_ICEN_Pos (9U) #define FLASH_ACR_ICEN_Msk (0x1U << FLASH_ACR_ICEN_Pos) /*!< 0x00000200 */ #define FLASH_ACR_ICEN FLASH_ACR_ICEN_Msk #define FLASH_ACR_DCEN_Pos (10U) #define FLASH_ACR_DCEN_Msk (0x1U << FLASH_ACR_DCEN_Pos) /*!< 0x00000400 */ #define FLASH_ACR_DCEN FLASH_ACR_DCEN_Msk #define FLASH_ACR_ICRST_Pos (11U) #define FLASH_ACR_ICRST_Msk (0x1U << FLASH_ACR_ICRST_Pos) /*!< 0x00000800 */ #define FLASH_ACR_ICRST FLASH_ACR_ICRST_Msk #define FLASH_ACR_DCRST_Pos (12U) #define FLASH_ACR_DCRST_Msk (0x1U << FLASH_ACR_DCRST_Pos) /*!< 0x00001000 */ #define FLASH_ACR_DCRST FLASH_ACR_DCRST_Msk #define FLASH_ACR_BYTE0_ADDRESS_Pos (10U) #define FLASH_ACR_BYTE0_ADDRESS_Msk (0x10008FU << FLASH_ACR_BYTE0_ADDRESS_Pos) /*!< 0x40023C00 */ #define FLASH_ACR_BYTE0_ADDRESS FLASH_ACR_BYTE0_ADDRESS_Msk #define FLASH_ACR_BYTE2_ADDRESS_Pos (0U) #define FLASH_ACR_BYTE2_ADDRESS_Msk (0x40023C03U << FLASH_ACR_BYTE2_ADDRESS_Pos) /*!< 0x40023C03 */ #define FLASH_ACR_BYTE2_ADDRESS FLASH_ACR_BYTE2_ADDRESS_Msk /******************* Bits definition for FLASH_SR register ******************/ #define FLASH_SR_EOP_Pos (0U) #define FLASH_SR_EOP_Msk (0x1U << FLASH_SR_EOP_Pos) /*!< 0x00000001 */ #define FLASH_SR_EOP FLASH_SR_EOP_Msk #define FLASH_SR_SOP_Pos (1U) #define FLASH_SR_SOP_Msk (0x1U << FLASH_SR_SOP_Pos) /*!< 0x00000002 */ #define FLASH_SR_SOP FLASH_SR_SOP_Msk #define FLASH_SR_WRPERR_Pos (4U) #define FLASH_SR_WRPERR_Msk (0x1U << FLASH_SR_WRPERR_Pos) /*!< 0x00000010 */ #define FLASH_SR_WRPERR FLASH_SR_WRPERR_Msk #define FLASH_SR_PGAERR_Pos (5U) #define FLASH_SR_PGAERR_Msk (0x1U << FLASH_SR_PGAERR_Pos) /*!< 0x00000020 */ #define FLASH_SR_PGAERR FLASH_SR_PGAERR_Msk #define FLASH_SR_PGPERR_Pos (6U) #define FLASH_SR_PGPERR_Msk (0x1U << FLASH_SR_PGPERR_Pos) /*!< 0x00000040 */ #define FLASH_SR_PGPERR FLASH_SR_PGPERR_Msk #define FLASH_SR_PGSERR_Pos (7U) #define FLASH_SR_PGSERR_Msk (0x1U << FLASH_SR_PGSERR_Pos) /*!< 0x00000080 */ #define FLASH_SR_PGSERR FLASH_SR_PGSERR_Msk #define FLASH_SR_RDERR_Pos (8U) #define FLASH_SR_RDERR_Msk (0x1U << FLASH_SR_RDERR_Pos) /*!< 0x00000100 */ #define FLASH_SR_RDERR FLASH_SR_RDERR_Msk #define FLASH_SR_BSY_Pos (16U) #define FLASH_SR_BSY_Msk (0x1U << FLASH_SR_BSY_Pos) /*!< 0x00010000 */ #define FLASH_SR_BSY FLASH_SR_BSY_Msk /******************* Bits definition for FLASH_CR register ******************/ #define FLASH_CR_PG_Pos (0U) #define FLASH_CR_PG_Msk (0x1U << FLASH_CR_PG_Pos) /*!< 0x00000001 */ #define FLASH_CR_PG FLASH_CR_PG_Msk #define FLASH_CR_SER_Pos (1U) #define FLASH_CR_SER_Msk (0x1U << FLASH_CR_SER_Pos) /*!< 0x00000002 */ #define FLASH_CR_SER FLASH_CR_SER_Msk #define FLASH_CR_MER_Pos (2U) #define FLASH_CR_MER_Msk (0x1U << FLASH_CR_MER_Pos) /*!< 0x00000004 */ #define FLASH_CR_MER FLASH_CR_MER_Msk #define FLASH_CR_MER1 FLASH_CR_MER #define FLASH_CR_SNB_Pos (3U) #define FLASH_CR_SNB_Msk (0x1FU << FLASH_CR_SNB_Pos) /*!< 0x000000F8 */ #define FLASH_CR_SNB FLASH_CR_SNB_Msk #define FLASH_CR_SNB_0 (0x01U << FLASH_CR_SNB_Pos) /*!< 0x00000008 */ #define FLASH_CR_SNB_1 (0x02U << FLASH_CR_SNB_Pos) /*!< 0x00000010 */ #define FLASH_CR_SNB_2 (0x04U << FLASH_CR_SNB_Pos) /*!< 0x00000020 */ #define FLASH_CR_SNB_3 (0x08U << FLASH_CR_SNB_Pos) /*!< 0x00000040 */ #define FLASH_CR_SNB_4 (0x10U << FLASH_CR_SNB_Pos) /*!< 0x00000080 */ #define FLASH_CR_PSIZE_Pos (8U) #define FLASH_CR_PSIZE_Msk (0x3U << FLASH_CR_PSIZE_Pos) /*!< 0x00000300 */ #define FLASH_CR_PSIZE FLASH_CR_PSIZE_Msk #define FLASH_CR_PSIZE_0 (0x1U << FLASH_CR_PSIZE_Pos) /*!< 0x00000100 */ #define FLASH_CR_PSIZE_1 (0x2U << FLASH_CR_PSIZE_Pos) /*!< 0x00000200 */ #define FLASH_CR_MER2_Pos (15U) #define FLASH_CR_MER2_Msk (0x1U << FLASH_CR_MER2_Pos) /*!< 0x00008000 */ #define FLASH_CR_MER2 FLASH_CR_MER2_Msk #define FLASH_CR_STRT_Pos (16U) #define FLASH_CR_STRT_Msk (0x1U << FLASH_CR_STRT_Pos) /*!< 0x00010000 */ #define FLASH_CR_STRT FLASH_CR_STRT_Msk #define FLASH_CR_EOPIE_Pos (24U) #define FLASH_CR_EOPIE_Msk (0x1U << FLASH_CR_EOPIE_Pos) /*!< 0x01000000 */ #define FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk #define FLASH_CR_LOCK_Pos (31U) #define FLASH_CR_LOCK_Msk (0x1U << FLASH_CR_LOCK_Pos) /*!< 0x80000000 */ #define FLASH_CR_LOCK FLASH_CR_LOCK_Msk /******************* Bits definition for FLASH_OPTCR register ***************/ #define FLASH_OPTCR_OPTLOCK_Pos (0U) #define FLASH_OPTCR_OPTLOCK_Msk (0x1U << FLASH_OPTCR_OPTLOCK_Pos) /*!< 0x00000001 */ #define FLASH_OPTCR_OPTLOCK FLASH_OPTCR_OPTLOCK_Msk #define FLASH_OPTCR_OPTSTRT_Pos (1U) #define FLASH_OPTCR_OPTSTRT_Msk (0x1U << FLASH_OPTCR_OPTSTRT_Pos) /*!< 0x00000002 */ #define FLASH_OPTCR_OPTSTRT FLASH_OPTCR_OPTSTRT_Msk #define FLASH_OPTCR_BOR_LEV_0 0x00000004U #define FLASH_OPTCR_BOR_LEV_1 0x00000008U #define FLASH_OPTCR_BOR_LEV_Pos (2U) #define FLASH_OPTCR_BOR_LEV_Msk (0x3U << FLASH_OPTCR_BOR_LEV_Pos) /*!< 0x0000000C */ #define FLASH_OPTCR_BOR_LEV FLASH_OPTCR_BOR_LEV_Msk #define FLASH_OPTCR_BFB2_Pos (4U) #define FLASH_OPTCR_BFB2_Msk (0x1U << FLASH_OPTCR_BFB2_Pos) /*!< 0x00000010 */ #define FLASH_OPTCR_BFB2 FLASH_OPTCR_BFB2_Msk #define FLASH_OPTCR_WDG_SW_Pos (5U) #define FLASH_OPTCR_WDG_SW_Msk (0x1U << FLASH_OPTCR_WDG_SW_Pos) /*!< 0x00000020 */ #define FLASH_OPTCR_WDG_SW FLASH_OPTCR_WDG_SW_Msk #define FLASH_OPTCR_nRST_STOP_Pos (6U) #define FLASH_OPTCR_nRST_STOP_Msk (0x1U << FLASH_OPTCR_nRST_STOP_Pos) /*!< 0x00000040 */ #define FLASH_OPTCR_nRST_STOP FLASH_OPTCR_nRST_STOP_Msk #define FLASH_OPTCR_nRST_STDBY_Pos (7U) #define FLASH_OPTCR_nRST_STDBY_Msk (0x1U << FLASH_OPTCR_nRST_STDBY_Pos) /*!< 0x00000080 */ #define FLASH_OPTCR_nRST_STDBY FLASH_OPTCR_nRST_STDBY_Msk #define FLASH_OPTCR_RDP_Pos (8U) #define FLASH_OPTCR_RDP_Msk (0xFFU << FLASH_OPTCR_RDP_Pos) /*!< 0x0000FF00 */ #define FLASH_OPTCR_RDP FLASH_OPTCR_RDP_Msk #define FLASH_OPTCR_RDP_0 (0x01U << FLASH_OPTCR_RDP_Pos) /*!< 0x00000100 */ #define FLASH_OPTCR_RDP_1 (0x02U << FLASH_OPTCR_RDP_Pos) /*!< 0x00000200 */ #define FLASH_OPTCR_RDP_2 (0x04U << FLASH_OPTCR_RDP_Pos) /*!< 0x00000400 */ #define FLASH_OPTCR_RDP_3 (0x08U << FLASH_OPTCR_RDP_Pos) /*!< 0x00000800 */ #define FLASH_OPTCR_RDP_4 (0x10U << FLASH_OPTCR_RDP_Pos) /*!< 0x00001000 */ #define FLASH_OPTCR_RDP_5 (0x20U << FLASH_OPTCR_RDP_Pos) /*!< 0x00002000 */ #define FLASH_OPTCR_RDP_6 (0x40U << FLASH_OPTCR_RDP_Pos) /*!< 0x00004000 */ #define FLASH_OPTCR_RDP_7 (0x80U << FLASH_OPTCR_RDP_Pos) /*!< 0x00008000 */ #define FLASH_OPTCR_nWRP_Pos (16U) #define FLASH_OPTCR_nWRP_Msk (0xFFFU << FLASH_OPTCR_nWRP_Pos) /*!< 0x0FFF0000 */ #define FLASH_OPTCR_nWRP FLASH_OPTCR_nWRP_Msk #define FLASH_OPTCR_nWRP_0 0x00010000U #define FLASH_OPTCR_nWRP_1 0x00020000U #define FLASH_OPTCR_nWRP_2 0x00040000U #define FLASH_OPTCR_nWRP_3 0x00080000U #define FLASH_OPTCR_nWRP_4 0x00100000U #define FLASH_OPTCR_nWRP_5 0x00200000U #define FLASH_OPTCR_nWRP_6 0x00400000U #define FLASH_OPTCR_nWRP_7 0x00800000U #define FLASH_OPTCR_nWRP_8 0x01000000U #define FLASH_OPTCR_nWRP_9 0x02000000U #define FLASH_OPTCR_nWRP_10 0x04000000U #define FLASH_OPTCR_nWRP_11 0x08000000U #define FLASH_OPTCR_DB1M_Pos (30U) #define FLASH_OPTCR_DB1M_Msk (0x1U << FLASH_OPTCR_DB1M_Pos) /*!< 0x40000000 */ #define FLASH_OPTCR_DB1M FLASH_OPTCR_DB1M_Msk #define FLASH_OPTCR_SPRMOD_Pos (31U) #define FLASH_OPTCR_SPRMOD_Msk (0x1U << FLASH_OPTCR_SPRMOD_Pos) /*!< 0x80000000 */ #define FLASH_OPTCR_SPRMOD FLASH_OPTCR_SPRMOD_Msk /****************** Bits definition for FLASH_OPTCR1 register ***************/ #define FLASH_OPTCR1_nWRP_Pos (16U) #define FLASH_OPTCR1_nWRP_Msk (0xFFFU << FLASH_OPTCR1_nWRP_Pos) /*!< 0x0FFF0000 */ #define FLASH_OPTCR1_nWRP FLASH_OPTCR1_nWRP_Msk #define FLASH_OPTCR1_nWRP_0 (0x001U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00010000 */ #define FLASH_OPTCR1_nWRP_1 (0x002U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00020000 */ #define FLASH_OPTCR1_nWRP_2 (0x004U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00040000 */ #define FLASH_OPTCR1_nWRP_3 (0x008U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00080000 */ #define FLASH_OPTCR1_nWRP_4 (0x010U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00100000 */ #define FLASH_OPTCR1_nWRP_5 (0x020U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00200000 */ #define FLASH_OPTCR1_nWRP_6 (0x040U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00400000 */ #define FLASH_OPTCR1_nWRP_7 (0x080U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00800000 */ #define FLASH_OPTCR1_nWRP_8 (0x100U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x01000000 */ #define FLASH_OPTCR1_nWRP_9 (0x200U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x02000000 */ #define FLASH_OPTCR1_nWRP_10 (0x400U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x04000000 */ #define FLASH_OPTCR1_nWRP_11 (0x800U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x08000000 */ /******************************************************************************/ /* */ /* Flexible Memory Controller */ /* */ /******************************************************************************/ /****************** Bit definition for FMC_BCR1 register *******************/ #define FMC_BCR1_MBKEN_Pos (0U) #define FMC_BCR1_MBKEN_Msk (0x1U << FMC_BCR1_MBKEN_Pos) /*!< 0x00000001 */ #define FMC_BCR1_MBKEN FMC_BCR1_MBKEN_Msk /*!<Memory bank enable bit */ #define FMC_BCR1_MUXEN_Pos (1U) #define FMC_BCR1_MUXEN_Msk (0x1U << FMC_BCR1_MUXEN_Pos) /*!< 0x00000002 */ #define FMC_BCR1_MUXEN FMC_BCR1_MUXEN_Msk /*!<Address/data multiplexing enable bit */ #define FMC_BCR1_MTYP_Pos (2U) #define FMC_BCR1_MTYP_Msk (0x3U << FMC_BCR1_MTYP_Pos) /*!< 0x0000000C */ #define FMC_BCR1_MTYP FMC_BCR1_MTYP_Msk /*!<MTYP[1:0] bits (Memory type) */ #define FMC_BCR1_MTYP_0 (0x1U << FMC_BCR1_MTYP_Pos) /*!< 0x00000004 */ #define FMC_BCR1_MTYP_1 (0x2U << FMC_BCR1_MTYP_Pos) /*!< 0x00000008 */ #define FMC_BCR1_MWID_Pos (4U) #define FMC_BCR1_MWID_Msk (0x3U << FMC_BCR1_MWID_Pos) /*!< 0x00000030 */ #define FMC_BCR1_MWID FMC_BCR1_MWID_Msk /*!<MWID[1:0] bits (Memory data bus width) */ #define FMC_BCR1_MWID_0 (0x1U << FMC_BCR1_MWID_Pos) /*!< 0x00000010 */ #define FMC_BCR1_MWID_1 (0x2U << FMC_BCR1_MWID_Pos) /*!< 0x00000020 */ #define FMC_BCR1_FACCEN_Pos (6U) #define FMC_BCR1_FACCEN_Msk (0x1U << FMC_BCR1_FACCEN_Pos) /*!< 0x00000040 */ #define FMC_BCR1_FACCEN FMC_BCR1_FACCEN_Msk /*!<Flash access enable */ #define FMC_BCR1_BURSTEN_Pos (8U) #define FMC_BCR1_BURSTEN_Msk (0x1U << FMC_BCR1_BURSTEN_Pos) /*!< 0x00000100 */ #define FMC_BCR1_BURSTEN FMC_BCR1_BURSTEN_Msk /*!<Burst enable bit */ #define FMC_BCR1_WAITPOL_Pos (9U) #define FMC_BCR1_WAITPOL_Msk (0x1U << FMC_BCR1_WAITPOL_Pos) /*!< 0x00000200 */ #define FMC_BCR1_WAITPOL FMC_BCR1_WAITPOL_Msk /*!<Wait signal polarity bit */ #define FMC_BCR1_WAITCFG_Pos (11U) #define FMC_BCR1_WAITCFG_Msk (0x1U << FMC_BCR1_WAITCFG_Pos) /*!< 0x00000800 */ #define FMC_BCR1_WAITCFG FMC_BCR1_WAITCFG_Msk /*!<Wait timing configuration */ #define FMC_BCR1_WREN_Pos (12U) #define FMC_BCR1_WREN_Msk (0x1U << FMC_BCR1_WREN_Pos) /*!< 0x00001000 */ #define FMC_BCR1_WREN FMC_BCR1_WREN_Msk /*!<Write enable bit */ #define FMC_BCR1_WAITEN_Pos (13U) #define FMC_BCR1_WAITEN_Msk (0x1U << FMC_BCR1_WAITEN_Pos) /*!< 0x00002000 */ #define FMC_BCR1_WAITEN FMC_BCR1_WAITEN_Msk /*!<Wait enable bit */ #define FMC_BCR1_EXTMOD_Pos (14U) #define FMC_BCR1_EXTMOD_Msk (0x1U << FMC_BCR1_EXTMOD_Pos) /*!< 0x00004000 */ #define FMC_BCR1_EXTMOD FMC_BCR1_EXTMOD_Msk /*!<Extended mode enable */ #define FMC_BCR1_ASYNCWAIT_Pos (15U) #define FMC_BCR1_ASYNCWAIT_Msk (0x1U << FMC_BCR1_ASYNCWAIT_Pos) /*!< 0x00008000 */ #define FMC_BCR1_ASYNCWAIT FMC_BCR1_ASYNCWAIT_Msk /*!<Asynchronous wait */ #define FMC_BCR1_CPSIZE_Pos (16U) #define FMC_BCR1_CPSIZE_Msk (0x7U << FMC_BCR1_CPSIZE_Pos) /*!< 0x00070000 */ #define FMC_BCR1_CPSIZE FMC_BCR1_CPSIZE_Msk /*!<CRAM page size */ #define FMC_BCR1_CPSIZE_0 (0x1U << FMC_BCR1_CPSIZE_Pos) /*!< 0x00010000 */ #define FMC_BCR1_CPSIZE_1 (0x2U << FMC_BCR1_CPSIZE_Pos) /*!< 0x00020000 */ #define FMC_BCR1_CPSIZE_2 (0x4U << FMC_BCR1_CPSIZE_Pos) /*!< 0x00040000 */ #define FMC_BCR1_CBURSTRW_Pos (19U) #define FMC_BCR1_CBURSTRW_Msk (0x1U << FMC_BCR1_CBURSTRW_Pos) /*!< 0x00080000 */ #define FMC_BCR1_CBURSTRW FMC_BCR1_CBURSTRW_Msk /*!<Write burst enable */ #define FMC_BCR1_CCLKEN_Pos (20U) #define FMC_BCR1_CCLKEN_Msk (0x1U << FMC_BCR1_CCLKEN_Pos) /*!< 0x00100000 */ #define FMC_BCR1_CCLKEN FMC_BCR1_CCLKEN_Msk /*!<Continous clock enable */ #define FMC_BCR1_WFDIS_Pos (21U) #define FMC_BCR1_WFDIS_Msk (0x1U << FMC_BCR1_WFDIS_Pos) /*!< 0x00200000 */ #define FMC_BCR1_WFDIS FMC_BCR1_WFDIS_Msk /*!<Write FIFO Disable */ /****************** Bit definition for FMC_BCR2 register *******************/ #define FMC_BCR2_MBKEN_Pos (0U) #define FMC_BCR2_MBKEN_Msk (0x1U << FMC_BCR2_MBKEN_Pos) /*!< 0x00000001 */ #define FMC_BCR2_MBKEN FMC_BCR2_MBKEN_Msk /*!<Memory bank enable bit */ #define FMC_BCR2_MUXEN_Pos (1U) #define FMC_BCR2_MUXEN_Msk (0x1U << FMC_BCR2_MUXEN_Pos) /*!< 0x00000002 */ #define FMC_BCR2_MUXEN FMC_BCR2_MUXEN_Msk /*!<Address/data multiplexing enable bit */ #define FMC_BCR2_MTYP_Pos (2U) #define FMC_BCR2_MTYP_Msk (0x3U << FMC_BCR2_MTYP_Pos) /*!< 0x0000000C */ #define FMC_BCR2_MTYP FMC_BCR2_MTYP_Msk /*!<MTYP[1:0] bits (Memory type) */ #define FMC_BCR2_MTYP_0 (0x1U << FMC_BCR2_MTYP_Pos) /*!< 0x00000004 */ #define FMC_BCR2_MTYP_1 (0x2U << FMC_BCR2_MTYP_Pos) /*!< 0x00000008 */ #define FMC_BCR2_MWID_Pos (4U) #define FMC_BCR2_MWID_Msk (0x3U << FMC_BCR2_MWID_Pos) /*!< 0x00000030 */ #define FMC_BCR2_MWID FMC_BCR2_MWID_Msk /*!<MWID[1:0] bits (Memory data bus width) */ #define FMC_BCR2_MWID_0 (0x1U << FMC_BCR2_MWID_Pos) /*!< 0x00000010 */ #define FMC_BCR2_MWID_1 (0x2U << FMC_BCR2_MWID_Pos) /*!< 0x00000020 */ #define FMC_BCR2_FACCEN_Pos (6U) #define FMC_BCR2_FACCEN_Msk (0x1U << FMC_BCR2_FACCEN_Pos) /*!< 0x00000040 */ #define FMC_BCR2_FACCEN FMC_BCR2_FACCEN_Msk /*!<Flash access enable */ #define FMC_BCR2_BURSTEN_Pos (8U) #define FMC_BCR2_BURSTEN_Msk (0x1U << FMC_BCR2_BURSTEN_Pos) /*!< 0x00000100 */ #define FMC_BCR2_BURSTEN FMC_BCR2_BURSTEN_Msk /*!<Burst enable bit */ #define FMC_BCR2_WAITPOL_Pos (9U) #define FMC_BCR2_WAITPOL_Msk (0x1U << FMC_BCR2_WAITPOL_Pos) /*!< 0x00000200 */ #define FMC_BCR2_WAITPOL FMC_BCR2_WAITPOL_Msk /*!<Wait signal polarity bit */ #define FMC_BCR2_WAITCFG_Pos (11U) #define FMC_BCR2_WAITCFG_Msk (0x1U << FMC_BCR2_WAITCFG_Pos) /*!< 0x00000800 */ #define FMC_BCR2_WAITCFG FMC_BCR2_WAITCFG_Msk /*!<Wait timing configuration */ #define FMC_BCR2_WREN_Pos (12U) #define FMC_BCR2_WREN_Msk (0x1U << FMC_BCR2_WREN_Pos) /*!< 0x00001000 */ #define FMC_BCR2_WREN FMC_BCR2_WREN_Msk /*!<Write enable bit */ #define FMC_BCR2_WAITEN_Pos (13U) #define FMC_BCR2_WAITEN_Msk (0x1U << FMC_BCR2_WAITEN_Pos) /*!< 0x00002000 */ #define FMC_BCR2_WAITEN FMC_BCR2_WAITEN_Msk /*!<Wait enable bit */ #define FMC_BCR2_EXTMOD_Pos (14U) #define FMC_BCR2_EXTMOD_Msk (0x1U << FMC_BCR2_EXTMOD_Pos) /*!< 0x00004000 */ #define FMC_BCR2_EXTMOD FMC_BCR2_EXTMOD_Msk /*!<Extended mode enable */ #define FMC_BCR2_ASYNCWAIT_Pos (15U) #define FMC_BCR2_ASYNCWAIT_Msk (0x1U << FMC_BCR2_ASYNCWAIT_Pos) /*!< 0x00008000 */ #define FMC_BCR2_ASYNCWAIT FMC_BCR2_ASYNCWAIT_Msk /*!<Asynchronous wait */ #define FMC_BCR2_CBURSTRW_Pos (19U) #define FMC_BCR2_CBURSTRW_Msk (0x1U << FMC_BCR2_CBURSTRW_Pos) /*!< 0x00080000 */ #define FMC_BCR2_CBURSTRW FMC_BCR2_CBURSTRW_Msk /*!<Write burst enable */ /****************** Bit definition for FMC_BCR3 register *******************/ #define FMC_BCR3_MBKEN_Pos (0U) #define FMC_BCR3_MBKEN_Msk (0x1U << FMC_BCR3_MBKEN_Pos) /*!< 0x00000001 */ #define FMC_BCR3_MBKEN FMC_BCR3_MBKEN_Msk /*!<Memory bank enable bit */ #define FMC_BCR3_MUXEN_Pos (1U) #define FMC_BCR3_MUXEN_Msk (0x1U << FMC_BCR3_MUXEN_Pos) /*!< 0x00000002 */ #define FMC_BCR3_MUXEN FMC_BCR3_MUXEN_Msk /*!<Address/data multiplexing enable bit */ #define FMC_BCR3_MTYP_Pos (2U) #define FMC_BCR3_MTYP_Msk (0x3U << FMC_BCR3_MTYP_Pos) /*!< 0x0000000C */ #define FMC_BCR3_MTYP FMC_BCR3_MTYP_Msk /*!<MTYP[1:0] bits (Memory type) */ #define FMC_BCR3_MTYP_0 (0x1U << FMC_BCR3_MTYP_Pos) /*!< 0x00000004 */ #define FMC_BCR3_MTYP_1 (0x2U << FMC_BCR3_MTYP_Pos) /*!< 0x00000008 */ #define FMC_BCR3_MWID_Pos (4U) #define FMC_BCR3_MWID_Msk (0x3U << FMC_BCR3_MWID_Pos) /*!< 0x00000030 */ #define FMC_BCR3_MWID FMC_BCR3_MWID_Msk /*!<MWID[1:0] bits (Memory data bus width) */ #define FMC_BCR3_MWID_0 (0x1U << FMC_BCR3_MWID_Pos) /*!< 0x00000010 */ #define FMC_BCR3_MWID_1 (0x2U << FMC_BCR3_MWID_Pos) /*!< 0x00000020 */ #define FMC_BCR3_FACCEN_Pos (6U) #define FMC_BCR3_FACCEN_Msk (0x1U << FMC_BCR3_FACCEN_Pos) /*!< 0x00000040 */ #define FMC_BCR3_FACCEN FMC_BCR3_FACCEN_Msk /*!<Flash access enable */ #define FMC_BCR3_BURSTEN_Pos (8U) #define FMC_BCR3_BURSTEN_Msk (0x1U << FMC_BCR3_BURSTEN_Pos) /*!< 0x00000100 */ #define FMC_BCR3_BURSTEN FMC_BCR3_BURSTEN_Msk /*!<Burst enable bit */ #define FMC_BCR3_WAITPOL_Pos (9U) #define FMC_BCR3_WAITPOL_Msk (0x1U << FMC_BCR3_WAITPOL_Pos) /*!< 0x00000200 */ #define FMC_BCR3_WAITPOL FMC_BCR3_WAITPOL_Msk /*!<Wait signal polarity bit */ #define FMC_BCR3_WAITCFG_Pos (11U) #define FMC_BCR3_WAITCFG_Msk (0x1U << FMC_BCR3_WAITCFG_Pos) /*!< 0x00000800 */ #define FMC_BCR3_WAITCFG FMC_BCR3_WAITCFG_Msk /*!<Wait timing configuration */ #define FMC_BCR3_WREN_Pos (12U) #define FMC_BCR3_WREN_Msk (0x1U << FMC_BCR3_WREN_Pos) /*!< 0x00001000 */ #define FMC_BCR3_WREN FMC_BCR3_WREN_Msk /*!<Write enable bit */ #define FMC_BCR3_WAITEN_Pos (13U) #define FMC_BCR3_WAITEN_Msk (0x1U << FMC_BCR3_WAITEN_Pos) /*!< 0x00002000 */ #define FMC_BCR3_WAITEN FMC_BCR3_WAITEN_Msk /*!<Wait enable bit */ #define FMC_BCR3_EXTMOD_Pos (14U) #define FMC_BCR3_EXTMOD_Msk (0x1U << FMC_BCR3_EXTMOD_Pos) /*!< 0x00004000 */ #define FMC_BCR3_EXTMOD FMC_BCR3_EXTMOD_Msk /*!<Extended mode enable */ #define FMC_BCR3_ASYNCWAIT_Pos (15U) #define FMC_BCR3_ASYNCWAIT_Msk (0x1U << FMC_BCR3_ASYNCWAIT_Pos) /*!< 0x00008000 */ #define FMC_BCR3_ASYNCWAIT FMC_BCR3_ASYNCWAIT_Msk /*!<Asynchronous wait */ #define FMC_BCR3_CBURSTRW_Pos (19U) #define FMC_BCR3_CBURSTRW_Msk (0x1U << FMC_BCR3_CBURSTRW_Pos) /*!< 0x00080000 */ #define FMC_BCR3_CBURSTRW FMC_BCR3_CBURSTRW_Msk /*!<Write burst enable */ /****************** Bit definition for FMC_BCR4 register *******************/ #define FMC_BCR4_MBKEN_Pos (0U) #define FMC_BCR4_MBKEN_Msk (0x1U << FMC_BCR4_MBKEN_Pos) /*!< 0x00000001 */ #define FMC_BCR4_MBKEN FMC_BCR4_MBKEN_Msk /*!<Memory bank enable bit */ #define FMC_BCR4_MUXEN_Pos (1U) #define FMC_BCR4_MUXEN_Msk (0x1U << FMC_BCR4_MUXEN_Pos) /*!< 0x00000002 */ #define FMC_BCR4_MUXEN FMC_BCR4_MUXEN_Msk /*!<Address/data multiplexing enable bit */ #define FMC_BCR4_MTYP_Pos (2U) #define FMC_BCR4_MTYP_Msk (0x3U << FMC_BCR4_MTYP_Pos) /*!< 0x0000000C */ #define FMC_BCR4_MTYP FMC_BCR4_MTYP_Msk /*!<MTYP[1:0] bits (Memory type) */ #define FMC_BCR4_MTYP_0 (0x1U << FMC_BCR4_MTYP_Pos) /*!< 0x00000004 */ #define FMC_BCR4_MTYP_1 (0x2U << FMC_BCR4_MTYP_Pos) /*!< 0x00000008 */ #define FMC_BCR4_MWID_Pos (4U) #define FMC_BCR4_MWID_Msk (0x3U << FMC_BCR4_MWID_Pos) /*!< 0x00000030 */ #define FMC_BCR4_MWID FMC_BCR4_MWID_Msk /*!<MWID[1:0] bits (Memory data bus width) */ #define FMC_BCR4_MWID_0 (0x1U << FMC_BCR4_MWID_Pos) /*!< 0x00000010 */ #define FMC_BCR4_MWID_1 (0x2U << FMC_BCR4_MWID_Pos) /*!< 0x00000020 */ #define FMC_BCR4_FACCEN_Pos (6U) #define FMC_BCR4_FACCEN_Msk (0x1U << FMC_BCR4_FACCEN_Pos) /*!< 0x00000040 */ #define FMC_BCR4_FACCEN FMC_BCR4_FACCEN_Msk /*!<Flash access enable */ #define FMC_BCR4_BURSTEN_Pos (8U) #define FMC_BCR4_BURSTEN_Msk (0x1U << FMC_BCR4_BURSTEN_Pos) /*!< 0x00000100 */ #define FMC_BCR4_BURSTEN FMC_BCR4_BURSTEN_Msk /*!<Burst enable bit */ #define FMC_BCR4_WAITPOL_Pos (9U) #define FMC_BCR4_WAITPOL_Msk (0x1U << FMC_BCR4_WAITPOL_Pos) /*!< 0x00000200 */ #define FMC_BCR4_WAITPOL FMC_BCR4_WAITPOL_Msk /*!<Wait signal polarity bit */ #define FMC_BCR4_WAITCFG_Pos (11U) #define FMC_BCR4_WAITCFG_Msk (0x1U << FMC_BCR4_WAITCFG_Pos) /*!< 0x00000800 */ #define FMC_BCR4_WAITCFG FMC_BCR4_WAITCFG_Msk /*!<Wait timing configuration */ #define FMC_BCR4_WREN_Pos (12U) #define FMC_BCR4_WREN_Msk (0x1U << FMC_BCR4_WREN_Pos) /*!< 0x00001000 */ #define FMC_BCR4_WREN FMC_BCR4_WREN_Msk /*!<Write enable bit */ #define FMC_BCR4_WAITEN_Pos (13U) #define FMC_BCR4_WAITEN_Msk (0x1U << FMC_BCR4_WAITEN_Pos) /*!< 0x00002000 */ #define FMC_BCR4_WAITEN FMC_BCR4_WAITEN_Msk /*!<Wait enable bit */ #define FMC_BCR4_EXTMOD_Pos (14U) #define FMC_BCR4_EXTMOD_Msk (0x1U << FMC_BCR4_EXTMOD_Pos) /*!< 0x00004000 */ #define FMC_BCR4_EXTMOD FMC_BCR4_EXTMOD_Msk /*!<Extended mode enable */ #define FMC_BCR4_ASYNCWAIT_Pos (15U) #define FMC_BCR4_ASYNCWAIT_Msk (0x1U << FMC_BCR4_ASYNCWAIT_Pos) /*!< 0x00008000 */ #define FMC_BCR4_ASYNCWAIT FMC_BCR4_ASYNCWAIT_Msk /*!<Asynchronous wait */ #define FMC_BCR4_CBURSTRW_Pos (19U) #define FMC_BCR4_CBURSTRW_Msk (0x1U << FMC_BCR4_CBURSTRW_Pos) /*!< 0x00080000 */ #define FMC_BCR4_CBURSTRW FMC_BCR4_CBURSTRW_Msk /*!<Write burst enable */ /****************** Bit definition for FMC_BTR1 register ******************/ #define FMC_BTR1_ADDSET_Pos (0U) #define FMC_BTR1_ADDSET_Msk (0xFU << FMC_BTR1_ADDSET_Pos) /*!< 0x0000000F */ #define FMC_BTR1_ADDSET FMC_BTR1_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */ #define FMC_BTR1_ADDSET_0 (0x1U << FMC_BTR1_ADDSET_Pos) /*!< 0x00000001 */ #define FMC_BTR1_ADDSET_1 (0x2U << FMC_BTR1_ADDSET_Pos) /*!< 0x00000002 */ #define FMC_BTR1_ADDSET_2 (0x4U << FMC_BTR1_ADDSET_Pos) /*!< 0x00000004 */ #define FMC_BTR1_ADDSET_3 (0x8U << FMC_BTR1_ADDSET_Pos) /*!< 0x00000008 */ #define FMC_BTR1_ADDHLD_Pos (4U) #define FMC_BTR1_ADDHLD_Msk (0xFU << FMC_BTR1_ADDHLD_Pos) /*!< 0x000000F0 */ #define FMC_BTR1_ADDHLD FMC_BTR1_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */ #define FMC_BTR1_ADDHLD_0 (0x1U << FMC_BTR1_ADDHLD_Pos) /*!< 0x00000010 */ #define FMC_BTR1_ADDHLD_1 (0x2U << FMC_BTR1_ADDHLD_Pos) /*!< 0x00000020 */ #define FMC_BTR1_ADDHLD_2 (0x4U << FMC_BTR1_ADDHLD_Pos) /*!< 0x00000040 */ #define FMC_BTR1_ADDHLD_3 (0x8U << FMC_BTR1_ADDHLD_Pos) /*!< 0x00000080 */ #define FMC_BTR1_DATAST_Pos (8U) #define FMC_BTR1_DATAST_Msk (0xFFU << FMC_BTR1_DATAST_Pos) /*!< 0x0000FF00 */ #define FMC_BTR1_DATAST FMC_BTR1_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */ #define FMC_BTR1_DATAST_0 (0x01U << FMC_BTR1_DATAST_Pos) /*!< 0x00000100 */ #define FMC_BTR1_DATAST_1 (0x02U << FMC_BTR1_DATAST_Pos) /*!< 0x00000200 */ #define FMC_BTR1_DATAST_2 (0x04U << FMC_BTR1_DATAST_Pos) /*!< 0x00000400 */ #define FMC_BTR1_DATAST_3 (0x08U << FMC_BTR1_DATAST_Pos) /*!< 0x00000800 */ #define FMC_BTR1_DATAST_4 (0x10U << FMC_BTR1_DATAST_Pos) /*!< 0x00001000 */ #define FMC_BTR1_DATAST_5 (0x20U << FMC_BTR1_DATAST_Pos) /*!< 0x00002000 */ #define FMC_BTR1_DATAST_6 (0x40U << FMC_BTR1_DATAST_Pos) /*!< 0x00004000 */ #define FMC_BTR1_DATAST_7 (0x80U << FMC_BTR1_DATAST_Pos) /*!< 0x00008000 */ #define FMC_BTR1_BUSTURN_Pos (16U) #define FMC_BTR1_BUSTURN_Msk (0xFU << FMC_BTR1_BUSTURN_Pos) /*!< 0x000F0000 */ #define FMC_BTR1_BUSTURN FMC_BTR1_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */ #define FMC_BTR1_BUSTURN_0 (0x1U << FMC_BTR1_BUSTURN_Pos) /*!< 0x00010000 */ #define FMC_BTR1_BUSTURN_1 (0x2U << FMC_BTR1_BUSTURN_Pos) /*!< 0x00020000 */ #define FMC_BTR1_BUSTURN_2 (0x4U << FMC_BTR1_BUSTURN_Pos) /*!< 0x00040000 */ #define FMC_BTR1_BUSTURN_3 (0x8U << FMC_BTR1_BUSTURN_Pos) /*!< 0x00080000 */ #define FMC_BTR1_CLKDIV_Pos (20U) #define FMC_BTR1_CLKDIV_Msk (0xFU << FMC_BTR1_CLKDIV_Pos) /*!< 0x00F00000 */ #define FMC_BTR1_CLKDIV FMC_BTR1_CLKDIV_Msk /*!<CLKDIV[3:0] bits (Clock divide ratio) */ #define FMC_BTR1_CLKDIV_0 (0x1U << FMC_BTR1_CLKDIV_Pos) /*!< 0x00100000 */ #define FMC_BTR1_CLKDIV_1 (0x2U << FMC_BTR1_CLKDIV_Pos) /*!< 0x00200000 */ #define FMC_BTR1_CLKDIV_2 (0x4U << FMC_BTR1_CLKDIV_Pos) /*!< 0x00400000 */ #define FMC_BTR1_CLKDIV_3 (0x8U << FMC_BTR1_CLKDIV_Pos) /*!< 0x00800000 */ #define FMC_BTR1_DATLAT_Pos (24U) #define FMC_BTR1_DATLAT_Msk (0xFU << FMC_BTR1_DATLAT_Pos) /*!< 0x0F000000 */ #define FMC_BTR1_DATLAT FMC_BTR1_DATLAT_Msk /*!<DATLA[3:0] bits (Data latency) */ #define FMC_BTR1_DATLAT_0 (0x1U << FMC_BTR1_DATLAT_Pos) /*!< 0x01000000 */ #define FMC_BTR1_DATLAT_1 (0x2U << FMC_BTR1_DATLAT_Pos) /*!< 0x02000000 */ #define FMC_BTR1_DATLAT_2 (0x4U << FMC_BTR1_DATLAT_Pos) /*!< 0x04000000 */ #define FMC_BTR1_DATLAT_3 (0x8U << FMC_BTR1_DATLAT_Pos) /*!< 0x08000000 */ #define FMC_BTR1_ACCMOD_Pos (28U) #define FMC_BTR1_ACCMOD_Msk (0x3U << FMC_BTR1_ACCMOD_Pos) /*!< 0x30000000 */ #define FMC_BTR1_ACCMOD FMC_BTR1_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */ #define FMC_BTR1_ACCMOD_0 (0x1U << FMC_BTR1_ACCMOD_Pos) /*!< 0x10000000 */ #define FMC_BTR1_ACCMOD_1 (0x2U << FMC_BTR1_ACCMOD_Pos) /*!< 0x20000000 */ /****************** Bit definition for FMC_BTR2 register *******************/ #define FMC_BTR2_ADDSET_Pos (0U) #define FMC_BTR2_ADDSET_Msk (0xFU << FMC_BTR2_ADDSET_Pos) /*!< 0x0000000F */ #define FMC_BTR2_ADDSET FMC_BTR2_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */ #define FMC_BTR2_ADDSET_0 (0x1U << FMC_BTR2_ADDSET_Pos) /*!< 0x00000001 */ #define FMC_BTR2_ADDSET_1 (0x2U << FMC_BTR2_ADDSET_Pos) /*!< 0x00000002 */ #define FMC_BTR2_ADDSET_2 (0x4U << FMC_BTR2_ADDSET_Pos) /*!< 0x00000004 */ #define FMC_BTR2_ADDSET_3 (0x8U << FMC_BTR2_ADDSET_Pos) /*!< 0x00000008 */ #define FMC_BTR2_ADDHLD_Pos (4U) #define FMC_BTR2_ADDHLD_Msk (0xFU << FMC_BTR2_ADDHLD_Pos) /*!< 0x000000F0 */ #define FMC_BTR2_ADDHLD FMC_BTR2_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */ #define FMC_BTR2_ADDHLD_0 (0x1U << FMC_BTR2_ADDHLD_Pos) /*!< 0x00000010 */ #define FMC_BTR2_ADDHLD_1 (0x2U << FMC_BTR2_ADDHLD_Pos) /*!< 0x00000020 */ #define FMC_BTR2_ADDHLD_2 (0x4U << FMC_BTR2_ADDHLD_Pos) /*!< 0x00000040 */ #define FMC_BTR2_ADDHLD_3 (0x8U << FMC_BTR2_ADDHLD_Pos) /*!< 0x00000080 */ #define FMC_BTR2_DATAST_Pos (8U) #define FMC_BTR2_DATAST_Msk (0xFFU << FMC_BTR2_DATAST_Pos) /*!< 0x0000FF00 */ #define FMC_BTR2_DATAST FMC_BTR2_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */ #define FMC_BTR2_DATAST_0 (0x01U << FMC_BTR2_DATAST_Pos) /*!< 0x00000100 */ #define FMC_BTR2_DATAST_1 (0x02U << FMC_BTR2_DATAST_Pos) /*!< 0x00000200 */ #define FMC_BTR2_DATAST_2 (0x04U << FMC_BTR2_DATAST_Pos) /*!< 0x00000400 */ #define FMC_BTR2_DATAST_3 (0x08U << FMC_BTR2_DATAST_Pos) /*!< 0x00000800 */ #define FMC_BTR2_DATAST_4 (0x10U << FMC_BTR2_DATAST_Pos) /*!< 0x00001000 */ #define FMC_BTR2_DATAST_5 (0x20U << FMC_BTR2_DATAST_Pos) /*!< 0x00002000 */ #define FMC_BTR2_DATAST_6 (0x40U << FMC_BTR2_DATAST_Pos) /*!< 0x00004000 */ #define FMC_BTR2_DATAST_7 (0x80U << FMC_BTR2_DATAST_Pos) /*!< 0x00008000 */ #define FMC_BTR2_BUSTURN_Pos (16U) #define FMC_BTR2_BUSTURN_Msk (0xFU << FMC_BTR2_BUSTURN_Pos) /*!< 0x000F0000 */ #define FMC_BTR2_BUSTURN FMC_BTR2_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */ #define FMC_BTR2_BUSTURN_0 (0x1U << FMC_BTR2_BUSTURN_Pos) /*!< 0x00010000 */ #define FMC_BTR2_BUSTURN_1 (0x2U << FMC_BTR2_BUSTURN_Pos) /*!< 0x00020000 */ #define FMC_BTR2_BUSTURN_2 (0x4U << FMC_BTR2_BUSTURN_Pos) /*!< 0x00040000 */ #define FMC_BTR2_BUSTURN_3 (0x8U << FMC_BTR2_BUSTURN_Pos) /*!< 0x00080000 */ #define FMC_BTR2_CLKDIV_Pos (20U) #define FMC_BTR2_CLKDIV_Msk (0xFU << FMC_BTR2_CLKDIV_Pos) /*!< 0x00F00000 */ #define FMC_BTR2_CLKDIV FMC_BTR2_CLKDIV_Msk /*!<CLKDIV[3:0] bits (Clock divide ratio) */ #define FMC_BTR2_CLKDIV_0 (0x1U << FMC_BTR2_CLKDIV_Pos) /*!< 0x00100000 */ #define FMC_BTR2_CLKDIV_1 (0x2U << FMC_BTR2_CLKDIV_Pos) /*!< 0x00200000 */ #define FMC_BTR2_CLKDIV_2 (0x4U << FMC_BTR2_CLKDIV_Pos) /*!< 0x00400000 */ #define FMC_BTR2_CLKDIV_3 (0x8U << FMC_BTR2_CLKDIV_Pos) /*!< 0x00800000 */ #define FMC_BTR2_DATLAT_Pos (24U) #define FMC_BTR2_DATLAT_Msk (0xFU << FMC_BTR2_DATLAT_Pos) /*!< 0x0F000000 */ #define FMC_BTR2_DATLAT FMC_BTR2_DATLAT_Msk /*!<DATLA[3:0] bits (Data latency) */ #define FMC_BTR2_DATLAT_0 (0x1U << FMC_BTR2_DATLAT_Pos) /*!< 0x01000000 */ #define FMC_BTR2_DATLAT_1 (0x2U << FMC_BTR2_DATLAT_Pos) /*!< 0x02000000 */ #define FMC_BTR2_DATLAT_2 (0x4U << FMC_BTR2_DATLAT_Pos) /*!< 0x04000000 */ #define FMC_BTR2_DATLAT_3 (0x8U << FMC_BTR2_DATLAT_Pos) /*!< 0x08000000 */ #define FMC_BTR2_ACCMOD_Pos (28U) #define FMC_BTR2_ACCMOD_Msk (0x3U << FMC_BTR2_ACCMOD_Pos) /*!< 0x30000000 */ #define FMC_BTR2_ACCMOD FMC_BTR2_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */ #define FMC_BTR2_ACCMOD_0 (0x1U << FMC_BTR2_ACCMOD_Pos) /*!< 0x10000000 */ #define FMC_BTR2_ACCMOD_1 (0x2U << FMC_BTR2_ACCMOD_Pos) /*!< 0x20000000 */ /******************* Bit definition for FMC_BTR3 register *******************/ #define FMC_BTR3_ADDSET_Pos (0U) #define FMC_BTR3_ADDSET_Msk (0xFU << FMC_BTR3_ADDSET_Pos) /*!< 0x0000000F */ #define FMC_BTR3_ADDSET FMC_BTR3_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */ #define FMC_BTR3_ADDSET_0 (0x1U << FMC_BTR3_ADDSET_Pos) /*!< 0x00000001 */ #define FMC_BTR3_ADDSET_1 (0x2U << FMC_BTR3_ADDSET_Pos) /*!< 0x00000002 */ #define FMC_BTR3_ADDSET_2 (0x4U << FMC_BTR3_ADDSET_Pos) /*!< 0x00000004 */ #define FMC_BTR3_ADDSET_3 (0x8U << FMC_BTR3_ADDSET_Pos) /*!< 0x00000008 */ #define FMC_BTR3_ADDHLD_Pos (4U) #define FMC_BTR3_ADDHLD_Msk (0xFU << FMC_BTR3_ADDHLD_Pos) /*!< 0x000000F0 */ #define FMC_BTR3_ADDHLD FMC_BTR3_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */ #define FMC_BTR3_ADDHLD_0 (0x1U << FMC_BTR3_ADDHLD_Pos) /*!< 0x00000010 */ #define FMC_BTR3_ADDHLD_1 (0x2U << FMC_BTR3_ADDHLD_Pos) /*!< 0x00000020 */ #define FMC_BTR3_ADDHLD_2 (0x4U << FMC_BTR3_ADDHLD_Pos) /*!< 0x00000040 */ #define FMC_BTR3_ADDHLD_3 (0x8U << FMC_BTR3_ADDHLD_Pos) /*!< 0x00000080 */ #define FMC_BTR3_DATAST_Pos (8U) #define FMC_BTR3_DATAST_Msk (0xFFU << FMC_BTR3_DATAST_Pos) /*!< 0x0000FF00 */ #define FMC_BTR3_DATAST FMC_BTR3_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */ #define FMC_BTR3_DATAST_0 (0x01U << FMC_BTR3_DATAST_Pos) /*!< 0x00000100 */ #define FMC_BTR3_DATAST_1 (0x02U << FMC_BTR3_DATAST_Pos) /*!< 0x00000200 */ #define FMC_BTR3_DATAST_2 (0x04U << FMC_BTR3_DATAST_Pos) /*!< 0x00000400 */ #define FMC_BTR3_DATAST_3 (0x08U << FMC_BTR3_DATAST_Pos) /*!< 0x00000800 */ #define FMC_BTR3_DATAST_4 (0x10U << FMC_BTR3_DATAST_Pos) /*!< 0x00001000 */ #define FMC_BTR3_DATAST_5 (0x20U << FMC_BTR3_DATAST_Pos) /*!< 0x00002000 */ #define FMC_BTR3_DATAST_6 (0x40U << FMC_BTR3_DATAST_Pos) /*!< 0x00004000 */ #define FMC_BTR3_DATAST_7 (0x80U << FMC_BTR3_DATAST_Pos) /*!< 0x00008000 */ #define FMC_BTR3_BUSTURN_Pos (16U) #define FMC_BTR3_BUSTURN_Msk (0xFU << FMC_BTR3_BUSTURN_Pos) /*!< 0x000F0000 */ #define FMC_BTR3_BUSTURN FMC_BTR3_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */ #define FMC_BTR3_BUSTURN_0 (0x1U << FMC_BTR3_BUSTURN_Pos) /*!< 0x00010000 */ #define FMC_BTR3_BUSTURN_1 (0x2U << FMC_BTR3_BUSTURN_Pos) /*!< 0x00020000 */ #define FMC_BTR3_BUSTURN_2 (0x4U << FMC_BTR3_BUSTURN_Pos) /*!< 0x00040000 */ #define FMC_BTR3_BUSTURN_3 (0x8U << FMC_BTR3_BUSTURN_Pos) /*!< 0x00080000 */ #define FMC_BTR3_CLKDIV_Pos (20U) #define FMC_BTR3_CLKDIV_Msk (0xFU << FMC_BTR3_CLKDIV_Pos) /*!< 0x00F00000 */ #define FMC_BTR3_CLKDIV FMC_BTR3_CLKDIV_Msk /*!<CLKDIV[3:0] bits (Clock divide ratio) */ #define FMC_BTR3_CLKDIV_0 (0x1U << FMC_BTR3_CLKDIV_Pos) /*!< 0x00100000 */ #define FMC_BTR3_CLKDIV_1 (0x2U << FMC_BTR3_CLKDIV_Pos) /*!< 0x00200000 */ #define FMC_BTR3_CLKDIV_2 (0x4U << FMC_BTR3_CLKDIV_Pos) /*!< 0x00400000 */ #define FMC_BTR3_CLKDIV_3 (0x8U << FMC_BTR3_CLKDIV_Pos) /*!< 0x00800000 */ #define FMC_BTR3_DATLAT_Pos (24U) #define FMC_BTR3_DATLAT_Msk (0xFU << FMC_BTR3_DATLAT_Pos) /*!< 0x0F000000 */ #define FMC_BTR3_DATLAT FMC_BTR3_DATLAT_Msk /*!<DATLA[3:0] bits (Data latency) */ #define FMC_BTR3_DATLAT_0 (0x1U << FMC_BTR3_DATLAT_Pos) /*!< 0x01000000 */ #define FMC_BTR3_DATLAT_1 (0x2U << FMC_BTR3_DATLAT_Pos) /*!< 0x02000000 */ #define FMC_BTR3_DATLAT_2 (0x4U << FMC_BTR3_DATLAT_Pos) /*!< 0x04000000 */ #define FMC_BTR3_DATLAT_3 (0x8U << FMC_BTR3_DATLAT_Pos) /*!< 0x08000000 */ #define FMC_BTR3_ACCMOD_Pos (28U) #define FMC_BTR3_ACCMOD_Msk (0x3U << FMC_BTR3_ACCMOD_Pos) /*!< 0x30000000 */ #define FMC_BTR3_ACCMOD FMC_BTR3_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */ #define FMC_BTR3_ACCMOD_0 (0x1U << FMC_BTR3_ACCMOD_Pos) /*!< 0x10000000 */ #define FMC_BTR3_ACCMOD_1 (0x2U << FMC_BTR3_ACCMOD_Pos) /*!< 0x20000000 */ /****************** Bit definition for FMC_BTR4 register *******************/ #define FMC_BTR4_ADDSET_Pos (0U) #define FMC_BTR4_ADDSET_Msk (0xFU << FMC_BTR4_ADDSET_Pos) /*!< 0x0000000F */ #define FMC_BTR4_ADDSET FMC_BTR4_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */ #define FMC_BTR4_ADDSET_0 (0x1U << FMC_BTR4_ADDSET_Pos) /*!< 0x00000001 */ #define FMC_BTR4_ADDSET_1 (0x2U << FMC_BTR4_ADDSET_Pos) /*!< 0x00000002 */ #define FMC_BTR4_ADDSET_2 (0x4U << FMC_BTR4_ADDSET_Pos) /*!< 0x00000004 */ #define FMC_BTR4_ADDSET_3 (0x8U << FMC_BTR4_ADDSET_Pos) /*!< 0x00000008 */ #define FMC_BTR4_ADDHLD_Pos (4U) #define FMC_BTR4_ADDHLD_Msk (0xFU << FMC_BTR4_ADDHLD_Pos) /*!< 0x000000F0 */ #define FMC_BTR4_ADDHLD FMC_BTR4_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */ #define FMC_BTR4_ADDHLD_0 (0x1U << FMC_BTR4_ADDHLD_Pos) /*!< 0x00000010 */ #define FMC_BTR4_ADDHLD_1 (0x2U << FMC_BTR4_ADDHLD_Pos) /*!< 0x00000020 */ #define FMC_BTR4_ADDHLD_2 (0x4U << FMC_BTR4_ADDHLD_Pos) /*!< 0x00000040 */ #define FMC_BTR4_ADDHLD_3 (0x8U << FMC_BTR4_ADDHLD_Pos) /*!< 0x00000080 */ #define FMC_BTR4_DATAST_Pos (8U) #define FMC_BTR4_DATAST_Msk (0xFFU << FMC_BTR4_DATAST_Pos) /*!< 0x0000FF00 */ #define FMC_BTR4_DATAST FMC_BTR4_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */ #define FMC_BTR4_DATAST_0 (0x01U << FMC_BTR4_DATAST_Pos) /*!< 0x00000100 */ #define FMC_BTR4_DATAST_1 (0x02U << FMC_BTR4_DATAST_Pos) /*!< 0x00000200 */ #define FMC_BTR4_DATAST_2 (0x04U << FMC_BTR4_DATAST_Pos) /*!< 0x00000400 */ #define FMC_BTR4_DATAST_3 (0x08U << FMC_BTR4_DATAST_Pos) /*!< 0x00000800 */ #define FMC_BTR4_DATAST_4 (0x10U << FMC_BTR4_DATAST_Pos) /*!< 0x00001000 */ #define FMC_BTR4_DATAST_5 (0x20U << FMC_BTR4_DATAST_Pos) /*!< 0x00002000 */ #define FMC_BTR4_DATAST_6 (0x40U << FMC_BTR4_DATAST_Pos) /*!< 0x00004000 */ #define FMC_BTR4_DATAST_7 (0x80U << FMC_BTR4_DATAST_Pos) /*!< 0x00008000 */ #define FMC_BTR4_BUSTURN_Pos (16U) #define FMC_BTR4_BUSTURN_Msk (0xFU << FMC_BTR4_BUSTURN_Pos) /*!< 0x000F0000 */ #define FMC_BTR4_BUSTURN FMC_BTR4_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */ #define FMC_BTR4_BUSTURN_0 (0x1U << FMC_BTR4_BUSTURN_Pos) /*!< 0x00010000 */ #define FMC_BTR4_BUSTURN_1 (0x2U << FMC_BTR4_BUSTURN_Pos) /*!< 0x00020000 */ #define FMC_BTR4_BUSTURN_2 (0x4U << FMC_BTR4_BUSTURN_Pos) /*!< 0x00040000 */ #define FMC_BTR4_BUSTURN_3 (0x8U << FMC_BTR4_BUSTURN_Pos) /*!< 0x00080000 */ #define FMC_BTR4_CLKDIV_Pos (20U) #define FMC_BTR4_CLKDIV_Msk (0xFU << FMC_BTR4_CLKDIV_Pos) /*!< 0x00F00000 */ #define FMC_BTR4_CLKDIV FMC_BTR4_CLKDIV_Msk /*!<CLKDIV[3:0] bits (Clock divide ratio) */ #define FMC_BTR4_CLKDIV_0 (0x1U << FMC_BTR4_CLKDIV_Pos) /*!< 0x00100000 */ #define FMC_BTR4_CLKDIV_1 (0x2U << FMC_BTR4_CLKDIV_Pos) /*!< 0x00200000 */ #define FMC_BTR4_CLKDIV_2 (0x4U << FMC_BTR4_CLKDIV_Pos) /*!< 0x00400000 */ #define FMC_BTR4_CLKDIV_3 (0x8U << FMC_BTR4_CLKDIV_Pos) /*!< 0x00800000 */ #define FMC_BTR4_DATLAT_Pos (24U) #define FMC_BTR4_DATLAT_Msk (0xFU << FMC_BTR4_DATLAT_Pos) /*!< 0x0F000000 */ #define FMC_BTR4_DATLAT FMC_BTR4_DATLAT_Msk /*!<DATLA[3:0] bits (Data latency) */ #define FMC_BTR4_DATLAT_0 (0x1U << FMC_BTR4_DATLAT_Pos) /*!< 0x01000000 */ #define FMC_BTR4_DATLAT_1 (0x2U << FMC_BTR4_DATLAT_Pos) /*!< 0x02000000 */ #define FMC_BTR4_DATLAT_2 (0x4U << FMC_BTR4_DATLAT_Pos) /*!< 0x04000000 */ #define FMC_BTR4_DATLAT_3 (0x8U << FMC_BTR4_DATLAT_Pos) /*!< 0x08000000 */ #define FMC_BTR4_ACCMOD_Pos (28U) #define FMC_BTR4_ACCMOD_Msk (0x3U << FMC_BTR4_ACCMOD_Pos) /*!< 0x30000000 */ #define FMC_BTR4_ACCMOD FMC_BTR4_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */ #define FMC_BTR4_ACCMOD_0 (0x1U << FMC_BTR4_ACCMOD_Pos) /*!< 0x10000000 */ #define FMC_BTR4_ACCMOD_1 (0x2U << FMC_BTR4_ACCMOD_Pos) /*!< 0x20000000 */ /****************** Bit definition for FMC_BWTR1 register ******************/ #define FMC_BWTR1_ADDSET_Pos (0U) #define FMC_BWTR1_ADDSET_Msk (0xFU << FMC_BWTR1_ADDSET_Pos) /*!< 0x0000000F */ #define FMC_BWTR1_ADDSET FMC_BWTR1_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */ #define FMC_BWTR1_ADDSET_0 (0x1U << FMC_BWTR1_ADDSET_Pos) /*!< 0x00000001 */ #define FMC_BWTR1_ADDSET_1 (0x2U << FMC_BWTR1_ADDSET_Pos) /*!< 0x00000002 */ #define FMC_BWTR1_ADDSET_2 (0x4U << FMC_BWTR1_ADDSET_Pos) /*!< 0x00000004 */ #define FMC_BWTR1_ADDSET_3 (0x8U << FMC_BWTR1_ADDSET_Pos) /*!< 0x00000008 */ #define FMC_BWTR1_ADDHLD_Pos (4U) #define FMC_BWTR1_ADDHLD_Msk (0xFU << FMC_BWTR1_ADDHLD_Pos) /*!< 0x000000F0 */ #define FMC_BWTR1_ADDHLD FMC_BWTR1_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */ #define FMC_BWTR1_ADDHLD_0 (0x1U << FMC_BWTR1_ADDHLD_Pos) /*!< 0x00000010 */ #define FMC_BWTR1_ADDHLD_1 (0x2U << FMC_BWTR1_ADDHLD_Pos) /*!< 0x00000020 */ #define FMC_BWTR1_ADDHLD_2 (0x4U << FMC_BWTR1_ADDHLD_Pos) /*!< 0x00000040 */ #define FMC_BWTR1_ADDHLD_3 (0x8U << FMC_BWTR1_ADDHLD_Pos) /*!< 0x00000080 */ #define FMC_BWTR1_DATAST_Pos (8U) #define FMC_BWTR1_DATAST_Msk (0xFFU << FMC_BWTR1_DATAST_Pos) /*!< 0x0000FF00 */ #define FMC_BWTR1_DATAST FMC_BWTR1_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */ #define FMC_BWTR1_DATAST_0 (0x01U << FMC_BWTR1_DATAST_Pos) /*!< 0x00000100 */ #define FMC_BWTR1_DATAST_1 (0x02U << FMC_BWTR1_DATAST_Pos) /*!< 0x00000200 */ #define FMC_BWTR1_DATAST_2 (0x04U << FMC_BWTR1_DATAST_Pos) /*!< 0x00000400 */ #define FMC_BWTR1_DATAST_3 (0x08U << FMC_BWTR1_DATAST_Pos) /*!< 0x00000800 */ #define FMC_BWTR1_DATAST_4 (0x10U << FMC_BWTR1_DATAST_Pos) /*!< 0x00001000 */ #define FMC_BWTR1_DATAST_5 (0x20U << FMC_BWTR1_DATAST_Pos) /*!< 0x00002000 */ #define FMC_BWTR1_DATAST_6 (0x40U << FMC_BWTR1_DATAST_Pos) /*!< 0x00004000 */ #define FMC_BWTR1_DATAST_7 (0x80U << FMC_BWTR1_DATAST_Pos) /*!< 0x00008000 */ #define FMC_BWTR1_BUSTURN_Pos (16U) #define FMC_BWTR1_BUSTURN_Msk (0xFU << FMC_BWTR1_BUSTURN_Pos) /*!< 0x000F0000 */ #define FMC_BWTR1_BUSTURN FMC_BWTR1_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround duration) */ #define FMC_BWTR1_BUSTURN_0 (0x1U << FMC_BWTR1_BUSTURN_Pos) /*!< 0x00010000 */ #define FMC_BWTR1_BUSTURN_1 (0x2U << FMC_BWTR1_BUSTURN_Pos) /*!< 0x00020000 */ #define FMC_BWTR1_BUSTURN_2 (0x4U << FMC_BWTR1_BUSTURN_Pos) /*!< 0x00040000 */ #define FMC_BWTR1_BUSTURN_3 (0x8U << FMC_BWTR1_BUSTURN_Pos) /*!< 0x00080000 */ #define FMC_BWTR1_ACCMOD_Pos (28U) #define FMC_BWTR1_ACCMOD_Msk (0x3U << FMC_BWTR1_ACCMOD_Pos) /*!< 0x30000000 */ #define FMC_BWTR1_ACCMOD FMC_BWTR1_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */ #define FMC_BWTR1_ACCMOD_0 (0x1U << FMC_BWTR1_ACCMOD_Pos) /*!< 0x10000000 */ #define FMC_BWTR1_ACCMOD_1 (0x2U << FMC_BWTR1_ACCMOD_Pos) /*!< 0x20000000 */ /****************** Bit definition for FMC_BWTR2 register ******************/ #define FMC_BWTR2_ADDSET_Pos (0U) #define FMC_BWTR2_ADDSET_Msk (0xFU << FMC_BWTR2_ADDSET_Pos) /*!< 0x0000000F */ #define FMC_BWTR2_ADDSET FMC_BWTR2_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */ #define FMC_BWTR2_ADDSET_0 (0x1U << FMC_BWTR2_ADDSET_Pos) /*!< 0x00000001 */ #define FMC_BWTR2_ADDSET_1 (0x2U << FMC_BWTR2_ADDSET_Pos) /*!< 0x00000002 */ #define FMC_BWTR2_ADDSET_2 (0x4U << FMC_BWTR2_ADDSET_Pos) /*!< 0x00000004 */ #define FMC_BWTR2_ADDSET_3 (0x8U << FMC_BWTR2_ADDSET_Pos) /*!< 0x00000008 */ #define FMC_BWTR2_ADDHLD_Pos (4U) #define FMC_BWTR2_ADDHLD_Msk (0xFU << FMC_BWTR2_ADDHLD_Pos) /*!< 0x000000F0 */ #define FMC_BWTR2_ADDHLD FMC_BWTR2_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */ #define FMC_BWTR2_ADDHLD_0 (0x1U << FMC_BWTR2_ADDHLD_Pos) /*!< 0x00000010 */ #define FMC_BWTR2_ADDHLD_1 (0x2U << FMC_BWTR2_ADDHLD_Pos) /*!< 0x00000020 */ #define FMC_BWTR2_ADDHLD_2 (0x4U << FMC_BWTR2_ADDHLD_Pos) /*!< 0x00000040 */ #define FMC_BWTR2_ADDHLD_3 (0x8U << FMC_BWTR2_ADDHLD_Pos) /*!< 0x00000080 */ #define FMC_BWTR2_DATAST_Pos (8U) #define FMC_BWTR2_DATAST_Msk (0xFFU << FMC_BWTR2_DATAST_Pos) /*!< 0x0000FF00 */ #define FMC_BWTR2_DATAST FMC_BWTR2_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */ #define FMC_BWTR2_DATAST_0 (0x01U << FMC_BWTR2_DATAST_Pos) /*!< 0x00000100 */ #define FMC_BWTR2_DATAST_1 (0x02U << FMC_BWTR2_DATAST_Pos) /*!< 0x00000200 */ #define FMC_BWTR2_DATAST_2 (0x04U << FMC_BWTR2_DATAST_Pos) /*!< 0x00000400 */ #define FMC_BWTR2_DATAST_3 (0x08U << FMC_BWTR2_DATAST_Pos) /*!< 0x00000800 */ #define FMC_BWTR2_DATAST_4 (0x10U << FMC_BWTR2_DATAST_Pos) /*!< 0x00001000 */ #define FMC_BWTR2_DATAST_5 (0x20U << FMC_BWTR2_DATAST_Pos) /*!< 0x00002000 */ #define FMC_BWTR2_DATAST_6 (0x40U << FMC_BWTR2_DATAST_Pos) /*!< 0x00004000 */ #define FMC_BWTR2_DATAST_7 (0x80U << FMC_BWTR2_DATAST_Pos) /*!< 0x00008000 */ #define FMC_BWTR2_BUSTURN_Pos (16U) #define FMC_BWTR2_BUSTURN_Msk (0xFU << FMC_BWTR2_BUSTURN_Pos) /*!< 0x000F0000 */ #define FMC_BWTR2_BUSTURN FMC_BWTR2_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround duration) */ #define FMC_BWTR2_BUSTURN_0 (0x1U << FMC_BWTR2_BUSTURN_Pos) /*!< 0x00010000 */ #define FMC_BWTR2_BUSTURN_1 (0x2U << FMC_BWTR2_BUSTURN_Pos) /*!< 0x00020000 */ #define FMC_BWTR2_BUSTURN_2 (0x4U << FMC_BWTR2_BUSTURN_Pos) /*!< 0x00040000 */ #define FMC_BWTR2_BUSTURN_3 (0x8U << FMC_BWTR2_BUSTURN_Pos) /*!< 0x00080000 */ #define FMC_BWTR2_ACCMOD_Pos (28U) #define FMC_BWTR2_ACCMOD_Msk (0x3U << FMC_BWTR2_ACCMOD_Pos) /*!< 0x30000000 */ #define FMC_BWTR2_ACCMOD FMC_BWTR2_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */ #define FMC_BWTR2_ACCMOD_0 (0x1U << FMC_BWTR2_ACCMOD_Pos) /*!< 0x10000000 */ #define FMC_BWTR2_ACCMOD_1 (0x2U << FMC_BWTR2_ACCMOD_Pos) /*!< 0x20000000 */ /****************** Bit definition for FMC_BWTR3 register ******************/ #define FMC_BWTR3_ADDSET_Pos (0U) #define FMC_BWTR3_ADDSET_Msk (0xFU << FMC_BWTR3_ADDSET_Pos) /*!< 0x0000000F */ #define FMC_BWTR3_ADDSET FMC_BWTR3_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */ #define FMC_BWTR3_ADDSET_0 (0x1U << FMC_BWTR3_ADDSET_Pos) /*!< 0x00000001 */ #define FMC_BWTR3_ADDSET_1 (0x2U << FMC_BWTR3_ADDSET_Pos) /*!< 0x00000002 */ #define FMC_BWTR3_ADDSET_2 (0x4U << FMC_BWTR3_ADDSET_Pos) /*!< 0x00000004 */ #define FMC_BWTR3_ADDSET_3 (0x8U << FMC_BWTR3_ADDSET_Pos) /*!< 0x00000008 */ #define FMC_BWTR3_ADDHLD_Pos (4U) #define FMC_BWTR3_ADDHLD_Msk (0xFU << FMC_BWTR3_ADDHLD_Pos) /*!< 0x000000F0 */ #define FMC_BWTR3_ADDHLD FMC_BWTR3_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */ #define FMC_BWTR3_ADDHLD_0 (0x1U << FMC_BWTR3_ADDHLD_Pos) /*!< 0x00000010 */ #define FMC_BWTR3_ADDHLD_1 (0x2U << FMC_BWTR3_ADDHLD_Pos) /*!< 0x00000020 */ #define FMC_BWTR3_ADDHLD_2 (0x4U << FMC_BWTR3_ADDHLD_Pos) /*!< 0x00000040 */ #define FMC_BWTR3_ADDHLD_3 (0x8U << FMC_BWTR3_ADDHLD_Pos) /*!< 0x00000080 */ #define FMC_BWTR3_DATAST_Pos (8U) #define FMC_BWTR3_DATAST_Msk (0xFFU << FMC_BWTR3_DATAST_Pos) /*!< 0x0000FF00 */ #define FMC_BWTR3_DATAST FMC_BWTR3_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */ #define FMC_BWTR3_DATAST_0 (0x01U << FMC_BWTR3_DATAST_Pos) /*!< 0x00000100 */ #define FMC_BWTR3_DATAST_1 (0x02U << FMC_BWTR3_DATAST_Pos) /*!< 0x00000200 */ #define FMC_BWTR3_DATAST_2 (0x04U << FMC_BWTR3_DATAST_Pos) /*!< 0x00000400 */ #define FMC_BWTR3_DATAST_3 (0x08U << FMC_BWTR3_DATAST_Pos) /*!< 0x00000800 */ #define FMC_BWTR3_DATAST_4 (0x10U << FMC_BWTR3_DATAST_Pos) /*!< 0x00001000 */ #define FMC_BWTR3_DATAST_5 (0x20U << FMC_BWTR3_DATAST_Pos) /*!< 0x00002000 */ #define FMC_BWTR3_DATAST_6 (0x40U << FMC_BWTR3_DATAST_Pos) /*!< 0x00004000 */ #define FMC_BWTR3_DATAST_7 (0x80U << FMC_BWTR3_DATAST_Pos) /*!< 0x00008000 */ #define FMC_BWTR3_BUSTURN_Pos (16U) #define FMC_BWTR3_BUSTURN_Msk (0xFU << FMC_BWTR3_BUSTURN_Pos) /*!< 0x000F0000 */ #define FMC_BWTR3_BUSTURN FMC_BWTR3_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround duration) */ #define FMC_BWTR3_BUSTURN_0 (0x1U << FMC_BWTR3_BUSTURN_Pos) /*!< 0x00010000 */ #define FMC_BWTR3_BUSTURN_1 (0x2U << FMC_BWTR3_BUSTURN_Pos) /*!< 0x00020000 */ #define FMC_BWTR3_BUSTURN_2 (0x4U << FMC_BWTR3_BUSTURN_Pos) /*!< 0x00040000 */ #define FMC_BWTR3_BUSTURN_3 (0x8U << FMC_BWTR3_BUSTURN_Pos) /*!< 0x00080000 */ #define FMC_BWTR3_ACCMOD_Pos (28U) #define FMC_BWTR3_ACCMOD_Msk (0x3U << FMC_BWTR3_ACCMOD_Pos) /*!< 0x30000000 */ #define FMC_BWTR3_ACCMOD FMC_BWTR3_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */ #define FMC_BWTR3_ACCMOD_0 (0x1U << FMC_BWTR3_ACCMOD_Pos) /*!< 0x10000000 */ #define FMC_BWTR3_ACCMOD_1 (0x2U << FMC_BWTR3_ACCMOD_Pos) /*!< 0x20000000 */ /****************** Bit definition for FMC_BWTR4 register ******************/ #define FMC_BWTR4_ADDSET_Pos (0U) #define FMC_BWTR4_ADDSET_Msk (0xFU << FMC_BWTR4_ADDSET_Pos) /*!< 0x0000000F */ #define FMC_BWTR4_ADDSET FMC_BWTR4_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */ #define FMC_BWTR4_ADDSET_0 (0x1U << FMC_BWTR4_ADDSET_Pos) /*!< 0x00000001 */ #define FMC_BWTR4_ADDSET_1 (0x2U << FMC_BWTR4_ADDSET_Pos) /*!< 0x00000002 */ #define FMC_BWTR4_ADDSET_2 (0x4U << FMC_BWTR4_ADDSET_Pos) /*!< 0x00000004 */ #define FMC_BWTR4_ADDSET_3 (0x8U << FMC_BWTR4_ADDSET_Pos) /*!< 0x00000008 */ #define FMC_BWTR4_ADDHLD_Pos (4U) #define FMC_BWTR4_ADDHLD_Msk (0xFU << FMC_BWTR4_ADDHLD_Pos) /*!< 0x000000F0 */ #define FMC_BWTR4_ADDHLD FMC_BWTR4_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */ #define FMC_BWTR4_ADDHLD_0 (0x1U << FMC_BWTR4_ADDHLD_Pos) /*!< 0x00000010 */ #define FMC_BWTR4_ADDHLD_1 (0x2U << FMC_BWTR4_ADDHLD_Pos) /*!< 0x00000020 */ #define FMC_BWTR4_ADDHLD_2 (0x4U << FMC_BWTR4_ADDHLD_Pos) /*!< 0x00000040 */ #define FMC_BWTR4_ADDHLD_3 (0x8U << FMC_BWTR4_ADDHLD_Pos) /*!< 0x00000080 */ #define FMC_BWTR4_DATAST_Pos (8U) #define FMC_BWTR4_DATAST_Msk (0xFFU << FMC_BWTR4_DATAST_Pos) /*!< 0x0000FF00 */ #define FMC_BWTR4_DATAST FMC_BWTR4_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */ #define FMC_BWTR4_DATAST_0 (0x01U << FMC_BWTR4_DATAST_Pos) /*!< 0x00000100 */ #define FMC_BWTR4_DATAST_1 (0x02U << FMC_BWTR4_DATAST_Pos) /*!< 0x00000200 */ #define FMC_BWTR4_DATAST_2 (0x04U << FMC_BWTR4_DATAST_Pos) /*!< 0x00000400 */ #define FMC_BWTR4_DATAST_3 (0x08U << FMC_BWTR4_DATAST_Pos) /*!< 0x00000800 */ #define FMC_BWTR4_DATAST_4 (0x10U << FMC_BWTR4_DATAST_Pos) /*!< 0x00001000 */ #define FMC_BWTR4_DATAST_5 (0x20U << FMC_BWTR4_DATAST_Pos) /*!< 0x00002000 */ #define FMC_BWTR4_DATAST_6 (0x40U << FMC_BWTR4_DATAST_Pos) /*!< 0x00004000 */ #define FMC_BWTR4_DATAST_7 (0x80U << FMC_BWTR4_DATAST_Pos) /*!< 0x00008000 */ #define FMC_BWTR4_BUSTURN_Pos (16U) #define FMC_BWTR4_BUSTURN_Msk (0xFU << FMC_BWTR4_BUSTURN_Pos) /*!< 0x000F0000 */ #define FMC_BWTR4_BUSTURN FMC_BWTR4_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround duration) */ #define FMC_BWTR4_BUSTURN_0 (0x1U << FMC_BWTR4_BUSTURN_Pos) /*!< 0x00010000 */ #define FMC_BWTR4_BUSTURN_1 (0x2U << FMC_BWTR4_BUSTURN_Pos) /*!< 0x00020000 */ #define FMC_BWTR4_BUSTURN_2 (0x4U << FMC_BWTR4_BUSTURN_Pos) /*!< 0x00040000 */ #define FMC_BWTR4_BUSTURN_3 (0x8U << FMC_BWTR4_BUSTURN_Pos) /*!< 0x00080000 */ #define FMC_BWTR4_ACCMOD_Pos (28U) #define FMC_BWTR4_ACCMOD_Msk (0x3U << FMC_BWTR4_ACCMOD_Pos) /*!< 0x30000000 */ #define FMC_BWTR4_ACCMOD FMC_BWTR4_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */ #define FMC_BWTR4_ACCMOD_0 (0x1U << FMC_BWTR4_ACCMOD_Pos) /*!< 0x10000000 */ #define FMC_BWTR4_ACCMOD_1 (0x2U << FMC_BWTR4_ACCMOD_Pos) /*!< 0x20000000 */ /****************** Bit definition for FMC_PCR register *******************/ #define FMC_PCR_PWAITEN_Pos (1U) #define FMC_PCR_PWAITEN_Msk (0x1U << FMC_PCR_PWAITEN_Pos) /*!< 0x00000002 */ #define FMC_PCR_PWAITEN FMC_PCR_PWAITEN_Msk /*!<Wait feature enable bit */ #define FMC_PCR_PBKEN_Pos (2U) #define FMC_PCR_PBKEN_Msk (0x1U << FMC_PCR_PBKEN_Pos) /*!< 0x00000004 */ #define FMC_PCR_PBKEN FMC_PCR_PBKEN_Msk /*!<PC Card/NAND Flash memory bank enable bit */ #define FMC_PCR_PTYP_Pos (3U) #define FMC_PCR_PTYP_Msk (0x1U << FMC_PCR_PTYP_Pos) /*!< 0x00000008 */ #define FMC_PCR_PTYP FMC_PCR_PTYP_Msk /*!<Memory type */ #define FMC_PCR_PWID_Pos (4U) #define FMC_PCR_PWID_Msk (0x3U << FMC_PCR_PWID_Pos) /*!< 0x00000030 */ #define FMC_PCR_PWID FMC_PCR_PWID_Msk /*!<PWID[1:0] bits (NAND Flash databus width) */ #define FMC_PCR_PWID_0 (0x1U << FMC_PCR_PWID_Pos) /*!< 0x00000010 */ #define FMC_PCR_PWID_1 (0x2U << FMC_PCR_PWID_Pos) /*!< 0x00000020 */ #define FMC_PCR_ECCEN_Pos (6U) #define FMC_PCR_ECCEN_Msk (0x1U << FMC_PCR_ECCEN_Pos) /*!< 0x00000040 */ #define FMC_PCR_ECCEN FMC_PCR_ECCEN_Msk /*!<ECC computation logic enable bit */ #define FMC_PCR_TCLR_Pos (9U) #define FMC_PCR_TCLR_Msk (0xFU << FMC_PCR_TCLR_Pos) /*!< 0x00001E00 */ #define FMC_PCR_TCLR FMC_PCR_TCLR_Msk /*!<TCLR[3:0] bits (CLE to RE delay) */ #define FMC_PCR_TCLR_0 (0x1U << FMC_PCR_TCLR_Pos) /*!< 0x00000200 */ #define FMC_PCR_TCLR_1 (0x2U << FMC_PCR_TCLR_Pos) /*!< 0x00000400 */ #define FMC_PCR_TCLR_2 (0x4U << FMC_PCR_TCLR_Pos) /*!< 0x00000800 */ #define FMC_PCR_TCLR_3 (0x8U << FMC_PCR_TCLR_Pos) /*!< 0x00001000 */ #define FMC_PCR_TAR_Pos (13U) #define FMC_PCR_TAR_Msk (0xFU << FMC_PCR_TAR_Pos) /*!< 0x0001E000 */ #define FMC_PCR_TAR FMC_PCR_TAR_Msk /*!<TAR[3:0] bits (ALE to RE delay) */ #define FMC_PCR_TAR_0 (0x1U << FMC_PCR_TAR_Pos) /*!< 0x00002000 */ #define FMC_PCR_TAR_1 (0x2U << FMC_PCR_TAR_Pos) /*!< 0x00004000 */ #define FMC_PCR_TAR_2 (0x4U << FMC_PCR_TAR_Pos) /*!< 0x00008000 */ #define FMC_PCR_TAR_3 (0x8U << FMC_PCR_TAR_Pos) /*!< 0x00010000 */ #define FMC_PCR_ECCPS_Pos (17U) #define FMC_PCR_ECCPS_Msk (0x7U << FMC_PCR_ECCPS_Pos) /*!< 0x000E0000 */ #define FMC_PCR_ECCPS FMC_PCR_ECCPS_Msk /*!<ECCPS[1:0] bits (ECC page size) */ #define FMC_PCR_ECCPS_0 (0x1U << FMC_PCR_ECCPS_Pos) /*!< 0x00020000 */ #define FMC_PCR_ECCPS_1 (0x2U << FMC_PCR_ECCPS_Pos) /*!< 0x00040000 */ #define FMC_PCR_ECCPS_2 (0x4U << FMC_PCR_ECCPS_Pos) /*!< 0x00080000 */ /******************* Bit definition for FMC_SR register *******************/ #define FMC_SR_IRS_Pos (0U) #define FMC_SR_IRS_Msk (0x1U << FMC_SR_IRS_Pos) /*!< 0x00000001 */ #define FMC_SR_IRS FMC_SR_IRS_Msk /*!<Interrupt Rising Edge status */ #define FMC_SR_ILS_Pos (1U) #define FMC_SR_ILS_Msk (0x1U << FMC_SR_ILS_Pos) /*!< 0x00000002 */ #define FMC_SR_ILS FMC_SR_ILS_Msk /*!<Interrupt Level status */ #define FMC_SR_IFS_Pos (2U) #define FMC_SR_IFS_Msk (0x1U << FMC_SR_IFS_Pos) /*!< 0x00000004 */ #define FMC_SR_IFS FMC_SR_IFS_Msk /*!<Interrupt Falling Edge status */ #define FMC_SR_IREN_Pos (3U) #define FMC_SR_IREN_Msk (0x1U << FMC_SR_IREN_Pos) /*!< 0x00000008 */ #define FMC_SR_IREN FMC_SR_IREN_Msk /*!<Interrupt Rising Edge detection Enable bit */ #define FMC_SR_ILEN_Pos (4U) #define FMC_SR_ILEN_Msk (0x1U << FMC_SR_ILEN_Pos) /*!< 0x00000010 */ #define FMC_SR_ILEN FMC_SR_ILEN_Msk /*!<Interrupt Level detection Enable bit */ #define FMC_SR_IFEN_Pos (5U) #define FMC_SR_IFEN_Msk (0x1U << FMC_SR_IFEN_Pos) /*!< 0x00000020 */ #define FMC_SR_IFEN FMC_SR_IFEN_Msk /*!<Interrupt Falling Edge detection Enable bit */ #define FMC_SR_FEMPT_Pos (6U) #define FMC_SR_FEMPT_Msk (0x1U << FMC_SR_FEMPT_Pos) /*!< 0x00000040 */ #define FMC_SR_FEMPT FMC_SR_FEMPT_Msk /*!<FIFO empty */ /****************** Bit definition for FMC_PMEM register ******************/ #define FMC_PMEM_MEMSET2_Pos (0U) #define FMC_PMEM_MEMSET2_Msk (0xFFU << FMC_PMEM_MEMSET2_Pos) /*!< 0x000000FF */ #define FMC_PMEM_MEMSET2 FMC_PMEM_MEMSET2_Msk /*!<MEMSET2[7:0] bits (Common memory 2 setup time) */ #define FMC_PMEM_MEMSET2_0 (0x01U << FMC_PMEM_MEMSET2_Pos) /*!< 0x00000001 */ #define FMC_PMEM_MEMSET2_1 (0x02U << FMC_PMEM_MEMSET2_Pos) /*!< 0x00000002 */ #define FMC_PMEM_MEMSET2_2 (0x04U << FMC_PMEM_MEMSET2_Pos) /*!< 0x00000004 */ #define FMC_PMEM_MEMSET2_3 (0x08U << FMC_PMEM_MEMSET2_Pos) /*!< 0x00000008 */ #define FMC_PMEM_MEMSET2_4 (0x10U << FMC_PMEM_MEMSET2_Pos) /*!< 0x00000010 */ #define FMC_PMEM_MEMSET2_5 (0x20U << FMC_PMEM_MEMSET2_Pos) /*!< 0x00000020 */ #define FMC_PMEM_MEMSET2_6 (0x40U << FMC_PMEM_MEMSET2_Pos) /*!< 0x00000040 */ #define FMC_PMEM_MEMSET2_7 (0x80U << FMC_PMEM_MEMSET2_Pos) /*!< 0x00000080 */ #define FMC_PMEM_MEMWAIT2_Pos (8U) #define FMC_PMEM_MEMWAIT2_Msk (0xFFU << FMC_PMEM_MEMWAIT2_Pos) /*!< 0x0000FF00 */ #define FMC_PMEM_MEMWAIT2 FMC_PMEM_MEMWAIT2_Msk /*!<MEMWAIT2[7:0] bits (Common memory 2 wait time) */ #define FMC_PMEM_MEMWAIT2_0 (0x01U << FMC_PMEM_MEMWAIT2_Pos) /*!< 0x00000100 */ #define FMC_PMEM_MEMWAIT2_1 (0x02U << FMC_PMEM_MEMWAIT2_Pos) /*!< 0x00000200 */ #define FMC_PMEM_MEMWAIT2_2 (0x04U << FMC_PMEM_MEMWAIT2_Pos) /*!< 0x00000400 */ #define FMC_PMEM_MEMWAIT2_3 (0x08U << FMC_PMEM_MEMWAIT2_Pos) /*!< 0x00000800 */ #define FMC_PMEM_MEMWAIT2_4 (0x10U << FMC_PMEM_MEMWAIT2_Pos) /*!< 0x00001000 */ #define FMC_PMEM_MEMWAIT2_5 (0x20U << FMC_PMEM_MEMWAIT2_Pos) /*!< 0x00002000 */ #define FMC_PMEM_MEMWAIT2_6 (0x40U << FMC_PMEM_MEMWAIT2_Pos) /*!< 0x00004000 */ #define FMC_PMEM_MEMWAIT2_7 (0x80U << FMC_PMEM_MEMWAIT2_Pos) /*!< 0x00008000 */ #define FMC_PMEM_MEMHOLD2_Pos (16U) #define FMC_PMEM_MEMHOLD2_Msk (0xFFU << FMC_PMEM_MEMHOLD2_Pos) /*!< 0x00FF0000 */ #define FMC_PMEM_MEMHOLD2 FMC_PMEM_MEMHOLD2_Msk /*!<MEMHOLD2[7:0] bits (Common memory 2 hold time) */ #define FMC_PMEM_MEMHOLD2_0 (0x01U << FMC_PMEM_MEMHOLD2_Pos) /*!< 0x00010000 */ #define FMC_PMEM_MEMHOLD2_1 (0x02U << FMC_PMEM_MEMHOLD2_Pos) /*!< 0x00020000 */ #define FMC_PMEM_MEMHOLD2_2 (0x04U << FMC_PMEM_MEMHOLD2_Pos) /*!< 0x00040000 */ #define FMC_PMEM_MEMHOLD2_3 (0x08U << FMC_PMEM_MEMHOLD2_Pos) /*!< 0x00080000 */ #define FMC_PMEM_MEMHOLD2_4 (0x10U << FMC_PMEM_MEMHOLD2_Pos) /*!< 0x00100000 */ #define FMC_PMEM_MEMHOLD2_5 (0x20U << FMC_PMEM_MEMHOLD2_Pos) /*!< 0x00200000 */ #define FMC_PMEM_MEMHOLD2_6 (0x40U << FMC_PMEM_MEMHOLD2_Pos) /*!< 0x00400000 */ #define FMC_PMEM_MEMHOLD2_7 (0x80U << FMC_PMEM_MEMHOLD2_Pos) /*!< 0x00800000 */ #define FMC_PMEM_MEMHIZ2_Pos (24U) #define FMC_PMEM_MEMHIZ2_Msk (0xFFU << FMC_PMEM_MEMHIZ2_Pos) /*!< 0xFF000000 */ #define FMC_PMEM_MEMHIZ2 FMC_PMEM_MEMHIZ2_Msk /*!<MEMHIZ2[7:0] bits (Common memory 2 databus HiZ time) */ #define FMC_PMEM_MEMHIZ2_0 (0x01U << FMC_PMEM_MEMHIZ2_Pos) /*!< 0x01000000 */ #define FMC_PMEM_MEMHIZ2_1 (0x02U << FMC_PMEM_MEMHIZ2_Pos) /*!< 0x02000000 */ #define FMC_PMEM_MEMHIZ2_2 (0x04U << FMC_PMEM_MEMHIZ2_Pos) /*!< 0x04000000 */ #define FMC_PMEM_MEMHIZ2_3 (0x08U << FMC_PMEM_MEMHIZ2_Pos) /*!< 0x08000000 */ #define FMC_PMEM_MEMHIZ2_4 (0x10U << FMC_PMEM_MEMHIZ2_Pos) /*!< 0x10000000 */ #define FMC_PMEM_MEMHIZ2_5 (0x20U << FMC_PMEM_MEMHIZ2_Pos) /*!< 0x20000000 */ #define FMC_PMEM_MEMHIZ2_6 (0x40U << FMC_PMEM_MEMHIZ2_Pos) /*!< 0x40000000 */ #define FMC_PMEM_MEMHIZ2_7 (0x80U << FMC_PMEM_MEMHIZ2_Pos) /*!< 0x80000000 */ /****************** Bit definition for FMC_PATT register ******************/ #define FMC_PATT_ATTSET2_Pos (0U) #define FMC_PATT_ATTSET2_Msk (0xFFU << FMC_PATT_ATTSET2_Pos) /*!< 0x000000FF */ #define FMC_PATT_ATTSET2 FMC_PATT_ATTSET2_Msk /*!<ATTSET2[7:0] bits (Attribute memory 2 setup time) */ #define FMC_PATT_ATTSET2_0 (0x01U << FMC_PATT_ATTSET2_Pos) /*!< 0x00000001 */ #define FMC_PATT_ATTSET2_1 (0x02U << FMC_PATT_ATTSET2_Pos) /*!< 0x00000002 */ #define FMC_PATT_ATTSET2_2 (0x04U << FMC_PATT_ATTSET2_Pos) /*!< 0x00000004 */ #define FMC_PATT_ATTSET2_3 (0x08U << FMC_PATT_ATTSET2_Pos) /*!< 0x00000008 */ #define FMC_PATT_ATTSET2_4 (0x10U << FMC_PATT_ATTSET2_Pos) /*!< 0x00000010 */ #define FMC_PATT_ATTSET2_5 (0x20U << FMC_PATT_ATTSET2_Pos) /*!< 0x00000020 */ #define FMC_PATT_ATTSET2_6 (0x40U << FMC_PATT_ATTSET2_Pos) /*!< 0x00000040 */ #define FMC_PATT_ATTSET2_7 (0x80U << FMC_PATT_ATTSET2_Pos) /*!< 0x00000080 */ #define FMC_PATT_ATTWAIT2_Pos (8U) #define FMC_PATT_ATTWAIT2_Msk (0xFFU << FMC_PATT_ATTWAIT2_Pos) /*!< 0x0000FF00 */ #define FMC_PATT_ATTWAIT2 FMC_PATT_ATTWAIT2_Msk /*!<ATTWAIT2[7:0] bits (Attribute memory 2 wait time) */ #define FMC_PATT_ATTWAIT2_0 (0x01U << FMC_PATT_ATTWAIT2_Pos) /*!< 0x00000100 */ #define FMC_PATT_ATTWAIT2_1 (0x02U << FMC_PATT_ATTWAIT2_Pos) /*!< 0x00000200 */ #define FMC_PATT_ATTWAIT2_2 (0x04U << FMC_PATT_ATTWAIT2_Pos) /*!< 0x00000400 */ #define FMC_PATT_ATTWAIT2_3 (0x08U << FMC_PATT_ATTWAIT2_Pos) /*!< 0x00000800 */ #define FMC_PATT_ATTWAIT2_4 (0x10U << FMC_PATT_ATTWAIT2_Pos) /*!< 0x00001000 */ #define FMC_PATT_ATTWAIT2_5 (0x20U << FMC_PATT_ATTWAIT2_Pos) /*!< 0x00002000 */ #define FMC_PATT_ATTWAIT2_6 (0x40U << FMC_PATT_ATTWAIT2_Pos) /*!< 0x00004000 */ #define FMC_PATT_ATTWAIT2_7 (0x80U << FMC_PATT_ATTWAIT2_Pos) /*!< 0x00008000 */ #define FMC_PATT_ATTHOLD2_Pos (16U) #define FMC_PATT_ATTHOLD2_Msk (0xFFU << FMC_PATT_ATTHOLD2_Pos) /*!< 0x00FF0000 */ #define FMC_PATT_ATTHOLD2 FMC_PATT_ATTHOLD2_Msk /*!<ATTHOLD2[7:0] bits (Attribute memory 2 hold time) */ #define FMC_PATT_ATTHOLD2_0 (0x01U << FMC_PATT_ATTHOLD2_Pos) /*!< 0x00010000 */ #define FMC_PATT_ATTHOLD2_1 (0x02U << FMC_PATT_ATTHOLD2_Pos) /*!< 0x00020000 */ #define FMC_PATT_ATTHOLD2_2 (0x04U << FMC_PATT_ATTHOLD2_Pos) /*!< 0x00040000 */ #define FMC_PATT_ATTHOLD2_3 (0x08U << FMC_PATT_ATTHOLD2_Pos) /*!< 0x00080000 */ #define FMC_PATT_ATTHOLD2_4 (0x10U << FMC_PATT_ATTHOLD2_Pos) /*!< 0x00100000 */ #define FMC_PATT_ATTHOLD2_5 (0x20U << FMC_PATT_ATTHOLD2_Pos) /*!< 0x00200000 */ #define FMC_PATT_ATTHOLD2_6 (0x40U << FMC_PATT_ATTHOLD2_Pos) /*!< 0x00400000 */ #define FMC_PATT_ATTHOLD2_7 (0x80U << FMC_PATT_ATTHOLD2_Pos) /*!< 0x00800000 */ #define FMC_PATT_ATTHIZ2_Pos (24U) #define FMC_PATT_ATTHIZ2_Msk (0xFFU << FMC_PATT_ATTHIZ2_Pos) /*!< 0xFF000000 */ #define FMC_PATT_ATTHIZ2 FMC_PATT_ATTHIZ2_Msk /*!<ATTHIZ2[7:0] bits (Attribute memory 2 databus HiZ time) */ #define FMC_PATT_ATTHIZ2_0 (0x01U << FMC_PATT_ATTHIZ2_Pos) /*!< 0x01000000 */ #define FMC_PATT_ATTHIZ2_1 (0x02U << FMC_PATT_ATTHIZ2_Pos) /*!< 0x02000000 */ #define FMC_PATT_ATTHIZ2_2 (0x04U << FMC_PATT_ATTHIZ2_Pos) /*!< 0x04000000 */ #define FMC_PATT_ATTHIZ2_3 (0x08U << FMC_PATT_ATTHIZ2_Pos) /*!< 0x08000000 */ #define FMC_PATT_ATTHIZ2_4 (0x10U << FMC_PATT_ATTHIZ2_Pos) /*!< 0x10000000 */ #define FMC_PATT_ATTHIZ2_5 (0x20U << FMC_PATT_ATTHIZ2_Pos) /*!< 0x20000000 */ #define FMC_PATT_ATTHIZ2_6 (0x40U << FMC_PATT_ATTHIZ2_Pos) /*!< 0x40000000 */ #define FMC_PATT_ATTHIZ2_7 (0x80U << FMC_PATT_ATTHIZ2_Pos) /*!< 0x80000000 */ /****************** Bit definition for FMC_ECCR register ******************/ #define FMC_ECCR_ECC2_Pos (0U) #define FMC_ECCR_ECC2_Msk (0xFFFFFFFFU << FMC_ECCR_ECC2_Pos) /*!< 0xFFFFFFFF */ #define FMC_ECCR_ECC2 FMC_ECCR_ECC2_Msk /*!<ECC result */ /****************** Bit definition for FMC_SDCR1 register ******************/ #define FMC_SDCR1_NC_Pos (0U) #define FMC_SDCR1_NC_Msk (0x3U << FMC_SDCR1_NC_Pos) /*!< 0x00000003 */ #define FMC_SDCR1_NC FMC_SDCR1_NC_Msk /*!<NC[1:0] bits (Number of column bits) */ #define FMC_SDCR1_NC_0 (0x1U << FMC_SDCR1_NC_Pos) /*!< 0x00000001 */ #define FMC_SDCR1_NC_1 (0x2U << FMC_SDCR1_NC_Pos) /*!< 0x00000002 */ #define FMC_SDCR1_NR_Pos (2U) #define FMC_SDCR1_NR_Msk (0x3U << FMC_SDCR1_NR_Pos) /*!< 0x0000000C */ #define FMC_SDCR1_NR FMC_SDCR1_NR_Msk /*!<NR[1:0] bits (Number of row bits) */ #define FMC_SDCR1_NR_0 (0x1U << FMC_SDCR1_NR_Pos) /*!< 0x00000004 */ #define FMC_SDCR1_NR_1 (0x2U << FMC_SDCR1_NR_Pos) /*!< 0x00000008 */ #define FMC_SDCR1_MWID_Pos (4U) #define FMC_SDCR1_MWID_Msk (0x3U << FMC_SDCR1_MWID_Pos) /*!< 0x00000030 */ #define FMC_SDCR1_MWID FMC_SDCR1_MWID_Msk /*!<NR[1:0] bits (Number of row bits) */ #define FMC_SDCR1_MWID_0 (0x1U << FMC_SDCR1_MWID_Pos) /*!< 0x00000010 */ #define FMC_SDCR1_MWID_1 (0x2U << FMC_SDCR1_MWID_Pos) /*!< 0x00000020 */ #define FMC_SDCR1_NB_Pos (6U) #define FMC_SDCR1_NB_Msk (0x1U << FMC_SDCR1_NB_Pos) /*!< 0x00000040 */ #define FMC_SDCR1_NB FMC_SDCR1_NB_Msk /*!<Number of internal bank */ #define FMC_SDCR1_CAS_Pos (7U) #define FMC_SDCR1_CAS_Msk (0x3U << FMC_SDCR1_CAS_Pos) /*!< 0x00000180 */ #define FMC_SDCR1_CAS FMC_SDCR1_CAS_Msk /*!<CAS[1:0] bits (CAS latency) */ #define FMC_SDCR1_CAS_0 (0x1U << FMC_SDCR1_CAS_Pos) /*!< 0x00000080 */ #define FMC_SDCR1_CAS_1 (0x2U << FMC_SDCR1_CAS_Pos) /*!< 0x00000100 */ #define FMC_SDCR1_WP_Pos (9U) #define FMC_SDCR1_WP_Msk (0x1U << FMC_SDCR1_WP_Pos) /*!< 0x00000200 */ #define FMC_SDCR1_WP FMC_SDCR1_WP_Msk /*!<Write protection */ #define FMC_SDCR1_SDCLK_Pos (10U) #define FMC_SDCR1_SDCLK_Msk (0x3U << FMC_SDCR1_SDCLK_Pos) /*!< 0x00000C00 */ #define FMC_SDCR1_SDCLK FMC_SDCR1_SDCLK_Msk /*!<SDRAM clock configuration */ #define FMC_SDCR1_SDCLK_0 (0x1U << FMC_SDCR1_SDCLK_Pos) /*!< 0x00000400 */ #define FMC_SDCR1_SDCLK_1 (0x2U << FMC_SDCR1_SDCLK_Pos) /*!< 0x00000800 */ #define FMC_SDCR1_RBURST_Pos (12U) #define FMC_SDCR1_RBURST_Msk (0x1U << FMC_SDCR1_RBURST_Pos) /*!< 0x00001000 */ #define FMC_SDCR1_RBURST FMC_SDCR1_RBURST_Msk /*!<Read burst */ #define FMC_SDCR1_RPIPE_Pos (13U) #define FMC_SDCR1_RPIPE_Msk (0x3U << FMC_SDCR1_RPIPE_Pos) /*!< 0x00006000 */ #define FMC_SDCR1_RPIPE FMC_SDCR1_RPIPE_Msk /*!<Write protection */ #define FMC_SDCR1_RPIPE_0 (0x1U << FMC_SDCR1_RPIPE_Pos) /*!< 0x00002000 */ #define FMC_SDCR1_RPIPE_1 (0x2U << FMC_SDCR1_RPIPE_Pos) /*!< 0x00004000 */ /****************** Bit definition for FMC_SDCR2 register ******************/ #define FMC_SDCR2_NC_Pos (0U) #define FMC_SDCR2_NC_Msk (0x3U << FMC_SDCR2_NC_Pos) /*!< 0x00000003 */ #define FMC_SDCR2_NC FMC_SDCR2_NC_Msk /*!<NC[1:0] bits (Number of column bits) */ #define FMC_SDCR2_NC_0 (0x1U << FMC_SDCR2_NC_Pos) /*!< 0x00000001 */ #define FMC_SDCR2_NC_1 (0x2U << FMC_SDCR2_NC_Pos) /*!< 0x00000002 */ #define FMC_SDCR2_NR_Pos (2U) #define FMC_SDCR2_NR_Msk (0x3U << FMC_SDCR2_NR_Pos) /*!< 0x0000000C */ #define FMC_SDCR2_NR FMC_SDCR2_NR_Msk /*!<NR[1:0] bits (Number of row bits) */ #define FMC_SDCR2_NR_0 (0x1U << FMC_SDCR2_NR_Pos) /*!< 0x00000004 */ #define FMC_SDCR2_NR_1 (0x2U << FMC_SDCR2_NR_Pos) /*!< 0x00000008 */ #define FMC_SDCR2_MWID_Pos (4U) #define FMC_SDCR2_MWID_Msk (0x3U << FMC_SDCR2_MWID_Pos) /*!< 0x00000030 */ #define FMC_SDCR2_MWID FMC_SDCR2_MWID_Msk /*!<NR[1:0] bits (Number of row bits) */ #define FMC_SDCR2_MWID_0 (0x1U << FMC_SDCR2_MWID_Pos) /*!< 0x00000010 */ #define FMC_SDCR2_MWID_1 (0x2U << FMC_SDCR2_MWID_Pos) /*!< 0x00000020 */ #define FMC_SDCR2_NB_Pos (6U) #define FMC_SDCR2_NB_Msk (0x1U << FMC_SDCR2_NB_Pos) /*!< 0x00000040 */ #define FMC_SDCR2_NB FMC_SDCR2_NB_Msk /*!<Number of internal bank */ #define FMC_SDCR2_CAS_Pos (7U) #define FMC_SDCR2_CAS_Msk (0x3U << FMC_SDCR2_CAS_Pos) /*!< 0x00000180 */ #define FMC_SDCR2_CAS FMC_SDCR2_CAS_Msk /*!<CAS[1:0] bits (CAS latency) */ #define FMC_SDCR2_CAS_0 (0x1U << FMC_SDCR2_CAS_Pos) /*!< 0x00000080 */ #define FMC_SDCR2_CAS_1 (0x2U << FMC_SDCR2_CAS_Pos) /*!< 0x00000100 */ #define FMC_SDCR2_WP_Pos (9U) #define FMC_SDCR2_WP_Msk (0x1U << FMC_SDCR2_WP_Pos) /*!< 0x00000200 */ #define FMC_SDCR2_WP FMC_SDCR2_WP_Msk /*!<Write protection */ #define FMC_SDCR2_SDCLK_Pos (10U) #define FMC_SDCR2_SDCLK_Msk (0x3U << FMC_SDCR2_SDCLK_Pos) /*!< 0x00000C00 */ #define FMC_SDCR2_SDCLK FMC_SDCR2_SDCLK_Msk /*!<SDCLK[1:0] (SDRAM clock configuration) */ #define FMC_SDCR2_SDCLK_0 (0x1U << FMC_SDCR2_SDCLK_Pos) /*!< 0x00000400 */ #define FMC_SDCR2_SDCLK_1 (0x2U << FMC_SDCR2_SDCLK_Pos) /*!< 0x00000800 */ #define FMC_SDCR2_RBURST_Pos (12U) #define FMC_SDCR2_RBURST_Msk (0x1U << FMC_SDCR2_RBURST_Pos) /*!< 0x00001000 */ #define FMC_SDCR2_RBURST FMC_SDCR2_RBURST_Msk /*!<Read burst */ #define FMC_SDCR2_RPIPE_Pos (13U) #define FMC_SDCR2_RPIPE_Msk (0x3U << FMC_SDCR2_RPIPE_Pos) /*!< 0x00006000 */ #define FMC_SDCR2_RPIPE FMC_SDCR2_RPIPE_Msk /*!<RPIPE[1:0](Read pipe) */ #define FMC_SDCR2_RPIPE_0 (0x1U << FMC_SDCR2_RPIPE_Pos) /*!< 0x00002000 */ #define FMC_SDCR2_RPIPE_1 (0x2U << FMC_SDCR2_RPIPE_Pos) /*!< 0x00004000 */ /****************** Bit definition for FMC_SDTR1 register ******************/ #define FMC_SDTR1_TMRD_Pos (0U) #define FMC_SDTR1_TMRD_Msk (0xFU << FMC_SDTR1_TMRD_Pos) /*!< 0x0000000F */ #define FMC_SDTR1_TMRD FMC_SDTR1_TMRD_Msk /*!<TMRD[3:0] bits (Load mode register to active) */ #define FMC_SDTR1_TMRD_0 (0x1U << FMC_SDTR1_TMRD_Pos) /*!< 0x00000001 */ #define FMC_SDTR1_TMRD_1 (0x2U << FMC_SDTR1_TMRD_Pos) /*!< 0x00000002 */ #define FMC_SDTR1_TMRD_2 (0x4U << FMC_SDTR1_TMRD_Pos) /*!< 0x00000004 */ #define FMC_SDTR1_TMRD_3 (0x8U << FMC_SDTR1_TMRD_Pos) /*!< 0x00000008 */ #define FMC_SDTR1_TXSR_Pos (4U) #define FMC_SDTR1_TXSR_Msk (0xFU << FMC_SDTR1_TXSR_Pos) /*!< 0x000000F0 */ #define FMC_SDTR1_TXSR FMC_SDTR1_TXSR_Msk /*!<TXSR[3:0] bits (Exit self refresh) */ #define FMC_SDTR1_TXSR_0 (0x1U << FMC_SDTR1_TXSR_Pos) /*!< 0x00000010 */ #define FMC_SDTR1_TXSR_1 (0x2U << FMC_SDTR1_TXSR_Pos) /*!< 0x00000020 */ #define FMC_SDTR1_TXSR_2 (0x4U << FMC_SDTR1_TXSR_Pos) /*!< 0x00000040 */ #define FMC_SDTR1_TXSR_3 (0x8U << FMC_SDTR1_TXSR_Pos) /*!< 0x00000080 */ #define FMC_SDTR1_TRAS_Pos (8U) #define FMC_SDTR1_TRAS_Msk (0xFU << FMC_SDTR1_TRAS_Pos) /*!< 0x00000F00 */ #define FMC_SDTR1_TRAS FMC_SDTR1_TRAS_Msk /*!<TRAS[3:0] bits (Self refresh time) */ #define FMC_SDTR1_TRAS_0 (0x1U << FMC_SDTR1_TRAS_Pos) /*!< 0x00000100 */ #define FMC_SDTR1_TRAS_1 (0x2U << FMC_SDTR1_TRAS_Pos) /*!< 0x00000200 */ #define FMC_SDTR1_TRAS_2 (0x4U << FMC_SDTR1_TRAS_Pos) /*!< 0x00000400 */ #define FMC_SDTR1_TRAS_3 (0x8U << FMC_SDTR1_TRAS_Pos) /*!< 0x00000800 */ #define FMC_SDTR1_TRC_Pos (12U) #define FMC_SDTR1_TRC_Msk (0xFU << FMC_SDTR1_TRC_Pos) /*!< 0x0000F000 */ #define FMC_SDTR1_TRC FMC_SDTR1_TRC_Msk /*!<TRC[2:0] bits (Row cycle delay) */ #define FMC_SDTR1_TRC_0 (0x1U << FMC_SDTR1_TRC_Pos) /*!< 0x00001000 */ #define FMC_SDTR1_TRC_1 (0x2U << FMC_SDTR1_TRC_Pos) /*!< 0x00002000 */ #define FMC_SDTR1_TRC_2 (0x4U << FMC_SDTR1_TRC_Pos) /*!< 0x00004000 */ #define FMC_SDTR1_TWR_Pos (16U) #define FMC_SDTR1_TWR_Msk (0xFU << FMC_SDTR1_TWR_Pos) /*!< 0x000F0000 */ #define FMC_SDTR1_TWR FMC_SDTR1_TWR_Msk /*!<TRC[2:0] bits (Write recovery delay) */ #define FMC_SDTR1_TWR_0 (0x1U << FMC_SDTR1_TWR_Pos) /*!< 0x00010000 */ #define FMC_SDTR1_TWR_1 (0x2U << FMC_SDTR1_TWR_Pos) /*!< 0x00020000 */ #define FMC_SDTR1_TWR_2 (0x4U << FMC_SDTR1_TWR_Pos) /*!< 0x00040000 */ #define FMC_SDTR1_TRP_Pos (20U) #define FMC_SDTR1_TRP_Msk (0xFU << FMC_SDTR1_TRP_Pos) /*!< 0x00F00000 */ #define FMC_SDTR1_TRP FMC_SDTR1_TRP_Msk /*!<TRP[2:0] bits (Row precharge delay) */ #define FMC_SDTR1_TRP_0 (0x1U << FMC_SDTR1_TRP_Pos) /*!< 0x00100000 */ #define FMC_SDTR1_TRP_1 (0x2U << FMC_SDTR1_TRP_Pos) /*!< 0x00200000 */ #define FMC_SDTR1_TRP_2 (0x4U << FMC_SDTR1_TRP_Pos) /*!< 0x00400000 */ #define FMC_SDTR1_TRCD_Pos (24U) #define FMC_SDTR1_TRCD_Msk (0xFU << FMC_SDTR1_TRCD_Pos) /*!< 0x0F000000 */ #define FMC_SDTR1_TRCD FMC_SDTR1_TRCD_Msk /*!<TRP[2:0] bits (Row to column delay) */ #define FMC_SDTR1_TRCD_0 (0x1U << FMC_SDTR1_TRCD_Pos) /*!< 0x01000000 */ #define FMC_SDTR1_TRCD_1 (0x2U << FMC_SDTR1_TRCD_Pos) /*!< 0x02000000 */ #define FMC_SDTR1_TRCD_2 (0x4U << FMC_SDTR1_TRCD_Pos) /*!< 0x04000000 */ /****************** Bit definition for FMC_SDTR2 register ******************/ #define FMC_SDTR2_TMRD_Pos (0U) #define FMC_SDTR2_TMRD_Msk (0xFU << FMC_SDTR2_TMRD_Pos) /*!< 0x0000000F */ #define FMC_SDTR2_TMRD FMC_SDTR2_TMRD_Msk /*!<TMRD[3:0] bits (Load mode register to active) */ #define FMC_SDTR2_TMRD_0 (0x1U << FMC_SDTR2_TMRD_Pos) /*!< 0x00000001 */ #define FMC_SDTR2_TMRD_1 (0x2U << FMC_SDTR2_TMRD_Pos) /*!< 0x00000002 */ #define FMC_SDTR2_TMRD_2 (0x4U << FMC_SDTR2_TMRD_Pos) /*!< 0x00000004 */ #define FMC_SDTR2_TMRD_3 (0x8U << FMC_SDTR2_TMRD_Pos) /*!< 0x00000008 */ #define FMC_SDTR2_TXSR_Pos (4U) #define FMC_SDTR2_TXSR_Msk (0xFU << FMC_SDTR2_TXSR_Pos) /*!< 0x000000F0 */ #define FMC_SDTR2_TXSR FMC_SDTR2_TXSR_Msk /*!<TXSR[3:0] bits (Exit self refresh) */ #define FMC_SDTR2_TXSR_0 (0x1U << FMC_SDTR2_TXSR_Pos) /*!< 0x00000010 */ #define FMC_SDTR2_TXSR_1 (0x2U << FMC_SDTR2_TXSR_Pos) /*!< 0x00000020 */ #define FMC_SDTR2_TXSR_2 (0x4U << FMC_SDTR2_TXSR_Pos) /*!< 0x00000040 */ #define FMC_SDTR2_TXSR_3 (0x8U << FMC_SDTR2_TXSR_Pos) /*!< 0x00000080 */ #define FMC_SDTR2_TRAS_Pos (8U) #define FMC_SDTR2_TRAS_Msk (0xFU << FMC_SDTR2_TRAS_Pos) /*!< 0x00000F00 */ #define FMC_SDTR2_TRAS FMC_SDTR2_TRAS_Msk /*!<TRAS[3:0] bits (Self refresh time) */ #define FMC_SDTR2_TRAS_0 (0x1U << FMC_SDTR2_TRAS_Pos) /*!< 0x00000100 */ #define FMC_SDTR2_TRAS_1 (0x2U << FMC_SDTR2_TRAS_Pos) /*!< 0x00000200 */ #define FMC_SDTR2_TRAS_2 (0x4U << FMC_SDTR2_TRAS_Pos) /*!< 0x00000400 */ #define FMC_SDTR2_TRAS_3 (0x8U << FMC_SDTR2_TRAS_Pos) /*!< 0x00000800 */ #define FMC_SDTR2_TRC_Pos (12U) #define FMC_SDTR2_TRC_Msk (0xFU << FMC_SDTR2_TRC_Pos) /*!< 0x0000F000 */ #define FMC_SDTR2_TRC FMC_SDTR2_TRC_Msk /*!<TRC[2:0] bits (Row cycle delay) */ #define FMC_SDTR2_TRC_0 (0x1U << FMC_SDTR2_TRC_Pos) /*!< 0x00001000 */ #define FMC_SDTR2_TRC_1 (0x2U << FMC_SDTR2_TRC_Pos) /*!< 0x00002000 */ #define FMC_SDTR2_TRC_2 (0x4U << FMC_SDTR2_TRC_Pos) /*!< 0x00004000 */ #define FMC_SDTR2_TWR_Pos (16U) #define FMC_SDTR2_TWR_Msk (0xFU << FMC_SDTR2_TWR_Pos) /*!< 0x000F0000 */ #define FMC_SDTR2_TWR FMC_SDTR2_TWR_Msk /*!<TRC[2:0] bits (Write recovery delay) */ #define FMC_SDTR2_TWR_0 (0x1U << FMC_SDTR2_TWR_Pos) /*!< 0x00010000 */ #define FMC_SDTR2_TWR_1 (0x2U << FMC_SDTR2_TWR_Pos) /*!< 0x00020000 */ #define FMC_SDTR2_TWR_2 (0x4U << FMC_SDTR2_TWR_Pos) /*!< 0x00040000 */ #define FMC_SDTR2_TRP_Pos (20U) #define FMC_SDTR2_TRP_Msk (0xFU << FMC_SDTR2_TRP_Pos) /*!< 0x00F00000 */ #define FMC_SDTR2_TRP FMC_SDTR2_TRP_Msk /*!<TRP[2:0] bits (Row precharge delay) */ #define FMC_SDTR2_TRP_0 (0x1U << FMC_SDTR2_TRP_Pos) /*!< 0x00100000 */ #define FMC_SDTR2_TRP_1 (0x2U << FMC_SDTR2_TRP_Pos) /*!< 0x00200000 */ #define FMC_SDTR2_TRP_2 (0x4U << FMC_SDTR2_TRP_Pos) /*!< 0x00400000 */ #define FMC_SDTR2_TRCD_Pos (24U) #define FMC_SDTR2_TRCD_Msk (0xFU << FMC_SDTR2_TRCD_Pos) /*!< 0x0F000000 */ #define FMC_SDTR2_TRCD FMC_SDTR2_TRCD_Msk /*!<TRP[2:0] bits (Row to column delay) */ #define FMC_SDTR2_TRCD_0 (0x1U << FMC_SDTR2_TRCD_Pos) /*!< 0x01000000 */ #define FMC_SDTR2_TRCD_1 (0x2U << FMC_SDTR2_TRCD_Pos) /*!< 0x02000000 */ #define FMC_SDTR2_TRCD_2 (0x4U << FMC_SDTR2_TRCD_Pos) /*!< 0x04000000 */ /****************** Bit definition for FMC_SDCMR register ******************/ #define FMC_SDCMR_MODE_Pos (0U) #define FMC_SDCMR_MODE_Msk (0x7U << FMC_SDCMR_MODE_Pos) /*!< 0x00000007 */ #define FMC_SDCMR_MODE FMC_SDCMR_MODE_Msk /*!<MODE[2:0] bits (Command mode) */ #define FMC_SDCMR_MODE_0 (0x1U << FMC_SDCMR_MODE_Pos) /*!< 0x00000001 */ #define FMC_SDCMR_MODE_1 (0x2U << FMC_SDCMR_MODE_Pos) /*!< 0x00000002 */ #define FMC_SDCMR_MODE_2 (0x4U << FMC_SDCMR_MODE_Pos) /*!< 0x00000004 */ #define FMC_SDCMR_CTB2_Pos (3U) #define FMC_SDCMR_CTB2_Msk (0x1U << FMC_SDCMR_CTB2_Pos) /*!< 0x00000008 */ #define FMC_SDCMR_CTB2 FMC_SDCMR_CTB2_Msk /*!<Command target 2 */ #define FMC_SDCMR_CTB1_Pos (4U) #define FMC_SDCMR_CTB1_Msk (0x1U << FMC_SDCMR_CTB1_Pos) /*!< 0x00000010 */ #define FMC_SDCMR_CTB1 FMC_SDCMR_CTB1_Msk /*!<Command target 1 */ #define FMC_SDCMR_NRFS_Pos (5U) #define FMC_SDCMR_NRFS_Msk (0xFU << FMC_SDCMR_NRFS_Pos) /*!< 0x000001E0 */ #define FMC_SDCMR_NRFS FMC_SDCMR_NRFS_Msk /*!<NRFS[3:0] bits (Number of auto-refresh) */ #define FMC_SDCMR_NRFS_0 (0x1U << FMC_SDCMR_NRFS_Pos) /*!< 0x00000020 */ #define FMC_SDCMR_NRFS_1 (0x2U << FMC_SDCMR_NRFS_Pos) /*!< 0x00000040 */ #define FMC_SDCMR_NRFS_2 (0x4U << FMC_SDCMR_NRFS_Pos) /*!< 0x00000080 */ #define FMC_SDCMR_NRFS_3 (0x8U << FMC_SDCMR_NRFS_Pos) /*!< 0x00000100 */ #define FMC_SDCMR_MRD_Pos (9U) #define FMC_SDCMR_MRD_Msk (0x1FFFU << FMC_SDCMR_MRD_Pos) /*!< 0x003FFE00 */ #define FMC_SDCMR_MRD FMC_SDCMR_MRD_Msk /*!<MRD[12:0] bits (Mode register definition) */ /****************** Bit definition for FMC_SDRTR register ******************/ #define FMC_SDRTR_CRE_Pos (0U) #define FMC_SDRTR_CRE_Msk (0x1U << FMC_SDRTR_CRE_Pos) /*!< 0x00000001 */ #define FMC_SDRTR_CRE FMC_SDRTR_CRE_Msk /*!<Clear refresh error flag */ #define FMC_SDRTR_COUNT_Pos (1U) #define FMC_SDRTR_COUNT_Msk (0x1FFFU << FMC_SDRTR_COUNT_Pos) /*!< 0x00003FFE */ #define FMC_SDRTR_COUNT FMC_SDRTR_COUNT_Msk /*!<COUNT[12:0] bits (Refresh timer count) */ #define FMC_SDRTR_REIE_Pos (14U) #define FMC_SDRTR_REIE_Msk (0x1U << FMC_SDRTR_REIE_Pos) /*!< 0x00004000 */ #define FMC_SDRTR_REIE FMC_SDRTR_REIE_Msk /*!<RES interupt enable */ /****************** Bit definition for FMC_SDSR register ******************/ #define FMC_SDSR_RE_Pos (0U) #define FMC_SDSR_RE_Msk (0x1U << FMC_SDSR_RE_Pos) /*!< 0x00000001 */ #define FMC_SDSR_RE FMC_SDSR_RE_Msk /*!<Refresh error flag */ #define FMC_SDSR_MODES1_Pos (1U) #define FMC_SDSR_MODES1_Msk (0x3U << FMC_SDSR_MODES1_Pos) /*!< 0x00000006 */ #define FMC_SDSR_MODES1 FMC_SDSR_MODES1_Msk /*!<MODES1[1:0]bits (Status mode for bank 1) */ #define FMC_SDSR_MODES1_0 (0x1U << FMC_SDSR_MODES1_Pos) /*!< 0x00000002 */ #define FMC_SDSR_MODES1_1 (0x2U << FMC_SDSR_MODES1_Pos) /*!< 0x00000004 */ #define FMC_SDSR_MODES2_Pos (3U) #define FMC_SDSR_MODES2_Msk (0x3U << FMC_SDSR_MODES2_Pos) /*!< 0x00000018 */ #define FMC_SDSR_MODES2 FMC_SDSR_MODES2_Msk /*!<MODES2[1:0]bits (Status mode for bank 2) */ #define FMC_SDSR_MODES2_0 (0x1U << FMC_SDSR_MODES2_Pos) /*!< 0x00000008 */ #define FMC_SDSR_MODES2_1 (0x2U << FMC_SDSR_MODES2_Pos) /*!< 0x00000010 */ #define FMC_SDSR_BUSY_Pos (5U) #define FMC_SDSR_BUSY_Msk (0x1U << FMC_SDSR_BUSY_Pos) /*!< 0x00000020 */ #define FMC_SDSR_BUSY FMC_SDSR_BUSY_Msk /*!<Busy status */ /******************************************************************************/ /* */ /* General Purpose I/O */ /* */ /******************************************************************************/ /****************** Bits definition for GPIO_MODER register *****************/ #define GPIO_MODER_MODE0_Pos (0U) #define GPIO_MODER_MODE0_Msk (0x3U << GPIO_MODER_MODE0_Pos) /*!< 0x00000003 */ #define GPIO_MODER_MODE0 GPIO_MODER_MODE0_Msk #define GPIO_MODER_MODE0_0 (0x1U << GPIO_MODER_MODE0_Pos) /*!< 0x00000001 */ #define GPIO_MODER_MODE0_1 (0x2U << GPIO_MODER_MODE0_Pos) /*!< 0x00000002 */ #define GPIO_MODER_MODE1_Pos (2U) #define GPIO_MODER_MODE1_Msk (0x3U << GPIO_MODER_MODE1_Pos) /*!< 0x0000000C */ #define GPIO_MODER_MODE1 GPIO_MODER_MODE1_Msk #define GPIO_MODER_MODE1_0 (0x1U << GPIO_MODER_MODE1_Pos) /*!< 0x00000004 */ #define GPIO_MODER_MODE1_1 (0x2U << GPIO_MODER_MODE1_Pos) /*!< 0x00000008 */ #define GPIO_MODER_MODE2_Pos (4U) #define GPIO_MODER_MODE2_Msk (0x3U << GPIO_MODER_MODE2_Pos) /*!< 0x00000030 */ #define GPIO_MODER_MODE2 GPIO_MODER_MODE2_Msk #define GPIO_MODER_MODE2_0 (0x1U << GPIO_MODER_MODE2_Pos) /*!< 0x00000010 */ #define GPIO_MODER_MODE2_1 (0x2U << GPIO_MODER_MODE2_Pos) /*!< 0x00000020 */ #define GPIO_MODER_MODE3_Pos (6U) #define GPIO_MODER_MODE3_Msk (0x3U << GPIO_MODER_MODE3_Pos) /*!< 0x000000C0 */ #define GPIO_MODER_MODE3 GPIO_MODER_MODE3_Msk #define GPIO_MODER_MODE3_0 (0x1U << GPIO_MODER_MODE3_Pos) /*!< 0x00000040 */ #define GPIO_MODER_MODE3_1 (0x2U << GPIO_MODER_MODE3_Pos) /*!< 0x00000080 */ #define GPIO_MODER_MODE4_Pos (8U) #define GPIO_MODER_MODE4_Msk (0x3U << GPIO_MODER_MODE4_Pos) /*!< 0x00000300 */ #define GPIO_MODER_MODE4 GPIO_MODER_MODE4_Msk #define GPIO_MODER_MODE4_0 (0x1U << GPIO_MODER_MODE4_Pos) /*!< 0x00000100 */ #define GPIO_MODER_MODE4_1 (0x2U << GPIO_MODER_MODE4_Pos) /*!< 0x00000200 */ #define GPIO_MODER_MODE5_Pos (10U) #define GPIO_MODER_MODE5_Msk (0x3U << GPIO_MODER_MODE5_Pos) /*!< 0x00000C00 */ #define GPIO_MODER_MODE5 GPIO_MODER_MODE5_Msk #define GPIO_MODER_MODE5_0 (0x1U << GPIO_MODER_MODE5_Pos) /*!< 0x00000400 */ #define GPIO_MODER_MODE5_1 (0x2U << GPIO_MODER_MODE5_Pos) /*!< 0x00000800 */ #define GPIO_MODER_MODE6_Pos (12U) #define GPIO_MODER_MODE6_Msk (0x3U << GPIO_MODER_MODE6_Pos) /*!< 0x00003000 */ #define GPIO_MODER_MODE6 GPIO_MODER_MODE6_Msk #define GPIO_MODER_MODE6_0 (0x1U << GPIO_MODER_MODE6_Pos) /*!< 0x00001000 */ #define GPIO_MODER_MODE6_1 (0x2U << GPIO_MODER_MODE6_Pos) /*!< 0x00002000 */ #define GPIO_MODER_MODE7_Pos (14U) #define GPIO_MODER_MODE7_Msk (0x3U << GPIO_MODER_MODE7_Pos) /*!< 0x0000C000 */ #define GPIO_MODER_MODE7 GPIO_MODER_MODE7_Msk #define GPIO_MODER_MODE7_0 (0x1U << GPIO_MODER_MODE7_Pos) /*!< 0x00004000 */ #define GPIO_MODER_MODE7_1 (0x2U << GPIO_MODER_MODE7_Pos) /*!< 0x00008000 */ #define GPIO_MODER_MODE8_Pos (16U) #define GPIO_MODER_MODE8_Msk (0x3U << GPIO_MODER_MODE8_Pos) /*!< 0x00030000 */ #define GPIO_MODER_MODE8 GPIO_MODER_MODE8_Msk #define GPIO_MODER_MODE8_0 (0x1U << GPIO_MODER_MODE8_Pos) /*!< 0x00010000 */ #define GPIO_MODER_MODE8_1 (0x2U << GPIO_MODER_MODE8_Pos) /*!< 0x00020000 */ #define GPIO_MODER_MODE9_Pos (18U) #define GPIO_MODER_MODE9_Msk (0x3U << GPIO_MODER_MODE9_Pos) /*!< 0x000C0000 */ #define GPIO_MODER_MODE9 GPIO_MODER_MODE9_Msk #define GPIO_MODER_MODE9_0 (0x1U << GPIO_MODER_MODE9_Pos) /*!< 0x00040000 */ #define GPIO_MODER_MODE9_1 (0x2U << GPIO_MODER_MODE9_Pos) /*!< 0x00080000 */ #define GPIO_MODER_MODE10_Pos (20U) #define GPIO_MODER_MODE10_Msk (0x3U << GPIO_MODER_MODE10_Pos) /*!< 0x00300000 */ #define GPIO_MODER_MODE10 GPIO_MODER_MODE10_Msk #define GPIO_MODER_MODE10_0 (0x1U << GPIO_MODER_MODE10_Pos) /*!< 0x00100000 */ #define GPIO_MODER_MODE10_1 (0x2U << GPIO_MODER_MODE10_Pos) /*!< 0x00200000 */ #define GPIO_MODER_MODE11_Pos (22U) #define GPIO_MODER_MODE11_Msk (0x3U << GPIO_MODER_MODE11_Pos) /*!< 0x00C00000 */ #define GPIO_MODER_MODE11 GPIO_MODER_MODE11_Msk #define GPIO_MODER_MODE11_0 (0x1U << GPIO_MODER_MODE11_Pos) /*!< 0x00400000 */ #define GPIO_MODER_MODE11_1 (0x2U << GPIO_MODER_MODE11_Pos) /*!< 0x00800000 */ #define GPIO_MODER_MODE12_Pos (24U) #define GPIO_MODER_MODE12_Msk (0x3U << GPIO_MODER_MODE12_Pos) /*!< 0x03000000 */ #define GPIO_MODER_MODE12 GPIO_MODER_MODE12_Msk #define GPIO_MODER_MODE12_0 (0x1U << GPIO_MODER_MODE12_Pos) /*!< 0x01000000 */ #define GPIO_MODER_MODE12_1 (0x2U << GPIO_MODER_MODE12_Pos) /*!< 0x02000000 */ #define GPIO_MODER_MODE13_Pos (26U) #define GPIO_MODER_MODE13_Msk (0x3U << GPIO_MODER_MODE13_Pos) /*!< 0x0C000000 */ #define GPIO_MODER_MODE13 GPIO_MODER_MODE13_Msk #define GPIO_MODER_MODE13_0 (0x1U << GPIO_MODER_MODE13_Pos) /*!< 0x04000000 */ #define GPIO_MODER_MODE13_1 (0x2U << GPIO_MODER_MODE13_Pos) /*!< 0x08000000 */ #define GPIO_MODER_MODE14_Pos (28U) #define GPIO_MODER_MODE14_Msk (0x3U << GPIO_MODER_MODE14_Pos) /*!< 0x30000000 */ #define GPIO_MODER_MODE14 GPIO_MODER_MODE14_Msk #define GPIO_MODER_MODE14_0 (0x1U << GPIO_MODER_MODE14_Pos) /*!< 0x10000000 */ #define GPIO_MODER_MODE14_1 (0x2U << GPIO_MODER_MODE14_Pos) /*!< 0x20000000 */ #define GPIO_MODER_MODE15_Pos (30U) #define GPIO_MODER_MODE15_Msk (0x3U << GPIO_MODER_MODE15_Pos) /*!< 0xC0000000 */ #define GPIO_MODER_MODE15 GPIO_MODER_MODE15_Msk #define GPIO_MODER_MODE15_0 (0x1U << GPIO_MODER_MODE15_Pos) /*!< 0x40000000 */ #define GPIO_MODER_MODE15_1 (0x2U << GPIO_MODER_MODE15_Pos) /*!< 0x80000000 */ /* Legacy defines */ #define GPIO_MODER_MODER0_Pos (0U) #define GPIO_MODER_MODER0_Msk (0x3U << GPIO_MODER_MODER0_Pos) /*!< 0x00000003 */ #define GPIO_MODER_MODER0 GPIO_MODER_MODER0_Msk #define GPIO_MODER_MODER0_0 (0x1U << GPIO_MODER_MODER0_Pos) /*!< 0x00000001 */ #define GPIO_MODER_MODER0_1 (0x2U << GPIO_MODER_MODER0_Pos) /*!< 0x00000002 */ #define GPIO_MODER_MODER1_Pos (2U) #define GPIO_MODER_MODER1_Msk (0x3U << GPIO_MODER_MODER1_Pos) /*!< 0x0000000C */ #define GPIO_MODER_MODER1 GPIO_MODER_MODER1_Msk #define GPIO_MODER_MODER1_0 (0x1U << GPIO_MODER_MODER1_Pos) /*!< 0x00000004 */ #define GPIO_MODER_MODER1_1 (0x2U << GPIO_MODER_MODER1_Pos) /*!< 0x00000008 */ #define GPIO_MODER_MODER2_Pos (4U) #define GPIO_MODER_MODER2_Msk (0x3U << GPIO_MODER_MODER2_Pos) /*!< 0x00000030 */ #define GPIO_MODER_MODER2 GPIO_MODER_MODER2_Msk #define GPIO_MODER_MODER2_0 (0x1U << GPIO_MODER_MODER2_Pos) /*!< 0x00000010 */ #define GPIO_MODER_MODER2_1 (0x2U << GPIO_MODER_MODER2_Pos) /*!< 0x00000020 */ #define GPIO_MODER_MODER3_Pos (6U) #define GPIO_MODER_MODER3_Msk (0x3U << GPIO_MODER_MODER3_Pos) /*!< 0x000000C0 */ #define GPIO_MODER_MODER3 GPIO_MODER_MODER3_Msk #define GPIO_MODER_MODER3_0 (0x1U << GPIO_MODER_MODER3_Pos) /*!< 0x00000040 */ #define GPIO_MODER_MODER3_1 (0x2U << GPIO_MODER_MODER3_Pos) /*!< 0x00000080 */ #define GPIO_MODER_MODER4_Pos (8U) #define GPIO_MODER_MODER4_Msk (0x3U << GPIO_MODER_MODER4_Pos) /*!< 0x00000300 */ #define GPIO_MODER_MODER4 GPIO_MODER_MODER4_Msk #define GPIO_MODER_MODER4_0 (0x1U << GPIO_MODER_MODER4_Pos) /*!< 0x00000100 */ #define GPIO_MODER_MODER4_1 (0x2U << GPIO_MODER_MODER4_Pos) /*!< 0x00000200 */ #define GPIO_MODER_MODER5_Pos (10U) #define GPIO_MODER_MODER5_Msk (0x3U << GPIO_MODER_MODER5_Pos) /*!< 0x00000C00 */ #define GPIO_MODER_MODER5 GPIO_MODER_MODER5_Msk #define GPIO_MODER_MODER5_0 (0x1U << GPIO_MODER_MODER5_Pos) /*!< 0x00000400 */ #define GPIO_MODER_MODER5_1 (0x2U << GPIO_MODER_MODER5_Pos) /*!< 0x00000800 */ #define GPIO_MODER_MODER6_Pos (12U) #define GPIO_MODER_MODER6_Msk (0x3U << GPIO_MODER_MODER6_Pos) /*!< 0x00003000 */ #define GPIO_MODER_MODER6 GPIO_MODER_MODER6_Msk #define GPIO_MODER_MODER6_0 (0x1U << GPIO_MODER_MODER6_Pos) /*!< 0x00001000 */ #define GPIO_MODER_MODER6_1 (0x2U << GPIO_MODER_MODER6_Pos) /*!< 0x00002000 */ #define GPIO_MODER_MODER7_Pos (14U) #define GPIO_MODER_MODER7_Msk (0x3U << GPIO_MODER_MODER7_Pos) /*!< 0x0000C000 */ #define GPIO_MODER_MODER7 GPIO_MODER_MODER7_Msk #define GPIO_MODER_MODER7_0 (0x1U << GPIO_MODER_MODER7_Pos) /*!< 0x00004000 */ #define GPIO_MODER_MODER7_1 (0x2U << GPIO_MODER_MODER7_Pos) /*!< 0x00008000 */ #define GPIO_MODER_MODER8_Pos (16U) #define GPIO_MODER_MODER8_Msk (0x3U << GPIO_MODER_MODER8_Pos) /*!< 0x00030000 */ #define GPIO_MODER_MODER8 GPIO_MODER_MODER8_Msk #define GPIO_MODER_MODER8_0 (0x1U << GPIO_MODER_MODER8_Pos) /*!< 0x00010000 */ #define GPIO_MODER_MODER8_1 (0x2U << GPIO_MODER_MODER8_Pos) /*!< 0x00020000 */ #define GPIO_MODER_MODER9_Pos (18U) #define GPIO_MODER_MODER9_Msk (0x3U << GPIO_MODER_MODER9_Pos) /*!< 0x000C0000 */ #define GPIO_MODER_MODER9 GPIO_MODER_MODER9_Msk #define GPIO_MODER_MODER9_0 (0x1U << GPIO_MODER_MODER9_Pos) /*!< 0x00040000 */ #define GPIO_MODER_MODER9_1 (0x2U << GPIO_MODER_MODER9_Pos) /*!< 0x00080000 */ #define GPIO_MODER_MODER10_Pos (20U) #define GPIO_MODER_MODER10_Msk (0x3U << GPIO_MODER_MODER10_Pos) /*!< 0x00300000 */ #define GPIO_MODER_MODER10 GPIO_MODER_MODER10_Msk #define GPIO_MODER_MODER10_0 (0x1U << GPIO_MODER_MODER10_Pos) /*!< 0x00100000 */ #define GPIO_MODER_MODER10_1 (0x2U << GPIO_MODER_MODER10_Pos) /*!< 0x00200000 */ #define GPIO_MODER_MODER11_Pos (22U) #define GPIO_MODER_MODER11_Msk (0x3U << GPIO_MODER_MODER11_Pos) /*!< 0x00C00000 */ #define GPIO_MODER_MODER11 GPIO_MODER_MODER11_Msk #define GPIO_MODER_MODER11_0 (0x1U << GPIO_MODER_MODER11_Pos) /*!< 0x00400000 */ #define GPIO_MODER_MODER11_1 (0x2U << GPIO_MODER_MODER11_Pos) /*!< 0x00800000 */ #define GPIO_MODER_MODER12_Pos (24U) #define GPIO_MODER_MODER12_Msk (0x3U << GPIO_MODER_MODER12_Pos) /*!< 0x03000000 */ #define GPIO_MODER_MODER12 GPIO_MODER_MODER12_Msk #define GPIO_MODER_MODER12_0 (0x1U << GPIO_MODER_MODER12_Pos) /*!< 0x01000000 */ #define GPIO_MODER_MODER12_1 (0x2U << GPIO_MODER_MODER12_Pos) /*!< 0x02000000 */ #define GPIO_MODER_MODER13_Pos (26U) #define GPIO_MODER_MODER13_Msk (0x3U << GPIO_MODER_MODER13_Pos) /*!< 0x0C000000 */ #define GPIO_MODER_MODER13 GPIO_MODER_MODER13_Msk #define GPIO_MODER_MODER13_0 (0x1U << GPIO_MODER_MODER13_Pos) /*!< 0x04000000 */ #define GPIO_MODER_MODER13_1 (0x2U << GPIO_MODER_MODER13_Pos) /*!< 0x08000000 */ #define GPIO_MODER_MODER14_Pos (28U) #define GPIO_MODER_MODER14_Msk (0x3U << GPIO_MODER_MODER14_Pos) /*!< 0x30000000 */ #define GPIO_MODER_MODER14 GPIO_MODER_MODER14_Msk #define GPIO_MODER_MODER14_0 (0x1U << GPIO_MODER_MODER14_Pos) /*!< 0x10000000 */ #define GPIO_MODER_MODER14_1 (0x2U << GPIO_MODER_MODER14_Pos) /*!< 0x20000000 */ #define GPIO_MODER_MODER15_Pos (30U) #define GPIO_MODER_MODER15_Msk (0x3U << GPIO_MODER_MODER15_Pos) /*!< 0xC0000000 */ #define GPIO_MODER_MODER15 GPIO_MODER_MODER15_Msk #define GPIO_MODER_MODER15_0 (0x1U << GPIO_MODER_MODER15_Pos) /*!< 0x40000000 */ #define GPIO_MODER_MODER15_1 (0x2U << GPIO_MODER_MODER15_Pos) /*!< 0x80000000 */ /****************** Bits definition for GPIO_OTYPER register ****************/ #define GPIO_OTYPER_OT0_Pos (0U) #define GPIO_OTYPER_OT0_Msk (0x1U << GPIO_OTYPER_OT0_Pos) /*!< 0x00000001 */ #define GPIO_OTYPER_OT0 GPIO_OTYPER_OT0_Msk #define GPIO_OTYPER_OT1_Pos (1U) #define GPIO_OTYPER_OT1_Msk (0x1U << GPIO_OTYPER_OT1_Pos) /*!< 0x00000002 */ #define GPIO_OTYPER_OT1 GPIO_OTYPER_OT1_Msk #define GPIO_OTYPER_OT2_Pos (2U) #define GPIO_OTYPER_OT2_Msk (0x1U << GPIO_OTYPER_OT2_Pos) /*!< 0x00000004 */ #define GPIO_OTYPER_OT2 GPIO_OTYPER_OT2_Msk #define GPIO_OTYPER_OT3_Pos (3U) #define GPIO_OTYPER_OT3_Msk (0x1U << GPIO_OTYPER_OT3_Pos) /*!< 0x00000008 */ #define GPIO_OTYPER_OT3 GPIO_OTYPER_OT3_Msk #define GPIO_OTYPER_OT4_Pos (4U) #define GPIO_OTYPER_OT4_Msk (0x1U << GPIO_OTYPER_OT4_Pos) /*!< 0x00000010 */ #define GPIO_OTYPER_OT4 GPIO_OTYPER_OT4_Msk #define GPIO_OTYPER_OT5_Pos (5U) #define GPIO_OTYPER_OT5_Msk (0x1U << GPIO_OTYPER_OT5_Pos) /*!< 0x00000020 */ #define GPIO_OTYPER_OT5 GPIO_OTYPER_OT5_Msk #define GPIO_OTYPER_OT6_Pos (6U) #define GPIO_OTYPER_OT6_Msk (0x1U << GPIO_OTYPER_OT6_Pos) /*!< 0x00000040 */ #define GPIO_OTYPER_OT6 GPIO_OTYPER_OT6_Msk #define GPIO_OTYPER_OT7_Pos (7U) #define GPIO_OTYPER_OT7_Msk (0x1U << GPIO_OTYPER_OT7_Pos) /*!< 0x00000080 */ #define GPIO_OTYPER_OT7 GPIO_OTYPER_OT7_Msk #define GPIO_OTYPER_OT8_Pos (8U) #define GPIO_OTYPER_OT8_Msk (0x1U << GPIO_OTYPER_OT8_Pos) /*!< 0x00000100 */ #define GPIO_OTYPER_OT8 GPIO_OTYPER_OT8_Msk #define GPIO_OTYPER_OT9_Pos (9U) #define GPIO_OTYPER_OT9_Msk (0x1U << GPIO_OTYPER_OT9_Pos) /*!< 0x00000200 */ #define GPIO_OTYPER_OT9 GPIO_OTYPER_OT9_Msk #define GPIO_OTYPER_OT10_Pos (10U) #define GPIO_OTYPER_OT10_Msk (0x1U << GPIO_OTYPER_OT10_Pos) /*!< 0x00000400 */ #define GPIO_OTYPER_OT10 GPIO_OTYPER_OT10_Msk #define GPIO_OTYPER_OT11_Pos (11U) #define GPIO_OTYPER_OT11_Msk (0x1U << GPIO_OTYPER_OT11_Pos) /*!< 0x00000800 */ #define GPIO_OTYPER_OT11 GPIO_OTYPER_OT11_Msk #define GPIO_OTYPER_OT12_Pos (12U) #define GPIO_OTYPER_OT12_Msk (0x1U << GPIO_OTYPER_OT12_Pos) /*!< 0x00001000 */ #define GPIO_OTYPER_OT12 GPIO_OTYPER_OT12_Msk #define GPIO_OTYPER_OT13_Pos (13U) #define GPIO_OTYPER_OT13_Msk (0x1U << GPIO_OTYPER_OT13_Pos) /*!< 0x00002000 */ #define GPIO_OTYPER_OT13 GPIO_OTYPER_OT13_Msk #define GPIO_OTYPER_OT14_Pos (14U) #define GPIO_OTYPER_OT14_Msk (0x1U << GPIO_OTYPER_OT14_Pos) /*!< 0x00004000 */ #define GPIO_OTYPER_OT14 GPIO_OTYPER_OT14_Msk #define GPIO_OTYPER_OT15_Pos (15U) #define GPIO_OTYPER_OT15_Msk (0x1U << GPIO_OTYPER_OT15_Pos) /*!< 0x00008000 */ #define GPIO_OTYPER_OT15 GPIO_OTYPER_OT15_Msk /* Legacy defines */ #define GPIO_OTYPER_OT_0 GPIO_OTYPER_OT0 #define GPIO_OTYPER_OT_1 GPIO_OTYPER_OT1 #define GPIO_OTYPER_OT_2 GPIO_OTYPER_OT2 #define GPIO_OTYPER_OT_3 GPIO_OTYPER_OT3 #define GPIO_OTYPER_OT_4 GPIO_OTYPER_OT4 #define GPIO_OTYPER_OT_5 GPIO_OTYPER_OT5 #define GPIO_OTYPER_OT_6 GPIO_OTYPER_OT6 #define GPIO_OTYPER_OT_7 GPIO_OTYPER_OT7 #define GPIO_OTYPER_OT_8 GPIO_OTYPER_OT8 #define GPIO_OTYPER_OT_9 GPIO_OTYPER_OT9 #define GPIO_OTYPER_OT_10 GPIO_OTYPER_OT10 #define GPIO_OTYPER_OT_11 GPIO_OTYPER_OT11 #define GPIO_OTYPER_OT_12 GPIO_OTYPER_OT12 #define GPIO_OTYPER_OT_13 GPIO_OTYPER_OT13 #define GPIO_OTYPER_OT_14 GPIO_OTYPER_OT14 #define GPIO_OTYPER_OT_15 GPIO_OTYPER_OT15 /****************** Bits definition for GPIO_OSPEEDR register ***************/ #define GPIO_OSPEEDR_OSPEED0_Pos (0U) #define GPIO_OSPEEDR_OSPEED0_Msk (0x3U << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000003 */ #define GPIO_OSPEEDR_OSPEED0 GPIO_OSPEEDR_OSPEED0_Msk #define GPIO_OSPEEDR_OSPEED0_0 (0x1U << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000001 */ #define GPIO_OSPEEDR_OSPEED0_1 (0x2U << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000002 */ #define GPIO_OSPEEDR_OSPEED1_Pos (2U) #define GPIO_OSPEEDR_OSPEED1_Msk (0x3U << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x0000000C */ #define GPIO_OSPEEDR_OSPEED1 GPIO_OSPEEDR_OSPEED1_Msk #define GPIO_OSPEEDR_OSPEED1_0 (0x1U << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x00000004 */ #define GPIO_OSPEEDR_OSPEED1_1 (0x2U << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x00000008 */ #define GPIO_OSPEEDR_OSPEED2_Pos (4U) #define GPIO_OSPEEDR_OSPEED2_Msk (0x3U << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000030 */ #define GPIO_OSPEEDR_OSPEED2 GPIO_OSPEEDR_OSPEED2_Msk #define GPIO_OSPEEDR_OSPEED2_0 (0x1U << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000010 */ #define GPIO_OSPEEDR_OSPEED2_1 (0x2U << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000020 */ #define GPIO_OSPEEDR_OSPEED3_Pos (6U) #define GPIO_OSPEEDR_OSPEED3_Msk (0x3U << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x000000C0 */ #define GPIO_OSPEEDR_OSPEED3 GPIO_OSPEEDR_OSPEED3_Msk #define GPIO_OSPEEDR_OSPEED3_0 (0x1U << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x00000040 */ #define GPIO_OSPEEDR_OSPEED3_1 (0x2U << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x00000080 */ #define GPIO_OSPEEDR_OSPEED4_Pos (8U) #define GPIO_OSPEEDR_OSPEED4_Msk (0x3U << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000300 */ #define GPIO_OSPEEDR_OSPEED4 GPIO_OSPEEDR_OSPEED4_Msk #define GPIO_OSPEEDR_OSPEED4_0 (0x1U << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000100 */ #define GPIO_OSPEEDR_OSPEED4_1 (0x2U << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000200 */ #define GPIO_OSPEEDR_OSPEED5_Pos (10U) #define GPIO_OSPEEDR_OSPEED5_Msk (0x3U << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000C00 */ #define GPIO_OSPEEDR_OSPEED5 GPIO_OSPEEDR_OSPEED5_Msk #define GPIO_OSPEEDR_OSPEED5_0 (0x1U << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000400 */ #define GPIO_OSPEEDR_OSPEED5_1 (0x2U << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000800 */ #define GPIO_OSPEEDR_OSPEED6_Pos (12U) #define GPIO_OSPEEDR_OSPEED6_Msk (0x3U << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00003000 */ #define GPIO_OSPEEDR_OSPEED6 GPIO_OSPEEDR_OSPEED6_Msk #define GPIO_OSPEEDR_OSPEED6_0 (0x1U << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00001000 */ #define GPIO_OSPEEDR_OSPEED6_1 (0x2U << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00002000 */ #define GPIO_OSPEEDR_OSPEED7_Pos (14U) #define GPIO_OSPEEDR_OSPEED7_Msk (0x3U << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x0000C000 */ #define GPIO_OSPEEDR_OSPEED7 GPIO_OSPEEDR_OSPEED7_Msk #define GPIO_OSPEEDR_OSPEED7_0 (0x1U << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x00004000 */ #define GPIO_OSPEEDR_OSPEED7_1 (0x2U << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x00008000 */ #define GPIO_OSPEEDR_OSPEED8_Pos (16U) #define GPIO_OSPEEDR_OSPEED8_Msk (0x3U << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00030000 */ #define GPIO_OSPEEDR_OSPEED8 GPIO_OSPEEDR_OSPEED8_Msk #define GPIO_OSPEEDR_OSPEED8_0 (0x1U << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00010000 */ #define GPIO_OSPEEDR_OSPEED8_1 (0x2U << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00020000 */ #define GPIO_OSPEEDR_OSPEED9_Pos (18U) #define GPIO_OSPEEDR_OSPEED9_Msk (0x3U << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x000C0000 */ #define GPIO_OSPEEDR_OSPEED9 GPIO_OSPEEDR_OSPEED9_Msk #define GPIO_OSPEEDR_OSPEED9_0 (0x1U << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x00040000 */ #define GPIO_OSPEEDR_OSPEED9_1 (0x2U << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x00080000 */ #define GPIO_OSPEEDR_OSPEED10_Pos (20U) #define GPIO_OSPEEDR_OSPEED10_Msk (0x3U << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00300000 */ #define GPIO_OSPEEDR_OSPEED10 GPIO_OSPEEDR_OSPEED10_Msk #define GPIO_OSPEEDR_OSPEED10_0 (0x1U << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00100000 */ #define GPIO_OSPEEDR_OSPEED10_1 (0x2U << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00200000 */ #define GPIO_OSPEEDR_OSPEED11_Pos (22U) #define GPIO_OSPEEDR_OSPEED11_Msk (0x3U << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00C00000 */ #define GPIO_OSPEEDR_OSPEED11 GPIO_OSPEEDR_OSPEED11_Msk #define GPIO_OSPEEDR_OSPEED11_0 (0x1U << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00400000 */ #define GPIO_OSPEEDR_OSPEED11_1 (0x2U << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00800000 */ #define GPIO_OSPEEDR_OSPEED12_Pos (24U) #define GPIO_OSPEEDR_OSPEED12_Msk (0x3U << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x03000000 */ #define GPIO_OSPEEDR_OSPEED12 GPIO_OSPEEDR_OSPEED12_Msk #define GPIO_OSPEEDR_OSPEED12_0 (0x1U << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x01000000 */ #define GPIO_OSPEEDR_OSPEED12_1 (0x2U << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x02000000 */ #define GPIO_OSPEEDR_OSPEED13_Pos (26U) #define GPIO_OSPEEDR_OSPEED13_Msk (0x3U << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x0C000000 */ #define GPIO_OSPEEDR_OSPEED13 GPIO_OSPEEDR_OSPEED13_Msk #define GPIO_OSPEEDR_OSPEED13_0 (0x1U << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x04000000 */ #define GPIO_OSPEEDR_OSPEED13_1 (0x2U << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x08000000 */ #define GPIO_OSPEEDR_OSPEED14_Pos (28U) #define GPIO_OSPEEDR_OSPEED14_Msk (0x3U << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x30000000 */ #define GPIO_OSPEEDR_OSPEED14 GPIO_OSPEEDR_OSPEED14_Msk #define GPIO_OSPEEDR_OSPEED14_0 (0x1U << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x10000000 */ #define GPIO_OSPEEDR_OSPEED14_1 (0x2U << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x20000000 */ #define GPIO_OSPEEDR_OSPEED15_Pos (30U) #define GPIO_OSPEEDR_OSPEED15_Msk (0x3U << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0xC0000000 */ #define GPIO_OSPEEDR_OSPEED15 GPIO_OSPEEDR_OSPEED15_Msk #define GPIO_OSPEEDR_OSPEED15_0 (0x1U << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0x40000000 */ #define GPIO_OSPEEDR_OSPEED15_1 (0x2U << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0x80000000 */ /* Legacy defines */ #define GPIO_OSPEEDER_OSPEEDR0 GPIO_OSPEEDR_OSPEED0 #define GPIO_OSPEEDER_OSPEEDR0_0 GPIO_OSPEEDR_OSPEED0_0 #define GPIO_OSPEEDER_OSPEEDR0_1 GPIO_OSPEEDR_OSPEED0_1 #define GPIO_OSPEEDER_OSPEEDR1 GPIO_OSPEEDR_OSPEED1 #define GPIO_OSPEEDER_OSPEEDR1_0 GPIO_OSPEEDR_OSPEED1_0 #define GPIO_OSPEEDER_OSPEEDR1_1 GPIO_OSPEEDR_OSPEED1_1 #define GPIO_OSPEEDER_OSPEEDR2 GPIO_OSPEEDR_OSPEED2 #define GPIO_OSPEEDER_OSPEEDR2_0 GPIO_OSPEEDR_OSPEED2_0 #define GPIO_OSPEEDER_OSPEEDR2_1 GPIO_OSPEEDR_OSPEED2_1 #define GPIO_OSPEEDER_OSPEEDR3 GPIO_OSPEEDR_OSPEED3 #define GPIO_OSPEEDER_OSPEEDR3_0 GPIO_OSPEEDR_OSPEED3_0 #define GPIO_OSPEEDER_OSPEEDR3_1 GPIO_OSPEEDR_OSPEED3_1 #define GPIO_OSPEEDER_OSPEEDR4 GPIO_OSPEEDR_OSPEED4 #define GPIO_OSPEEDER_OSPEEDR4_0 GPIO_OSPEEDR_OSPEED4_0 #define GPIO_OSPEEDER_OSPEEDR4_1 GPIO_OSPEEDR_OSPEED4_1 #define GPIO_OSPEEDER_OSPEEDR5 GPIO_OSPEEDR_OSPEED5 #define GPIO_OSPEEDER_OSPEEDR5_0 GPIO_OSPEEDR_OSPEED5_0 #define GPIO_OSPEEDER_OSPEEDR5_1 GPIO_OSPEEDR_OSPEED5_1 #define GPIO_OSPEEDER_OSPEEDR6 GPIO_OSPEEDR_OSPEED6 #define GPIO_OSPEEDER_OSPEEDR6_0 GPIO_OSPEEDR_OSPEED6_0 #define GPIO_OSPEEDER_OSPEEDR6_1 GPIO_OSPEEDR_OSPEED6_1 #define GPIO_OSPEEDER_OSPEEDR7 GPIO_OSPEEDR_OSPEED7 #define GPIO_OSPEEDER_OSPEEDR7_0 GPIO_OSPEEDR_OSPEED7_0 #define GPIO_OSPEEDER_OSPEEDR7_1 GPIO_OSPEEDR_OSPEED7_1 #define GPIO_OSPEEDER_OSPEEDR8 GPIO_OSPEEDR_OSPEED8 #define GPIO_OSPEEDER_OSPEEDR8_0 GPIO_OSPEEDR_OSPEED8_0 #define GPIO_OSPEEDER_OSPEEDR8_1 GPIO_OSPEEDR_OSPEED8_1 #define GPIO_OSPEEDER_OSPEEDR9 GPIO_OSPEEDR_OSPEED9 #define GPIO_OSPEEDER_OSPEEDR9_0 GPIO_OSPEEDR_OSPEED9_0 #define GPIO_OSPEEDER_OSPEEDR9_1 GPIO_OSPEEDR_OSPEED9_1 #define GPIO_OSPEEDER_OSPEEDR10 GPIO_OSPEEDR_OSPEED10 #define GPIO_OSPEEDER_OSPEEDR10_0 GPIO_OSPEEDR_OSPEED10_0 #define GPIO_OSPEEDER_OSPEEDR10_1 GPIO_OSPEEDR_OSPEED10_1 #define GPIO_OSPEEDER_OSPEEDR11 GPIO_OSPEEDR_OSPEED11 #define GPIO_OSPEEDER_OSPEEDR11_0 GPIO_OSPEEDR_OSPEED11_0 #define GPIO_OSPEEDER_OSPEEDR11_1 GPIO_OSPEEDR_OSPEED11_1 #define GPIO_OSPEEDER_OSPEEDR12 GPIO_OSPEEDR_OSPEED12 #define GPIO_OSPEEDER_OSPEEDR12_0 GPIO_OSPEEDR_OSPEED12_0 #define GPIO_OSPEEDER_OSPEEDR12_1 GPIO_OSPEEDR_OSPEED12_1 #define GPIO_OSPEEDER_OSPEEDR13 GPIO_OSPEEDR_OSPEED13 #define GPIO_OSPEEDER_OSPEEDR13_0 GPIO_OSPEEDR_OSPEED13_0 #define GPIO_OSPEEDER_OSPEEDR13_1 GPIO_OSPEEDR_OSPEED13_1 #define GPIO_OSPEEDER_OSPEEDR14 GPIO_OSPEEDR_OSPEED14 #define GPIO_OSPEEDER_OSPEEDR14_0 GPIO_OSPEEDR_OSPEED14_0 #define GPIO_OSPEEDER_OSPEEDR14_1 GPIO_OSPEEDR_OSPEED14_1 #define GPIO_OSPEEDER_OSPEEDR15 GPIO_OSPEEDR_OSPEED15 #define GPIO_OSPEEDER_OSPEEDR15_0 GPIO_OSPEEDR_OSPEED15_0 #define GPIO_OSPEEDER_OSPEEDR15_1 GPIO_OSPEEDR_OSPEED15_1 /****************** Bits definition for GPIO_PUPDR register *****************/ #define GPIO_PUPDR_PUPD0_Pos (0U) #define GPIO_PUPDR_PUPD0_Msk (0x3U << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000003 */ #define GPIO_PUPDR_PUPD0 GPIO_PUPDR_PUPD0_Msk #define GPIO_PUPDR_PUPD0_0 (0x1U << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000001 */ #define GPIO_PUPDR_PUPD0_1 (0x2U << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000002 */ #define GPIO_PUPDR_PUPD1_Pos (2U) #define GPIO_PUPDR_PUPD1_Msk (0x3U << GPIO_PUPDR_PUPD1_Pos) /*!< 0x0000000C */ #define GPIO_PUPDR_PUPD1 GPIO_PUPDR_PUPD1_Msk #define GPIO_PUPDR_PUPD1_0 (0x1U << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000004 */ #define GPIO_PUPDR_PUPD1_1 (0x2U << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000008 */ #define GPIO_PUPDR_PUPD2_Pos (4U) #define GPIO_PUPDR_PUPD2_Msk (0x3U << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000030 */ #define GPIO_PUPDR_PUPD2 GPIO_PUPDR_PUPD2_Msk #define GPIO_PUPDR_PUPD2_0 (0x1U << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000010 */ #define GPIO_PUPDR_PUPD2_1 (0x2U << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000020 */ #define GPIO_PUPDR_PUPD3_Pos (6U) #define GPIO_PUPDR_PUPD3_Msk (0x3U << GPIO_PUPDR_PUPD3_Pos) /*!< 0x000000C0 */ #define GPIO_PUPDR_PUPD3 GPIO_PUPDR_PUPD3_Msk #define GPIO_PUPDR_PUPD3_0 (0x1U << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000040 */ #define GPIO_PUPDR_PUPD3_1 (0x2U << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000080 */ #define GPIO_PUPDR_PUPD4_Pos (8U) #define GPIO_PUPDR_PUPD4_Msk (0x3U << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000300 */ #define GPIO_PUPDR_PUPD4 GPIO_PUPDR_PUPD4_Msk #define GPIO_PUPDR_PUPD4_0 (0x1U << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000100 */ #define GPIO_PUPDR_PUPD4_1 (0x2U << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000200 */ #define GPIO_PUPDR_PUPD5_Pos (10U) #define GPIO_PUPDR_PUPD5_Msk (0x3U << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000C00 */ #define GPIO_PUPDR_PUPD5 GPIO_PUPDR_PUPD5_Msk #define GPIO_PUPDR_PUPD5_0 (0x1U << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000400 */ #define GPIO_PUPDR_PUPD5_1 (0x2U << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000800 */ #define GPIO_PUPDR_PUPD6_Pos (12U) #define GPIO_PUPDR_PUPD6_Msk (0x3U << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00003000 */ #define GPIO_PUPDR_PUPD6 GPIO_PUPDR_PUPD6_Msk #define GPIO_PUPDR_PUPD6_0 (0x1U << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00001000 */ #define GPIO_PUPDR_PUPD6_1 (0x2U << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00002000 */ #define GPIO_PUPDR_PUPD7_Pos (14U) #define GPIO_PUPDR_PUPD7_Msk (0x3U << GPIO_PUPDR_PUPD7_Pos) /*!< 0x0000C000 */ #define GPIO_PUPDR_PUPD7 GPIO_PUPDR_PUPD7_Msk #define GPIO_PUPDR_PUPD7_0 (0x1U << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00004000 */ #define GPIO_PUPDR_PUPD7_1 (0x2U << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00008000 */ #define GPIO_PUPDR_PUPD8_Pos (16U) #define GPIO_PUPDR_PUPD8_Msk (0x3U << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00030000 */ #define GPIO_PUPDR_PUPD8 GPIO_PUPDR_PUPD8_Msk #define GPIO_PUPDR_PUPD8_0 (0x1U << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00010000 */ #define GPIO_PUPDR_PUPD8_1 (0x2U << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00020000 */ #define GPIO_PUPDR_PUPD9_Pos (18U) #define GPIO_PUPDR_PUPD9_Msk (0x3U << GPIO_PUPDR_PUPD9_Pos) /*!< 0x000C0000 */ #define GPIO_PUPDR_PUPD9 GPIO_PUPDR_PUPD9_Msk #define GPIO_PUPDR_PUPD9_0 (0x1U << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00040000 */ #define GPIO_PUPDR_PUPD9_1 (0x2U << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00080000 */ #define GPIO_PUPDR_PUPD10_Pos (20U) #define GPIO_PUPDR_PUPD10_Msk (0x3U << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00300000 */ #define GPIO_PUPDR_PUPD10 GPIO_PUPDR_PUPD10_Msk #define GPIO_PUPDR_PUPD10_0 (0x1U << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00100000 */ #define GPIO_PUPDR_PUPD10_1 (0x2U << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00200000 */ #define GPIO_PUPDR_PUPD11_Pos (22U) #define GPIO_PUPDR_PUPD11_Msk (0x3U << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00C00000 */ #define GPIO_PUPDR_PUPD11 GPIO_PUPDR_PUPD11_Msk #define GPIO_PUPDR_PUPD11_0 (0x1U << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00400000 */ #define GPIO_PUPDR_PUPD11_1 (0x2U << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00800000 */ #define GPIO_PUPDR_PUPD12_Pos (24U) #define GPIO_PUPDR_PUPD12_Msk (0x3U << GPIO_PUPDR_PUPD12_Pos) /*!< 0x03000000 */ #define GPIO_PUPDR_PUPD12 GPIO_PUPDR_PUPD12_Msk #define GPIO_PUPDR_PUPD12_0 (0x1U << GPIO_PUPDR_PUPD12_Pos) /*!< 0x01000000 */ #define GPIO_PUPDR_PUPD12_1 (0x2U << GPIO_PUPDR_PUPD12_Pos) /*!< 0x02000000 */ #define GPIO_PUPDR_PUPD13_Pos (26U) #define GPIO_PUPDR_PUPD13_Msk (0x3U << GPIO_PUPDR_PUPD13_Pos) /*!< 0x0C000000 */ #define GPIO_PUPDR_PUPD13 GPIO_PUPDR_PUPD13_Msk #define GPIO_PUPDR_PUPD13_0 (0x1U << GPIO_PUPDR_PUPD13_Pos) /*!< 0x04000000 */ #define GPIO_PUPDR_PUPD13_1 (0x2U << GPIO_PUPDR_PUPD13_Pos) /*!< 0x08000000 */ #define GPIO_PUPDR_PUPD14_Pos (28U) #define GPIO_PUPDR_PUPD14_Msk (0x3U << GPIO_PUPDR_PUPD14_Pos) /*!< 0x30000000 */ #define GPIO_PUPDR_PUPD14 GPIO_PUPDR_PUPD14_Msk #define GPIO_PUPDR_PUPD14_0 (0x1U << GPIO_PUPDR_PUPD14_Pos) /*!< 0x10000000 */ #define GPIO_PUPDR_PUPD14_1 (0x2U << GPIO_PUPDR_PUPD14_Pos) /*!< 0x20000000 */ #define GPIO_PUPDR_PUPD15_Pos (30U) #define GPIO_PUPDR_PUPD15_Msk (0x3U << GPIO_PUPDR_PUPD15_Pos) /*!< 0xC0000000 */ #define GPIO_PUPDR_PUPD15 GPIO_PUPDR_PUPD15_Msk #define GPIO_PUPDR_PUPD15_0 (0x1U << GPIO_PUPDR_PUPD15_Pos) /*!< 0x40000000 */ #define GPIO_PUPDR_PUPD15_1 (0x2U << GPIO_PUPDR_PUPD15_Pos) /*!< 0x80000000 */ /* Legacy defines */ #define GPIO_PUPDR_PUPDR0 GPIO_PUPDR_PUPD0 #define GPIO_PUPDR_PUPDR0_0 GPIO_PUPDR_PUPD0_0 #define GPIO_PUPDR_PUPDR0_1 GPIO_PUPDR_PUPD0_1 #define GPIO_PUPDR_PUPDR1 GPIO_PUPDR_PUPD1 #define GPIO_PUPDR_PUPDR1_0 GPIO_PUPDR_PUPD1_0 #define GPIO_PUPDR_PUPDR1_1 GPIO_PUPDR_PUPD1_1 #define GPIO_PUPDR_PUPDR2 GPIO_PUPDR_PUPD2 #define GPIO_PUPDR_PUPDR2_0 GPIO_PUPDR_PUPD2_0 #define GPIO_PUPDR_PUPDR2_1 GPIO_PUPDR_PUPD2_1 #define GPIO_PUPDR_PUPDR3 GPIO_PUPDR_PUPD3 #define GPIO_PUPDR_PUPDR3_0 GPIO_PUPDR_PUPD3_0 #define GPIO_PUPDR_PUPDR3_1 GPIO_PUPDR_PUPD3_1 #define GPIO_PUPDR_PUPDR4 GPIO_PUPDR_PUPD4 #define GPIO_PUPDR_PUPDR4_0 GPIO_PUPDR_PUPD4_0 #define GPIO_PUPDR_PUPDR4_1 GPIO_PUPDR_PUPD4_1 #define GPIO_PUPDR_PUPDR5 GPIO_PUPDR_PUPD5 #define GPIO_PUPDR_PUPDR5_0 GPIO_PUPDR_PUPD5_0 #define GPIO_PUPDR_PUPDR5_1 GPIO_PUPDR_PUPD5_1 #define GPIO_PUPDR_PUPDR6 GPIO_PUPDR_PUPD6 #define GPIO_PUPDR_PUPDR6_0 GPIO_PUPDR_PUPD6_0 #define GPIO_PUPDR_PUPDR6_1 GPIO_PUPDR_PUPD6_1 #define GPIO_PUPDR_PUPDR7 GPIO_PUPDR_PUPD7 #define GPIO_PUPDR_PUPDR7_0 GPIO_PUPDR_PUPD7_0 #define GPIO_PUPDR_PUPDR7_1 GPIO_PUPDR_PUPD7_1 #define GPIO_PUPDR_PUPDR8 GPIO_PUPDR_PUPD8 #define GPIO_PUPDR_PUPDR8_0 GPIO_PUPDR_PUPD8_0 #define GPIO_PUPDR_PUPDR8_1 GPIO_PUPDR_PUPD8_1 #define GPIO_PUPDR_PUPDR9 GPIO_PUPDR_PUPD9 #define GPIO_PUPDR_PUPDR9_0 GPIO_PUPDR_PUPD9_0 #define GPIO_PUPDR_PUPDR9_1 GPIO_PUPDR_PUPD9_1 #define GPIO_PUPDR_PUPDR10 GPIO_PUPDR_PUPD10 #define GPIO_PUPDR_PUPDR10_0 GPIO_PUPDR_PUPD10_0 #define GPIO_PUPDR_PUPDR10_1 GPIO_PUPDR_PUPD10_1 #define GPIO_PUPDR_PUPDR11 GPIO_PUPDR_PUPD11 #define GPIO_PUPDR_PUPDR11_0 GPIO_PUPDR_PUPD11_0 #define GPIO_PUPDR_PUPDR11_1 GPIO_PUPDR_PUPD11_1 #define GPIO_PUPDR_PUPDR12 GPIO_PUPDR_PUPD12 #define GPIO_PUPDR_PUPDR12_0 GPIO_PUPDR_PUPD12_0 #define GPIO_PUPDR_PUPDR12_1 GPIO_PUPDR_PUPD12_1 #define GPIO_PUPDR_PUPDR13 GPIO_PUPDR_PUPD13 #define GPIO_PUPDR_PUPDR13_0 GPIO_PUPDR_PUPD13_0 #define GPIO_PUPDR_PUPDR13_1 GPIO_PUPDR_PUPD13_1 #define GPIO_PUPDR_PUPDR14 GPIO_PUPDR_PUPD14 #define GPIO_PUPDR_PUPDR14_0 GPIO_PUPDR_PUPD14_0 #define GPIO_PUPDR_PUPDR14_1 GPIO_PUPDR_PUPD14_1 #define GPIO_PUPDR_PUPDR15 GPIO_PUPDR_PUPD15 #define GPIO_PUPDR_PUPDR15_0 GPIO_PUPDR_PUPD15_0 #define GPIO_PUPDR_PUPDR15_1 GPIO_PUPDR_PUPD15_1 /****************** Bits definition for GPIO_IDR register *******************/ #define GPIO_IDR_ID0_Pos (0U) #define GPIO_IDR_ID0_Msk (0x1U << GPIO_IDR_ID0_Pos) /*!< 0x00000001 */ #define GPIO_IDR_ID0 GPIO_IDR_ID0_Msk #define GPIO_IDR_ID1_Pos (1U) #define GPIO_IDR_ID1_Msk (0x1U << GPIO_IDR_ID1_Pos) /*!< 0x00000002 */ #define GPIO_IDR_ID1 GPIO_IDR_ID1_Msk #define GPIO_IDR_ID2_Pos (2U) #define GPIO_IDR_ID2_Msk (0x1U << GPIO_IDR_ID2_Pos) /*!< 0x00000004 */ #define GPIO_IDR_ID2 GPIO_IDR_ID2_Msk #define GPIO_IDR_ID3_Pos (3U) #define GPIO_IDR_ID3_Msk (0x1U << GPIO_IDR_ID3_Pos) /*!< 0x00000008 */ #define GPIO_IDR_ID3 GPIO_IDR_ID3_Msk #define GPIO_IDR_ID4_Pos (4U) #define GPIO_IDR_ID4_Msk (0x1U << GPIO_IDR_ID4_Pos) /*!< 0x00000010 */ #define GPIO_IDR_ID4 GPIO_IDR_ID4_Msk #define GPIO_IDR_ID5_Pos (5U) #define GPIO_IDR_ID5_Msk (0x1U << GPIO_IDR_ID5_Pos) /*!< 0x00000020 */ #define GPIO_IDR_ID5 GPIO_IDR_ID5_Msk #define GPIO_IDR_ID6_Pos (6U) #define GPIO_IDR_ID6_Msk (0x1U << GPIO_IDR_ID6_Pos) /*!< 0x00000040 */ #define GPIO_IDR_ID6 GPIO_IDR_ID6_Msk #define GPIO_IDR_ID7_Pos (7U) #define GPIO_IDR_ID7_Msk (0x1U << GPIO_IDR_ID7_Pos) /*!< 0x00000080 */ #define GPIO_IDR_ID7 GPIO_IDR_ID7_Msk #define GPIO_IDR_ID8_Pos (8U) #define GPIO_IDR_ID8_Msk (0x1U << GPIO_IDR_ID8_Pos) /*!< 0x00000100 */ #define GPIO_IDR_ID8 GPIO_IDR_ID8_Msk #define GPIO_IDR_ID9_Pos (9U) #define GPIO_IDR_ID9_Msk (0x1U << GPIO_IDR_ID9_Pos) /*!< 0x00000200 */ #define GPIO_IDR_ID9 GPIO_IDR_ID9_Msk #define GPIO_IDR_ID10_Pos (10U) #define GPIO_IDR_ID10_Msk (0x1U << GPIO_IDR_ID10_Pos) /*!< 0x00000400 */ #define GPIO_IDR_ID10 GPIO_IDR_ID10_Msk #define GPIO_IDR_ID11_Pos (11U) #define GPIO_IDR_ID11_Msk (0x1U << GPIO_IDR_ID11_Pos) /*!< 0x00000800 */ #define GPIO_IDR_ID11 GPIO_IDR_ID11_Msk #define GPIO_IDR_ID12_Pos (12U) #define GPIO_IDR_ID12_Msk (0x1U << GPIO_IDR_ID12_Pos) /*!< 0x00001000 */ #define GPIO_IDR_ID12 GPIO_IDR_ID12_Msk #define GPIO_IDR_ID13_Pos (13U) #define GPIO_IDR_ID13_Msk (0x1U << GPIO_IDR_ID13_Pos) /*!< 0x00002000 */ #define GPIO_IDR_ID13 GPIO_IDR_ID13_Msk #define GPIO_IDR_ID14_Pos (14U) #define GPIO_IDR_ID14_Msk (0x1U << GPIO_IDR_ID14_Pos) /*!< 0x00004000 */ #define GPIO_IDR_ID14 GPIO_IDR_ID14_Msk #define GPIO_IDR_ID15_Pos (15U) #define GPIO_IDR_ID15_Msk (0x1U << GPIO_IDR_ID15_Pos) /*!< 0x00008000 */ #define GPIO_IDR_ID15 GPIO_IDR_ID15_Msk /* Legacy defines */ #define GPIO_IDR_IDR_0 GPIO_IDR_ID0 #define GPIO_IDR_IDR_1 GPIO_IDR_ID1 #define GPIO_IDR_IDR_2 GPIO_IDR_ID2 #define GPIO_IDR_IDR_3 GPIO_IDR_ID3 #define GPIO_IDR_IDR_4 GPIO_IDR_ID4 #define GPIO_IDR_IDR_5 GPIO_IDR_ID5 #define GPIO_IDR_IDR_6 GPIO_IDR_ID6 #define GPIO_IDR_IDR_7 GPIO_IDR_ID7 #define GPIO_IDR_IDR_8 GPIO_IDR_ID8 #define GPIO_IDR_IDR_9 GPIO_IDR_ID9 #define GPIO_IDR_IDR_10 GPIO_IDR_ID10 #define GPIO_IDR_IDR_11 GPIO_IDR_ID11 #define GPIO_IDR_IDR_12 GPIO_IDR_ID12 #define GPIO_IDR_IDR_13 GPIO_IDR_ID13 #define GPIO_IDR_IDR_14 GPIO_IDR_ID14 #define GPIO_IDR_IDR_15 GPIO_IDR_ID15 /****************** Bits definition for GPIO_ODR register *******************/ #define GPIO_ODR_OD0_Pos (0U) #define GPIO_ODR_OD0_Msk (0x1U << GPIO_ODR_OD0_Pos) /*!< 0x00000001 */ #define GPIO_ODR_OD0 GPIO_ODR_OD0_Msk #define GPIO_ODR_OD1_Pos (1U) #define GPIO_ODR_OD1_Msk (0x1U << GPIO_ODR_OD1_Pos) /*!< 0x00000002 */ #define GPIO_ODR_OD1 GPIO_ODR_OD1_Msk #define GPIO_ODR_OD2_Pos (2U) #define GPIO_ODR_OD2_Msk (0x1U << GPIO_ODR_OD2_Pos) /*!< 0x00000004 */ #define GPIO_ODR_OD2 GPIO_ODR_OD2_Msk #define GPIO_ODR_OD3_Pos (3U) #define GPIO_ODR_OD3_Msk (0x1U << GPIO_ODR_OD3_Pos) /*!< 0x00000008 */ #define GPIO_ODR_OD3 GPIO_ODR_OD3_Msk #define GPIO_ODR_OD4_Pos (4U) #define GPIO_ODR_OD4_Msk (0x1U << GPIO_ODR_OD4_Pos) /*!< 0x00000010 */ #define GPIO_ODR_OD4 GPIO_ODR_OD4_Msk #define GPIO_ODR_OD5_Pos (5U) #define GPIO_ODR_OD5_Msk (0x1U << GPIO_ODR_OD5_Pos) /*!< 0x00000020 */ #define GPIO_ODR_OD5 GPIO_ODR_OD5_Msk #define GPIO_ODR_OD6_Pos (6U) #define GPIO_ODR_OD6_Msk (0x1U << GPIO_ODR_OD6_Pos) /*!< 0x00000040 */ #define GPIO_ODR_OD6 GPIO_ODR_OD6_Msk #define GPIO_ODR_OD7_Pos (7U) #define GPIO_ODR_OD7_Msk (0x1U << GPIO_ODR_OD7_Pos) /*!< 0x00000080 */ #define GPIO_ODR_OD7 GPIO_ODR_OD7_Msk #define GPIO_ODR_OD8_Pos (8U) #define GPIO_ODR_OD8_Msk (0x1U << GPIO_ODR_OD8_Pos) /*!< 0x00000100 */ #define GPIO_ODR_OD8 GPIO_ODR_OD8_Msk #define GPIO_ODR_OD9_Pos (9U) #define GPIO_ODR_OD9_Msk (0x1U << GPIO_ODR_OD9_Pos) /*!< 0x00000200 */ #define GPIO_ODR_OD9 GPIO_ODR_OD9_Msk #define GPIO_ODR_OD10_Pos (10U) #define GPIO_ODR_OD10_Msk (0x1U << GPIO_ODR_OD10_Pos) /*!< 0x00000400 */ #define GPIO_ODR_OD10 GPIO_ODR_OD10_Msk #define GPIO_ODR_OD11_Pos (11U) #define GPIO_ODR_OD11_Msk (0x1U << GPIO_ODR_OD11_Pos) /*!< 0x00000800 */ #define GPIO_ODR_OD11 GPIO_ODR_OD11_Msk #define GPIO_ODR_OD12_Pos (12U) #define GPIO_ODR_OD12_Msk (0x1U << GPIO_ODR_OD12_Pos) /*!< 0x00001000 */ #define GPIO_ODR_OD12 GPIO_ODR_OD12_Msk #define GPIO_ODR_OD13_Pos (13U) #define GPIO_ODR_OD13_Msk (0x1U << GPIO_ODR_OD13_Pos) /*!< 0x00002000 */ #define GPIO_ODR_OD13 GPIO_ODR_OD13_Msk #define GPIO_ODR_OD14_Pos (14U) #define GPIO_ODR_OD14_Msk (0x1U << GPIO_ODR_OD14_Pos) /*!< 0x00004000 */ #define GPIO_ODR_OD14 GPIO_ODR_OD14_Msk #define GPIO_ODR_OD15_Pos (15U) #define GPIO_ODR_OD15_Msk (0x1U << GPIO_ODR_OD15_Pos) /*!< 0x00008000 */ #define GPIO_ODR_OD15 GPIO_ODR_OD15_Msk /* Legacy defines */ #define GPIO_ODR_ODR_0 GPIO_ODR_OD0 #define GPIO_ODR_ODR_1 GPIO_ODR_OD1 #define GPIO_ODR_ODR_2 GPIO_ODR_OD2 #define GPIO_ODR_ODR_3 GPIO_ODR_OD3 #define GPIO_ODR_ODR_4 GPIO_ODR_OD4 #define GPIO_ODR_ODR_5 GPIO_ODR_OD5 #define GPIO_ODR_ODR_6 GPIO_ODR_OD6 #define GPIO_ODR_ODR_7 GPIO_ODR_OD7 #define GPIO_ODR_ODR_8 GPIO_ODR_OD8 #define GPIO_ODR_ODR_9 GPIO_ODR_OD9 #define GPIO_ODR_ODR_10 GPIO_ODR_OD10 #define GPIO_ODR_ODR_11 GPIO_ODR_OD11 #define GPIO_ODR_ODR_12 GPIO_ODR_OD12 #define GPIO_ODR_ODR_13 GPIO_ODR_OD13 #define GPIO_ODR_ODR_14 GPIO_ODR_OD14 #define GPIO_ODR_ODR_15 GPIO_ODR_OD15 /****************** Bits definition for GPIO_BSRR register ******************/ #define GPIO_BSRR_BS0_Pos (0U) #define GPIO_BSRR_BS0_Msk (0x1U << GPIO_BSRR_BS0_Pos) /*!< 0x00000001 */ #define GPIO_BSRR_BS0 GPIO_BSRR_BS0_Msk #define GPIO_BSRR_BS1_Pos (1U) #define GPIO_BSRR_BS1_Msk (0x1U << GPIO_BSRR_BS1_Pos) /*!< 0x00000002 */ #define GPIO_BSRR_BS1 GPIO_BSRR_BS1_Msk #define GPIO_BSRR_BS2_Pos (2U) #define GPIO_BSRR_BS2_Msk (0x1U << GPIO_BSRR_BS2_Pos) /*!< 0x00000004 */ #define GPIO_BSRR_BS2 GPIO_BSRR_BS2_Msk #define GPIO_BSRR_BS3_Pos (3U) #define GPIO_BSRR_BS3_Msk (0x1U << GPIO_BSRR_BS3_Pos) /*!< 0x00000008 */ #define GPIO_BSRR_BS3 GPIO_BSRR_BS3_Msk #define GPIO_BSRR_BS4_Pos (4U) #define GPIO_BSRR_BS4_Msk (0x1U << GPIO_BSRR_BS4_Pos) /*!< 0x00000010 */ #define GPIO_BSRR_BS4 GPIO_BSRR_BS4_Msk #define GPIO_BSRR_BS5_Pos (5U) #define GPIO_BSRR_BS5_Msk (0x1U << GPIO_BSRR_BS5_Pos) /*!< 0x00000020 */ #define GPIO_BSRR_BS5 GPIO_BSRR_BS5_Msk #define GPIO_BSRR_BS6_Pos (6U) #define GPIO_BSRR_BS6_Msk (0x1U << GPIO_BSRR_BS6_Pos) /*!< 0x00000040 */ #define GPIO_BSRR_BS6 GPIO_BSRR_BS6_Msk #define GPIO_BSRR_BS7_Pos (7U) #define GPIO_BSRR_BS7_Msk (0x1U << GPIO_BSRR_BS7_Pos) /*!< 0x00000080 */ #define GPIO_BSRR_BS7 GPIO_BSRR_BS7_Msk #define GPIO_BSRR_BS8_Pos (8U) #define GPIO_BSRR_BS8_Msk (0x1U << GPIO_BSRR_BS8_Pos) /*!< 0x00000100 */ #define GPIO_BSRR_BS8 GPIO_BSRR_BS8_Msk #define GPIO_BSRR_BS9_Pos (9U) #define GPIO_BSRR_BS9_Msk (0x1U << GPIO_BSRR_BS9_Pos) /*!< 0x00000200 */ #define GPIO_BSRR_BS9 GPIO_BSRR_BS9_Msk #define GPIO_BSRR_BS10_Pos (10U) #define GPIO_BSRR_BS10_Msk (0x1U << GPIO_BSRR_BS10_Pos) /*!< 0x00000400 */ #define GPIO_BSRR_BS10 GPIO_BSRR_BS10_Msk #define GPIO_BSRR_BS11_Pos (11U) #define GPIO_BSRR_BS11_Msk (0x1U << GPIO_BSRR_BS11_Pos) /*!< 0x00000800 */ #define GPIO_BSRR_BS11 GPIO_BSRR_BS11_Msk #define GPIO_BSRR_BS12_Pos (12U) #define GPIO_BSRR_BS12_Msk (0x1U << GPIO_BSRR_BS12_Pos) /*!< 0x00001000 */ #define GPIO_BSRR_BS12 GPIO_BSRR_BS12_Msk #define GPIO_BSRR_BS13_Pos (13U) #define GPIO_BSRR_BS13_Msk (0x1U << GPIO_BSRR_BS13_Pos) /*!< 0x00002000 */ #define GPIO_BSRR_BS13 GPIO_BSRR_BS13_Msk #define GPIO_BSRR_BS14_Pos (14U) #define GPIO_BSRR_BS14_Msk (0x1U << GPIO_BSRR_BS14_Pos) /*!< 0x00004000 */ #define GPIO_BSRR_BS14 GPIO_BSRR_BS14_Msk #define GPIO_BSRR_BS15_Pos (15U) #define GPIO_BSRR_BS15_Msk (0x1U << GPIO_BSRR_BS15_Pos) /*!< 0x00008000 */ #define GPIO_BSRR_BS15 GPIO_BSRR_BS15_Msk #define GPIO_BSRR_BR0_Pos (16U) #define GPIO_BSRR_BR0_Msk (0x1U << GPIO_BSRR_BR0_Pos) /*!< 0x00010000 */ #define GPIO_BSRR_BR0 GPIO_BSRR_BR0_Msk #define GPIO_BSRR_BR1_Pos (17U) #define GPIO_BSRR_BR1_Msk (0x1U << GPIO_BSRR_BR1_Pos) /*!< 0x00020000 */ #define GPIO_BSRR_BR1 GPIO_BSRR_BR1_Msk #define GPIO_BSRR_BR2_Pos (18U) #define GPIO_BSRR_BR2_Msk (0x1U << GPIO_BSRR_BR2_Pos) /*!< 0x00040000 */ #define GPIO_BSRR_BR2 GPIO_BSRR_BR2_Msk #define GPIO_BSRR_BR3_Pos (19U) #define GPIO_BSRR_BR3_Msk (0x1U << GPIO_BSRR_BR3_Pos) /*!< 0x00080000 */ #define GPIO_BSRR_BR3 GPIO_BSRR_BR3_Msk #define GPIO_BSRR_BR4_Pos (20U) #define GPIO_BSRR_BR4_Msk (0x1U << GPIO_BSRR_BR4_Pos) /*!< 0x00100000 */ #define GPIO_BSRR_BR4 GPIO_BSRR_BR4_Msk #define GPIO_BSRR_BR5_Pos (21U) #define GPIO_BSRR_BR5_Msk (0x1U << GPIO_BSRR_BR5_Pos) /*!< 0x00200000 */ #define GPIO_BSRR_BR5 GPIO_BSRR_BR5_Msk #define GPIO_BSRR_BR6_Pos (22U) #define GPIO_BSRR_BR6_Msk (0x1U << GPIO_BSRR_BR6_Pos) /*!< 0x00400000 */ #define GPIO_BSRR_BR6 GPIO_BSRR_BR6_Msk #define GPIO_BSRR_BR7_Pos (23U) #define GPIO_BSRR_BR7_Msk (0x1U << GPIO_BSRR_BR7_Pos) /*!< 0x00800000 */ #define GPIO_BSRR_BR7 GPIO_BSRR_BR7_Msk #define GPIO_BSRR_BR8_Pos (24U) #define GPIO_BSRR_BR8_Msk (0x1U << GPIO_BSRR_BR8_Pos) /*!< 0x01000000 */ #define GPIO_BSRR_BR8 GPIO_BSRR_BR8_Msk #define GPIO_BSRR_BR9_Pos (25U) #define GPIO_BSRR_BR9_Msk (0x1U << GPIO_BSRR_BR9_Pos) /*!< 0x02000000 */ #define GPIO_BSRR_BR9 GPIO_BSRR_BR9_Msk #define GPIO_BSRR_BR10_Pos (26U) #define GPIO_BSRR_BR10_Msk (0x1U << GPIO_BSRR_BR10_Pos) /*!< 0x04000000 */ #define GPIO_BSRR_BR10 GPIO_BSRR_BR10_Msk #define GPIO_BSRR_BR11_Pos (27U) #define GPIO_BSRR_BR11_Msk (0x1U << GPIO_BSRR_BR11_Pos) /*!< 0x08000000 */ #define GPIO_BSRR_BR11 GPIO_BSRR_BR11_Msk #define GPIO_BSRR_BR12_Pos (28U) #define GPIO_BSRR_BR12_Msk (0x1U << GPIO_BSRR_BR12_Pos) /*!< 0x10000000 */ #define GPIO_BSRR_BR12 GPIO_BSRR_BR12_Msk #define GPIO_BSRR_BR13_Pos (29U) #define GPIO_BSRR_BR13_Msk (0x1U << GPIO_BSRR_BR13_Pos) /*!< 0x20000000 */ #define GPIO_BSRR_BR13 GPIO_BSRR_BR13_Msk #define GPIO_BSRR_BR14_Pos (30U) #define GPIO_BSRR_BR14_Msk (0x1U << GPIO_BSRR_BR14_Pos) /*!< 0x40000000 */ #define GPIO_BSRR_BR14 GPIO_BSRR_BR14_Msk #define GPIO_BSRR_BR15_Pos (31U) #define GPIO_BSRR_BR15_Msk (0x1U << GPIO_BSRR_BR15_Pos) /*!< 0x80000000 */ #define GPIO_BSRR_BR15 GPIO_BSRR_BR15_Msk /* Legacy defines */ #define GPIO_BSRR_BS_0 GPIO_BSRR_BS0 #define GPIO_BSRR_BS_1 GPIO_BSRR_BS1 #define GPIO_BSRR_BS_2 GPIO_BSRR_BS2 #define GPIO_BSRR_BS_3 GPIO_BSRR_BS3 #define GPIO_BSRR_BS_4 GPIO_BSRR_BS4 #define GPIO_BSRR_BS_5 GPIO_BSRR_BS5 #define GPIO_BSRR_BS_6 GPIO_BSRR_BS6 #define GPIO_BSRR_BS_7 GPIO_BSRR_BS7 #define GPIO_BSRR_BS_8 GPIO_BSRR_BS8 #define GPIO_BSRR_BS_9 GPIO_BSRR_BS9 #define GPIO_BSRR_BS_10 GPIO_BSRR_BS10 #define GPIO_BSRR_BS_11 GPIO_BSRR_BS11 #define GPIO_BSRR_BS_12 GPIO_BSRR_BS12 #define GPIO_BSRR_BS_13 GPIO_BSRR_BS13 #define GPIO_BSRR_BS_14 GPIO_BSRR_BS14 #define GPIO_BSRR_BS_15 GPIO_BSRR_BS15 #define GPIO_BSRR_BR_0 GPIO_BSRR_BR0 #define GPIO_BSRR_BR_1 GPIO_BSRR_BR1 #define GPIO_BSRR_BR_2 GPIO_BSRR_BR2 #define GPIO_BSRR_BR_3 GPIO_BSRR_BR3 #define GPIO_BSRR_BR_4 GPIO_BSRR_BR4 #define GPIO_BSRR_BR_5 GPIO_BSRR_BR5 #define GPIO_BSRR_BR_6 GPIO_BSRR_BR6 #define GPIO_BSRR_BR_7 GPIO_BSRR_BR7 #define GPIO_BSRR_BR_8 GPIO_BSRR_BR8 #define GPIO_BSRR_BR_9 GPIO_BSRR_BR9 #define GPIO_BSRR_BR_10 GPIO_BSRR_BR10 #define GPIO_BSRR_BR_11 GPIO_BSRR_BR11 #define GPIO_BSRR_BR_12 GPIO_BSRR_BR12 #define GPIO_BSRR_BR_13 GPIO_BSRR_BR13 #define GPIO_BSRR_BR_14 GPIO_BSRR_BR14 #define GPIO_BSRR_BR_15 GPIO_BSRR_BR15 /****************** Bit definition for GPIO_LCKR register *********************/ #define GPIO_LCKR_LCK0_Pos (0U) #define GPIO_LCKR_LCK0_Msk (0x1U << GPIO_LCKR_LCK0_Pos) /*!< 0x00000001 */ #define GPIO_LCKR_LCK0 GPIO_LCKR_LCK0_Msk #define GPIO_LCKR_LCK1_Pos (1U) #define GPIO_LCKR_LCK1_Msk (0x1U << GPIO_LCKR_LCK1_Pos) /*!< 0x00000002 */ #define GPIO_LCKR_LCK1 GPIO_LCKR_LCK1_Msk #define GPIO_LCKR_LCK2_Pos (2U) #define GPIO_LCKR_LCK2_Msk (0x1U << GPIO_LCKR_LCK2_Pos) /*!< 0x00000004 */ #define GPIO_LCKR_LCK2 GPIO_LCKR_LCK2_Msk #define GPIO_LCKR_LCK3_Pos (3U) #define GPIO_LCKR_LCK3_Msk (0x1U << GPIO_LCKR_LCK3_Pos) /*!< 0x00000008 */ #define GPIO_LCKR_LCK3 GPIO_LCKR_LCK3_Msk #define GPIO_LCKR_LCK4_Pos (4U) #define GPIO_LCKR_LCK4_Msk (0x1U << GPIO_LCKR_LCK4_Pos) /*!< 0x00000010 */ #define GPIO_LCKR_LCK4 GPIO_LCKR_LCK4_Msk #define GPIO_LCKR_LCK5_Pos (5U) #define GPIO_LCKR_LCK5_Msk (0x1U << GPIO_LCKR_LCK5_Pos) /*!< 0x00000020 */ #define GPIO_LCKR_LCK5 GPIO_LCKR_LCK5_Msk #define GPIO_LCKR_LCK6_Pos (6U) #define GPIO_LCKR_LCK6_Msk (0x1U << GPIO_LCKR_LCK6_Pos) /*!< 0x00000040 */ #define GPIO_LCKR_LCK6 GPIO_LCKR_LCK6_Msk #define GPIO_LCKR_LCK7_Pos (7U) #define GPIO_LCKR_LCK7_Msk (0x1U << GPIO_LCKR_LCK7_Pos) /*!< 0x00000080 */ #define GPIO_LCKR_LCK7 GPIO_LCKR_LCK7_Msk #define GPIO_LCKR_LCK8_Pos (8U) #define GPIO_LCKR_LCK8_Msk (0x1U << GPIO_LCKR_LCK8_Pos) /*!< 0x00000100 */ #define GPIO_LCKR_LCK8 GPIO_LCKR_LCK8_Msk #define GPIO_LCKR_LCK9_Pos (9U) #define GPIO_LCKR_LCK9_Msk (0x1U << GPIO_LCKR_LCK9_Pos) /*!< 0x00000200 */ #define GPIO_LCKR_LCK9 GPIO_LCKR_LCK9_Msk #define GPIO_LCKR_LCK10_Pos (10U) #define GPIO_LCKR_LCK10_Msk (0x1U << GPIO_LCKR_LCK10_Pos) /*!< 0x00000400 */ #define GPIO_LCKR_LCK10 GPIO_LCKR_LCK10_Msk #define GPIO_LCKR_LCK11_Pos (11U) #define GPIO_LCKR_LCK11_Msk (0x1U << GPIO_LCKR_LCK11_Pos) /*!< 0x00000800 */ #define GPIO_LCKR_LCK11 GPIO_LCKR_LCK11_Msk #define GPIO_LCKR_LCK12_Pos (12U) #define GPIO_LCKR_LCK12_Msk (0x1U << GPIO_LCKR_LCK12_Pos) /*!< 0x00001000 */ #define GPIO_LCKR_LCK12 GPIO_LCKR_LCK12_Msk #define GPIO_LCKR_LCK13_Pos (13U) #define GPIO_LCKR_LCK13_Msk (0x1U << GPIO_LCKR_LCK13_Pos) /*!< 0x00002000 */ #define GPIO_LCKR_LCK13 GPIO_LCKR_LCK13_Msk #define GPIO_LCKR_LCK14_Pos (14U) #define GPIO_LCKR_LCK14_Msk (0x1U << GPIO_LCKR_LCK14_Pos) /*!< 0x00004000 */ #define GPIO_LCKR_LCK14 GPIO_LCKR_LCK14_Msk #define GPIO_LCKR_LCK15_Pos (15U) #define GPIO_LCKR_LCK15_Msk (0x1U << GPIO_LCKR_LCK15_Pos) /*!< 0x00008000 */ #define GPIO_LCKR_LCK15 GPIO_LCKR_LCK15_Msk #define GPIO_LCKR_LCKK_Pos (16U) #define GPIO_LCKR_LCKK_Msk (0x1U << GPIO_LCKR_LCKK_Pos) /*!< 0x00010000 */ #define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk /****************** Bit definition for GPIO_AFRL register *********************/ #define GPIO_AFRL_AFSEL0_Pos (0U) #define GPIO_AFRL_AFSEL0_Msk (0xFU << GPIO_AFRL_AFSEL0_Pos) /*!< 0x0000000F */ #define GPIO_AFRL_AFSEL0 GPIO_AFRL_AFSEL0_Msk #define GPIO_AFRL_AFSEL0_0 (0x1U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000001 */ #define GPIO_AFRL_AFSEL0_1 (0x2U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000002 */ #define GPIO_AFRL_AFSEL0_2 (0x4U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000004 */ #define GPIO_AFRL_AFSEL0_3 (0x8U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000008 */ #define GPIO_AFRL_AFSEL1_Pos (4U) #define GPIO_AFRL_AFSEL1_Msk (0xFU << GPIO_AFRL_AFSEL1_Pos) /*!< 0x000000F0 */ #define GPIO_AFRL_AFSEL1 GPIO_AFRL_AFSEL1_Msk #define GPIO_AFRL_AFSEL1_0 (0x1U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000010 */ #define GPIO_AFRL_AFSEL1_1 (0x2U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000020 */ #define GPIO_AFRL_AFSEL1_2 (0x4U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000040 */ #define GPIO_AFRL_AFSEL1_3 (0x8U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000080 */ #define GPIO_AFRL_AFSEL2_Pos (8U) #define GPIO_AFRL_AFSEL2_Msk (0xFU << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000F00 */ #define GPIO_AFRL_AFSEL2 GPIO_AFRL_AFSEL2_Msk #define GPIO_AFRL_AFSEL2_0 (0x1U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000100 */ #define GPIO_AFRL_AFSEL2_1 (0x2U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000200 */ #define GPIO_AFRL_AFSEL2_2 (0x4U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000400 */ #define GPIO_AFRL_AFSEL2_3 (0x8U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000800 */ #define GPIO_AFRL_AFSEL3_Pos (12U) #define GPIO_AFRL_AFSEL3_Msk (0xFU << GPIO_AFRL_AFSEL3_Pos) /*!< 0x0000F000 */ #define GPIO_AFRL_AFSEL3 GPIO_AFRL_AFSEL3_Msk #define GPIO_AFRL_AFSEL3_0 (0x1U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00001000 */ #define GPIO_AFRL_AFSEL3_1 (0x2U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00002000 */ #define GPIO_AFRL_AFSEL3_2 (0x4U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00004000 */ #define GPIO_AFRL_AFSEL3_3 (0x8U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00008000 */ #define GPIO_AFRL_AFSEL4_Pos (16U) #define GPIO_AFRL_AFSEL4_Msk (0xFU << GPIO_AFRL_AFSEL4_Pos) /*!< 0x000F0000 */ #define GPIO_AFRL_AFSEL4 GPIO_AFRL_AFSEL4_Msk #define GPIO_AFRL_AFSEL4_0 (0x1U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00010000 */ #define GPIO_AFRL_AFSEL4_1 (0x2U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00020000 */ #define GPIO_AFRL_AFSEL4_2 (0x4U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00040000 */ #define GPIO_AFRL_AFSEL4_3 (0x8U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00080000 */ #define GPIO_AFRL_AFSEL5_Pos (20U) #define GPIO_AFRL_AFSEL5_Msk (0xFU << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00F00000 */ #define GPIO_AFRL_AFSEL5 GPIO_AFRL_AFSEL5_Msk #define GPIO_AFRL_AFSEL5_0 (0x1U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00100000 */ #define GPIO_AFRL_AFSEL5_1 (0x2U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00200000 */ #define GPIO_AFRL_AFSEL5_2 (0x4U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00400000 */ #define GPIO_AFRL_AFSEL5_3 (0x8U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00800000 */ #define GPIO_AFRL_AFSEL6_Pos (24U) #define GPIO_AFRL_AFSEL6_Msk (0xFU << GPIO_AFRL_AFSEL6_Pos) /*!< 0x0F000000 */ #define GPIO_AFRL_AFSEL6 GPIO_AFRL_AFSEL6_Msk #define GPIO_AFRL_AFSEL6_0 (0x1U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x01000000 */ #define GPIO_AFRL_AFSEL6_1 (0x2U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x02000000 */ #define GPIO_AFRL_AFSEL6_2 (0x4U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x04000000 */ #define GPIO_AFRL_AFSEL6_3 (0x8U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x08000000 */ #define GPIO_AFRL_AFSEL7_Pos (28U) #define GPIO_AFRL_AFSEL7_Msk (0xFU << GPIO_AFRL_AFSEL7_Pos) /*!< 0xF0000000 */ #define GPIO_AFRL_AFSEL7 GPIO_AFRL_AFSEL7_Msk #define GPIO_AFRL_AFSEL7_0 (0x1U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x10000000 */ #define GPIO_AFRL_AFSEL7_1 (0x2U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x20000000 */ #define GPIO_AFRL_AFSEL7_2 (0x4U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x40000000 */ #define GPIO_AFRL_AFSEL7_3 (0x8U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x80000000 */ /* Legacy defines */ #define GPIO_AFRL_AFRL0 GPIO_AFRL_AFSEL0 #define GPIO_AFRL_AFRL0_0 GPIO_AFRL_AFSEL0_0 #define GPIO_AFRL_AFRL0_1 GPIO_AFRL_AFSEL0_1 #define GPIO_AFRL_AFRL0_2 GPIO_AFRL_AFSEL0_2 #define GPIO_AFRL_AFRL0_3 GPIO_AFRL_AFSEL0_3 #define GPIO_AFRL_AFRL1 GPIO_AFRL_AFSEL1 #define GPIO_AFRL_AFRL1_0 GPIO_AFRL_AFSEL1_0 #define GPIO_AFRL_AFRL1_1 GPIO_AFRL_AFSEL1_1 #define GPIO_AFRL_AFRL1_2 GPIO_AFRL_AFSEL1_2 #define GPIO_AFRL_AFRL1_3 GPIO_AFRL_AFSEL1_3 #define GPIO_AFRL_AFRL2 GPIO_AFRL_AFSEL2 #define GPIO_AFRL_AFRL2_0 GPIO_AFRL_AFSEL2_0 #define GPIO_AFRL_AFRL2_1 GPIO_AFRL_AFSEL2_1 #define GPIO_AFRL_AFRL2_2 GPIO_AFRL_AFSEL2_2 #define GPIO_AFRL_AFRL2_3 GPIO_AFRL_AFSEL2_3 #define GPIO_AFRL_AFRL3 GPIO_AFRL_AFSEL3 #define GPIO_AFRL_AFRL3_0 GPIO_AFRL_AFSEL3_0 #define GPIO_AFRL_AFRL3_1 GPIO_AFRL_AFSEL3_1 #define GPIO_AFRL_AFRL3_2 GPIO_AFRL_AFSEL3_2 #define GPIO_AFRL_AFRL3_3 GPIO_AFRL_AFSEL3_3 #define GPIO_AFRL_AFRL4 GPIO_AFRL_AFSEL4 #define GPIO_AFRL_AFRL4_0 GPIO_AFRL_AFSEL4_0 #define GPIO_AFRL_AFRL4_1 GPIO_AFRL_AFSEL4_1 #define GPIO_AFRL_AFRL4_2 GPIO_AFRL_AFSEL4_2 #define GPIO_AFRL_AFRL4_3 GPIO_AFRL_AFSEL4_3 #define GPIO_AFRL_AFRL5 GPIO_AFRL_AFSEL5 #define GPIO_AFRL_AFRL5_0 GPIO_AFRL_AFSEL5_0 #define GPIO_AFRL_AFRL5_1 GPIO_AFRL_AFSEL5_1 #define GPIO_AFRL_AFRL5_2 GPIO_AFRL_AFSEL5_2 #define GPIO_AFRL_AFRL5_3 GPIO_AFRL_AFSEL5_3 #define GPIO_AFRL_AFRL6 GPIO_AFRL_AFSEL6 #define GPIO_AFRL_AFRL6_0 GPIO_AFRL_AFSEL6_0 #define GPIO_AFRL_AFRL6_1 GPIO_AFRL_AFSEL6_1 #define GPIO_AFRL_AFRL6_2 GPIO_AFRL_AFSEL6_2 #define GPIO_AFRL_AFRL6_3 GPIO_AFRL_AFSEL6_3 #define GPIO_AFRL_AFRL7 GPIO_AFRL_AFSEL7 #define GPIO_AFRL_AFRL7_0 GPIO_AFRL_AFSEL7_0 #define GPIO_AFRL_AFRL7_1 GPIO_AFRL_AFSEL7_1 #define GPIO_AFRL_AFRL7_2 GPIO_AFRL_AFSEL7_2 #define GPIO_AFRL_AFRL7_3 GPIO_AFRL_AFSEL7_3 /****************** Bit definition for GPIO_AFRH register *********************/ #define GPIO_AFRH_AFSEL8_Pos (0U) #define GPIO_AFRH_AFSEL8_Msk (0xFU << GPIO_AFRH_AFSEL8_Pos) /*!< 0x0000000F */ #define GPIO_AFRH_AFSEL8 GPIO_AFRH_AFSEL8_Msk #define GPIO_AFRH_AFSEL8_0 (0x1U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000001 */ #define GPIO_AFRH_AFSEL8_1 (0x2U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000002 */ #define GPIO_AFRH_AFSEL8_2 (0x4U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000004 */ #define GPIO_AFRH_AFSEL8_3 (0x8U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000008 */ #define GPIO_AFRH_AFSEL9_Pos (4U) #define GPIO_AFRH_AFSEL9_Msk (0xFU << GPIO_AFRH_AFSEL9_Pos) /*!< 0x000000F0 */ #define GPIO_AFRH_AFSEL9 GPIO_AFRH_AFSEL9_Msk #define GPIO_AFRH_AFSEL9_0 (0x1U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000010 */ #define GPIO_AFRH_AFSEL9_1 (0x2U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000020 */ #define GPIO_AFRH_AFSEL9_2 (0x4U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000040 */ #define GPIO_AFRH_AFSEL9_3 (0x8U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000080 */ #define GPIO_AFRH_AFSEL10_Pos (8U) #define GPIO_AFRH_AFSEL10_Msk (0xFU << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000F00 */ #define GPIO_AFRH_AFSEL10 GPIO_AFRH_AFSEL10_Msk #define GPIO_AFRH_AFSEL10_0 (0x1U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000100 */ #define GPIO_AFRH_AFSEL10_1 (0x2U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000200 */ #define GPIO_AFRH_AFSEL10_2 (0x4U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000400 */ #define GPIO_AFRH_AFSEL10_3 (0x8U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000800 */ #define GPIO_AFRH_AFSEL11_Pos (12U) #define GPIO_AFRH_AFSEL11_Msk (0xFU << GPIO_AFRH_AFSEL11_Pos) /*!< 0x0000F000 */ #define GPIO_AFRH_AFSEL11 GPIO_AFRH_AFSEL11_Msk #define GPIO_AFRH_AFSEL11_0 (0x1U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00001000 */ #define GPIO_AFRH_AFSEL11_1 (0x2U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00002000 */ #define GPIO_AFRH_AFSEL11_2 (0x4U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00004000 */ #define GPIO_AFRH_AFSEL11_3 (0x8U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00008000 */ #define GPIO_AFRH_AFSEL12_Pos (16U) #define GPIO_AFRH_AFSEL12_Msk (0xFU << GPIO_AFRH_AFSEL12_Pos) /*!< 0x000F0000 */ #define GPIO_AFRH_AFSEL12 GPIO_AFRH_AFSEL12_Msk #define GPIO_AFRH_AFSEL12_0 (0x1U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00010000 */ #define GPIO_AFRH_AFSEL12_1 (0x2U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00020000 */ #define GPIO_AFRH_AFSEL12_2 (0x4U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00040000 */ #define GPIO_AFRH_AFSEL12_3 (0x8U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00080000 */ #define GPIO_AFRH_AFSEL13_Pos (20U) #define GPIO_AFRH_AFSEL13_Msk (0xFU << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00F00000 */ #define GPIO_AFRH_AFSEL13 GPIO_AFRH_AFSEL13_Msk #define GPIO_AFRH_AFSEL13_0 (0x1U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00100000 */ #define GPIO_AFRH_AFSEL13_1 (0x2U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00200000 */ #define GPIO_AFRH_AFSEL13_2 (0x4U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00400000 */ #define GPIO_AFRH_AFSEL13_3 (0x8U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00800000 */ #define GPIO_AFRH_AFSEL14_Pos (24U) #define GPIO_AFRH_AFSEL14_Msk (0xFU << GPIO_AFRH_AFSEL14_Pos) /*!< 0x0F000000 */ #define GPIO_AFRH_AFSEL14 GPIO_AFRH_AFSEL14_Msk #define GPIO_AFRH_AFSEL14_0 (0x1U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x01000000 */ #define GPIO_AFRH_AFSEL14_1 (0x2U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x02000000 */ #define GPIO_AFRH_AFSEL14_2 (0x4U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x04000000 */ #define GPIO_AFRH_AFSEL14_3 (0x8U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x08000000 */ #define GPIO_AFRH_AFSEL15_Pos (28U) #define GPIO_AFRH_AFSEL15_Msk (0xFU << GPIO_AFRH_AFSEL15_Pos) /*!< 0xF0000000 */ #define GPIO_AFRH_AFSEL15 GPIO_AFRH_AFSEL15_Msk #define GPIO_AFRH_AFSEL15_0 (0x1U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x10000000 */ #define GPIO_AFRH_AFSEL15_1 (0x2U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x20000000 */ #define GPIO_AFRH_AFSEL15_2 (0x4U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x40000000 */ #define GPIO_AFRH_AFSEL15_3 (0x8U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x80000000 */ /* Legacy defines */ #define GPIO_AFRH_AFRH0 GPIO_AFRH_AFSEL8 #define GPIO_AFRH_AFRH0_0 GPIO_AFRH_AFSEL8_0 #define GPIO_AFRH_AFRH0_1 GPIO_AFRH_AFSEL8_1 #define GPIO_AFRH_AFRH0_2 GPIO_AFRH_AFSEL8_2 #define GPIO_AFRH_AFRH0_3 GPIO_AFRH_AFSEL8_3 #define GPIO_AFRH_AFRH1 GPIO_AFRH_AFSEL9 #define GPIO_AFRH_AFRH1_0 GPIO_AFRH_AFSEL9_0 #define GPIO_AFRH_AFRH1_1 GPIO_AFRH_AFSEL9_1 #define GPIO_AFRH_AFRH1_2 GPIO_AFRH_AFSEL9_2 #define GPIO_AFRH_AFRH1_3 GPIO_AFRH_AFSEL9_3 #define GPIO_AFRH_AFRH2 GPIO_AFRH_AFSEL10 #define GPIO_AFRH_AFRH2_0 GPIO_AFRH_AFSEL10_0 #define GPIO_AFRH_AFRH2_1 GPIO_AFRH_AFSEL10_1 #define GPIO_AFRH_AFRH2_2 GPIO_AFRH_AFSEL10_2 #define GPIO_AFRH_AFRH2_3 GPIO_AFRH_AFSEL10_3 #define GPIO_AFRH_AFRH3 GPIO_AFRH_AFSEL11 #define GPIO_AFRH_AFRH3_0 GPIO_AFRH_AFSEL11_0 #define GPIO_AFRH_AFRH3_1 GPIO_AFRH_AFSEL11_1 #define GPIO_AFRH_AFRH3_2 GPIO_AFRH_AFSEL11_2 #define GPIO_AFRH_AFRH3_3 GPIO_AFRH_AFSEL11_3 #define GPIO_AFRH_AFRH4 GPIO_AFRH_AFSEL12 #define GPIO_AFRH_AFRH4_0 GPIO_AFRH_AFSEL12_0 #define GPIO_AFRH_AFRH4_1 GPIO_AFRH_AFSEL12_1 #define GPIO_AFRH_AFRH4_2 GPIO_AFRH_AFSEL12_2 #define GPIO_AFRH_AFRH4_3 GPIO_AFRH_AFSEL12_3 #define GPIO_AFRH_AFRH5 GPIO_AFRH_AFSEL13 #define GPIO_AFRH_AFRH5_0 GPIO_AFRH_AFSEL13_0 #define GPIO_AFRH_AFRH5_1 GPIO_AFRH_AFSEL13_1 #define GPIO_AFRH_AFRH5_2 GPIO_AFRH_AFSEL13_2 #define GPIO_AFRH_AFRH5_3 GPIO_AFRH_AFSEL13_3 #define GPIO_AFRH_AFRH6 GPIO_AFRH_AFSEL14 #define GPIO_AFRH_AFRH6_0 GPIO_AFRH_AFSEL14_0 #define GPIO_AFRH_AFRH6_1 GPIO_AFRH_AFSEL14_1 #define GPIO_AFRH_AFRH6_2 GPIO_AFRH_AFSEL14_2 #define GPIO_AFRH_AFRH6_3 GPIO_AFRH_AFSEL14_3 #define GPIO_AFRH_AFRH7 GPIO_AFRH_AFSEL15 #define GPIO_AFRH_AFRH7_0 GPIO_AFRH_AFSEL15_0 #define GPIO_AFRH_AFRH7_1 GPIO_AFRH_AFSEL15_1 #define GPIO_AFRH_AFRH7_2 GPIO_AFRH_AFSEL15_2 #define GPIO_AFRH_AFRH7_3 GPIO_AFRH_AFSEL15_3 /****************** Bits definition for GPIO_BRR register ******************/ #define GPIO_BRR_BR0_Pos (0U) #define GPIO_BRR_BR0_Msk (0x1U << GPIO_BRR_BR0_Pos) /*!< 0x00000001 */ #define GPIO_BRR_BR0 GPIO_BRR_BR0_Msk #define GPIO_BRR_BR1_Pos (1U) #define GPIO_BRR_BR1_Msk (0x1U << GPIO_BRR_BR1_Pos) /*!< 0x00000002 */ #define GPIO_BRR_BR1 GPIO_BRR_BR1_Msk #define GPIO_BRR_BR2_Pos (2U) #define GPIO_BRR_BR2_Msk (0x1U << GPIO_BRR_BR2_Pos) /*!< 0x00000004 */ #define GPIO_BRR_BR2 GPIO_BRR_BR2_Msk #define GPIO_BRR_BR3_Pos (3U) #define GPIO_BRR_BR3_Msk (0x1U << GPIO_BRR_BR3_Pos) /*!< 0x00000008 */ #define GPIO_BRR_BR3 GPIO_BRR_BR3_Msk #define GPIO_BRR_BR4_Pos (4U) #define GPIO_BRR_BR4_Msk (0x1U << GPIO_BRR_BR4_Pos) /*!< 0x00000010 */ #define GPIO_BRR_BR4 GPIO_BRR_BR4_Msk #define GPIO_BRR_BR5_Pos (5U) #define GPIO_BRR_BR5_Msk (0x1U << GPIO_BRR_BR5_Pos) /*!< 0x00000020 */ #define GPIO_BRR_BR5 GPIO_BRR_BR5_Msk #define GPIO_BRR_BR6_Pos (6U) #define GPIO_BRR_BR6_Msk (0x1U << GPIO_BRR_BR6_Pos) /*!< 0x00000040 */ #define GPIO_BRR_BR6 GPIO_BRR_BR6_Msk #define GPIO_BRR_BR7_Pos (7U) #define GPIO_BRR_BR7_Msk (0x1U << GPIO_BRR_BR7_Pos) /*!< 0x00000080 */ #define GPIO_BRR_BR7 GPIO_BRR_BR7_Msk #define GPIO_BRR_BR8_Pos (8U) #define GPIO_BRR_BR8_Msk (0x1U << GPIO_BRR_BR8_Pos) /*!< 0x00000100 */ #define GPIO_BRR_BR8 GPIO_BRR_BR8_Msk #define GPIO_BRR_BR9_Pos (9U) #define GPIO_BRR_BR9_Msk (0x1U << GPIO_BRR_BR9_Pos) /*!< 0x00000200 */ #define GPIO_BRR_BR9 GPIO_BRR_BR9_Msk #define GPIO_BRR_BR10_Pos (10U) #define GPIO_BRR_BR10_Msk (0x1U << GPIO_BRR_BR10_Pos) /*!< 0x00000400 */ #define GPIO_BRR_BR10 GPIO_BRR_BR10_Msk #define GPIO_BRR_BR11_Pos (11U) #define GPIO_BRR_BR11_Msk (0x1U << GPIO_BRR_BR11_Pos) /*!< 0x00000800 */ #define GPIO_BRR_BR11 GPIO_BRR_BR11_Msk #define GPIO_BRR_BR12_Pos (12U) #define GPIO_BRR_BR12_Msk (0x1U << GPIO_BRR_BR12_Pos) /*!< 0x00001000 */ #define GPIO_BRR_BR12 GPIO_BRR_BR12_Msk #define GPIO_BRR_BR13_Pos (13U) #define GPIO_BRR_BR13_Msk (0x1U << GPIO_BRR_BR13_Pos) /*!< 0x00002000 */ #define GPIO_BRR_BR13 GPIO_BRR_BR13_Msk #define GPIO_BRR_BR14_Pos (14U) #define GPIO_BRR_BR14_Msk (0x1U << GPIO_BRR_BR14_Pos) /*!< 0x00004000 */ #define GPIO_BRR_BR14 GPIO_BRR_BR14_Msk #define GPIO_BRR_BR15_Pos (15U) #define GPIO_BRR_BR15_Msk (0x1U << GPIO_BRR_BR15_Pos) /*!< 0x00008000 */ #define GPIO_BRR_BR15 GPIO_BRR_BR15_Msk /******************************************************************************/ /* */ /* Inter-integrated Circuit Interface */ /* */ /******************************************************************************/ /******************* Bit definition for I2C_CR1 register ********************/ #define I2C_CR1_PE_Pos (0U) #define I2C_CR1_PE_Msk (0x1U << I2C_CR1_PE_Pos) /*!< 0x00000001 */ #define I2C_CR1_PE I2C_CR1_PE_Msk /*!<Peripheral Enable */ #define I2C_CR1_SMBUS_Pos (1U) #define I2C_CR1_SMBUS_Msk (0x1U << I2C_CR1_SMBUS_Pos) /*!< 0x00000002 */ #define I2C_CR1_SMBUS I2C_CR1_SMBUS_Msk /*!<SMBus Mode */ #define I2C_CR1_SMBTYPE_Pos (3U) #define I2C_CR1_SMBTYPE_Msk (0x1U << I2C_CR1_SMBTYPE_Pos) /*!< 0x00000008 */ #define I2C_CR1_SMBTYPE I2C_CR1_SMBTYPE_Msk /*!<SMBus Type */ #define I2C_CR1_ENARP_Pos (4U) #define I2C_CR1_ENARP_Msk (0x1U << I2C_CR1_ENARP_Pos) /*!< 0x00000010 */ #define I2C_CR1_ENARP I2C_CR1_ENARP_Msk /*!<ARP Enable */ #define I2C_CR1_ENPEC_Pos (5U) #define I2C_CR1_ENPEC_Msk (0x1U << I2C_CR1_ENPEC_Pos) /*!< 0x00000020 */ #define I2C_CR1_ENPEC I2C_CR1_ENPEC_Msk /*!<PEC Enable */ #define I2C_CR1_ENGC_Pos (6U) #define I2C_CR1_ENGC_Msk (0x1U << I2C_CR1_ENGC_Pos) /*!< 0x00000040 */ #define I2C_CR1_ENGC I2C_CR1_ENGC_Msk /*!<General Call Enable */ #define I2C_CR1_NOSTRETCH_Pos (7U) #define I2C_CR1_NOSTRETCH_Msk (0x1U << I2C_CR1_NOSTRETCH_Pos) /*!< 0x00000080 */ #define I2C_CR1_NOSTRETCH I2C_CR1_NOSTRETCH_Msk /*!<Clock Stretching Disable (Slave mode) */ #define I2C_CR1_START_Pos (8U) #define I2C_CR1_START_Msk (0x1U << I2C_CR1_START_Pos) /*!< 0x00000100 */ #define I2C_CR1_START I2C_CR1_START_Msk /*!<Start Generation */ #define I2C_CR1_STOP_Pos (9U) #define I2C_CR1_STOP_Msk (0x1U << I2C_CR1_STOP_Pos) /*!< 0x00000200 */ #define I2C_CR1_STOP I2C_CR1_STOP_Msk /*!<Stop Generation */ #define I2C_CR1_ACK_Pos (10U) #define I2C_CR1_ACK_Msk (0x1U << I2C_CR1_ACK_Pos) /*!< 0x00000400 */ #define I2C_CR1_ACK I2C_CR1_ACK_Msk /*!<Acknowledge Enable */ #define I2C_CR1_POS_Pos (11U) #define I2C_CR1_POS_Msk (0x1U << I2C_CR1_POS_Pos) /*!< 0x00000800 */ #define I2C_CR1_POS I2C_CR1_POS_Msk /*!<Acknowledge/PEC Position (for data reception) */ #define I2C_CR1_PEC_Pos (12U) #define I2C_CR1_PEC_Msk (0x1U << I2C_CR1_PEC_Pos) /*!< 0x00001000 */ #define I2C_CR1_PEC I2C_CR1_PEC_Msk /*!<Packet Error Checking */ #define I2C_CR1_ALERT_Pos (13U) #define I2C_CR1_ALERT_Msk (0x1U << I2C_CR1_ALERT_Pos) /*!< 0x00002000 */ #define I2C_CR1_ALERT I2C_CR1_ALERT_Msk /*!<SMBus Alert */ #define I2C_CR1_SWRST_Pos (15U) #define I2C_CR1_SWRST_Msk (0x1U << I2C_CR1_SWRST_Pos) /*!< 0x00008000 */ #define I2C_CR1_SWRST I2C_CR1_SWRST_Msk /*!<Software Reset */ /******************* Bit definition for I2C_CR2 register ********************/ #define I2C_CR2_FREQ_Pos (0U) #define I2C_CR2_FREQ_Msk (0x3FU << I2C_CR2_FREQ_Pos) /*!< 0x0000003F */ #define I2C_CR2_FREQ I2C_CR2_FREQ_Msk /*!<FREQ[5:0] bits (Peripheral Clock Frequency) */ #define I2C_CR2_FREQ_0 (0x01U << I2C_CR2_FREQ_Pos) /*!< 0x00000001 */ #define I2C_CR2_FREQ_1 (0x02U << I2C_CR2_FREQ_Pos) /*!< 0x00000002 */ #define I2C_CR2_FREQ_2 (0x04U << I2C_CR2_FREQ_Pos) /*!< 0x00000004 */ #define I2C_CR2_FREQ_3 (0x08U << I2C_CR2_FREQ_Pos) /*!< 0x00000008 */ #define I2C_CR2_FREQ_4 (0x10U << I2C_CR2_FREQ_Pos) /*!< 0x00000010 */ #define I2C_CR2_FREQ_5 (0x20U << I2C_CR2_FREQ_Pos) /*!< 0x00000020 */ #define I2C_CR2_ITERREN_Pos (8U) #define I2C_CR2_ITERREN_Msk (0x1U << I2C_CR2_ITERREN_Pos) /*!< 0x00000100 */ #define I2C_CR2_ITERREN I2C_CR2_ITERREN_Msk /*!<Error Interrupt Enable */ #define I2C_CR2_ITEVTEN_Pos (9U) #define I2C_CR2_ITEVTEN_Msk (0x1U << I2C_CR2_ITEVTEN_Pos) /*!< 0x00000200 */ #define I2C_CR2_ITEVTEN I2C_CR2_ITEVTEN_Msk /*!<Event Interrupt Enable */ #define I2C_CR2_ITBUFEN_Pos (10U) #define I2C_CR2_ITBUFEN_Msk (0x1U << I2C_CR2_ITBUFEN_Pos) /*!< 0x00000400 */ #define I2C_CR2_ITBUFEN I2C_CR2_ITBUFEN_Msk /*!<Buffer Interrupt Enable */ #define I2C_CR2_DMAEN_Pos (11U) #define I2C_CR2_DMAEN_Msk (0x1U << I2C_CR2_DMAEN_Pos) /*!< 0x00000800 */ #define I2C_CR2_DMAEN I2C_CR2_DMAEN_Msk /*!<DMA Requests Enable */ #define I2C_CR2_LAST_Pos (12U) #define I2C_CR2_LAST_Msk (0x1U << I2C_CR2_LAST_Pos) /*!< 0x00001000 */ #define I2C_CR2_LAST I2C_CR2_LAST_Msk /*!<DMA Last Transfer */ /******************* Bit definition for I2C_OAR1 register *******************/ #define I2C_OAR1_ADD1_7 0x000000FEU /*!<Interface Address */ #define I2C_OAR1_ADD8_9 0x00000300U /*!<Interface Address */ #define I2C_OAR1_ADD0_Pos (0U) #define I2C_OAR1_ADD0_Msk (0x1U << I2C_OAR1_ADD0_Pos) /*!< 0x00000001 */ #define I2C_OAR1_ADD0 I2C_OAR1_ADD0_Msk /*!<Bit 0 */ #define I2C_OAR1_ADD1_Pos (1U) #define I2C_OAR1_ADD1_Msk (0x1U << I2C_OAR1_ADD1_Pos) /*!< 0x00000002 */ #define I2C_OAR1_ADD1 I2C_OAR1_ADD1_Msk /*!<Bit 1 */ #define I2C_OAR1_ADD2_Pos (2U) #define I2C_OAR1_ADD2_Msk (0x1U << I2C_OAR1_ADD2_Pos) /*!< 0x00000004 */ #define I2C_OAR1_ADD2 I2C_OAR1_ADD2_Msk /*!<Bit 2 */ #define I2C_OAR1_ADD3_Pos (3U) #define I2C_OAR1_ADD3_Msk (0x1U << I2C_OAR1_ADD3_Pos) /*!< 0x00000008 */ #define I2C_OAR1_ADD3 I2C_OAR1_ADD3_Msk /*!<Bit 3 */ #define I2C_OAR1_ADD4_Pos (4U) #define I2C_OAR1_ADD4_Msk (0x1U << I2C_OAR1_ADD4_Pos) /*!< 0x00000010 */ #define I2C_OAR1_ADD4 I2C_OAR1_ADD4_Msk /*!<Bit 4 */ #define I2C_OAR1_ADD5_Pos (5U) #define I2C_OAR1_ADD5_Msk (0x1U << I2C_OAR1_ADD5_Pos) /*!< 0x00000020 */ #define I2C_OAR1_ADD5 I2C_OAR1_ADD5_Msk /*!<Bit 5 */ #define I2C_OAR1_ADD6_Pos (6U) #define I2C_OAR1_ADD6_Msk (0x1U << I2C_OAR1_ADD6_Pos) /*!< 0x00000040 */ #define I2C_OAR1_ADD6 I2C_OAR1_ADD6_Msk /*!<Bit 6 */ #define I2C_OAR1_ADD7_Pos (7U) #define I2C_OAR1_ADD7_Msk (0x1U << I2C_OAR1_ADD7_Pos) /*!< 0x00000080 */ #define I2C_OAR1_ADD7 I2C_OAR1_ADD7_Msk /*!<Bit 7 */ #define I2C_OAR1_ADD8_Pos (8U) #define I2C_OAR1_ADD8_Msk (0x1U << I2C_OAR1_ADD8_Pos) /*!< 0x00000100 */ #define I2C_OAR1_ADD8 I2C_OAR1_ADD8_Msk /*!<Bit 8 */ #define I2C_OAR1_ADD9_Pos (9U) #define I2C_OAR1_ADD9_Msk (0x1U << I2C_OAR1_ADD9_Pos) /*!< 0x00000200 */ #define I2C_OAR1_ADD9 I2C_OAR1_ADD9_Msk /*!<Bit 9 */ #define I2C_OAR1_ADDMODE_Pos (15U) #define I2C_OAR1_ADDMODE_Msk (0x1U << I2C_OAR1_ADDMODE_Pos) /*!< 0x00008000 */ #define I2C_OAR1_ADDMODE I2C_OAR1_ADDMODE_Msk /*!<Addressing Mode (Slave mode) */ /******************* Bit definition for I2C_OAR2 register *******************/ #define I2C_OAR2_ENDUAL_Pos (0U) #define I2C_OAR2_ENDUAL_Msk (0x1U << I2C_OAR2_ENDUAL_Pos) /*!< 0x00000001 */ #define I2C_OAR2_ENDUAL I2C_OAR2_ENDUAL_Msk /*!<Dual addressing mode enable */ #define I2C_OAR2_ADD2_Pos (1U) #define I2C_OAR2_ADD2_Msk (0x7FU << I2C_OAR2_ADD2_Pos) /*!< 0x000000FE */ #define I2C_OAR2_ADD2 I2C_OAR2_ADD2_Msk /*!<Interface address */ /******************** Bit definition for I2C_DR register ********************/ #define I2C_DR_DR_Pos (0U) #define I2C_DR_DR_Msk (0xFFU << I2C_DR_DR_Pos) /*!< 0x000000FF */ #define I2C_DR_DR I2C_DR_DR_Msk /*!<8-bit Data Register */ /******************* Bit definition for I2C_SR1 register ********************/ #define I2C_SR1_SB_Pos (0U) #define I2C_SR1_SB_Msk (0x1U << I2C_SR1_SB_Pos) /*!< 0x00000001 */ #define I2C_SR1_SB I2C_SR1_SB_Msk /*!<Start Bit (Master mode) */ #define I2C_SR1_ADDR_Pos (1U) #define I2C_SR1_ADDR_Msk (0x1U << I2C_SR1_ADDR_Pos) /*!< 0x00000002 */ #define I2C_SR1_ADDR I2C_SR1_ADDR_Msk /*!<Address sent (master mode)/matched (slave mode) */ #define I2C_SR1_BTF_Pos (2U) #define I2C_SR1_BTF_Msk (0x1U << I2C_SR1_BTF_Pos) /*!< 0x00000004 */ #define I2C_SR1_BTF I2C_SR1_BTF_Msk /*!<Byte Transfer Finished */ #define I2C_SR1_ADD10_Pos (3U) #define I2C_SR1_ADD10_Msk (0x1U << I2C_SR1_ADD10_Pos) /*!< 0x00000008 */ #define I2C_SR1_ADD10 I2C_SR1_ADD10_Msk /*!<10-bit header sent (Master mode) */ #define I2C_SR1_STOPF_Pos (4U) #define I2C_SR1_STOPF_Msk (0x1U << I2C_SR1_STOPF_Pos) /*!< 0x00000010 */ #define I2C_SR1_STOPF I2C_SR1_STOPF_Msk /*!<Stop detection (Slave mode) */ #define I2C_SR1_RXNE_Pos (6U) #define I2C_SR1_RXNE_Msk (0x1U << I2C_SR1_RXNE_Pos) /*!< 0x00000040 */ #define I2C_SR1_RXNE I2C_SR1_RXNE_Msk /*!<Data Register not Empty (receivers) */ #define I2C_SR1_TXE_Pos (7U) #define I2C_SR1_TXE_Msk (0x1U << I2C_SR1_TXE_Pos) /*!< 0x00000080 */ #define I2C_SR1_TXE I2C_SR1_TXE_Msk /*!<Data Register Empty (transmitters) */ #define I2C_SR1_BERR_Pos (8U) #define I2C_SR1_BERR_Msk (0x1U << I2C_SR1_BERR_Pos) /*!< 0x00000100 */ #define I2C_SR1_BERR I2C_SR1_BERR_Msk /*!<Bus Error */ #define I2C_SR1_ARLO_Pos (9U) #define I2C_SR1_ARLO_Msk (0x1U << I2C_SR1_ARLO_Pos) /*!< 0x00000200 */ #define I2C_SR1_ARLO I2C_SR1_ARLO_Msk /*!<Arbitration Lost (master mode) */ #define I2C_SR1_AF_Pos (10U) #define I2C_SR1_AF_Msk (0x1U << I2C_SR1_AF_Pos) /*!< 0x00000400 */ #define I2C_SR1_AF I2C_SR1_AF_Msk /*!<Acknowledge Failure */ #define I2C_SR1_OVR_Pos (11U) #define I2C_SR1_OVR_Msk (0x1U << I2C_SR1_OVR_Pos) /*!< 0x00000800 */ #define I2C_SR1_OVR I2C_SR1_OVR_Msk /*!<Overrun/Underrun */ #define I2C_SR1_PECERR_Pos (12U) #define I2C_SR1_PECERR_Msk (0x1U << I2C_SR1_PECERR_Pos) /*!< 0x00001000 */ #define I2C_SR1_PECERR I2C_SR1_PECERR_Msk /*!<PEC Error in reception */ #define I2C_SR1_TIMEOUT_Pos (14U) #define I2C_SR1_TIMEOUT_Msk (0x1U << I2C_SR1_TIMEOUT_Pos) /*!< 0x00004000 */ #define I2C_SR1_TIMEOUT I2C_SR1_TIMEOUT_Msk /*!<Timeout or Tlow Error */ #define I2C_SR1_SMBALERT_Pos (15U) #define I2C_SR1_SMBALERT_Msk (0x1U << I2C_SR1_SMBALERT_Pos) /*!< 0x00008000 */ #define I2C_SR1_SMBALERT I2C_SR1_SMBALERT_Msk /*!<SMBus Alert */ /******************* Bit definition for I2C_SR2 register ********************/ #define I2C_SR2_MSL_Pos (0U) #define I2C_SR2_MSL_Msk (0x1U << I2C_SR2_MSL_Pos) /*!< 0x00000001 */ #define I2C_SR2_MSL I2C_SR2_MSL_Msk /*!<Master/Slave */ #define I2C_SR2_BUSY_Pos (1U) #define I2C_SR2_BUSY_Msk (0x1U << I2C_SR2_BUSY_Pos) /*!< 0x00000002 */ #define I2C_SR2_BUSY I2C_SR2_BUSY_Msk /*!<Bus Busy */ #define I2C_SR2_TRA_Pos (2U) #define I2C_SR2_TRA_Msk (0x1U << I2C_SR2_TRA_Pos) /*!< 0x00000004 */ #define I2C_SR2_TRA I2C_SR2_TRA_Msk /*!<Transmitter/Receiver */ #define I2C_SR2_GENCALL_Pos (4U) #define I2C_SR2_GENCALL_Msk (0x1U << I2C_SR2_GENCALL_Pos) /*!< 0x00000010 */ #define I2C_SR2_GENCALL I2C_SR2_GENCALL_Msk /*!<General Call Address (Slave mode) */ #define I2C_SR2_SMBDEFAULT_Pos (5U) #define I2C_SR2_SMBDEFAULT_Msk (0x1U << I2C_SR2_SMBDEFAULT_Pos) /*!< 0x00000020 */ #define I2C_SR2_SMBDEFAULT I2C_SR2_SMBDEFAULT_Msk /*!<SMBus Device Default Address (Slave mode) */ #define I2C_SR2_SMBHOST_Pos (6U) #define I2C_SR2_SMBHOST_Msk (0x1U << I2C_SR2_SMBHOST_Pos) /*!< 0x00000040 */ #define I2C_SR2_SMBHOST I2C_SR2_SMBHOST_Msk /*!<SMBus Host Header (Slave mode) */ #define I2C_SR2_DUALF_Pos (7U) #define I2C_SR2_DUALF_Msk (0x1U << I2C_SR2_DUALF_Pos) /*!< 0x00000080 */ #define I2C_SR2_DUALF I2C_SR2_DUALF_Msk /*!<Dual Flag (Slave mode) */ #define I2C_SR2_PEC_Pos (8U) #define I2C_SR2_PEC_Msk (0xFFU << I2C_SR2_PEC_Pos) /*!< 0x0000FF00 */ #define I2C_SR2_PEC I2C_SR2_PEC_Msk /*!<Packet Error Checking Register */ /******************* Bit definition for I2C_CCR register ********************/ #define I2C_CCR_CCR_Pos (0U) #define I2C_CCR_CCR_Msk (0xFFFU << I2C_CCR_CCR_Pos) /*!< 0x00000FFF */ #define I2C_CCR_CCR I2C_CCR_CCR_Msk /*!<Clock Control Register in Fast/Standard mode (Master mode) */ #define I2C_CCR_DUTY_Pos (14U) #define I2C_CCR_DUTY_Msk (0x1U << I2C_CCR_DUTY_Pos) /*!< 0x00004000 */ #define I2C_CCR_DUTY I2C_CCR_DUTY_Msk /*!<Fast Mode Duty Cycle */ #define I2C_CCR_FS_Pos (15U) #define I2C_CCR_FS_Msk (0x1U << I2C_CCR_FS_Pos) /*!< 0x00008000 */ #define I2C_CCR_FS I2C_CCR_FS_Msk /*!<I2C Master Mode Selection */ /****************** Bit definition for I2C_TRISE register *******************/ #define I2C_TRISE_TRISE_Pos (0U) #define I2C_TRISE_TRISE_Msk (0x3FU << I2C_TRISE_TRISE_Pos) /*!< 0x0000003F */ #define I2C_TRISE_TRISE I2C_TRISE_TRISE_Msk /*!<Maximum Rise Time in Fast/Standard mode (Master mode) */ /****************** Bit definition for I2C_FLTR register *******************/ #define I2C_FLTR_DNF_Pos (0U) #define I2C_FLTR_DNF_Msk (0xFU << I2C_FLTR_DNF_Pos) /*!< 0x0000000F */ #define I2C_FLTR_DNF I2C_FLTR_DNF_Msk /*!<Digital Noise Filter */ #define I2C_FLTR_ANOFF_Pos (4U) #define I2C_FLTR_ANOFF_Msk (0x1U << I2C_FLTR_ANOFF_Pos) /*!< 0x00000010 */ #define I2C_FLTR_ANOFF I2C_FLTR_ANOFF_Msk /*!<Analog Noise Filter OFF */ /******************************************************************************/ /* */ /* Independent WATCHDOG */ /* */ /******************************************************************************/ /******************* Bit definition for IWDG_KR register ********************/ #define IWDG_KR_KEY_Pos (0U) #define IWDG_KR_KEY_Msk (0xFFFFU << IWDG_KR_KEY_Pos) /*!< 0x0000FFFF */ #define IWDG_KR_KEY IWDG_KR_KEY_Msk /*!<Key value (write only, read 0000h) */ /******************* Bit definition for IWDG_PR register ********************/ #define IWDG_PR_PR_Pos (0U) #define IWDG_PR_PR_Msk (0x7U << IWDG_PR_PR_Pos) /*!< 0x00000007 */ #define IWDG_PR_PR IWDG_PR_PR_Msk /*!<PR[2:0] (Prescaler divider) */ #define IWDG_PR_PR_0 (0x1U << IWDG_PR_PR_Pos) /*!< 0x01 */ #define IWDG_PR_PR_1 (0x2U << IWDG_PR_PR_Pos) /*!< 0x02 */ #define IWDG_PR_PR_2 (0x4U << IWDG_PR_PR_Pos) /*!< 0x04 */ /******************* Bit definition for IWDG_RLR register *******************/ #define IWDG_RLR_RL_Pos (0U) #define IWDG_RLR_RL_Msk (0xFFFU << IWDG_RLR_RL_Pos) /*!< 0x00000FFF */ #define IWDG_RLR_RL IWDG_RLR_RL_Msk /*!<Watchdog counter reload value */ /******************* Bit definition for IWDG_SR register ********************/ #define IWDG_SR_PVU_Pos (0U) #define IWDG_SR_PVU_Msk (0x1U << IWDG_SR_PVU_Pos) /*!< 0x00000001 */ #define IWDG_SR_PVU IWDG_SR_PVU_Msk /*!<Watchdog prescaler value update */ #define IWDG_SR_RVU_Pos (1U) #define IWDG_SR_RVU_Msk (0x1U << IWDG_SR_RVU_Pos) /*!< 0x00000002 */ #define IWDG_SR_RVU IWDG_SR_RVU_Msk /*!<Watchdog counter reload value update */ /******************************************************************************/ /* */ /* LCD-TFT Display Controller (LTDC) */ /* */ /******************************************************************************/ /******************** Bit definition for LTDC_SSCR register *****************/ #define LTDC_SSCR_VSH_Pos (0U) #define LTDC_SSCR_VSH_Msk (0x7FFU << LTDC_SSCR_VSH_Pos) /*!< 0x000007FF */ #define LTDC_SSCR_VSH LTDC_SSCR_VSH_Msk /*!< Vertical Synchronization Height */ #define LTDC_SSCR_HSW_Pos (16U) #define LTDC_SSCR_HSW_Msk (0xFFFU << LTDC_SSCR_HSW_Pos) /*!< 0x0FFF0000 */ #define LTDC_SSCR_HSW LTDC_SSCR_HSW_Msk /*!< Horizontal Synchronization Width */ /******************** Bit definition for LTDC_BPCR register *****************/ #define LTDC_BPCR_AVBP_Pos (0U) #define LTDC_BPCR_AVBP_Msk (0x7FFU << LTDC_BPCR_AVBP_Pos) /*!< 0x000007FF */ #define LTDC_BPCR_AVBP LTDC_BPCR_AVBP_Msk /*!< Accumulated Vertical Back Porch */ #define LTDC_BPCR_AHBP_Pos (16U) #define LTDC_BPCR_AHBP_Msk (0xFFFU << LTDC_BPCR_AHBP_Pos) /*!< 0x0FFF0000 */ #define LTDC_BPCR_AHBP LTDC_BPCR_AHBP_Msk /*!< Accumulated Horizontal Back Porch */ /******************** Bit definition for LTDC_AWCR register *****************/ #define LTDC_AWCR_AAH_Pos (0U) #define LTDC_AWCR_AAH_Msk (0x7FFU << LTDC_AWCR_AAH_Pos) /*!< 0x000007FF */ #define LTDC_AWCR_AAH LTDC_AWCR_AAH_Msk /*!< Accumulated Active heigh */ #define LTDC_AWCR_AAW_Pos (16U) #define LTDC_AWCR_AAW_Msk (0xFFFU << LTDC_AWCR_AAW_Pos) /*!< 0x0FFF0000 */ #define LTDC_AWCR_AAW LTDC_AWCR_AAW_Msk /*!< Accumulated Active Width */ /******************** Bit definition for LTDC_TWCR register *****************/ #define LTDC_TWCR_TOTALH_Pos (0U) #define LTDC_TWCR_TOTALH_Msk (0x7FFU << LTDC_TWCR_TOTALH_Pos) /*!< 0x000007FF */ #define LTDC_TWCR_TOTALH LTDC_TWCR_TOTALH_Msk /*!< Total Heigh */ #define LTDC_TWCR_TOTALW_Pos (16U) #define LTDC_TWCR_TOTALW_Msk (0xFFFU << LTDC_TWCR_TOTALW_Pos) /*!< 0x0FFF0000 */ #define LTDC_TWCR_TOTALW LTDC_TWCR_TOTALW_Msk /*!< Total Width */ /******************** Bit definition for LTDC_GCR register ******************/ #define LTDC_GCR_LTDCEN_Pos (0U) #define LTDC_GCR_LTDCEN_Msk (0x1U << LTDC_GCR_LTDCEN_Pos) /*!< 0x00000001 */ #define LTDC_GCR_LTDCEN LTDC_GCR_LTDCEN_Msk /*!< LCD-TFT controller enable bit */ #define LTDC_GCR_DBW_Pos (4U) #define LTDC_GCR_DBW_Msk (0x7U << LTDC_GCR_DBW_Pos) /*!< 0x00000070 */ #define LTDC_GCR_DBW LTDC_GCR_DBW_Msk /*!< Dither Blue Width */ #define LTDC_GCR_DGW_Pos (8U) #define LTDC_GCR_DGW_Msk (0x7U << LTDC_GCR_DGW_Pos) /*!< 0x00000700 */ #define LTDC_GCR_DGW LTDC_GCR_DGW_Msk /*!< Dither Green Width */ #define LTDC_GCR_DRW_Pos (12U) #define LTDC_GCR_DRW_Msk (0x7U << LTDC_GCR_DRW_Pos) /*!< 0x00007000 */ #define LTDC_GCR_DRW LTDC_GCR_DRW_Msk /*!< Dither Red Width */ #define LTDC_GCR_DEN_Pos (16U) #define LTDC_GCR_DEN_Msk (0x1U << LTDC_GCR_DEN_Pos) /*!< 0x00010000 */ #define LTDC_GCR_DEN LTDC_GCR_DEN_Msk /*!< Dither Enable */ #define LTDC_GCR_PCPOL_Pos (28U) #define LTDC_GCR_PCPOL_Msk (0x1U << LTDC_GCR_PCPOL_Pos) /*!< 0x10000000 */ #define LTDC_GCR_PCPOL LTDC_GCR_PCPOL_Msk /*!< Pixel Clock Polarity */ #define LTDC_GCR_DEPOL_Pos (29U) #define LTDC_GCR_DEPOL_Msk (0x1U << LTDC_GCR_DEPOL_Pos) /*!< 0x20000000 */ #define LTDC_GCR_DEPOL LTDC_GCR_DEPOL_Msk /*!< Data Enable Polarity */ #define LTDC_GCR_VSPOL_Pos (30U) #define LTDC_GCR_VSPOL_Msk (0x1U << LTDC_GCR_VSPOL_Pos) /*!< 0x40000000 */ #define LTDC_GCR_VSPOL LTDC_GCR_VSPOL_Msk /*!< Vertical Synchronization Polarity */ #define LTDC_GCR_HSPOL_Pos (31U) #define LTDC_GCR_HSPOL_Msk (0x1U << LTDC_GCR_HSPOL_Pos) /*!< 0x80000000 */ #define LTDC_GCR_HSPOL LTDC_GCR_HSPOL_Msk /*!< Horizontal Synchronization Polarity */ /* Legacy defines */ #define LTDC_GCR_DTEN LTDC_GCR_DEN /******************** Bit definition for LTDC_SRCR register *****************/ #define LTDC_SRCR_IMR_Pos (0U) #define LTDC_SRCR_IMR_Msk (0x1U << LTDC_SRCR_IMR_Pos) /*!< 0x00000001 */ #define LTDC_SRCR_IMR LTDC_SRCR_IMR_Msk /*!< Immediate Reload */ #define LTDC_SRCR_VBR_Pos (1U) #define LTDC_SRCR_VBR_Msk (0x1U << LTDC_SRCR_VBR_Pos) /*!< 0x00000002 */ #define LTDC_SRCR_VBR LTDC_SRCR_VBR_Msk /*!< Vertical Blanking Reload */ /******************** Bit definition for LTDC_BCCR register *****************/ #define LTDC_BCCR_BCBLUE_Pos (0U) #define LTDC_BCCR_BCBLUE_Msk (0xFFU << LTDC_BCCR_BCBLUE_Pos) /*!< 0x000000FF */ #define LTDC_BCCR_BCBLUE LTDC_BCCR_BCBLUE_Msk /*!< Background Blue value */ #define LTDC_BCCR_BCGREEN_Pos (8U) #define LTDC_BCCR_BCGREEN_Msk (0xFFU << LTDC_BCCR_BCGREEN_Pos) /*!< 0x0000FF00 */ #define LTDC_BCCR_BCGREEN LTDC_BCCR_BCGREEN_Msk /*!< Background Green value */ #define LTDC_BCCR_BCRED_Pos (16U) #define LTDC_BCCR_BCRED_Msk (0xFFU << LTDC_BCCR_BCRED_Pos) /*!< 0x00FF0000 */ #define LTDC_BCCR_BCRED LTDC_BCCR_BCRED_Msk /*!< Background Red value */ /******************** Bit definition for LTDC_IER register ******************/ #define LTDC_IER_LIE_Pos (0U) #define LTDC_IER_LIE_Msk (0x1U << LTDC_IER_LIE_Pos) /*!< 0x00000001 */ #define LTDC_IER_LIE LTDC_IER_LIE_Msk /*!< Line Interrupt Enable */ #define LTDC_IER_FUIE_Pos (1U) #define LTDC_IER_FUIE_Msk (0x1U << LTDC_IER_FUIE_Pos) /*!< 0x00000002 */ #define LTDC_IER_FUIE LTDC_IER_FUIE_Msk /*!< FIFO Underrun Interrupt Enable */ #define LTDC_IER_TERRIE_Pos (2U) #define LTDC_IER_TERRIE_Msk (0x1U << LTDC_IER_TERRIE_Pos) /*!< 0x00000004 */ #define LTDC_IER_TERRIE LTDC_IER_TERRIE_Msk /*!< Transfer Error Interrupt Enable */ #define LTDC_IER_RRIE_Pos (3U) #define LTDC_IER_RRIE_Msk (0x1U << LTDC_IER_RRIE_Pos) /*!< 0x00000008 */ #define LTDC_IER_RRIE LTDC_IER_RRIE_Msk /*!< Register Reload interrupt enable */ /******************** Bit definition for LTDC_ISR register ******************/ #define LTDC_ISR_LIF_Pos (0U) #define LTDC_ISR_LIF_Msk (0x1U << LTDC_ISR_LIF_Pos) /*!< 0x00000001 */ #define LTDC_ISR_LIF LTDC_ISR_LIF_Msk /*!< Line Interrupt Flag */ #define LTDC_ISR_FUIF_Pos (1U) #define LTDC_ISR_FUIF_Msk (0x1U << LTDC_ISR_FUIF_Pos) /*!< 0x00000002 */ #define LTDC_ISR_FUIF LTDC_ISR_FUIF_Msk /*!< FIFO Underrun Interrupt Flag */ #define LTDC_ISR_TERRIF_Pos (2U) #define LTDC_ISR_TERRIF_Msk (0x1U << LTDC_ISR_TERRIF_Pos) /*!< 0x00000004 */ #define LTDC_ISR_TERRIF LTDC_ISR_TERRIF_Msk /*!< Transfer Error Interrupt Flag */ #define LTDC_ISR_RRIF_Pos (3U) #define LTDC_ISR_RRIF_Msk (0x1U << LTDC_ISR_RRIF_Pos) /*!< 0x00000008 */ #define LTDC_ISR_RRIF LTDC_ISR_RRIF_Msk /*!< Register Reload interrupt Flag */ /******************** Bit definition for LTDC_ICR register ******************/ #define LTDC_ICR_CLIF_Pos (0U) #define LTDC_ICR_CLIF_Msk (0x1U << LTDC_ICR_CLIF_Pos) /*!< 0x00000001 */ #define LTDC_ICR_CLIF LTDC_ICR_CLIF_Msk /*!< Clears the Line Interrupt Flag */ #define LTDC_ICR_CFUIF_Pos (1U) #define LTDC_ICR_CFUIF_Msk (0x1U << LTDC_ICR_CFUIF_Pos) /*!< 0x00000002 */ #define LTDC_ICR_CFUIF LTDC_ICR_CFUIF_Msk /*!< Clears the FIFO Underrun Interrupt Flag */ #define LTDC_ICR_CTERRIF_Pos (2U) #define LTDC_ICR_CTERRIF_Msk (0x1U << LTDC_ICR_CTERRIF_Pos) /*!< 0x00000004 */ #define LTDC_ICR_CTERRIF LTDC_ICR_CTERRIF_Msk /*!< Clears the Transfer Error Interrupt Flag */ #define LTDC_ICR_CRRIF_Pos (3U) #define LTDC_ICR_CRRIF_Msk (0x1U << LTDC_ICR_CRRIF_Pos) /*!< 0x00000008 */ #define LTDC_ICR_CRRIF LTDC_ICR_CRRIF_Msk /*!< Clears Register Reload interrupt Flag */ /******************** Bit definition for LTDC_LIPCR register ****************/ #define LTDC_LIPCR_LIPOS_Pos (0U) #define LTDC_LIPCR_LIPOS_Msk (0x7FFU << LTDC_LIPCR_LIPOS_Pos) /*!< 0x000007FF */ #define LTDC_LIPCR_LIPOS LTDC_LIPCR_LIPOS_Msk /*!< Line Interrupt Position */ /******************** Bit definition for LTDC_CPSR register *****************/ #define LTDC_CPSR_CYPOS_Pos (0U) #define LTDC_CPSR_CYPOS_Msk (0xFFFFU << LTDC_CPSR_CYPOS_Pos) /*!< 0x0000FFFF */ #define LTDC_CPSR_CYPOS LTDC_CPSR_CYPOS_Msk /*!< Current Y Position */ #define LTDC_CPSR_CXPOS_Pos (16U) #define LTDC_CPSR_CXPOS_Msk (0xFFFFU << LTDC_CPSR_CXPOS_Pos) /*!< 0xFFFF0000 */ #define LTDC_CPSR_CXPOS LTDC_CPSR_CXPOS_Msk /*!< Current X Position */ /******************** Bit definition for LTDC_CDSR register *****************/ #define LTDC_CDSR_VDES_Pos (0U) #define LTDC_CDSR_VDES_Msk (0x1U << LTDC_CDSR_VDES_Pos) /*!< 0x00000001 */ #define LTDC_CDSR_VDES LTDC_CDSR_VDES_Msk /*!< Vertical Data Enable Status */ #define LTDC_CDSR_HDES_Pos (1U) #define LTDC_CDSR_HDES_Msk (0x1U << LTDC_CDSR_HDES_Pos) /*!< 0x00000002 */ #define LTDC_CDSR_HDES LTDC_CDSR_HDES_Msk /*!< Horizontal Data Enable Status */ #define LTDC_CDSR_VSYNCS_Pos (2U) #define LTDC_CDSR_VSYNCS_Msk (0x1U << LTDC_CDSR_VSYNCS_Pos) /*!< 0x00000004 */ #define LTDC_CDSR_VSYNCS LTDC_CDSR_VSYNCS_Msk /*!< Vertical Synchronization Status */ #define LTDC_CDSR_HSYNCS_Pos (3U) #define LTDC_CDSR_HSYNCS_Msk (0x1U << LTDC_CDSR_HSYNCS_Pos) /*!< 0x00000008 */ #define LTDC_CDSR_HSYNCS LTDC_CDSR_HSYNCS_Msk /*!< Horizontal Synchronization Status */ /******************** Bit definition for LTDC_LxCR register *****************/ #define LTDC_LxCR_LEN_Pos (0U) #define LTDC_LxCR_LEN_Msk (0x1U << LTDC_LxCR_LEN_Pos) /*!< 0x00000001 */ #define LTDC_LxCR_LEN LTDC_LxCR_LEN_Msk /*!< Layer Enable */ #define LTDC_LxCR_COLKEN_Pos (1U) #define LTDC_LxCR_COLKEN_Msk (0x1U << LTDC_LxCR_COLKEN_Pos) /*!< 0x00000002 */ #define LTDC_LxCR_COLKEN LTDC_LxCR_COLKEN_Msk /*!< Color Keying Enable */ #define LTDC_LxCR_CLUTEN_Pos (4U) #define LTDC_LxCR_CLUTEN_Msk (0x1U << LTDC_LxCR_CLUTEN_Pos) /*!< 0x00000010 */ #define LTDC_LxCR_CLUTEN LTDC_LxCR_CLUTEN_Msk /*!< Color Lockup Table Enable */ /******************** Bit definition for LTDC_LxWHPCR register **************/ #define LTDC_LxWHPCR_WHSTPOS_Pos (0U) #define LTDC_LxWHPCR_WHSTPOS_Msk (0xFFFU << LTDC_LxWHPCR_WHSTPOS_Pos) /*!< 0x00000FFF */ #define LTDC_LxWHPCR_WHSTPOS LTDC_LxWHPCR_WHSTPOS_Msk /*!< Window Horizontal Start Position */ #define LTDC_LxWHPCR_WHSPPOS_Pos (16U) #define LTDC_LxWHPCR_WHSPPOS_Msk (0xFFFFU << LTDC_LxWHPCR_WHSPPOS_Pos) /*!< 0xFFFF0000 */ #define LTDC_LxWHPCR_WHSPPOS LTDC_LxWHPCR_WHSPPOS_Msk /*!< Window Horizontal Stop Position */ /******************** Bit definition for LTDC_LxWVPCR register **************/ #define LTDC_LxWVPCR_WVSTPOS_Pos (0U) #define LTDC_LxWVPCR_WVSTPOS_Msk (0xFFFU << LTDC_LxWVPCR_WVSTPOS_Pos) /*!< 0x00000FFF */ #define LTDC_LxWVPCR_WVSTPOS LTDC_LxWVPCR_WVSTPOS_Msk /*!< Window Vertical Start Position */ #define LTDC_LxWVPCR_WVSPPOS_Pos (16U) #define LTDC_LxWVPCR_WVSPPOS_Msk (0xFFFFU << LTDC_LxWVPCR_WVSPPOS_Pos) /*!< 0xFFFF0000 */ #define LTDC_LxWVPCR_WVSPPOS LTDC_LxWVPCR_WVSPPOS_Msk /*!< Window Vertical Stop Position */ /******************** Bit definition for LTDC_LxCKCR register ***************/ #define LTDC_LxCKCR_CKBLUE_Pos (0U) #define LTDC_LxCKCR_CKBLUE_Msk (0xFFU << LTDC_LxCKCR_CKBLUE_Pos) /*!< 0x000000FF */ #define LTDC_LxCKCR_CKBLUE LTDC_LxCKCR_CKBLUE_Msk /*!< Color Key Blue value */ #define LTDC_LxCKCR_CKGREEN_Pos (8U) #define LTDC_LxCKCR_CKGREEN_Msk (0xFFU << LTDC_LxCKCR_CKGREEN_Pos) /*!< 0x0000FF00 */ #define LTDC_LxCKCR_CKGREEN LTDC_LxCKCR_CKGREEN_Msk /*!< Color Key Green value */ #define LTDC_LxCKCR_CKRED_Pos (16U) #define LTDC_LxCKCR_CKRED_Msk (0xFFU << LTDC_LxCKCR_CKRED_Pos) /*!< 0x00FF0000 */ #define LTDC_LxCKCR_CKRED LTDC_LxCKCR_CKRED_Msk /*!< Color Key Red value */ /******************** Bit definition for LTDC_LxPFCR register ***************/ #define LTDC_LxPFCR_PF_Pos (0U) #define LTDC_LxPFCR_PF_Msk (0x7U << LTDC_LxPFCR_PF_Pos) /*!< 0x00000007 */ #define LTDC_LxPFCR_PF LTDC_LxPFCR_PF_Msk /*!< Pixel Format */ /******************** Bit definition for LTDC_LxCACR register ***************/ #define LTDC_LxCACR_CONSTA_Pos (0U) #define LTDC_LxCACR_CONSTA_Msk (0xFFU << LTDC_LxCACR_CONSTA_Pos) /*!< 0x000000FF */ #define LTDC_LxCACR_CONSTA LTDC_LxCACR_CONSTA_Msk /*!< Constant Alpha */ /******************** Bit definition for LTDC_LxDCCR register ***************/ #define LTDC_LxDCCR_DCBLUE_Pos (0U) #define LTDC_LxDCCR_DCBLUE_Msk (0xFFU << LTDC_LxDCCR_DCBLUE_Pos) /*!< 0x000000FF */ #define LTDC_LxDCCR_DCBLUE LTDC_LxDCCR_DCBLUE_Msk /*!< Default Color Blue */ #define LTDC_LxDCCR_DCGREEN_Pos (8U) #define LTDC_LxDCCR_DCGREEN_Msk (0xFFU << LTDC_LxDCCR_DCGREEN_Pos) /*!< 0x0000FF00 */ #define LTDC_LxDCCR_DCGREEN LTDC_LxDCCR_DCGREEN_Msk /*!< Default Color Green */ #define LTDC_LxDCCR_DCRED_Pos (16U) #define LTDC_LxDCCR_DCRED_Msk (0xFFU << LTDC_LxDCCR_DCRED_Pos) /*!< 0x00FF0000 */ #define LTDC_LxDCCR_DCRED LTDC_LxDCCR_DCRED_Msk /*!< Default Color Red */ #define LTDC_LxDCCR_DCALPHA_Pos (24U) #define LTDC_LxDCCR_DCALPHA_Msk (0xFFU << LTDC_LxDCCR_DCALPHA_Pos) /*!< 0xFF000000 */ #define LTDC_LxDCCR_DCALPHA LTDC_LxDCCR_DCALPHA_Msk /*!< Default Color Alpha */ /******************** Bit definition for LTDC_LxBFCR register ***************/ #define LTDC_LxBFCR_BF2_Pos (0U) #define LTDC_LxBFCR_BF2_Msk (0x7U << LTDC_LxBFCR_BF2_Pos) /*!< 0x00000007 */ #define LTDC_LxBFCR_BF2 LTDC_LxBFCR_BF2_Msk /*!< Blending Factor 2 */ #define LTDC_LxBFCR_BF1_Pos (8U) #define LTDC_LxBFCR_BF1_Msk (0x7U << LTDC_LxBFCR_BF1_Pos) /*!< 0x00000700 */ #define LTDC_LxBFCR_BF1 LTDC_LxBFCR_BF1_Msk /*!< Blending Factor 1 */ /******************** Bit definition for LTDC_LxCFBAR register **************/ #define LTDC_LxCFBAR_CFBADD_Pos (0U) #define LTDC_LxCFBAR_CFBADD_Msk (0xFFFFFFFFU << LTDC_LxCFBAR_CFBADD_Pos) /*!< 0xFFFFFFFF */ #define LTDC_LxCFBAR_CFBADD LTDC_LxCFBAR_CFBADD_Msk /*!< Color Frame Buffer Start Address */ /******************** Bit definition for LTDC_LxCFBLR register **************/ #define LTDC_LxCFBLR_CFBLL_Pos (0U) #define LTDC_LxCFBLR_CFBLL_Msk (0x1FFFU << LTDC_LxCFBLR_CFBLL_Pos) /*!< 0x00001FFF */ #define LTDC_LxCFBLR_CFBLL LTDC_LxCFBLR_CFBLL_Msk /*!< Color Frame Buffer Line Length */ #define LTDC_LxCFBLR_CFBP_Pos (16U) #define LTDC_LxCFBLR_CFBP_Msk (0x1FFFU << LTDC_LxCFBLR_CFBP_Pos) /*!< 0x1FFF0000 */ #define LTDC_LxCFBLR_CFBP LTDC_LxCFBLR_CFBP_Msk /*!< Color Frame Buffer Pitch in bytes */ /******************** Bit definition for LTDC_LxCFBLNR register *************/ #define LTDC_LxCFBLNR_CFBLNBR_Pos (0U) #define LTDC_LxCFBLNR_CFBLNBR_Msk (0x7FFU << LTDC_LxCFBLNR_CFBLNBR_Pos) /*!< 0x000007FF */ #define LTDC_LxCFBLNR_CFBLNBR LTDC_LxCFBLNR_CFBLNBR_Msk /*!< Frame Buffer Line Number */ /******************** Bit definition for LTDC_LxCLUTWR register *************/ #define LTDC_LxCLUTWR_BLUE_Pos (0U) #define LTDC_LxCLUTWR_BLUE_Msk (0xFFU << LTDC_LxCLUTWR_BLUE_Pos) /*!< 0x000000FF */ #define LTDC_LxCLUTWR_BLUE LTDC_LxCLUTWR_BLUE_Msk /*!< Blue value */ #define LTDC_LxCLUTWR_GREEN_Pos (8U) #define LTDC_LxCLUTWR_GREEN_Msk (0xFFU << LTDC_LxCLUTWR_GREEN_Pos) /*!< 0x0000FF00 */ #define LTDC_LxCLUTWR_GREEN LTDC_LxCLUTWR_GREEN_Msk /*!< Green value */ #define LTDC_LxCLUTWR_RED_Pos (16U) #define LTDC_LxCLUTWR_RED_Msk (0xFFU << LTDC_LxCLUTWR_RED_Pos) /*!< 0x00FF0000 */ #define LTDC_LxCLUTWR_RED LTDC_LxCLUTWR_RED_Msk /*!< Red value */ #define LTDC_LxCLUTWR_CLUTADD_Pos (24U) #define LTDC_LxCLUTWR_CLUTADD_Msk (0xFFU << LTDC_LxCLUTWR_CLUTADD_Pos) /*!< 0xFF000000 */ #define LTDC_LxCLUTWR_CLUTADD LTDC_LxCLUTWR_CLUTADD_Msk /*!< CLUT address */ /******************************************************************************/ /* */ /* Power Control */ /* */ /******************************************************************************/ /******************** Bit definition for PWR_CR register ********************/ #define PWR_CR_LPDS_Pos (0U) #define PWR_CR_LPDS_Msk (0x1U << PWR_CR_LPDS_Pos) /*!< 0x00000001 */ #define PWR_CR_LPDS PWR_CR_LPDS_Msk /*!< Low-Power Deepsleep */ #define PWR_CR_PDDS_Pos (1U) #define PWR_CR_PDDS_Msk (0x1U << PWR_CR_PDDS_Pos) /*!< 0x00000002 */ #define PWR_CR_PDDS PWR_CR_PDDS_Msk /*!< Power Down Deepsleep */ #define PWR_CR_CWUF_Pos (2U) #define PWR_CR_CWUF_Msk (0x1U << PWR_CR_CWUF_Pos) /*!< 0x00000004 */ #define PWR_CR_CWUF PWR_CR_CWUF_Msk /*!< Clear Wakeup Flag */ #define PWR_CR_CSBF_Pos (3U) #define PWR_CR_CSBF_Msk (0x1U << PWR_CR_CSBF_Pos) /*!< 0x00000008 */ #define PWR_CR_CSBF PWR_CR_CSBF_Msk /*!< Clear Standby Flag */ #define PWR_CR_PVDE_Pos (4U) #define PWR_CR_PVDE_Msk (0x1U << PWR_CR_PVDE_Pos) /*!< 0x00000010 */ #define PWR_CR_PVDE PWR_CR_PVDE_Msk /*!< Power Voltage Detector Enable */ #define PWR_CR_PLS_Pos (5U) #define PWR_CR_PLS_Msk (0x7U << PWR_CR_PLS_Pos) /*!< 0x000000E0 */ #define PWR_CR_PLS PWR_CR_PLS_Msk /*!< PLS[2:0] bits (PVD Level Selection) */ #define PWR_CR_PLS_0 (0x1U << PWR_CR_PLS_Pos) /*!< 0x00000020 */ #define PWR_CR_PLS_1 (0x2U << PWR_CR_PLS_Pos) /*!< 0x00000040 */ #define PWR_CR_PLS_2 (0x4U << PWR_CR_PLS_Pos) /*!< 0x00000080 */ /*!< PVD level configuration */ #define PWR_CR_PLS_LEV0 0x00000000U /*!< PVD level 0 */ #define PWR_CR_PLS_LEV1 0x00000020U /*!< PVD level 1 */ #define PWR_CR_PLS_LEV2 0x00000040U /*!< PVD level 2 */ #define PWR_CR_PLS_LEV3 0x00000060U /*!< PVD level 3 */ #define PWR_CR_PLS_LEV4 0x00000080U /*!< PVD level 4 */ #define PWR_CR_PLS_LEV5 0x000000A0U /*!< PVD level 5 */ #define PWR_CR_PLS_LEV6 0x000000C0U /*!< PVD level 6 */ #define PWR_CR_PLS_LEV7 0x000000E0U /*!< PVD level 7 */ #define PWR_CR_DBP_Pos (8U) #define PWR_CR_DBP_Msk (0x1U << PWR_CR_DBP_Pos) /*!< 0x00000100 */ #define PWR_CR_DBP PWR_CR_DBP_Msk /*!< Disable Backup Domain write protection */ #define PWR_CR_FPDS_Pos (9U) #define PWR_CR_FPDS_Msk (0x1U << PWR_CR_FPDS_Pos) /*!< 0x00000200 */ #define PWR_CR_FPDS PWR_CR_FPDS_Msk /*!< Flash power down in Stop mode */ #define PWR_CR_LPLVDS_Pos (10U) #define PWR_CR_LPLVDS_Msk (0x1U << PWR_CR_LPLVDS_Pos) /*!< 0x00000400 */ #define PWR_CR_LPLVDS PWR_CR_LPLVDS_Msk /*!< Low-Power Regulator Low Voltage Scaling in Stop mode */ #define PWR_CR_MRLVDS_Pos (11U) #define PWR_CR_MRLVDS_Msk (0x1U << PWR_CR_MRLVDS_Pos) /*!< 0x00000800 */ #define PWR_CR_MRLVDS PWR_CR_MRLVDS_Msk /*!< Main regulator Low Voltage Scaling in Stop mode */ #define PWR_CR_ADCDC1_Pos (13U) #define PWR_CR_ADCDC1_Msk (0x1U << PWR_CR_ADCDC1_Pos) /*!< 0x00002000 */ #define PWR_CR_ADCDC1 PWR_CR_ADCDC1_Msk /*!< Refer to AN4073 on how to use this bit */ #define PWR_CR_VOS_Pos (14U) #define PWR_CR_VOS_Msk (0x3U << PWR_CR_VOS_Pos) /*!< 0x0000C000 */ #define PWR_CR_VOS PWR_CR_VOS_Msk /*!< VOS[1:0] bits (Regulator voltage scaling output selection) */ #define PWR_CR_VOS_0 0x00004000U /*!< Bit 0 */ #define PWR_CR_VOS_1 0x00008000U /*!< Bit 1 */ #define PWR_CR_ODEN_Pos (16U) #define PWR_CR_ODEN_Msk (0x1U << PWR_CR_ODEN_Pos) /*!< 0x00010000 */ #define PWR_CR_ODEN PWR_CR_ODEN_Msk /*!< Over Drive enable */ #define PWR_CR_ODSWEN_Pos (17U) #define PWR_CR_ODSWEN_Msk (0x1U << PWR_CR_ODSWEN_Pos) /*!< 0x00020000 */ #define PWR_CR_ODSWEN PWR_CR_ODSWEN_Msk /*!< Over Drive switch enabled */ #define PWR_CR_UDEN_Pos (18U) #define PWR_CR_UDEN_Msk (0x3U << PWR_CR_UDEN_Pos) /*!< 0x000C0000 */ #define PWR_CR_UDEN PWR_CR_UDEN_Msk /*!< Under Drive enable in stop mode */ #define PWR_CR_UDEN_0 (0x1U << PWR_CR_UDEN_Pos) /*!< 0x00040000 */ #define PWR_CR_UDEN_1 (0x2U << PWR_CR_UDEN_Pos) /*!< 0x00080000 */ /* Legacy define */ #define PWR_CR_PMODE PWR_CR_VOS #define PWR_CR_LPUDS PWR_CR_LPLVDS /*!< Low-Power Regulator in deepsleep under-drive mode */ #define PWR_CR_MRUDS PWR_CR_MRLVDS /*!< Main regulator in deepsleep under-drive mode */ /******************* Bit definition for PWR_CSR register ********************/ #define PWR_CSR_WUF_Pos (0U) #define PWR_CSR_WUF_Msk (0x1U << PWR_CSR_WUF_Pos) /*!< 0x00000001 */ #define PWR_CSR_WUF PWR_CSR_WUF_Msk /*!< Wakeup Flag */ #define PWR_CSR_SBF_Pos (1U) #define PWR_CSR_SBF_Msk (0x1U << PWR_CSR_SBF_Pos) /*!< 0x00000002 */ #define PWR_CSR_SBF PWR_CSR_SBF_Msk /*!< Standby Flag */ #define PWR_CSR_PVDO_Pos (2U) #define PWR_CSR_PVDO_Msk (0x1U << PWR_CSR_PVDO_Pos) /*!< 0x00000004 */ #define PWR_CSR_PVDO PWR_CSR_PVDO_Msk /*!< PVD Output */ #define PWR_CSR_BRR_Pos (3U) #define PWR_CSR_BRR_Msk (0x1U << PWR_CSR_BRR_Pos) /*!< 0x00000008 */ #define PWR_CSR_BRR PWR_CSR_BRR_Msk /*!< Backup regulator ready */ #define PWR_CSR_WUPP_Pos (7U) #define PWR_CSR_WUPP_Msk (0x1U << PWR_CSR_WUPP_Pos) /*!< 0x00000080 */ #define PWR_CSR_WUPP PWR_CSR_WUPP_Msk /*!< WKUP pin Polarity */ #define PWR_CSR_EWUP_Pos (8U) #define PWR_CSR_EWUP_Msk (0x1U << PWR_CSR_EWUP_Pos) /*!< 0x00000100 */ #define PWR_CSR_EWUP PWR_CSR_EWUP_Msk /*!< Enable WKUP pin */ #define PWR_CSR_BRE_Pos (9U) #define PWR_CSR_BRE_Msk (0x1U << PWR_CSR_BRE_Pos) /*!< 0x00000200 */ #define PWR_CSR_BRE PWR_CSR_BRE_Msk /*!< Backup regulator enable */ #define PWR_CSR_VOSRDY_Pos (14U) #define PWR_CSR_VOSRDY_Msk (0x1U << PWR_CSR_VOSRDY_Pos) /*!< 0x00004000 */ #define PWR_CSR_VOSRDY PWR_CSR_VOSRDY_Msk /*!< Regulator voltage scaling output selection ready */ #define PWR_CSR_ODRDY_Pos (16U) #define PWR_CSR_ODRDY_Msk (0x1U << PWR_CSR_ODRDY_Pos) /*!< 0x00010000 */ #define PWR_CSR_ODRDY PWR_CSR_ODRDY_Msk /*!< Over Drive generator ready */ #define PWR_CSR_ODSWRDY_Pos (17U) #define PWR_CSR_ODSWRDY_Msk (0x1U << PWR_CSR_ODSWRDY_Pos) /*!< 0x00020000 */ #define PWR_CSR_ODSWRDY PWR_CSR_ODSWRDY_Msk /*!< Over Drive Switch ready */ #define PWR_CSR_UDRDY_Pos (18U) #define PWR_CSR_UDRDY_Msk (0x3U << PWR_CSR_UDRDY_Pos) /*!< 0x000C0000 */ #define PWR_CSR_UDRDY PWR_CSR_UDRDY_Msk /*!< Under Drive ready */ /* Legacy define */ #define PWR_CSR_UDSWRDY PWR_CSR_UDRDY /* Legacy define */ #define PWR_CSR_REGRDY PWR_CSR_VOSRDY /******************************************************************************/ /* */ /* QUADSPI */ /* */ /******************************************************************************/ /***************** Bit definition for QUADSPI_CR register *******************/ #define QUADSPI_CR_EN_Pos (0U) #define QUADSPI_CR_EN_Msk (0x1U << QUADSPI_CR_EN_Pos) /*!< 0x00000001 */ #define QUADSPI_CR_EN QUADSPI_CR_EN_Msk /*!< Enable */ #define QUADSPI_CR_ABORT_Pos (1U) #define QUADSPI_CR_ABORT_Msk (0x1U << QUADSPI_CR_ABORT_Pos) /*!< 0x00000002 */ #define QUADSPI_CR_ABORT QUADSPI_CR_ABORT_Msk /*!< Abort request */ #define QUADSPI_CR_DMAEN_Pos (2U) #define QUADSPI_CR_DMAEN_Msk (0x1U << QUADSPI_CR_DMAEN_Pos) /*!< 0x00000004 */ #define QUADSPI_CR_DMAEN QUADSPI_CR_DMAEN_Msk /*!< DMA Enable */ #define QUADSPI_CR_TCEN_Pos (3U) #define QUADSPI_CR_TCEN_Msk (0x1U << QUADSPI_CR_TCEN_Pos) /*!< 0x00000008 */ #define QUADSPI_CR_TCEN QUADSPI_CR_TCEN_Msk /*!< Timeout Counter Enable */ #define QUADSPI_CR_SSHIFT_Pos (4U) #define QUADSPI_CR_SSHIFT_Msk (0x1U << QUADSPI_CR_SSHIFT_Pos) /*!< 0x00000010 */ #define QUADSPI_CR_SSHIFT QUADSPI_CR_SSHIFT_Msk /*!< SSHIFT Sample Shift */ #define QUADSPI_CR_DFM_Pos (6U) #define QUADSPI_CR_DFM_Msk (0x1U << QUADSPI_CR_DFM_Pos) /*!< 0x00000040 */ #define QUADSPI_CR_DFM QUADSPI_CR_DFM_Msk /*!< Dual Flash Mode */ #define QUADSPI_CR_FSEL_Pos (7U) #define QUADSPI_CR_FSEL_Msk (0x1U << QUADSPI_CR_FSEL_Pos) /*!< 0x00000080 */ #define QUADSPI_CR_FSEL QUADSPI_CR_FSEL_Msk /*!< Flash Select */ #define QUADSPI_CR_FTHRES_Pos (8U) #define QUADSPI_CR_FTHRES_Msk (0x1FU << QUADSPI_CR_FTHRES_Pos) /*!< 0x00001F00 */ #define QUADSPI_CR_FTHRES QUADSPI_CR_FTHRES_Msk /*!< FTHRES[3:0] FIFO Level */ #define QUADSPI_CR_FTHRES_0 (0x01U << QUADSPI_CR_FTHRES_Pos) /*!< 0x00000100 */ #define QUADSPI_CR_FTHRES_1 (0x02U << QUADSPI_CR_FTHRES_Pos) /*!< 0x00000200 */ #define QUADSPI_CR_FTHRES_2 (0x04U << QUADSPI_CR_FTHRES_Pos) /*!< 0x00000400 */ #define QUADSPI_CR_FTHRES_3 (0x08U << QUADSPI_CR_FTHRES_Pos) /*!< 0x00000800 */ #define QUADSPI_CR_FTHRES_4 (0x10U << QUADSPI_CR_FTHRES_Pos) /*!< 0x00001000 */ #define QUADSPI_CR_TEIE_Pos (16U) #define QUADSPI_CR_TEIE_Msk (0x1U << QUADSPI_CR_TEIE_Pos) /*!< 0x00010000 */ #define QUADSPI_CR_TEIE QUADSPI_CR_TEIE_Msk /*!< Transfer Error Interrupt Enable */ #define QUADSPI_CR_TCIE_Pos (17U) #define QUADSPI_CR_TCIE_Msk (0x1U << QUADSPI_CR_TCIE_Pos) /*!< 0x00020000 */ #define QUADSPI_CR_TCIE QUADSPI_CR_TCIE_Msk /*!< Transfer Complete Interrupt Enable */ #define QUADSPI_CR_FTIE_Pos (18U) #define QUADSPI_CR_FTIE_Msk (0x1U << QUADSPI_CR_FTIE_Pos) /*!< 0x00040000 */ #define QUADSPI_CR_FTIE QUADSPI_CR_FTIE_Msk /*!< FIFO Threshold Interrupt Enable */ #define QUADSPI_CR_SMIE_Pos (19U) #define QUADSPI_CR_SMIE_Msk (0x1U << QUADSPI_CR_SMIE_Pos) /*!< 0x00080000 */ #define QUADSPI_CR_SMIE QUADSPI_CR_SMIE_Msk /*!< Status Match Interrupt Enable */ #define QUADSPI_CR_TOIE_Pos (20U) #define QUADSPI_CR_TOIE_Msk (0x1U << QUADSPI_CR_TOIE_Pos) /*!< 0x00100000 */ #define QUADSPI_CR_TOIE QUADSPI_CR_TOIE_Msk /*!< TimeOut Interrupt Enable */ #define QUADSPI_CR_APMS_Pos (22U) #define QUADSPI_CR_APMS_Msk (0x1U << QUADSPI_CR_APMS_Pos) /*!< 0x00400000 */ #define QUADSPI_CR_APMS QUADSPI_CR_APMS_Msk /*!< Bit 1 */ #define QUADSPI_CR_PMM_Pos (23U) #define QUADSPI_CR_PMM_Msk (0x1U << QUADSPI_CR_PMM_Pos) /*!< 0x00800000 */ #define QUADSPI_CR_PMM QUADSPI_CR_PMM_Msk /*!< Polling Match Mode */ #define QUADSPI_CR_PRESCALER_Pos (24U) #define QUADSPI_CR_PRESCALER_Msk (0xFFU << QUADSPI_CR_PRESCALER_Pos) /*!< 0xFF000000 */ #define QUADSPI_CR_PRESCALER QUADSPI_CR_PRESCALER_Msk /*!< PRESCALER[7:0] Clock prescaler */ #define QUADSPI_CR_PRESCALER_0 (0x01U << QUADSPI_CR_PRESCALER_Pos) /*!< 0x01000000 */ #define QUADSPI_CR_PRESCALER_1 (0x02U << QUADSPI_CR_PRESCALER_Pos) /*!< 0x02000000 */ #define QUADSPI_CR_PRESCALER_2 (0x04U << QUADSPI_CR_PRESCALER_Pos) /*!< 0x04000000 */ #define QUADSPI_CR_PRESCALER_3 (0x08U << QUADSPI_CR_PRESCALER_Pos) /*!< 0x08000000 */ #define QUADSPI_CR_PRESCALER_4 (0x10U << QUADSPI_CR_PRESCALER_Pos) /*!< 0x10000000 */ #define QUADSPI_CR_PRESCALER_5 (0x20U << QUADSPI_CR_PRESCALER_Pos) /*!< 0x20000000 */ #define QUADSPI_CR_PRESCALER_6 (0x40U << QUADSPI_CR_PRESCALER_Pos) /*!< 0x40000000 */ #define QUADSPI_CR_PRESCALER_7 (0x80U << QUADSPI_CR_PRESCALER_Pos) /*!< 0x80000000 */ /***************** Bit definition for QUADSPI_DCR register ******************/ #define QUADSPI_DCR_CKMODE_Pos (0U) #define QUADSPI_DCR_CKMODE_Msk (0x1U << QUADSPI_DCR_CKMODE_Pos) /*!< 0x00000001 */ #define QUADSPI_DCR_CKMODE QUADSPI_DCR_CKMODE_Msk /*!< Mode 0 / Mode 3 */ #define QUADSPI_DCR_CSHT_Pos (8U) #define QUADSPI_DCR_CSHT_Msk (0x7U << QUADSPI_DCR_CSHT_Pos) /*!< 0x00000700 */ #define QUADSPI_DCR_CSHT QUADSPI_DCR_CSHT_Msk /*!< CSHT[2:0]: ChipSelect High Time */ #define QUADSPI_DCR_CSHT_0 (0x1U << QUADSPI_DCR_CSHT_Pos) /*!< 0x00000100 */ #define QUADSPI_DCR_CSHT_1 (0x2U << QUADSPI_DCR_CSHT_Pos) /*!< 0x00000200 */ #define QUADSPI_DCR_CSHT_2 (0x4U << QUADSPI_DCR_CSHT_Pos) /*!< 0x00000400 */ #define QUADSPI_DCR_FSIZE_Pos (16U) #define QUADSPI_DCR_FSIZE_Msk (0x1FU << QUADSPI_DCR_FSIZE_Pos) /*!< 0x001F0000 */ #define QUADSPI_DCR_FSIZE QUADSPI_DCR_FSIZE_Msk /*!< FSIZE[4:0]: Flash Size */ #define QUADSPI_DCR_FSIZE_0 (0x01U << QUADSPI_DCR_FSIZE_Pos) /*!< 0x00010000 */ #define QUADSPI_DCR_FSIZE_1 (0x02U << QUADSPI_DCR_FSIZE_Pos) /*!< 0x00020000 */ #define QUADSPI_DCR_FSIZE_2 (0x04U << QUADSPI_DCR_FSIZE_Pos) /*!< 0x00040000 */ #define QUADSPI_DCR_FSIZE_3 (0x08U << QUADSPI_DCR_FSIZE_Pos) /*!< 0x00080000 */ #define QUADSPI_DCR_FSIZE_4 (0x10U << QUADSPI_DCR_FSIZE_Pos) /*!< 0x00100000 */ /****************** Bit definition for QUADSPI_SR register *******************/ #define QUADSPI_SR_TEF_Pos (0U) #define QUADSPI_SR_TEF_Msk (0x1U << QUADSPI_SR_TEF_Pos) /*!< 0x00000001 */ #define QUADSPI_SR_TEF QUADSPI_SR_TEF_Msk /*!< Transfer Error Flag */ #define QUADSPI_SR_TCF_Pos (1U) #define QUADSPI_SR_TCF_Msk (0x1U << QUADSPI_SR_TCF_Pos) /*!< 0x00000002 */ #define QUADSPI_SR_TCF QUADSPI_SR_TCF_Msk /*!< Transfer Complete Flag */ #define QUADSPI_SR_FTF_Pos (2U) #define QUADSPI_SR_FTF_Msk (0x1U << QUADSPI_SR_FTF_Pos) /*!< 0x00000004 */ #define QUADSPI_SR_FTF QUADSPI_SR_FTF_Msk /*!< FIFO Threshlod Flag */ #define QUADSPI_SR_SMF_Pos (3U) #define QUADSPI_SR_SMF_Msk (0x1U << QUADSPI_SR_SMF_Pos) /*!< 0x00000008 */ #define QUADSPI_SR_SMF QUADSPI_SR_SMF_Msk /*!< Status Match Flag */ #define QUADSPI_SR_TOF_Pos (4U) #define QUADSPI_SR_TOF_Msk (0x1U << QUADSPI_SR_TOF_Pos) /*!< 0x00000010 */ #define QUADSPI_SR_TOF QUADSPI_SR_TOF_Msk /*!< Timeout Flag */ #define QUADSPI_SR_BUSY_Pos (5U) #define QUADSPI_SR_BUSY_Msk (0x1U << QUADSPI_SR_BUSY_Pos) /*!< 0x00000020 */ #define QUADSPI_SR_BUSY QUADSPI_SR_BUSY_Msk /*!< Busy */ #define QUADSPI_SR_FLEVEL_Pos (8U) #define QUADSPI_SR_FLEVEL_Msk (0x3FU << QUADSPI_SR_FLEVEL_Pos) /*!< 0x00003F00 */ #define QUADSPI_SR_FLEVEL QUADSPI_SR_FLEVEL_Msk /*!< FIFO Threshlod Flag */ #define QUADSPI_SR_FLEVEL_0 (0x01U << QUADSPI_SR_FLEVEL_Pos) /*!< 0x00000100 */ #define QUADSPI_SR_FLEVEL_1 (0x02U << QUADSPI_SR_FLEVEL_Pos) /*!< 0x00000200 */ #define QUADSPI_SR_FLEVEL_2 (0x04U << QUADSPI_SR_FLEVEL_Pos) /*!< 0x00000400 */ #define QUADSPI_SR_FLEVEL_3 (0x08U << QUADSPI_SR_FLEVEL_Pos) /*!< 0x00000800 */ #define QUADSPI_SR_FLEVEL_4 (0x10U << QUADSPI_SR_FLEVEL_Pos) /*!< 0x00001000 */ #define QUADSPI_SR_FLEVEL_5 (0x20U << QUADSPI_SR_FLEVEL_Pos) /*!< 0x00002000 */ /****************** Bit definition for QUADSPI_FCR register ******************/ #define QUADSPI_FCR_CTEF_Pos (0U) #define QUADSPI_FCR_CTEF_Msk (0x1U << QUADSPI_FCR_CTEF_Pos) /*!< 0x00000001 */ #define QUADSPI_FCR_CTEF QUADSPI_FCR_CTEF_Msk /*!< Clear Transfer Error Flag */ #define QUADSPI_FCR_CTCF_Pos (1U) #define QUADSPI_FCR_CTCF_Msk (0x1U << QUADSPI_FCR_CTCF_Pos) /*!< 0x00000002 */ #define QUADSPI_FCR_CTCF QUADSPI_FCR_CTCF_Msk /*!< Clear Transfer Complete Flag */ #define QUADSPI_FCR_CSMF_Pos (3U) #define QUADSPI_FCR_CSMF_Msk (0x1U << QUADSPI_FCR_CSMF_Pos) /*!< 0x00000008 */ #define QUADSPI_FCR_CSMF QUADSPI_FCR_CSMF_Msk /*!< Clear Status Match Flag */ #define QUADSPI_FCR_CTOF_Pos (4U) #define QUADSPI_FCR_CTOF_Msk (0x1U << QUADSPI_FCR_CTOF_Pos) /*!< 0x00000010 */ #define QUADSPI_FCR_CTOF QUADSPI_FCR_CTOF_Msk /*!< Clear Timeout Flag */ /****************** Bit definition for QUADSPI_DLR register ******************/ #define QUADSPI_DLR_DL_Pos (0U) #define QUADSPI_DLR_DL_Msk (0xFFFFFFFFU << QUADSPI_DLR_DL_Pos) /*!< 0xFFFFFFFF */ #define QUADSPI_DLR_DL QUADSPI_DLR_DL_Msk /*!< DL[31:0]: Data Length */ /****************** Bit definition for QUADSPI_CCR register ******************/ #define QUADSPI_CCR_INSTRUCTION_Pos (0U) #define QUADSPI_CCR_INSTRUCTION_Msk (0xFFU << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x000000FF */ #define QUADSPI_CCR_INSTRUCTION QUADSPI_CCR_INSTRUCTION_Msk /*!< INSTRUCTION[7:0]: Instruction */ #define QUADSPI_CCR_INSTRUCTION_0 (0x01U << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000001 */ #define QUADSPI_CCR_INSTRUCTION_1 (0x02U << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000002 */ #define QUADSPI_CCR_INSTRUCTION_2 (0x04U << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000004 */ #define QUADSPI_CCR_INSTRUCTION_3 (0x08U << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000008 */ #define QUADSPI_CCR_INSTRUCTION_4 (0x10U << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000010 */ #define QUADSPI_CCR_INSTRUCTION_5 (0x20U << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000020 */ #define QUADSPI_CCR_INSTRUCTION_6 (0x40U << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000040 */ #define QUADSPI_CCR_INSTRUCTION_7 (0x80U << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000080 */ #define QUADSPI_CCR_IMODE_Pos (8U) #define QUADSPI_CCR_IMODE_Msk (0x3U << QUADSPI_CCR_IMODE_Pos) /*!< 0x00000300 */ #define QUADSPI_CCR_IMODE QUADSPI_CCR_IMODE_Msk /*!< IMODE[1:0]: Instruction Mode */ #define QUADSPI_CCR_IMODE_0 (0x1U << QUADSPI_CCR_IMODE_Pos) /*!< 0x00000100 */ #define QUADSPI_CCR_IMODE_1 (0x2U << QUADSPI_CCR_IMODE_Pos) /*!< 0x00000200 */ #define QUADSPI_CCR_ADMODE_Pos (10U) #define QUADSPI_CCR_ADMODE_Msk (0x3U << QUADSPI_CCR_ADMODE_Pos) /*!< 0x00000C00 */ #define QUADSPI_CCR_ADMODE QUADSPI_CCR_ADMODE_Msk /*!< ADMODE[1:0]: Address Mode */ #define QUADSPI_CCR_ADMODE_0 (0x1U << QUADSPI_CCR_ADMODE_Pos) /*!< 0x00000400 */ #define QUADSPI_CCR_ADMODE_1 (0x2U << QUADSPI_CCR_ADMODE_Pos) /*!< 0x00000800 */ #define QUADSPI_CCR_ADSIZE_Pos (12U) #define QUADSPI_CCR_ADSIZE_Msk (0x3U << QUADSPI_CCR_ADSIZE_Pos) /*!< 0x00003000 */ #define QUADSPI_CCR_ADSIZE QUADSPI_CCR_ADSIZE_Msk /*!< ADSIZE[1:0]: Address Size */ #define QUADSPI_CCR_ADSIZE_0 (0x1U << QUADSPI_CCR_ADSIZE_Pos) /*!< 0x00001000 */ #define QUADSPI_CCR_ADSIZE_1 (0x2U << QUADSPI_CCR_ADSIZE_Pos) /*!< 0x00002000 */ #define QUADSPI_CCR_ABMODE_Pos (14U) #define QUADSPI_CCR_ABMODE_Msk (0x3U << QUADSPI_CCR_ABMODE_Pos) /*!< 0x0000C000 */ #define QUADSPI_CCR_ABMODE QUADSPI_CCR_ABMODE_Msk /*!< ABMODE[1:0]: Alternate Bytes Mode */ #define QUADSPI_CCR_ABMODE_0 (0x1U << QUADSPI_CCR_ABMODE_Pos) /*!< 0x00004000 */ #define QUADSPI_CCR_ABMODE_1 (0x2U << QUADSPI_CCR_ABMODE_Pos) /*!< 0x00008000 */ #define QUADSPI_CCR_ABSIZE_Pos (16U) #define QUADSPI_CCR_ABSIZE_Msk (0x3U << QUADSPI_CCR_ABSIZE_Pos) /*!< 0x00030000 */ #define QUADSPI_CCR_ABSIZE QUADSPI_CCR_ABSIZE_Msk /*!< ABSIZE[1:0]: Instruction Mode */ #define QUADSPI_CCR_ABSIZE_0 (0x1U << QUADSPI_CCR_ABSIZE_Pos) /*!< 0x00010000 */ #define QUADSPI_CCR_ABSIZE_1 (0x2U << QUADSPI_CCR_ABSIZE_Pos) /*!< 0x00020000 */ #define QUADSPI_CCR_DCYC_Pos (18U) #define QUADSPI_CCR_DCYC_Msk (0x1FU << QUADSPI_CCR_DCYC_Pos) /*!< 0x007C0000 */ #define QUADSPI_CCR_DCYC QUADSPI_CCR_DCYC_Msk /*!< DCYC[4:0]: Dummy Cycles */ #define QUADSPI_CCR_DCYC_0 (0x01U << QUADSPI_CCR_DCYC_Pos) /*!< 0x00040000 */ #define QUADSPI_CCR_DCYC_1 (0x02U << QUADSPI_CCR_DCYC_Pos) /*!< 0x00080000 */ #define QUADSPI_CCR_DCYC_2 (0x04U << QUADSPI_CCR_DCYC_Pos) /*!< 0x00100000 */ #define QUADSPI_CCR_DCYC_3 (0x08U << QUADSPI_CCR_DCYC_Pos) /*!< 0x00200000 */ #define QUADSPI_CCR_DCYC_4 (0x10U << QUADSPI_CCR_DCYC_Pos) /*!< 0x00400000 */ #define QUADSPI_CCR_DMODE_Pos (24U) #define QUADSPI_CCR_DMODE_Msk (0x3U << QUADSPI_CCR_DMODE_Pos) /*!< 0x03000000 */ #define QUADSPI_CCR_DMODE QUADSPI_CCR_DMODE_Msk /*!< DMODE[1:0]: Data Mode */ #define QUADSPI_CCR_DMODE_0 (0x1U << QUADSPI_CCR_DMODE_Pos) /*!< 0x01000000 */ #define QUADSPI_CCR_DMODE_1 (0x2U << QUADSPI_CCR_DMODE_Pos) /*!< 0x02000000 */ #define QUADSPI_CCR_FMODE_Pos (26U) #define QUADSPI_CCR_FMODE_Msk (0x3U << QUADSPI_CCR_FMODE_Pos) /*!< 0x0C000000 */ #define QUADSPI_CCR_FMODE QUADSPI_CCR_FMODE_Msk /*!< FMODE[1:0]: Functional Mode */ #define QUADSPI_CCR_FMODE_0 (0x1U << QUADSPI_CCR_FMODE_Pos) /*!< 0x04000000 */ #define QUADSPI_CCR_FMODE_1 (0x2U << QUADSPI_CCR_FMODE_Pos) /*!< 0x08000000 */ #define QUADSPI_CCR_SIOO_Pos (28U) #define QUADSPI_CCR_SIOO_Msk (0x1U << QUADSPI_CCR_SIOO_Pos) /*!< 0x10000000 */ #define QUADSPI_CCR_SIOO QUADSPI_CCR_SIOO_Msk /*!< SIOO: Send Instruction Only Once Mode */ #define QUADSPI_CCR_DHHC_Pos (30U) #define QUADSPI_CCR_DHHC_Msk (0x1U << QUADSPI_CCR_DHHC_Pos) /*!< 0x40000000 */ #define QUADSPI_CCR_DHHC QUADSPI_CCR_DHHC_Msk /*!< DHHC: Delay Half Hclk Cycle */ #define QUADSPI_CCR_DDRM_Pos (31U) #define QUADSPI_CCR_DDRM_Msk (0x1U << QUADSPI_CCR_DDRM_Pos) /*!< 0x80000000 */ #define QUADSPI_CCR_DDRM QUADSPI_CCR_DDRM_Msk /*!< DDRM: Double Data Rate Mode */ /****************** Bit definition for QUADSPI_AR register *******************/ #define QUADSPI_AR_ADDRESS_Pos (0U) #define QUADSPI_AR_ADDRESS_Msk (0xFFFFFFFFU << QUADSPI_AR_ADDRESS_Pos) /*!< 0xFFFFFFFF */ #define QUADSPI_AR_ADDRESS QUADSPI_AR_ADDRESS_Msk /*!< ADDRESS[31:0]: Address */ /****************** Bit definition for QUADSPI_ABR register ******************/ #define QUADSPI_ABR_ALTERNATE_Pos (0U) #define QUADSPI_ABR_ALTERNATE_Msk (0xFFFFFFFFU << QUADSPI_ABR_ALTERNATE_Pos) /*!< 0xFFFFFFFF */ #define QUADSPI_ABR_ALTERNATE QUADSPI_ABR_ALTERNATE_Msk /*!< ALTERNATE[31:0]: Alternate Bytes */ /****************** Bit definition for QUADSPI_DR register *******************/ #define QUADSPI_DR_DATA_Pos (0U) #define QUADSPI_DR_DATA_Msk (0xFFFFFFFFU << QUADSPI_DR_DATA_Pos) /*!< 0xFFFFFFFF */ #define QUADSPI_DR_DATA QUADSPI_DR_DATA_Msk /*!< DATA[31:0]: Data */ /****************** Bit definition for QUADSPI_PSMKR register ****************/ #define QUADSPI_PSMKR_MASK_Pos (0U) #define QUADSPI_PSMKR_MASK_Msk (0xFFFFFFFFU << QUADSPI_PSMKR_MASK_Pos) /*!< 0xFFFFFFFF */ #define QUADSPI_PSMKR_MASK QUADSPI_PSMKR_MASK_Msk /*!< MASK[31:0]: Status Mask */ /****************** Bit definition for QUADSPI_PSMAR register ****************/ #define QUADSPI_PSMAR_MATCH_Pos (0U) #define QUADSPI_PSMAR_MATCH_Msk (0xFFFFFFFFU << QUADSPI_PSMAR_MATCH_Pos) /*!< 0xFFFFFFFF */ #define QUADSPI_PSMAR_MATCH QUADSPI_PSMAR_MATCH_Msk /*!< MATCH[31:0]: Status Match */ /****************** Bit definition for QUADSPI_PIR register *****************/ #define QUADSPI_PIR_INTERVAL_Pos (0U) #define QUADSPI_PIR_INTERVAL_Msk (0xFFFFU << QUADSPI_PIR_INTERVAL_Pos) /*!< 0x0000FFFF */ #define QUADSPI_PIR_INTERVAL QUADSPI_PIR_INTERVAL_Msk /*!< INTERVAL[15:0]: Polling Interval */ /****************** Bit definition for QUADSPI_LPTR register *****************/ #define QUADSPI_LPTR_TIMEOUT_Pos (0U) #define QUADSPI_LPTR_TIMEOUT_Msk (0xFFFFU << QUADSPI_LPTR_TIMEOUT_Pos) /*!< 0x0000FFFF */ #define QUADSPI_LPTR_TIMEOUT QUADSPI_LPTR_TIMEOUT_Msk /*!< TIMEOUT[15:0]: Timeout period */ /******************************************************************************/ /* */ /* Reset and Clock Control */ /* */ /******************************************************************************/ /******************** Bit definition for RCC_CR register ********************/ #define RCC_CR_HSION_Pos (0U) #define RCC_CR_HSION_Msk (0x1U << RCC_CR_HSION_Pos) /*!< 0x00000001 */ #define RCC_CR_HSION RCC_CR_HSION_Msk #define RCC_CR_HSIRDY_Pos (1U) #define RCC_CR_HSIRDY_Msk (0x1U << RCC_CR_HSIRDY_Pos) /*!< 0x00000002 */ #define RCC_CR_HSIRDY RCC_CR_HSIRDY_Msk #define RCC_CR_HSITRIM_Pos (3U) #define RCC_CR_HSITRIM_Msk (0x1FU << RCC_CR_HSITRIM_Pos) /*!< 0x000000F8 */ #define RCC_CR_HSITRIM RCC_CR_HSITRIM_Msk #define RCC_CR_HSITRIM_0 (0x01U << RCC_CR_HSITRIM_Pos) /*!< 0x00000008 */ #define RCC_CR_HSITRIM_1 (0x02U << RCC_CR_HSITRIM_Pos) /*!< 0x00000010 */ #define RCC_CR_HSITRIM_2 (0x04U << RCC_CR_HSITRIM_Pos) /*!< 0x00000020 */ #define RCC_CR_HSITRIM_3 (0x08U << RCC_CR_HSITRIM_Pos) /*!< 0x00000040 */ #define RCC_CR_HSITRIM_4 (0x10U << RCC_CR_HSITRIM_Pos) /*!< 0x00000080 */ #define RCC_CR_HSICAL_Pos (8U) #define RCC_CR_HSICAL_Msk (0xFFU << RCC_CR_HSICAL_Pos) /*!< 0x0000FF00 */ #define RCC_CR_HSICAL RCC_CR_HSICAL_Msk #define RCC_CR_HSICAL_0 (0x01U << RCC_CR_HSICAL_Pos) /*!< 0x00000100 */ #define RCC_CR_HSICAL_1 (0x02U << RCC_CR_HSICAL_Pos) /*!< 0x00000200 */ #define RCC_CR_HSICAL_2 (0x04U << RCC_CR_HSICAL_Pos) /*!< 0x00000400 */ #define RCC_CR_HSICAL_3 (0x08U << RCC_CR_HSICAL_Pos) /*!< 0x00000800 */ #define RCC_CR_HSICAL_4 (0x10U << RCC_CR_HSICAL_Pos) /*!< 0x00001000 */ #define RCC_CR_HSICAL_5 (0x20U << RCC_CR_HSICAL_Pos) /*!< 0x00002000 */ #define RCC_CR_HSICAL_6 (0x40U << RCC_CR_HSICAL_Pos) /*!< 0x00004000 */ #define RCC_CR_HSICAL_7 (0x80U << RCC_CR_HSICAL_Pos) /*!< 0x00008000 */ #define RCC_CR_HSEON_Pos (16U) #define RCC_CR_HSEON_Msk (0x1U << RCC_CR_HSEON_Pos) /*!< 0x00010000 */ #define RCC_CR_HSEON RCC_CR_HSEON_Msk #define RCC_CR_HSERDY_Pos (17U) #define RCC_CR_HSERDY_Msk (0x1U << RCC_CR_HSERDY_Pos) /*!< 0x00020000 */ #define RCC_CR_HSERDY RCC_CR_HSERDY_Msk #define RCC_CR_HSEBYP_Pos (18U) #define RCC_CR_HSEBYP_Msk (0x1U << RCC_CR_HSEBYP_Pos) /*!< 0x00040000 */ #define RCC_CR_HSEBYP RCC_CR_HSEBYP_Msk #define RCC_CR_CSSON_Pos (19U) #define RCC_CR_CSSON_Msk (0x1U << RCC_CR_CSSON_Pos) /*!< 0x00080000 */ #define RCC_CR_CSSON RCC_CR_CSSON_Msk #define RCC_CR_PLLON_Pos (24U) #define RCC_CR_PLLON_Msk (0x1U << RCC_CR_PLLON_Pos) /*!< 0x01000000 */ #define RCC_CR_PLLON RCC_CR_PLLON_Msk #define RCC_CR_PLLRDY_Pos (25U) #define RCC_CR_PLLRDY_Msk (0x1U << RCC_CR_PLLRDY_Pos) /*!< 0x02000000 */ #define RCC_CR_PLLRDY RCC_CR_PLLRDY_Msk /* * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie) */ #define RCC_PLLI2S_SUPPORT /*!< Support PLLI2S oscillator */ #define RCC_CR_PLLI2SON_Pos (26U) #define RCC_CR_PLLI2SON_Msk (0x1U << RCC_CR_PLLI2SON_Pos) /*!< 0x04000000 */ #define RCC_CR_PLLI2SON RCC_CR_PLLI2SON_Msk #define RCC_CR_PLLI2SRDY_Pos (27U) #define RCC_CR_PLLI2SRDY_Msk (0x1U << RCC_CR_PLLI2SRDY_Pos) /*!< 0x08000000 */ #define RCC_CR_PLLI2SRDY RCC_CR_PLLI2SRDY_Msk /* * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie) */ #define RCC_PLLSAI_SUPPORT /*!< Support PLLSAI oscillator */ #define RCC_CR_PLLSAION_Pos (28U) #define RCC_CR_PLLSAION_Msk (0x1U << RCC_CR_PLLSAION_Pos) /*!< 0x10000000 */ #define RCC_CR_PLLSAION RCC_CR_PLLSAION_Msk #define RCC_CR_PLLSAIRDY_Pos (29U) #define RCC_CR_PLLSAIRDY_Msk (0x1U << RCC_CR_PLLSAIRDY_Pos) /*!< 0x20000000 */ #define RCC_CR_PLLSAIRDY RCC_CR_PLLSAIRDY_Msk /******************** Bit definition for RCC_PLLCFGR register ***************/ #define RCC_PLLCFGR_PLLM_Pos (0U) #define RCC_PLLCFGR_PLLM_Msk (0x3FU << RCC_PLLCFGR_PLLM_Pos) /*!< 0x0000003F */ #define RCC_PLLCFGR_PLLM RCC_PLLCFGR_PLLM_Msk #define RCC_PLLCFGR_PLLM_0 (0x01U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000001 */ #define RCC_PLLCFGR_PLLM_1 (0x02U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000002 */ #define RCC_PLLCFGR_PLLM_2 (0x04U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000004 */ #define RCC_PLLCFGR_PLLM_3 (0x08U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000008 */ #define RCC_PLLCFGR_PLLM_4 (0x10U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000010 */ #define RCC_PLLCFGR_PLLM_5 (0x20U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000020 */ #define RCC_PLLCFGR_PLLN_Pos (6U) #define RCC_PLLCFGR_PLLN_Msk (0x1FFU << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00007FC0 */ #define RCC_PLLCFGR_PLLN RCC_PLLCFGR_PLLN_Msk #define RCC_PLLCFGR_PLLN_0 (0x001U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000040 */ #define RCC_PLLCFGR_PLLN_1 (0x002U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000080 */ #define RCC_PLLCFGR_PLLN_2 (0x004U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000100 */ #define RCC_PLLCFGR_PLLN_3 (0x008U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000200 */ #define RCC_PLLCFGR_PLLN_4 (0x010U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000400 */ #define RCC_PLLCFGR_PLLN_5 (0x020U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000800 */ #define RCC_PLLCFGR_PLLN_6 (0x040U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00001000 */ #define RCC_PLLCFGR_PLLN_7 (0x080U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00002000 */ #define RCC_PLLCFGR_PLLN_8 (0x100U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00004000 */ #define RCC_PLLCFGR_PLLP_Pos (16U) #define RCC_PLLCFGR_PLLP_Msk (0x3U << RCC_PLLCFGR_PLLP_Pos) /*!< 0x00030000 */ #define RCC_PLLCFGR_PLLP RCC_PLLCFGR_PLLP_Msk #define RCC_PLLCFGR_PLLP_0 (0x1U << RCC_PLLCFGR_PLLP_Pos) /*!< 0x00010000 */ #define RCC_PLLCFGR_PLLP_1 (0x2U << RCC_PLLCFGR_PLLP_Pos) /*!< 0x00020000 */ #define RCC_PLLCFGR_PLLSRC_Pos (22U) #define RCC_PLLCFGR_PLLSRC_Msk (0x1U << RCC_PLLCFGR_PLLSRC_Pos) /*!< 0x00400000 */ #define RCC_PLLCFGR_PLLSRC RCC_PLLCFGR_PLLSRC_Msk #define RCC_PLLCFGR_PLLSRC_HSE_Pos (22U) #define RCC_PLLCFGR_PLLSRC_HSE_Msk (0x1U << RCC_PLLCFGR_PLLSRC_HSE_Pos) /*!< 0x00400000 */ #define RCC_PLLCFGR_PLLSRC_HSE RCC_PLLCFGR_PLLSRC_HSE_Msk #define RCC_PLLCFGR_PLLSRC_HSI 0x00000000U #define RCC_PLLCFGR_PLLQ_Pos (24U) #define RCC_PLLCFGR_PLLQ_Msk (0xFU << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x0F000000 */ #define RCC_PLLCFGR_PLLQ RCC_PLLCFGR_PLLQ_Msk #define RCC_PLLCFGR_PLLQ_0 (0x1U << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x01000000 */ #define RCC_PLLCFGR_PLLQ_1 (0x2U << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x02000000 */ #define RCC_PLLCFGR_PLLQ_2 (0x4U << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x04000000 */ #define RCC_PLLCFGR_PLLQ_3 (0x8U << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x08000000 */ #define RCC_PLLCFGR_PLLR_Pos (28U) #define RCC_PLLCFGR_PLLR_Msk (0x7U << RCC_PLLCFGR_PLLR_Pos) /*!< 0x70000000 */ #define RCC_PLLCFGR_PLLR RCC_PLLCFGR_PLLR_Msk #define RCC_PLLCFGR_PLLR_0 (0x1U << RCC_PLLCFGR_PLLR_Pos) /*!< 0x10000000 */ #define RCC_PLLCFGR_PLLR_1 (0x2U << RCC_PLLCFGR_PLLR_Pos) /*!< 0x20000000 */ #define RCC_PLLCFGR_PLLR_2 (0x4U << RCC_PLLCFGR_PLLR_Pos) /*!< 0x40000000 */ /******************** Bit definition for RCC_CFGR register ******************/ /*!< SW configuration */ #define RCC_CFGR_SW_Pos (0U) #define RCC_CFGR_SW_Msk (0x3U << RCC_CFGR_SW_Pos) /*!< 0x00000003 */ #define RCC_CFGR_SW RCC_CFGR_SW_Msk /*!< SW[1:0] bits (System clock Switch) */ #define RCC_CFGR_SW_0 (0x1U << RCC_CFGR_SW_Pos) /*!< 0x00000001 */ #define RCC_CFGR_SW_1 (0x2U << RCC_CFGR_SW_Pos) /*!< 0x00000002 */ #define RCC_CFGR_SW_HSI 0x00000000U /*!< HSI selected as system clock */ #define RCC_CFGR_SW_HSE 0x00000001U /*!< HSE selected as system clock */ #define RCC_CFGR_SW_PLL 0x00000002U /*!< PLL selected as system clock */ /*!< SWS configuration */ #define RCC_CFGR_SWS_Pos (2U) #define RCC_CFGR_SWS_Msk (0x3U << RCC_CFGR_SWS_Pos) /*!< 0x0000000C */ #define RCC_CFGR_SWS RCC_CFGR_SWS_Msk /*!< SWS[1:0] bits (System Clock Switch Status) */ #define RCC_CFGR_SWS_0 (0x1U << RCC_CFGR_SWS_Pos) /*!< 0x00000004 */ #define RCC_CFGR_SWS_1 (0x2U << RCC_CFGR_SWS_Pos) /*!< 0x00000008 */ #define RCC_CFGR_SWS_HSI 0x00000000U /*!< HSI oscillator used as system clock */ #define RCC_CFGR_SWS_HSE 0x00000004U /*!< HSE oscillator used as system clock */ #define RCC_CFGR_SWS_PLL 0x00000008U /*!< PLL used as system clock */ /*!< HPRE configuration */ #define RCC_CFGR_HPRE_Pos (4U) #define RCC_CFGR_HPRE_Msk (0xFU << RCC_CFGR_HPRE_Pos) /*!< 0x000000F0 */ #define RCC_CFGR_HPRE RCC_CFGR_HPRE_Msk /*!< HPRE[3:0] bits (AHB prescaler) */ #define RCC_CFGR_HPRE_0 (0x1U << RCC_CFGR_HPRE_Pos) /*!< 0x00000010 */ #define RCC_CFGR_HPRE_1 (0x2U << RCC_CFGR_HPRE_Pos) /*!< 0x00000020 */ #define RCC_CFGR_HPRE_2 (0x4U << RCC_CFGR_HPRE_Pos) /*!< 0x00000040 */ #define RCC_CFGR_HPRE_3 (0x8U << RCC_CFGR_HPRE_Pos) /*!< 0x00000080 */ #define RCC_CFGR_HPRE_DIV1 0x00000000U /*!< SYSCLK not divided */ #define RCC_CFGR_HPRE_DIV2 0x00000080U /*!< SYSCLK divided by 2 */ #define RCC_CFGR_HPRE_DIV4 0x00000090U /*!< SYSCLK divided by 4 */ #define RCC_CFGR_HPRE_DIV8 0x000000A0U /*!< SYSCLK divided by 8 */ #define RCC_CFGR_HPRE_DIV16 0x000000B0U /*!< SYSCLK divided by 16 */ #define RCC_CFGR_HPRE_DIV64 0x000000C0U /*!< SYSCLK divided by 64 */ #define RCC_CFGR_HPRE_DIV128 0x000000D0U /*!< SYSCLK divided by 128 */ #define RCC_CFGR_HPRE_DIV256 0x000000E0U /*!< SYSCLK divided by 256 */ #define RCC_CFGR_HPRE_DIV512 0x000000F0U /*!< SYSCLK divided by 512 */ /*!< PPRE1 configuration */ #define RCC_CFGR_PPRE1_Pos (10U) #define RCC_CFGR_PPRE1_Msk (0x7U << RCC_CFGR_PPRE1_Pos) /*!< 0x00001C00 */ #define RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_Msk /*!< PRE1[2:0] bits (APB1 prescaler) */ #define RCC_CFGR_PPRE1_0 (0x1U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000400 */ #define RCC_CFGR_PPRE1_1 (0x2U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000800 */ #define RCC_CFGR_PPRE1_2 (0x4U << RCC_CFGR_PPRE1_Pos) /*!< 0x00001000 */ #define RCC_CFGR_PPRE1_DIV1 0x00000000U /*!< HCLK not divided */ #define RCC_CFGR_PPRE1_DIV2 0x00001000U /*!< HCLK divided by 2 */ #define RCC_CFGR_PPRE1_DIV4 0x00001400U /*!< HCLK divided by 4 */ #define RCC_CFGR_PPRE1_DIV8 0x00001800U /*!< HCLK divided by 8 */ #define RCC_CFGR_PPRE1_DIV16 0x00001C00U /*!< HCLK divided by 16 */ /*!< PPRE2 configuration */ #define RCC_CFGR_PPRE2_Pos (13U) #define RCC_CFGR_PPRE2_Msk (0x7U << RCC_CFGR_PPRE2_Pos) /*!< 0x0000E000 */ #define RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_Msk /*!< PRE2[2:0] bits (APB2 prescaler) */ #define RCC_CFGR_PPRE2_0 (0x1U << RCC_CFGR_PPRE2_Pos) /*!< 0x00002000 */ #define RCC_CFGR_PPRE2_1 (0x2U << RCC_CFGR_PPRE2_Pos) /*!< 0x00004000 */ #define RCC_CFGR_PPRE2_2 (0x4U << RCC_CFGR_PPRE2_Pos) /*!< 0x00008000 */ #define RCC_CFGR_PPRE2_DIV1 0x00000000U /*!< HCLK not divided */ #define RCC_CFGR_PPRE2_DIV2 0x00008000U /*!< HCLK divided by 2 */ #define RCC_CFGR_PPRE2_DIV4 0x0000A000U /*!< HCLK divided by 4 */ #define RCC_CFGR_PPRE2_DIV8 0x0000C000U /*!< HCLK divided by 8 */ #define RCC_CFGR_PPRE2_DIV16 0x0000E000U /*!< HCLK divided by 16 */ /*!< RTCPRE configuration */ #define RCC_CFGR_RTCPRE_Pos (16U) #define RCC_CFGR_RTCPRE_Msk (0x1FU << RCC_CFGR_RTCPRE_Pos) /*!< 0x001F0000 */ #define RCC_CFGR_RTCPRE RCC_CFGR_RTCPRE_Msk #define RCC_CFGR_RTCPRE_0 (0x01U << RCC_CFGR_RTCPRE_Pos) /*!< 0x00010000 */ #define RCC_CFGR_RTCPRE_1 (0x02U << RCC_CFGR_RTCPRE_Pos) /*!< 0x00020000 */ #define RCC_CFGR_RTCPRE_2 (0x04U << RCC_CFGR_RTCPRE_Pos) /*!< 0x00040000 */ #define RCC_CFGR_RTCPRE_3 (0x08U << RCC_CFGR_RTCPRE_Pos) /*!< 0x00080000 */ #define RCC_CFGR_RTCPRE_4 (0x10U << RCC_CFGR_RTCPRE_Pos) /*!< 0x00100000 */ /*!< MCO1 configuration */ #define RCC_CFGR_MCO1_Pos (21U) #define RCC_CFGR_MCO1_Msk (0x3U << RCC_CFGR_MCO1_Pos) /*!< 0x00600000 */ #define RCC_CFGR_MCO1 RCC_CFGR_MCO1_Msk #define RCC_CFGR_MCO1_0 (0x1U << RCC_CFGR_MCO1_Pos) /*!< 0x00200000 */ #define RCC_CFGR_MCO1_1 (0x2U << RCC_CFGR_MCO1_Pos) /*!< 0x00400000 */ #define RCC_CFGR_I2SSRC_Pos (23U) #define RCC_CFGR_I2SSRC_Msk (0x1U << RCC_CFGR_I2SSRC_Pos) /*!< 0x00800000 */ #define RCC_CFGR_I2SSRC RCC_CFGR_I2SSRC_Msk #define RCC_CFGR_MCO1PRE_Pos (24U) #define RCC_CFGR_MCO1PRE_Msk (0x7U << RCC_CFGR_MCO1PRE_Pos) /*!< 0x07000000 */ #define RCC_CFGR_MCO1PRE RCC_CFGR_MCO1PRE_Msk #define RCC_CFGR_MCO1PRE_0 (0x1U << RCC_CFGR_MCO1PRE_Pos) /*!< 0x01000000 */ #define RCC_CFGR_MCO1PRE_1 (0x2U << RCC_CFGR_MCO1PRE_Pos) /*!< 0x02000000 */ #define RCC_CFGR_MCO1PRE_2 (0x4U << RCC_CFGR_MCO1PRE_Pos) /*!< 0x04000000 */ #define RCC_CFGR_MCO2PRE_Pos (27U) #define RCC_CFGR_MCO2PRE_Msk (0x7U << RCC_CFGR_MCO2PRE_Pos) /*!< 0x38000000 */ #define RCC_CFGR_MCO2PRE RCC_CFGR_MCO2PRE_Msk #define RCC_CFGR_MCO2PRE_0 (0x1U << RCC_CFGR_MCO2PRE_Pos) /*!< 0x08000000 */ #define RCC_CFGR_MCO2PRE_1 (0x2U << RCC_CFGR_MCO2PRE_Pos) /*!< 0x10000000 */ #define RCC_CFGR_MCO2PRE_2 (0x4U << RCC_CFGR_MCO2PRE_Pos) /*!< 0x20000000 */ #define RCC_CFGR_MCO2_Pos (30U) #define RCC_CFGR_MCO2_Msk (0x3U << RCC_CFGR_MCO2_Pos) /*!< 0xC0000000 */ #define RCC_CFGR_MCO2 RCC_CFGR_MCO2_Msk #define RCC_CFGR_MCO2_0 (0x1U << RCC_CFGR_MCO2_Pos) /*!< 0x40000000 */ #define RCC_CFGR_MCO2_1 (0x2U << RCC_CFGR_MCO2_Pos) /*!< 0x80000000 */ /******************** Bit definition for RCC_CIR register *******************/ #define RCC_CIR_LSIRDYF_Pos (0U) #define RCC_CIR_LSIRDYF_Msk (0x1U << RCC_CIR_LSIRDYF_Pos) /*!< 0x00000001 */ #define RCC_CIR_LSIRDYF RCC_CIR_LSIRDYF_Msk #define RCC_CIR_LSERDYF_Pos (1U) #define RCC_CIR_LSERDYF_Msk (0x1U << RCC_CIR_LSERDYF_Pos) /*!< 0x00000002 */ #define RCC_CIR_LSERDYF RCC_CIR_LSERDYF_Msk #define RCC_CIR_HSIRDYF_Pos (2U) #define RCC_CIR_HSIRDYF_Msk (0x1U << RCC_CIR_HSIRDYF_Pos) /*!< 0x00000004 */ #define RCC_CIR_HSIRDYF RCC_CIR_HSIRDYF_Msk #define RCC_CIR_HSERDYF_Pos (3U) #define RCC_CIR_HSERDYF_Msk (0x1U << RCC_CIR_HSERDYF_Pos) /*!< 0x00000008 */ #define RCC_CIR_HSERDYF RCC_CIR_HSERDYF_Msk #define RCC_CIR_PLLRDYF_Pos (4U) #define RCC_CIR_PLLRDYF_Msk (0x1U << RCC_CIR_PLLRDYF_Pos) /*!< 0x00000010 */ #define RCC_CIR_PLLRDYF RCC_CIR_PLLRDYF_Msk #define RCC_CIR_PLLI2SRDYF_Pos (5U) #define RCC_CIR_PLLI2SRDYF_Msk (0x1U << RCC_CIR_PLLI2SRDYF_Pos) /*!< 0x00000020 */ #define RCC_CIR_PLLI2SRDYF RCC_CIR_PLLI2SRDYF_Msk #define RCC_CIR_PLLSAIRDYF_Pos (6U) #define RCC_CIR_PLLSAIRDYF_Msk (0x1U << RCC_CIR_PLLSAIRDYF_Pos) /*!< 0x00000040 */ #define RCC_CIR_PLLSAIRDYF RCC_CIR_PLLSAIRDYF_Msk #define RCC_CIR_CSSF_Pos (7U) #define RCC_CIR_CSSF_Msk (0x1U << RCC_CIR_CSSF_Pos) /*!< 0x00000080 */ #define RCC_CIR_CSSF RCC_CIR_CSSF_Msk #define RCC_CIR_LSIRDYIE_Pos (8U) #define RCC_CIR_LSIRDYIE_Msk (0x1U << RCC_CIR_LSIRDYIE_Pos) /*!< 0x00000100 */ #define RCC_CIR_LSIRDYIE RCC_CIR_LSIRDYIE_Msk #define RCC_CIR_LSERDYIE_Pos (9U) #define RCC_CIR_LSERDYIE_Msk (0x1U << RCC_CIR_LSERDYIE_Pos) /*!< 0x00000200 */ #define RCC_CIR_LSERDYIE RCC_CIR_LSERDYIE_Msk #define RCC_CIR_HSIRDYIE_Pos (10U) #define RCC_CIR_HSIRDYIE_Msk (0x1U << RCC_CIR_HSIRDYIE_Pos) /*!< 0x00000400 */ #define RCC_CIR_HSIRDYIE RCC_CIR_HSIRDYIE_Msk #define RCC_CIR_HSERDYIE_Pos (11U) #define RCC_CIR_HSERDYIE_Msk (0x1U << RCC_CIR_HSERDYIE_Pos) /*!< 0x00000800 */ #define RCC_CIR_HSERDYIE RCC_CIR_HSERDYIE_Msk #define RCC_CIR_PLLRDYIE_Pos (12U) #define RCC_CIR_PLLRDYIE_Msk (0x1U << RCC_CIR_PLLRDYIE_Pos) /*!< 0x00001000 */ #define RCC_CIR_PLLRDYIE RCC_CIR_PLLRDYIE_Msk #define RCC_CIR_PLLI2SRDYIE_Pos (13U) #define RCC_CIR_PLLI2SRDYIE_Msk (0x1U << RCC_CIR_PLLI2SRDYIE_Pos) /*!< 0x00002000 */ #define RCC_CIR_PLLI2SRDYIE RCC_CIR_PLLI2SRDYIE_Msk #define RCC_CIR_PLLSAIRDYIE_Pos (14U) #define RCC_CIR_PLLSAIRDYIE_Msk (0x1U << RCC_CIR_PLLSAIRDYIE_Pos) /*!< 0x00004000 */ #define RCC_CIR_PLLSAIRDYIE RCC_CIR_PLLSAIRDYIE_Msk #define RCC_CIR_LSIRDYC_Pos (16U) #define RCC_CIR_LSIRDYC_Msk (0x1U << RCC_CIR_LSIRDYC_Pos) /*!< 0x00010000 */ #define RCC_CIR_LSIRDYC RCC_CIR_LSIRDYC_Msk #define RCC_CIR_LSERDYC_Pos (17U) #define RCC_CIR_LSERDYC_Msk (0x1U << RCC_CIR_LSERDYC_Pos) /*!< 0x00020000 */ #define RCC_CIR_LSERDYC RCC_CIR_LSERDYC_Msk #define RCC_CIR_HSIRDYC_Pos (18U) #define RCC_CIR_HSIRDYC_Msk (0x1U << RCC_CIR_HSIRDYC_Pos) /*!< 0x00040000 */ #define RCC_CIR_HSIRDYC RCC_CIR_HSIRDYC_Msk #define RCC_CIR_HSERDYC_Pos (19U) #define RCC_CIR_HSERDYC_Msk (0x1U << RCC_CIR_HSERDYC_Pos) /*!< 0x00080000 */ #define RCC_CIR_HSERDYC RCC_CIR_HSERDYC_Msk #define RCC_CIR_PLLRDYC_Pos (20U) #define RCC_CIR_PLLRDYC_Msk (0x1U << RCC_CIR_PLLRDYC_Pos) /*!< 0x00100000 */ #define RCC_CIR_PLLRDYC RCC_CIR_PLLRDYC_Msk #define RCC_CIR_PLLI2SRDYC_Pos (21U) #define RCC_CIR_PLLI2SRDYC_Msk (0x1U << RCC_CIR_PLLI2SRDYC_Pos) /*!< 0x00200000 */ #define RCC_CIR_PLLI2SRDYC RCC_CIR_PLLI2SRDYC_Msk #define RCC_CIR_PLLSAIRDYC_Pos (22U) #define RCC_CIR_PLLSAIRDYC_Msk (0x1U << RCC_CIR_PLLSAIRDYC_Pos) /*!< 0x00400000 */ #define RCC_CIR_PLLSAIRDYC RCC_CIR_PLLSAIRDYC_Msk #define RCC_CIR_CSSC_Pos (23U) #define RCC_CIR_CSSC_Msk (0x1U << RCC_CIR_CSSC_Pos) /*!< 0x00800000 */ #define RCC_CIR_CSSC RCC_CIR_CSSC_Msk /******************** Bit definition for RCC_AHB1RSTR register **************/ #define RCC_AHB1RSTR_GPIOARST_Pos (0U) #define RCC_AHB1RSTR_GPIOARST_Msk (0x1U << RCC_AHB1RSTR_GPIOARST_Pos) /*!< 0x00000001 */ #define RCC_AHB1RSTR_GPIOARST RCC_AHB1RSTR_GPIOARST_Msk #define RCC_AHB1RSTR_GPIOBRST_Pos (1U) #define RCC_AHB1RSTR_GPIOBRST_Msk (0x1U << RCC_AHB1RSTR_GPIOBRST_Pos) /*!< 0x00000002 */ #define RCC_AHB1RSTR_GPIOBRST RCC_AHB1RSTR_GPIOBRST_Msk #define RCC_AHB1RSTR_GPIOCRST_Pos (2U) #define RCC_AHB1RSTR_GPIOCRST_Msk (0x1U << RCC_AHB1RSTR_GPIOCRST_Pos) /*!< 0x00000004 */ #define RCC_AHB1RSTR_GPIOCRST RCC_AHB1RSTR_GPIOCRST_Msk #define RCC_AHB1RSTR_GPIODRST_Pos (3U) #define RCC_AHB1RSTR_GPIODRST_Msk (0x1U << RCC_AHB1RSTR_GPIODRST_Pos) /*!< 0x00000008 */ #define RCC_AHB1RSTR_GPIODRST RCC_AHB1RSTR_GPIODRST_Msk #define RCC_AHB1RSTR_GPIOERST_Pos (4U) #define RCC_AHB1RSTR_GPIOERST_Msk (0x1U << RCC_AHB1RSTR_GPIOERST_Pos) /*!< 0x00000010 */ #define RCC_AHB1RSTR_GPIOERST RCC_AHB1RSTR_GPIOERST_Msk #define RCC_AHB1RSTR_GPIOFRST_Pos (5U) #define RCC_AHB1RSTR_GPIOFRST_Msk (0x1U << RCC_AHB1RSTR_GPIOFRST_Pos) /*!< 0x00000020 */ #define RCC_AHB1RSTR_GPIOFRST RCC_AHB1RSTR_GPIOFRST_Msk #define RCC_AHB1RSTR_GPIOGRST_Pos (6U) #define RCC_AHB1RSTR_GPIOGRST_Msk (0x1U << RCC_AHB1RSTR_GPIOGRST_Pos) /*!< 0x00000040 */ #define RCC_AHB1RSTR_GPIOGRST RCC_AHB1RSTR_GPIOGRST_Msk #define RCC_AHB1RSTR_GPIOHRST_Pos (7U) #define RCC_AHB1RSTR_GPIOHRST_Msk (0x1U << RCC_AHB1RSTR_GPIOHRST_Pos) /*!< 0x00000080 */ #define RCC_AHB1RSTR_GPIOHRST RCC_AHB1RSTR_GPIOHRST_Msk #define RCC_AHB1RSTR_GPIOIRST_Pos (8U) #define RCC_AHB1RSTR_GPIOIRST_Msk (0x1U << RCC_AHB1RSTR_GPIOIRST_Pos) /*!< 0x00000100 */ #define RCC_AHB1RSTR_GPIOIRST RCC_AHB1RSTR_GPIOIRST_Msk #define RCC_AHB1RSTR_GPIOJRST_Pos (9U) #define RCC_AHB1RSTR_GPIOJRST_Msk (0x1U << RCC_AHB1RSTR_GPIOJRST_Pos) /*!< 0x00000200 */ #define RCC_AHB1RSTR_GPIOJRST RCC_AHB1RSTR_GPIOJRST_Msk #define RCC_AHB1RSTR_GPIOKRST_Pos (10U) #define RCC_AHB1RSTR_GPIOKRST_Msk (0x1U << RCC_AHB1RSTR_GPIOKRST_Pos) /*!< 0x00000400 */ #define RCC_AHB1RSTR_GPIOKRST RCC_AHB1RSTR_GPIOKRST_Msk #define RCC_AHB1RSTR_CRCRST_Pos (12U) #define RCC_AHB1RSTR_CRCRST_Msk (0x1U << RCC_AHB1RSTR_CRCRST_Pos) /*!< 0x00001000 */ #define RCC_AHB1RSTR_CRCRST RCC_AHB1RSTR_CRCRST_Msk #define RCC_AHB1RSTR_DMA1RST_Pos (21U) #define RCC_AHB1RSTR_DMA1RST_Msk (0x1U << RCC_AHB1RSTR_DMA1RST_Pos) /*!< 0x00200000 */ #define RCC_AHB1RSTR_DMA1RST RCC_AHB1RSTR_DMA1RST_Msk #define RCC_AHB1RSTR_DMA2RST_Pos (22U) #define RCC_AHB1RSTR_DMA2RST_Msk (0x1U << RCC_AHB1RSTR_DMA2RST_Pos) /*!< 0x00400000 */ #define RCC_AHB1RSTR_DMA2RST RCC_AHB1RSTR_DMA2RST_Msk #define RCC_AHB1RSTR_DMA2DRST_Pos (23U) #define RCC_AHB1RSTR_DMA2DRST_Msk (0x1U << RCC_AHB1RSTR_DMA2DRST_Pos) /*!< 0x00800000 */ #define RCC_AHB1RSTR_DMA2DRST RCC_AHB1RSTR_DMA2DRST_Msk #define RCC_AHB1RSTR_ETHMACRST_Pos (25U) #define RCC_AHB1RSTR_ETHMACRST_Msk (0x1U << RCC_AHB1RSTR_ETHMACRST_Pos) /*!< 0x02000000 */ #define RCC_AHB1RSTR_ETHMACRST RCC_AHB1RSTR_ETHMACRST_Msk #define RCC_AHB1RSTR_OTGHRST_Pos (29U) #define RCC_AHB1RSTR_OTGHRST_Msk (0x1U << RCC_AHB1RSTR_OTGHRST_Pos) /*!< 0x20000000 */ #define RCC_AHB1RSTR_OTGHRST RCC_AHB1RSTR_OTGHRST_Msk /******************** Bit definition for RCC_AHB2RSTR register **************/ #define RCC_AHB2RSTR_DCMIRST_Pos (0U) #define RCC_AHB2RSTR_DCMIRST_Msk (0x1U << RCC_AHB2RSTR_DCMIRST_Pos) /*!< 0x00000001 */ #define RCC_AHB2RSTR_DCMIRST RCC_AHB2RSTR_DCMIRST_Msk #define RCC_AHB2RSTR_RNGRST_Pos (6U) #define RCC_AHB2RSTR_RNGRST_Msk (0x1U << RCC_AHB2RSTR_RNGRST_Pos) /*!< 0x00000040 */ #define RCC_AHB2RSTR_RNGRST RCC_AHB2RSTR_RNGRST_Msk #define RCC_AHB2RSTR_OTGFSRST_Pos (7U) #define RCC_AHB2RSTR_OTGFSRST_Msk (0x1U << RCC_AHB2RSTR_OTGFSRST_Pos) /*!< 0x00000080 */ #define RCC_AHB2RSTR_OTGFSRST RCC_AHB2RSTR_OTGFSRST_Msk /******************** Bit definition for RCC_AHB3RSTR register **************/ #define RCC_AHB3RSTR_FMCRST_Pos (0U) #define RCC_AHB3RSTR_FMCRST_Msk (0x1U << RCC_AHB3RSTR_FMCRST_Pos) /*!< 0x00000001 */ #define RCC_AHB3RSTR_FMCRST RCC_AHB3RSTR_FMCRST_Msk #define RCC_AHB3RSTR_QSPIRST_Pos (1U) #define RCC_AHB3RSTR_QSPIRST_Msk (0x1U << RCC_AHB3RSTR_QSPIRST_Pos) /*!< 0x00000002 */ #define RCC_AHB3RSTR_QSPIRST RCC_AHB3RSTR_QSPIRST_Msk /******************** Bit definition for RCC_APB1RSTR register **************/ #define RCC_APB1RSTR_TIM2RST_Pos (0U) #define RCC_APB1RSTR_TIM2RST_Msk (0x1U << RCC_APB1RSTR_TIM2RST_Pos) /*!< 0x00000001 */ #define RCC_APB1RSTR_TIM2RST RCC_APB1RSTR_TIM2RST_Msk #define RCC_APB1RSTR_TIM3RST_Pos (1U) #define RCC_APB1RSTR_TIM3RST_Msk (0x1U << RCC_APB1RSTR_TIM3RST_Pos) /*!< 0x00000002 */ #define RCC_APB1RSTR_TIM3RST RCC_APB1RSTR_TIM3RST_Msk #define RCC_APB1RSTR_TIM4RST_Pos (2U) #define RCC_APB1RSTR_TIM4RST_Msk (0x1U << RCC_APB1RSTR_TIM4RST_Pos) /*!< 0x00000004 */ #define RCC_APB1RSTR_TIM4RST RCC_APB1RSTR_TIM4RST_Msk #define RCC_APB1RSTR_TIM5RST_Pos (3U) #define RCC_APB1RSTR_TIM5RST_Msk (0x1U << RCC_APB1RSTR_TIM5RST_Pos) /*!< 0x00000008 */ #define RCC_APB1RSTR_TIM5RST RCC_APB1RSTR_TIM5RST_Msk #define RCC_APB1RSTR_TIM6RST_Pos (4U) #define RCC_APB1RSTR_TIM6RST_Msk (0x1U << RCC_APB1RSTR_TIM6RST_Pos) /*!< 0x00000010 */ #define RCC_APB1RSTR_TIM6RST RCC_APB1RSTR_TIM6RST_Msk #define RCC_APB1RSTR_TIM7RST_Pos (5U) #define RCC_APB1RSTR_TIM7RST_Msk (0x1U << RCC_APB1RSTR_TIM7RST_Pos) /*!< 0x00000020 */ #define RCC_APB1RSTR_TIM7RST RCC_APB1RSTR_TIM7RST_Msk #define RCC_APB1RSTR_TIM12RST_Pos (6U) #define RCC_APB1RSTR_TIM12RST_Msk (0x1U << RCC_APB1RSTR_TIM12RST_Pos) /*!< 0x00000040 */ #define RCC_APB1RSTR_TIM12RST RCC_APB1RSTR_TIM12RST_Msk #define RCC_APB1RSTR_TIM13RST_Pos (7U) #define RCC_APB1RSTR_TIM13RST_Msk (0x1U << RCC_APB1RSTR_TIM13RST_Pos) /*!< 0x00000080 */ #define RCC_APB1RSTR_TIM13RST RCC_APB1RSTR_TIM13RST_Msk #define RCC_APB1RSTR_TIM14RST_Pos (8U) #define RCC_APB1RSTR_TIM14RST_Msk (0x1U << RCC_APB1RSTR_TIM14RST_Pos) /*!< 0x00000100 */ #define RCC_APB1RSTR_TIM14RST RCC_APB1RSTR_TIM14RST_Msk #define RCC_APB1RSTR_WWDGRST_Pos (11U) #define RCC_APB1RSTR_WWDGRST_Msk (0x1U << RCC_APB1RSTR_WWDGRST_Pos) /*!< 0x00000800 */ #define RCC_APB1RSTR_WWDGRST RCC_APB1RSTR_WWDGRST_Msk #define RCC_APB1RSTR_SPI2RST_Pos (14U) #define RCC_APB1RSTR_SPI2RST_Msk (0x1U << RCC_APB1RSTR_SPI2RST_Pos) /*!< 0x00004000 */ #define RCC_APB1RSTR_SPI2RST RCC_APB1RSTR_SPI2RST_Msk #define RCC_APB1RSTR_SPI3RST_Pos (15U) #define RCC_APB1RSTR_SPI3RST_Msk (0x1U << RCC_APB1RSTR_SPI3RST_Pos) /*!< 0x00008000 */ #define RCC_APB1RSTR_SPI3RST RCC_APB1RSTR_SPI3RST_Msk #define RCC_APB1RSTR_USART2RST_Pos (17U) #define RCC_APB1RSTR_USART2RST_Msk (0x1U << RCC_APB1RSTR_USART2RST_Pos) /*!< 0x00020000 */ #define RCC_APB1RSTR_USART2RST RCC_APB1RSTR_USART2RST_Msk #define RCC_APB1RSTR_USART3RST_Pos (18U) #define RCC_APB1RSTR_USART3RST_Msk (0x1U << RCC_APB1RSTR_USART3RST_Pos) /*!< 0x00040000 */ #define RCC_APB1RSTR_USART3RST RCC_APB1RSTR_USART3RST_Msk #define RCC_APB1RSTR_UART4RST_Pos (19U) #define RCC_APB1RSTR_UART4RST_Msk (0x1U << RCC_APB1RSTR_UART4RST_Pos) /*!< 0x00080000 */ #define RCC_APB1RSTR_UART4RST RCC_APB1RSTR_UART4RST_Msk #define RCC_APB1RSTR_UART5RST_Pos (20U) #define RCC_APB1RSTR_UART5RST_Msk (0x1U << RCC_APB1RSTR_UART5RST_Pos) /*!< 0x00100000 */ #define RCC_APB1RSTR_UART5RST RCC_APB1RSTR_UART5RST_Msk #define RCC_APB1RSTR_I2C1RST_Pos (21U) #define RCC_APB1RSTR_I2C1RST_Msk (0x1U << RCC_APB1RSTR_I2C1RST_Pos) /*!< 0x00200000 */ #define RCC_APB1RSTR_I2C1RST RCC_APB1RSTR_I2C1RST_Msk #define RCC_APB1RSTR_I2C2RST_Pos (22U) #define RCC_APB1RSTR_I2C2RST_Msk (0x1U << RCC_APB1RSTR_I2C2RST_Pos) /*!< 0x00400000 */ #define RCC_APB1RSTR_I2C2RST RCC_APB1RSTR_I2C2RST_Msk #define RCC_APB1RSTR_I2C3RST_Pos (23U) #define RCC_APB1RSTR_I2C3RST_Msk (0x1U << RCC_APB1RSTR_I2C3RST_Pos) /*!< 0x00800000 */ #define RCC_APB1RSTR_I2C3RST RCC_APB1RSTR_I2C3RST_Msk #define RCC_APB1RSTR_CAN1RST_Pos (25U) #define RCC_APB1RSTR_CAN1RST_Msk (0x1U << RCC_APB1RSTR_CAN1RST_Pos) /*!< 0x02000000 */ #define RCC_APB1RSTR_CAN1RST RCC_APB1RSTR_CAN1RST_Msk #define RCC_APB1RSTR_CAN2RST_Pos (26U) #define RCC_APB1RSTR_CAN2RST_Msk (0x1U << RCC_APB1RSTR_CAN2RST_Pos) /*!< 0x04000000 */ #define RCC_APB1RSTR_CAN2RST RCC_APB1RSTR_CAN2RST_Msk #define RCC_APB1RSTR_PWRRST_Pos (28U) #define RCC_APB1RSTR_PWRRST_Msk (0x1U << RCC_APB1RSTR_PWRRST_Pos) /*!< 0x10000000 */ #define RCC_APB1RSTR_PWRRST RCC_APB1RSTR_PWRRST_Msk #define RCC_APB1RSTR_DACRST_Pos (29U) #define RCC_APB1RSTR_DACRST_Msk (0x1U << RCC_APB1RSTR_DACRST_Pos) /*!< 0x20000000 */ #define RCC_APB1RSTR_DACRST RCC_APB1RSTR_DACRST_Msk #define RCC_APB1RSTR_UART7RST_Pos (30U) #define RCC_APB1RSTR_UART7RST_Msk (0x1U << RCC_APB1RSTR_UART7RST_Pos) /*!< 0x40000000 */ #define RCC_APB1RSTR_UART7RST RCC_APB1RSTR_UART7RST_Msk #define RCC_APB1RSTR_UART8RST_Pos (31U) #define RCC_APB1RSTR_UART8RST_Msk (0x1U << RCC_APB1RSTR_UART8RST_Pos) /*!< 0x80000000 */ #define RCC_APB1RSTR_UART8RST RCC_APB1RSTR_UART8RST_Msk /******************** Bit definition for RCC_APB2RSTR register **************/ #define RCC_APB2RSTR_TIM1RST_Pos (0U) #define RCC_APB2RSTR_TIM1RST_Msk (0x1U << RCC_APB2RSTR_TIM1RST_Pos) /*!< 0x00000001 */ #define RCC_APB2RSTR_TIM1RST RCC_APB2RSTR_TIM1RST_Msk #define RCC_APB2RSTR_TIM8RST_Pos (1U) #define RCC_APB2RSTR_TIM8RST_Msk (0x1U << RCC_APB2RSTR_TIM8RST_Pos) /*!< 0x00000002 */ #define RCC_APB2RSTR_TIM8RST RCC_APB2RSTR_TIM8RST_Msk #define RCC_APB2RSTR_USART1RST_Pos (4U) #define RCC_APB2RSTR_USART1RST_Msk (0x1U << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00000010 */ #define RCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_Msk #define RCC_APB2RSTR_USART6RST_Pos (5U) #define RCC_APB2RSTR_USART6RST_Msk (0x1U << RCC_APB2RSTR_USART6RST_Pos) /*!< 0x00000020 */ #define RCC_APB2RSTR_USART6RST RCC_APB2RSTR_USART6RST_Msk #define RCC_APB2RSTR_ADCRST_Pos (8U) #define RCC_APB2RSTR_ADCRST_Msk (0x1U << RCC_APB2RSTR_ADCRST_Pos) /*!< 0x00000100 */ #define RCC_APB2RSTR_ADCRST RCC_APB2RSTR_ADCRST_Msk #define RCC_APB2RSTR_SDIORST_Pos (11U) #define RCC_APB2RSTR_SDIORST_Msk (0x1U << RCC_APB2RSTR_SDIORST_Pos) /*!< 0x00000800 */ #define RCC_APB2RSTR_SDIORST RCC_APB2RSTR_SDIORST_Msk #define RCC_APB2RSTR_SPI1RST_Pos (12U) #define RCC_APB2RSTR_SPI1RST_Msk (0x1U << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */ #define RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk #define RCC_APB2RSTR_SPI4RST_Pos (13U) #define RCC_APB2RSTR_SPI4RST_Msk (0x1U << RCC_APB2RSTR_SPI4RST_Pos) /*!< 0x00002000 */ #define RCC_APB2RSTR_SPI4RST RCC_APB2RSTR_SPI4RST_Msk #define RCC_APB2RSTR_SYSCFGRST_Pos (14U) #define RCC_APB2RSTR_SYSCFGRST_Msk (0x1U << RCC_APB2RSTR_SYSCFGRST_Pos) /*!< 0x00004000 */ #define RCC_APB2RSTR_SYSCFGRST RCC_APB2RSTR_SYSCFGRST_Msk #define RCC_APB2RSTR_TIM9RST_Pos (16U) #define RCC_APB2RSTR_TIM9RST_Msk (0x1U << RCC_APB2RSTR_TIM9RST_Pos) /*!< 0x00010000 */ #define RCC_APB2RSTR_TIM9RST RCC_APB2RSTR_TIM9RST_Msk #define RCC_APB2RSTR_TIM10RST_Pos (17U) #define RCC_APB2RSTR_TIM10RST_Msk (0x1U << RCC_APB2RSTR_TIM10RST_Pos) /*!< 0x00020000 */ #define RCC_APB2RSTR_TIM10RST RCC_APB2RSTR_TIM10RST_Msk #define RCC_APB2RSTR_TIM11RST_Pos (18U) #define RCC_APB2RSTR_TIM11RST_Msk (0x1U << RCC_APB2RSTR_TIM11RST_Pos) /*!< 0x00040000 */ #define RCC_APB2RSTR_TIM11RST RCC_APB2RSTR_TIM11RST_Msk #define RCC_APB2RSTR_SPI5RST_Pos (20U) #define RCC_APB2RSTR_SPI5RST_Msk (0x1U << RCC_APB2RSTR_SPI5RST_Pos) /*!< 0x00100000 */ #define RCC_APB2RSTR_SPI5RST RCC_APB2RSTR_SPI5RST_Msk #define RCC_APB2RSTR_SPI6RST_Pos (21U) #define RCC_APB2RSTR_SPI6RST_Msk (0x1U << RCC_APB2RSTR_SPI6RST_Pos) /*!< 0x00200000 */ #define RCC_APB2RSTR_SPI6RST RCC_APB2RSTR_SPI6RST_Msk #define RCC_APB2RSTR_SAI1RST_Pos (22U) #define RCC_APB2RSTR_SAI1RST_Msk (0x1U << RCC_APB2RSTR_SAI1RST_Pos) /*!< 0x00400000 */ #define RCC_APB2RSTR_SAI1RST RCC_APB2RSTR_SAI1RST_Msk #define RCC_APB2RSTR_LTDCRST_Pos (26U) #define RCC_APB2RSTR_LTDCRST_Msk (0x1U << RCC_APB2RSTR_LTDCRST_Pos) /*!< 0x04000000 */ #define RCC_APB2RSTR_LTDCRST RCC_APB2RSTR_LTDCRST_Msk #define RCC_APB2RSTR_DSIRST_Pos (27U) #define RCC_APB2RSTR_DSIRST_Msk (0x1U << RCC_APB2RSTR_DSIRST_Pos) /*!< 0x08000000 */ #define RCC_APB2RSTR_DSIRST RCC_APB2RSTR_DSIRST_Msk /* Old SPI1RST bit definition, maintained for legacy purpose */ #define RCC_APB2RSTR_SPI1 RCC_APB2RSTR_SPI1RST /******************** Bit definition for RCC_AHB1ENR register ***************/ #define RCC_AHB1ENR_GPIOAEN_Pos (0U) #define RCC_AHB1ENR_GPIOAEN_Msk (0x1U << RCC_AHB1ENR_GPIOAEN_Pos) /*!< 0x00000001 */ #define RCC_AHB1ENR_GPIOAEN RCC_AHB1ENR_GPIOAEN_Msk #define RCC_AHB1ENR_GPIOBEN_Pos (1U) #define RCC_AHB1ENR_GPIOBEN_Msk (0x1U << RCC_AHB1ENR_GPIOBEN_Pos) /*!< 0x00000002 */ #define RCC_AHB1ENR_GPIOBEN RCC_AHB1ENR_GPIOBEN_Msk #define RCC_AHB1ENR_GPIOCEN_Pos (2U) #define RCC_AHB1ENR_GPIOCEN_Msk (0x1U << RCC_AHB1ENR_GPIOCEN_Pos) /*!< 0x00000004 */ #define RCC_AHB1ENR_GPIOCEN RCC_AHB1ENR_GPIOCEN_Msk #define RCC_AHB1ENR_GPIODEN_Pos (3U) #define RCC_AHB1ENR_GPIODEN_Msk (0x1U << RCC_AHB1ENR_GPIODEN_Pos) /*!< 0x00000008 */ #define RCC_AHB1ENR_GPIODEN RCC_AHB1ENR_GPIODEN_Msk #define RCC_AHB1ENR_GPIOEEN_Pos (4U) #define RCC_AHB1ENR_GPIOEEN_Msk (0x1U << RCC_AHB1ENR_GPIOEEN_Pos) /*!< 0x00000010 */ #define RCC_AHB1ENR_GPIOEEN RCC_AHB1ENR_GPIOEEN_Msk #define RCC_AHB1ENR_GPIOFEN_Pos (5U) #define RCC_AHB1ENR_GPIOFEN_Msk (0x1U << RCC_AHB1ENR_GPIOFEN_Pos) /*!< 0x00000020 */ #define RCC_AHB1ENR_GPIOFEN RCC_AHB1ENR_GPIOFEN_Msk #define RCC_AHB1ENR_GPIOGEN_Pos (6U) #define RCC_AHB1ENR_GPIOGEN_Msk (0x1U << RCC_AHB1ENR_GPIOGEN_Pos) /*!< 0x00000040 */ #define RCC_AHB1ENR_GPIOGEN RCC_AHB1ENR_GPIOGEN_Msk #define RCC_AHB1ENR_GPIOHEN_Pos (7U) #define RCC_AHB1ENR_GPIOHEN_Msk (0x1U << RCC_AHB1ENR_GPIOHEN_Pos) /*!< 0x00000080 */ #define RCC_AHB1ENR_GPIOHEN RCC_AHB1ENR_GPIOHEN_Msk #define RCC_AHB1ENR_GPIOIEN_Pos (8U) #define RCC_AHB1ENR_GPIOIEN_Msk (0x1U << RCC_AHB1ENR_GPIOIEN_Pos) /*!< 0x00000100 */ #define RCC_AHB1ENR_GPIOIEN RCC_AHB1ENR_GPIOIEN_Msk #define RCC_AHB1ENR_GPIOJEN_Pos (9U) #define RCC_AHB1ENR_GPIOJEN_Msk (0x1U << RCC_AHB1ENR_GPIOJEN_Pos) /*!< 0x00000200 */ #define RCC_AHB1ENR_GPIOJEN RCC_AHB1ENR_GPIOJEN_Msk #define RCC_AHB1ENR_GPIOKEN_Pos (10U) #define RCC_AHB1ENR_GPIOKEN_Msk (0x1U << RCC_AHB1ENR_GPIOKEN_Pos) /*!< 0x00000400 */ #define RCC_AHB1ENR_GPIOKEN RCC_AHB1ENR_GPIOKEN_Msk #define RCC_AHB1ENR_CRCEN_Pos (12U) #define RCC_AHB1ENR_CRCEN_Msk (0x1U << RCC_AHB1ENR_CRCEN_Pos) /*!< 0x00001000 */ #define RCC_AHB1ENR_CRCEN RCC_AHB1ENR_CRCEN_Msk #define RCC_AHB1ENR_BKPSRAMEN_Pos (18U) #define RCC_AHB1ENR_BKPSRAMEN_Msk (0x1U << RCC_AHB1ENR_BKPSRAMEN_Pos) /*!< 0x00040000 */ #define RCC_AHB1ENR_BKPSRAMEN RCC_AHB1ENR_BKPSRAMEN_Msk #define RCC_AHB1ENR_CCMDATARAMEN_Pos (20U) #define RCC_AHB1ENR_CCMDATARAMEN_Msk (0x1U << RCC_AHB1ENR_CCMDATARAMEN_Pos) /*!< 0x00100000 */ #define RCC_AHB1ENR_CCMDATARAMEN RCC_AHB1ENR_CCMDATARAMEN_Msk #define RCC_AHB1ENR_DMA1EN_Pos (21U) #define RCC_AHB1ENR_DMA1EN_Msk (0x1U << RCC_AHB1ENR_DMA1EN_Pos) /*!< 0x00200000 */ #define RCC_AHB1ENR_DMA1EN RCC_AHB1ENR_DMA1EN_Msk #define RCC_AHB1ENR_DMA2EN_Pos (22U) #define RCC_AHB1ENR_DMA2EN_Msk (0x1U << RCC_AHB1ENR_DMA2EN_Pos) /*!< 0x00400000 */ #define RCC_AHB1ENR_DMA2EN RCC_AHB1ENR_DMA2EN_Msk #define RCC_AHB1ENR_DMA2DEN_Pos (23U) #define RCC_AHB1ENR_DMA2DEN_Msk (0x1U << RCC_AHB1ENR_DMA2DEN_Pos) /*!< 0x00800000 */ #define RCC_AHB1ENR_DMA2DEN RCC_AHB1ENR_DMA2DEN_Msk #define RCC_AHB1ENR_ETHMACEN_Pos (25U) #define RCC_AHB1ENR_ETHMACEN_Msk (0x1U << RCC_AHB1ENR_ETHMACEN_Pos) /*!< 0x02000000 */ #define RCC_AHB1ENR_ETHMACEN RCC_AHB1ENR_ETHMACEN_Msk #define RCC_AHB1ENR_ETHMACTXEN_Pos (26U) #define RCC_AHB1ENR_ETHMACTXEN_Msk (0x1U << RCC_AHB1ENR_ETHMACTXEN_Pos) /*!< 0x04000000 */ #define RCC_AHB1ENR_ETHMACTXEN RCC_AHB1ENR_ETHMACTXEN_Msk #define RCC_AHB1ENR_ETHMACRXEN_Pos (27U) #define RCC_AHB1ENR_ETHMACRXEN_Msk (0x1U << RCC_AHB1ENR_ETHMACRXEN_Pos) /*!< 0x08000000 */ #define RCC_AHB1ENR_ETHMACRXEN RCC_AHB1ENR_ETHMACRXEN_Msk #define RCC_AHB1ENR_ETHMACPTPEN_Pos (28U) #define RCC_AHB1ENR_ETHMACPTPEN_Msk (0x1U << RCC_AHB1ENR_ETHMACPTPEN_Pos) /*!< 0x10000000 */ #define RCC_AHB1ENR_ETHMACPTPEN RCC_AHB1ENR_ETHMACPTPEN_Msk #define RCC_AHB1ENR_OTGHSEN_Pos (29U) #define RCC_AHB1ENR_OTGHSEN_Msk (0x1U << RCC_AHB1ENR_OTGHSEN_Pos) /*!< 0x20000000 */ #define RCC_AHB1ENR_OTGHSEN RCC_AHB1ENR_OTGHSEN_Msk #define RCC_AHB1ENR_OTGHSULPIEN_Pos (30U) #define RCC_AHB1ENR_OTGHSULPIEN_Msk (0x1U << RCC_AHB1ENR_OTGHSULPIEN_Pos) /*!< 0x40000000 */ #define RCC_AHB1ENR_OTGHSULPIEN RCC_AHB1ENR_OTGHSULPIEN_Msk /******************** Bit definition for RCC_AHB2ENR register ***************/ /* * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie) */ #define RCC_AHB2_SUPPORT /*!< AHB2 Bus is supported */ #define RCC_AHB2ENR_DCMIEN_Pos (0U) #define RCC_AHB2ENR_DCMIEN_Msk (0x1U << RCC_AHB2ENR_DCMIEN_Pos) /*!< 0x00000001 */ #define RCC_AHB2ENR_DCMIEN RCC_AHB2ENR_DCMIEN_Msk #define RCC_AHB2ENR_RNGEN_Pos (6U) #define RCC_AHB2ENR_RNGEN_Msk (0x1U << RCC_AHB2ENR_RNGEN_Pos) /*!< 0x00000040 */ #define RCC_AHB2ENR_RNGEN RCC_AHB2ENR_RNGEN_Msk #define RCC_AHB2ENR_OTGFSEN_Pos (7U) #define RCC_AHB2ENR_OTGFSEN_Msk (0x1U << RCC_AHB2ENR_OTGFSEN_Pos) /*!< 0x00000080 */ #define RCC_AHB2ENR_OTGFSEN RCC_AHB2ENR_OTGFSEN_Msk /******************** Bit definition for RCC_AHB3ENR register ***************/ /* * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie) */ #define RCC_AHB3_SUPPORT /*!< AHB3 Bus is supported */ #define RCC_AHB3ENR_FMCEN_Pos (0U) #define RCC_AHB3ENR_FMCEN_Msk (0x1U << RCC_AHB3ENR_FMCEN_Pos) /*!< 0x00000001 */ #define RCC_AHB3ENR_FMCEN RCC_AHB3ENR_FMCEN_Msk #define RCC_AHB3ENR_QSPIEN_Pos (1U) #define RCC_AHB3ENR_QSPIEN_Msk (0x1U << RCC_AHB3ENR_QSPIEN_Pos) /*!< 0x00000002 */ #define RCC_AHB3ENR_QSPIEN RCC_AHB3ENR_QSPIEN_Msk /******************** Bit definition for RCC_APB1ENR register ***************/ #define RCC_APB1ENR_TIM2EN_Pos (0U) #define RCC_APB1ENR_TIM2EN_Msk (0x1U << RCC_APB1ENR_TIM2EN_Pos) /*!< 0x00000001 */ #define RCC_APB1ENR_TIM2EN RCC_APB1ENR_TIM2EN_Msk #define RCC_APB1ENR_TIM3EN_Pos (1U) #define RCC_APB1ENR_TIM3EN_Msk (0x1U << RCC_APB1ENR_TIM3EN_Pos) /*!< 0x00000002 */ #define RCC_APB1ENR_TIM3EN RCC_APB1ENR_TIM3EN_Msk #define RCC_APB1ENR_TIM4EN_Pos (2U) #define RCC_APB1ENR_TIM4EN_Msk (0x1U << RCC_APB1ENR_TIM4EN_Pos) /*!< 0x00000004 */ #define RCC_APB1ENR_TIM4EN RCC_APB1ENR_TIM4EN_Msk #define RCC_APB1ENR_TIM5EN_Pos (3U) #define RCC_APB1ENR_TIM5EN_Msk (0x1U << RCC_APB1ENR_TIM5EN_Pos) /*!< 0x00000008 */ #define RCC_APB1ENR_TIM5EN RCC_APB1ENR_TIM5EN_Msk #define RCC_APB1ENR_TIM6EN_Pos (4U) #define RCC_APB1ENR_TIM6EN_Msk (0x1U << RCC_APB1ENR_TIM6EN_Pos) /*!< 0x00000010 */ #define RCC_APB1ENR_TIM6EN RCC_APB1ENR_TIM6EN_Msk #define RCC_APB1ENR_TIM7EN_Pos (5U) #define RCC_APB1ENR_TIM7EN_Msk (0x1U << RCC_APB1ENR_TIM7EN_Pos) /*!< 0x00000020 */ #define RCC_APB1ENR_TIM7EN RCC_APB1ENR_TIM7EN_Msk #define RCC_APB1ENR_TIM12EN_Pos (6U) #define RCC_APB1ENR_TIM12EN_Msk (0x1U << RCC_APB1ENR_TIM12EN_Pos) /*!< 0x00000040 */ #define RCC_APB1ENR_TIM12EN RCC_APB1ENR_TIM12EN_Msk #define RCC_APB1ENR_TIM13EN_Pos (7U) #define RCC_APB1ENR_TIM13EN_Msk (0x1U << RCC_APB1ENR_TIM13EN_Pos) /*!< 0x00000080 */ #define RCC_APB1ENR_TIM13EN RCC_APB1ENR_TIM13EN_Msk #define RCC_APB1ENR_TIM14EN_Pos (8U) #define RCC_APB1ENR_TIM14EN_Msk (0x1U << RCC_APB1ENR_TIM14EN_Pos) /*!< 0x00000100 */ #define RCC_APB1ENR_TIM14EN RCC_APB1ENR_TIM14EN_Msk #define RCC_APB1ENR_WWDGEN_Pos (11U) #define RCC_APB1ENR_WWDGEN_Msk (0x1U << RCC_APB1ENR_WWDGEN_Pos) /*!< 0x00000800 */ #define RCC_APB1ENR_WWDGEN RCC_APB1ENR_WWDGEN_Msk #define RCC_APB1ENR_SPI2EN_Pos (14U) #define RCC_APB1ENR_SPI2EN_Msk (0x1U << RCC_APB1ENR_SPI2EN_Pos) /*!< 0x00004000 */ #define RCC_APB1ENR_SPI2EN RCC_APB1ENR_SPI2EN_Msk #define RCC_APB1ENR_SPI3EN_Pos (15U) #define RCC_APB1ENR_SPI3EN_Msk (0x1U << RCC_APB1ENR_SPI3EN_Pos) /*!< 0x00008000 */ #define RCC_APB1ENR_SPI3EN RCC_APB1ENR_SPI3EN_Msk #define RCC_APB1ENR_USART2EN_Pos (17U) #define RCC_APB1ENR_USART2EN_Msk (0x1U << RCC_APB1ENR_USART2EN_Pos) /*!< 0x00020000 */ #define RCC_APB1ENR_USART2EN RCC_APB1ENR_USART2EN_Msk #define RCC_APB1ENR_USART3EN_Pos (18U) #define RCC_APB1ENR_USART3EN_Msk (0x1U << RCC_APB1ENR_USART3EN_Pos) /*!< 0x00040000 */ #define RCC_APB1ENR_USART3EN RCC_APB1ENR_USART3EN_Msk #define RCC_APB1ENR_UART4EN_Pos (19U) #define RCC_APB1ENR_UART4EN_Msk (0x1U << RCC_APB1ENR_UART4EN_Pos) /*!< 0x00080000 */ #define RCC_APB1ENR_UART4EN RCC_APB1ENR_UART4EN_Msk #define RCC_APB1ENR_UART5EN_Pos (20U) #define RCC_APB1ENR_UART5EN_Msk (0x1U << RCC_APB1ENR_UART5EN_Pos) /*!< 0x00100000 */ #define RCC_APB1ENR_UART5EN RCC_APB1ENR_UART5EN_Msk #define RCC_APB1ENR_I2C1EN_Pos (21U) #define RCC_APB1ENR_I2C1EN_Msk (0x1U << RCC_APB1ENR_I2C1EN_Pos) /*!< 0x00200000 */ #define RCC_APB1ENR_I2C1EN RCC_APB1ENR_I2C1EN_Msk #define RCC_APB1ENR_I2C2EN_Pos (22U) #define RCC_APB1ENR_I2C2EN_Msk (0x1U << RCC_APB1ENR_I2C2EN_Pos) /*!< 0x00400000 */ #define RCC_APB1ENR_I2C2EN RCC_APB1ENR_I2C2EN_Msk #define RCC_APB1ENR_I2C3EN_Pos (23U) #define RCC_APB1ENR_I2C3EN_Msk (0x1U << RCC_APB1ENR_I2C3EN_Pos) /*!< 0x00800000 */ #define RCC_APB1ENR_I2C3EN RCC_APB1ENR_I2C3EN_Msk #define RCC_APB1ENR_CAN1EN_Pos (25U) #define RCC_APB1ENR_CAN1EN_Msk (0x1U << RCC_APB1ENR_CAN1EN_Pos) /*!< 0x02000000 */ #define RCC_APB1ENR_CAN1EN RCC_APB1ENR_CAN1EN_Msk #define RCC_APB1ENR_CAN2EN_Pos (26U) #define RCC_APB1ENR_CAN2EN_Msk (0x1U << RCC_APB1ENR_CAN2EN_Pos) /*!< 0x04000000 */ #define RCC_APB1ENR_CAN2EN RCC_APB1ENR_CAN2EN_Msk #define RCC_APB1ENR_PWREN_Pos (28U) #define RCC_APB1ENR_PWREN_Msk (0x1U << RCC_APB1ENR_PWREN_Pos) /*!< 0x10000000 */ #define RCC_APB1ENR_PWREN RCC_APB1ENR_PWREN_Msk #define RCC_APB1ENR_DACEN_Pos (29U) #define RCC_APB1ENR_DACEN_Msk (0x1U << RCC_APB1ENR_DACEN_Pos) /*!< 0x20000000 */ #define RCC_APB1ENR_DACEN RCC_APB1ENR_DACEN_Msk #define RCC_APB1ENR_UART7EN_Pos (30U) #define RCC_APB1ENR_UART7EN_Msk (0x1U << RCC_APB1ENR_UART7EN_Pos) /*!< 0x40000000 */ #define RCC_APB1ENR_UART7EN RCC_APB1ENR_UART7EN_Msk #define RCC_APB1ENR_UART8EN_Pos (31U) #define RCC_APB1ENR_UART8EN_Msk (0x1U << RCC_APB1ENR_UART8EN_Pos) /*!< 0x80000000 */ #define RCC_APB1ENR_UART8EN RCC_APB1ENR_UART8EN_Msk /******************** Bit definition for RCC_APB2ENR register ***************/ #define RCC_APB2ENR_TIM1EN_Pos (0U) #define RCC_APB2ENR_TIM1EN_Msk (0x1U << RCC_APB2ENR_TIM1EN_Pos) /*!< 0x00000001 */ #define RCC_APB2ENR_TIM1EN RCC_APB2ENR_TIM1EN_Msk #define RCC_APB2ENR_TIM8EN_Pos (1U) #define RCC_APB2ENR_TIM8EN_Msk (0x1U << RCC_APB2ENR_TIM8EN_Pos) /*!< 0x00000002 */ #define RCC_APB2ENR_TIM8EN RCC_APB2ENR_TIM8EN_Msk #define RCC_APB2ENR_USART1EN_Pos (4U) #define RCC_APB2ENR_USART1EN_Msk (0x1U << RCC_APB2ENR_USART1EN_Pos) /*!< 0x00000010 */ #define RCC_APB2ENR_USART1EN RCC_APB2ENR_USART1EN_Msk #define RCC_APB2ENR_USART6EN_Pos (5U) #define RCC_APB2ENR_USART6EN_Msk (0x1U << RCC_APB2ENR_USART6EN_Pos) /*!< 0x00000020 */ #define RCC_APB2ENR_USART6EN RCC_APB2ENR_USART6EN_Msk #define RCC_APB2ENR_ADC1EN_Pos (8U) #define RCC_APB2ENR_ADC1EN_Msk (0x1U << RCC_APB2ENR_ADC1EN_Pos) /*!< 0x00000100 */ #define RCC_APB2ENR_ADC1EN RCC_APB2ENR_ADC1EN_Msk #define RCC_APB2ENR_ADC2EN_Pos (9U) #define RCC_APB2ENR_ADC2EN_Msk (0x1U << RCC_APB2ENR_ADC2EN_Pos) /*!< 0x00000200 */ #define RCC_APB2ENR_ADC2EN RCC_APB2ENR_ADC2EN_Msk #define RCC_APB2ENR_ADC3EN_Pos (10U) #define RCC_APB2ENR_ADC3EN_Msk (0x1U << RCC_APB2ENR_ADC3EN_Pos) /*!< 0x00000400 */ #define RCC_APB2ENR_ADC3EN RCC_APB2ENR_ADC3EN_Msk #define RCC_APB2ENR_SDIOEN_Pos (11U) #define RCC_APB2ENR_SDIOEN_Msk (0x1U << RCC_APB2ENR_SDIOEN_Pos) /*!< 0x00000800 */ #define RCC_APB2ENR_SDIOEN RCC_APB2ENR_SDIOEN_Msk #define RCC_APB2ENR_SPI1EN_Pos (12U) #define RCC_APB2ENR_SPI1EN_Msk (0x1U << RCC_APB2ENR_SPI1EN_Pos) /*!< 0x00001000 */ #define RCC_APB2ENR_SPI1EN RCC_APB2ENR_SPI1EN_Msk #define RCC_APB2ENR_SPI4EN_Pos (13U) #define RCC_APB2ENR_SPI4EN_Msk (0x1U << RCC_APB2ENR_SPI4EN_Pos) /*!< 0x00002000 */ #define RCC_APB2ENR_SPI4EN RCC_APB2ENR_SPI4EN_Msk #define RCC_APB2ENR_SYSCFGEN_Pos (14U) #define RCC_APB2ENR_SYSCFGEN_Msk (0x1U << RCC_APB2ENR_SYSCFGEN_Pos) /*!< 0x00004000 */ #define RCC_APB2ENR_SYSCFGEN RCC_APB2ENR_SYSCFGEN_Msk #define RCC_APB2ENR_TIM9EN_Pos (16U) #define RCC_APB2ENR_TIM9EN_Msk (0x1U << RCC_APB2ENR_TIM9EN_Pos) /*!< 0x00010000 */ #define RCC_APB2ENR_TIM9EN RCC_APB2ENR_TIM9EN_Msk #define RCC_APB2ENR_TIM10EN_Pos (17U) #define RCC_APB2ENR_TIM10EN_Msk (0x1U << RCC_APB2ENR_TIM10EN_Pos) /*!< 0x00020000 */ #define RCC_APB2ENR_TIM10EN RCC_APB2ENR_TIM10EN_Msk #define RCC_APB2ENR_TIM11EN_Pos (18U) #define RCC_APB2ENR_TIM11EN_Msk (0x1U << RCC_APB2ENR_TIM11EN_Pos) /*!< 0x00040000 */ #define RCC_APB2ENR_TIM11EN RCC_APB2ENR_TIM11EN_Msk #define RCC_APB2ENR_SPI5EN_Pos (20U) #define RCC_APB2ENR_SPI5EN_Msk (0x1U << RCC_APB2ENR_SPI5EN_Pos) /*!< 0x00100000 */ #define RCC_APB2ENR_SPI5EN RCC_APB2ENR_SPI5EN_Msk #define RCC_APB2ENR_SPI6EN_Pos (21U) #define RCC_APB2ENR_SPI6EN_Msk (0x1U << RCC_APB2ENR_SPI6EN_Pos) /*!< 0x00200000 */ #define RCC_APB2ENR_SPI6EN RCC_APB2ENR_SPI6EN_Msk #define RCC_APB2ENR_SAI1EN_Pos (22U) #define RCC_APB2ENR_SAI1EN_Msk (0x1U << RCC_APB2ENR_SAI1EN_Pos) /*!< 0x00400000 */ #define RCC_APB2ENR_SAI1EN RCC_APB2ENR_SAI1EN_Msk #define RCC_APB2ENR_LTDCEN_Pos (26U) #define RCC_APB2ENR_LTDCEN_Msk (0x1U << RCC_APB2ENR_LTDCEN_Pos) /*!< 0x04000000 */ #define RCC_APB2ENR_LTDCEN RCC_APB2ENR_LTDCEN_Msk #define RCC_APB2ENR_DSIEN_Pos (27U) #define RCC_APB2ENR_DSIEN_Msk (0x1U << RCC_APB2ENR_DSIEN_Pos) /*!< 0x08000000 */ #define RCC_APB2ENR_DSIEN RCC_APB2ENR_DSIEN_Msk /******************** Bit definition for RCC_AHB1LPENR register *************/ #define RCC_AHB1LPENR_GPIOALPEN_Pos (0U) #define RCC_AHB1LPENR_GPIOALPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOALPEN_Pos) /*!< 0x00000001 */ #define RCC_AHB1LPENR_GPIOALPEN RCC_AHB1LPENR_GPIOALPEN_Msk #define RCC_AHB1LPENR_GPIOBLPEN_Pos (1U) #define RCC_AHB1LPENR_GPIOBLPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOBLPEN_Pos) /*!< 0x00000002 */ #define RCC_AHB1LPENR_GPIOBLPEN RCC_AHB1LPENR_GPIOBLPEN_Msk #define RCC_AHB1LPENR_GPIOCLPEN_Pos (2U) #define RCC_AHB1LPENR_GPIOCLPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOCLPEN_Pos) /*!< 0x00000004 */ #define RCC_AHB1LPENR_GPIOCLPEN RCC_AHB1LPENR_GPIOCLPEN_Msk #define RCC_AHB1LPENR_GPIODLPEN_Pos (3U) #define RCC_AHB1LPENR_GPIODLPEN_Msk (0x1U << RCC_AHB1LPENR_GPIODLPEN_Pos) /*!< 0x00000008 */ #define RCC_AHB1LPENR_GPIODLPEN RCC_AHB1LPENR_GPIODLPEN_Msk #define RCC_AHB1LPENR_GPIOELPEN_Pos (4U) #define RCC_AHB1LPENR_GPIOELPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOELPEN_Pos) /*!< 0x00000010 */ #define RCC_AHB1LPENR_GPIOELPEN RCC_AHB1LPENR_GPIOELPEN_Msk #define RCC_AHB1LPENR_GPIOFLPEN_Pos (5U) #define RCC_AHB1LPENR_GPIOFLPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOFLPEN_Pos) /*!< 0x00000020 */ #define RCC_AHB1LPENR_GPIOFLPEN RCC_AHB1LPENR_GPIOFLPEN_Msk #define RCC_AHB1LPENR_GPIOGLPEN_Pos (6U) #define RCC_AHB1LPENR_GPIOGLPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOGLPEN_Pos) /*!< 0x00000040 */ #define RCC_AHB1LPENR_GPIOGLPEN RCC_AHB1LPENR_GPIOGLPEN_Msk #define RCC_AHB1LPENR_GPIOHLPEN_Pos (7U) #define RCC_AHB1LPENR_GPIOHLPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOHLPEN_Pos) /*!< 0x00000080 */ #define RCC_AHB1LPENR_GPIOHLPEN RCC_AHB1LPENR_GPIOHLPEN_Msk #define RCC_AHB1LPENR_GPIOILPEN_Pos (8U) #define RCC_AHB1LPENR_GPIOILPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOILPEN_Pos) /*!< 0x00000100 */ #define RCC_AHB1LPENR_GPIOILPEN RCC_AHB1LPENR_GPIOILPEN_Msk #define RCC_AHB1LPENR_GPIOJLPEN_Pos (9U) #define RCC_AHB1LPENR_GPIOJLPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOJLPEN_Pos) /*!< 0x00000200 */ #define RCC_AHB1LPENR_GPIOJLPEN RCC_AHB1LPENR_GPIOJLPEN_Msk #define RCC_AHB1LPENR_GPIOKLPEN_Pos (10U) #define RCC_AHB1LPENR_GPIOKLPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOKLPEN_Pos) /*!< 0x00000400 */ #define RCC_AHB1LPENR_GPIOKLPEN RCC_AHB1LPENR_GPIOKLPEN_Msk #define RCC_AHB1LPENR_CRCLPEN_Pos (12U) #define RCC_AHB1LPENR_CRCLPEN_Msk (0x1U << RCC_AHB1LPENR_CRCLPEN_Pos) /*!< 0x00001000 */ #define RCC_AHB1LPENR_CRCLPEN RCC_AHB1LPENR_CRCLPEN_Msk #define RCC_AHB1LPENR_FLITFLPEN_Pos (15U) #define RCC_AHB1LPENR_FLITFLPEN_Msk (0x1U << RCC_AHB1LPENR_FLITFLPEN_Pos) /*!< 0x00008000 */ #define RCC_AHB1LPENR_FLITFLPEN RCC_AHB1LPENR_FLITFLPEN_Msk #define RCC_AHB1LPENR_SRAM1LPEN_Pos (16U) #define RCC_AHB1LPENR_SRAM1LPEN_Msk (0x1U << RCC_AHB1LPENR_SRAM1LPEN_Pos) /*!< 0x00010000 */ #define RCC_AHB1LPENR_SRAM1LPEN RCC_AHB1LPENR_SRAM1LPEN_Msk #define RCC_AHB1LPENR_SRAM2LPEN_Pos (17U) #define RCC_AHB1LPENR_SRAM2LPEN_Msk (0x1U << RCC_AHB1LPENR_SRAM2LPEN_Pos) /*!< 0x00020000 */ #define RCC_AHB1LPENR_SRAM2LPEN RCC_AHB1LPENR_SRAM2LPEN_Msk #define RCC_AHB1LPENR_BKPSRAMLPEN_Pos (18U) #define RCC_AHB1LPENR_BKPSRAMLPEN_Msk (0x1U << RCC_AHB1LPENR_BKPSRAMLPEN_Pos) /*!< 0x00040000 */ #define RCC_AHB1LPENR_BKPSRAMLPEN RCC_AHB1LPENR_BKPSRAMLPEN_Msk #define RCC_AHB1LPENR_SRAM3LPEN_Pos (19U) #define RCC_AHB1LPENR_SRAM3LPEN_Msk (0x1U << RCC_AHB1LPENR_SRAM3LPEN_Pos) /*!< 0x00080000 */ #define RCC_AHB1LPENR_SRAM3LPEN RCC_AHB1LPENR_SRAM3LPEN_Msk #define RCC_AHB1LPENR_DMA1LPEN_Pos (21U) #define RCC_AHB1LPENR_DMA1LPEN_Msk (0x1U << RCC_AHB1LPENR_DMA1LPEN_Pos) /*!< 0x00200000 */ #define RCC_AHB1LPENR_DMA1LPEN RCC_AHB1LPENR_DMA1LPEN_Msk #define RCC_AHB1LPENR_DMA2LPEN_Pos (22U) #define RCC_AHB1LPENR_DMA2LPEN_Msk (0x1U << RCC_AHB1LPENR_DMA2LPEN_Pos) /*!< 0x00400000 */ #define RCC_AHB1LPENR_DMA2LPEN RCC_AHB1LPENR_DMA2LPEN_Msk #define RCC_AHB1LPENR_DMA2DLPEN_Pos (23U) #define RCC_AHB1LPENR_DMA2DLPEN_Msk (0x1U << RCC_AHB1LPENR_DMA2DLPEN_Pos) /*!< 0x00800000 */ #define RCC_AHB1LPENR_DMA2DLPEN RCC_AHB1LPENR_DMA2DLPEN_Msk #define RCC_AHB1LPENR_ETHMACLPEN_Pos (25U) #define RCC_AHB1LPENR_ETHMACLPEN_Msk (0x1U << RCC_AHB1LPENR_ETHMACLPEN_Pos) /*!< 0x02000000 */ #define RCC_AHB1LPENR_ETHMACLPEN RCC_AHB1LPENR_ETHMACLPEN_Msk #define RCC_AHB1LPENR_ETHMACTXLPEN_Pos (26U) #define RCC_AHB1LPENR_ETHMACTXLPEN_Msk (0x1U << RCC_AHB1LPENR_ETHMACTXLPEN_Pos) /*!< 0x04000000 */ #define RCC_AHB1LPENR_ETHMACTXLPEN RCC_AHB1LPENR_ETHMACTXLPEN_Msk #define RCC_AHB1LPENR_ETHMACRXLPEN_Pos (27U) #define RCC_AHB1LPENR_ETHMACRXLPEN_Msk (0x1U << RCC_AHB1LPENR_ETHMACRXLPEN_Pos) /*!< 0x08000000 */ #define RCC_AHB1LPENR_ETHMACRXLPEN RCC_AHB1LPENR_ETHMACRXLPEN_Msk #define RCC_AHB1LPENR_ETHMACPTPLPEN_Pos (28U) #define RCC_AHB1LPENR_ETHMACPTPLPEN_Msk (0x1U << RCC_AHB1LPENR_ETHMACPTPLPEN_Pos) /*!< 0x10000000 */ #define RCC_AHB1LPENR_ETHMACPTPLPEN RCC_AHB1LPENR_ETHMACPTPLPEN_Msk #define RCC_AHB1LPENR_OTGHSLPEN_Pos (29U) #define RCC_AHB1LPENR_OTGHSLPEN_Msk (0x1U << RCC_AHB1LPENR_OTGHSLPEN_Pos) /*!< 0x20000000 */ #define RCC_AHB1LPENR_OTGHSLPEN RCC_AHB1LPENR_OTGHSLPEN_Msk #define RCC_AHB1LPENR_OTGHSULPILPEN_Pos (30U) #define RCC_AHB1LPENR_OTGHSULPILPEN_Msk (0x1U << RCC_AHB1LPENR_OTGHSULPILPEN_Pos) /*!< 0x40000000 */ #define RCC_AHB1LPENR_OTGHSULPILPEN RCC_AHB1LPENR_OTGHSULPILPEN_Msk /******************** Bit definition for RCC_AHB2LPENR register *************/ #define RCC_AHB2LPENR_DCMILPEN_Pos (0U) #define RCC_AHB2LPENR_DCMILPEN_Msk (0x1U << RCC_AHB2LPENR_DCMILPEN_Pos) /*!< 0x00000001 */ #define RCC_AHB2LPENR_DCMILPEN RCC_AHB2LPENR_DCMILPEN_Msk #define RCC_AHB2LPENR_RNGLPEN_Pos (6U) #define RCC_AHB2LPENR_RNGLPEN_Msk (0x1U << RCC_AHB2LPENR_RNGLPEN_Pos) /*!< 0x00000040 */ #define RCC_AHB2LPENR_RNGLPEN RCC_AHB2LPENR_RNGLPEN_Msk #define RCC_AHB2LPENR_OTGFSLPEN_Pos (7U) #define RCC_AHB2LPENR_OTGFSLPEN_Msk (0x1U << RCC_AHB2LPENR_OTGFSLPEN_Pos) /*!< 0x00000080 */ #define RCC_AHB2LPENR_OTGFSLPEN RCC_AHB2LPENR_OTGFSLPEN_Msk /******************** Bit definition for RCC_AHB3LPENR register *************/ #define RCC_AHB3LPENR_FMCLPEN_Pos (0U) #define RCC_AHB3LPENR_FMCLPEN_Msk (0x1U << RCC_AHB3LPENR_FMCLPEN_Pos) /*!< 0x00000001 */ #define RCC_AHB3LPENR_FMCLPEN RCC_AHB3LPENR_FMCLPEN_Msk #define RCC_AHB3LPENR_QSPILPEN_Pos (1U) #define RCC_AHB3LPENR_QSPILPEN_Msk (0x1U << RCC_AHB3LPENR_QSPILPEN_Pos) /*!< 0x00000002 */ #define RCC_AHB3LPENR_QSPILPEN RCC_AHB3LPENR_QSPILPEN_Msk /******************** Bit definition for RCC_APB1LPENR register *************/ #define RCC_APB1LPENR_TIM2LPEN_Pos (0U) #define RCC_APB1LPENR_TIM2LPEN_Msk (0x1U << RCC_APB1LPENR_TIM2LPEN_Pos) /*!< 0x00000001 */ #define RCC_APB1LPENR_TIM2LPEN RCC_APB1LPENR_TIM2LPEN_Msk #define RCC_APB1LPENR_TIM3LPEN_Pos (1U) #define RCC_APB1LPENR_TIM3LPEN_Msk (0x1U << RCC_APB1LPENR_TIM3LPEN_Pos) /*!< 0x00000002 */ #define RCC_APB1LPENR_TIM3LPEN RCC_APB1LPENR_TIM3LPEN_Msk #define RCC_APB1LPENR_TIM4LPEN_Pos (2U) #define RCC_APB1LPENR_TIM4LPEN_Msk (0x1U << RCC_APB1LPENR_TIM4LPEN_Pos) /*!< 0x00000004 */ #define RCC_APB1LPENR_TIM4LPEN RCC_APB1LPENR_TIM4LPEN_Msk #define RCC_APB1LPENR_TIM5LPEN_Pos (3U) #define RCC_APB1LPENR_TIM5LPEN_Msk (0x1U << RCC_APB1LPENR_TIM5LPEN_Pos) /*!< 0x00000008 */ #define RCC_APB1LPENR_TIM5LPEN RCC_APB1LPENR_TIM5LPEN_Msk #define RCC_APB1LPENR_TIM6LPEN_Pos (4U) #define RCC_APB1LPENR_TIM6LPEN_Msk (0x1U << RCC_APB1LPENR_TIM6LPEN_Pos) /*!< 0x00000010 */ #define RCC_APB1LPENR_TIM6LPEN RCC_APB1LPENR_TIM6LPEN_Msk #define RCC_APB1LPENR_TIM7LPEN_Pos (5U) #define RCC_APB1LPENR_TIM7LPEN_Msk (0x1U << RCC_APB1LPENR_TIM7LPEN_Pos) /*!< 0x00000020 */ #define RCC_APB1LPENR_TIM7LPEN RCC_APB1LPENR_TIM7LPEN_Msk #define RCC_APB1LPENR_TIM12LPEN_Pos (6U) #define RCC_APB1LPENR_TIM12LPEN_Msk (0x1U << RCC_APB1LPENR_TIM12LPEN_Pos) /*!< 0x00000040 */ #define RCC_APB1LPENR_TIM12LPEN RCC_APB1LPENR_TIM12LPEN_Msk #define RCC_APB1LPENR_TIM13LPEN_Pos (7U) #define RCC_APB1LPENR_TIM13LPEN_Msk (0x1U << RCC_APB1LPENR_TIM13LPEN_Pos) /*!< 0x00000080 */ #define RCC_APB1LPENR_TIM13LPEN RCC_APB1LPENR_TIM13LPEN_Msk #define RCC_APB1LPENR_TIM14LPEN_Pos (8U) #define RCC_APB1LPENR_TIM14LPEN_Msk (0x1U << RCC_APB1LPENR_TIM14LPEN_Pos) /*!< 0x00000100 */ #define RCC_APB1LPENR_TIM14LPEN RCC_APB1LPENR_TIM14LPEN_Msk #define RCC_APB1LPENR_WWDGLPEN_Pos (11U) #define RCC_APB1LPENR_WWDGLPEN_Msk (0x1U << RCC_APB1LPENR_WWDGLPEN_Pos) /*!< 0x00000800 */ #define RCC_APB1LPENR_WWDGLPEN RCC_APB1LPENR_WWDGLPEN_Msk #define RCC_APB1LPENR_SPI2LPEN_Pos (14U) #define RCC_APB1LPENR_SPI2LPEN_Msk (0x1U << RCC_APB1LPENR_SPI2LPEN_Pos) /*!< 0x00004000 */ #define RCC_APB1LPENR_SPI2LPEN RCC_APB1LPENR_SPI2LPEN_Msk #define RCC_APB1LPENR_SPI3LPEN_Pos (15U) #define RCC_APB1LPENR_SPI3LPEN_Msk (0x1U << RCC_APB1LPENR_SPI3LPEN_Pos) /*!< 0x00008000 */ #define RCC_APB1LPENR_SPI3LPEN RCC_APB1LPENR_SPI3LPEN_Msk #define RCC_APB1LPENR_USART2LPEN_Pos (17U) #define RCC_APB1LPENR_USART2LPEN_Msk (0x1U << RCC_APB1LPENR_USART2LPEN_Pos) /*!< 0x00020000 */ #define RCC_APB1LPENR_USART2LPEN RCC_APB1LPENR_USART2LPEN_Msk #define RCC_APB1LPENR_USART3LPEN_Pos (18U) #define RCC_APB1LPENR_USART3LPEN_Msk (0x1U << RCC_APB1LPENR_USART3LPEN_Pos) /*!< 0x00040000 */ #define RCC_APB1LPENR_USART3LPEN RCC_APB1LPENR_USART3LPEN_Msk #define RCC_APB1LPENR_UART4LPEN_Pos (19U) #define RCC_APB1LPENR_UART4LPEN_Msk (0x1U << RCC_APB1LPENR_UART4LPEN_Pos) /*!< 0x00080000 */ #define RCC_APB1LPENR_UART4LPEN RCC_APB1LPENR_UART4LPEN_Msk #define RCC_APB1LPENR_UART5LPEN_Pos (20U) #define RCC_APB1LPENR_UART5LPEN_Msk (0x1U << RCC_APB1LPENR_UART5LPEN_Pos) /*!< 0x00100000 */ #define RCC_APB1LPENR_UART5LPEN RCC_APB1LPENR_UART5LPEN_Msk #define RCC_APB1LPENR_I2C1LPEN_Pos (21U) #define RCC_APB1LPENR_I2C1LPEN_Msk (0x1U << RCC_APB1LPENR_I2C1LPEN_Pos) /*!< 0x00200000 */ #define RCC_APB1LPENR_I2C1LPEN RCC_APB1LPENR_I2C1LPEN_Msk #define RCC_APB1LPENR_I2C2LPEN_Pos (22U) #define RCC_APB1LPENR_I2C2LPEN_Msk (0x1U << RCC_APB1LPENR_I2C2LPEN_Pos) /*!< 0x00400000 */ #define RCC_APB1LPENR_I2C2LPEN RCC_APB1LPENR_I2C2LPEN_Msk #define RCC_APB1LPENR_I2C3LPEN_Pos (23U) #define RCC_APB1LPENR_I2C3LPEN_Msk (0x1U << RCC_APB1LPENR_I2C3LPEN_Pos) /*!< 0x00800000 */ #define RCC_APB1LPENR_I2C3LPEN RCC_APB1LPENR_I2C3LPEN_Msk #define RCC_APB1LPENR_CAN1LPEN_Pos (25U) #define RCC_APB1LPENR_CAN1LPEN_Msk (0x1U << RCC_APB1LPENR_CAN1LPEN_Pos) /*!< 0x02000000 */ #define RCC_APB1LPENR_CAN1LPEN RCC_APB1LPENR_CAN1LPEN_Msk #define RCC_APB1LPENR_CAN2LPEN_Pos (26U) #define RCC_APB1LPENR_CAN2LPEN_Msk (0x1U << RCC_APB1LPENR_CAN2LPEN_Pos) /*!< 0x04000000 */ #define RCC_APB1LPENR_CAN2LPEN RCC_APB1LPENR_CAN2LPEN_Msk #define RCC_APB1LPENR_PWRLPEN_Pos (28U) #define RCC_APB1LPENR_PWRLPEN_Msk (0x1U << RCC_APB1LPENR_PWRLPEN_Pos) /*!< 0x10000000 */ #define RCC_APB1LPENR_PWRLPEN RCC_APB1LPENR_PWRLPEN_Msk #define RCC_APB1LPENR_DACLPEN_Pos (29U) #define RCC_APB1LPENR_DACLPEN_Msk (0x1U << RCC_APB1LPENR_DACLPEN_Pos) /*!< 0x20000000 */ #define RCC_APB1LPENR_DACLPEN RCC_APB1LPENR_DACLPEN_Msk #define RCC_APB1LPENR_UART7LPEN_Pos (30U) #define RCC_APB1LPENR_UART7LPEN_Msk (0x1U << RCC_APB1LPENR_UART7LPEN_Pos) /*!< 0x40000000 */ #define RCC_APB1LPENR_UART7LPEN RCC_APB1LPENR_UART7LPEN_Msk #define RCC_APB1LPENR_UART8LPEN_Pos (31U) #define RCC_APB1LPENR_UART8LPEN_Msk (0x1U << RCC_APB1LPENR_UART8LPEN_Pos) /*!< 0x80000000 */ #define RCC_APB1LPENR_UART8LPEN RCC_APB1LPENR_UART8LPEN_Msk /******************** Bit definition for RCC_APB2LPENR register *************/ #define RCC_APB2LPENR_TIM1LPEN_Pos (0U) #define RCC_APB2LPENR_TIM1LPEN_Msk (0x1U << RCC_APB2LPENR_TIM1LPEN_Pos) /*!< 0x00000001 */ #define RCC_APB2LPENR_TIM1LPEN RCC_APB2LPENR_TIM1LPEN_Msk #define RCC_APB2LPENR_TIM8LPEN_Pos (1U) #define RCC_APB2LPENR_TIM8LPEN_Msk (0x1U << RCC_APB2LPENR_TIM8LPEN_Pos) /*!< 0x00000002 */ #define RCC_APB2LPENR_TIM8LPEN RCC_APB2LPENR_TIM8LPEN_Msk #define RCC_APB2LPENR_USART1LPEN_Pos (4U) #define RCC_APB2LPENR_USART1LPEN_Msk (0x1U << RCC_APB2LPENR_USART1LPEN_Pos) /*!< 0x00000010 */ #define RCC_APB2LPENR_USART1LPEN RCC_APB2LPENR_USART1LPEN_Msk #define RCC_APB2LPENR_USART6LPEN_Pos (5U) #define RCC_APB2LPENR_USART6LPEN_Msk (0x1U << RCC_APB2LPENR_USART6LPEN_Pos) /*!< 0x00000020 */ #define RCC_APB2LPENR_USART6LPEN RCC_APB2LPENR_USART6LPEN_Msk #define RCC_APB2LPENR_ADC1LPEN_Pos (8U) #define RCC_APB2LPENR_ADC1LPEN_Msk (0x1U << RCC_APB2LPENR_ADC1LPEN_Pos) /*!< 0x00000100 */ #define RCC_APB2LPENR_ADC1LPEN RCC_APB2LPENR_ADC1LPEN_Msk #define RCC_APB2LPENR_ADC2LPEN_Pos (9U) #define RCC_APB2LPENR_ADC2LPEN_Msk (0x1U << RCC_APB2LPENR_ADC2LPEN_Pos) /*!< 0x00000200 */ #define RCC_APB2LPENR_ADC2LPEN RCC_APB2LPENR_ADC2LPEN_Msk #define RCC_APB2LPENR_ADC3LPEN_Pos (10U) #define RCC_APB2LPENR_ADC3LPEN_Msk (0x1U << RCC_APB2LPENR_ADC3LPEN_Pos) /*!< 0x00000400 */ #define RCC_APB2LPENR_ADC3LPEN RCC_APB2LPENR_ADC3LPEN_Msk #define RCC_APB2LPENR_SDIOLPEN_Pos (11U) #define RCC_APB2LPENR_SDIOLPEN_Msk (0x1U << RCC_APB2LPENR_SDIOLPEN_Pos) /*!< 0x00000800 */ #define RCC_APB2LPENR_SDIOLPEN RCC_APB2LPENR_SDIOLPEN_Msk #define RCC_APB2LPENR_SPI1LPEN_Pos (12U) #define RCC_APB2LPENR_SPI1LPEN_Msk (0x1U << RCC_APB2LPENR_SPI1LPEN_Pos) /*!< 0x00001000 */ #define RCC_APB2LPENR_SPI1LPEN RCC_APB2LPENR_SPI1LPEN_Msk #define RCC_APB2LPENR_SPI4LPEN_Pos (13U) #define RCC_APB2LPENR_SPI4LPEN_Msk (0x1U << RCC_APB2LPENR_SPI4LPEN_Pos) /*!< 0x00002000 */ #define RCC_APB2LPENR_SPI4LPEN RCC_APB2LPENR_SPI4LPEN_Msk #define RCC_APB2LPENR_SYSCFGLPEN_Pos (14U) #define RCC_APB2LPENR_SYSCFGLPEN_Msk (0x1U << RCC_APB2LPENR_SYSCFGLPEN_Pos) /*!< 0x00004000 */ #define RCC_APB2LPENR_SYSCFGLPEN RCC_APB2LPENR_SYSCFGLPEN_Msk #define RCC_APB2LPENR_TIM9LPEN_Pos (16U) #define RCC_APB2LPENR_TIM9LPEN_Msk (0x1U << RCC_APB2LPENR_TIM9LPEN_Pos) /*!< 0x00010000 */ #define RCC_APB2LPENR_TIM9LPEN RCC_APB2LPENR_TIM9LPEN_Msk #define RCC_APB2LPENR_TIM10LPEN_Pos (17U) #define RCC_APB2LPENR_TIM10LPEN_Msk (0x1U << RCC_APB2LPENR_TIM10LPEN_Pos) /*!< 0x00020000 */ #define RCC_APB2LPENR_TIM10LPEN RCC_APB2LPENR_TIM10LPEN_Msk #define RCC_APB2LPENR_TIM11LPEN_Pos (18U) #define RCC_APB2LPENR_TIM11LPEN_Msk (0x1U << RCC_APB2LPENR_TIM11LPEN_Pos) /*!< 0x00040000 */ #define RCC_APB2LPENR_TIM11LPEN RCC_APB2LPENR_TIM11LPEN_Msk #define RCC_APB2LPENR_SPI5LPEN_Pos (20U) #define RCC_APB2LPENR_SPI5LPEN_Msk (0x1U << RCC_APB2LPENR_SPI5LPEN_Pos) /*!< 0x00100000 */ #define RCC_APB2LPENR_SPI5LPEN RCC_APB2LPENR_SPI5LPEN_Msk #define RCC_APB2LPENR_SPI6LPEN_Pos (21U) #define RCC_APB2LPENR_SPI6LPEN_Msk (0x1U << RCC_APB2LPENR_SPI6LPEN_Pos) /*!< 0x00200000 */ #define RCC_APB2LPENR_SPI6LPEN RCC_APB2LPENR_SPI6LPEN_Msk #define RCC_APB2LPENR_SAI1LPEN_Pos (22U) #define RCC_APB2LPENR_SAI1LPEN_Msk (0x1U << RCC_APB2LPENR_SAI1LPEN_Pos) /*!< 0x00400000 */ #define RCC_APB2LPENR_SAI1LPEN RCC_APB2LPENR_SAI1LPEN_Msk #define RCC_APB2LPENR_LTDCLPEN_Pos (26U) #define RCC_APB2LPENR_LTDCLPEN_Msk (0x1U << RCC_APB2LPENR_LTDCLPEN_Pos) /*!< 0x04000000 */ #define RCC_APB2LPENR_LTDCLPEN RCC_APB2LPENR_LTDCLPEN_Msk #define RCC_APB2LPENR_DSILPEN_Pos (27U) #define RCC_APB2LPENR_DSILPEN_Msk (0x1U << RCC_APB2LPENR_DSILPEN_Pos) /*!< 0x08000000 */ #define RCC_APB2LPENR_DSILPEN RCC_APB2LPENR_DSILPEN_Msk /******************** Bit definition for RCC_BDCR register ******************/ #define RCC_BDCR_LSEON_Pos (0U) #define RCC_BDCR_LSEON_Msk (0x1U << RCC_BDCR_LSEON_Pos) /*!< 0x00000001 */ #define RCC_BDCR_LSEON RCC_BDCR_LSEON_Msk #define RCC_BDCR_LSERDY_Pos (1U) #define RCC_BDCR_LSERDY_Msk (0x1U << RCC_BDCR_LSERDY_Pos) /*!< 0x00000002 */ #define RCC_BDCR_LSERDY RCC_BDCR_LSERDY_Msk #define RCC_BDCR_LSEBYP_Pos (2U) #define RCC_BDCR_LSEBYP_Msk (0x1U << RCC_BDCR_LSEBYP_Pos) /*!< 0x00000004 */ #define RCC_BDCR_LSEBYP RCC_BDCR_LSEBYP_Msk #define RCC_BDCR_LSEMOD_Pos (3U) #define RCC_BDCR_LSEMOD_Msk (0x1U << RCC_BDCR_LSEMOD_Pos) /*!< 0x00000008 */ #define RCC_BDCR_LSEMOD RCC_BDCR_LSEMOD_Msk #define RCC_BDCR_RTCSEL_Pos (8U) #define RCC_BDCR_RTCSEL_Msk (0x3U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000300 */ #define RCC_BDCR_RTCSEL RCC_BDCR_RTCSEL_Msk #define RCC_BDCR_RTCSEL_0 (0x1U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000100 */ #define RCC_BDCR_RTCSEL_1 (0x2U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000200 */ #define RCC_BDCR_RTCEN_Pos (15U) #define RCC_BDCR_RTCEN_Msk (0x1U << RCC_BDCR_RTCEN_Pos) /*!< 0x00008000 */ #define RCC_BDCR_RTCEN RCC_BDCR_RTCEN_Msk #define RCC_BDCR_BDRST_Pos (16U) #define RCC_BDCR_BDRST_Msk (0x1U << RCC_BDCR_BDRST_Pos) /*!< 0x00010000 */ #define RCC_BDCR_BDRST RCC_BDCR_BDRST_Msk /******************** Bit definition for RCC_CSR register *******************/ #define RCC_CSR_LSION_Pos (0U) #define RCC_CSR_LSION_Msk (0x1U << RCC_CSR_LSION_Pos) /*!< 0x00000001 */ #define RCC_CSR_LSION RCC_CSR_LSION_Msk #define RCC_CSR_LSIRDY_Pos (1U) #define RCC_CSR_LSIRDY_Msk (0x1U << RCC_CSR_LSIRDY_Pos) /*!< 0x00000002 */ #define RCC_CSR_LSIRDY RCC_CSR_LSIRDY_Msk #define RCC_CSR_RMVF_Pos (24U) #define RCC_CSR_RMVF_Msk (0x1U << RCC_CSR_RMVF_Pos) /*!< 0x01000000 */ #define RCC_CSR_RMVF RCC_CSR_RMVF_Msk #define RCC_CSR_BORRSTF_Pos (25U) #define RCC_CSR_BORRSTF_Msk (0x1U << RCC_CSR_BORRSTF_Pos) /*!< 0x02000000 */ #define RCC_CSR_BORRSTF RCC_CSR_BORRSTF_Msk #define RCC_CSR_PINRSTF_Pos (26U) #define RCC_CSR_PINRSTF_Msk (0x1U << RCC_CSR_PINRSTF_Pos) /*!< 0x04000000 */ #define RCC_CSR_PINRSTF RCC_CSR_PINRSTF_Msk #define RCC_CSR_PORRSTF_Pos (27U) #define RCC_CSR_PORRSTF_Msk (0x1U << RCC_CSR_PORRSTF_Pos) /*!< 0x08000000 */ #define RCC_CSR_PORRSTF RCC_CSR_PORRSTF_Msk #define RCC_CSR_SFTRSTF_Pos (28U) #define RCC_CSR_SFTRSTF_Msk (0x1U << RCC_CSR_SFTRSTF_Pos) /*!< 0x10000000 */ #define RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF_Msk #define RCC_CSR_IWDGRSTF_Pos (29U) #define RCC_CSR_IWDGRSTF_Msk (0x1U << RCC_CSR_IWDGRSTF_Pos) /*!< 0x20000000 */ #define RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF_Msk #define RCC_CSR_WWDGRSTF_Pos (30U) #define RCC_CSR_WWDGRSTF_Msk (0x1U << RCC_CSR_WWDGRSTF_Pos) /*!< 0x40000000 */ #define RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF_Msk #define RCC_CSR_LPWRRSTF_Pos (31U) #define RCC_CSR_LPWRRSTF_Msk (0x1U << RCC_CSR_LPWRRSTF_Pos) /*!< 0x80000000 */ #define RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF_Msk /* Legacy defines */ #define RCC_CSR_PADRSTF RCC_CSR_PINRSTF #define RCC_CSR_WDGRSTF RCC_CSR_IWDGRSTF /******************** Bit definition for RCC_SSCGR register *****************/ #define RCC_SSCGR_MODPER_Pos (0U) #define RCC_SSCGR_MODPER_Msk (0x1FFFU << RCC_SSCGR_MODPER_Pos) /*!< 0x00001FFF */ #define RCC_SSCGR_MODPER RCC_SSCGR_MODPER_Msk #define RCC_SSCGR_INCSTEP_Pos (13U) #define RCC_SSCGR_INCSTEP_Msk (0x7FFFU << RCC_SSCGR_INCSTEP_Pos) /*!< 0x0FFFE000 */ #define RCC_SSCGR_INCSTEP RCC_SSCGR_INCSTEP_Msk #define RCC_SSCGR_SPREADSEL_Pos (30U) #define RCC_SSCGR_SPREADSEL_Msk (0x1U << RCC_SSCGR_SPREADSEL_Pos) /*!< 0x40000000 */ #define RCC_SSCGR_SPREADSEL RCC_SSCGR_SPREADSEL_Msk #define RCC_SSCGR_SSCGEN_Pos (31U) #define RCC_SSCGR_SSCGEN_Msk (0x1U << RCC_SSCGR_SSCGEN_Pos) /*!< 0x80000000 */ #define RCC_SSCGR_SSCGEN RCC_SSCGR_SSCGEN_Msk /******************** Bit definition for RCC_PLLI2SCFGR register ************/ #define RCC_PLLI2SCFGR_PLLI2SN_Pos (6U) #define RCC_PLLI2SCFGR_PLLI2SN_Msk (0x1FFU << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00007FC0 */ #define RCC_PLLI2SCFGR_PLLI2SN RCC_PLLI2SCFGR_PLLI2SN_Msk #define RCC_PLLI2SCFGR_PLLI2SN_0 (0x001U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000040 */ #define RCC_PLLI2SCFGR_PLLI2SN_1 (0x002U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000080 */ #define RCC_PLLI2SCFGR_PLLI2SN_2 (0x004U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000100 */ #define RCC_PLLI2SCFGR_PLLI2SN_3 (0x008U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000200 */ #define RCC_PLLI2SCFGR_PLLI2SN_4 (0x010U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000400 */ #define RCC_PLLI2SCFGR_PLLI2SN_5 (0x020U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000800 */ #define RCC_PLLI2SCFGR_PLLI2SN_6 (0x040U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00001000 */ #define RCC_PLLI2SCFGR_PLLI2SN_7 (0x080U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00002000 */ #define RCC_PLLI2SCFGR_PLLI2SN_8 (0x100U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00004000 */ #define RCC_PLLI2SCFGR_PLLI2SQ_Pos (24U) #define RCC_PLLI2SCFGR_PLLI2SQ_Msk (0xFU << RCC_PLLI2SCFGR_PLLI2SQ_Pos) /*!< 0x0F000000 */ #define RCC_PLLI2SCFGR_PLLI2SQ RCC_PLLI2SCFGR_PLLI2SQ_Msk #define RCC_PLLI2SCFGR_PLLI2SQ_0 (0x1U << RCC_PLLI2SCFGR_PLLI2SQ_Pos) /*!< 0x01000000 */ #define RCC_PLLI2SCFGR_PLLI2SQ_1 (0x2U << RCC_PLLI2SCFGR_PLLI2SQ_Pos) /*!< 0x02000000 */ #define RCC_PLLI2SCFGR_PLLI2SQ_2 (0x4U << RCC_PLLI2SCFGR_PLLI2SQ_Pos) /*!< 0x04000000 */ #define RCC_PLLI2SCFGR_PLLI2SQ_3 (0x8U << RCC_PLLI2SCFGR_PLLI2SQ_Pos) /*!< 0x08000000 */ #define RCC_PLLI2SCFGR_PLLI2SR_Pos (28U) #define RCC_PLLI2SCFGR_PLLI2SR_Msk (0x7U << RCC_PLLI2SCFGR_PLLI2SR_Pos) /*!< 0x70000000 */ #define RCC_PLLI2SCFGR_PLLI2SR RCC_PLLI2SCFGR_PLLI2SR_Msk #define RCC_PLLI2SCFGR_PLLI2SR_0 (0x1U << RCC_PLLI2SCFGR_PLLI2SR_Pos) /*!< 0x10000000 */ #define RCC_PLLI2SCFGR_PLLI2SR_1 (0x2U << RCC_PLLI2SCFGR_PLLI2SR_Pos) /*!< 0x20000000 */ #define RCC_PLLI2SCFGR_PLLI2SR_2 (0x4U << RCC_PLLI2SCFGR_PLLI2SR_Pos) /*!< 0x40000000 */ /******************** Bit definition for RCC_PLLSAICFGR register ************/ #define RCC_PLLSAICFGR_PLLSAIN_Pos (6U) #define RCC_PLLSAICFGR_PLLSAIN_Msk (0x1FFU << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00007FC0 */ #define RCC_PLLSAICFGR_PLLSAIN RCC_PLLSAICFGR_PLLSAIN_Msk #define RCC_PLLSAICFGR_PLLSAIN_0 (0x001U << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00000040 */ #define RCC_PLLSAICFGR_PLLSAIN_1 (0x002U << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00000080 */ #define RCC_PLLSAICFGR_PLLSAIN_2 (0x004U << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00000100 */ #define RCC_PLLSAICFGR_PLLSAIN_3 (0x008U << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00000200 */ #define RCC_PLLSAICFGR_PLLSAIN_4 (0x010U << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00000400 */ #define RCC_PLLSAICFGR_PLLSAIN_5 (0x020U << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00000800 */ #define RCC_PLLSAICFGR_PLLSAIN_6 (0x040U << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00001000 */ #define RCC_PLLSAICFGR_PLLSAIN_7 (0x080U << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00002000 */ #define RCC_PLLSAICFGR_PLLSAIN_8 (0x100U << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00004000 */ #define RCC_PLLSAICFGR_PLLSAIP_Pos (16U) #define RCC_PLLSAICFGR_PLLSAIP_Msk (0x3U << RCC_PLLSAICFGR_PLLSAIP_Pos) /*!< 0x00030000 */ #define RCC_PLLSAICFGR_PLLSAIP RCC_PLLSAICFGR_PLLSAIP_Msk #define RCC_PLLSAICFGR_PLLSAIP_0 (0x1U << RCC_PLLSAICFGR_PLLSAIP_Pos) /*!< 0x00010000 */ #define RCC_PLLSAICFGR_PLLSAIP_1 (0x2U << RCC_PLLSAICFGR_PLLSAIP_Pos) /*!< 0x00020000 */ #define RCC_PLLSAICFGR_PLLSAIQ_Pos (24U) #define RCC_PLLSAICFGR_PLLSAIQ_Msk (0xFU << RCC_PLLSAICFGR_PLLSAIQ_Pos) /*!< 0x0F000000 */ #define RCC_PLLSAICFGR_PLLSAIQ RCC_PLLSAICFGR_PLLSAIQ_Msk #define RCC_PLLSAICFGR_PLLSAIQ_0 (0x1U << RCC_PLLSAICFGR_PLLSAIQ_Pos) /*!< 0x01000000 */ #define RCC_PLLSAICFGR_PLLSAIQ_1 (0x2U << RCC_PLLSAICFGR_PLLSAIQ_Pos) /*!< 0x02000000 */ #define RCC_PLLSAICFGR_PLLSAIQ_2 (0x4U << RCC_PLLSAICFGR_PLLSAIQ_Pos) /*!< 0x04000000 */ #define RCC_PLLSAICFGR_PLLSAIQ_3 (0x8U << RCC_PLLSAICFGR_PLLSAIQ_Pos) /*!< 0x08000000 */ #define RCC_PLLSAICFGR_PLLSAIR_Pos (28U) #define RCC_PLLSAICFGR_PLLSAIR_Msk (0x7U << RCC_PLLSAICFGR_PLLSAIR_Pos) /*!< 0x70000000 */ #define RCC_PLLSAICFGR_PLLSAIR RCC_PLLSAICFGR_PLLSAIR_Msk #define RCC_PLLSAICFGR_PLLSAIR_0 (0x1U << RCC_PLLSAICFGR_PLLSAIR_Pos) /*!< 0x10000000 */ #define RCC_PLLSAICFGR_PLLSAIR_1 (0x2U << RCC_PLLSAICFGR_PLLSAIR_Pos) /*!< 0x20000000 */ #define RCC_PLLSAICFGR_PLLSAIR_2 (0x4U << RCC_PLLSAICFGR_PLLSAIR_Pos) /*!< 0x40000000 */ /******************** Bit definition for RCC_DCKCFGR register ***************/ #define RCC_DCKCFGR_PLLI2SDIVQ_Pos (0U) #define RCC_DCKCFGR_PLLI2SDIVQ_Msk (0x1FU << RCC_DCKCFGR_PLLI2SDIVQ_Pos) /*!< 0x0000001F */ #define RCC_DCKCFGR_PLLI2SDIVQ RCC_DCKCFGR_PLLI2SDIVQ_Msk #define RCC_DCKCFGR_PLLI2SDIVQ_0 (0x01U << RCC_DCKCFGR_PLLI2SDIVQ_Pos) /*!< 0x00000001 */ #define RCC_DCKCFGR_PLLI2SDIVQ_1 (0x02U << RCC_DCKCFGR_PLLI2SDIVQ_Pos) /*!< 0x00000002 */ #define RCC_DCKCFGR_PLLI2SDIVQ_2 (0x04U << RCC_DCKCFGR_PLLI2SDIVQ_Pos) /*!< 0x00000004 */ #define RCC_DCKCFGR_PLLI2SDIVQ_3 (0x08U << RCC_DCKCFGR_PLLI2SDIVQ_Pos) /*!< 0x00000008 */ #define RCC_DCKCFGR_PLLI2SDIVQ_4 (0x10U << RCC_DCKCFGR_PLLI2SDIVQ_Pos) /*!< 0x00000010 */ #define RCC_DCKCFGR_PLLSAIDIVQ_Pos (8U) #define RCC_DCKCFGR_PLLSAIDIVQ_Msk (0x1FU << RCC_DCKCFGR_PLLSAIDIVQ_Pos) /*!< 0x00001F00 */ #define RCC_DCKCFGR_PLLSAIDIVQ RCC_DCKCFGR_PLLSAIDIVQ_Msk #define RCC_DCKCFGR_PLLSAIDIVQ_0 (0x01U << RCC_DCKCFGR_PLLSAIDIVQ_Pos) /*!< 0x00000100 */ #define RCC_DCKCFGR_PLLSAIDIVQ_1 (0x02U << RCC_DCKCFGR_PLLSAIDIVQ_Pos) /*!< 0x00000200 */ #define RCC_DCKCFGR_PLLSAIDIVQ_2 (0x04U << RCC_DCKCFGR_PLLSAIDIVQ_Pos) /*!< 0x00000400 */ #define RCC_DCKCFGR_PLLSAIDIVQ_3 (0x08U << RCC_DCKCFGR_PLLSAIDIVQ_Pos) /*!< 0x00000800 */ #define RCC_DCKCFGR_PLLSAIDIVQ_4 (0x10U << RCC_DCKCFGR_PLLSAIDIVQ_Pos) /*!< 0x00001000 */ #define RCC_DCKCFGR_PLLSAIDIVR_Pos (16U) #define RCC_DCKCFGR_PLLSAIDIVR_Msk (0x3U << RCC_DCKCFGR_PLLSAIDIVR_Pos) /*!< 0x00030000 */ #define RCC_DCKCFGR_PLLSAIDIVR RCC_DCKCFGR_PLLSAIDIVR_Msk #define RCC_DCKCFGR_PLLSAIDIVR_0 (0x1U << RCC_DCKCFGR_PLLSAIDIVR_Pos) /*!< 0x00010000 */ #define RCC_DCKCFGR_PLLSAIDIVR_1 (0x2U << RCC_DCKCFGR_PLLSAIDIVR_Pos) /*!< 0x00020000 */ #define RCC_DCKCFGR_SAI1ASRC_Pos (20U) #define RCC_DCKCFGR_SAI1ASRC_Msk (0x3U << RCC_DCKCFGR_SAI1ASRC_Pos) /*!< 0x00300000 */ #define RCC_DCKCFGR_SAI1ASRC RCC_DCKCFGR_SAI1ASRC_Msk #define RCC_DCKCFGR_SAI1ASRC_0 (0x1U << RCC_DCKCFGR_SAI1ASRC_Pos) /*!< 0x00100000 */ #define RCC_DCKCFGR_SAI1ASRC_1 (0x2U << RCC_DCKCFGR_SAI1ASRC_Pos) /*!< 0x00200000 */ #define RCC_DCKCFGR_SAI1BSRC_Pos (22U) #define RCC_DCKCFGR_SAI1BSRC_Msk (0x3U << RCC_DCKCFGR_SAI1BSRC_Pos) /*!< 0x00C00000 */ #define RCC_DCKCFGR_SAI1BSRC RCC_DCKCFGR_SAI1BSRC_Msk #define RCC_DCKCFGR_SAI1BSRC_0 (0x1U << RCC_DCKCFGR_SAI1BSRC_Pos) /*!< 0x00400000 */ #define RCC_DCKCFGR_SAI1BSRC_1 (0x2U << RCC_DCKCFGR_SAI1BSRC_Pos) /*!< 0x00800000 */ #define RCC_DCKCFGR_TIMPRE_Pos (24U) #define RCC_DCKCFGR_TIMPRE_Msk (0x1U << RCC_DCKCFGR_TIMPRE_Pos) /*!< 0x01000000 */ #define RCC_DCKCFGR_TIMPRE RCC_DCKCFGR_TIMPRE_Msk #define RCC_DCKCFGR_CK48MSEL_Pos (27U) #define RCC_DCKCFGR_CK48MSEL_Msk (0x1U << RCC_DCKCFGR_CK48MSEL_Pos) /*!< 0x08000000 */ #define RCC_DCKCFGR_CK48MSEL RCC_DCKCFGR_CK48MSEL_Msk #define RCC_DCKCFGR_SDIOSEL_Pos (28U) #define RCC_DCKCFGR_SDIOSEL_Msk (0x1U << RCC_DCKCFGR_SDIOSEL_Pos) /*!< 0x10000000 */ #define RCC_DCKCFGR_SDIOSEL RCC_DCKCFGR_SDIOSEL_Msk #define RCC_DCKCFGR_DSISEL_Pos (29U) #define RCC_DCKCFGR_DSISEL_Msk (0x1U << RCC_DCKCFGR_DSISEL_Pos) /*!< 0x20000000 */ #define RCC_DCKCFGR_DSISEL RCC_DCKCFGR_DSISEL_Msk /******************************************************************************/ /* */ /* RNG */ /* */ /******************************************************************************/ /******************** Bits definition for RNG_CR register *******************/ #define RNG_CR_RNGEN_Pos (2U) #define RNG_CR_RNGEN_Msk (0x1U << RNG_CR_RNGEN_Pos) /*!< 0x00000004 */ #define RNG_CR_RNGEN RNG_CR_RNGEN_Msk #define RNG_CR_IE_Pos (3U) #define RNG_CR_IE_Msk (0x1U << RNG_CR_IE_Pos) /*!< 0x00000008 */ #define RNG_CR_IE RNG_CR_IE_Msk /******************** Bits definition for RNG_SR register *******************/ #define RNG_SR_DRDY_Pos (0U) #define RNG_SR_DRDY_Msk (0x1U << RNG_SR_DRDY_Pos) /*!< 0x00000001 */ #define RNG_SR_DRDY RNG_SR_DRDY_Msk #define RNG_SR_CECS_Pos (1U) #define RNG_SR_CECS_Msk (0x1U << RNG_SR_CECS_Pos) /*!< 0x00000002 */ #define RNG_SR_CECS RNG_SR_CECS_Msk #define RNG_SR_SECS_Pos (2U) #define RNG_SR_SECS_Msk (0x1U << RNG_SR_SECS_Pos) /*!< 0x00000004 */ #define RNG_SR_SECS RNG_SR_SECS_Msk #define RNG_SR_CEIS_Pos (5U) #define RNG_SR_CEIS_Msk (0x1U << RNG_SR_CEIS_Pos) /*!< 0x00000020 */ #define RNG_SR_CEIS RNG_SR_CEIS_Msk #define RNG_SR_SEIS_Pos (6U) #define RNG_SR_SEIS_Msk (0x1U << RNG_SR_SEIS_Pos) /*!< 0x00000040 */ #define RNG_SR_SEIS RNG_SR_SEIS_Msk /******************************************************************************/ /* */ /* Real-Time Clock (RTC) */ /* */ /******************************************************************************/ /* * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie) */ #define RTC_TAMPER2_SUPPORT /*!< TAMPER 2 feature support */ #define RTC_AF2_SUPPORT /*!< RTC Alternate Function 2 mapping support */ /******************** Bits definition for RTC_TR register *******************/ #define RTC_TR_PM_Pos (22U) #define RTC_TR_PM_Msk (0x1U << RTC_TR_PM_Pos) /*!< 0x00400000 */ #define RTC_TR_PM RTC_TR_PM_Msk #define RTC_TR_HT_Pos (20U) #define RTC_TR_HT_Msk (0x3U << RTC_TR_HT_Pos) /*!< 0x00300000 */ #define RTC_TR_HT RTC_TR_HT_Msk #define RTC_TR_HT_0 (0x1U << RTC_TR_HT_Pos) /*!< 0x00100000 */ #define RTC_TR_HT_1 (0x2U << RTC_TR_HT_Pos) /*!< 0x00200000 */ #define RTC_TR_HU_Pos (16U) #define RTC_TR_HU_Msk (0xFU << RTC_TR_HU_Pos) /*!< 0x000F0000 */ #define RTC_TR_HU RTC_TR_HU_Msk #define RTC_TR_HU_0 (0x1U << RTC_TR_HU_Pos) /*!< 0x00010000 */ #define RTC_TR_HU_1 (0x2U << RTC_TR_HU_Pos) /*!< 0x00020000 */ #define RTC_TR_HU_2 (0x4U << RTC_TR_HU_Pos) /*!< 0x00040000 */ #define RTC_TR_HU_3 (0x8U << RTC_TR_HU_Pos) /*!< 0x00080000 */ #define RTC_TR_MNT_Pos (12U) #define RTC_TR_MNT_Msk (0x7U << RTC_TR_MNT_Pos) /*!< 0x00007000 */ #define RTC_TR_MNT RTC_TR_MNT_Msk #define RTC_TR_MNT_0 (0x1U << RTC_TR_MNT_Pos) /*!< 0x00001000 */ #define RTC_TR_MNT_1 (0x2U << RTC_TR_MNT_Pos) /*!< 0x00002000 */ #define RTC_TR_MNT_2 (0x4U << RTC_TR_MNT_Pos) /*!< 0x00004000 */ #define RTC_TR_MNU_Pos (8U) #define RTC_TR_MNU_Msk (0xFU << RTC_TR_MNU_Pos) /*!< 0x00000F00 */ #define RTC_TR_MNU RTC_TR_MNU_Msk #define RTC_TR_MNU_0 (0x1U << RTC_TR_MNU_Pos) /*!< 0x00000100 */ #define RTC_TR_MNU_1 (0x2U << RTC_TR_MNU_Pos) /*!< 0x00000200 */ #define RTC_TR_MNU_2 (0x4U << RTC_TR_MNU_Pos) /*!< 0x00000400 */ #define RTC_TR_MNU_3 (0x8U << RTC_TR_MNU_Pos) /*!< 0x00000800 */ #define RTC_TR_ST_Pos (4U) #define RTC_TR_ST_Msk (0x7U << RTC_TR_ST_Pos) /*!< 0x00000070 */ #define RTC_TR_ST RTC_TR_ST_Msk #define RTC_TR_ST_0 (0x1U << RTC_TR_ST_Pos) /*!< 0x00000010 */ #define RTC_TR_ST_1 (0x2U << RTC_TR_ST_Pos) /*!< 0x00000020 */ #define RTC_TR_ST_2 (0x4U << RTC_TR_ST_Pos) /*!< 0x00000040 */ #define RTC_TR_SU_Pos (0U) #define RTC_TR_SU_Msk (0xFU << RTC_TR_SU_Pos) /*!< 0x0000000F */ #define RTC_TR_SU RTC_TR_SU_Msk #define RTC_TR_SU_0 (0x1U << RTC_TR_SU_Pos) /*!< 0x00000001 */ #define RTC_TR_SU_1 (0x2U << RTC_TR_SU_Pos) /*!< 0x00000002 */ #define RTC_TR_SU_2 (0x4U << RTC_TR_SU_Pos) /*!< 0x00000004 */ #define RTC_TR_SU_3 (0x8U << RTC_TR_SU_Pos) /*!< 0x00000008 */ /******************** Bits definition for RTC_DR register *******************/ #define RTC_DR_YT_Pos (20U) #define RTC_DR_YT_Msk (0xFU << RTC_DR_YT_Pos) /*!< 0x00F00000 */ #define RTC_DR_YT RTC_DR_YT_Msk #define RTC_DR_YT_0 (0x1U << RTC_DR_YT_Pos) /*!< 0x00100000 */ #define RTC_DR_YT_1 (0x2U << RTC_DR_YT_Pos) /*!< 0x00200000 */ #define RTC_DR_YT_2 (0x4U << RTC_DR_YT_Pos) /*!< 0x00400000 */ #define RTC_DR_YT_3 (0x8U << RTC_DR_YT_Pos) /*!< 0x00800000 */ #define RTC_DR_YU_Pos (16U) #define RTC_DR_YU_Msk (0xFU << RTC_DR_YU_Pos) /*!< 0x000F0000 */ #define RTC_DR_YU RTC_DR_YU_Msk #define RTC_DR_YU_0 (0x1U << RTC_DR_YU_Pos) /*!< 0x00010000 */ #define RTC_DR_YU_1 (0x2U << RTC_DR_YU_Pos) /*!< 0x00020000 */ #define RTC_DR_YU_2 (0x4U << RTC_DR_YU_Pos) /*!< 0x00040000 */ #define RTC_DR_YU_3 (0x8U << RTC_DR_YU_Pos) /*!< 0x00080000 */ #define RTC_DR_WDU_Pos (13U) #define RTC_DR_WDU_Msk (0x7U << RTC_DR_WDU_Pos) /*!< 0x0000E000 */ #define RTC_DR_WDU RTC_DR_WDU_Msk #define RTC_DR_WDU_0 (0x1U << RTC_DR_WDU_Pos) /*!< 0x00002000 */ #define RTC_DR_WDU_1 (0x2U << RTC_DR_WDU_Pos) /*!< 0x00004000 */ #define RTC_DR_WDU_2 (0x4U << RTC_DR_WDU_Pos) /*!< 0x00008000 */ #define RTC_DR_MT_Pos (12U) #define RTC_DR_MT_Msk (0x1U << RTC_DR_MT_Pos) /*!< 0x00001000 */ #define RTC_DR_MT RTC_DR_MT_Msk #define RTC_DR_MU_Pos (8U) #define RTC_DR_MU_Msk (0xFU << RTC_DR_MU_Pos) /*!< 0x00000F00 */ #define RTC_DR_MU RTC_DR_MU_Msk #define RTC_DR_MU_0 (0x1U << RTC_DR_MU_Pos) /*!< 0x00000100 */ #define RTC_DR_MU_1 (0x2U << RTC_DR_MU_Pos) /*!< 0x00000200 */ #define RTC_DR_MU_2 (0x4U << RTC_DR_MU_Pos) /*!< 0x00000400 */ #define RTC_DR_MU_3 (0x8U << RTC_DR_MU_Pos) /*!< 0x00000800 */ #define RTC_DR_DT_Pos (4U) #define RTC_DR_DT_Msk (0x3U << RTC_DR_DT_Pos) /*!< 0x00000030 */ #define RTC_DR_DT RTC_DR_DT_Msk #define RTC_DR_DT_0 (0x1U << RTC_DR_DT_Pos) /*!< 0x00000010 */ #define RTC_DR_DT_1 (0x2U << RTC_DR_DT_Pos) /*!< 0x00000020 */ #define RTC_DR_DU_Pos (0U) #define RTC_DR_DU_Msk (0xFU << RTC_DR_DU_Pos) /*!< 0x0000000F */ #define RTC_DR_DU RTC_DR_DU_Msk #define RTC_DR_DU_0 (0x1U << RTC_DR_DU_Pos) /*!< 0x00000001 */ #define RTC_DR_DU_1 (0x2U << RTC_DR_DU_Pos) /*!< 0x00000002 */ #define RTC_DR_DU_2 (0x4U << RTC_DR_DU_Pos) /*!< 0x00000004 */ #define RTC_DR_DU_3 (0x8U << RTC_DR_DU_Pos) /*!< 0x00000008 */ /******************** Bits definition for RTC_CR register *******************/ #define RTC_CR_COE_Pos (23U) #define RTC_CR_COE_Msk (0x1U << RTC_CR_COE_Pos) /*!< 0x00800000 */ #define RTC_CR_COE RTC_CR_COE_Msk #define RTC_CR_OSEL_Pos (21U) #define RTC_CR_OSEL_Msk (0x3U << RTC_CR_OSEL_Pos) /*!< 0x00600000 */ #define RTC_CR_OSEL RTC_CR_OSEL_Msk #define RTC_CR_OSEL_0 (0x1U << RTC_CR_OSEL_Pos) /*!< 0x00200000 */ #define RTC_CR_OSEL_1 (0x2U << RTC_CR_OSEL_Pos) /*!< 0x00400000 */ #define RTC_CR_POL_Pos (20U) #define RTC_CR_POL_Msk (0x1U << RTC_CR_POL_Pos) /*!< 0x00100000 */ #define RTC_CR_POL RTC_CR_POL_Msk #define RTC_CR_COSEL_Pos (19U) #define RTC_CR_COSEL_Msk (0x1U << RTC_CR_COSEL_Pos) /*!< 0x00080000 */ #define RTC_CR_COSEL RTC_CR_COSEL_Msk #define RTC_CR_BKP_Pos (18U) #define RTC_CR_BKP_Msk (0x1U << RTC_CR_BKP_Pos) /*!< 0x00040000 */ #define RTC_CR_BKP RTC_CR_BKP_Msk #define RTC_CR_SUB1H_Pos (17U) #define RTC_CR_SUB1H_Msk (0x1U << RTC_CR_SUB1H_Pos) /*!< 0x00020000 */ #define RTC_CR_SUB1H RTC_CR_SUB1H_Msk #define RTC_CR_ADD1H_Pos (16U) #define RTC_CR_ADD1H_Msk (0x1U << RTC_CR_ADD1H_Pos) /*!< 0x00010000 */ #define RTC_CR_ADD1H RTC_CR_ADD1H_Msk #define RTC_CR_TSIE_Pos (15U) #define RTC_CR_TSIE_Msk (0x1U << RTC_CR_TSIE_Pos) /*!< 0x00008000 */ #define RTC_CR_TSIE RTC_CR_TSIE_Msk #define RTC_CR_WUTIE_Pos (14U) #define RTC_CR_WUTIE_Msk (0x1U << RTC_CR_WUTIE_Pos) /*!< 0x00004000 */ #define RTC_CR_WUTIE RTC_CR_WUTIE_Msk #define RTC_CR_ALRBIE_Pos (13U) #define RTC_CR_ALRBIE_Msk (0x1U << RTC_CR_ALRBIE_Pos) /*!< 0x00002000 */ #define RTC_CR_ALRBIE RTC_CR_ALRBIE_Msk #define RTC_CR_ALRAIE_Pos (12U) #define RTC_CR_ALRAIE_Msk (0x1U << RTC_CR_ALRAIE_Pos) /*!< 0x00001000 */ #define RTC_CR_ALRAIE RTC_CR_ALRAIE_Msk #define RTC_CR_TSE_Pos (11U) #define RTC_CR_TSE_Msk (0x1U << RTC_CR_TSE_Pos) /*!< 0x00000800 */ #define RTC_CR_TSE RTC_CR_TSE_Msk #define RTC_CR_WUTE_Pos (10U) #define RTC_CR_WUTE_Msk (0x1U << RTC_CR_WUTE_Pos) /*!< 0x00000400 */ #define RTC_CR_WUTE RTC_CR_WUTE_Msk #define RTC_CR_ALRBE_Pos (9U) #define RTC_CR_ALRBE_Msk (0x1U << RTC_CR_ALRBE_Pos) /*!< 0x00000200 */ #define RTC_CR_ALRBE RTC_CR_ALRBE_Msk #define RTC_CR_ALRAE_Pos (8U) #define RTC_CR_ALRAE_Msk (0x1U << RTC_CR_ALRAE_Pos) /*!< 0x00000100 */ #define RTC_CR_ALRAE RTC_CR_ALRAE_Msk #define RTC_CR_DCE_Pos (7U) #define RTC_CR_DCE_Msk (0x1U << RTC_CR_DCE_Pos) /*!< 0x00000080 */ #define RTC_CR_DCE RTC_CR_DCE_Msk #define RTC_CR_FMT_Pos (6U) #define RTC_CR_FMT_Msk (0x1U << RTC_CR_FMT_Pos) /*!< 0x00000040 */ #define RTC_CR_FMT RTC_CR_FMT_Msk #define RTC_CR_BYPSHAD_Pos (5U) #define RTC_CR_BYPSHAD_Msk (0x1U << RTC_CR_BYPSHAD_Pos) /*!< 0x00000020 */ #define RTC_CR_BYPSHAD RTC_CR_BYPSHAD_Msk #define RTC_CR_REFCKON_Pos (4U) #define RTC_CR_REFCKON_Msk (0x1U << RTC_CR_REFCKON_Pos) /*!< 0x00000010 */ #define RTC_CR_REFCKON RTC_CR_REFCKON_Msk #define RTC_CR_TSEDGE_Pos (3U) #define RTC_CR_TSEDGE_Msk (0x1U << RTC_CR_TSEDGE_Pos) /*!< 0x00000008 */ #define RTC_CR_TSEDGE RTC_CR_TSEDGE_Msk #define RTC_CR_WUCKSEL_Pos (0U) #define RTC_CR_WUCKSEL_Msk (0x7U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000007 */ #define RTC_CR_WUCKSEL RTC_CR_WUCKSEL_Msk #define RTC_CR_WUCKSEL_0 (0x1U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000001 */ #define RTC_CR_WUCKSEL_1 (0x2U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000002 */ #define RTC_CR_WUCKSEL_2 (0x4U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000004 */ /* Legacy defines */ #define RTC_CR_BCK RTC_CR_BKP /******************** Bits definition for RTC_ISR register ******************/ #define RTC_ISR_RECALPF_Pos (16U) #define RTC_ISR_RECALPF_Msk (0x1U << RTC_ISR_RECALPF_Pos) /*!< 0x00010000 */ #define RTC_ISR_RECALPF RTC_ISR_RECALPF_Msk #define RTC_ISR_TAMP1F_Pos (13U) #define RTC_ISR_TAMP1F_Msk (0x1U << RTC_ISR_TAMP1F_Pos) /*!< 0x00002000 */ #define RTC_ISR_TAMP1F RTC_ISR_TAMP1F_Msk #define RTC_ISR_TAMP2F_Pos (14U) #define RTC_ISR_TAMP2F_Msk (0x1U << RTC_ISR_TAMP2F_Pos) /*!< 0x00004000 */ #define RTC_ISR_TAMP2F RTC_ISR_TAMP2F_Msk #define RTC_ISR_TSOVF_Pos (12U) #define RTC_ISR_TSOVF_Msk (0x1U << RTC_ISR_TSOVF_Pos) /*!< 0x00001000 */ #define RTC_ISR_TSOVF RTC_ISR_TSOVF_Msk #define RTC_ISR_TSF_Pos (11U) #define RTC_ISR_TSF_Msk (0x1U << RTC_ISR_TSF_Pos) /*!< 0x00000800 */ #define RTC_ISR_TSF RTC_ISR_TSF_Msk #define RTC_ISR_WUTF_Pos (10U) #define RTC_ISR_WUTF_Msk (0x1U << RTC_ISR_WUTF_Pos) /*!< 0x00000400 */ #define RTC_ISR_WUTF RTC_ISR_WUTF_Msk #define RTC_ISR_ALRBF_Pos (9U) #define RTC_ISR_ALRBF_Msk (0x1U << RTC_ISR_ALRBF_Pos) /*!< 0x00000200 */ #define RTC_ISR_ALRBF RTC_ISR_ALRBF_Msk #define RTC_ISR_ALRAF_Pos (8U) #define RTC_ISR_ALRAF_Msk (0x1U << RTC_ISR_ALRAF_Pos) /*!< 0x00000100 */ #define RTC_ISR_ALRAF RTC_ISR_ALRAF_Msk #define RTC_ISR_INIT_Pos (7U) #define RTC_ISR_INIT_Msk (0x1U << RTC_ISR_INIT_Pos) /*!< 0x00000080 */ #define RTC_ISR_INIT RTC_ISR_INIT_Msk #define RTC_ISR_INITF_Pos (6U) #define RTC_ISR_INITF_Msk (0x1U << RTC_ISR_INITF_Pos) /*!< 0x00000040 */ #define RTC_ISR_INITF RTC_ISR_INITF_Msk #define RTC_ISR_RSF_Pos (5U) #define RTC_ISR_RSF_Msk (0x1U << RTC_ISR_RSF_Pos) /*!< 0x00000020 */ #define RTC_ISR_RSF RTC_ISR_RSF_Msk #define RTC_ISR_INITS_Pos (4U) #define RTC_ISR_INITS_Msk (0x1U << RTC_ISR_INITS_Pos) /*!< 0x00000010 */ #define RTC_ISR_INITS RTC_ISR_INITS_Msk #define RTC_ISR_SHPF_Pos (3U) #define RTC_ISR_SHPF_Msk (0x1U << RTC_ISR_SHPF_Pos) /*!< 0x00000008 */ #define RTC_ISR_SHPF RTC_ISR_SHPF_Msk #define RTC_ISR_WUTWF_Pos (2U) #define RTC_ISR_WUTWF_Msk (0x1U << RTC_ISR_WUTWF_Pos) /*!< 0x00000004 */ #define RTC_ISR_WUTWF RTC_ISR_WUTWF_Msk #define RTC_ISR_ALRBWF_Pos (1U) #define RTC_ISR_ALRBWF_Msk (0x1U << RTC_ISR_ALRBWF_Pos) /*!< 0x00000002 */ #define RTC_ISR_ALRBWF RTC_ISR_ALRBWF_Msk #define RTC_ISR_ALRAWF_Pos (0U) #define RTC_ISR_ALRAWF_Msk (0x1U << RTC_ISR_ALRAWF_Pos) /*!< 0x00000001 */ #define RTC_ISR_ALRAWF RTC_ISR_ALRAWF_Msk /******************** Bits definition for RTC_PRER register *****************/ #define RTC_PRER_PREDIV_A_Pos (16U) #define RTC_PRER_PREDIV_A_Msk (0x7FU << RTC_PRER_PREDIV_A_Pos) /*!< 0x007F0000 */ #define RTC_PRER_PREDIV_A RTC_PRER_PREDIV_A_Msk #define RTC_PRER_PREDIV_S_Pos (0U) #define RTC_PRER_PREDIV_S_Msk (0x7FFFU << RTC_PRER_PREDIV_S_Pos) /*!< 0x00007FFF */ #define RTC_PRER_PREDIV_S RTC_PRER_PREDIV_S_Msk /******************** Bits definition for RTC_WUTR register *****************/ #define RTC_WUTR_WUT_Pos (0U) #define RTC_WUTR_WUT_Msk (0xFFFFU << RTC_WUTR_WUT_Pos) /*!< 0x0000FFFF */ #define RTC_WUTR_WUT RTC_WUTR_WUT_Msk /******************** Bits definition for RTC_CALIBR register ***************/ #define RTC_CALIBR_DCS_Pos (7U) #define RTC_CALIBR_DCS_Msk (0x1U << RTC_CALIBR_DCS_Pos) /*!< 0x00000080 */ #define RTC_CALIBR_DCS RTC_CALIBR_DCS_Msk #define RTC_CALIBR_DC_Pos (0U) #define RTC_CALIBR_DC_Msk (0x1FU << RTC_CALIBR_DC_Pos) /*!< 0x0000001F */ #define RTC_CALIBR_DC RTC_CALIBR_DC_Msk /******************** Bits definition for RTC_ALRMAR register ***************/ #define RTC_ALRMAR_MSK4_Pos (31U) #define RTC_ALRMAR_MSK4_Msk (0x1U << RTC_ALRMAR_MSK4_Pos) /*!< 0x80000000 */ #define RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk #define RTC_ALRMAR_WDSEL_Pos (30U) #define RTC_ALRMAR_WDSEL_Msk (0x1U << RTC_ALRMAR_WDSEL_Pos) /*!< 0x40000000 */ #define RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk #define RTC_ALRMAR_DT_Pos (28U) #define RTC_ALRMAR_DT_Msk (0x3U << RTC_ALRMAR_DT_Pos) /*!< 0x30000000 */ #define RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk #define RTC_ALRMAR_DT_0 (0x1U << RTC_ALRMAR_DT_Pos) /*!< 0x10000000 */ #define RTC_ALRMAR_DT_1 (0x2U << RTC_ALRMAR_DT_Pos) /*!< 0x20000000 */ #define RTC_ALRMAR_DU_Pos (24U) #define RTC_ALRMAR_DU_Msk (0xFU << RTC_ALRMAR_DU_Pos) /*!< 0x0F000000 */ #define RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk #define RTC_ALRMAR_DU_0 (0x1U << RTC_ALRMAR_DU_Pos) /*!< 0x01000000 */ #define RTC_ALRMAR_DU_1 (0x2U << RTC_ALRMAR_DU_Pos) /*!< 0x02000000 */ #define RTC_ALRMAR_DU_2 (0x4U << RTC_ALRMAR_DU_Pos) /*!< 0x04000000 */ #define RTC_ALRMAR_DU_3 (0x8U << RTC_ALRMAR_DU_Pos) /*!< 0x08000000 */ #define RTC_ALRMAR_MSK3_Pos (23U) #define RTC_ALRMAR_MSK3_Msk (0x1U << RTC_ALRMAR_MSK3_Pos) /*!< 0x00800000 */ #define RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk #define RTC_ALRMAR_PM_Pos (22U) #define RTC_ALRMAR_PM_Msk (0x1U << RTC_ALRMAR_PM_Pos) /*!< 0x00400000 */ #define RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk #define RTC_ALRMAR_HT_Pos (20U) #define RTC_ALRMAR_HT_Msk (0x3U << RTC_ALRMAR_HT_Pos) /*!< 0x00300000 */ #define RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk #define RTC_ALRMAR_HT_0 (0x1U << RTC_ALRMAR_HT_Pos) /*!< 0x00100000 */ #define RTC_ALRMAR_HT_1 (0x2U << RTC_ALRMAR_HT_Pos) /*!< 0x00200000 */ #define RTC_ALRMAR_HU_Pos (16U) #define RTC_ALRMAR_HU_Msk (0xFU << RTC_ALRMAR_HU_Pos) /*!< 0x000F0000 */ #define RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk #define RTC_ALRMAR_HU_0 (0x1U << RTC_ALRMAR_HU_Pos) /*!< 0x00010000 */ #define RTC_ALRMAR_HU_1 (0x2U << RTC_ALRMAR_HU_Pos) /*!< 0x00020000 */ #define RTC_ALRMAR_HU_2 (0x4U << RTC_ALRMAR_HU_Pos) /*!< 0x00040000 */ #define RTC_ALRMAR_HU_3 (0x8U << RTC_ALRMAR_HU_Pos) /*!< 0x00080000 */ #define RTC_ALRMAR_MSK2_Pos (15U) #define RTC_ALRMAR_MSK2_Msk (0x1U << RTC_ALRMAR_MSK2_Pos) /*!< 0x00008000 */ #define RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk #define RTC_ALRMAR_MNT_Pos (12U) #define RTC_ALRMAR_MNT_Msk (0x7U << RTC_ALRMAR_MNT_Pos) /*!< 0x00007000 */ #define RTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk #define RTC_ALRMAR_MNT_0 (0x1U << RTC_ALRMAR_MNT_Pos) /*!< 0x00001000 */ #define RTC_ALRMAR_MNT_1 (0x2U << RTC_ALRMAR_MNT_Pos) /*!< 0x00002000 */ #define RTC_ALRMAR_MNT_2 (0x4U << RTC_ALRMAR_MNT_Pos) /*!< 0x00004000 */ #define RTC_ALRMAR_MNU_Pos (8U) #define RTC_ALRMAR_MNU_Msk (0xFU << RTC_ALRMAR_MNU_Pos) /*!< 0x00000F00 */ #define RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk #define RTC_ALRMAR_MNU_0 (0x1U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000100 */ #define RTC_ALRMAR_MNU_1 (0x2U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000200 */ #define RTC_ALRMAR_MNU_2 (0x4U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000400 */ #define RTC_ALRMAR_MNU_3 (0x8U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000800 */ #define RTC_ALRMAR_MSK1_Pos (7U) #define RTC_ALRMAR_MSK1_Msk (0x1U << RTC_ALRMAR_MSK1_Pos) /*!< 0x00000080 */ #define RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_Msk #define RTC_ALRMAR_ST_Pos (4U) #define RTC_ALRMAR_ST_Msk (0x7U << RTC_ALRMAR_ST_Pos) /*!< 0x00000070 */ #define RTC_ALRMAR_ST RTC_ALRMAR_ST_Msk #define RTC_ALRMAR_ST_0 (0x1U << RTC_ALRMAR_ST_Pos) /*!< 0x00000010 */ #define RTC_ALRMAR_ST_1 (0x2U << RTC_ALRMAR_ST_Pos) /*!< 0x00000020 */ #define RTC_ALRMAR_ST_2 (0x4U << RTC_ALRMAR_ST_Pos) /*!< 0x00000040 */ #define RTC_ALRMAR_SU_Pos (0U) #define RTC_ALRMAR_SU_Msk (0xFU << RTC_ALRMAR_SU_Pos) /*!< 0x0000000F */ #define RTC_ALRMAR_SU RTC_ALRMAR_SU_Msk #define RTC_ALRMAR_SU_0 (0x1U << RTC_ALRMAR_SU_Pos) /*!< 0x00000001 */ #define RTC_ALRMAR_SU_1 (0x2U << RTC_ALRMAR_SU_Pos) /*!< 0x00000002 */ #define RTC_ALRMAR_SU_2 (0x4U << RTC_ALRMAR_SU_Pos) /*!< 0x00000004 */ #define RTC_ALRMAR_SU_3 (0x8U << RTC_ALRMAR_SU_Pos) /*!< 0x00000008 */ /******************** Bits definition for RTC_ALRMBR register ***************/ #define RTC_ALRMBR_MSK4_Pos (31U) #define RTC_ALRMBR_MSK4_Msk (0x1U << RTC_ALRMBR_MSK4_Pos) /*!< 0x80000000 */ #define RTC_ALRMBR_MSK4 RTC_ALRMBR_MSK4_Msk #define RTC_ALRMBR_WDSEL_Pos (30U) #define RTC_ALRMBR_WDSEL_Msk (0x1U << RTC_ALRMBR_WDSEL_Pos) /*!< 0x40000000 */ #define RTC_ALRMBR_WDSEL RTC_ALRMBR_WDSEL_Msk #define RTC_ALRMBR_DT_Pos (28U) #define RTC_ALRMBR_DT_Msk (0x3U << RTC_ALRMBR_DT_Pos) /*!< 0x30000000 */ #define RTC_ALRMBR_DT RTC_ALRMBR_DT_Msk #define RTC_ALRMBR_DT_0 (0x1U << RTC_ALRMBR_DT_Pos) /*!< 0x10000000 */ #define RTC_ALRMBR_DT_1 (0x2U << RTC_ALRMBR_DT_Pos) /*!< 0x20000000 */ #define RTC_ALRMBR_DU_Pos (24U) #define RTC_ALRMBR_DU_Msk (0xFU << RTC_ALRMBR_DU_Pos) /*!< 0x0F000000 */ #define RTC_ALRMBR_DU RTC_ALRMBR_DU_Msk #define RTC_ALRMBR_DU_0 (0x1U << RTC_ALRMBR_DU_Pos) /*!< 0x01000000 */ #define RTC_ALRMBR_DU_1 (0x2U << RTC_ALRMBR_DU_Pos) /*!< 0x02000000 */ #define RTC_ALRMBR_DU_2 (0x4U << RTC_ALRMBR_DU_Pos) /*!< 0x04000000 */ #define RTC_ALRMBR_DU_3 (0x8U << RTC_ALRMBR_DU_Pos) /*!< 0x08000000 */ #define RTC_ALRMBR_MSK3_Pos (23U) #define RTC_ALRMBR_MSK3_Msk (0x1U << RTC_ALRMBR_MSK3_Pos) /*!< 0x00800000 */ #define RTC_ALRMBR_MSK3 RTC_ALRMBR_MSK3_Msk #define RTC_ALRMBR_PM_Pos (22U) #define RTC_ALRMBR_PM_Msk (0x1U << RTC_ALRMBR_PM_Pos) /*!< 0x00400000 */ #define RTC_ALRMBR_PM RTC_ALRMBR_PM_Msk #define RTC_ALRMBR_HT_Pos (20U) #define RTC_ALRMBR_HT_Msk (0x3U << RTC_ALRMBR_HT_Pos) /*!< 0x00300000 */ #define RTC_ALRMBR_HT RTC_ALRMBR_HT_Msk #define RTC_ALRMBR_HT_0 (0x1U << RTC_ALRMBR_HT_Pos) /*!< 0x00100000 */ #define RTC_ALRMBR_HT_1 (0x2U << RTC_ALRMBR_HT_Pos) /*!< 0x00200000 */ #define RTC_ALRMBR_HU_Pos (16U) #define RTC_ALRMBR_HU_Msk (0xFU << RTC_ALRMBR_HU_Pos) /*!< 0x000F0000 */ #define RTC_ALRMBR_HU RTC_ALRMBR_HU_Msk #define RTC_ALRMBR_HU_0 (0x1U << RTC_ALRMBR_HU_Pos) /*!< 0x00010000 */ #define RTC_ALRMBR_HU_1 (0x2U << RTC_ALRMBR_HU_Pos) /*!< 0x00020000 */ #define RTC_ALRMBR_HU_2 (0x4U << RTC_ALRMBR_HU_Pos) /*!< 0x00040000 */ #define RTC_ALRMBR_HU_3 (0x8U << RTC_ALRMBR_HU_Pos) /*!< 0x00080000 */ #define RTC_ALRMBR_MSK2_Pos (15U) #define RTC_ALRMBR_MSK2_Msk (0x1U << RTC_ALRMBR_MSK2_Pos) /*!< 0x00008000 */ #define RTC_ALRMBR_MSK2 RTC_ALRMBR_MSK2_Msk #define RTC_ALRMBR_MNT_Pos (12U) #define RTC_ALRMBR_MNT_Msk (0x7U << RTC_ALRMBR_MNT_Pos) /*!< 0x00007000 */ #define RTC_ALRMBR_MNT RTC_ALRMBR_MNT_Msk #define RTC_ALRMBR_MNT_0 (0x1U << RTC_ALRMBR_MNT_Pos) /*!< 0x00001000 */ #define RTC_ALRMBR_MNT_1 (0x2U << RTC_ALRMBR_MNT_Pos) /*!< 0x00002000 */ #define RTC_ALRMBR_MNT_2 (0x4U << RTC_ALRMBR_MNT_Pos) /*!< 0x00004000 */ #define RTC_ALRMBR_MNU_Pos (8U) #define RTC_ALRMBR_MNU_Msk (0xFU << RTC_ALRMBR_MNU_Pos) /*!< 0x00000F00 */ #define RTC_ALRMBR_MNU RTC_ALRMBR_MNU_Msk #define RTC_ALRMBR_MNU_0 (0x1U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000100 */ #define RTC_ALRMBR_MNU_1 (0x2U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000200 */ #define RTC_ALRMBR_MNU_2 (0x4U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000400 */ #define RTC_ALRMBR_MNU_3 (0x8U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000800 */ #define RTC_ALRMBR_MSK1_Pos (7U) #define RTC_ALRMBR_MSK1_Msk (0x1U << RTC_ALRMBR_MSK1_Pos) /*!< 0x00000080 */ #define RTC_ALRMBR_MSK1 RTC_ALRMBR_MSK1_Msk #define RTC_ALRMBR_ST_Pos (4U) #define RTC_ALRMBR_ST_Msk (0x7U << RTC_ALRMBR_ST_Pos) /*!< 0x00000070 */ #define RTC_ALRMBR_ST RTC_ALRMBR_ST_Msk #define RTC_ALRMBR_ST_0 (0x1U << RTC_ALRMBR_ST_Pos) /*!< 0x00000010 */ #define RTC_ALRMBR_ST_1 (0x2U << RTC_ALRMBR_ST_Pos) /*!< 0x00000020 */ #define RTC_ALRMBR_ST_2 (0x4U << RTC_ALRMBR_ST_Pos) /*!< 0x00000040 */ #define RTC_ALRMBR_SU_Pos (0U) #define RTC_ALRMBR_SU_Msk (0xFU << RTC_ALRMBR_SU_Pos) /*!< 0x0000000F */ #define RTC_ALRMBR_SU RTC_ALRMBR_SU_Msk #define RTC_ALRMBR_SU_0 (0x1U << RTC_ALRMBR_SU_Pos) /*!< 0x00000001 */ #define RTC_ALRMBR_SU_1 (0x2U << RTC_ALRMBR_SU_Pos) /*!< 0x00000002 */ #define RTC_ALRMBR_SU_2 (0x4U << RTC_ALRMBR_SU_Pos) /*!< 0x00000004 */ #define RTC_ALRMBR_SU_3 (0x8U << RTC_ALRMBR_SU_Pos) /*!< 0x00000008 */ /******************** Bits definition for RTC_WPR register ******************/ #define RTC_WPR_KEY_Pos (0U) #define RTC_WPR_KEY_Msk (0xFFU << RTC_WPR_KEY_Pos) /*!< 0x000000FF */ #define RTC_WPR_KEY RTC_WPR_KEY_Msk /******************** Bits definition for RTC_SSR register ******************/ #define RTC_SSR_SS_Pos (0U) #define RTC_SSR_SS_Msk (0xFFFFU << RTC_SSR_SS_Pos) /*!< 0x0000FFFF */ #define RTC_SSR_SS RTC_SSR_SS_Msk /******************** Bits definition for RTC_SHIFTR register ***************/ #define RTC_SHIFTR_SUBFS_Pos (0U) #define RTC_SHIFTR_SUBFS_Msk (0x7FFFU << RTC_SHIFTR_SUBFS_Pos) /*!< 0x00007FFF */ #define RTC_SHIFTR_SUBFS RTC_SHIFTR_SUBFS_Msk #define RTC_SHIFTR_ADD1S_Pos (31U) #define RTC_SHIFTR_ADD1S_Msk (0x1U << RTC_SHIFTR_ADD1S_Pos) /*!< 0x80000000 */ #define RTC_SHIFTR_ADD1S RTC_SHIFTR_ADD1S_Msk /******************** Bits definition for RTC_TSTR register *****************/ #define RTC_TSTR_PM_Pos (22U) #define RTC_TSTR_PM_Msk (0x1U << RTC_TSTR_PM_Pos) /*!< 0x00400000 */ #define RTC_TSTR_PM RTC_TSTR_PM_Msk #define RTC_TSTR_HT_Pos (20U) #define RTC_TSTR_HT_Msk (0x3U << RTC_TSTR_HT_Pos) /*!< 0x00300000 */ #define RTC_TSTR_HT RTC_TSTR_HT_Msk #define RTC_TSTR_HT_0 (0x1U << RTC_TSTR_HT_Pos) /*!< 0x00100000 */ #define RTC_TSTR_HT_1 (0x2U << RTC_TSTR_HT_Pos) /*!< 0x00200000 */ #define RTC_TSTR_HU_Pos (16U) #define RTC_TSTR_HU_Msk (0xFU << RTC_TSTR_HU_Pos) /*!< 0x000F0000 */ #define RTC_TSTR_HU RTC_TSTR_HU_Msk #define RTC_TSTR_HU_0 (0x1U << RTC_TSTR_HU_Pos) /*!< 0x00010000 */ #define RTC_TSTR_HU_1 (0x2U << RTC_TSTR_HU_Pos) /*!< 0x00020000 */ #define RTC_TSTR_HU_2 (0x4U << RTC_TSTR_HU_Pos) /*!< 0x00040000 */ #define RTC_TSTR_HU_3 (0x8U << RTC_TSTR_HU_Pos) /*!< 0x00080000 */ #define RTC_TSTR_MNT_Pos (12U) #define RTC_TSTR_MNT_Msk (0x7U << RTC_TSTR_MNT_Pos) /*!< 0x00007000 */ #define RTC_TSTR_MNT RTC_TSTR_MNT_Msk #define RTC_TSTR_MNT_0 (0x1U << RTC_TSTR_MNT_Pos) /*!< 0x00001000 */ #define RTC_TSTR_MNT_1 (0x2U << RTC_TSTR_MNT_Pos) /*!< 0x00002000 */ #define RTC_TSTR_MNT_2 (0x4U << RTC_TSTR_MNT_Pos) /*!< 0x00004000 */ #define RTC_TSTR_MNU_Pos (8U) #define RTC_TSTR_MNU_Msk (0xFU << RTC_TSTR_MNU_Pos) /*!< 0x00000F00 */ #define RTC_TSTR_MNU RTC_TSTR_MNU_Msk #define RTC_TSTR_MNU_0 (0x1U << RTC_TSTR_MNU_Pos) /*!< 0x00000100 */ #define RTC_TSTR_MNU_1 (0x2U << RTC_TSTR_MNU_Pos) /*!< 0x00000200 */ #define RTC_TSTR_MNU_2 (0x4U << RTC_TSTR_MNU_Pos) /*!< 0x00000400 */ #define RTC_TSTR_MNU_3 (0x8U << RTC_TSTR_MNU_Pos) /*!< 0x00000800 */ #define RTC_TSTR_ST_Pos (4U) #define RTC_TSTR_ST_Msk (0x7U << RTC_TSTR_ST_Pos) /*!< 0x00000070 */ #define RTC_TSTR_ST RTC_TSTR_ST_Msk #define RTC_TSTR_ST_0 (0x1U << RTC_TSTR_ST_Pos) /*!< 0x00000010 */ #define RTC_TSTR_ST_1 (0x2U << RTC_TSTR_ST_Pos) /*!< 0x00000020 */ #define RTC_TSTR_ST_2 (0x4U << RTC_TSTR_ST_Pos) /*!< 0x00000040 */ #define RTC_TSTR_SU_Pos (0U) #define RTC_TSTR_SU_Msk (0xFU << RTC_TSTR_SU_Pos) /*!< 0x0000000F */ #define RTC_TSTR_SU RTC_TSTR_SU_Msk #define RTC_TSTR_SU_0 (0x1U << RTC_TSTR_SU_Pos) /*!< 0x00000001 */ #define RTC_TSTR_SU_1 (0x2U << RTC_TSTR_SU_Pos) /*!< 0x00000002 */ #define RTC_TSTR_SU_2 (0x4U << RTC_TSTR_SU_Pos) /*!< 0x00000004 */ #define RTC_TSTR_SU_3 (0x8U << RTC_TSTR_SU_Pos) /*!< 0x00000008 */ /******************** Bits definition for RTC_TSDR register *****************/ #define RTC_TSDR_WDU_Pos (13U) #define RTC_TSDR_WDU_Msk (0x7U << RTC_TSDR_WDU_Pos) /*!< 0x0000E000 */ #define RTC_TSDR_WDU RTC_TSDR_WDU_Msk #define RTC_TSDR_WDU_0 (0x1U << RTC_TSDR_WDU_Pos) /*!< 0x00002000 */ #define RTC_TSDR_WDU_1 (0x2U << RTC_TSDR_WDU_Pos) /*!< 0x00004000 */ #define RTC_TSDR_WDU_2 (0x4U << RTC_TSDR_WDU_Pos) /*!< 0x00008000 */ #define RTC_TSDR_MT_Pos (12U) #define RTC_TSDR_MT_Msk (0x1U << RTC_TSDR_MT_Pos) /*!< 0x00001000 */ #define RTC_TSDR_MT RTC_TSDR_MT_Msk #define RTC_TSDR_MU_Pos (8U) #define RTC_TSDR_MU_Msk (0xFU << RTC_TSDR_MU_Pos) /*!< 0x00000F00 */ #define RTC_TSDR_MU RTC_TSDR_MU_Msk #define RTC_TSDR_MU_0 (0x1U << RTC_TSDR_MU_Pos) /*!< 0x00000100 */ #define RTC_TSDR_MU_1 (0x2U << RTC_TSDR_MU_Pos) /*!< 0x00000200 */ #define RTC_TSDR_MU_2 (0x4U << RTC_TSDR_MU_Pos) /*!< 0x00000400 */ #define RTC_TSDR_MU_3 (0x8U << RTC_TSDR_MU_Pos) /*!< 0x00000800 */ #define RTC_TSDR_DT_Pos (4U) #define RTC_TSDR_DT_Msk (0x3U << RTC_TSDR_DT_Pos) /*!< 0x00000030 */ #define RTC_TSDR_DT RTC_TSDR_DT_Msk #define RTC_TSDR_DT_0 (0x1U << RTC_TSDR_DT_Pos) /*!< 0x00000010 */ #define RTC_TSDR_DT_1 (0x2U << RTC_TSDR_DT_Pos) /*!< 0x00000020 */ #define RTC_TSDR_DU_Pos (0U) #define RTC_TSDR_DU_Msk (0xFU << RTC_TSDR_DU_Pos) /*!< 0x0000000F */ #define RTC_TSDR_DU RTC_TSDR_DU_Msk #define RTC_TSDR_DU_0 (0x1U << RTC_TSDR_DU_Pos) /*!< 0x00000001 */ #define RTC_TSDR_DU_1 (0x2U << RTC_TSDR_DU_Pos) /*!< 0x00000002 */ #define RTC_TSDR_DU_2 (0x4U << RTC_TSDR_DU_Pos) /*!< 0x00000004 */ #define RTC_TSDR_DU_3 (0x8U << RTC_TSDR_DU_Pos) /*!< 0x00000008 */ /******************** Bits definition for RTC_TSSSR register ****************/ #define RTC_TSSSR_SS_Pos (0U) #define RTC_TSSSR_SS_Msk (0xFFFFU << RTC_TSSSR_SS_Pos) /*!< 0x0000FFFF */ #define RTC_TSSSR_SS RTC_TSSSR_SS_Msk /******************** Bits definition for RTC_CAL register *****************/ #define RTC_CALR_CALP_Pos (15U) #define RTC_CALR_CALP_Msk (0x1U << RTC_CALR_CALP_Pos) /*!< 0x00008000 */ #define RTC_CALR_CALP RTC_CALR_CALP_Msk #define RTC_CALR_CALW8_Pos (14U) #define RTC_CALR_CALW8_Msk (0x1U << RTC_CALR_CALW8_Pos) /*!< 0x00004000 */ #define RTC_CALR_CALW8 RTC_CALR_CALW8_Msk #define RTC_CALR_CALW16_Pos (13U) #define RTC_CALR_CALW16_Msk (0x1U << RTC_CALR_CALW16_Pos) /*!< 0x00002000 */ #define RTC_CALR_CALW16 RTC_CALR_CALW16_Msk #define RTC_CALR_CALM_Pos (0U) #define RTC_CALR_CALM_Msk (0x1FFU << RTC_CALR_CALM_Pos) /*!< 0x000001FF */ #define RTC_CALR_CALM RTC_CALR_CALM_Msk #define RTC_CALR_CALM_0 (0x001U << RTC_CALR_CALM_Pos) /*!< 0x00000001 */ #define RTC_CALR_CALM_1 (0x002U << RTC_CALR_CALM_Pos) /*!< 0x00000002 */ #define RTC_CALR_CALM_2 (0x004U << RTC_CALR_CALM_Pos) /*!< 0x00000004 */ #define RTC_CALR_CALM_3 (0x008U << RTC_CALR_CALM_Pos) /*!< 0x00000008 */ #define RTC_CALR_CALM_4 (0x010U << RTC_CALR_CALM_Pos) /*!< 0x00000010 */ #define RTC_CALR_CALM_5 (0x020U << RTC_CALR_CALM_Pos) /*!< 0x00000020 */ #define RTC_CALR_CALM_6 (0x040U << RTC_CALR_CALM_Pos) /*!< 0x00000040 */ #define RTC_CALR_CALM_7 (0x080U << RTC_CALR_CALM_Pos) /*!< 0x00000080 */ #define RTC_CALR_CALM_8 (0x100U << RTC_CALR_CALM_Pos) /*!< 0x00000100 */ /******************** Bits definition for RTC_TAFCR register ****************/ #define RTC_TAFCR_ALARMOUTTYPE_Pos (18U) #define RTC_TAFCR_ALARMOUTTYPE_Msk (0x1U << RTC_TAFCR_ALARMOUTTYPE_Pos) /*!< 0x00040000 */ #define RTC_TAFCR_ALARMOUTTYPE RTC_TAFCR_ALARMOUTTYPE_Msk #define RTC_TAFCR_TSINSEL_Pos (17U) #define RTC_TAFCR_TSINSEL_Msk (0x1U << RTC_TAFCR_TSINSEL_Pos) /*!< 0x00020000 */ #define RTC_TAFCR_TSINSEL RTC_TAFCR_TSINSEL_Msk #define RTC_TAFCR_TAMP1INSEL_Pos (16U) #define RTC_TAFCR_TAMP1INSEL_Msk (0x1U << RTC_TAFCR_TAMP1INSEL_Pos) /*!< 0x00010000 */ #define RTC_TAFCR_TAMP1INSEL RTC_TAFCR_TAMP1INSEL_Msk #define RTC_TAFCR_TAMPPUDIS_Pos (15U) #define RTC_TAFCR_TAMPPUDIS_Msk (0x1U << RTC_TAFCR_TAMPPUDIS_Pos) /*!< 0x00008000 */ #define RTC_TAFCR_TAMPPUDIS RTC_TAFCR_TAMPPUDIS_Msk #define RTC_TAFCR_TAMPPRCH_Pos (13U) #define RTC_TAFCR_TAMPPRCH_Msk (0x3U << RTC_TAFCR_TAMPPRCH_Pos) /*!< 0x00006000 */ #define RTC_TAFCR_TAMPPRCH RTC_TAFCR_TAMPPRCH_Msk #define RTC_TAFCR_TAMPPRCH_0 (0x1U << RTC_TAFCR_TAMPPRCH_Pos) /*!< 0x00002000 */ #define RTC_TAFCR_TAMPPRCH_1 (0x2U << RTC_TAFCR_TAMPPRCH_Pos) /*!< 0x00004000 */ #define RTC_TAFCR_TAMPFLT_Pos (11U) #define RTC_TAFCR_TAMPFLT_Msk (0x3U << RTC_TAFCR_TAMPFLT_Pos) /*!< 0x00001800 */ #define RTC_TAFCR_TAMPFLT RTC_TAFCR_TAMPFLT_Msk #define RTC_TAFCR_TAMPFLT_0 (0x1U << RTC_TAFCR_TAMPFLT_Pos) /*!< 0x00000800 */ #define RTC_TAFCR_TAMPFLT_1 (0x2U << RTC_TAFCR_TAMPFLT_Pos) /*!< 0x00001000 */ #define RTC_TAFCR_TAMPFREQ_Pos (8U) #define RTC_TAFCR_TAMPFREQ_Msk (0x7U << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000700 */ #define RTC_TAFCR_TAMPFREQ RTC_TAFCR_TAMPFREQ_Msk #define RTC_TAFCR_TAMPFREQ_0 (0x1U << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000100 */ #define RTC_TAFCR_TAMPFREQ_1 (0x2U << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000200 */ #define RTC_TAFCR_TAMPFREQ_2 (0x4U << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000400 */ #define RTC_TAFCR_TAMPTS_Pos (7U) #define RTC_TAFCR_TAMPTS_Msk (0x1U << RTC_TAFCR_TAMPTS_Pos) /*!< 0x00000080 */ #define RTC_TAFCR_TAMPTS RTC_TAFCR_TAMPTS_Msk #define RTC_TAFCR_TAMP2TRG_Pos (4U) #define RTC_TAFCR_TAMP2TRG_Msk (0x1U << RTC_TAFCR_TAMP2TRG_Pos) /*!< 0x00000010 */ #define RTC_TAFCR_TAMP2TRG RTC_TAFCR_TAMP2TRG_Msk #define RTC_TAFCR_TAMP2E_Pos (3U) #define RTC_TAFCR_TAMP2E_Msk (0x1U << RTC_TAFCR_TAMP2E_Pos) /*!< 0x00000008 */ #define RTC_TAFCR_TAMP2E RTC_TAFCR_TAMP2E_Msk #define RTC_TAFCR_TAMPIE_Pos (2U) #define RTC_TAFCR_TAMPIE_Msk (0x1U << RTC_TAFCR_TAMPIE_Pos) /*!< 0x00000004 */ #define RTC_TAFCR_TAMPIE RTC_TAFCR_TAMPIE_Msk #define RTC_TAFCR_TAMP1TRG_Pos (1U) #define RTC_TAFCR_TAMP1TRG_Msk (0x1U << RTC_TAFCR_TAMP1TRG_Pos) /*!< 0x00000002 */ #define RTC_TAFCR_TAMP1TRG RTC_TAFCR_TAMP1TRG_Msk #define RTC_TAFCR_TAMP1E_Pos (0U) #define RTC_TAFCR_TAMP1E_Msk (0x1U << RTC_TAFCR_TAMP1E_Pos) /*!< 0x00000001 */ #define RTC_TAFCR_TAMP1E RTC_TAFCR_TAMP1E_Msk /* Legacy defines */ #define RTC_TAFCR_TAMPINSEL RTC_TAFCR_TAMP1INSEL /******************** Bits definition for RTC_ALRMASSR register *************/ #define RTC_ALRMASSR_MASKSS_Pos (24U) #define RTC_ALRMASSR_MASKSS_Msk (0xFU << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x0F000000 */ #define RTC_ALRMASSR_MASKSS RTC_ALRMASSR_MASKSS_Msk #define RTC_ALRMASSR_MASKSS_0 (0x1U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x01000000 */ #define RTC_ALRMASSR_MASKSS_1 (0x2U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x02000000 */ #define RTC_ALRMASSR_MASKSS_2 (0x4U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x04000000 */ #define RTC_ALRMASSR_MASKSS_3 (0x8U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x08000000 */ #define RTC_ALRMASSR_SS_Pos (0U) #define RTC_ALRMASSR_SS_Msk (0x7FFFU << RTC_ALRMASSR_SS_Pos) /*!< 0x00007FFF */ #define RTC_ALRMASSR_SS RTC_ALRMASSR_SS_Msk /******************** Bits definition for RTC_ALRMBSSR register *************/ #define RTC_ALRMBSSR_MASKSS_Pos (24U) #define RTC_ALRMBSSR_MASKSS_Msk (0xFU << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x0F000000 */ #define RTC_ALRMBSSR_MASKSS RTC_ALRMBSSR_MASKSS_Msk #define RTC_ALRMBSSR_MASKSS_0 (0x1U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x01000000 */ #define RTC_ALRMBSSR_MASKSS_1 (0x2U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x02000000 */ #define RTC_ALRMBSSR_MASKSS_2 (0x4U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x04000000 */ #define RTC_ALRMBSSR_MASKSS_3 (0x8U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x08000000 */ #define RTC_ALRMBSSR_SS_Pos (0U) #define RTC_ALRMBSSR_SS_Msk (0x7FFFU << RTC_ALRMBSSR_SS_Pos) /*!< 0x00007FFF */ #define RTC_ALRMBSSR_SS RTC_ALRMBSSR_SS_Msk /******************** Bits definition for RTC_BKP0R register ****************/ #define RTC_BKP0R_Pos (0U) #define RTC_BKP0R_Msk (0xFFFFFFFFU << RTC_BKP0R_Pos) /*!< 0xFFFFFFFF */ #define RTC_BKP0R RTC_BKP0R_Msk /******************** Bits definition for RTC_BKP1R register ****************/ #define RTC_BKP1R_Pos (0U) #define RTC_BKP1R_Msk (0xFFFFFFFFU << RTC_BKP1R_Pos) /*!< 0xFFFFFFFF */ #define RTC_BKP1R RTC_BKP1R_Msk /******************** Bits definition for RTC_BKP2R register ****************/ #define RTC_BKP2R_Pos (0U) #define RTC_BKP2R_Msk (0xFFFFFFFFU << RTC_BKP2R_Pos) /*!< 0xFFFFFFFF */ #define RTC_BKP2R RTC_BKP2R_Msk /******************** Bits definition for RTC_BKP3R register ****************/ #define RTC_BKP3R_Pos (0U) #define RTC_BKP3R_Msk (0xFFFFFFFFU << RTC_BKP3R_Pos) /*!< 0xFFFFFFFF */ #define RTC_BKP3R RTC_BKP3R_Msk /******************** Bits definition for RTC_BKP4R register ****************/ #define RTC_BKP4R_Pos (0U) #define RTC_BKP4R_Msk (0xFFFFFFFFU << RTC_BKP4R_Pos) /*!< 0xFFFFFFFF */ #define RTC_BKP4R RTC_BKP4R_Msk /******************** Bits definition for RTC_BKP5R register ****************/ #define RTC_BKP5R_Pos (0U) #define RTC_BKP5R_Msk (0xFFFFFFFFU << RTC_BKP5R_Pos) /*!< 0xFFFFFFFF */ #define RTC_BKP5R RTC_BKP5R_Msk /******************** Bits definition for RTC_BKP6R register ****************/ #define RTC_BKP6R_Pos (0U) #define RTC_BKP6R_Msk (0xFFFFFFFFU << RTC_BKP6R_Pos) /*!< 0xFFFFFFFF */ #define RTC_BKP6R RTC_BKP6R_Msk /******************** Bits definition for RTC_BKP7R register ****************/ #define RTC_BKP7R_Pos (0U) #define RTC_BKP7R_Msk (0xFFFFFFFFU << RTC_BKP7R_Pos) /*!< 0xFFFFFFFF */ #define RTC_BKP7R RTC_BKP7R_Msk /******************** Bits definition for RTC_BKP8R register ****************/ #define RTC_BKP8R_Pos (0U) #define RTC_BKP8R_Msk (0xFFFFFFFFU << RTC_BKP8R_Pos) /*!< 0xFFFFFFFF */ #define RTC_BKP8R RTC_BKP8R_Msk /******************** Bits definition for RTC_BKP9R register ****************/ #define RTC_BKP9R_Pos (0U) #define RTC_BKP9R_Msk (0xFFFFFFFFU << RTC_BKP9R_Pos) /*!< 0xFFFFFFFF */ #define RTC_BKP9R RTC_BKP9R_Msk /******************** Bits definition for RTC_BKP10R register ***************/ #define RTC_BKP10R_Pos (0U) #define RTC_BKP10R_Msk (0xFFFFFFFFU << RTC_BKP10R_Pos) /*!< 0xFFFFFFFF */ #define RTC_BKP10R RTC_BKP10R_Msk /******************** Bits definition for RTC_BKP11R register ***************/ #define RTC_BKP11R_Pos (0U) #define RTC_BKP11R_Msk (0xFFFFFFFFU << RTC_BKP11R_Pos) /*!< 0xFFFFFFFF */ #define RTC_BKP11R RTC_BKP11R_Msk /******************** Bits definition for RTC_BKP12R register ***************/ #define RTC_BKP12R_Pos (0U) #define RTC_BKP12R_Msk (0xFFFFFFFFU << RTC_BKP12R_Pos) /*!< 0xFFFFFFFF */ #define RTC_BKP12R RTC_BKP12R_Msk /******************** Bits definition for RTC_BKP13R register ***************/ #define RTC_BKP13R_Pos (0U) #define RTC_BKP13R_Msk (0xFFFFFFFFU << RTC_BKP13R_Pos) /*!< 0xFFFFFFFF */ #define RTC_BKP13R RTC_BKP13R_Msk /******************** Bits definition for RTC_BKP14R register ***************/ #define RTC_BKP14R_Pos (0U) #define RTC_BKP14R_Msk (0xFFFFFFFFU << RTC_BKP14R_Pos) /*!< 0xFFFFFFFF */ #define RTC_BKP14R RTC_BKP14R_Msk /******************** Bits definition for RTC_BKP15R register ***************/ #define RTC_BKP15R_Pos (0U) #define RTC_BKP15R_Msk (0xFFFFFFFFU << RTC_BKP15R_Pos) /*!< 0xFFFFFFFF */ #define RTC_BKP15R RTC_BKP15R_Msk /******************** Bits definition for RTC_BKP16R register ***************/ #define RTC_BKP16R_Pos (0U) #define RTC_BKP16R_Msk (0xFFFFFFFFU << RTC_BKP16R_Pos) /*!< 0xFFFFFFFF */ #define RTC_BKP16R RTC_BKP16R_Msk /******************** Bits definition for RTC_BKP17R register ***************/ #define RTC_BKP17R_Pos (0U) #define RTC_BKP17R_Msk (0xFFFFFFFFU << RTC_BKP17R_Pos) /*!< 0xFFFFFFFF */ #define RTC_BKP17R RTC_BKP17R_Msk /******************** Bits definition for RTC_BKP18R register ***************/ #define RTC_BKP18R_Pos (0U) #define RTC_BKP18R_Msk (0xFFFFFFFFU << RTC_BKP18R_Pos) /*!< 0xFFFFFFFF */ #define RTC_BKP18R RTC_BKP18R_Msk /******************** Bits definition for RTC_BKP19R register ***************/ #define RTC_BKP19R_Pos (0U) #define RTC_BKP19R_Msk (0xFFFFFFFFU << RTC_BKP19R_Pos) /*!< 0xFFFFFFFF */ #define RTC_BKP19R RTC_BKP19R_Msk /******************** Number of backup registers ******************************/ #define RTC_BKP_NUMBER 0x000000014U /******************************************************************************/ /* */ /* Serial Audio Interface */ /* */ /******************************************************************************/ /******************** Bit definition for SAI_GCR register *******************/ #define SAI_GCR_SYNCIN_Pos (0U) #define SAI_GCR_SYNCIN_Msk (0x3U << SAI_GCR_SYNCIN_Pos) /*!< 0x00000003 */ #define SAI_GCR_SYNCIN SAI_GCR_SYNCIN_Msk /*!<SYNCIN[1:0] bits (Synchronization Inputs) */ #define SAI_GCR_SYNCIN_0 (0x1U << SAI_GCR_SYNCIN_Pos) /*!< 0x00000001 */ #define SAI_GCR_SYNCIN_1 (0x2U << SAI_GCR_SYNCIN_Pos) /*!< 0x00000002 */ #define SAI_GCR_SYNCOUT_Pos (4U) #define SAI_GCR_SYNCOUT_Msk (0x3U << SAI_GCR_SYNCOUT_Pos) /*!< 0x00000030 */ #define SAI_GCR_SYNCOUT SAI_GCR_SYNCOUT_Msk /*!<SYNCOUT[1:0] bits (Synchronization Outputs) */ #define SAI_GCR_SYNCOUT_0 (0x1U << SAI_GCR_SYNCOUT_Pos) /*!< 0x00000010 */ #define SAI_GCR_SYNCOUT_1 (0x2U << SAI_GCR_SYNCOUT_Pos) /*!< 0x00000020 */ /******************* Bit definition for SAI_xCR1 register *******************/ #define SAI_xCR1_MODE_Pos (0U) #define SAI_xCR1_MODE_Msk (0x3U << SAI_xCR1_MODE_Pos) /*!< 0x00000003 */ #define SAI_xCR1_MODE SAI_xCR1_MODE_Msk /*!<MODE[1:0] bits (Audio Block Mode) */ #define SAI_xCR1_MODE_0 (0x1U << SAI_xCR1_MODE_Pos) /*!< 0x00000001 */ #define SAI_xCR1_MODE_1 (0x2U << SAI_xCR1_MODE_Pos) /*!< 0x00000002 */ #define SAI_xCR1_PRTCFG_Pos (2U) #define SAI_xCR1_PRTCFG_Msk (0x3U << SAI_xCR1_PRTCFG_Pos) /*!< 0x0000000C */ #define SAI_xCR1_PRTCFG SAI_xCR1_PRTCFG_Msk /*!<PRTCFG[1:0] bits (Protocol Configuration) */ #define SAI_xCR1_PRTCFG_0 (0x1U << SAI_xCR1_PRTCFG_Pos) /*!< 0x00000004 */ #define SAI_xCR1_PRTCFG_1 (0x2U << SAI_xCR1_PRTCFG_Pos) /*!< 0x00000008 */ #define SAI_xCR1_DS_Pos (5U) #define SAI_xCR1_DS_Msk (0x7U << SAI_xCR1_DS_Pos) /*!< 0x000000E0 */ #define SAI_xCR1_DS SAI_xCR1_DS_Msk /*!<DS[1:0] bits (Data Size) */ #define SAI_xCR1_DS_0 (0x1U << SAI_xCR1_DS_Pos) /*!< 0x00000020 */ #define SAI_xCR1_DS_1 (0x2U << SAI_xCR1_DS_Pos) /*!< 0x00000040 */ #define SAI_xCR1_DS_2 (0x4U << SAI_xCR1_DS_Pos) /*!< 0x00000080 */ #define SAI_xCR1_LSBFIRST_Pos (8U) #define SAI_xCR1_LSBFIRST_Msk (0x1U << SAI_xCR1_LSBFIRST_Pos) /*!< 0x00000100 */ #define SAI_xCR1_LSBFIRST SAI_xCR1_LSBFIRST_Msk /*!<LSB First Configuration */ #define SAI_xCR1_CKSTR_Pos (9U) #define SAI_xCR1_CKSTR_Msk (0x1U << SAI_xCR1_CKSTR_Pos) /*!< 0x00000200 */ #define SAI_xCR1_CKSTR SAI_xCR1_CKSTR_Msk /*!<ClocK STRobing edge */ #define SAI_xCR1_SYNCEN_Pos (10U) #define SAI_xCR1_SYNCEN_Msk (0x3U << SAI_xCR1_SYNCEN_Pos) /*!< 0x00000C00 */ #define SAI_xCR1_SYNCEN SAI_xCR1_SYNCEN_Msk /*!<SYNCEN[1:0](SYNChronization ENable) */ #define SAI_xCR1_SYNCEN_0 (0x1U << SAI_xCR1_SYNCEN_Pos) /*!< 0x00000400 */ #define SAI_xCR1_SYNCEN_1 (0x2U << SAI_xCR1_SYNCEN_Pos) /*!< 0x00000800 */ #define SAI_xCR1_MONO_Pos (12U) #define SAI_xCR1_MONO_Msk (0x1U << SAI_xCR1_MONO_Pos) /*!< 0x00001000 */ #define SAI_xCR1_MONO SAI_xCR1_MONO_Msk /*!<Mono mode */ #define SAI_xCR1_OUTDRIV_Pos (13U) #define SAI_xCR1_OUTDRIV_Msk (0x1U << SAI_xCR1_OUTDRIV_Pos) /*!< 0x00002000 */ #define SAI_xCR1_OUTDRIV SAI_xCR1_OUTDRIV_Msk /*!<Output Drive */ #define SAI_xCR1_SAIEN_Pos (16U) #define SAI_xCR1_SAIEN_Msk (0x1U << SAI_xCR1_SAIEN_Pos) /*!< 0x00010000 */ #define SAI_xCR1_SAIEN SAI_xCR1_SAIEN_Msk /*!<Audio Block enable */ #define SAI_xCR1_DMAEN_Pos (17U) #define SAI_xCR1_DMAEN_Msk (0x1U << SAI_xCR1_DMAEN_Pos) /*!< 0x00020000 */ #define SAI_xCR1_DMAEN SAI_xCR1_DMAEN_Msk /*!<DMA enable */ #define SAI_xCR1_NODIV_Pos (19U) #define SAI_xCR1_NODIV_Msk (0x1U << SAI_xCR1_NODIV_Pos) /*!< 0x00080000 */ #define SAI_xCR1_NODIV SAI_xCR1_NODIV_Msk /*!<No Divider Configuration */ #define SAI_xCR1_MCKDIV_Pos (20U) #define SAI_xCR1_MCKDIV_Msk (0xFU << SAI_xCR1_MCKDIV_Pos) /*!< 0x00F00000 */ #define SAI_xCR1_MCKDIV SAI_xCR1_MCKDIV_Msk /*!<MCKDIV[3:0] (Master ClocK Divider) */ #define SAI_xCR1_MCKDIV_0 (0x1U << SAI_xCR1_MCKDIV_Pos) /*!< 0x00100000 */ #define SAI_xCR1_MCKDIV_1 (0x2U << SAI_xCR1_MCKDIV_Pos) /*!< 0x00200000 */ #define SAI_xCR1_MCKDIV_2 (0x4U << SAI_xCR1_MCKDIV_Pos) /*!< 0x00400000 */ #define SAI_xCR1_MCKDIV_3 (0x8U << SAI_xCR1_MCKDIV_Pos) /*!< 0x00800000 */ /******************* Bit definition for SAI_xCR2 register *******************/ #define SAI_xCR2_FTH_Pos (0U) #define SAI_xCR2_FTH_Msk (0x7U << SAI_xCR2_FTH_Pos) /*!< 0x00000007 */ #define SAI_xCR2_FTH SAI_xCR2_FTH_Msk /*!<FTH[2:0](Fifo THreshold) */ #define SAI_xCR2_FTH_0 (0x1U << SAI_xCR2_FTH_Pos) /*!< 0x00000001 */ #define SAI_xCR2_FTH_1 (0x2U << SAI_xCR2_FTH_Pos) /*!< 0x00000002 */ #define SAI_xCR2_FTH_2 (0x4U << SAI_xCR2_FTH_Pos) /*!< 0x00000004 */ #define SAI_xCR2_FFLUSH_Pos (3U) #define SAI_xCR2_FFLUSH_Msk (0x1U << SAI_xCR2_FFLUSH_Pos) /*!< 0x00000008 */ #define SAI_xCR2_FFLUSH SAI_xCR2_FFLUSH_Msk /*!<Fifo FLUSH */ #define SAI_xCR2_TRIS_Pos (4U) #define SAI_xCR2_TRIS_Msk (0x1U << SAI_xCR2_TRIS_Pos) /*!< 0x00000010 */ #define SAI_xCR2_TRIS SAI_xCR2_TRIS_Msk /*!<TRIState Management on data line */ #define SAI_xCR2_MUTE_Pos (5U) #define SAI_xCR2_MUTE_Msk (0x1U << SAI_xCR2_MUTE_Pos) /*!< 0x00000020 */ #define SAI_xCR2_MUTE SAI_xCR2_MUTE_Msk /*!<Mute mode */ #define SAI_xCR2_MUTEVAL_Pos (6U) #define SAI_xCR2_MUTEVAL_Msk (0x1U << SAI_xCR2_MUTEVAL_Pos) /*!< 0x00000040 */ #define SAI_xCR2_MUTEVAL SAI_xCR2_MUTEVAL_Msk /*!<Muate value */ #define SAI_xCR2_MUTECNT_Pos (7U) #define SAI_xCR2_MUTECNT_Msk (0x3FU << SAI_xCR2_MUTECNT_Pos) /*!< 0x00001F80 */ #define SAI_xCR2_MUTECNT SAI_xCR2_MUTECNT_Msk /*!<MUTECNT[5:0] (MUTE counter) */ #define SAI_xCR2_MUTECNT_0 (0x01U << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000080 */ #define SAI_xCR2_MUTECNT_1 (0x02U << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000100 */ #define SAI_xCR2_MUTECNT_2 (0x04U << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000200 */ #define SAI_xCR2_MUTECNT_3 (0x08U << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000400 */ #define SAI_xCR2_MUTECNT_4 (0x10U << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000800 */ #define SAI_xCR2_MUTECNT_5 (0x20U << SAI_xCR2_MUTECNT_Pos) /*!< 0x00001000 */ #define SAI_xCR2_CPL_Pos (13U) #define SAI_xCR2_CPL_Msk (0x1U << SAI_xCR2_CPL_Pos) /*!< 0x00002000 */ #define SAI_xCR2_CPL SAI_xCR2_CPL_Msk /*!< Complement Bit */ #define SAI_xCR2_COMP_Pos (14U) #define SAI_xCR2_COMP_Msk (0x3U << SAI_xCR2_COMP_Pos) /*!< 0x0000C000 */ #define SAI_xCR2_COMP SAI_xCR2_COMP_Msk /*!<COMP[1:0] (Companding mode) */ #define SAI_xCR2_COMP_0 (0x1U << SAI_xCR2_COMP_Pos) /*!< 0x00004000 */ #define SAI_xCR2_COMP_1 (0x2U << SAI_xCR2_COMP_Pos) /*!< 0x00008000 */ /****************** Bit definition for SAI_xFRCR register *******************/ #define SAI_xFRCR_FRL_Pos (0U) #define SAI_xFRCR_FRL_Msk (0xFFU << SAI_xFRCR_FRL_Pos) /*!< 0x000000FF */ #define SAI_xFRCR_FRL SAI_xFRCR_FRL_Msk /*!<FRL[1:0](Frame length) */ #define SAI_xFRCR_FRL_0 (0x01U << SAI_xFRCR_FRL_Pos) /*!< 0x00000001 */ #define SAI_xFRCR_FRL_1 (0x02U << SAI_xFRCR_FRL_Pos) /*!< 0x00000002 */ #define SAI_xFRCR_FRL_2 (0x04U << SAI_xFRCR_FRL_Pos) /*!< 0x00000004 */ #define SAI_xFRCR_FRL_3 (0x08U << SAI_xFRCR_FRL_Pos) /*!< 0x00000008 */ #define SAI_xFRCR_FRL_4 (0x10U << SAI_xFRCR_FRL_Pos) /*!< 0x00000010 */ #define SAI_xFRCR_FRL_5 (0x20U << SAI_xFRCR_FRL_Pos) /*!< 0x00000020 */ #define SAI_xFRCR_FRL_6 (0x40U << SAI_xFRCR_FRL_Pos) /*!< 0x00000040 */ #define SAI_xFRCR_FRL_7 (0x80U << SAI_xFRCR_FRL_Pos) /*!< 0x00000080 */ #define SAI_xFRCR_FSALL_Pos (8U) #define SAI_xFRCR_FSALL_Msk (0x7FU << SAI_xFRCR_FSALL_Pos) /*!< 0x00007F00 */ #define SAI_xFRCR_FSALL SAI_xFRCR_FSALL_Msk /*!<FRL[1:0] (Frame synchronization active level length) */ #define SAI_xFRCR_FSALL_0 (0x01U << SAI_xFRCR_FSALL_Pos) /*!< 0x00000100 */ #define SAI_xFRCR_FSALL_1 (0x02U << SAI_xFRCR_FSALL_Pos) /*!< 0x00000200 */ #define SAI_xFRCR_FSALL_2 (0x04U << SAI_xFRCR_FSALL_Pos) /*!< 0x00000400 */ #define SAI_xFRCR_FSALL_3 (0x08U << SAI_xFRCR_FSALL_Pos) /*!< 0x00000800 */ #define SAI_xFRCR_FSALL_4 (0x10U << SAI_xFRCR_FSALL_Pos) /*!< 0x00001000 */ #define SAI_xFRCR_FSALL_5 (0x20U << SAI_xFRCR_FSALL_Pos) /*!< 0x00002000 */ #define SAI_xFRCR_FSALL_6 (0x40U << SAI_xFRCR_FSALL_Pos) /*!< 0x00004000 */ #define SAI_xFRCR_FSDEF_Pos (16U) #define SAI_xFRCR_FSDEF_Msk (0x1U << SAI_xFRCR_FSDEF_Pos) /*!< 0x00010000 */ #define SAI_xFRCR_FSDEF SAI_xFRCR_FSDEF_Msk /*!< Frame Synchronization Definition */ #define SAI_xFRCR_FSPOL_Pos (17U) #define SAI_xFRCR_FSPOL_Msk (0x1U << SAI_xFRCR_FSPOL_Pos) /*!< 0x00020000 */ #define SAI_xFRCR_FSPOL SAI_xFRCR_FSPOL_Msk /*!<Frame Synchronization POLarity */ #define SAI_xFRCR_FSOFF_Pos (18U) #define SAI_xFRCR_FSOFF_Msk (0x1U << SAI_xFRCR_FSOFF_Pos) /*!< 0x00040000 */ #define SAI_xFRCR_FSOFF SAI_xFRCR_FSOFF_Msk /*!<Frame Synchronization OFFset */ /* Legacy defines */ #define SAI_xFRCR_FSPO SAI_xFRCR_FSPOL /****************** Bit definition for SAI_xSLOTR register *******************/ #define SAI_xSLOTR_FBOFF_Pos (0U) #define SAI_xSLOTR_FBOFF_Msk (0x1FU << SAI_xSLOTR_FBOFF_Pos) /*!< 0x0000001F */ #define SAI_xSLOTR_FBOFF SAI_xSLOTR_FBOFF_Msk /*!<FRL[4:0](First Bit Offset) */ #define SAI_xSLOTR_FBOFF_0 (0x01U << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000001 */ #define SAI_xSLOTR_FBOFF_1 (0x02U << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000002 */ #define SAI_xSLOTR_FBOFF_2 (0x04U << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000004 */ #define SAI_xSLOTR_FBOFF_3 (0x08U << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000008 */ #define SAI_xSLOTR_FBOFF_4 (0x10U << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000010 */ #define SAI_xSLOTR_SLOTSZ_Pos (6U) #define SAI_xSLOTR_SLOTSZ_Msk (0x3U << SAI_xSLOTR_SLOTSZ_Pos) /*!< 0x000000C0 */ #define SAI_xSLOTR_SLOTSZ SAI_xSLOTR_SLOTSZ_Msk /*!<SLOTSZ[1:0] (Slot size) */ #define SAI_xSLOTR_SLOTSZ_0 (0x1U << SAI_xSLOTR_SLOTSZ_Pos) /*!< 0x00000040 */ #define SAI_xSLOTR_SLOTSZ_1 (0x2U << SAI_xSLOTR_SLOTSZ_Pos) /*!< 0x00000080 */ #define SAI_xSLOTR_NBSLOT_Pos (8U) #define SAI_xSLOTR_NBSLOT_Msk (0xFU << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000F00 */ #define SAI_xSLOTR_NBSLOT SAI_xSLOTR_NBSLOT_Msk /*!<NBSLOT[3:0] (Number of Slot in audio Frame) */ #define SAI_xSLOTR_NBSLOT_0 (0x1U << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000100 */ #define SAI_xSLOTR_NBSLOT_1 (0x2U << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000200 */ #define SAI_xSLOTR_NBSLOT_2 (0x4U << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000400 */ #define SAI_xSLOTR_NBSLOT_3 (0x8U << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000800 */ #define SAI_xSLOTR_SLOTEN_Pos (16U) #define SAI_xSLOTR_SLOTEN_Msk (0xFFFFU << SAI_xSLOTR_SLOTEN_Pos) /*!< 0xFFFF0000 */ #define SAI_xSLOTR_SLOTEN SAI_xSLOTR_SLOTEN_Msk /*!<SLOTEN[15:0] (Slot Enable) */ /******************* Bit definition for SAI_xIMR register *******************/ #define SAI_xIMR_OVRUDRIE_Pos (0U) #define SAI_xIMR_OVRUDRIE_Msk (0x1U << SAI_xIMR_OVRUDRIE_Pos) /*!< 0x00000001 */ #define SAI_xIMR_OVRUDRIE SAI_xIMR_OVRUDRIE_Msk /*!<Overrun underrun interrupt enable */ #define SAI_xIMR_MUTEDETIE_Pos (1U) #define SAI_xIMR_MUTEDETIE_Msk (0x1U << SAI_xIMR_MUTEDETIE_Pos) /*!< 0x00000002 */ #define SAI_xIMR_MUTEDETIE SAI_xIMR_MUTEDETIE_Msk /*!<Mute detection interrupt enable */ #define SAI_xIMR_WCKCFGIE_Pos (2U) #define SAI_xIMR_WCKCFGIE_Msk (0x1U << SAI_xIMR_WCKCFGIE_Pos) /*!< 0x00000004 */ #define SAI_xIMR_WCKCFGIE SAI_xIMR_WCKCFGIE_Msk /*!<Wrong Clock Configuration interrupt enable */ #define SAI_xIMR_FREQIE_Pos (3U) #define SAI_xIMR_FREQIE_Msk (0x1U << SAI_xIMR_FREQIE_Pos) /*!< 0x00000008 */ #define SAI_xIMR_FREQIE SAI_xIMR_FREQIE_Msk /*!<FIFO request interrupt enable */ #define SAI_xIMR_CNRDYIE_Pos (4U) #define SAI_xIMR_CNRDYIE_Msk (0x1U << SAI_xIMR_CNRDYIE_Pos) /*!< 0x00000010 */ #define SAI_xIMR_CNRDYIE SAI_xIMR_CNRDYIE_Msk /*!<Codec not ready interrupt enable */ #define SAI_xIMR_AFSDETIE_Pos (5U) #define SAI_xIMR_AFSDETIE_Msk (0x1U << SAI_xIMR_AFSDETIE_Pos) /*!< 0x00000020 */ #define SAI_xIMR_AFSDETIE SAI_xIMR_AFSDETIE_Msk /*!<Anticipated frame synchronization detection interrupt enable */ #define SAI_xIMR_LFSDETIE_Pos (6U) #define SAI_xIMR_LFSDETIE_Msk (0x1U << SAI_xIMR_LFSDETIE_Pos) /*!< 0x00000040 */ #define SAI_xIMR_LFSDETIE SAI_xIMR_LFSDETIE_Msk /*!<Late frame synchronization detection interrupt enable */ /******************** Bit definition for SAI_xSR register *******************/ #define SAI_xSR_OVRUDR_Pos (0U) #define SAI_xSR_OVRUDR_Msk (0x1U << SAI_xSR_OVRUDR_Pos) /*!< 0x00000001 */ #define SAI_xSR_OVRUDR SAI_xSR_OVRUDR_Msk /*!<Overrun underrun */ #define SAI_xSR_MUTEDET_Pos (1U) #define SAI_xSR_MUTEDET_Msk (0x1U << SAI_xSR_MUTEDET_Pos) /*!< 0x00000002 */ #define SAI_xSR_MUTEDET SAI_xSR_MUTEDET_Msk /*!<Mute detection */ #define SAI_xSR_WCKCFG_Pos (2U) #define SAI_xSR_WCKCFG_Msk (0x1U << SAI_xSR_WCKCFG_Pos) /*!< 0x00000004 */ #define SAI_xSR_WCKCFG SAI_xSR_WCKCFG_Msk /*!<Wrong Clock Configuration */ #define SAI_xSR_FREQ_Pos (3U) #define SAI_xSR_FREQ_Msk (0x1U << SAI_xSR_FREQ_Pos) /*!< 0x00000008 */ #define SAI_xSR_FREQ SAI_xSR_FREQ_Msk /*!<FIFO request */ #define SAI_xSR_CNRDY_Pos (4U) #define SAI_xSR_CNRDY_Msk (0x1U << SAI_xSR_CNRDY_Pos) /*!< 0x00000010 */ #define SAI_xSR_CNRDY SAI_xSR_CNRDY_Msk /*!<Codec not ready */ #define SAI_xSR_AFSDET_Pos (5U) #define SAI_xSR_AFSDET_Msk (0x1U << SAI_xSR_AFSDET_Pos) /*!< 0x00000020 */ #define SAI_xSR_AFSDET SAI_xSR_AFSDET_Msk /*!<Anticipated frame synchronization detection */ #define SAI_xSR_LFSDET_Pos (6U) #define SAI_xSR_LFSDET_Msk (0x1U << SAI_xSR_LFSDET_Pos) /*!< 0x00000040 */ #define SAI_xSR_LFSDET SAI_xSR_LFSDET_Msk /*!<Late frame synchronization detection */ #define SAI_xSR_FLVL_Pos (16U) #define SAI_xSR_FLVL_Msk (0x7U << SAI_xSR_FLVL_Pos) /*!< 0x00070000 */ #define SAI_xSR_FLVL SAI_xSR_FLVL_Msk /*!<FLVL[2:0] (FIFO Level Threshold) */ #define SAI_xSR_FLVL_0 (0x1U << SAI_xSR_FLVL_Pos) /*!< 0x00010000 */ #define SAI_xSR_FLVL_1 (0x2U << SAI_xSR_FLVL_Pos) /*!< 0x00020000 */ #define SAI_xSR_FLVL_2 (0x4U << SAI_xSR_FLVL_Pos) /*!< 0x00040000 */ /****************** Bit definition for SAI_xCLRFR register ******************/ #define SAI_xCLRFR_COVRUDR_Pos (0U) #define SAI_xCLRFR_COVRUDR_Msk (0x1U << SAI_xCLRFR_COVRUDR_Pos) /*!< 0x00000001 */ #define SAI_xCLRFR_COVRUDR SAI_xCLRFR_COVRUDR_Msk /*!<Clear Overrun underrun */ #define SAI_xCLRFR_CMUTEDET_Pos (1U) #define SAI_xCLRFR_CMUTEDET_Msk (0x1U << SAI_xCLRFR_CMUTEDET_Pos) /*!< 0x00000002 */ #define SAI_xCLRFR_CMUTEDET SAI_xCLRFR_CMUTEDET_Msk /*!<Clear Mute detection */ #define SAI_xCLRFR_CWCKCFG_Pos (2U) #define SAI_xCLRFR_CWCKCFG_Msk (0x1U << SAI_xCLRFR_CWCKCFG_Pos) /*!< 0x00000004 */ #define SAI_xCLRFR_CWCKCFG SAI_xCLRFR_CWCKCFG_Msk /*!<Clear Wrong Clock Configuration */ #define SAI_xCLRFR_CFREQ_Pos (3U) #define SAI_xCLRFR_CFREQ_Msk (0x1U << SAI_xCLRFR_CFREQ_Pos) /*!< 0x00000008 */ #define SAI_xCLRFR_CFREQ SAI_xCLRFR_CFREQ_Msk /*!<Clear FIFO request */ #define SAI_xCLRFR_CCNRDY_Pos (4U) #define SAI_xCLRFR_CCNRDY_Msk (0x1U << SAI_xCLRFR_CCNRDY_Pos) /*!< 0x00000010 */ #define SAI_xCLRFR_CCNRDY SAI_xCLRFR_CCNRDY_Msk /*!<Clear Codec not ready */ #define SAI_xCLRFR_CAFSDET_Pos (5U) #define SAI_xCLRFR_CAFSDET_Msk (0x1U << SAI_xCLRFR_CAFSDET_Pos) /*!< 0x00000020 */ #define SAI_xCLRFR_CAFSDET SAI_xCLRFR_CAFSDET_Msk /*!<Clear Anticipated frame synchronization detection */ #define SAI_xCLRFR_CLFSDET_Pos (6U) #define SAI_xCLRFR_CLFSDET_Msk (0x1U << SAI_xCLRFR_CLFSDET_Pos) /*!< 0x00000040 */ #define SAI_xCLRFR_CLFSDET SAI_xCLRFR_CLFSDET_Msk /*!<Clear Late frame synchronization detection */ /****************** Bit definition for SAI_xDR register ******************/ #define SAI_xDR_DATA_Pos (0U) #define SAI_xDR_DATA_Msk (0xFFFFFFFFU << SAI_xDR_DATA_Pos) /*!< 0xFFFFFFFF */ #define SAI_xDR_DATA SAI_xDR_DATA_Msk /******************************************************************************/ /* */ /* SD host Interface */ /* */ /******************************************************************************/ /****************** Bit definition for SDIO_POWER register ******************/ #define SDIO_POWER_PWRCTRL_Pos (0U) #define SDIO_POWER_PWRCTRL_Msk (0x3U << SDIO_POWER_PWRCTRL_Pos) /*!< 0x00000003 */ #define SDIO_POWER_PWRCTRL SDIO_POWER_PWRCTRL_Msk /*!<PWRCTRL[1:0] bits (Power supply control bits) */ #define SDIO_POWER_PWRCTRL_0 (0x1U << SDIO_POWER_PWRCTRL_Pos) /*!< 0x01 */ #define SDIO_POWER_PWRCTRL_1 (0x2U << SDIO_POWER_PWRCTRL_Pos) /*!< 0x02 */ /****************** Bit definition for SDIO_CLKCR register ******************/ #define SDIO_CLKCR_CLKDIV_Pos (0U) #define SDIO_CLKCR_CLKDIV_Msk (0xFFU << SDIO_CLKCR_CLKDIV_Pos) /*!< 0x000000FF */ #define SDIO_CLKCR_CLKDIV SDIO_CLKCR_CLKDIV_Msk /*!<Clock divide factor */ #define SDIO_CLKCR_CLKEN_Pos (8U) #define SDIO_CLKCR_CLKEN_Msk (0x1U << SDIO_CLKCR_CLKEN_Pos) /*!< 0x00000100 */ #define SDIO_CLKCR_CLKEN SDIO_CLKCR_CLKEN_Msk /*!<Clock enable bit */ #define SDIO_CLKCR_PWRSAV_Pos (9U) #define SDIO_CLKCR_PWRSAV_Msk (0x1U << SDIO_CLKCR_PWRSAV_Pos) /*!< 0x00000200 */ #define SDIO_CLKCR_PWRSAV SDIO_CLKCR_PWRSAV_Msk /*!<Power saving configuration bit */ #define SDIO_CLKCR_BYPASS_Pos (10U) #define SDIO_CLKCR_BYPASS_Msk (0x1U << SDIO_CLKCR_BYPASS_Pos) /*!< 0x00000400 */ #define SDIO_CLKCR_BYPASS SDIO_CLKCR_BYPASS_Msk /*!<Clock divider bypass enable bit */ #define SDIO_CLKCR_WIDBUS_Pos (11U) #define SDIO_CLKCR_WIDBUS_Msk (0x3U << SDIO_CLKCR_WIDBUS_Pos) /*!< 0x00001800 */ #define SDIO_CLKCR_WIDBUS SDIO_CLKCR_WIDBUS_Msk /*!<WIDBUS[1:0] bits (Wide bus mode enable bit) */ #define SDIO_CLKCR_WIDBUS_0 (0x1U << SDIO_CLKCR_WIDBUS_Pos) /*!< 0x0800 */ #define SDIO_CLKCR_WIDBUS_1 (0x2U << SDIO_CLKCR_WIDBUS_Pos) /*!< 0x1000 */ #define SDIO_CLKCR_NEGEDGE_Pos (13U) #define SDIO_CLKCR_NEGEDGE_Msk (0x1U << SDIO_CLKCR_NEGEDGE_Pos) /*!< 0x00002000 */ #define SDIO_CLKCR_NEGEDGE SDIO_CLKCR_NEGEDGE_Msk /*!<SDIO_CK dephasing selection bit */ #define SDIO_CLKCR_HWFC_EN_Pos (14U) #define SDIO_CLKCR_HWFC_EN_Msk (0x1U << SDIO_CLKCR_HWFC_EN_Pos) /*!< 0x00004000 */ #define SDIO_CLKCR_HWFC_EN SDIO_CLKCR_HWFC_EN_Msk /*!<HW Flow Control enable */ /******************* Bit definition for SDIO_ARG register *******************/ #define SDIO_ARG_CMDARG_Pos (0U) #define SDIO_ARG_CMDARG_Msk (0xFFFFFFFFU << SDIO_ARG_CMDARG_Pos) /*!< 0xFFFFFFFF */ #define SDIO_ARG_CMDARG SDIO_ARG_CMDARG_Msk /*!<Command argument */ /******************* Bit definition for SDIO_CMD register *******************/ #define SDIO_CMD_CMDINDEX_Pos (0U) #define SDIO_CMD_CMDINDEX_Msk (0x3FU << SDIO_CMD_CMDINDEX_Pos) /*!< 0x0000003F */ #define SDIO_CMD_CMDINDEX SDIO_CMD_CMDINDEX_Msk /*!<Command Index */ #define SDIO_CMD_WAITRESP_Pos (6U) #define SDIO_CMD_WAITRESP_Msk (0x3U << SDIO_CMD_WAITRESP_Pos) /*!< 0x000000C0 */ #define SDIO_CMD_WAITRESP SDIO_CMD_WAITRESP_Msk /*!<WAITRESP[1:0] bits (Wait for response bits) */ #define SDIO_CMD_WAITRESP_0 (0x1U << SDIO_CMD_WAITRESP_Pos) /*!< 0x0040 */ #define SDIO_CMD_WAITRESP_1 (0x2U << SDIO_CMD_WAITRESP_Pos) /*!< 0x0080 */ #define SDIO_CMD_WAITINT_Pos (8U) #define SDIO_CMD_WAITINT_Msk (0x1U << SDIO_CMD_WAITINT_Pos) /*!< 0x00000100 */ #define SDIO_CMD_WAITINT SDIO_CMD_WAITINT_Msk /*!<CPSM Waits for Interrupt Request */ #define SDIO_CMD_WAITPEND_Pos (9U) #define SDIO_CMD_WAITPEND_Msk (0x1U << SDIO_CMD_WAITPEND_Pos) /*!< 0x00000200 */ #define SDIO_CMD_WAITPEND SDIO_CMD_WAITPEND_Msk /*!<CPSM Waits for ends of data transfer (CmdPend internal signal) */ #define SDIO_CMD_CPSMEN_Pos (10U) #define SDIO_CMD_CPSMEN_Msk (0x1U << SDIO_CMD_CPSMEN_Pos) /*!< 0x00000400 */ #define SDIO_CMD_CPSMEN SDIO_CMD_CPSMEN_Msk /*!<Command path state machine (CPSM) Enable bit */ #define SDIO_CMD_SDIOSUSPEND_Pos (11U) #define SDIO_CMD_SDIOSUSPEND_Msk (0x1U << SDIO_CMD_SDIOSUSPEND_Pos) /*!< 0x00000800 */ #define SDIO_CMD_SDIOSUSPEND SDIO_CMD_SDIOSUSPEND_Msk /*!<SD I/O suspend command */ /***************** Bit definition for SDIO_RESPCMD register *****************/ #define SDIO_RESPCMD_RESPCMD_Pos (0U) #define SDIO_RESPCMD_RESPCMD_Msk (0x3FU << SDIO_RESPCMD_RESPCMD_Pos) /*!< 0x0000003F */ #define SDIO_RESPCMD_RESPCMD SDIO_RESPCMD_RESPCMD_Msk /*!<Response command index */ /****************** Bit definition for SDIO_RESP0 register ******************/ #define SDIO_RESP0_CARDSTATUS0_Pos (0U) #define SDIO_RESP0_CARDSTATUS0_Msk (0xFFFFFFFFU << SDIO_RESP0_CARDSTATUS0_Pos) /*!< 0xFFFFFFFF */ #define SDIO_RESP0_CARDSTATUS0 SDIO_RESP0_CARDSTATUS0_Msk /*!<Card Status */ /****************** Bit definition for SDIO_RESP1 register ******************/ #define SDIO_RESP1_CARDSTATUS1_Pos (0U) #define SDIO_RESP1_CARDSTATUS1_Msk (0xFFFFFFFFU << SDIO_RESP1_CARDSTATUS1_Pos) /*!< 0xFFFFFFFF */ #define SDIO_RESP1_CARDSTATUS1 SDIO_RESP1_CARDSTATUS1_Msk /*!<Card Status */ /****************** Bit definition for SDIO_RESP2 register ******************/ #define SDIO_RESP2_CARDSTATUS2_Pos (0U) #define SDIO_RESP2_CARDSTATUS2_Msk (0xFFFFFFFFU << SDIO_RESP2_CARDSTATUS2_Pos) /*!< 0xFFFFFFFF */ #define SDIO_RESP2_CARDSTATUS2 SDIO_RESP2_CARDSTATUS2_Msk /*!<Card Status */ /****************** Bit definition for SDIO_RESP3 register ******************/ #define SDIO_RESP3_CARDSTATUS3_Pos (0U) #define SDIO_RESP3_CARDSTATUS3_Msk (0xFFFFFFFFU << SDIO_RESP3_CARDSTATUS3_Pos) /*!< 0xFFFFFFFF */ #define SDIO_RESP3_CARDSTATUS3 SDIO_RESP3_CARDSTATUS3_Msk /*!<Card Status */ /****************** Bit definition for SDIO_RESP4 register ******************/ #define SDIO_RESP4_CARDSTATUS4_Pos (0U) #define SDIO_RESP4_CARDSTATUS4_Msk (0xFFFFFFFFU << SDIO_RESP4_CARDSTATUS4_Pos) /*!< 0xFFFFFFFF */ #define SDIO_RESP4_CARDSTATUS4 SDIO_RESP4_CARDSTATUS4_Msk /*!<Card Status */ /****************** Bit definition for SDIO_DTIMER register *****************/ #define SDIO_DTIMER_DATATIME_Pos (0U) #define SDIO_DTIMER_DATATIME_Msk (0xFFFFFFFFU << SDIO_DTIMER_DATATIME_Pos) /*!< 0xFFFFFFFF */ #define SDIO_DTIMER_DATATIME SDIO_DTIMER_DATATIME_Msk /*!<Data timeout period. */ /****************** Bit definition for SDIO_DLEN register *******************/ #define SDIO_DLEN_DATALENGTH_Pos (0U) #define SDIO_DLEN_DATALENGTH_Msk (0x1FFFFFFU << SDIO_DLEN_DATALENGTH_Pos) /*!< 0x01FFFFFF */ #define SDIO_DLEN_DATALENGTH SDIO_DLEN_DATALENGTH_Msk /*!<Data length value */ /****************** Bit definition for SDIO_DCTRL register ******************/ #define SDIO_DCTRL_DTEN_Pos (0U) #define SDIO_DCTRL_DTEN_Msk (0x1U << SDIO_DCTRL_DTEN_Pos) /*!< 0x00000001 */ #define SDIO_DCTRL_DTEN SDIO_DCTRL_DTEN_Msk /*!<Data transfer enabled bit */ #define SDIO_DCTRL_DTDIR_Pos (1U) #define SDIO_DCTRL_DTDIR_Msk (0x1U << SDIO_DCTRL_DTDIR_Pos) /*!< 0x00000002 */ #define SDIO_DCTRL_DTDIR SDIO_DCTRL_DTDIR_Msk /*!<Data transfer direction selection */ #define SDIO_DCTRL_DTMODE_Pos (2U) #define SDIO_DCTRL_DTMODE_Msk (0x1U << SDIO_DCTRL_DTMODE_Pos) /*!< 0x00000004 */ #define SDIO_DCTRL_DTMODE SDIO_DCTRL_DTMODE_Msk /*!<Data transfer mode selection */ #define SDIO_DCTRL_DMAEN_Pos (3U) #define SDIO_DCTRL_DMAEN_Msk (0x1U << SDIO_DCTRL_DMAEN_Pos) /*!< 0x00000008 */ #define SDIO_DCTRL_DMAEN SDIO_DCTRL_DMAEN_Msk /*!<DMA enabled bit */ #define SDIO_DCTRL_DBLOCKSIZE_Pos (4U) #define SDIO_DCTRL_DBLOCKSIZE_Msk (0xFU << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x000000F0 */ #define SDIO_DCTRL_DBLOCKSIZE SDIO_DCTRL_DBLOCKSIZE_Msk /*!<DBLOCKSIZE[3:0] bits (Data block size) */ #define SDIO_DCTRL_DBLOCKSIZE_0 (0x1U << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0010 */ #define SDIO_DCTRL_DBLOCKSIZE_1 (0x2U << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0020 */ #define SDIO_DCTRL_DBLOCKSIZE_2 (0x4U << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0040 */ #define SDIO_DCTRL_DBLOCKSIZE_3 (0x8U << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0080 */ #define SDIO_DCTRL_RWSTART_Pos (8U) #define SDIO_DCTRL_RWSTART_Msk (0x1U << SDIO_DCTRL_RWSTART_Pos) /*!< 0x00000100 */ #define SDIO_DCTRL_RWSTART SDIO_DCTRL_RWSTART_Msk /*!<Read wait start */ #define SDIO_DCTRL_RWSTOP_Pos (9U) #define SDIO_DCTRL_RWSTOP_Msk (0x1U << SDIO_DCTRL_RWSTOP_Pos) /*!< 0x00000200 */ #define SDIO_DCTRL_RWSTOP SDIO_DCTRL_RWSTOP_Msk /*!<Read wait stop */ #define SDIO_DCTRL_RWMOD_Pos (10U) #define SDIO_DCTRL_RWMOD_Msk (0x1U << SDIO_DCTRL_RWMOD_Pos) /*!< 0x00000400 */ #define SDIO_DCTRL_RWMOD SDIO_DCTRL_RWMOD_Msk /*!<Read wait mode */ #define SDIO_DCTRL_SDIOEN_Pos (11U) #define SDIO_DCTRL_SDIOEN_Msk (0x1U << SDIO_DCTRL_SDIOEN_Pos) /*!< 0x00000800 */ #define SDIO_DCTRL_SDIOEN SDIO_DCTRL_SDIOEN_Msk /*!<SD I/O enable functions */ /****************** Bit definition for SDIO_DCOUNT register *****************/ #define SDIO_DCOUNT_DATACOUNT_Pos (0U) #define SDIO_DCOUNT_DATACOUNT_Msk (0x1FFFFFFU << SDIO_DCOUNT_DATACOUNT_Pos) /*!< 0x01FFFFFF */ #define SDIO_DCOUNT_DATACOUNT SDIO_DCOUNT_DATACOUNT_Msk /*!<Data count value */ /****************** Bit definition for SDIO_STA register ********************/ #define SDIO_STA_CCRCFAIL_Pos (0U) #define SDIO_STA_CCRCFAIL_Msk (0x1U << SDIO_STA_CCRCFAIL_Pos) /*!< 0x00000001 */ #define SDIO_STA_CCRCFAIL SDIO_STA_CCRCFAIL_Msk /*!<Command response received (CRC check failed) */ #define SDIO_STA_DCRCFAIL_Pos (1U) #define SDIO_STA_DCRCFAIL_Msk (0x1U << SDIO_STA_DCRCFAIL_Pos) /*!< 0x00000002 */ #define SDIO_STA_DCRCFAIL SDIO_STA_DCRCFAIL_Msk /*!<Data block sent/received (CRC check failed) */ #define SDIO_STA_CTIMEOUT_Pos (2U) #define SDIO_STA_CTIMEOUT_Msk (0x1U << SDIO_STA_CTIMEOUT_Pos) /*!< 0x00000004 */ #define SDIO_STA_CTIMEOUT SDIO_STA_CTIMEOUT_Msk /*!<Command response timeout */ #define SDIO_STA_DTIMEOUT_Pos (3U) #define SDIO_STA_DTIMEOUT_Msk (0x1U << SDIO_STA_DTIMEOUT_Pos) /*!< 0x00000008 */ #define SDIO_STA_DTIMEOUT SDIO_STA_DTIMEOUT_Msk /*!<Data timeout */ #define SDIO_STA_TXUNDERR_Pos (4U) #define SDIO_STA_TXUNDERR_Msk (0x1U << SDIO_STA_TXUNDERR_Pos) /*!< 0x00000010 */ #define SDIO_STA_TXUNDERR SDIO_STA_TXUNDERR_Msk /*!<Transmit FIFO underrun error */ #define SDIO_STA_RXOVERR_Pos (5U) #define SDIO_STA_RXOVERR_Msk (0x1U << SDIO_STA_RXOVERR_Pos) /*!< 0x00000020 */ #define SDIO_STA_RXOVERR SDIO_STA_RXOVERR_Msk /*!<Received FIFO overrun error */ #define SDIO_STA_CMDREND_Pos (6U) #define SDIO_STA_CMDREND_Msk (0x1U << SDIO_STA_CMDREND_Pos) /*!< 0x00000040 */ #define SDIO_STA_CMDREND SDIO_STA_CMDREND_Msk /*!<Command response received (CRC check passed) */ #define SDIO_STA_CMDSENT_Pos (7U) #define SDIO_STA_CMDSENT_Msk (0x1U << SDIO_STA_CMDSENT_Pos) /*!< 0x00000080 */ #define SDIO_STA_CMDSENT SDIO_STA_CMDSENT_Msk /*!<Command sent (no response required) */ #define SDIO_STA_DATAEND_Pos (8U) #define SDIO_STA_DATAEND_Msk (0x1U << SDIO_STA_DATAEND_Pos) /*!< 0x00000100 */ #define SDIO_STA_DATAEND SDIO_STA_DATAEND_Msk /*!<Data end (data counter, SDIDCOUNT, is zero) */ #define SDIO_STA_DBCKEND_Pos (10U) #define SDIO_STA_DBCKEND_Msk (0x1U << SDIO_STA_DBCKEND_Pos) /*!< 0x00000400 */ #define SDIO_STA_DBCKEND SDIO_STA_DBCKEND_Msk /*!<Data block sent/received (CRC check passed) */ #define SDIO_STA_CMDACT_Pos (11U) #define SDIO_STA_CMDACT_Msk (0x1U << SDIO_STA_CMDACT_Pos) /*!< 0x00000800 */ #define SDIO_STA_CMDACT SDIO_STA_CMDACT_Msk /*!<Command transfer in progress */ #define SDIO_STA_TXACT_Pos (12U) #define SDIO_STA_TXACT_Msk (0x1U << SDIO_STA_TXACT_Pos) /*!< 0x00001000 */ #define SDIO_STA_TXACT SDIO_STA_TXACT_Msk /*!<Data transmit in progress */ #define SDIO_STA_RXACT_Pos (13U) #define SDIO_STA_RXACT_Msk (0x1U << SDIO_STA_RXACT_Pos) /*!< 0x00002000 */ #define SDIO_STA_RXACT SDIO_STA_RXACT_Msk /*!<Data receive in progress */ #define SDIO_STA_TXFIFOHE_Pos (14U) #define SDIO_STA_TXFIFOHE_Msk (0x1U << SDIO_STA_TXFIFOHE_Pos) /*!< 0x00004000 */ #define SDIO_STA_TXFIFOHE SDIO_STA_TXFIFOHE_Msk /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */ #define SDIO_STA_RXFIFOHF_Pos (15U) #define SDIO_STA_RXFIFOHF_Msk (0x1U << SDIO_STA_RXFIFOHF_Pos) /*!< 0x00008000 */ #define SDIO_STA_RXFIFOHF SDIO_STA_RXFIFOHF_Msk /*!<Receive FIFO Half Full: there are at least 8 words in the FIFO */ #define SDIO_STA_TXFIFOF_Pos (16U) #define SDIO_STA_TXFIFOF_Msk (0x1U << SDIO_STA_TXFIFOF_Pos) /*!< 0x00010000 */ #define SDIO_STA_TXFIFOF SDIO_STA_TXFIFOF_Msk /*!<Transmit FIFO full */ #define SDIO_STA_RXFIFOF_Pos (17U) #define SDIO_STA_RXFIFOF_Msk (0x1U << SDIO_STA_RXFIFOF_Pos) /*!< 0x00020000 */ #define SDIO_STA_RXFIFOF SDIO_STA_RXFIFOF_Msk /*!<Receive FIFO full */ #define SDIO_STA_TXFIFOE_Pos (18U) #define SDIO_STA_TXFIFOE_Msk (0x1U << SDIO_STA_TXFIFOE_Pos) /*!< 0x00040000 */ #define SDIO_STA_TXFIFOE SDIO_STA_TXFIFOE_Msk /*!<Transmit FIFO empty */ #define SDIO_STA_RXFIFOE_Pos (19U) #define SDIO_STA_RXFIFOE_Msk (0x1U << SDIO_STA_RXFIFOE_Pos) /*!< 0x00080000 */ #define SDIO_STA_RXFIFOE SDIO_STA_RXFIFOE_Msk /*!<Receive FIFO empty */ #define SDIO_STA_TXDAVL_Pos (20U) #define SDIO_STA_TXDAVL_Msk (0x1U << SDIO_STA_TXDAVL_Pos) /*!< 0x00100000 */ #define SDIO_STA_TXDAVL SDIO_STA_TXDAVL_Msk /*!<Data available in transmit FIFO */ #define SDIO_STA_RXDAVL_Pos (21U) #define SDIO_STA_RXDAVL_Msk (0x1U << SDIO_STA_RXDAVL_Pos) /*!< 0x00200000 */ #define SDIO_STA_RXDAVL SDIO_STA_RXDAVL_Msk /*!<Data available in receive FIFO */ #define SDIO_STA_SDIOIT_Pos (22U) #define SDIO_STA_SDIOIT_Msk (0x1U << SDIO_STA_SDIOIT_Pos) /*!< 0x00400000 */ #define SDIO_STA_SDIOIT SDIO_STA_SDIOIT_Msk /*!<SDIO interrupt received */ /******************* Bit definition for SDIO_ICR register *******************/ #define SDIO_ICR_CCRCFAILC_Pos (0U) #define SDIO_ICR_CCRCFAILC_Msk (0x1U << SDIO_ICR_CCRCFAILC_Pos) /*!< 0x00000001 */ #define SDIO_ICR_CCRCFAILC SDIO_ICR_CCRCFAILC_Msk /*!<CCRCFAIL flag clear bit */ #define SDIO_ICR_DCRCFAILC_Pos (1U) #define SDIO_ICR_DCRCFAILC_Msk (0x1U << SDIO_ICR_DCRCFAILC_Pos) /*!< 0x00000002 */ #define SDIO_ICR_DCRCFAILC SDIO_ICR_DCRCFAILC_Msk /*!<DCRCFAIL flag clear bit */ #define SDIO_ICR_CTIMEOUTC_Pos (2U) #define SDIO_ICR_CTIMEOUTC_Msk (0x1U << SDIO_ICR_CTIMEOUTC_Pos) /*!< 0x00000004 */ #define SDIO_ICR_CTIMEOUTC SDIO_ICR_CTIMEOUTC_Msk /*!<CTIMEOUT flag clear bit */ #define SDIO_ICR_DTIMEOUTC_Pos (3U) #define SDIO_ICR_DTIMEOUTC_Msk (0x1U << SDIO_ICR_DTIMEOUTC_Pos) /*!< 0x00000008 */ #define SDIO_ICR_DTIMEOUTC SDIO_ICR_DTIMEOUTC_Msk /*!<DTIMEOUT flag clear bit */ #define SDIO_ICR_TXUNDERRC_Pos (4U) #define SDIO_ICR_TXUNDERRC_Msk (0x1U << SDIO_ICR_TXUNDERRC_Pos) /*!< 0x00000010 */ #define SDIO_ICR_TXUNDERRC SDIO_ICR_TXUNDERRC_Msk /*!<TXUNDERR flag clear bit */ #define SDIO_ICR_RXOVERRC_Pos (5U) #define SDIO_ICR_RXOVERRC_Msk (0x1U << SDIO_ICR_RXOVERRC_Pos) /*!< 0x00000020 */ #define SDIO_ICR_RXOVERRC SDIO_ICR_RXOVERRC_Msk /*!<RXOVERR flag clear bit */ #define SDIO_ICR_CMDRENDC_Pos (6U) #define SDIO_ICR_CMDRENDC_Msk (0x1U << SDIO_ICR_CMDRENDC_Pos) /*!< 0x00000040 */ #define SDIO_ICR_CMDRENDC SDIO_ICR_CMDRENDC_Msk /*!<CMDREND flag clear bit */ #define SDIO_ICR_CMDSENTC_Pos (7U) #define SDIO_ICR_CMDSENTC_Msk (0x1U << SDIO_ICR_CMDSENTC_Pos) /*!< 0x00000080 */ #define SDIO_ICR_CMDSENTC SDIO_ICR_CMDSENTC_Msk /*!<CMDSENT flag clear bit */ #define SDIO_ICR_DATAENDC_Pos (8U) #define SDIO_ICR_DATAENDC_Msk (0x1U << SDIO_ICR_DATAENDC_Pos) /*!< 0x00000100 */ #define SDIO_ICR_DATAENDC SDIO_ICR_DATAENDC_Msk /*!<DATAEND flag clear bit */ #define SDIO_ICR_DBCKENDC_Pos (10U) #define SDIO_ICR_DBCKENDC_Msk (0x1U << SDIO_ICR_DBCKENDC_Pos) /*!< 0x00000400 */ #define SDIO_ICR_DBCKENDC SDIO_ICR_DBCKENDC_Msk /*!<DBCKEND flag clear bit */ #define SDIO_ICR_SDIOITC_Pos (22U) #define SDIO_ICR_SDIOITC_Msk (0x1U << SDIO_ICR_SDIOITC_Pos) /*!< 0x00400000 */ #define SDIO_ICR_SDIOITC SDIO_ICR_SDIOITC_Msk /*!<SDIOIT flag clear bit */ /****************** Bit definition for SDIO_MASK register *******************/ #define SDIO_MASK_CCRCFAILIE_Pos (0U) #define SDIO_MASK_CCRCFAILIE_Msk (0x1U << SDIO_MASK_CCRCFAILIE_Pos) /*!< 0x00000001 */ #define SDIO_MASK_CCRCFAILIE SDIO_MASK_CCRCFAILIE_Msk /*!<Command CRC Fail Interrupt Enable */ #define SDIO_MASK_DCRCFAILIE_Pos (1U) #define SDIO_MASK_DCRCFAILIE_Msk (0x1U << SDIO_MASK_DCRCFAILIE_Pos) /*!< 0x00000002 */ #define SDIO_MASK_DCRCFAILIE SDIO_MASK_DCRCFAILIE_Msk /*!<Data CRC Fail Interrupt Enable */ #define SDIO_MASK_CTIMEOUTIE_Pos (2U) #define SDIO_MASK_CTIMEOUTIE_Msk (0x1U << SDIO_MASK_CTIMEOUTIE_Pos) /*!< 0x00000004 */ #define SDIO_MASK_CTIMEOUTIE SDIO_MASK_CTIMEOUTIE_Msk /*!<Command TimeOut Interrupt Enable */ #define SDIO_MASK_DTIMEOUTIE_Pos (3U) #define SDIO_MASK_DTIMEOUTIE_Msk (0x1U << SDIO_MASK_DTIMEOUTIE_Pos) /*!< 0x00000008 */ #define SDIO_MASK_DTIMEOUTIE SDIO_MASK_DTIMEOUTIE_Msk /*!<Data TimeOut Interrupt Enable */ #define SDIO_MASK_TXUNDERRIE_Pos (4U) #define SDIO_MASK_TXUNDERRIE_Msk (0x1U << SDIO_MASK_TXUNDERRIE_Pos) /*!< 0x00000010 */ #define SDIO_MASK_TXUNDERRIE SDIO_MASK_TXUNDERRIE_Msk /*!<Tx FIFO UnderRun Error Interrupt Enable */ #define SDIO_MASK_RXOVERRIE_Pos (5U) #define SDIO_MASK_RXOVERRIE_Msk (0x1U << SDIO_MASK_RXOVERRIE_Pos) /*!< 0x00000020 */ #define SDIO_MASK_RXOVERRIE SDIO_MASK_RXOVERRIE_Msk /*!<Rx FIFO OverRun Error Interrupt Enable */ #define SDIO_MASK_CMDRENDIE_Pos (6U) #define SDIO_MASK_CMDRENDIE_Msk (0x1U << SDIO_MASK_CMDRENDIE_Pos) /*!< 0x00000040 */ #define SDIO_MASK_CMDRENDIE SDIO_MASK_CMDRENDIE_Msk /*!<Command Response Received Interrupt Enable */ #define SDIO_MASK_CMDSENTIE_Pos (7U) #define SDIO_MASK_CMDSENTIE_Msk (0x1U << SDIO_MASK_CMDSENTIE_Pos) /*!< 0x00000080 */ #define SDIO_MASK_CMDSENTIE SDIO_MASK_CMDSENTIE_Msk /*!<Command Sent Interrupt Enable */ #define SDIO_MASK_DATAENDIE_Pos (8U) #define SDIO_MASK_DATAENDIE_Msk (0x1U << SDIO_MASK_DATAENDIE_Pos) /*!< 0x00000100 */ #define SDIO_MASK_DATAENDIE SDIO_MASK_DATAENDIE_Msk /*!<Data End Interrupt Enable */ #define SDIO_MASK_DBCKENDIE_Pos (10U) #define SDIO_MASK_DBCKENDIE_Msk (0x1U << SDIO_MASK_DBCKENDIE_Pos) /*!< 0x00000400 */ #define SDIO_MASK_DBCKENDIE SDIO_MASK_DBCKENDIE_Msk /*!<Data Block End Interrupt Enable */ #define SDIO_MASK_CMDACTIE_Pos (11U) #define SDIO_MASK_CMDACTIE_Msk (0x1U << SDIO_MASK_CMDACTIE_Pos) /*!< 0x00000800 */ #define SDIO_MASK_CMDACTIE SDIO_MASK_CMDACTIE_Msk /*!<CCommand Acting Interrupt Enable */ #define SDIO_MASK_TXACTIE_Pos (12U) #define SDIO_MASK_TXACTIE_Msk (0x1U << SDIO_MASK_TXACTIE_Pos) /*!< 0x00001000 */ #define SDIO_MASK_TXACTIE SDIO_MASK_TXACTIE_Msk /*!<Data Transmit Acting Interrupt Enable */ #define SDIO_MASK_RXACTIE_Pos (13U) #define SDIO_MASK_RXACTIE_Msk (0x1U << SDIO_MASK_RXACTIE_Pos) /*!< 0x00002000 */ #define SDIO_MASK_RXACTIE SDIO_MASK_RXACTIE_Msk /*!<Data receive acting interrupt enabled */ #define SDIO_MASK_TXFIFOHEIE_Pos (14U) #define SDIO_MASK_TXFIFOHEIE_Msk (0x1U << SDIO_MASK_TXFIFOHEIE_Pos) /*!< 0x00004000 */ #define SDIO_MASK_TXFIFOHEIE SDIO_MASK_TXFIFOHEIE_Msk /*!<Tx FIFO Half Empty interrupt Enable */ #define SDIO_MASK_RXFIFOHFIE_Pos (15U) #define SDIO_MASK_RXFIFOHFIE_Msk (0x1U << SDIO_MASK_RXFIFOHFIE_Pos) /*!< 0x00008000 */ #define SDIO_MASK_RXFIFOHFIE SDIO_MASK_RXFIFOHFIE_Msk /*!<Rx FIFO Half Full interrupt Enable */ #define SDIO_MASK_TXFIFOFIE_Pos (16U) #define SDIO_MASK_TXFIFOFIE_Msk (0x1U << SDIO_MASK_TXFIFOFIE_Pos) /*!< 0x00010000 */ #define SDIO_MASK_TXFIFOFIE SDIO_MASK_TXFIFOFIE_Msk /*!<Tx FIFO Full interrupt Enable */ #define SDIO_MASK_RXFIFOFIE_Pos (17U) #define SDIO_MASK_RXFIFOFIE_Msk (0x1U << SDIO_MASK_RXFIFOFIE_Pos) /*!< 0x00020000 */ #define SDIO_MASK_RXFIFOFIE SDIO_MASK_RXFIFOFIE_Msk /*!<Rx FIFO Full interrupt Enable */ #define SDIO_MASK_TXFIFOEIE_Pos (18U) #define SDIO_MASK_TXFIFOEIE_Msk (0x1U << SDIO_MASK_TXFIFOEIE_Pos) /*!< 0x00040000 */ #define SDIO_MASK_TXFIFOEIE SDIO_MASK_TXFIFOEIE_Msk /*!<Tx FIFO Empty interrupt Enable */ #define SDIO_MASK_RXFIFOEIE_Pos (19U) #define SDIO_MASK_RXFIFOEIE_Msk (0x1U << SDIO_MASK_RXFIFOEIE_Pos) /*!< 0x00080000 */ #define SDIO_MASK_RXFIFOEIE SDIO_MASK_RXFIFOEIE_Msk /*!<Rx FIFO Empty interrupt Enable */ #define SDIO_MASK_TXDAVLIE_Pos (20U) #define SDIO_MASK_TXDAVLIE_Msk (0x1U << SDIO_MASK_TXDAVLIE_Pos) /*!< 0x00100000 */ #define SDIO_MASK_TXDAVLIE SDIO_MASK_TXDAVLIE_Msk /*!<Data available in Tx FIFO interrupt Enable */ #define SDIO_MASK_RXDAVLIE_Pos (21U) #define SDIO_MASK_RXDAVLIE_Msk (0x1U << SDIO_MASK_RXDAVLIE_Pos) /*!< 0x00200000 */ #define SDIO_MASK_RXDAVLIE SDIO_MASK_RXDAVLIE_Msk /*!<Data available in Rx FIFO interrupt Enable */ #define SDIO_MASK_SDIOITIE_Pos (22U) #define SDIO_MASK_SDIOITIE_Msk (0x1U << SDIO_MASK_SDIOITIE_Pos) /*!< 0x00400000 */ #define SDIO_MASK_SDIOITIE SDIO_MASK_SDIOITIE_Msk /*!<SDIO Mode Interrupt Received interrupt Enable */ /***************** Bit definition for SDIO_FIFOCNT register *****************/ #define SDIO_FIFOCNT_FIFOCOUNT_Pos (0U) #define SDIO_FIFOCNT_FIFOCOUNT_Msk (0xFFFFFFU << SDIO_FIFOCNT_FIFOCOUNT_Pos) /*!< 0x00FFFFFF */ #define SDIO_FIFOCNT_FIFOCOUNT SDIO_FIFOCNT_FIFOCOUNT_Msk /*!<Remaining number of words to be written to or read from the FIFO */ /****************** Bit definition for SDIO_FIFO register *******************/ #define SDIO_FIFO_FIFODATA_Pos (0U) #define SDIO_FIFO_FIFODATA_Msk (0xFFFFFFFFU << SDIO_FIFO_FIFODATA_Pos) /*!< 0xFFFFFFFF */ #define SDIO_FIFO_FIFODATA SDIO_FIFO_FIFODATA_Msk /*!<Receive and transmit FIFO data */ /******************************************************************************/ /* */ /* Serial Peripheral Interface */ /* */ /******************************************************************************/ #define SPI_I2S_FULLDUPLEX_SUPPORT /*!< I2S Full-Duplex support */ /******************* Bit definition for SPI_CR1 register ********************/ #define SPI_CR1_CPHA_Pos (0U) #define SPI_CR1_CPHA_Msk (0x1U << SPI_CR1_CPHA_Pos) /*!< 0x00000001 */ #define SPI_CR1_CPHA SPI_CR1_CPHA_Msk /*!<Clock Phase */ #define SPI_CR1_CPOL_Pos (1U) #define SPI_CR1_CPOL_Msk (0x1U << SPI_CR1_CPOL_Pos) /*!< 0x00000002 */ #define SPI_CR1_CPOL SPI_CR1_CPOL_Msk /*!<Clock Polarity */ #define SPI_CR1_MSTR_Pos (2U) #define SPI_CR1_MSTR_Msk (0x1U << SPI_CR1_MSTR_Pos) /*!< 0x00000004 */ #define SPI_CR1_MSTR SPI_CR1_MSTR_Msk /*!<Master Selection */ #define SPI_CR1_BR_Pos (3U) #define SPI_CR1_BR_Msk (0x7U << SPI_CR1_BR_Pos) /*!< 0x00000038 */ #define SPI_CR1_BR SPI_CR1_BR_Msk /*!<BR[2:0] bits (Baud Rate Control) */ #define SPI_CR1_BR_0 (0x1U << SPI_CR1_BR_Pos) /*!< 0x00000008 */ #define SPI_CR1_BR_1 (0x2U << SPI_CR1_BR_Pos) /*!< 0x00000010 */ #define SPI_CR1_BR_2 (0x4U << SPI_CR1_BR_Pos) /*!< 0x00000020 */ #define SPI_CR1_SPE_Pos (6U) #define SPI_CR1_SPE_Msk (0x1U << SPI_CR1_SPE_Pos) /*!< 0x00000040 */ #define SPI_CR1_SPE SPI_CR1_SPE_Msk /*!<SPI Enable */ #define SPI_CR1_LSBFIRST_Pos (7U) #define SPI_CR1_LSBFIRST_Msk (0x1U << SPI_CR1_LSBFIRST_Pos) /*!< 0x00000080 */ #define SPI_CR1_LSBFIRST SPI_CR1_LSBFIRST_Msk /*!<Frame Format */ #define SPI_CR1_SSI_Pos (8U) #define SPI_CR1_SSI_Msk (0x1U << SPI_CR1_SSI_Pos) /*!< 0x00000100 */ #define SPI_CR1_SSI SPI_CR1_SSI_Msk /*!<Internal slave select */ #define SPI_CR1_SSM_Pos (9U) #define SPI_CR1_SSM_Msk (0x1U << SPI_CR1_SSM_Pos) /*!< 0x00000200 */ #define SPI_CR1_SSM SPI_CR1_SSM_Msk /*!<Software slave management */ #define SPI_CR1_RXONLY_Pos (10U) #define SPI_CR1_RXONLY_Msk (0x1U << SPI_CR1_RXONLY_Pos) /*!< 0x00000400 */ #define SPI_CR1_RXONLY SPI_CR1_RXONLY_Msk /*!<Receive only */ #define SPI_CR1_DFF_Pos (11U) #define SPI_CR1_DFF_Msk (0x1U << SPI_CR1_DFF_Pos) /*!< 0x00000800 */ #define SPI_CR1_DFF SPI_CR1_DFF_Msk /*!<Data Frame Format */ #define SPI_CR1_CRCNEXT_Pos (12U) #define SPI_CR1_CRCNEXT_Msk (0x1U << SPI_CR1_CRCNEXT_Pos) /*!< 0x00001000 */ #define SPI_CR1_CRCNEXT SPI_CR1_CRCNEXT_Msk /*!<Transmit CRC next */ #define SPI_CR1_CRCEN_Pos (13U) #define SPI_CR1_CRCEN_Msk (0x1U << SPI_CR1_CRCEN_Pos) /*!< 0x00002000 */ #define SPI_CR1_CRCEN SPI_CR1_CRCEN_Msk /*!<Hardware CRC calculation enable */ #define SPI_CR1_BIDIOE_Pos (14U) #define SPI_CR1_BIDIOE_Msk (0x1U << SPI_CR1_BIDIOE_Pos) /*!< 0x00004000 */ #define SPI_CR1_BIDIOE SPI_CR1_BIDIOE_Msk /*!<Output enable in bidirectional mode */ #define SPI_CR1_BIDIMODE_Pos (15U) #define SPI_CR1_BIDIMODE_Msk (0x1U << SPI_CR1_BIDIMODE_Pos) /*!< 0x00008000 */ #define SPI_CR1_BIDIMODE SPI_CR1_BIDIMODE_Msk /*!<Bidirectional data mode enable */ /******************* Bit definition for SPI_CR2 register ********************/ #define SPI_CR2_RXDMAEN_Pos (0U) #define SPI_CR2_RXDMAEN_Msk (0x1U << SPI_CR2_RXDMAEN_Pos) /*!< 0x00000001 */ #define SPI_CR2_RXDMAEN SPI_CR2_RXDMAEN_Msk /*!<Rx Buffer DMA Enable */ #define SPI_CR2_TXDMAEN_Pos (1U) #define SPI_CR2_TXDMAEN_Msk (0x1U << SPI_CR2_TXDMAEN_Pos) /*!< 0x00000002 */ #define SPI_CR2_TXDMAEN SPI_CR2_TXDMAEN_Msk /*!<Tx Buffer DMA Enable */ #define SPI_CR2_SSOE_Pos (2U) #define SPI_CR2_SSOE_Msk (0x1U << SPI_CR2_SSOE_Pos) /*!< 0x00000004 */ #define SPI_CR2_SSOE SPI_CR2_SSOE_Msk /*!<SS Output Enable */ #define SPI_CR2_FRF_Pos (4U) #define SPI_CR2_FRF_Msk (0x1U << SPI_CR2_FRF_Pos) /*!< 0x00000010 */ #define SPI_CR2_FRF SPI_CR2_FRF_Msk /*!<Frame Format */ #define SPI_CR2_ERRIE_Pos (5U) #define SPI_CR2_ERRIE_Msk (0x1U << SPI_CR2_ERRIE_Pos) /*!< 0x00000020 */ #define SPI_CR2_ERRIE SPI_CR2_ERRIE_Msk /*!<Error Interrupt Enable */ #define SPI_CR2_RXNEIE_Pos (6U) #define SPI_CR2_RXNEIE_Msk (0x1U << SPI_CR2_RXNEIE_Pos) /*!< 0x00000040 */ #define SPI_CR2_RXNEIE SPI_CR2_RXNEIE_Msk /*!<RX buffer Not Empty Interrupt Enable */ #define SPI_CR2_TXEIE_Pos (7U) #define SPI_CR2_TXEIE_Msk (0x1U << SPI_CR2_TXEIE_Pos) /*!< 0x00000080 */ #define SPI_CR2_TXEIE SPI_CR2_TXEIE_Msk /*!<Tx buffer Empty Interrupt Enable */ /******************** Bit definition for SPI_SR register ********************/ #define SPI_SR_RXNE_Pos (0U) #define SPI_SR_RXNE_Msk (0x1U << SPI_SR_RXNE_Pos) /*!< 0x00000001 */ #define SPI_SR_RXNE SPI_SR_RXNE_Msk /*!<Receive buffer Not Empty */ #define SPI_SR_TXE_Pos (1U) #define SPI_SR_TXE_Msk (0x1U << SPI_SR_TXE_Pos) /*!< 0x00000002 */ #define SPI_SR_TXE SPI_SR_TXE_Msk /*!<Transmit buffer Empty */ #define SPI_SR_CHSIDE_Pos (2U) #define SPI_SR_CHSIDE_Msk (0x1U << SPI_SR_CHSIDE_Pos) /*!< 0x00000004 */ #define SPI_SR_CHSIDE SPI_SR_CHSIDE_Msk /*!<Channel side */ #define SPI_SR_UDR_Pos (3U) #define SPI_SR_UDR_Msk (0x1U << SPI_SR_UDR_Pos) /*!< 0x00000008 */ #define SPI_SR_UDR SPI_SR_UDR_Msk /*!<Underrun flag */ #define SPI_SR_CRCERR_Pos (4U) #define SPI_SR_CRCERR_Msk (0x1U << SPI_SR_CRCERR_Pos) /*!< 0x00000010 */ #define SPI_SR_CRCERR SPI_SR_CRCERR_Msk /*!<CRC Error flag */ #define SPI_SR_MODF_Pos (5U) #define SPI_SR_MODF_Msk (0x1U << SPI_SR_MODF_Pos) /*!< 0x00000020 */ #define SPI_SR_MODF SPI_SR_MODF_Msk /*!<Mode fault */ #define SPI_SR_OVR_Pos (6U) #define SPI_SR_OVR_Msk (0x1U << SPI_SR_OVR_Pos) /*!< 0x00000040 */ #define SPI_SR_OVR SPI_SR_OVR_Msk /*!<Overrun flag */ #define SPI_SR_BSY_Pos (7U) #define SPI_SR_BSY_Msk (0x1U << SPI_SR_BSY_Pos) /*!< 0x00000080 */ #define SPI_SR_BSY SPI_SR_BSY_Msk /*!<Busy flag */ #define SPI_SR_FRE_Pos (8U) #define SPI_SR_FRE_Msk (0x1U << SPI_SR_FRE_Pos) /*!< 0x00000100 */ #define SPI_SR_FRE SPI_SR_FRE_Msk /*!<Frame format error flag */ /******************** Bit definition for SPI_DR register ********************/ #define SPI_DR_DR_Pos (0U) #define SPI_DR_DR_Msk (0xFFFFU << SPI_DR_DR_Pos) /*!< 0x0000FFFF */ #define SPI_DR_DR SPI_DR_DR_Msk /*!<Data Register */ /******************* Bit definition for SPI_CRCPR register ******************/ #define SPI_CRCPR_CRCPOLY_Pos (0U) #define SPI_CRCPR_CRCPOLY_Msk (0xFFFFU << SPI_CRCPR_CRCPOLY_Pos) /*!< 0x0000FFFF */ #define SPI_CRCPR_CRCPOLY SPI_CRCPR_CRCPOLY_Msk /*!<CRC polynomial register */ /****************** Bit definition for SPI_RXCRCR register ******************/ #define SPI_RXCRCR_RXCRC_Pos (0U) #define SPI_RXCRCR_RXCRC_Msk (0xFFFFU << SPI_RXCRCR_RXCRC_Pos) /*!< 0x0000FFFF */ #define SPI_RXCRCR_RXCRC SPI_RXCRCR_RXCRC_Msk /*!<Rx CRC Register */ /****************** Bit definition for SPI_TXCRCR register ******************/ #define SPI_TXCRCR_TXCRC_Pos (0U) #define SPI_TXCRCR_TXCRC_Msk (0xFFFFU << SPI_TXCRCR_TXCRC_Pos) /*!< 0x0000FFFF */ #define SPI_TXCRCR_TXCRC SPI_TXCRCR_TXCRC_Msk /*!<Tx CRC Register */ /****************** Bit definition for SPI_I2SCFGR register *****************/ #define SPI_I2SCFGR_CHLEN_Pos (0U) #define SPI_I2SCFGR_CHLEN_Msk (0x1U << SPI_I2SCFGR_CHLEN_Pos) /*!< 0x00000001 */ #define SPI_I2SCFGR_CHLEN SPI_I2SCFGR_CHLEN_Msk /*!<Channel length (number of bits per audio channel) */ #define SPI_I2SCFGR_DATLEN_Pos (1U) #define SPI_I2SCFGR_DATLEN_Msk (0x3U << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000006 */ #define SPI_I2SCFGR_DATLEN SPI_I2SCFGR_DATLEN_Msk /*!<DATLEN[1:0] bits (Data length to be transferred) */ #define SPI_I2SCFGR_DATLEN_0 (0x1U << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000002 */ #define SPI_I2SCFGR_DATLEN_1 (0x2U << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000004 */ #define SPI_I2SCFGR_CKPOL_Pos (3U) #define SPI_I2SCFGR_CKPOL_Msk (0x1U << SPI_I2SCFGR_CKPOL_Pos) /*!< 0x00000008 */ #define SPI_I2SCFGR_CKPOL SPI_I2SCFGR_CKPOL_Msk /*!<steady state clock polarity */ #define SPI_I2SCFGR_I2SSTD_Pos (4U) #define SPI_I2SCFGR_I2SSTD_Msk (0x3U << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000030 */ #define SPI_I2SCFGR_I2SSTD SPI_I2SCFGR_I2SSTD_Msk /*!<I2SSTD[1:0] bits (I2S standard selection) */ #define SPI_I2SCFGR_I2SSTD_0 (0x1U << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000010 */ #define SPI_I2SCFGR_I2SSTD_1 (0x2U << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000020 */ #define SPI_I2SCFGR_PCMSYNC_Pos (7U) #define SPI_I2SCFGR_PCMSYNC_Msk (0x1U << SPI_I2SCFGR_PCMSYNC_Pos) /*!< 0x00000080 */ #define SPI_I2SCFGR_PCMSYNC SPI_I2SCFGR_PCMSYNC_Msk /*!<PCM frame synchronization */ #define SPI_I2SCFGR_I2SCFG_Pos (8U) #define SPI_I2SCFGR_I2SCFG_Msk (0x3U << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000300 */ #define SPI_I2SCFGR_I2SCFG SPI_I2SCFGR_I2SCFG_Msk /*!<I2SCFG[1:0] bits (I2S configuration mode) */ #define SPI_I2SCFGR_I2SCFG_0 (0x1U << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000100 */ #define SPI_I2SCFGR_I2SCFG_1 (0x2U << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000200 */ #define SPI_I2SCFGR_I2SE_Pos (10U) #define SPI_I2SCFGR_I2SE_Msk (0x1U << SPI_I2SCFGR_I2SE_Pos) /*!< 0x00000400 */ #define SPI_I2SCFGR_I2SE SPI_I2SCFGR_I2SE_Msk /*!<I2S Enable */ #define SPI_I2SCFGR_I2SMOD_Pos (11U) #define SPI_I2SCFGR_I2SMOD_Msk (0x1U << SPI_I2SCFGR_I2SMOD_Pos) /*!< 0x00000800 */ #define SPI_I2SCFGR_I2SMOD SPI_I2SCFGR_I2SMOD_Msk /*!<I2S mode selection */ #define SPI_I2SCFGR_ASTRTEN_Pos (12U) #define SPI_I2SCFGR_ASTRTEN_Msk (0x1U << SPI_I2SCFGR_ASTRTEN_Pos) /*!< 0x00001000 */ #define SPI_I2SCFGR_ASTRTEN SPI_I2SCFGR_ASTRTEN_Msk /*!<Asynchronous start enable */ /****************** Bit definition for SPI_I2SPR register *******************/ #define SPI_I2SPR_I2SDIV_Pos (0U) #define SPI_I2SPR_I2SDIV_Msk (0xFFU << SPI_I2SPR_I2SDIV_Pos) /*!< 0x000000FF */ #define SPI_I2SPR_I2SDIV SPI_I2SPR_I2SDIV_Msk /*!<I2S Linear prescaler */ #define SPI_I2SPR_ODD_Pos (8U) #define SPI_I2SPR_ODD_Msk (0x1U << SPI_I2SPR_ODD_Pos) /*!< 0x00000100 */ #define SPI_I2SPR_ODD SPI_I2SPR_ODD_Msk /*!<Odd factor for the prescaler */ #define SPI_I2SPR_MCKOE_Pos (9U) #define SPI_I2SPR_MCKOE_Msk (0x1U << SPI_I2SPR_MCKOE_Pos) /*!< 0x00000200 */ #define SPI_I2SPR_MCKOE SPI_I2SPR_MCKOE_Msk /*!<Master Clock Output Enable */ /******************************************************************************/ /* */ /* SYSCFG */ /* */ /******************************************************************************/ /****************** Bit definition for SYSCFG_MEMRMP register ***************/ #define SYSCFG_MEMRMP_MEM_MODE_Pos (0U) #define SYSCFG_MEMRMP_MEM_MODE_Msk (0x7U << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000007 */ #define SYSCFG_MEMRMP_MEM_MODE SYSCFG_MEMRMP_MEM_MODE_Msk /*!< SYSCFG_Memory Remap Config */ #define SYSCFG_MEMRMP_MEM_MODE_0 (0x1U << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000001 */ #define SYSCFG_MEMRMP_MEM_MODE_1 (0x2U << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000002 */ #define SYSCFG_MEMRMP_MEM_MODE_2 (0x4U << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000004 */ #define SYSCFG_MEMRMP_UFB_MODE_Pos (8U) #define SYSCFG_MEMRMP_UFB_MODE_Msk (0x1U << SYSCFG_MEMRMP_UFB_MODE_Pos) /*!< 0x00000100 */ #define SYSCFG_MEMRMP_UFB_MODE SYSCFG_MEMRMP_UFB_MODE_Msk /*!< User Flash Bank mode */ #define SYSCFG_MEMRMP_SWP_FMC_Pos (10U) #define SYSCFG_MEMRMP_SWP_FMC_Msk (0x3U << SYSCFG_MEMRMP_SWP_FMC_Pos) /*!< 0x00000C00 */ #define SYSCFG_MEMRMP_SWP_FMC SYSCFG_MEMRMP_SWP_FMC_Msk /*!< FMC memory mapping swap */ #define SYSCFG_MEMRMP_SWP_FMC_0 (0x1U << SYSCFG_MEMRMP_SWP_FMC_Pos) /*!< 0x00000400 */ /* Legacy Defines */ #define SYSCFG_SWP_FMC SYSCFG_MEMRMP_SWP_FMC /****************** Bit definition for SYSCFG_PMC register ******************/ #define SYSCFG_PMC_ADCxDC2_Pos (16U) #define SYSCFG_PMC_ADCxDC2_Msk (0x7U << SYSCFG_PMC_ADCxDC2_Pos) /*!< 0x00070000 */ #define SYSCFG_PMC_ADCxDC2 SYSCFG_PMC_ADCxDC2_Msk /*!< Refer to AN4073 on how to use this bit */ #define SYSCFG_PMC_ADC1DC2_Pos (16U) #define SYSCFG_PMC_ADC1DC2_Msk (0x1U << SYSCFG_PMC_ADC1DC2_Pos) /*!< 0x00010000 */ #define SYSCFG_PMC_ADC1DC2 SYSCFG_PMC_ADC1DC2_Msk /*!< Refer to AN4073 on how to use this bit */ #define SYSCFG_PMC_ADC2DC2_Pos (17U) #define SYSCFG_PMC_ADC2DC2_Msk (0x1U << SYSCFG_PMC_ADC2DC2_Pos) /*!< 0x00020000 */ #define SYSCFG_PMC_ADC2DC2 SYSCFG_PMC_ADC2DC2_Msk /*!< Refer to AN4073 on how to use this bit */ #define SYSCFG_PMC_ADC3DC2_Pos (18U) #define SYSCFG_PMC_ADC3DC2_Msk (0x1U << SYSCFG_PMC_ADC3DC2_Pos) /*!< 0x00040000 */ #define SYSCFG_PMC_ADC3DC2 SYSCFG_PMC_ADC3DC2_Msk /*!< Refer to AN4073 on how to use this bit */ #define SYSCFG_PMC_MII_RMII_SEL_Pos (23U) #define SYSCFG_PMC_MII_RMII_SEL_Msk (0x1U << SYSCFG_PMC_MII_RMII_SEL_Pos) /*!< 0x00800000 */ #define SYSCFG_PMC_MII_RMII_SEL SYSCFG_PMC_MII_RMII_SEL_Msk /*!<Ethernet PHY interface selection */ /***************** Bit definition for SYSCFG_EXTICR1 register ***************/ #define SYSCFG_EXTICR1_EXTI0_Pos (0U) #define SYSCFG_EXTICR1_EXTI0_Msk (0xFU << SYSCFG_EXTICR1_EXTI0_Pos) /*!< 0x0000000F */ #define SYSCFG_EXTICR1_EXTI0 SYSCFG_EXTICR1_EXTI0_Msk /*!<EXTI 0 configuration */ #define SYSCFG_EXTICR1_EXTI1_Pos (4U) #define SYSCFG_EXTICR1_EXTI1_Msk (0xFU << SYSCFG_EXTICR1_EXTI1_Pos) /*!< 0x000000F0 */ #define SYSCFG_EXTICR1_EXTI1 SYSCFG_EXTICR1_EXTI1_Msk /*!<EXTI 1 configuration */ #define SYSCFG_EXTICR1_EXTI2_Pos (8U) #define SYSCFG_EXTICR1_EXTI2_Msk (0xFU << SYSCFG_EXTICR1_EXTI2_Pos) /*!< 0x00000F00 */ #define SYSCFG_EXTICR1_EXTI2 SYSCFG_EXTICR1_EXTI2_Msk /*!<EXTI 2 configuration */ #define SYSCFG_EXTICR1_EXTI3_Pos (12U) #define SYSCFG_EXTICR1_EXTI3_Msk (0xFU << SYSCFG_EXTICR1_EXTI3_Pos) /*!< 0x0000F000 */ #define SYSCFG_EXTICR1_EXTI3 SYSCFG_EXTICR1_EXTI3_Msk /*!<EXTI 3 configuration */ /** * @brief EXTI0 configuration */ #define SYSCFG_EXTICR1_EXTI0_PA 0x0000U /*!<PA[0] pin */ #define SYSCFG_EXTICR1_EXTI0_PB 0x0001U /*!<PB[0] pin */ #define SYSCFG_EXTICR1_EXTI0_PC 0x0002U /*!<PC[0] pin */ #define SYSCFG_EXTICR1_EXTI0_PD 0x0003U /*!<PD[0] pin */ #define SYSCFG_EXTICR1_EXTI0_PE 0x0004U /*!<PE[0] pin */ #define SYSCFG_EXTICR1_EXTI0_PF 0x0005U /*!<PF[0] pin */ #define SYSCFG_EXTICR1_EXTI0_PG 0x0006U /*!<PG[0] pin */ #define SYSCFG_EXTICR1_EXTI0_PH 0x0007U /*!<PH[0] pin */ #define SYSCFG_EXTICR1_EXTI0_PI 0x0008U /*!<PI[0] pin */ #define SYSCFG_EXTICR1_EXTI0_PJ 0x0009U /*!<PJ[0] pin */ #define SYSCFG_EXTICR1_EXTI0_PK 0x000AU /*!<PK[0] pin */ /** * @brief EXTI1 configuration */ #define SYSCFG_EXTICR1_EXTI1_PA 0x0000U /*!<PA[1] pin */ #define SYSCFG_EXTICR1_EXTI1_PB 0x0010U /*!<PB[1] pin */ #define SYSCFG_EXTICR1_EXTI1_PC 0x0020U /*!<PC[1] pin */ #define SYSCFG_EXTICR1_EXTI1_PD 0x0030U /*!<PD[1] pin */ #define SYSCFG_EXTICR1_EXTI1_PE 0x0040U /*!<PE[1] pin */ #define SYSCFG_EXTICR1_EXTI1_PF 0x0050U /*!<PF[1] pin */ #define SYSCFG_EXTICR1_EXTI1_PG 0x0060U /*!<PG[1] pin */ #define SYSCFG_EXTICR1_EXTI1_PH 0x0070U /*!<PH[1] pin */ #define SYSCFG_EXTICR1_EXTI1_PI 0x0080U /*!<PI[1] pin */ #define SYSCFG_EXTICR1_EXTI1_PJ 0x0090U /*!<PJ[1] pin */ #define SYSCFG_EXTICR1_EXTI1_PK 0x00A0U /*!<PK[1] pin */ /** * @brief EXTI2 configuration */ #define SYSCFG_EXTICR1_EXTI2_PA 0x0000U /*!<PA[2] pin */ #define SYSCFG_EXTICR1_EXTI2_PB 0x0100U /*!<PB[2] pin */ #define SYSCFG_EXTICR1_EXTI2_PC 0x0200U /*!<PC[2] pin */ #define SYSCFG_EXTICR1_EXTI2_PD 0x0300U /*!<PD[2] pin */ #define SYSCFG_EXTICR1_EXTI2_PE 0x0400U /*!<PE[2] pin */ #define SYSCFG_EXTICR1_EXTI2_PF 0x0500U /*!<PF[2] pin */ #define SYSCFG_EXTICR1_EXTI2_PG 0x0600U /*!<PG[2] pin */ #define SYSCFG_EXTICR1_EXTI2_PH 0x0700U /*!<PH[2] pin */ #define SYSCFG_EXTICR1_EXTI2_PI 0x0800U /*!<PI[2] pin */ #define SYSCFG_EXTICR1_EXTI2_PJ 0x0900U /*!<PJ[2] pin */ #define SYSCFG_EXTICR1_EXTI2_PK 0x0A00U /*!<PK[2] pin */ /** * @brief EXTI3 configuration */ #define SYSCFG_EXTICR1_EXTI3_PA 0x0000U /*!<PA[3] pin */ #define SYSCFG_EXTICR1_EXTI3_PB 0x1000U /*!<PB[3] pin */ #define SYSCFG_EXTICR1_EXTI3_PC 0x2000U /*!<PC[3] pin */ #define SYSCFG_EXTICR1_EXTI3_PD 0x3000U /*!<PD[3] pin */ #define SYSCFG_EXTICR1_EXTI3_PE 0x4000U /*!<PE[3] pin */ #define SYSCFG_EXTICR1_EXTI3_PF 0x5000U /*!<PF[3] pin */ #define SYSCFG_EXTICR1_EXTI3_PG 0x6000U /*!<PG[3] pin */ #define SYSCFG_EXTICR1_EXTI3_PH 0x7000U /*!<PH[3] pin */ #define SYSCFG_EXTICR1_EXTI3_PI 0x8000U /*!<PI[3] pin */ #define SYSCFG_EXTICR1_EXTI3_PJ 0x9000U /*!<PJ[3] pin */ #define SYSCFG_EXTICR1_EXTI3_PK 0xA000U /*!<PK[3] pin */ /***************** Bit definition for SYSCFG_EXTICR2 register ***************/ #define SYSCFG_EXTICR2_EXTI4_Pos (0U) #define SYSCFG_EXTICR2_EXTI4_Msk (0xFU << SYSCFG_EXTICR2_EXTI4_Pos) /*!< 0x0000000F */ #define SYSCFG_EXTICR2_EXTI4 SYSCFG_EXTICR2_EXTI4_Msk /*!<EXTI 4 configuration */ #define SYSCFG_EXTICR2_EXTI5_Pos (4U) #define SYSCFG_EXTICR2_EXTI5_Msk (0xFU << SYSCFG_EXTICR2_EXTI5_Pos) /*!< 0x000000F0 */ #define SYSCFG_EXTICR2_EXTI5 SYSCFG_EXTICR2_EXTI5_Msk /*!<EXTI 5 configuration */ #define SYSCFG_EXTICR2_EXTI6_Pos (8U) #define SYSCFG_EXTICR2_EXTI6_Msk (0xFU << SYSCFG_EXTICR2_EXTI6_Pos) /*!< 0x00000F00 */ #define SYSCFG_EXTICR2_EXTI6 SYSCFG_EXTICR2_EXTI6_Msk /*!<EXTI 6 configuration */ #define SYSCFG_EXTICR2_EXTI7_Pos (12U) #define SYSCFG_EXTICR2_EXTI7_Msk (0xFU << SYSCFG_EXTICR2_EXTI7_Pos) /*!< 0x0000F000 */ #define SYSCFG_EXTICR2_EXTI7 SYSCFG_EXTICR2_EXTI7_Msk /*!<EXTI 7 configuration */ /** * @brief EXTI4 configuration */ #define SYSCFG_EXTICR2_EXTI4_PA 0x0000U /*!<PA[4] pin */ #define SYSCFG_EXTICR2_EXTI4_PB 0x0001U /*!<PB[4] pin */ #define SYSCFG_EXTICR2_EXTI4_PC 0x0002U /*!<PC[4] pin */ #define SYSCFG_EXTICR2_EXTI4_PD 0x0003U /*!<PD[4] pin */ #define SYSCFG_EXTICR2_EXTI4_PE 0x0004U /*!<PE[4] pin */ #define SYSCFG_EXTICR2_EXTI4_PF 0x0005U /*!<PF[4] pin */ #define SYSCFG_EXTICR2_EXTI4_PG 0x0006U /*!<PG[4] pin */ #define SYSCFG_EXTICR2_EXTI4_PH 0x0007U /*!<PH[4] pin */ #define SYSCFG_EXTICR2_EXTI4_PI 0x0008U /*!<PI[4] pin */ #define SYSCFG_EXTICR2_EXTI4_PJ 0x0009U /*!<PJ[4] pin */ #define SYSCFG_EXTICR2_EXTI4_PK 0x000AU /*!<PK[4] pin */ /** * @brief EXTI5 configuration */ #define SYSCFG_EXTICR2_EXTI5_PA 0x0000U /*!<PA[5] pin */ #define SYSCFG_EXTICR2_EXTI5_PB 0x0010U /*!<PB[5] pin */ #define SYSCFG_EXTICR2_EXTI5_PC 0x0020U /*!<PC[5] pin */ #define SYSCFG_EXTICR2_EXTI5_PD 0x0030U /*!<PD[5] pin */ #define SYSCFG_EXTICR2_EXTI5_PE 0x0040U /*!<PE[5] pin */ #define SYSCFG_EXTICR2_EXTI5_PF 0x0050U /*!<PF[5] pin */ #define SYSCFG_EXTICR2_EXTI5_PG 0x0060U /*!<PG[5] pin */ #define SYSCFG_EXTICR2_EXTI5_PH 0x0070U /*!<PH[5] pin */ #define SYSCFG_EXTICR2_EXTI5_PI 0x0080U /*!<PI[5] pin */ #define SYSCFG_EXTICR2_EXTI5_PJ 0x0090U /*!<PJ[5] pin */ #define SYSCFG_EXTICR2_EXTI5_PK 0x00A0U /*!<PK[5] pin */ /** * @brief EXTI6 configuration */ #define SYSCFG_EXTICR2_EXTI6_PA 0x0000U /*!<PA[6] pin */ #define SYSCFG_EXTICR2_EXTI6_PB 0x0100U /*!<PB[6] pin */ #define SYSCFG_EXTICR2_EXTI6_PC 0x0200U /*!<PC[6] pin */ #define SYSCFG_EXTICR2_EXTI6_PD 0x0300U /*!<PD[6] pin */ #define SYSCFG_EXTICR2_EXTI6_PE 0x0400U /*!<PE[6] pin */ #define SYSCFG_EXTICR2_EXTI6_PF 0x0500U /*!<PF[6] pin */ #define SYSCFG_EXTICR2_EXTI6_PG 0x0600U /*!<PG[6] pin */ #define SYSCFG_EXTICR2_EXTI6_PH 0x0700U /*!<PH[6] pin */ #define SYSCFG_EXTICR2_EXTI6_PI 0x0800U /*!<PI[6] pin */ #define SYSCFG_EXTICR2_EXTI6_PJ 0x0900U /*!<PJ[6] pin */ #define SYSCFG_EXTICR2_EXTI6_PK 0x0A00U /*!<PK[6] pin */ /** * @brief EXTI7 configuration */ #define SYSCFG_EXTICR2_EXTI7_PA 0x0000U /*!<PA[7] pin */ #define SYSCFG_EXTICR2_EXTI7_PB 0x1000U /*!<PB[7] pin */ #define SYSCFG_EXTICR2_EXTI7_PC 0x2000U /*!<PC[7] pin */ #define SYSCFG_EXTICR2_EXTI7_PD 0x3000U /*!<PD[7] pin */ #define SYSCFG_EXTICR2_EXTI7_PE 0x4000U /*!<PE[7] pin */ #define SYSCFG_EXTICR2_EXTI7_PF 0x5000U /*!<PF[7] pin */ #define SYSCFG_EXTICR2_EXTI7_PG 0x6000U /*!<PG[7] pin */ #define SYSCFG_EXTICR2_EXTI7_PH 0x7000U /*!<PH[7] pin */ #define SYSCFG_EXTICR2_EXTI7_PI 0x8000U /*!<PI[7] pin */ #define SYSCFG_EXTICR2_EXTI7_PJ 0x9000U /*!<PJ[7] pin */ #define SYSCFG_EXTICR2_EXTI7_PK 0xA000U /*!<PK[7] pin */ /***************** Bit definition for SYSCFG_EXTICR3 register ***************/ #define SYSCFG_EXTICR3_EXTI8_Pos (0U) #define SYSCFG_EXTICR3_EXTI8_Msk (0xFU << SYSCFG_EXTICR3_EXTI8_Pos) /*!< 0x0000000F */ #define SYSCFG_EXTICR3_EXTI8 SYSCFG_EXTICR3_EXTI8_Msk /*!<EXTI 8 configuration */ #define SYSCFG_EXTICR3_EXTI9_Pos (4U) #define SYSCFG_EXTICR3_EXTI9_Msk (0xFU << SYSCFG_EXTICR3_EXTI9_Pos) /*!< 0x000000F0 */ #define SYSCFG_EXTICR3_EXTI9 SYSCFG_EXTICR3_EXTI9_Msk /*!<EXTI 9 configuration */ #define SYSCFG_EXTICR3_EXTI10_Pos (8U) #define SYSCFG_EXTICR3_EXTI10_Msk (0xFU << SYSCFG_EXTICR3_EXTI10_Pos) /*!< 0x00000F00 */ #define SYSCFG_EXTICR3_EXTI10 SYSCFG_EXTICR3_EXTI10_Msk /*!<EXTI 10 configuration */ #define SYSCFG_EXTICR3_EXTI11_Pos (12U) #define SYSCFG_EXTICR3_EXTI11_Msk (0xFU << SYSCFG_EXTICR3_EXTI11_Pos) /*!< 0x0000F000 */ #define SYSCFG_EXTICR3_EXTI11 SYSCFG_EXTICR3_EXTI11_Msk /*!<EXTI 11 configuration */ /** * @brief EXTI8 configuration */ #define SYSCFG_EXTICR3_EXTI8_PA 0x0000U /*!<PA[8] pin */ #define SYSCFG_EXTICR3_EXTI8_PB 0x0001U /*!<PB[8] pin */ #define SYSCFG_EXTICR3_EXTI8_PC 0x0002U /*!<PC[8] pin */ #define SYSCFG_EXTICR3_EXTI8_PD 0x0003U /*!<PD[8] pin */ #define SYSCFG_EXTICR3_EXTI8_PE 0x0004U /*!<PE[8] pin */ #define SYSCFG_EXTICR3_EXTI8_PF 0x0005U /*!<PF[8] pin */ #define SYSCFG_EXTICR3_EXTI8_PG 0x0006U /*!<PG[8] pin */ #define SYSCFG_EXTICR3_EXTI8_PH 0x0007U /*!<PH[8] pin */ #define SYSCFG_EXTICR3_EXTI8_PI 0x0008U /*!<PI[8] pin */ #define SYSCFG_EXTICR3_EXTI8_PJ 0x0009U /*!<PJ[8] pin */ /** * @brief EXTI9 configuration */ #define SYSCFG_EXTICR3_EXTI9_PA 0x0000U /*!<PA[9] pin */ #define SYSCFG_EXTICR3_EXTI9_PB 0x0010U /*!<PB[9] pin */ #define SYSCFG_EXTICR3_EXTI9_PC 0x0020U /*!<PC[9] pin */ #define SYSCFG_EXTICR3_EXTI9_PD 0x0030U /*!<PD[9] pin */ #define SYSCFG_EXTICR3_EXTI9_PE 0x0040U /*!<PE[9] pin */ #define SYSCFG_EXTICR3_EXTI9_PF 0x0050U /*!<PF[9] pin */ #define SYSCFG_EXTICR3_EXTI9_PG 0x0060U /*!<PG[9] pin */ #define SYSCFG_EXTICR3_EXTI9_PH 0x0070U /*!<PH[9] pin */ #define SYSCFG_EXTICR3_EXTI9_PI 0x0080U /*!<PI[9] pin */ #define SYSCFG_EXTICR3_EXTI9_PJ 0x0090U /*!<PJ[9] pin */ /** * @brief EXTI10 configuration */ #define SYSCFG_EXTICR3_EXTI10_PA 0x0000U /*!<PA[10] pin */ #define SYSCFG_EXTICR3_EXTI10_PB 0x0100U /*!<PB[10] pin */ #define SYSCFG_EXTICR3_EXTI10_PC 0x0200U /*!<PC[10] pin */ #define SYSCFG_EXTICR3_EXTI10_PD 0x0300U /*!<PD[10] pin */ #define SYSCFG_EXTICR3_EXTI10_PE 0x0400U /*!<PE[10] pin */ #define SYSCFG_EXTICR3_EXTI10_PF 0x0500U /*!<PF[10] pin */ #define SYSCFG_EXTICR3_EXTI10_PG 0x0600U /*!<PG[10] pin */ #define SYSCFG_EXTICR3_EXTI10_PH 0x0700U /*!<PH[10] pin */ #define SYSCFG_EXTICR3_EXTI10_PI 0x0800U /*!<PI[10] pin */ #define SYSCFG_EXTICR3_EXTI10_PJ 0x0900U /*!<PJ[10] pin */ /** * @brief EXTI11 configuration */ #define SYSCFG_EXTICR3_EXTI11_PA 0x0000U /*!<PA[11] pin */ #define SYSCFG_EXTICR3_EXTI11_PB 0x1000U /*!<PB[11] pin */ #define SYSCFG_EXTICR3_EXTI11_PC 0x2000U /*!<PC[11] pin */ #define SYSCFG_EXTICR3_EXTI11_PD 0x3000U /*!<PD[11] pin */ #define SYSCFG_EXTICR3_EXTI11_PE 0x4000U /*!<PE[11] pin */ #define SYSCFG_EXTICR3_EXTI11_PF 0x5000U /*!<PF[11] pin */ #define SYSCFG_EXTICR3_EXTI11_PG 0x6000U /*!<PG[11] pin */ #define SYSCFG_EXTICR3_EXTI11_PH 0x7000U /*!<PH[11] pin */ #define SYSCFG_EXTICR3_EXTI11_PI 0x8000U /*!<PI[11] pin */ #define SYSCFG_EXTICR3_EXTI11_PJ 0x9000U /*!<PJ[11] pin */ /***************** Bit definition for SYSCFG_EXTICR4 register ***************/ #define SYSCFG_EXTICR4_EXTI12_Pos (0U) #define SYSCFG_EXTICR4_EXTI12_Msk (0xFU << SYSCFG_EXTICR4_EXTI12_Pos) /*!< 0x0000000F */ #define SYSCFG_EXTICR4_EXTI12 SYSCFG_EXTICR4_EXTI12_Msk /*!<EXTI 12 configuration */ #define SYSCFG_EXTICR4_EXTI13_Pos (4U) #define SYSCFG_EXTICR4_EXTI13_Msk (0xFU << SYSCFG_EXTICR4_EXTI13_Pos) /*!< 0x000000F0 */ #define SYSCFG_EXTICR4_EXTI13 SYSCFG_EXTICR4_EXTI13_Msk /*!<EXTI 13 configuration */ #define SYSCFG_EXTICR4_EXTI14_Pos (8U) #define SYSCFG_EXTICR4_EXTI14_Msk (0xFU << SYSCFG_EXTICR4_EXTI14_Pos) /*!< 0x00000F00 */ #define SYSCFG_EXTICR4_EXTI14 SYSCFG_EXTICR4_EXTI14_Msk /*!<EXTI 14 configuration */ #define SYSCFG_EXTICR4_EXTI15_Pos (12U) #define SYSCFG_EXTICR4_EXTI15_Msk (0xFU << SYSCFG_EXTICR4_EXTI15_Pos) /*!< 0x0000F000 */ #define SYSCFG_EXTICR4_EXTI15 SYSCFG_EXTICR4_EXTI15_Msk /*!<EXTI 15 configuration */ /** * @brief EXTI12 configuration */ #define SYSCFG_EXTICR4_EXTI12_PA 0x0000U /*!<PA[12] pin */ #define SYSCFG_EXTICR4_EXTI12_PB 0x0001U /*!<PB[12] pin */ #define SYSCFG_EXTICR4_EXTI12_PC 0x0002U /*!<PC[12] pin */ #define SYSCFG_EXTICR4_EXTI12_PD 0x0003U /*!<PD[12] pin */ #define SYSCFG_EXTICR4_EXTI12_PE 0x0004U /*!<PE[12] pin */ #define SYSCFG_EXTICR4_EXTI12_PF 0x0005U /*!<PF[12] pin */ #define SYSCFG_EXTICR4_EXTI12_PG 0x0006U /*!<PG[12] pin */ #define SYSCFG_EXTICR4_EXTI12_PH 0x0007U /*!<PH[12] pin */ #define SYSCFG_EXTICR4_EXTI12_PI 0x0008U /*!<PI[12] pin */ #define SYSCFG_EXTICR4_EXTI12_PJ 0x0009U /*!<PJ[12] pin */ /** * @brief EXTI13 configuration */ #define SYSCFG_EXTICR4_EXTI13_PA 0x0000U /*!<PA[13] pin */ #define SYSCFG_EXTICR4_EXTI13_PB 0x0010U /*!<PB[13] pin */ #define SYSCFG_EXTICR4_EXTI13_PC 0x0020U /*!<PC[13] pin */ #define SYSCFG_EXTICR4_EXTI13_PD 0x0030U /*!<PD[13] pin */ #define SYSCFG_EXTICR4_EXTI13_PE 0x0040U /*!<PE[13] pin */ #define SYSCFG_EXTICR4_EXTI13_PF 0x0050U /*!<PF[13] pin */ #define SYSCFG_EXTICR4_EXTI13_PG 0x0060U /*!<PG[13] pin */ #define SYSCFG_EXTICR4_EXTI13_PH 0x0070U /*!<PH[13] pin */ #define SYSCFG_EXTICR4_EXTI13_PI 0x0008U /*!<PI[13] pin */ #define SYSCFG_EXTICR4_EXTI13_PJ 0x0009U /*!<PJ[13] pin */ /** * @brief EXTI14 configuration */ #define SYSCFG_EXTICR4_EXTI14_PA 0x0000U /*!<PA[14] pin */ #define SYSCFG_EXTICR4_EXTI14_PB 0x0100U /*!<PB[14] pin */ #define SYSCFG_EXTICR4_EXTI14_PC 0x0200U /*!<PC[14] pin */ #define SYSCFG_EXTICR4_EXTI14_PD 0x0300U /*!<PD[14] pin */ #define SYSCFG_EXTICR4_EXTI14_PE 0x0400U /*!<PE[14] pin */ #define SYSCFG_EXTICR4_EXTI14_PF 0x0500U /*!<PF[14] pin */ #define SYSCFG_EXTICR4_EXTI14_PG 0x0600U /*!<PG[14] pin */ #define SYSCFG_EXTICR4_EXTI14_PH 0x0700U /*!<PH[14] pin */ #define SYSCFG_EXTICR4_EXTI14_PI 0x0800U /*!<PI[14] pin */ #define SYSCFG_EXTICR4_EXTI14_PJ 0x0900U /*!<PJ[14] pin */ /** * @brief EXTI15 configuration */ #define SYSCFG_EXTICR4_EXTI15_PA 0x0000U /*!<PA[15] pin */ #define SYSCFG_EXTICR4_EXTI15_PB 0x1000U /*!<PB[15] pin */ #define SYSCFG_EXTICR4_EXTI15_PC 0x2000U /*!<PC[15] pin */ #define SYSCFG_EXTICR4_EXTI15_PD 0x3000U /*!<PD[15] pin */ #define SYSCFG_EXTICR4_EXTI15_PE 0x4000U /*!<PE[15] pin */ #define SYSCFG_EXTICR4_EXTI15_PF 0x5000U /*!<PF[15] pin */ #define SYSCFG_EXTICR4_EXTI15_PG 0x6000U /*!<PG[15] pin */ #define SYSCFG_EXTICR4_EXTI15_PH 0x7000U /*!<PH[15] pin */ #define SYSCFG_EXTICR4_EXTI15_PI 0x8000U /*!<PI[15] pin */ #define SYSCFG_EXTICR4_EXTI15_PJ 0x9000U /*!<PJ[15] pin */ /****************** Bit definition for SYSCFG_CMPCR register ****************/ #define SYSCFG_CMPCR_CMP_PD_Pos (0U) #define SYSCFG_CMPCR_CMP_PD_Msk (0x1U << SYSCFG_CMPCR_CMP_PD_Pos) /*!< 0x00000001 */ #define SYSCFG_CMPCR_CMP_PD SYSCFG_CMPCR_CMP_PD_Msk /*!<Compensation cell ready flag */ #define SYSCFG_CMPCR_READY_Pos (8U) #define SYSCFG_CMPCR_READY_Msk (0x1U << SYSCFG_CMPCR_READY_Pos) /*!< 0x00000100 */ #define SYSCFG_CMPCR_READY SYSCFG_CMPCR_READY_Msk /*!<Compensation cell power-down */ /******************************************************************************/ /* */ /* TIM */ /* */ /******************************************************************************/ /******************* Bit definition for TIM_CR1 register ********************/ #define TIM_CR1_CEN_Pos (0U) #define TIM_CR1_CEN_Msk (0x1U << TIM_CR1_CEN_Pos) /*!< 0x00000001 */ #define TIM_CR1_CEN TIM_CR1_CEN_Msk /*!<Counter enable */ #define TIM_CR1_UDIS_Pos (1U) #define TIM_CR1_UDIS_Msk (0x1U << TIM_CR1_UDIS_Pos) /*!< 0x00000002 */ #define TIM_CR1_UDIS TIM_CR1_UDIS_Msk /*!<Update disable */ #define TIM_CR1_URS_Pos (2U) #define TIM_CR1_URS_Msk (0x1U << TIM_CR1_URS_Pos) /*!< 0x00000004 */ #define TIM_CR1_URS TIM_CR1_URS_Msk /*!<Update request source */ #define TIM_CR1_OPM_Pos (3U) #define TIM_CR1_OPM_Msk (0x1U << TIM_CR1_OPM_Pos) /*!< 0x00000008 */ #define TIM_CR1_OPM TIM_CR1_OPM_Msk /*!<One pulse mode */ #define TIM_CR1_DIR_Pos (4U) #define TIM_CR1_DIR_Msk (0x1U << TIM_CR1_DIR_Pos) /*!< 0x00000010 */ #define TIM_CR1_DIR TIM_CR1_DIR_Msk /*!<Direction */ #define TIM_CR1_CMS_Pos (5U) #define TIM_CR1_CMS_Msk (0x3U << TIM_CR1_CMS_Pos) /*!< 0x00000060 */ #define TIM_CR1_CMS TIM_CR1_CMS_Msk /*!<CMS[1:0] bits (Center-aligned mode selection) */ #define TIM_CR1_CMS_0 (0x1U << TIM_CR1_CMS_Pos) /*!< 0x0020 */ #define TIM_CR1_CMS_1 (0x2U << TIM_CR1_CMS_Pos) /*!< 0x0040 */ #define TIM_CR1_ARPE_Pos (7U) #define TIM_CR1_ARPE_Msk (0x1U << TIM_CR1_ARPE_Pos) /*!< 0x00000080 */ #define TIM_CR1_ARPE TIM_CR1_ARPE_Msk /*!<Auto-reload preload enable */ #define TIM_CR1_CKD_Pos (8U) #define TIM_CR1_CKD_Msk (0x3U << TIM_CR1_CKD_Pos) /*!< 0x00000300 */ #define TIM_CR1_CKD TIM_CR1_CKD_Msk /*!<CKD[1:0] bits (clock division) */ #define TIM_CR1_CKD_0 (0x1U << TIM_CR1_CKD_Pos) /*!< 0x0100 */ #define TIM_CR1_CKD_1 (0x2U << TIM_CR1_CKD_Pos) /*!< 0x0200 */ /******************* Bit definition for TIM_CR2 register ********************/ #define TIM_CR2_CCPC_Pos (0U) #define TIM_CR2_CCPC_Msk (0x1U << TIM_CR2_CCPC_Pos) /*!< 0x00000001 */ #define TIM_CR2_CCPC TIM_CR2_CCPC_Msk /*!<Capture/Compare Preloaded Control */ #define TIM_CR2_CCUS_Pos (2U) #define TIM_CR2_CCUS_Msk (0x1U << TIM_CR2_CCUS_Pos) /*!< 0x00000004 */ #define TIM_CR2_CCUS TIM_CR2_CCUS_Msk /*!<Capture/Compare Control Update Selection */ #define TIM_CR2_CCDS_Pos (3U) #define TIM_CR2_CCDS_Msk (0x1U << TIM_CR2_CCDS_Pos) /*!< 0x00000008 */ #define TIM_CR2_CCDS TIM_CR2_CCDS_Msk /*!<Capture/Compare DMA Selection */ #define TIM_CR2_MMS_Pos (4U) #define TIM_CR2_MMS_Msk (0x7U << TIM_CR2_MMS_Pos) /*!< 0x00000070 */ #define TIM_CR2_MMS TIM_CR2_MMS_Msk /*!<MMS[2:0] bits (Master Mode Selection) */ #define TIM_CR2_MMS_0 (0x1U << TIM_CR2_MMS_Pos) /*!< 0x0010 */ #define TIM_CR2_MMS_1 (0x2U << TIM_CR2_MMS_Pos) /*!< 0x0020 */ #define TIM_CR2_MMS_2 (0x4U << TIM_CR2_MMS_Pos) /*!< 0x0040 */ #define TIM_CR2_TI1S_Pos (7U) #define TIM_CR2_TI1S_Msk (0x1U << TIM_CR2_TI1S_Pos) /*!< 0x00000080 */ #define TIM_CR2_TI1S TIM_CR2_TI1S_Msk /*!<TI1 Selection */ #define TIM_CR2_OIS1_Pos (8U) #define TIM_CR2_OIS1_Msk (0x1U << TIM_CR2_OIS1_Pos) /*!< 0x00000100 */ #define TIM_CR2_OIS1 TIM_CR2_OIS1_Msk /*!<Output Idle state 1 (OC1 output) */ #define TIM_CR2_OIS1N_Pos (9U) #define TIM_CR2_OIS1N_Msk (0x1U << TIM_CR2_OIS1N_Pos) /*!< 0x00000200 */ #define TIM_CR2_OIS1N TIM_CR2_OIS1N_Msk /*!<Output Idle state 1 (OC1N output) */ #define TIM_CR2_OIS2_Pos (10U) #define TIM_CR2_OIS2_Msk (0x1U << TIM_CR2_OIS2_Pos) /*!< 0x00000400 */ #define TIM_CR2_OIS2 TIM_CR2_OIS2_Msk /*!<Output Idle state 2 (OC2 output) */ #define TIM_CR2_OIS2N_Pos (11U) #define TIM_CR2_OIS2N_Msk (0x1U << TIM_CR2_OIS2N_Pos) /*!< 0x00000800 */ #define TIM_CR2_OIS2N TIM_CR2_OIS2N_Msk /*!<Output Idle state 2 (OC2N output) */ #define TIM_CR2_OIS3_Pos (12U) #define TIM_CR2_OIS3_Msk (0x1U << TIM_CR2_OIS3_Pos) /*!< 0x00001000 */ #define TIM_CR2_OIS3 TIM_CR2_OIS3_Msk /*!<Output Idle state 3 (OC3 output) */ #define TIM_CR2_OIS3N_Pos (13U) #define TIM_CR2_OIS3N_Msk (0x1U << TIM_CR2_OIS3N_Pos) /*!< 0x00002000 */ #define TIM_CR2_OIS3N TIM_CR2_OIS3N_Msk /*!<Output Idle state 3 (OC3N output) */ #define TIM_CR2_OIS4_Pos (14U) #define TIM_CR2_OIS4_Msk (0x1U << TIM_CR2_OIS4_Pos) /*!< 0x00004000 */ #define TIM_CR2_OIS4 TIM_CR2_OIS4_Msk /*!<Output Idle state 4 (OC4 output) */ /******************* Bit definition for TIM_SMCR register *******************/ #define TIM_SMCR_SMS_Pos (0U) #define TIM_SMCR_SMS_Msk (0x7U << TIM_SMCR_SMS_Pos) /*!< 0x00000007 */ #define TIM_SMCR_SMS TIM_SMCR_SMS_Msk /*!<SMS[2:0] bits (Slave mode selection) */ #define TIM_SMCR_SMS_0 (0x1U << TIM_SMCR_SMS_Pos) /*!< 0x0001 */ #define TIM_SMCR_SMS_1 (0x2U << TIM_SMCR_SMS_Pos) /*!< 0x0002 */ #define TIM_SMCR_SMS_2 (0x4U << TIM_SMCR_SMS_Pos) /*!< 0x0004 */ #define TIM_SMCR_TS_Pos (4U) #define TIM_SMCR_TS_Msk (0x7U << TIM_SMCR_TS_Pos) /*!< 0x00000070 */ #define TIM_SMCR_TS TIM_SMCR_TS_Msk /*!<TS[2:0] bits (Trigger selection) */ #define TIM_SMCR_TS_0 (0x1U << TIM_SMCR_TS_Pos) /*!< 0x0010 */ #define TIM_SMCR_TS_1 (0x2U << TIM_SMCR_TS_Pos) /*!< 0x0020 */ #define TIM_SMCR_TS_2 (0x4U << TIM_SMCR_TS_Pos) /*!< 0x0040 */ #define TIM_SMCR_MSM_Pos (7U) #define TIM_SMCR_MSM_Msk (0x1U << TIM_SMCR_MSM_Pos) /*!< 0x00000080 */ #define TIM_SMCR_MSM TIM_SMCR_MSM_Msk /*!<Master/slave mode */ #define TIM_SMCR_ETF_Pos (8U) #define TIM_SMCR_ETF_Msk (0xFU << TIM_SMCR_ETF_Pos) /*!< 0x00000F00 */ #define TIM_SMCR_ETF TIM_SMCR_ETF_Msk /*!<ETF[3:0] bits (External trigger filter) */ #define TIM_SMCR_ETF_0 (0x1U << TIM_SMCR_ETF_Pos) /*!< 0x0100 */ #define TIM_SMCR_ETF_1 (0x2U << TIM_SMCR_ETF_Pos) /*!< 0x0200 */ #define TIM_SMCR_ETF_2 (0x4U << TIM_SMCR_ETF_Pos) /*!< 0x0400 */ #define TIM_SMCR_ETF_3 (0x8U << TIM_SMCR_ETF_Pos) /*!< 0x0800 */ #define TIM_SMCR_ETPS_Pos (12U) #define TIM_SMCR_ETPS_Msk (0x3U << TIM_SMCR_ETPS_Pos) /*!< 0x00003000 */ #define TIM_SMCR_ETPS TIM_SMCR_ETPS_Msk /*!<ETPS[1:0] bits (External trigger prescaler) */ #define TIM_SMCR_ETPS_0 (0x1U << TIM_SMCR_ETPS_Pos) /*!< 0x1000 */ #define TIM_SMCR_ETPS_1 (0x2U << TIM_SMCR_ETPS_Pos) /*!< 0x2000 */ #define TIM_SMCR_ECE_Pos (14U) #define TIM_SMCR_ECE_Msk (0x1U << TIM_SMCR_ECE_Pos) /*!< 0x00004000 */ #define TIM_SMCR_ECE TIM_SMCR_ECE_Msk /*!<External clock enable */ #define TIM_SMCR_ETP_Pos (15U) #define TIM_SMCR_ETP_Msk (0x1U << TIM_SMCR_ETP_Pos) /*!< 0x00008000 */ #define TIM_SMCR_ETP TIM_SMCR_ETP_Msk /*!<External trigger polarity */ /******************* Bit definition for TIM_DIER register *******************/ #define TIM_DIER_UIE_Pos (0U) #define TIM_DIER_UIE_Msk (0x1U << TIM_DIER_UIE_Pos) /*!< 0x00000001 */ #define TIM_DIER_UIE TIM_DIER_UIE_Msk /*!<Update interrupt enable */ #define TIM_DIER_CC1IE_Pos (1U) #define TIM_DIER_CC1IE_Msk (0x1U << TIM_DIER_CC1IE_Pos) /*!< 0x00000002 */ #define TIM_DIER_CC1IE TIM_DIER_CC1IE_Msk /*!<Capture/Compare 1 interrupt enable */ #define TIM_DIER_CC2IE_Pos (2U) #define TIM_DIER_CC2IE_Msk (0x1U << TIM_DIER_CC2IE_Pos) /*!< 0x00000004 */ #define TIM_DIER_CC2IE TIM_DIER_CC2IE_Msk /*!<Capture/Compare 2 interrupt enable */ #define TIM_DIER_CC3IE_Pos (3U) #define TIM_DIER_CC3IE_Msk (0x1U << TIM_DIER_CC3IE_Pos) /*!< 0x00000008 */ #define TIM_DIER_CC3IE TIM_DIER_CC3IE_Msk /*!<Capture/Compare 3 interrupt enable */ #define TIM_DIER_CC4IE_Pos (4U) #define TIM_DIER_CC4IE_Msk (0x1U << TIM_DIER_CC4IE_Pos) /*!< 0x00000010 */ #define TIM_DIER_CC4IE TIM_DIER_CC4IE_Msk /*!<Capture/Compare 4 interrupt enable */ #define TIM_DIER_COMIE_Pos (5U) #define TIM_DIER_COMIE_Msk (0x1U << TIM_DIER_COMIE_Pos) /*!< 0x00000020 */ #define TIM_DIER_COMIE TIM_DIER_COMIE_Msk /*!<COM interrupt enable */ #define TIM_DIER_TIE_Pos (6U) #define TIM_DIER_TIE_Msk (0x1U << TIM_DIER_TIE_Pos) /*!< 0x00000040 */ #define TIM_DIER_TIE TIM_DIER_TIE_Msk /*!<Trigger interrupt enable */ #define TIM_DIER_BIE_Pos (7U) #define TIM_DIER_BIE_Msk (0x1U << TIM_DIER_BIE_Pos) /*!< 0x00000080 */ #define TIM_DIER_BIE TIM_DIER_BIE_Msk /*!<Break interrupt enable */ #define TIM_DIER_UDE_Pos (8U) #define TIM_DIER_UDE_Msk (0x1U << TIM_DIER_UDE_Pos) /*!< 0x00000100 */ #define TIM_DIER_UDE TIM_DIER_UDE_Msk /*!<Update DMA request enable */ #define TIM_DIER_CC1DE_Pos (9U) #define TIM_DIER_CC1DE_Msk (0x1U << TIM_DIER_CC1DE_Pos) /*!< 0x00000200 */ #define TIM_DIER_CC1DE TIM_DIER_CC1DE_Msk /*!<Capture/Compare 1 DMA request enable */ #define TIM_DIER_CC2DE_Pos (10U) #define TIM_DIER_CC2DE_Msk (0x1U << TIM_DIER_CC2DE_Pos) /*!< 0x00000400 */ #define TIM_DIER_CC2DE TIM_DIER_CC2DE_Msk /*!<Capture/Compare 2 DMA request enable */ #define TIM_DIER_CC3DE_Pos (11U) #define TIM_DIER_CC3DE_Msk (0x1U << TIM_DIER_CC3DE_Pos) /*!< 0x00000800 */ #define TIM_DIER_CC3DE TIM_DIER_CC3DE_Msk /*!<Capture/Compare 3 DMA request enable */ #define TIM_DIER_CC4DE_Pos (12U) #define TIM_DIER_CC4DE_Msk (0x1U << TIM_DIER_CC4DE_Pos) /*!< 0x00001000 */ #define TIM_DIER_CC4DE TIM_DIER_CC4DE_Msk /*!<Capture/Compare 4 DMA request enable */ #define TIM_DIER_COMDE_Pos (13U) #define TIM_DIER_COMDE_Msk (0x1U << TIM_DIER_COMDE_Pos) /*!< 0x00002000 */ #define TIM_DIER_COMDE TIM_DIER_COMDE_Msk /*!<COM DMA request enable */ #define TIM_DIER_TDE_Pos (14U) #define TIM_DIER_TDE_Msk (0x1U << TIM_DIER_TDE_Pos) /*!< 0x00004000 */ #define TIM_DIER_TDE TIM_DIER_TDE_Msk /*!<Trigger DMA request enable */ /******************** Bit definition for TIM_SR register ********************/ #define TIM_SR_UIF_Pos (0U) #define TIM_SR_UIF_Msk (0x1U << TIM_SR_UIF_Pos) /*!< 0x00000001 */ #define TIM_SR_UIF TIM_SR_UIF_Msk /*!<Update interrupt Flag */ #define TIM_SR_CC1IF_Pos (1U) #define TIM_SR_CC1IF_Msk (0x1U << TIM_SR_CC1IF_Pos) /*!< 0x00000002 */ #define TIM_SR_CC1IF TIM_SR_CC1IF_Msk /*!<Capture/Compare 1 interrupt Flag */ #define TIM_SR_CC2IF_Pos (2U) #define TIM_SR_CC2IF_Msk (0x1U << TIM_SR_CC2IF_Pos) /*!< 0x00000004 */ #define TIM_SR_CC2IF TIM_SR_CC2IF_Msk /*!<Capture/Compare 2 interrupt Flag */ #define TIM_SR_CC3IF_Pos (3U) #define TIM_SR_CC3IF_Msk (0x1U << TIM_SR_CC3IF_Pos) /*!< 0x00000008 */ #define TIM_SR_CC3IF TIM_SR_CC3IF_Msk /*!<Capture/Compare 3 interrupt Flag */ #define TIM_SR_CC4IF_Pos (4U) #define TIM_SR_CC4IF_Msk (0x1U << TIM_SR_CC4IF_Pos) /*!< 0x00000010 */ #define TIM_SR_CC4IF TIM_SR_CC4IF_Msk /*!<Capture/Compare 4 interrupt Flag */ #define TIM_SR_COMIF_Pos (5U) #define TIM_SR_COMIF_Msk (0x1U << TIM_SR_COMIF_Pos) /*!< 0x00000020 */ #define TIM_SR_COMIF TIM_SR_COMIF_Msk /*!<COM interrupt Flag */ #define TIM_SR_TIF_Pos (6U) #define TIM_SR_TIF_Msk (0x1U << TIM_SR_TIF_Pos) /*!< 0x00000040 */ #define TIM_SR_TIF TIM_SR_TIF_Msk /*!<Trigger interrupt Flag */ #define TIM_SR_BIF_Pos (7U) #define TIM_SR_BIF_Msk (0x1U << TIM_SR_BIF_Pos) /*!< 0x00000080 */ #define TIM_SR_BIF TIM_SR_BIF_Msk /*!<Break interrupt Flag */ #define TIM_SR_CC1OF_Pos (9U) #define TIM_SR_CC1OF_Msk (0x1U << TIM_SR_CC1OF_Pos) /*!< 0x00000200 */ #define TIM_SR_CC1OF TIM_SR_CC1OF_Msk /*!<Capture/Compare 1 Overcapture Flag */ #define TIM_SR_CC2OF_Pos (10U) #define TIM_SR_CC2OF_Msk (0x1U << TIM_SR_CC2OF_Pos) /*!< 0x00000400 */ #define TIM_SR_CC2OF TIM_SR_CC2OF_Msk /*!<Capture/Compare 2 Overcapture Flag */ #define TIM_SR_CC3OF_Pos (11U) #define TIM_SR_CC3OF_Msk (0x1U << TIM_SR_CC3OF_Pos) /*!< 0x00000800 */ #define TIM_SR_CC3OF TIM_SR_CC3OF_Msk /*!<Capture/Compare 3 Overcapture Flag */ #define TIM_SR_CC4OF_Pos (12U) #define TIM_SR_CC4OF_Msk (0x1U << TIM_SR_CC4OF_Pos) /*!< 0x00001000 */ #define TIM_SR_CC4OF TIM_SR_CC4OF_Msk /*!<Capture/Compare 4 Overcapture Flag */ /******************* Bit definition for TIM_EGR register ********************/ #define TIM_EGR_UG_Pos (0U) #define TIM_EGR_UG_Msk (0x1U << TIM_EGR_UG_Pos) /*!< 0x00000001 */ #define TIM_EGR_UG TIM_EGR_UG_Msk /*!<Update Generation */ #define TIM_EGR_CC1G_Pos (1U) #define TIM_EGR_CC1G_Msk (0x1U << TIM_EGR_CC1G_Pos) /*!< 0x00000002 */ #define TIM_EGR_CC1G TIM_EGR_CC1G_Msk /*!<Capture/Compare 1 Generation */ #define TIM_EGR_CC2G_Pos (2U) #define TIM_EGR_CC2G_Msk (0x1U << TIM_EGR_CC2G_Pos) /*!< 0x00000004 */ #define TIM_EGR_CC2G TIM_EGR_CC2G_Msk /*!<Capture/Compare 2 Generation */ #define TIM_EGR_CC3G_Pos (3U) #define TIM_EGR_CC3G_Msk (0x1U << TIM_EGR_CC3G_Pos) /*!< 0x00000008 */ #define TIM_EGR_CC3G TIM_EGR_CC3G_Msk /*!<Capture/Compare 3 Generation */ #define TIM_EGR_CC4G_Pos (4U) #define TIM_EGR_CC4G_Msk (0x1U << TIM_EGR_CC4G_Pos) /*!< 0x00000010 */ #define TIM_EGR_CC4G TIM_EGR_CC4G_Msk /*!<Capture/Compare 4 Generation */ #define TIM_EGR_COMG_Pos (5U) #define TIM_EGR_COMG_Msk (0x1U << TIM_EGR_COMG_Pos) /*!< 0x00000020 */ #define TIM_EGR_COMG TIM_EGR_COMG_Msk /*!<Capture/Compare Control Update Generation */ #define TIM_EGR_TG_Pos (6U) #define TIM_EGR_TG_Msk (0x1U << TIM_EGR_TG_Pos) /*!< 0x00000040 */ #define TIM_EGR_TG TIM_EGR_TG_Msk /*!<Trigger Generation */ #define TIM_EGR_BG_Pos (7U) #define TIM_EGR_BG_Msk (0x1U << TIM_EGR_BG_Pos) /*!< 0x00000080 */ #define TIM_EGR_BG TIM_EGR_BG_Msk /*!<Break Generation */ /****************** Bit definition for TIM_CCMR1 register *******************/ #define TIM_CCMR1_CC1S_Pos (0U) #define TIM_CCMR1_CC1S_Msk (0x3U << TIM_CCMR1_CC1S_Pos) /*!< 0x00000003 */ #define TIM_CCMR1_CC1S TIM_CCMR1_CC1S_Msk /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */ #define TIM_CCMR1_CC1S_0 (0x1U << TIM_CCMR1_CC1S_Pos) /*!< 0x0001 */ #define TIM_CCMR1_CC1S_1 (0x2U << TIM_CCMR1_CC1S_Pos) /*!< 0x0002 */ #define TIM_CCMR1_OC1FE_Pos (2U) #define TIM_CCMR1_OC1FE_Msk (0x1U << TIM_CCMR1_OC1FE_Pos) /*!< 0x00000004 */ #define TIM_CCMR1_OC1FE TIM_CCMR1_OC1FE_Msk /*!<Output Compare 1 Fast enable */ #define TIM_CCMR1_OC1PE_Pos (3U) #define TIM_CCMR1_OC1PE_Msk (0x1U << TIM_CCMR1_OC1PE_Pos) /*!< 0x00000008 */ #define TIM_CCMR1_OC1PE TIM_CCMR1_OC1PE_Msk /*!<Output Compare 1 Preload enable */ #define TIM_CCMR1_OC1M_Pos (4U) #define TIM_CCMR1_OC1M_Msk (0x7U << TIM_CCMR1_OC1M_Pos) /*!< 0x00000070 */ #define TIM_CCMR1_OC1M TIM_CCMR1_OC1M_Msk /*!<OC1M[2:0] bits (Output Compare 1 Mode) */ #define TIM_CCMR1_OC1M_0 (0x1U << TIM_CCMR1_OC1M_Pos) /*!< 0x0010 */ #define TIM_CCMR1_OC1M_1 (0x2U << TIM_CCMR1_OC1M_Pos) /*!< 0x0020 */ #define TIM_CCMR1_OC1M_2 (0x4U << TIM_CCMR1_OC1M_Pos) /*!< 0x0040 */ #define TIM_CCMR1_OC1CE_Pos (7U) #define TIM_CCMR1_OC1CE_Msk (0x1U << TIM_CCMR1_OC1CE_Pos) /*!< 0x00000080 */ #define TIM_CCMR1_OC1CE TIM_CCMR1_OC1CE_Msk /*!<Output Compare 1Clear Enable */ #define TIM_CCMR1_CC2S_Pos (8U) #define TIM_CCMR1_CC2S_Msk (0x3U << TIM_CCMR1_CC2S_Pos) /*!< 0x00000300 */ #define TIM_CCMR1_CC2S TIM_CCMR1_CC2S_Msk /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */ #define TIM_CCMR1_CC2S_0 (0x1U << TIM_CCMR1_CC2S_Pos) /*!< 0x0100 */ #define TIM_CCMR1_CC2S_1 (0x2U << TIM_CCMR1_CC2S_Pos) /*!< 0x0200 */ #define TIM_CCMR1_OC2FE_Pos (10U) #define TIM_CCMR1_OC2FE_Msk (0x1U << TIM_CCMR1_OC2FE_Pos) /*!< 0x00000400 */ #define TIM_CCMR1_OC2FE TIM_CCMR1_OC2FE_Msk /*!<Output Compare 2 Fast enable */ #define TIM_CCMR1_OC2PE_Pos (11U) #define TIM_CCMR1_OC2PE_Msk (0x1U << TIM_CCMR1_OC2PE_Pos) /*!< 0x00000800 */ #define TIM_CCMR1_OC2PE TIM_CCMR1_OC2PE_Msk /*!<Output Compare 2 Preload enable */ #define TIM_CCMR1_OC2M_Pos (12U) #define TIM_CCMR1_OC2M_Msk (0x7U << TIM_CCMR1_OC2M_Pos) /*!< 0x00007000 */ #define TIM_CCMR1_OC2M TIM_CCMR1_OC2M_Msk /*!<OC2M[2:0] bits (Output Compare 2 Mode) */ #define TIM_CCMR1_OC2M_0 (0x1U << TIM_CCMR1_OC2M_Pos) /*!< 0x1000 */ #define TIM_CCMR1_OC2M_1 (0x2U << TIM_CCMR1_OC2M_Pos) /*!< 0x2000 */ #define TIM_CCMR1_OC2M_2 (0x4U << TIM_CCMR1_OC2M_Pos) /*!< 0x4000 */ #define TIM_CCMR1_OC2CE_Pos (15U) #define TIM_CCMR1_OC2CE_Msk (0x1U << TIM_CCMR1_OC2CE_Pos) /*!< 0x00008000 */ #define TIM_CCMR1_OC2CE TIM_CCMR1_OC2CE_Msk /*!<Output Compare 2 Clear Enable */ /*----------------------------------------------------------------------------*/ #define TIM_CCMR1_IC1PSC_Pos (2U) #define TIM_CCMR1_IC1PSC_Msk (0x3U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x0000000C */ #define TIM_CCMR1_IC1PSC TIM_CCMR1_IC1PSC_Msk /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */ #define TIM_CCMR1_IC1PSC_0 (0x1U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x0004 */ #define TIM_CCMR1_IC1PSC_1 (0x2U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x0008 */ #define TIM_CCMR1_IC1F_Pos (4U) #define TIM_CCMR1_IC1F_Msk (0xFU << TIM_CCMR1_IC1F_Pos) /*!< 0x000000F0 */ #define TIM_CCMR1_IC1F TIM_CCMR1_IC1F_Msk /*!<IC1F[3:0] bits (Input Capture 1 Filter) */ #define TIM_CCMR1_IC1F_0 (0x1U << TIM_CCMR1_IC1F_Pos) /*!< 0x0010 */ #define TIM_CCMR1_IC1F_1 (0x2U << TIM_CCMR1_IC1F_Pos) /*!< 0x0020 */ #define TIM_CCMR1_IC1F_2 (0x4U << TIM_CCMR1_IC1F_Pos) /*!< 0x0040 */ #define TIM_CCMR1_IC1F_3 (0x8U << TIM_CCMR1_IC1F_Pos) /*!< 0x0080 */ #define TIM_CCMR1_IC2PSC_Pos (10U) #define TIM_CCMR1_IC2PSC_Msk (0x3U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000C00 */ #define TIM_CCMR1_IC2PSC TIM_CCMR1_IC2PSC_Msk /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */ #define TIM_CCMR1_IC2PSC_0 (0x1U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x0400 */ #define TIM_CCMR1_IC2PSC_1 (0x2U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x0800 */ #define TIM_CCMR1_IC2F_Pos (12U) #define TIM_CCMR1_IC2F_Msk (0xFU << TIM_CCMR1_IC2F_Pos) /*!< 0x0000F000 */ #define TIM_CCMR1_IC2F TIM_CCMR1_IC2F_Msk /*!<IC2F[3:0] bits (Input Capture 2 Filter) */ #define TIM_CCMR1_IC2F_0 (0x1U << TIM_CCMR1_IC2F_Pos) /*!< 0x1000 */ #define TIM_CCMR1_IC2F_1 (0x2U << TIM_CCMR1_IC2F_Pos) /*!< 0x2000 */ #define TIM_CCMR1_IC2F_2 (0x4U << TIM_CCMR1_IC2F_Pos) /*!< 0x4000 */ #define TIM_CCMR1_IC2F_3 (0x8U << TIM_CCMR1_IC2F_Pos) /*!< 0x8000 */ /****************** Bit definition for TIM_CCMR2 register *******************/ #define TIM_CCMR2_CC3S_Pos (0U) #define TIM_CCMR2_CC3S_Msk (0x3U << TIM_CCMR2_CC3S_Pos) /*!< 0x00000003 */ #define TIM_CCMR2_CC3S TIM_CCMR2_CC3S_Msk /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */ #define TIM_CCMR2_CC3S_0 (0x1U << TIM_CCMR2_CC3S_Pos) /*!< 0x0001 */ #define TIM_CCMR2_CC3S_1 (0x2U << TIM_CCMR2_CC3S_Pos) /*!< 0x0002 */ #define TIM_CCMR2_OC3FE_Pos (2U) #define TIM_CCMR2_OC3FE_Msk (0x1U << TIM_CCMR2_OC3FE_Pos) /*!< 0x00000004 */ #define TIM_CCMR2_OC3FE TIM_CCMR2_OC3FE_Msk /*!<Output Compare 3 Fast enable */ #define TIM_CCMR2_OC3PE_Pos (3U) #define TIM_CCMR2_OC3PE_Msk (0x1U << TIM_CCMR2_OC3PE_Pos) /*!< 0x00000008 */ #define TIM_CCMR2_OC3PE TIM_CCMR2_OC3PE_Msk /*!<Output Compare 3 Preload enable */ #define TIM_CCMR2_OC3M_Pos (4U) #define TIM_CCMR2_OC3M_Msk (0x7U << TIM_CCMR2_OC3M_Pos) /*!< 0x00000070 */ #define TIM_CCMR2_OC3M TIM_CCMR2_OC3M_Msk /*!<OC3M[2:0] bits (Output Compare 3 Mode) */ #define TIM_CCMR2_OC3M_0 (0x1U << TIM_CCMR2_OC3M_Pos) /*!< 0x0010 */ #define TIM_CCMR2_OC3M_1 (0x2U << TIM_CCMR2_OC3M_Pos) /*!< 0x0020 */ #define TIM_CCMR2_OC3M_2 (0x4U << TIM_CCMR2_OC3M_Pos) /*!< 0x0040 */ #define TIM_CCMR2_OC3CE_Pos (7U) #define TIM_CCMR2_OC3CE_Msk (0x1U << TIM_CCMR2_OC3CE_Pos) /*!< 0x00000080 */ #define TIM_CCMR2_OC3CE TIM_CCMR2_OC3CE_Msk /*!<Output Compare 3 Clear Enable */ #define TIM_CCMR2_CC4S_Pos (8U) #define TIM_CCMR2_CC4S_Msk (0x3U << TIM_CCMR2_CC4S_Pos) /*!< 0x00000300 */ #define TIM_CCMR2_CC4S TIM_CCMR2_CC4S_Msk /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */ #define TIM_CCMR2_CC4S_0 (0x1U << TIM_CCMR2_CC4S_Pos) /*!< 0x0100 */ #define TIM_CCMR2_CC4S_1 (0x2U << TIM_CCMR2_CC4S_Pos) /*!< 0x0200 */ #define TIM_CCMR2_OC4FE_Pos (10U) #define TIM_CCMR2_OC4FE_Msk (0x1U << TIM_CCMR2_OC4FE_Pos) /*!< 0x00000400 */ #define TIM_CCMR2_OC4FE TIM_CCMR2_OC4FE_Msk /*!<Output Compare 4 Fast enable */ #define TIM_CCMR2_OC4PE_Pos (11U) #define TIM_CCMR2_OC4PE_Msk (0x1U << TIM_CCMR2_OC4PE_Pos) /*!< 0x00000800 */ #define TIM_CCMR2_OC4PE TIM_CCMR2_OC4PE_Msk /*!<Output Compare 4 Preload enable */ #define TIM_CCMR2_OC4M_Pos (12U) #define TIM_CCMR2_OC4M_Msk (0x7U << TIM_CCMR2_OC4M_Pos) /*!< 0x00007000 */ #define TIM_CCMR2_OC4M TIM_CCMR2_OC4M_Msk /*!<OC4M[2:0] bits (Output Compare 4 Mode) */ #define TIM_CCMR2_OC4M_0 (0x1U << TIM_CCMR2_OC4M_Pos) /*!< 0x1000 */ #define TIM_CCMR2_OC4M_1 (0x2U << TIM_CCMR2_OC4M_Pos) /*!< 0x2000 */ #define TIM_CCMR2_OC4M_2 (0x4U << TIM_CCMR2_OC4M_Pos) /*!< 0x4000 */ #define TIM_CCMR2_OC4CE_Pos (15U) #define TIM_CCMR2_OC4CE_Msk (0x1U << TIM_CCMR2_OC4CE_Pos) /*!< 0x00008000 */ #define TIM_CCMR2_OC4CE TIM_CCMR2_OC4CE_Msk /*!<Output Compare 4 Clear Enable */ /*----------------------------------------------------------------------------*/ #define TIM_CCMR2_IC3PSC_Pos (2U) #define TIM_CCMR2_IC3PSC_Msk (0x3U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x0000000C */ #define TIM_CCMR2_IC3PSC TIM_CCMR2_IC3PSC_Msk /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */ #define TIM_CCMR2_IC3PSC_0 (0x1U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x0004 */ #define TIM_CCMR2_IC3PSC_1 (0x2U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x0008 */ #define TIM_CCMR2_IC3F_Pos (4U) #define TIM_CCMR2_IC3F_Msk (0xFU << TIM_CCMR2_IC3F_Pos) /*!< 0x000000F0 */ #define TIM_CCMR2_IC3F TIM_CCMR2_IC3F_Msk /*!<IC3F[3:0] bits (Input Capture 3 Filter) */ #define TIM_CCMR2_IC3F_0 (0x1U << TIM_CCMR2_IC3F_Pos) /*!< 0x0010 */ #define TIM_CCMR2_IC3F_1 (0x2U << TIM_CCMR2_IC3F_Pos) /*!< 0x0020 */ #define TIM_CCMR2_IC3F_2 (0x4U << TIM_CCMR2_IC3F_Pos) /*!< 0x0040 */ #define TIM_CCMR2_IC3F_3 (0x8U << TIM_CCMR2_IC3F_Pos) /*!< 0x0080 */ #define TIM_CCMR2_IC4PSC_Pos (10U) #define TIM_CCMR2_IC4PSC_Msk (0x3U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000C00 */ #define TIM_CCMR2_IC4PSC TIM_CCMR2_IC4PSC_Msk /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */ #define TIM_CCMR2_IC4PSC_0 (0x1U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x0400 */ #define TIM_CCMR2_IC4PSC_1 (0x2U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x0800 */ #define TIM_CCMR2_IC4F_Pos (12U) #define TIM_CCMR2_IC4F_Msk (0xFU << TIM_CCMR2_IC4F_Pos) /*!< 0x0000F000 */ #define TIM_CCMR2_IC4F TIM_CCMR2_IC4F_Msk /*!<IC4F[3:0] bits (Input Capture 4 Filter) */ #define TIM_CCMR2_IC4F_0 (0x1U << TIM_CCMR2_IC4F_Pos) /*!< 0x1000 */ #define TIM_CCMR2_IC4F_1 (0x2U << TIM_CCMR2_IC4F_Pos) /*!< 0x2000 */ #define TIM_CCMR2_IC4F_2 (0x4U << TIM_CCMR2_IC4F_Pos) /*!< 0x4000 */ #define TIM_CCMR2_IC4F_3 (0x8U << TIM_CCMR2_IC4F_Pos) /*!< 0x8000 */ /******************* Bit definition for TIM_CCER register *******************/ #define TIM_CCER_CC1E_Pos (0U) #define TIM_CCER_CC1E_Msk (0x1U << TIM_CCER_CC1E_Pos) /*!< 0x00000001 */ #define TIM_CCER_CC1E TIM_CCER_CC1E_Msk /*!<Capture/Compare 1 output enable */ #define TIM_CCER_CC1P_Pos (1U) #define TIM_CCER_CC1P_Msk (0x1U << TIM_CCER_CC1P_Pos) /*!< 0x00000002 */ #define TIM_CCER_CC1P TIM_CCER_CC1P_Msk /*!<Capture/Compare 1 output Polarity */ #define TIM_CCER_CC1NE_Pos (2U) #define TIM_CCER_CC1NE_Msk (0x1U << TIM_CCER_CC1NE_Pos) /*!< 0x00000004 */ #define TIM_CCER_CC1NE TIM_CCER_CC1NE_Msk /*!<Capture/Compare 1 Complementary output enable */ #define TIM_CCER_CC1NP_Pos (3U) #define TIM_CCER_CC1NP_Msk (0x1U << TIM_CCER_CC1NP_Pos) /*!< 0x00000008 */ #define TIM_CCER_CC1NP TIM_CCER_CC1NP_Msk /*!<Capture/Compare 1 Complementary output Polarity */ #define TIM_CCER_CC2E_Pos (4U) #define TIM_CCER_CC2E_Msk (0x1U << TIM_CCER_CC2E_Pos) /*!< 0x00000010 */ #define TIM_CCER_CC2E TIM_CCER_CC2E_Msk /*!<Capture/Compare 2 output enable */ #define TIM_CCER_CC2P_Pos (5U) #define TIM_CCER_CC2P_Msk (0x1U << TIM_CCER_CC2P_Pos) /*!< 0x00000020 */ #define TIM_CCER_CC2P TIM_CCER_CC2P_Msk /*!<Capture/Compare 2 output Polarity */ #define TIM_CCER_CC2NE_Pos (6U) #define TIM_CCER_CC2NE_Msk (0x1U << TIM_CCER_CC2NE_Pos) /*!< 0x00000040 */ #define TIM_CCER_CC2NE TIM_CCER_CC2NE_Msk /*!<Capture/Compare 2 Complementary output enable */ #define TIM_CCER_CC2NP_Pos (7U) #define TIM_CCER_CC2NP_Msk (0x1U << TIM_CCER_CC2NP_Pos) /*!< 0x00000080 */ #define TIM_CCER_CC2NP TIM_CCER_CC2NP_Msk /*!<Capture/Compare 2 Complementary output Polarity */ #define TIM_CCER_CC3E_Pos (8U) #define TIM_CCER_CC3E_Msk (0x1U << TIM_CCER_CC3E_Pos) /*!< 0x00000100 */ #define TIM_CCER_CC3E TIM_CCER_CC3E_Msk /*!<Capture/Compare 3 output enable */ #define TIM_CCER_CC3P_Pos (9U) #define TIM_CCER_CC3P_Msk (0x1U << TIM_CCER_CC3P_Pos) /*!< 0x00000200 */ #define TIM_CCER_CC3P TIM_CCER_CC3P_Msk /*!<Capture/Compare 3 output Polarity */ #define TIM_CCER_CC3NE_Pos (10U) #define TIM_CCER_CC3NE_Msk (0x1U << TIM_CCER_CC3NE_Pos) /*!< 0x00000400 */ #define TIM_CCER_CC3NE TIM_CCER_CC3NE_Msk /*!<Capture/Compare 3 Complementary output enable */ #define TIM_CCER_CC3NP_Pos (11U) #define TIM_CCER_CC3NP_Msk (0x1U << TIM_CCER_CC3NP_Pos) /*!< 0x00000800 */ #define TIM_CCER_CC3NP TIM_CCER_CC3NP_Msk /*!<Capture/Compare 3 Complementary output Polarity */ #define TIM_CCER_CC4E_Pos (12U) #define TIM_CCER_CC4E_Msk (0x1U << TIM_CCER_CC4E_Pos) /*!< 0x00001000 */ #define TIM_CCER_CC4E TIM_CCER_CC4E_Msk /*!<Capture/Compare 4 output enable */ #define TIM_CCER_CC4P_Pos (13U) #define TIM_CCER_CC4P_Msk (0x1U << TIM_CCER_CC4P_Pos) /*!< 0x00002000 */ #define TIM_CCER_CC4P TIM_CCER_CC4P_Msk /*!<Capture/Compare 4 output Polarity */ #define TIM_CCER_CC4NP_Pos (15U) #define TIM_CCER_CC4NP_Msk (0x1U << TIM_CCER_CC4NP_Pos) /*!< 0x00008000 */ #define TIM_CCER_CC4NP TIM_CCER_CC4NP_Msk /*!<Capture/Compare 4 Complementary output Polarity */ /******************* Bit definition for TIM_CNT register ********************/ #define TIM_CNT_CNT_Pos (0U) #define TIM_CNT_CNT_Msk (0xFFFFFFFFU << TIM_CNT_CNT_Pos) /*!< 0xFFFFFFFF */ #define TIM_CNT_CNT TIM_CNT_CNT_Msk /*!<Counter Value */ /******************* Bit definition for TIM_PSC register ********************/ #define TIM_PSC_PSC_Pos (0U) #define TIM_PSC_PSC_Msk (0xFFFFU << TIM_PSC_PSC_Pos) /*!< 0x0000FFFF */ #define TIM_PSC_PSC TIM_PSC_PSC_Msk /*!<Prescaler Value */ /******************* Bit definition for TIM_ARR register ********************/ #define TIM_ARR_ARR_Pos (0U) #define TIM_ARR_ARR_Msk (0xFFFFFFFFU << TIM_ARR_ARR_Pos) /*!< 0xFFFFFFFF */ #define TIM_ARR_ARR TIM_ARR_ARR_Msk /*!<actual auto-reload Value */ /******************* Bit definition for TIM_RCR register ********************/ #define TIM_RCR_REP_Pos (0U) #define TIM_RCR_REP_Msk (0xFFU << TIM_RCR_REP_Pos) /*!< 0x000000FF */ #define TIM_RCR_REP TIM_RCR_REP_Msk /*!<Repetition Counter Value */ /******************* Bit definition for TIM_CCR1 register *******************/ #define TIM_CCR1_CCR1_Pos (0U) #define TIM_CCR1_CCR1_Msk (0xFFFFU << TIM_CCR1_CCR1_Pos) /*!< 0x0000FFFF */ #define TIM_CCR1_CCR1 TIM_CCR1_CCR1_Msk /*!<Capture/Compare 1 Value */ /******************* Bit definition for TIM_CCR2 register *******************/ #define TIM_CCR2_CCR2_Pos (0U) #define TIM_CCR2_CCR2_Msk (0xFFFFU << TIM_CCR2_CCR2_Pos) /*!< 0x0000FFFF */ #define TIM_CCR2_CCR2 TIM_CCR2_CCR2_Msk /*!<Capture/Compare 2 Value */ /******************* Bit definition for TIM_CCR3 register *******************/ #define TIM_CCR3_CCR3_Pos (0U) #define TIM_CCR3_CCR3_Msk (0xFFFFU << TIM_CCR3_CCR3_Pos) /*!< 0x0000FFFF */ #define TIM_CCR3_CCR3 TIM_CCR3_CCR3_Msk /*!<Capture/Compare 3 Value */ /******************* Bit definition for TIM_CCR4 register *******************/ #define TIM_CCR4_CCR4_Pos (0U) #define TIM_CCR4_CCR4_Msk (0xFFFFU << TIM_CCR4_CCR4_Pos) /*!< 0x0000FFFF */ #define TIM_CCR4_CCR4 TIM_CCR4_CCR4_Msk /*!<Capture/Compare 4 Value */ /******************* Bit definition for TIM_BDTR register *******************/ #define TIM_BDTR_DTG_Pos (0U) #define TIM_BDTR_DTG_Msk (0xFFU << TIM_BDTR_DTG_Pos) /*!< 0x000000FF */ #define TIM_BDTR_DTG TIM_BDTR_DTG_Msk /*!<DTG[0:7] bits (Dead-Time Generator set-up) */ #define TIM_BDTR_DTG_0 (0x01U << TIM_BDTR_DTG_Pos) /*!< 0x0001 */ #define TIM_BDTR_DTG_1 (0x02U << TIM_BDTR_DTG_Pos) /*!< 0x0002 */ #define TIM_BDTR_DTG_2 (0x04U << TIM_BDTR_DTG_Pos) /*!< 0x0004 */ #define TIM_BDTR_DTG_3 (0x08U << TIM_BDTR_DTG_Pos) /*!< 0x0008 */ #define TIM_BDTR_DTG_4 (0x10U << TIM_BDTR_DTG_Pos) /*!< 0x0010 */ #define TIM_BDTR_DTG_5 (0x20U << TIM_BDTR_DTG_Pos) /*!< 0x0020 */ #define TIM_BDTR_DTG_6 (0x40U << TIM_BDTR_DTG_Pos) /*!< 0x0040 */ #define TIM_BDTR_DTG_7 (0x80U << TIM_BDTR_DTG_Pos) /*!< 0x0080 */ #define TIM_BDTR_LOCK_Pos (8U) #define TIM_BDTR_LOCK_Msk (0x3U << TIM_BDTR_LOCK_Pos) /*!< 0x00000300 */ #define TIM_BDTR_LOCK TIM_BDTR_LOCK_Msk /*!<LOCK[1:0] bits (Lock Configuration) */ #define TIM_BDTR_LOCK_0 (0x1U << TIM_BDTR_LOCK_Pos) /*!< 0x0100 */ #define TIM_BDTR_LOCK_1 (0x2U << TIM_BDTR_LOCK_Pos) /*!< 0x0200 */ #define TIM_BDTR_OSSI_Pos (10U) #define TIM_BDTR_OSSI_Msk (0x1U << TIM_BDTR_OSSI_Pos) /*!< 0x00000400 */ #define TIM_BDTR_OSSI TIM_BDTR_OSSI_Msk /*!<Off-State Selection for Idle mode */ #define TIM_BDTR_OSSR_Pos (11U) #define TIM_BDTR_OSSR_Msk (0x1U << TIM_BDTR_OSSR_Pos) /*!< 0x00000800 */ #define TIM_BDTR_OSSR TIM_BDTR_OSSR_Msk /*!<Off-State Selection for Run mode */ #define TIM_BDTR_BKE_Pos (12U) #define TIM_BDTR_BKE_Msk (0x1U << TIM_BDTR_BKE_Pos) /*!< 0x00001000 */ #define TIM_BDTR_BKE TIM_BDTR_BKE_Msk /*!<Break enable */ #define TIM_BDTR_BKP_Pos (13U) #define TIM_BDTR_BKP_Msk (0x1U << TIM_BDTR_BKP_Pos) /*!< 0x00002000 */ #define TIM_BDTR_BKP TIM_BDTR_BKP_Msk /*!<Break Polarity */ #define TIM_BDTR_AOE_Pos (14U) #define TIM_BDTR_AOE_Msk (0x1U << TIM_BDTR_AOE_Pos) /*!< 0x00004000 */ #define TIM_BDTR_AOE TIM_BDTR_AOE_Msk /*!<Automatic Output enable */ #define TIM_BDTR_MOE_Pos (15U) #define TIM_BDTR_MOE_Msk (0x1U << TIM_BDTR_MOE_Pos) /*!< 0x00008000 */ #define TIM_BDTR_MOE TIM_BDTR_MOE_Msk /*!<Main Output enable */ /******************* Bit definition for TIM_DCR register ********************/ #define TIM_DCR_DBA_Pos (0U) #define TIM_DCR_DBA_Msk (0x1FU << TIM_DCR_DBA_Pos) /*!< 0x0000001F */ #define TIM_DCR_DBA TIM_DCR_DBA_Msk /*!<DBA[4:0] bits (DMA Base Address) */ #define TIM_DCR_DBA_0 (0x01U << TIM_DCR_DBA_Pos) /*!< 0x0001 */ #define TIM_DCR_DBA_1 (0x02U << TIM_DCR_DBA_Pos) /*!< 0x0002 */ #define TIM_DCR_DBA_2 (0x04U << TIM_DCR_DBA_Pos) /*!< 0x0004 */ #define TIM_DCR_DBA_3 (0x08U << TIM_DCR_DBA_Pos) /*!< 0x0008 */ #define TIM_DCR_DBA_4 (0x10U << TIM_DCR_DBA_Pos) /*!< 0x0010 */ #define TIM_DCR_DBL_Pos (8U) #define TIM_DCR_DBL_Msk (0x1FU << TIM_DCR_DBL_Pos) /*!< 0x00001F00 */ #define TIM_DCR_DBL TIM_DCR_DBL_Msk /*!<DBL[4:0] bits (DMA Burst Length) */ #define TIM_DCR_DBL_0 (0x01U << TIM_DCR_DBL_Pos) /*!< 0x0100 */ #define TIM_DCR_DBL_1 (0x02U << TIM_DCR_DBL_Pos) /*!< 0x0200 */ #define TIM_DCR_DBL_2 (0x04U << TIM_DCR_DBL_Pos) /*!< 0x0400 */ #define TIM_DCR_DBL_3 (0x08U << TIM_DCR_DBL_Pos) /*!< 0x0800 */ #define TIM_DCR_DBL_4 (0x10U << TIM_DCR_DBL_Pos) /*!< 0x1000 */ /******************* Bit definition for TIM_DMAR register *******************/ #define TIM_DMAR_DMAB_Pos (0U) #define TIM_DMAR_DMAB_Msk (0xFFFFU << TIM_DMAR_DMAB_Pos) /*!< 0x0000FFFF */ #define TIM_DMAR_DMAB TIM_DMAR_DMAB_Msk /*!<DMA register for burst accesses */ /******************* Bit definition for TIM_OR register *********************/ #define TIM_OR_TI1_RMP_Pos (0U) #define TIM_OR_TI1_RMP_Msk (0x3U << TIM_OR_TI1_RMP_Pos) /*!< 0x00000003 */ #define TIM_OR_TI1_RMP TIM_OR_TI1_RMP_Msk /*!< TI1_RMP[1:0] bits (TIM11 Input Capture 1 remap) */ #define TIM_OR_TI1_RMP_0 (0x1U << TIM_OR_TI1_RMP_Pos) /*!< 0x00000001 */ #define TIM_OR_TI1_RMP_1 (0x2U << TIM_OR_TI1_RMP_Pos) /*!< 0x00000002 */ #define TIM_OR_TI4_RMP_Pos (6U) #define TIM_OR_TI4_RMP_Msk (0x3U << TIM_OR_TI4_RMP_Pos) /*!< 0x000000C0 */ #define TIM_OR_TI4_RMP TIM_OR_TI4_RMP_Msk /*!<TI4_RMP[1:0] bits (TIM5 Input 4 remap) */ #define TIM_OR_TI4_RMP_0 (0x1U << TIM_OR_TI4_RMP_Pos) /*!< 0x0040 */ #define TIM_OR_TI4_RMP_1 (0x2U << TIM_OR_TI4_RMP_Pos) /*!< 0x0080 */ #define TIM_OR_ITR1_RMP_Pos (10U) #define TIM_OR_ITR1_RMP_Msk (0x3U << TIM_OR_ITR1_RMP_Pos) /*!< 0x00000C00 */ #define TIM_OR_ITR1_RMP TIM_OR_ITR1_RMP_Msk /*!<ITR1_RMP[1:0] bits (TIM2 Internal trigger 1 remap) */ #define TIM_OR_ITR1_RMP_0 (0x1U << TIM_OR_ITR1_RMP_Pos) /*!< 0x0400 */ #define TIM_OR_ITR1_RMP_1 (0x2U << TIM_OR_ITR1_RMP_Pos) /*!< 0x0800 */ /******************************************************************************/ /* */ /* Universal Synchronous Asynchronous Receiver Transmitter */ /* */ /******************************************************************************/ /******************* Bit definition for USART_SR register *******************/ #define USART_SR_PE_Pos (0U) #define USART_SR_PE_Msk (0x1U << USART_SR_PE_Pos) /*!< 0x00000001 */ #define USART_SR_PE USART_SR_PE_Msk /*!<Parity Error */ #define USART_SR_FE_Pos (1U) #define USART_SR_FE_Msk (0x1U << USART_SR_FE_Pos) /*!< 0x00000002 */ #define USART_SR_FE USART_SR_FE_Msk /*!<Framing Error */ #define USART_SR_NE_Pos (2U) #define USART_SR_NE_Msk (0x1U << USART_SR_NE_Pos) /*!< 0x00000004 */ #define USART_SR_NE USART_SR_NE_Msk /*!<Noise Error Flag */ #define USART_SR_ORE_Pos (3U) #define USART_SR_ORE_Msk (0x1U << USART_SR_ORE_Pos) /*!< 0x00000008 */ #define USART_SR_ORE USART_SR_ORE_Msk /*!<OverRun Error */ #define USART_SR_IDLE_Pos (4U) #define USART_SR_IDLE_Msk (0x1U << USART_SR_IDLE_Pos) /*!< 0x00000010 */ #define USART_SR_IDLE USART_SR_IDLE_Msk /*!<IDLE line detected */ #define USART_SR_RXNE_Pos (5U) #define USART_SR_RXNE_Msk (0x1U << USART_SR_RXNE_Pos) /*!< 0x00000020 */ #define USART_SR_RXNE USART_SR_RXNE_Msk /*!<Read Data Register Not Empty */ #define USART_SR_TC_Pos (6U) #define USART_SR_TC_Msk (0x1U << USART_SR_TC_Pos) /*!< 0x00000040 */ #define USART_SR_TC USART_SR_TC_Msk /*!<Transmission Complete */ #define USART_SR_TXE_Pos (7U) #define USART_SR_TXE_Msk (0x1U << USART_SR_TXE_Pos) /*!< 0x00000080 */ #define USART_SR_TXE USART_SR_TXE_Msk /*!<Transmit Data Register Empty */ #define USART_SR_LBD_Pos (8U) #define USART_SR_LBD_Msk (0x1U << USART_SR_LBD_Pos) /*!< 0x00000100 */ #define USART_SR_LBD USART_SR_LBD_Msk /*!<LIN Break Detection Flag */ #define USART_SR_CTS_Pos (9U) #define USART_SR_CTS_Msk (0x1U << USART_SR_CTS_Pos) /*!< 0x00000200 */ #define USART_SR_CTS USART_SR_CTS_Msk /*!<CTS Flag */ /******************* Bit definition for USART_DR register *******************/ #define USART_DR_DR_Pos (0U) #define USART_DR_DR_Msk (0x1FFU << USART_DR_DR_Pos) /*!< 0x000001FF */ #define USART_DR_DR USART_DR_DR_Msk /*!<Data value */ /****************** Bit definition for USART_BRR register *******************/ #define USART_BRR_DIV_Fraction_Pos (0U) #define USART_BRR_DIV_Fraction_Msk (0xFU << USART_BRR_DIV_Fraction_Pos) /*!< 0x0000000F */ #define USART_BRR_DIV_Fraction USART_BRR_DIV_Fraction_Msk /*!<Fraction of USARTDIV */ #define USART_BRR_DIV_Mantissa_Pos (4U) #define USART_BRR_DIV_Mantissa_Msk (0xFFFU << USART_BRR_DIV_Mantissa_Pos) /*!< 0x0000FFF0 */ #define USART_BRR_DIV_Mantissa USART_BRR_DIV_Mantissa_Msk /*!<Mantissa of USARTDIV */ /****************** Bit definition for USART_CR1 register *******************/ #define USART_CR1_SBK_Pos (0U) #define USART_CR1_SBK_Msk (0x1U << USART_CR1_SBK_Pos) /*!< 0x00000001 */ #define USART_CR1_SBK USART_CR1_SBK_Msk /*!<Send Break */ #define USART_CR1_RWU_Pos (1U) #define USART_CR1_RWU_Msk (0x1U << USART_CR1_RWU_Pos) /*!< 0x00000002 */ #define USART_CR1_RWU USART_CR1_RWU_Msk /*!<Receiver wakeup */ #define USART_CR1_RE_Pos (2U) #define USART_CR1_RE_Msk (0x1U << USART_CR1_RE_Pos) /*!< 0x00000004 */ #define USART_CR1_RE USART_CR1_RE_Msk /*!<Receiver Enable */ #define USART_CR1_TE_Pos (3U) #define USART_CR1_TE_Msk (0x1U << USART_CR1_TE_Pos) /*!< 0x00000008 */ #define USART_CR1_TE USART_CR1_TE_Msk /*!<Transmitter Enable */ #define USART_CR1_IDLEIE_Pos (4U) #define USART_CR1_IDLEIE_Msk (0x1U << USART_CR1_IDLEIE_Pos) /*!< 0x00000010 */ #define USART_CR1_IDLEIE USART_CR1_IDLEIE_Msk /*!<IDLE Interrupt Enable */ #define USART_CR1_RXNEIE_Pos (5U) #define USART_CR1_RXNEIE_Msk (0x1U << USART_CR1_RXNEIE_Pos) /*!< 0x00000020 */ #define USART_CR1_RXNEIE USART_CR1_RXNEIE_Msk /*!<RXNE Interrupt Enable */ #define USART_CR1_TCIE_Pos (6U) #define USART_CR1_TCIE_Msk (0x1U << USART_CR1_TCIE_Pos) /*!< 0x00000040 */ #define USART_CR1_TCIE USART_CR1_TCIE_Msk /*!<Transmission Complete Interrupt Enable */ #define USART_CR1_TXEIE_Pos (7U) #define USART_CR1_TXEIE_Msk (0x1U << USART_CR1_TXEIE_Pos) /*!< 0x00000080 */ #define USART_CR1_TXEIE USART_CR1_TXEIE_Msk /*!<TXE Interrupt Enable */ #define USART_CR1_PEIE_Pos (8U) #define USART_CR1_PEIE_Msk (0x1U << USART_CR1_PEIE_Pos) /*!< 0x00000100 */ #define USART_CR1_PEIE USART_CR1_PEIE_Msk /*!<PE Interrupt Enable */ #define USART_CR1_PS_Pos (9U) #define USART_CR1_PS_Msk (0x1U << USART_CR1_PS_Pos) /*!< 0x00000200 */ #define USART_CR1_PS USART_CR1_PS_Msk /*!<Parity Selection */ #define USART_CR1_PCE_Pos (10U) #define USART_CR1_PCE_Msk (0x1U << USART_CR1_PCE_Pos) /*!< 0x00000400 */ #define USART_CR1_PCE USART_CR1_PCE_Msk /*!<Parity Control Enable */ #define USART_CR1_WAKE_Pos (11U) #define USART_CR1_WAKE_Msk (0x1U << USART_CR1_WAKE_Pos) /*!< 0x00000800 */ #define USART_CR1_WAKE USART_CR1_WAKE_Msk /*!<Wakeup method */ #define USART_CR1_M_Pos (12U) #define USART_CR1_M_Msk (0x1U << USART_CR1_M_Pos) /*!< 0x00001000 */ #define USART_CR1_M USART_CR1_M_Msk /*!<Word length */ #define USART_CR1_UE_Pos (13U) #define USART_CR1_UE_Msk (0x1U << USART_CR1_UE_Pos) /*!< 0x00002000 */ #define USART_CR1_UE USART_CR1_UE_Msk /*!<USART Enable */ #define USART_CR1_OVER8_Pos (15U) #define USART_CR1_OVER8_Msk (0x1U << USART_CR1_OVER8_Pos) /*!< 0x00008000 */ #define USART_CR1_OVER8 USART_CR1_OVER8_Msk /*!<USART Oversampling by 8 enable */ /****************** Bit definition for USART_CR2 register *******************/ #define USART_CR2_ADD_Pos (0U) #define USART_CR2_ADD_Msk (0xFU << USART_CR2_ADD_Pos) /*!< 0x0000000F */ #define USART_CR2_ADD USART_CR2_ADD_Msk /*!<Address of the USART node */ #define USART_CR2_LBDL_Pos (5U) #define USART_CR2_LBDL_Msk (0x1U << USART_CR2_LBDL_Pos) /*!< 0x00000020 */ #define USART_CR2_LBDL USART_CR2_LBDL_Msk /*!<LIN Break Detection Length */ #define USART_CR2_LBDIE_Pos (6U) #define USART_CR2_LBDIE_Msk (0x1U << USART_CR2_LBDIE_Pos) /*!< 0x00000040 */ #define USART_CR2_LBDIE USART_CR2_LBDIE_Msk /*!<LIN Break Detection Interrupt Enable */ #define USART_CR2_LBCL_Pos (8U) #define USART_CR2_LBCL_Msk (0x1U << USART_CR2_LBCL_Pos) /*!< 0x00000100 */ #define USART_CR2_LBCL USART_CR2_LBCL_Msk /*!<Last Bit Clock pulse */ #define USART_CR2_CPHA_Pos (9U) #define USART_CR2_CPHA_Msk (0x1U << USART_CR2_CPHA_Pos) /*!< 0x00000200 */ #define USART_CR2_CPHA USART_CR2_CPHA_Msk /*!<Clock Phase */ #define USART_CR2_CPOL_Pos (10U) #define USART_CR2_CPOL_Msk (0x1U << USART_CR2_CPOL_Pos) /*!< 0x00000400 */ #define USART_CR2_CPOL USART_CR2_CPOL_Msk /*!<Clock Polarity */ #define USART_CR2_CLKEN_Pos (11U) #define USART_CR2_CLKEN_Msk (0x1U << USART_CR2_CLKEN_Pos) /*!< 0x00000800 */ #define USART_CR2_CLKEN USART_CR2_CLKEN_Msk /*!<Clock Enable */ #define USART_CR2_STOP_Pos (12U) #define USART_CR2_STOP_Msk (0x3U << USART_CR2_STOP_Pos) /*!< 0x00003000 */ #define USART_CR2_STOP USART_CR2_STOP_Msk /*!<STOP[1:0] bits (STOP bits) */ #define USART_CR2_STOP_0 (0x1U << USART_CR2_STOP_Pos) /*!< 0x1000 */ #define USART_CR2_STOP_1 (0x2U << USART_CR2_STOP_Pos) /*!< 0x2000 */ #define USART_CR2_LINEN_Pos (14U) #define USART_CR2_LINEN_Msk (0x1U << USART_CR2_LINEN_Pos) /*!< 0x00004000 */ #define USART_CR2_LINEN USART_CR2_LINEN_Msk /*!<LIN mode enable */ /****************** Bit definition for USART_CR3 register *******************/ #define USART_CR3_EIE_Pos (0U) #define USART_CR3_EIE_Msk (0x1U << USART_CR3_EIE_Pos) /*!< 0x00000001 */ #define USART_CR3_EIE USART_CR3_EIE_Msk /*!<Error Interrupt Enable */ #define USART_CR3_IREN_Pos (1U) #define USART_CR3_IREN_Msk (0x1U << USART_CR3_IREN_Pos) /*!< 0x00000002 */ #define USART_CR3_IREN USART_CR3_IREN_Msk /*!<IrDA mode Enable */ #define USART_CR3_IRLP_Pos (2U) #define USART_CR3_IRLP_Msk (0x1U << USART_CR3_IRLP_Pos) /*!< 0x00000004 */ #define USART_CR3_IRLP USART_CR3_IRLP_Msk /*!<IrDA Low-Power */ #define USART_CR3_HDSEL_Pos (3U) #define USART_CR3_HDSEL_Msk (0x1U << USART_CR3_HDSEL_Pos) /*!< 0x00000008 */ #define USART_CR3_HDSEL USART_CR3_HDSEL_Msk /*!<Half-Duplex Selection */ #define USART_CR3_NACK_Pos (4U) #define USART_CR3_NACK_Msk (0x1U << USART_CR3_NACK_Pos) /*!< 0x00000010 */ #define USART_CR3_NACK USART_CR3_NACK_Msk /*!<Smartcard NACK enable */ #define USART_CR3_SCEN_Pos (5U) #define USART_CR3_SCEN_Msk (0x1U << USART_CR3_SCEN_Pos) /*!< 0x00000020 */ #define USART_CR3_SCEN USART_CR3_SCEN_Msk /*!<Smartcard mode enable */ #define USART_CR3_DMAR_Pos (6U) #define USART_CR3_DMAR_Msk (0x1U << USART_CR3_DMAR_Pos) /*!< 0x00000040 */ #define USART_CR3_DMAR USART_CR3_DMAR_Msk /*!<DMA Enable Receiver */ #define USART_CR3_DMAT_Pos (7U) #define USART_CR3_DMAT_Msk (0x1U << USART_CR3_DMAT_Pos) /*!< 0x00000080 */ #define USART_CR3_DMAT USART_CR3_DMAT_Msk /*!<DMA Enable Transmitter */ #define USART_CR3_RTSE_Pos (8U) #define USART_CR3_RTSE_Msk (0x1U << USART_CR3_RTSE_Pos) /*!< 0x00000100 */ #define USART_CR3_RTSE USART_CR3_RTSE_Msk /*!<RTS Enable */ #define USART_CR3_CTSE_Pos (9U) #define USART_CR3_CTSE_Msk (0x1U << USART_CR3_CTSE_Pos) /*!< 0x00000200 */ #define USART_CR3_CTSE USART_CR3_CTSE_Msk /*!<CTS Enable */ #define USART_CR3_CTSIE_Pos (10U) #define USART_CR3_CTSIE_Msk (0x1U << USART_CR3_CTSIE_Pos) /*!< 0x00000400 */ #define USART_CR3_CTSIE USART_CR3_CTSIE_Msk /*!<CTS Interrupt Enable */ #define USART_CR3_ONEBIT_Pos (11U) #define USART_CR3_ONEBIT_Msk (0x1U << USART_CR3_ONEBIT_Pos) /*!< 0x00000800 */ #define USART_CR3_ONEBIT USART_CR3_ONEBIT_Msk /*!<USART One bit method enable */ /****************** Bit definition for USART_GTPR register ******************/ #define USART_GTPR_PSC_Pos (0U) #define USART_GTPR_PSC_Msk (0xFFU << USART_GTPR_PSC_Pos) /*!< 0x000000FF */ #define USART_GTPR_PSC USART_GTPR_PSC_Msk /*!<PSC[7:0] bits (Prescaler value) */ #define USART_GTPR_PSC_0 (0x01U << USART_GTPR_PSC_Pos) /*!< 0x0001 */ #define USART_GTPR_PSC_1 (0x02U << USART_GTPR_PSC_Pos) /*!< 0x0002 */ #define USART_GTPR_PSC_2 (0x04U << USART_GTPR_PSC_Pos) /*!< 0x0004 */ #define USART_GTPR_PSC_3 (0x08U << USART_GTPR_PSC_Pos) /*!< 0x0008 */ #define USART_GTPR_PSC_4 (0x10U << USART_GTPR_PSC_Pos) /*!< 0x0010 */ #define USART_GTPR_PSC_5 (0x20U << USART_GTPR_PSC_Pos) /*!< 0x0020 */ #define USART_GTPR_PSC_6 (0x40U << USART_GTPR_PSC_Pos) /*!< 0x0040 */ #define USART_GTPR_PSC_7 (0x80U << USART_GTPR_PSC_Pos) /*!< 0x0080 */ #define USART_GTPR_GT_Pos (8U) #define USART_GTPR_GT_Msk (0xFFU << USART_GTPR_GT_Pos) /*!< 0x0000FF00 */ #define USART_GTPR_GT USART_GTPR_GT_Msk /*!<Guard time value */ /******************************************************************************/ /* */ /* Window WATCHDOG */ /* */ /******************************************************************************/ /******************* Bit definition for WWDG_CR register ********************/ #define WWDG_CR_T_Pos (0U) #define WWDG_CR_T_Msk (0x7FU << WWDG_CR_T_Pos) /*!< 0x0000007F */ #define WWDG_CR_T WWDG_CR_T_Msk /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */ #define WWDG_CR_T_0 (0x01U << WWDG_CR_T_Pos) /*!< 0x01 */ #define WWDG_CR_T_1 (0x02U << WWDG_CR_T_Pos) /*!< 0x02 */ #define WWDG_CR_T_2 (0x04U << WWDG_CR_T_Pos) /*!< 0x04 */ #define WWDG_CR_T_3 (0x08U << WWDG_CR_T_Pos) /*!< 0x08 */ #define WWDG_CR_T_4 (0x10U << WWDG_CR_T_Pos) /*!< 0x10 */ #define WWDG_CR_T_5 (0x20U << WWDG_CR_T_Pos) /*!< 0x20 */ #define WWDG_CR_T_6 (0x40U << WWDG_CR_T_Pos) /*!< 0x40 */ /* Legacy defines */ #define WWDG_CR_T0 WWDG_CR_T_0 #define WWDG_CR_T1 WWDG_CR_T_1 #define WWDG_CR_T2 WWDG_CR_T_2 #define WWDG_CR_T3 WWDG_CR_T_3 #define WWDG_CR_T4 WWDG_CR_T_4 #define WWDG_CR_T5 WWDG_CR_T_5 #define WWDG_CR_T6 WWDG_CR_T_6 #define WWDG_CR_WDGA_Pos (7U) #define WWDG_CR_WDGA_Msk (0x1U << WWDG_CR_WDGA_Pos) /*!< 0x00000080 */ #define WWDG_CR_WDGA WWDG_CR_WDGA_Msk /*!<Activation bit */ /******************* Bit definition for WWDG_CFR register *******************/ #define WWDG_CFR_W_Pos (0U) #define WWDG_CFR_W_Msk (0x7FU << WWDG_CFR_W_Pos) /*!< 0x0000007F */ #define WWDG_CFR_W WWDG_CFR_W_Msk /*!<W[6:0] bits (7-bit window value) */ #define WWDG_CFR_W_0 (0x01U << WWDG_CFR_W_Pos) /*!< 0x0001 */ #define WWDG_CFR_W_1 (0x02U << WWDG_CFR_W_Pos) /*!< 0x0002 */ #define WWDG_CFR_W_2 (0x04U << WWDG_CFR_W_Pos) /*!< 0x0004 */ #define WWDG_CFR_W_3 (0x08U << WWDG_CFR_W_Pos) /*!< 0x0008 */ #define WWDG_CFR_W_4 (0x10U << WWDG_CFR_W_Pos) /*!< 0x0010 */ #define WWDG_CFR_W_5 (0x20U << WWDG_CFR_W_Pos) /*!< 0x0020 */ #define WWDG_CFR_W_6 (0x40U << WWDG_CFR_W_Pos) /*!< 0x0040 */ /* Legacy defines */ #define WWDG_CFR_W0 WWDG_CFR_W_0 #define WWDG_CFR_W1 WWDG_CFR_W_1 #define WWDG_CFR_W2 WWDG_CFR_W_2 #define WWDG_CFR_W3 WWDG_CFR_W_3 #define WWDG_CFR_W4 WWDG_CFR_W_4 #define WWDG_CFR_W5 WWDG_CFR_W_5 #define WWDG_CFR_W6 WWDG_CFR_W_6 #define WWDG_CFR_WDGTB_Pos (7U) #define WWDG_CFR_WDGTB_Msk (0x3U << WWDG_CFR_WDGTB_Pos) /*!< 0x00000180 */ #define WWDG_CFR_WDGTB WWDG_CFR_WDGTB_Msk /*!<WDGTB[1:0] bits (Timer Base) */ #define WWDG_CFR_WDGTB_0 (0x1U << WWDG_CFR_WDGTB_Pos) /*!< 0x0080 */ #define WWDG_CFR_WDGTB_1 (0x2U << WWDG_CFR_WDGTB_Pos) /*!< 0x0100 */ /* Legacy defines */ #define WWDG_CFR_WDGTB0 WWDG_CFR_WDGTB_0 #define WWDG_CFR_WDGTB1 WWDG_CFR_WDGTB_1 #define WWDG_CFR_EWI_Pos (9U) #define WWDG_CFR_EWI_Msk (0x1U << WWDG_CFR_EWI_Pos) /*!< 0x00000200 */ #define WWDG_CFR_EWI WWDG_CFR_EWI_Msk /*!<Early Wakeup Interrupt */ /******************* Bit definition for WWDG_SR register ********************/ #define WWDG_SR_EWIF_Pos (0U) #define WWDG_SR_EWIF_Msk (0x1U << WWDG_SR_EWIF_Pos) /*!< 0x00000001 */ #define WWDG_SR_EWIF WWDG_SR_EWIF_Msk /*!<Early Wakeup Interrupt Flag */ /******************************************************************************/ /* */ /* DBG */ /* */ /******************************************************************************/ /******************** Bit definition for DBGMCU_IDCODE register *************/ #define DBGMCU_IDCODE_DEV_ID_Pos (0U) #define DBGMCU_IDCODE_DEV_ID_Msk (0xFFFU << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */ #define DBGMCU_IDCODE_DEV_ID DBGMCU_IDCODE_DEV_ID_Msk #define DBGMCU_IDCODE_REV_ID_Pos (16U) #define DBGMCU_IDCODE_REV_ID_Msk (0xFFFFU << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */ #define DBGMCU_IDCODE_REV_ID DBGMCU_IDCODE_REV_ID_Msk /******************** Bit definition for DBGMCU_CR register *****************/ #define DBGMCU_CR_DBG_SLEEP_Pos (0U) #define DBGMCU_CR_DBG_SLEEP_Msk (0x1U << DBGMCU_CR_DBG_SLEEP_Pos) /*!< 0x00000001 */ #define DBGMCU_CR_DBG_SLEEP DBGMCU_CR_DBG_SLEEP_Msk #define DBGMCU_CR_DBG_STOP_Pos (1U) #define DBGMCU_CR_DBG_STOP_Msk (0x1U << DBGMCU_CR_DBG_STOP_Pos) /*!< 0x00000002 */ #define DBGMCU_CR_DBG_STOP DBGMCU_CR_DBG_STOP_Msk #define DBGMCU_CR_DBG_STANDBY_Pos (2U) #define DBGMCU_CR_DBG_STANDBY_Msk (0x1U << DBGMCU_CR_DBG_STANDBY_Pos) /*!< 0x00000004 */ #define DBGMCU_CR_DBG_STANDBY DBGMCU_CR_DBG_STANDBY_Msk #define DBGMCU_CR_TRACE_IOEN_Pos (5U) #define DBGMCU_CR_TRACE_IOEN_Msk (0x1U << DBGMCU_CR_TRACE_IOEN_Pos) /*!< 0x00000020 */ #define DBGMCU_CR_TRACE_IOEN DBGMCU_CR_TRACE_IOEN_Msk #define DBGMCU_CR_TRACE_MODE_Pos (6U) #define DBGMCU_CR_TRACE_MODE_Msk (0x3U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x000000C0 */ #define DBGMCU_CR_TRACE_MODE DBGMCU_CR_TRACE_MODE_Msk #define DBGMCU_CR_TRACE_MODE_0 (0x1U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000040 */ #define DBGMCU_CR_TRACE_MODE_1 (0x2U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000080 */ /******************** Bit definition for DBGMCU_APB1_FZ register ************/ #define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos (0U) #define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos) /*!< 0x00000001 */ #define DBGMCU_APB1_FZ_DBG_TIM2_STOP DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk #define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos (1U) #define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos) /*!< 0x00000002 */ #define DBGMCU_APB1_FZ_DBG_TIM3_STOP DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk #define DBGMCU_APB1_FZ_DBG_TIM4_STOP_Pos (2U) #define DBGMCU_APB1_FZ_DBG_TIM4_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM4_STOP_Pos) /*!< 0x00000004 */ #define DBGMCU_APB1_FZ_DBG_TIM4_STOP DBGMCU_APB1_FZ_DBG_TIM4_STOP_Msk #define DBGMCU_APB1_FZ_DBG_TIM5_STOP_Pos (3U) #define DBGMCU_APB1_FZ_DBG_TIM5_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM5_STOP_Pos) /*!< 0x00000008 */ #define DBGMCU_APB1_FZ_DBG_TIM5_STOP DBGMCU_APB1_FZ_DBG_TIM5_STOP_Msk #define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos (4U) #define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos) /*!< 0x00000010 */ #define DBGMCU_APB1_FZ_DBG_TIM6_STOP DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk #define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos (5U) #define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos) /*!< 0x00000020 */ #define DBGMCU_APB1_FZ_DBG_TIM7_STOP DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk #define DBGMCU_APB1_FZ_DBG_TIM12_STOP_Pos (6U) #define DBGMCU_APB1_FZ_DBG_TIM12_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM12_STOP_Pos) /*!< 0x00000040 */ #define DBGMCU_APB1_FZ_DBG_TIM12_STOP DBGMCU_APB1_FZ_DBG_TIM12_STOP_Msk #define DBGMCU_APB1_FZ_DBG_TIM13_STOP_Pos (7U) #define DBGMCU_APB1_FZ_DBG_TIM13_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM13_STOP_Pos) /*!< 0x00000080 */ #define DBGMCU_APB1_FZ_DBG_TIM13_STOP DBGMCU_APB1_FZ_DBG_TIM13_STOP_Msk #define DBGMCU_APB1_FZ_DBG_TIM14_STOP_Pos (8U) #define DBGMCU_APB1_FZ_DBG_TIM14_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM14_STOP_Pos) /*!< 0x00000100 */ #define DBGMCU_APB1_FZ_DBG_TIM14_STOP DBGMCU_APB1_FZ_DBG_TIM14_STOP_Msk #define DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos (10U) #define DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos) /*!< 0x00000400 */ #define DBGMCU_APB1_FZ_DBG_RTC_STOP DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk #define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos (11U) #define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos) /*!< 0x00000800 */ #define DBGMCU_APB1_FZ_DBG_WWDG_STOP DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk #define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos (12U) #define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos) /*!< 0x00001000 */ #define DBGMCU_APB1_FZ_DBG_IWDG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos (21U) #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk (0x1U << DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos) /*!< 0x00200000 */ #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk #define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Pos (22U) #define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Msk (0x1U << DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Pos) /*!< 0x00400000 */ #define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Msk #define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Pos (23U) #define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Msk (0x1U << DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Pos) /*!< 0x00800000 */ #define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Msk #define DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT_Pos (24U) #define DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT_Msk (0x1U << DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT_Pos) /*!< 0x01000000 */ #define DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT_Msk #define DBGMCU_APB1_FZ_DBG_CAN1_STOP_Pos (25U) #define DBGMCU_APB1_FZ_DBG_CAN1_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_CAN1_STOP_Pos) /*!< 0x02000000 */ #define DBGMCU_APB1_FZ_DBG_CAN1_STOP DBGMCU_APB1_FZ_DBG_CAN1_STOP_Msk #define DBGMCU_APB1_FZ_DBG_CAN2_STOP_Pos (26U) #define DBGMCU_APB1_FZ_DBG_CAN2_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_CAN2_STOP_Pos) /*!< 0x04000000 */ #define DBGMCU_APB1_FZ_DBG_CAN2_STOP DBGMCU_APB1_FZ_DBG_CAN2_STOP_Msk /* Old IWDGSTOP bit definition, maintained for legacy purpose */ #define DBGMCU_APB1_FZ_DBG_IWDEG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP /******************** Bit definition for DBGMCU_APB2_FZ register ************/ #define DBGMCU_APB2_FZ_DBG_TIM1_STOP_Pos (0U) #define DBGMCU_APB2_FZ_DBG_TIM1_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM1_STOP_Pos) /*!< 0x00000001 */ #define DBGMCU_APB2_FZ_DBG_TIM1_STOP DBGMCU_APB2_FZ_DBG_TIM1_STOP_Msk #define DBGMCU_APB2_FZ_DBG_TIM8_STOP_Pos (1U) #define DBGMCU_APB2_FZ_DBG_TIM8_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM8_STOP_Pos) /*!< 0x00000002 */ #define DBGMCU_APB2_FZ_DBG_TIM8_STOP DBGMCU_APB2_FZ_DBG_TIM8_STOP_Msk #define DBGMCU_APB2_FZ_DBG_TIM9_STOP_Pos (16U) #define DBGMCU_APB2_FZ_DBG_TIM9_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM9_STOP_Pos) /*!< 0x00010000 */ #define DBGMCU_APB2_FZ_DBG_TIM9_STOP DBGMCU_APB2_FZ_DBG_TIM9_STOP_Msk #define DBGMCU_APB2_FZ_DBG_TIM10_STOP_Pos (17U) #define DBGMCU_APB2_FZ_DBG_TIM10_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM10_STOP_Pos) /*!< 0x00020000 */ #define DBGMCU_APB2_FZ_DBG_TIM10_STOP DBGMCU_APB2_FZ_DBG_TIM10_STOP_Msk #define DBGMCU_APB2_FZ_DBG_TIM11_STOP_Pos (18U) #define DBGMCU_APB2_FZ_DBG_TIM11_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM11_STOP_Pos) /*!< 0x00040000 */ #define DBGMCU_APB2_FZ_DBG_TIM11_STOP DBGMCU_APB2_FZ_DBG_TIM11_STOP_Msk /******************************************************************************/ /* */ /* Ethernet MAC Registers bits definitions */ /* */ /******************************************************************************/ /* Bit definition for Ethernet MAC Control Register register */ #define ETH_MACCR_WD_Pos (23U) #define ETH_MACCR_WD_Msk (0x1U << ETH_MACCR_WD_Pos) /*!< 0x00800000 */ #define ETH_MACCR_WD ETH_MACCR_WD_Msk /* Watchdog disable */ #define ETH_MACCR_JD_Pos (22U) #define ETH_MACCR_JD_Msk (0x1U << ETH_MACCR_JD_Pos) /*!< 0x00400000 */ #define ETH_MACCR_JD ETH_MACCR_JD_Msk /* Jabber disable */ #define ETH_MACCR_IFG_Pos (17U) #define ETH_MACCR_IFG_Msk (0x7U << ETH_MACCR_IFG_Pos) /*!< 0x000E0000 */ #define ETH_MACCR_IFG ETH_MACCR_IFG_Msk /* Inter-frame gap */ #define ETH_MACCR_IFG_96Bit 0x00000000U /* Minimum IFG between frames during transmission is 96Bit */ #define ETH_MACCR_IFG_88Bit 0x00020000U /* Minimum IFG between frames during transmission is 88Bit */ #define ETH_MACCR_IFG_80Bit 0x00040000U /* Minimum IFG between frames during transmission is 80Bit */ #define ETH_MACCR_IFG_72Bit 0x00060000U /* Minimum IFG between frames during transmission is 72Bit */ #define ETH_MACCR_IFG_64Bit 0x00080000U /* Minimum IFG between frames during transmission is 64Bit */ #define ETH_MACCR_IFG_56Bit 0x000A0000U /* Minimum IFG between frames during transmission is 56Bit */ #define ETH_MACCR_IFG_48Bit 0x000C0000U /* Minimum IFG between frames during transmission is 48Bit */ #define ETH_MACCR_IFG_40Bit 0x000E0000U /* Minimum IFG between frames during transmission is 40Bit */ #define ETH_MACCR_CSD_Pos (16U) #define ETH_MACCR_CSD_Msk (0x1U << ETH_MACCR_CSD_Pos) /*!< 0x00010000 */ #define ETH_MACCR_CSD ETH_MACCR_CSD_Msk /* Carrier sense disable (during transmission) */ #define ETH_MACCR_FES_Pos (14U) #define ETH_MACCR_FES_Msk (0x1U << ETH_MACCR_FES_Pos) /*!< 0x00004000 */ #define ETH_MACCR_FES ETH_MACCR_FES_Msk /* Fast ethernet speed */ #define ETH_MACCR_ROD_Pos (13U) #define ETH_MACCR_ROD_Msk (0x1U << ETH_MACCR_ROD_Pos) /*!< 0x00002000 */ #define ETH_MACCR_ROD ETH_MACCR_ROD_Msk /* Receive own disable */ #define ETH_MACCR_LM_Pos (12U) #define ETH_MACCR_LM_Msk (0x1U << ETH_MACCR_LM_Pos) /*!< 0x00001000 */ #define ETH_MACCR_LM ETH_MACCR_LM_Msk /* loopback mode */ #define ETH_MACCR_DM_Pos (11U) #define ETH_MACCR_DM_Msk (0x1U << ETH_MACCR_DM_Pos) /*!< 0x00000800 */ #define ETH_MACCR_DM ETH_MACCR_DM_Msk /* Duplex mode */ #define ETH_MACCR_IPCO_Pos (10U) #define ETH_MACCR_IPCO_Msk (0x1U << ETH_MACCR_IPCO_Pos) /*!< 0x00000400 */ #define ETH_MACCR_IPCO ETH_MACCR_IPCO_Msk /* IP Checksum offload */ #define ETH_MACCR_RD_Pos (9U) #define ETH_MACCR_RD_Msk (0x1U << ETH_MACCR_RD_Pos) /*!< 0x00000200 */ #define ETH_MACCR_RD ETH_MACCR_RD_Msk /* Retry disable */ #define ETH_MACCR_APCS_Pos (7U) #define ETH_MACCR_APCS_Msk (0x1U << ETH_MACCR_APCS_Pos) /*!< 0x00000080 */ #define ETH_MACCR_APCS ETH_MACCR_APCS_Msk /* Automatic Pad/CRC stripping */ #define ETH_MACCR_BL_Pos (5U) #define ETH_MACCR_BL_Msk (0x3U << ETH_MACCR_BL_Pos) /*!< 0x00000060 */ #define ETH_MACCR_BL ETH_MACCR_BL_Msk /* Back-off limit: random integer number (r) of slot time delays before rescheduling a transmission attempt during retries after a collision: 0 =< r <2^k */ #define ETH_MACCR_BL_10 0x00000000U /* k = min (n, 10) */ #define ETH_MACCR_BL_8 0x00000020U /* k = min (n, 8) */ #define ETH_MACCR_BL_4 0x00000040U /* k = min (n, 4) */ #define ETH_MACCR_BL_1 0x00000060U /* k = min (n, 1) */ #define ETH_MACCR_DC_Pos (4U) #define ETH_MACCR_DC_Msk (0x1U << ETH_MACCR_DC_Pos) /*!< 0x00000010 */ #define ETH_MACCR_DC ETH_MACCR_DC_Msk /* Defferal check */ #define ETH_MACCR_TE_Pos (3U) #define ETH_MACCR_TE_Msk (0x1U << ETH_MACCR_TE_Pos) /*!< 0x00000008 */ #define ETH_MACCR_TE ETH_MACCR_TE_Msk /* Transmitter enable */ #define ETH_MACCR_RE_Pos (2U) #define ETH_MACCR_RE_Msk (0x1U << ETH_MACCR_RE_Pos) /*!< 0x00000004 */ #define ETH_MACCR_RE ETH_MACCR_RE_Msk /* Receiver enable */ /* Bit definition for Ethernet MAC Frame Filter Register */ #define ETH_MACFFR_RA_Pos (31U) #define ETH_MACFFR_RA_Msk (0x1U << ETH_MACFFR_RA_Pos) /*!< 0x80000000 */ #define ETH_MACFFR_RA ETH_MACFFR_RA_Msk /* Receive all */ #define ETH_MACFFR_HPF_Pos (10U) #define ETH_MACFFR_HPF_Msk (0x1U << ETH_MACFFR_HPF_Pos) /*!< 0x00000400 */ #define ETH_MACFFR_HPF ETH_MACFFR_HPF_Msk /* Hash or perfect filter */ #define ETH_MACFFR_SAF_Pos (9U) #define ETH_MACFFR_SAF_Msk (0x1U << ETH_MACFFR_SAF_Pos) /*!< 0x00000200 */ #define ETH_MACFFR_SAF ETH_MACFFR_SAF_Msk /* Source address filter enable */ #define ETH_MACFFR_SAIF_Pos (8U) #define ETH_MACFFR_SAIF_Msk (0x1U << ETH_MACFFR_SAIF_Pos) /*!< 0x00000100 */ #define ETH_MACFFR_SAIF ETH_MACFFR_SAIF_Msk /* SA inverse filtering */ #define ETH_MACFFR_PCF_Pos (6U) #define ETH_MACFFR_PCF_Msk (0x3U << ETH_MACFFR_PCF_Pos) /*!< 0x000000C0 */ #define ETH_MACFFR_PCF ETH_MACFFR_PCF_Msk /* Pass control frames: 3 cases */ #define ETH_MACFFR_PCF_BlockAll_Pos (6U) #define ETH_MACFFR_PCF_BlockAll_Msk (0x1U << ETH_MACFFR_PCF_BlockAll_Pos) /*!< 0x00000040 */ #define ETH_MACFFR_PCF_BlockAll ETH_MACFFR_PCF_BlockAll_Msk /* MAC filters all control frames from reaching the application */ #define ETH_MACFFR_PCF_ForwardAll_Pos (7U) #define ETH_MACFFR_PCF_ForwardAll_Msk (0x1U << ETH_MACFFR_PCF_ForwardAll_Pos) /*!< 0x00000080 */ #define ETH_MACFFR_PCF_ForwardAll ETH_MACFFR_PCF_ForwardAll_Msk /* MAC forwards all control frames to application even if they fail the Address Filter */ #define ETH_MACFFR_PCF_ForwardPassedAddrFilter_Pos (6U) #define ETH_MACFFR_PCF_ForwardPassedAddrFilter_Msk (0x3U << ETH_MACFFR_PCF_ForwardPassedAddrFilter_Pos) /*!< 0x000000C0 */ #define ETH_MACFFR_PCF_ForwardPassedAddrFilter ETH_MACFFR_PCF_ForwardPassedAddrFilter_Msk /* MAC forwards control frames that pass the Address Filter. */ #define ETH_MACFFR_BFD_Pos (5U) #define ETH_MACFFR_BFD_Msk (0x1U << ETH_MACFFR_BFD_Pos) /*!< 0x00000020 */ #define ETH_MACFFR_BFD ETH_MACFFR_BFD_Msk /* Broadcast frame disable */ #define ETH_MACFFR_PAM_Pos (4U) #define ETH_MACFFR_PAM_Msk (0x1U << ETH_MACFFR_PAM_Pos) /*!< 0x00000010 */ #define ETH_MACFFR_PAM ETH_MACFFR_PAM_Msk /* Pass all mutlicast */ #define ETH_MACFFR_DAIF_Pos (3U) #define ETH_MACFFR_DAIF_Msk (0x1U << ETH_MACFFR_DAIF_Pos) /*!< 0x00000008 */ #define ETH_MACFFR_DAIF ETH_MACFFR_DAIF_Msk /* DA Inverse filtering */ #define ETH_MACFFR_HM_Pos (2U) #define ETH_MACFFR_HM_Msk (0x1U << ETH_MACFFR_HM_Pos) /*!< 0x00000004 */ #define ETH_MACFFR_HM ETH_MACFFR_HM_Msk /* Hash multicast */ #define ETH_MACFFR_HU_Pos (1U) #define ETH_MACFFR_HU_Msk (0x1U << ETH_MACFFR_HU_Pos) /*!< 0x00000002 */ #define ETH_MACFFR_HU ETH_MACFFR_HU_Msk /* Hash unicast */ #define ETH_MACFFR_PM_Pos (0U) #define ETH_MACFFR_PM_Msk (0x1U << ETH_MACFFR_PM_Pos) /*!< 0x00000001 */ #define ETH_MACFFR_PM ETH_MACFFR_PM_Msk /* Promiscuous mode */ /* Bit definition for Ethernet MAC Hash Table High Register */ #define ETH_MACHTHR_HTH_Pos (0U) #define ETH_MACHTHR_HTH_Msk (0xFFFFFFFFU << ETH_MACHTHR_HTH_Pos) /*!< 0xFFFFFFFF */ #define ETH_MACHTHR_HTH ETH_MACHTHR_HTH_Msk /* Hash table high */ /* Bit definition for Ethernet MAC Hash Table Low Register */ #define ETH_MACHTLR_HTL_Pos (0U) #define ETH_MACHTLR_HTL_Msk (0xFFFFFFFFU << ETH_MACHTLR_HTL_Pos) /*!< 0xFFFFFFFF */ #define ETH_MACHTLR_HTL ETH_MACHTLR_HTL_Msk /* Hash table low */ /* Bit definition for Ethernet MAC MII Address Register */ #define ETH_MACMIIAR_PA_Pos (11U) #define ETH_MACMIIAR_PA_Msk (0x1FU << ETH_MACMIIAR_PA_Pos) /*!< 0x0000F800 */ #define ETH_MACMIIAR_PA ETH_MACMIIAR_PA_Msk /* Physical layer address */ #define ETH_MACMIIAR_MR_Pos (6U) #define ETH_MACMIIAR_MR_Msk (0x1FU << ETH_MACMIIAR_MR_Pos) /*!< 0x000007C0 */ #define ETH_MACMIIAR_MR ETH_MACMIIAR_MR_Msk /* MII register in the selected PHY */ #define ETH_MACMIIAR_CR_Pos (2U) #define ETH_MACMIIAR_CR_Msk (0x7U << ETH_MACMIIAR_CR_Pos) /*!< 0x0000001C */ #define ETH_MACMIIAR_CR ETH_MACMIIAR_CR_Msk /* CR clock range: 6 cases */ #define ETH_MACMIIAR_CR_Div42 0x00000000U /* HCLK:60-100 MHz; MDC clock= HCLK/42 */ #define ETH_MACMIIAR_CR_Div62_Pos (2U) #define ETH_MACMIIAR_CR_Div62_Msk (0x1U << ETH_MACMIIAR_CR_Div62_Pos) /*!< 0x00000004 */ #define ETH_MACMIIAR_CR_Div62 ETH_MACMIIAR_CR_Div62_Msk /* HCLK:100-150 MHz; MDC clock= HCLK/62 */ #define ETH_MACMIIAR_CR_Div16_Pos (3U) #define ETH_MACMIIAR_CR_Div16_Msk (0x1U << ETH_MACMIIAR_CR_Div16_Pos) /*!< 0x00000008 */ #define ETH_MACMIIAR_CR_Div16 ETH_MACMIIAR_CR_Div16_Msk /* HCLK:20-35 MHz; MDC clock= HCLK/16 */ #define ETH_MACMIIAR_CR_Div26_Pos (2U) #define ETH_MACMIIAR_CR_Div26_Msk (0x3U << ETH_MACMIIAR_CR_Div26_Pos) /*!< 0x0000000C */ #define ETH_MACMIIAR_CR_Div26 ETH_MACMIIAR_CR_Div26_Msk /* HCLK:35-60 MHz; MDC clock= HCLK/26 */ #define ETH_MACMIIAR_CR_Div102_Pos (4U) #define ETH_MACMIIAR_CR_Div102_Msk (0x1U << ETH_MACMIIAR_CR_Div102_Pos) /*!< 0x00000010 */ #define ETH_MACMIIAR_CR_Div102 ETH_MACMIIAR_CR_Div102_Msk /* HCLK:150-168 MHz; MDC clock= HCLK/102 */ #define ETH_MACMIIAR_MW_Pos (1U) #define ETH_MACMIIAR_MW_Msk (0x1U << ETH_MACMIIAR_MW_Pos) /*!< 0x00000002 */ #define ETH_MACMIIAR_MW ETH_MACMIIAR_MW_Msk /* MII write */ #define ETH_MACMIIAR_MB_Pos (0U) #define ETH_MACMIIAR_MB_Msk (0x1U << ETH_MACMIIAR_MB_Pos) /*!< 0x00000001 */ #define ETH_MACMIIAR_MB ETH_MACMIIAR_MB_Msk /* MII busy */ /* Bit definition for Ethernet MAC MII Data Register */ #define ETH_MACMIIDR_MD_Pos (0U) #define ETH_MACMIIDR_MD_Msk (0xFFFFU << ETH_MACMIIDR_MD_Pos) /*!< 0x0000FFFF */ #define ETH_MACMIIDR_MD ETH_MACMIIDR_MD_Msk /* MII data: read/write data from/to PHY */ /* Bit definition for Ethernet MAC Flow Control Register */ #define ETH_MACFCR_PT_Pos (16U) #define ETH_MACFCR_PT_Msk (0xFFFFU << ETH_MACFCR_PT_Pos) /*!< 0xFFFF0000 */ #define ETH_MACFCR_PT ETH_MACFCR_PT_Msk /* Pause time */ #define ETH_MACFCR_ZQPD_Pos (7U) #define ETH_MACFCR_ZQPD_Msk (0x1U << ETH_MACFCR_ZQPD_Pos) /*!< 0x00000080 */ #define ETH_MACFCR_ZQPD ETH_MACFCR_ZQPD_Msk /* Zero-quanta pause disable */ #define ETH_MACFCR_PLT_Pos (4U) #define ETH_MACFCR_PLT_Msk (0x3U << ETH_MACFCR_PLT_Pos) /*!< 0x00000030 */ #define ETH_MACFCR_PLT ETH_MACFCR_PLT_Msk /* Pause low threshold: 4 cases */ #define ETH_MACFCR_PLT_Minus4 0x00000000U /* Pause time minus 4 slot times */ #define ETH_MACFCR_PLT_Minus28_Pos (4U) #define ETH_MACFCR_PLT_Minus28_Msk (0x1U << ETH_MACFCR_PLT_Minus28_Pos) /*!< 0x00000010 */ #define ETH_MACFCR_PLT_Minus28 ETH_MACFCR_PLT_Minus28_Msk /* Pause time minus 28 slot times */ #define ETH_MACFCR_PLT_Minus144_Pos (5U) #define ETH_MACFCR_PLT_Minus144_Msk (0x1U << ETH_MACFCR_PLT_Minus144_Pos) /*!< 0x00000020 */ #define ETH_MACFCR_PLT_Minus144 ETH_MACFCR_PLT_Minus144_Msk /* Pause time minus 144 slot times */ #define ETH_MACFCR_PLT_Minus256_Pos (4U) #define ETH_MACFCR_PLT_Minus256_Msk (0x3U << ETH_MACFCR_PLT_Minus256_Pos) /*!< 0x00000030 */ #define ETH_MACFCR_PLT_Minus256 ETH_MACFCR_PLT_Minus256_Msk /* Pause time minus 256 slot times */ #define ETH_MACFCR_UPFD_Pos (3U) #define ETH_MACFCR_UPFD_Msk (0x1U << ETH_MACFCR_UPFD_Pos) /*!< 0x00000008 */ #define ETH_MACFCR_UPFD ETH_MACFCR_UPFD_Msk /* Unicast pause frame detect */ #define ETH_MACFCR_RFCE_Pos (2U) #define ETH_MACFCR_RFCE_Msk (0x1U << ETH_MACFCR_RFCE_Pos) /*!< 0x00000004 */ #define ETH_MACFCR_RFCE ETH_MACFCR_RFCE_Msk /* Receive flow control enable */ #define ETH_MACFCR_TFCE_Pos (1U) #define ETH_MACFCR_TFCE_Msk (0x1U << ETH_MACFCR_TFCE_Pos) /*!< 0x00000002 */ #define ETH_MACFCR_TFCE ETH_MACFCR_TFCE_Msk /* Transmit flow control enable */ #define ETH_MACFCR_FCBBPA_Pos (0U) #define ETH_MACFCR_FCBBPA_Msk (0x1U << ETH_MACFCR_FCBBPA_Pos) /*!< 0x00000001 */ #define ETH_MACFCR_FCBBPA ETH_MACFCR_FCBBPA_Msk /* Flow control busy/backpressure activate */ /* Bit definition for Ethernet MAC VLAN Tag Register */ #define ETH_MACVLANTR_VLANTC_Pos (16U) #define ETH_MACVLANTR_VLANTC_Msk (0x1U << ETH_MACVLANTR_VLANTC_Pos) /*!< 0x00010000 */ #define ETH_MACVLANTR_VLANTC ETH_MACVLANTR_VLANTC_Msk /* 12-bit VLAN tag comparison */ #define ETH_MACVLANTR_VLANTI_Pos (0U) #define ETH_MACVLANTR_VLANTI_Msk (0xFFFFU << ETH_MACVLANTR_VLANTI_Pos) /*!< 0x0000FFFF */ #define ETH_MACVLANTR_VLANTI ETH_MACVLANTR_VLANTI_Msk /* VLAN tag identifier (for receive frames) */ /* Bit definition for Ethernet MAC Remote Wake-UpFrame Filter Register */ #define ETH_MACRWUFFR_D_Pos (0U) #define ETH_MACRWUFFR_D_Msk (0xFFFFFFFFU << ETH_MACRWUFFR_D_Pos) /*!< 0xFFFFFFFF */ #define ETH_MACRWUFFR_D ETH_MACRWUFFR_D_Msk /* Wake-up frame filter register data */ /* Eight sequential Writes to this address (offset 0x28) will write all Wake-UpFrame Filter Registers. Eight sequential Reads from this address (offset 0x28) will read all Wake-UpFrame Filter Registers. */ /* Wake-UpFrame Filter Reg0 : Filter 0 Byte Mask Wake-UpFrame Filter Reg1 : Filter 1 Byte Mask Wake-UpFrame Filter Reg2 : Filter 2 Byte Mask Wake-UpFrame Filter Reg3 : Filter 3 Byte Mask Wake-UpFrame Filter Reg4 : RSVD - Filter3 Command - RSVD - Filter2 Command - RSVD - Filter1 Command - RSVD - Filter0 Command Wake-UpFrame Filter Re5 : Filter3 Offset - Filter2 Offset - Filter1 Offset - Filter0 Offset Wake-UpFrame Filter Re6 : Filter1 CRC16 - Filter0 CRC16 Wake-UpFrame Filter Re7 : Filter3 CRC16 - Filter2 CRC16 */ /* Bit definition for Ethernet MAC PMT Control and Status Register */ #define ETH_MACPMTCSR_WFFRPR_Pos (31U) #define ETH_MACPMTCSR_WFFRPR_Msk (0x1U << ETH_MACPMTCSR_WFFRPR_Pos) /*!< 0x80000000 */ #define ETH_MACPMTCSR_WFFRPR ETH_MACPMTCSR_WFFRPR_Msk /* Wake-Up Frame Filter Register Pointer Reset */ #define ETH_MACPMTCSR_GU_Pos (9U) #define ETH_MACPMTCSR_GU_Msk (0x1U << ETH_MACPMTCSR_GU_Pos) /*!< 0x00000200 */ #define ETH_MACPMTCSR_GU ETH_MACPMTCSR_GU_Msk /* Global Unicast */ #define ETH_MACPMTCSR_WFR_Pos (6U) #define ETH_MACPMTCSR_WFR_Msk (0x1U << ETH_MACPMTCSR_WFR_Pos) /*!< 0x00000040 */ #define ETH_MACPMTCSR_WFR ETH_MACPMTCSR_WFR_Msk /* Wake-Up Frame Received */ #define ETH_MACPMTCSR_MPR_Pos (5U) #define ETH_MACPMTCSR_MPR_Msk (0x1U << ETH_MACPMTCSR_MPR_Pos) /*!< 0x00000020 */ #define ETH_MACPMTCSR_MPR ETH_MACPMTCSR_MPR_Msk /* Magic Packet Received */ #define ETH_MACPMTCSR_WFE_Pos (2U) #define ETH_MACPMTCSR_WFE_Msk (0x1U << ETH_MACPMTCSR_WFE_Pos) /*!< 0x00000004 */ #define ETH_MACPMTCSR_WFE ETH_MACPMTCSR_WFE_Msk /* Wake-Up Frame Enable */ #define ETH_MACPMTCSR_MPE_Pos (1U) #define ETH_MACPMTCSR_MPE_Msk (0x1U << ETH_MACPMTCSR_MPE_Pos) /*!< 0x00000002 */ #define ETH_MACPMTCSR_MPE ETH_MACPMTCSR_MPE_Msk /* Magic Packet Enable */ #define ETH_MACPMTCSR_PD_Pos (0U) #define ETH_MACPMTCSR_PD_Msk (0x1U << ETH_MACPMTCSR_PD_Pos) /*!< 0x00000001 */ #define ETH_MACPMTCSR_PD ETH_MACPMTCSR_PD_Msk /* Power Down */ /* Bit definition for Ethernet MAC debug Register */ #define ETH_MACDBGR_TFF_Pos (25U) #define ETH_MACDBGR_TFF_Msk (0x1U << ETH_MACDBGR_TFF_Pos) /*!< 0x02000000 */ #define ETH_MACDBGR_TFF ETH_MACDBGR_TFF_Msk /* Tx FIFO full */ #define ETH_MACDBGR_TFNE_Pos (24U) #define ETH_MACDBGR_TFNE_Msk (0x1U << ETH_MACDBGR_TFNE_Pos) /*!< 0x01000000 */ #define ETH_MACDBGR_TFNE ETH_MACDBGR_TFNE_Msk /* Tx FIFO not empty */ #define ETH_MACDBGR_TFWA_Pos (22U) #define ETH_MACDBGR_TFWA_Msk (0x1U << ETH_MACDBGR_TFWA_Pos) /*!< 0x00400000 */ #define ETH_MACDBGR_TFWA ETH_MACDBGR_TFWA_Msk /* Tx FIFO write active */ #define ETH_MACDBGR_TFRS_Pos (20U) #define ETH_MACDBGR_TFRS_Msk (0x3U << ETH_MACDBGR_TFRS_Pos) /*!< 0x00300000 */ #define ETH_MACDBGR_TFRS ETH_MACDBGR_TFRS_Msk /* Tx FIFO read status mask */ #define ETH_MACDBGR_TFRS_WRITING_Pos (20U) #define ETH_MACDBGR_TFRS_WRITING_Msk (0x3U << ETH_MACDBGR_TFRS_WRITING_Pos) /*!< 0x00300000 */ #define ETH_MACDBGR_TFRS_WRITING ETH_MACDBGR_TFRS_WRITING_Msk /* Writing the received TxStatus or flushing the TxFIFO */ #define ETH_MACDBGR_TFRS_WAITING_Pos (21U) #define ETH_MACDBGR_TFRS_WAITING_Msk (0x1U << ETH_MACDBGR_TFRS_WAITING_Pos) /*!< 0x00200000 */ #define ETH_MACDBGR_TFRS_WAITING ETH_MACDBGR_TFRS_WAITING_Msk /* Waiting for TxStatus from MAC transmitter */ #define ETH_MACDBGR_TFRS_READ_Pos (20U) #define ETH_MACDBGR_TFRS_READ_Msk (0x1U << ETH_MACDBGR_TFRS_READ_Pos) /*!< 0x00100000 */ #define ETH_MACDBGR_TFRS_READ ETH_MACDBGR_TFRS_READ_Msk /* Read state (transferring data to the MAC transmitter) */ #define ETH_MACDBGR_TFRS_IDLE 0x00000000U /* Idle state */ #define ETH_MACDBGR_MTP_Pos (19U) #define ETH_MACDBGR_MTP_Msk (0x1U << ETH_MACDBGR_MTP_Pos) /*!< 0x00080000 */ #define ETH_MACDBGR_MTP ETH_MACDBGR_MTP_Msk /* MAC transmitter in pause */ #define ETH_MACDBGR_MTFCS_Pos (17U) #define ETH_MACDBGR_MTFCS_Msk (0x3U << ETH_MACDBGR_MTFCS_Pos) /*!< 0x00060000 */ #define ETH_MACDBGR_MTFCS ETH_MACDBGR_MTFCS_Msk /* MAC transmit frame controller status mask */ #define ETH_MACDBGR_MTFCS_TRANSFERRING_Pos (17U) #define ETH_MACDBGR_MTFCS_TRANSFERRING_Msk (0x3U << ETH_MACDBGR_MTFCS_TRANSFERRING_Pos) /*!< 0x00060000 */ #define ETH_MACDBGR_MTFCS_TRANSFERRING ETH_MACDBGR_MTFCS_TRANSFERRING_Msk /* Transferring input frame for transmission */ #define ETH_MACDBGR_MTFCS_GENERATINGPCF_Pos (18U) #define ETH_MACDBGR_MTFCS_GENERATINGPCF_Msk (0x1U << ETH_MACDBGR_MTFCS_GENERATINGPCF_Pos) /*!< 0x00040000 */ #define ETH_MACDBGR_MTFCS_GENERATINGPCF ETH_MACDBGR_MTFCS_GENERATINGPCF_Msk /* Generating and transmitting a Pause control frame (in full duplex mode) */ #define ETH_MACDBGR_MTFCS_WAITING_Pos (17U) #define ETH_MACDBGR_MTFCS_WAITING_Msk (0x1U << ETH_MACDBGR_MTFCS_WAITING_Pos) /*!< 0x00020000 */ #define ETH_MACDBGR_MTFCS_WAITING ETH_MACDBGR_MTFCS_WAITING_Msk /* Waiting for Status of previous frame or IFG/backoff period to be over */ #define ETH_MACDBGR_MTFCS_IDLE 0x00000000U /* Idle */ #define ETH_MACDBGR_MMTEA_Pos (16U) #define ETH_MACDBGR_MMTEA_Msk (0x1U << ETH_MACDBGR_MMTEA_Pos) /*!< 0x00010000 */ #define ETH_MACDBGR_MMTEA ETH_MACDBGR_MMTEA_Msk /* MAC MII transmit engine active */ #define ETH_MACDBGR_RFFL_Pos (8U) #define ETH_MACDBGR_RFFL_Msk (0x3U << ETH_MACDBGR_RFFL_Pos) /*!< 0x00000300 */ #define ETH_MACDBGR_RFFL ETH_MACDBGR_RFFL_Msk /* Rx FIFO fill level mask */ #define ETH_MACDBGR_RFFL_FULL_Pos (8U) #define ETH_MACDBGR_RFFL_FULL_Msk (0x3U << ETH_MACDBGR_RFFL_FULL_Pos) /*!< 0x00000300 */ #define ETH_MACDBGR_RFFL_FULL ETH_MACDBGR_RFFL_FULL_Msk /* RxFIFO full */ #define ETH_MACDBGR_RFFL_ABOVEFCT_Pos (9U) #define ETH_MACDBGR_RFFL_ABOVEFCT_Msk (0x1U << ETH_MACDBGR_RFFL_ABOVEFCT_Pos) /*!< 0x00000200 */ #define ETH_MACDBGR_RFFL_ABOVEFCT ETH_MACDBGR_RFFL_ABOVEFCT_Msk /* RxFIFO fill-level above flow-control activate threshold */ #define ETH_MACDBGR_RFFL_BELOWFCT_Pos (8U) #define ETH_MACDBGR_RFFL_BELOWFCT_Msk (0x1U << ETH_MACDBGR_RFFL_BELOWFCT_Pos) /*!< 0x00000100 */ #define ETH_MACDBGR_RFFL_BELOWFCT ETH_MACDBGR_RFFL_BELOWFCT_Msk /* RxFIFO fill-level below flow-control de-activate threshold */ #define ETH_MACDBGR_RFFL_EMPTY 0x00000000U /* RxFIFO empty */ #define ETH_MACDBGR_RFRCS_Pos (5U) #define ETH_MACDBGR_RFRCS_Msk (0x3U << ETH_MACDBGR_RFRCS_Pos) /*!< 0x00000060 */ #define ETH_MACDBGR_RFRCS ETH_MACDBGR_RFRCS_Msk /* Rx FIFO read controller status mask */ #define ETH_MACDBGR_RFRCS_FLUSHING_Pos (5U) #define ETH_MACDBGR_RFRCS_FLUSHING_Msk (0x3U << ETH_MACDBGR_RFRCS_FLUSHING_Pos) /*!< 0x00000060 */ #define ETH_MACDBGR_RFRCS_FLUSHING ETH_MACDBGR_RFRCS_FLUSHING_Msk /* Flushing the frame data and status */ #define ETH_MACDBGR_RFRCS_STATUSREADING_Pos (6U) #define ETH_MACDBGR_RFRCS_STATUSREADING_Msk (0x1U << ETH_MACDBGR_RFRCS_STATUSREADING_Pos) /*!< 0x00000040 */ #define ETH_MACDBGR_RFRCS_STATUSREADING ETH_MACDBGR_RFRCS_STATUSREADING_Msk /* Reading frame status (or time-stamp) */ #define ETH_MACDBGR_RFRCS_DATAREADING_Pos (5U) #define ETH_MACDBGR_RFRCS_DATAREADING_Msk (0x1U << ETH_MACDBGR_RFRCS_DATAREADING_Pos) /*!< 0x00000020 */ #define ETH_MACDBGR_RFRCS_DATAREADING ETH_MACDBGR_RFRCS_DATAREADING_Msk /* Reading frame data */ #define ETH_MACDBGR_RFRCS_IDLE 0x00000000U /* IDLE state */ #define ETH_MACDBGR_RFWRA_Pos (4U) #define ETH_MACDBGR_RFWRA_Msk (0x1U << ETH_MACDBGR_RFWRA_Pos) /*!< 0x00000010 */ #define ETH_MACDBGR_RFWRA ETH_MACDBGR_RFWRA_Msk /* Rx FIFO write controller active */ #define ETH_MACDBGR_MSFRWCS_Pos (1U) #define ETH_MACDBGR_MSFRWCS_Msk (0x3U << ETH_MACDBGR_MSFRWCS_Pos) /*!< 0x00000006 */ #define ETH_MACDBGR_MSFRWCS ETH_MACDBGR_MSFRWCS_Msk /* MAC small FIFO read / write controllers status mask */ #define ETH_MACDBGR_MSFRWCS_1 (0x2U << ETH_MACDBGR_MSFRWCS_Pos) /*!< 0x00000004 */ #define ETH_MACDBGR_MSFRWCS_0 (0x1U << ETH_MACDBGR_MSFRWCS_Pos) /*!< 0x00000002 */ #define ETH_MACDBGR_MMRPEA_Pos (0U) #define ETH_MACDBGR_MMRPEA_Msk (0x1U << ETH_MACDBGR_MMRPEA_Pos) /*!< 0x00000001 */ #define ETH_MACDBGR_MMRPEA ETH_MACDBGR_MMRPEA_Msk /* MAC MII receive protocol engine active */ /* Bit definition for Ethernet MAC Status Register */ #define ETH_MACSR_TSTS_Pos (9U) #define ETH_MACSR_TSTS_Msk (0x1U << ETH_MACSR_TSTS_Pos) /*!< 0x00000200 */ #define ETH_MACSR_TSTS ETH_MACSR_TSTS_Msk /* Time stamp trigger status */ #define ETH_MACSR_MMCTS_Pos (6U) #define ETH_MACSR_MMCTS_Msk (0x1U << ETH_MACSR_MMCTS_Pos) /*!< 0x00000040 */ #define ETH_MACSR_MMCTS ETH_MACSR_MMCTS_Msk /* MMC transmit status */ #define ETH_MACSR_MMMCRS_Pos (5U) #define ETH_MACSR_MMMCRS_Msk (0x1U << ETH_MACSR_MMMCRS_Pos) /*!< 0x00000020 */ #define ETH_MACSR_MMMCRS ETH_MACSR_MMMCRS_Msk /* MMC receive status */ #define ETH_MACSR_MMCS_Pos (4U) #define ETH_MACSR_MMCS_Msk (0x1U << ETH_MACSR_MMCS_Pos) /*!< 0x00000010 */ #define ETH_MACSR_MMCS ETH_MACSR_MMCS_Msk /* MMC status */ #define ETH_MACSR_PMTS_Pos (3U) #define ETH_MACSR_PMTS_Msk (0x1U << ETH_MACSR_PMTS_Pos) /*!< 0x00000008 */ #define ETH_MACSR_PMTS ETH_MACSR_PMTS_Msk /* PMT status */ /* Bit definition for Ethernet MAC Interrupt Mask Register */ #define ETH_MACIMR_TSTIM_Pos (9U) #define ETH_MACIMR_TSTIM_Msk (0x1U << ETH_MACIMR_TSTIM_Pos) /*!< 0x00000200 */ #define ETH_MACIMR_TSTIM ETH_MACIMR_TSTIM_Msk /* Time stamp trigger interrupt mask */ #define ETH_MACIMR_PMTIM_Pos (3U) #define ETH_MACIMR_PMTIM_Msk (0x1U << ETH_MACIMR_PMTIM_Pos) /*!< 0x00000008 */ #define ETH_MACIMR_PMTIM ETH_MACIMR_PMTIM_Msk /* PMT interrupt mask */ /* Bit definition for Ethernet MAC Address0 High Register */ #define ETH_MACA0HR_MACA0H_Pos (0U) #define ETH_MACA0HR_MACA0H_Msk (0xFFFFU << ETH_MACA0HR_MACA0H_Pos) /*!< 0x0000FFFF */ #define ETH_MACA0HR_MACA0H ETH_MACA0HR_MACA0H_Msk /* MAC address0 high */ /* Bit definition for Ethernet MAC Address0 Low Register */ #define ETH_MACA0LR_MACA0L_Pos (0U) #define ETH_MACA0LR_MACA0L_Msk (0xFFFFFFFFU << ETH_MACA0LR_MACA0L_Pos) /*!< 0xFFFFFFFF */ #define ETH_MACA0LR_MACA0L ETH_MACA0LR_MACA0L_Msk /* MAC address0 low */ /* Bit definition for Ethernet MAC Address1 High Register */ #define ETH_MACA1HR_AE_Pos (31U) #define ETH_MACA1HR_AE_Msk (0x1U << ETH_MACA1HR_AE_Pos) /*!< 0x80000000 */ #define ETH_MACA1HR_AE ETH_MACA1HR_AE_Msk /* Address enable */ #define ETH_MACA1HR_SA_Pos (30U) #define ETH_MACA1HR_SA_Msk (0x1U << ETH_MACA1HR_SA_Pos) /*!< 0x40000000 */ #define ETH_MACA1HR_SA ETH_MACA1HR_SA_Msk /* Source address */ #define ETH_MACA1HR_MBC_Pos (24U) #define ETH_MACA1HR_MBC_Msk (0x3FU << ETH_MACA1HR_MBC_Pos) /*!< 0x3F000000 */ #define ETH_MACA1HR_MBC ETH_MACA1HR_MBC_Msk /* Mask byte control: bits to mask for comparison of the MAC Address bytes */ #define ETH_MACA1HR_MBC_HBits15_8 0x20000000U /* Mask MAC Address high reg bits [15:8] */ #define ETH_MACA1HR_MBC_HBits7_0 0x10000000U /* Mask MAC Address high reg bits [7:0] */ #define ETH_MACA1HR_MBC_LBits31_24 0x08000000U /* Mask MAC Address low reg bits [31:24] */ #define ETH_MACA1HR_MBC_LBits23_16 0x04000000U /* Mask MAC Address low reg bits [23:16] */ #define ETH_MACA1HR_MBC_LBits15_8 0x02000000U /* Mask MAC Address low reg bits [15:8] */ #define ETH_MACA1HR_MBC_LBits7_0 0x01000000U /* Mask MAC Address low reg bits [7:0] */ #define ETH_MACA1HR_MACA1H_Pos (0U) #define ETH_MACA1HR_MACA1H_Msk (0xFFFFU << ETH_MACA1HR_MACA1H_Pos) /*!< 0x0000FFFF */ #define ETH_MACA1HR_MACA1H ETH_MACA1HR_MACA1H_Msk /* MAC address1 high */ /* Bit definition for Ethernet MAC Address1 Low Register */ #define ETH_MACA1LR_MACA1L_Pos (0U) #define ETH_MACA1LR_MACA1L_Msk (0xFFFFFFFFU << ETH_MACA1LR_MACA1L_Pos) /*!< 0xFFFFFFFF */ #define ETH_MACA1LR_MACA1L ETH_MACA1LR_MACA1L_Msk /* MAC address1 low */ /* Bit definition for Ethernet MAC Address2 High Register */ #define ETH_MACA2HR_AE_Pos (31U) #define ETH_MACA2HR_AE_Msk (0x1U << ETH_MACA2HR_AE_Pos) /*!< 0x80000000 */ #define ETH_MACA2HR_AE ETH_MACA2HR_AE_Msk /* Address enable */ #define ETH_MACA2HR_SA_Pos (30U) #define ETH_MACA2HR_SA_Msk (0x1U << ETH_MACA2HR_SA_Pos) /*!< 0x40000000 */ #define ETH_MACA2HR_SA ETH_MACA2HR_SA_Msk /* Source address */ #define ETH_MACA2HR_MBC_Pos (24U) #define ETH_MACA2HR_MBC_Msk (0x3FU << ETH_MACA2HR_MBC_Pos) /*!< 0x3F000000 */ #define ETH_MACA2HR_MBC ETH_MACA2HR_MBC_Msk /* Mask byte control */ #define ETH_MACA2HR_MBC_HBits15_8 0x20000000U /* Mask MAC Address high reg bits [15:8] */ #define ETH_MACA2HR_MBC_HBits7_0 0x10000000U /* Mask MAC Address high reg bits [7:0] */ #define ETH_MACA2HR_MBC_LBits31_24 0x08000000U /* Mask MAC Address low reg bits [31:24] */ #define ETH_MACA2HR_MBC_LBits23_16 0x04000000U /* Mask MAC Address low reg bits [23:16] */ #define ETH_MACA2HR_MBC_LBits15_8 0x02000000U /* Mask MAC Address low reg bits [15:8] */ #define ETH_MACA2HR_MBC_LBits7_0 0x01000000U /* Mask MAC Address low reg bits [70] */ #define ETH_MACA2HR_MACA2H_Pos (0U) #define ETH_MACA2HR_MACA2H_Msk (0xFFFFU << ETH_MACA2HR_MACA2H_Pos) /*!< 0x0000FFFF */ #define ETH_MACA2HR_MACA2H ETH_MACA2HR_MACA2H_Msk /* MAC address1 high */ /* Bit definition for Ethernet MAC Address2 Low Register */ #define ETH_MACA2LR_MACA2L_Pos (0U) #define ETH_MACA2LR_MACA2L_Msk (0xFFFFFFFFU << ETH_MACA2LR_MACA2L_Pos) /*!< 0xFFFFFFFF */ #define ETH_MACA2LR_MACA2L ETH_MACA2LR_MACA2L_Msk /* MAC address2 low */ /* Bit definition for Ethernet MAC Address3 High Register */ #define ETH_MACA3HR_AE_Pos (31U) #define ETH_MACA3HR_AE_Msk (0x1U << ETH_MACA3HR_AE_Pos) /*!< 0x80000000 */ #define ETH_MACA3HR_AE ETH_MACA3HR_AE_Msk /* Address enable */ #define ETH_MACA3HR_SA_Pos (30U) #define ETH_MACA3HR_SA_Msk (0x1U << ETH_MACA3HR_SA_Pos) /*!< 0x40000000 */ #define ETH_MACA3HR_SA ETH_MACA3HR_SA_Msk /* Source address */ #define ETH_MACA3HR_MBC_Pos (24U) #define ETH_MACA3HR_MBC_Msk (0x3FU << ETH_MACA3HR_MBC_Pos) /*!< 0x3F000000 */ #define ETH_MACA3HR_MBC ETH_MACA3HR_MBC_Msk /* Mask byte control */ #define ETH_MACA3HR_MBC_HBits15_8 0x20000000U /* Mask MAC Address high reg bits [15:8] */ #define ETH_MACA3HR_MBC_HBits7_0 0x10000000U /* Mask MAC Address high reg bits [7:0] */ #define ETH_MACA3HR_MBC_LBits31_24 0x08000000U /* Mask MAC Address low reg bits [31:24] */ #define ETH_MACA3HR_MBC_LBits23_16 0x04000000U /* Mask MAC Address low reg bits [23:16] */ #define ETH_MACA3HR_MBC_LBits15_8 0x02000000U /* Mask MAC Address low reg bits [15:8] */ #define ETH_MACA3HR_MBC_LBits7_0 0x01000000U /* Mask MAC Address low reg bits [70] */ #define ETH_MACA3HR_MACA3H_Pos (0U) #define ETH_MACA3HR_MACA3H_Msk (0xFFFFU << ETH_MACA3HR_MACA3H_Pos) /*!< 0x0000FFFF */ #define ETH_MACA3HR_MACA3H ETH_MACA3HR_MACA3H_Msk /* MAC address3 high */ /* Bit definition for Ethernet MAC Address3 Low Register */ #define ETH_MACA3LR_MACA3L_Pos (0U) #define ETH_MACA3LR_MACA3L_Msk (0xFFFFFFFFU << ETH_MACA3LR_MACA3L_Pos) /*!< 0xFFFFFFFF */ #define ETH_MACA3LR_MACA3L ETH_MACA3LR_MACA3L_Msk /* MAC address3 low */ /******************************************************************************/ /* Ethernet MMC Registers bits definition */ /******************************************************************************/ /* Bit definition for Ethernet MMC Contol Register */ #define ETH_MMCCR_MCFHP_Pos (5U) #define ETH_MMCCR_MCFHP_Msk (0x1U << ETH_MMCCR_MCFHP_Pos) /*!< 0x00000020 */ #define ETH_MMCCR_MCFHP ETH_MMCCR_MCFHP_Msk /* MMC counter Full-Half preset */ #define ETH_MMCCR_MCP_Pos (4U) #define ETH_MMCCR_MCP_Msk (0x1U << ETH_MMCCR_MCP_Pos) /*!< 0x00000010 */ #define ETH_MMCCR_MCP ETH_MMCCR_MCP_Msk /* MMC counter preset */ #define ETH_MMCCR_MCF_Pos (3U) #define ETH_MMCCR_MCF_Msk (0x1U << ETH_MMCCR_MCF_Pos) /*!< 0x00000008 */ #define ETH_MMCCR_MCF ETH_MMCCR_MCF_Msk /* MMC Counter Freeze */ #define ETH_MMCCR_ROR_Pos (2U) #define ETH_MMCCR_ROR_Msk (0x1U << ETH_MMCCR_ROR_Pos) /*!< 0x00000004 */ #define ETH_MMCCR_ROR ETH_MMCCR_ROR_Msk /* Reset on Read */ #define ETH_MMCCR_CSR_Pos (1U) #define ETH_MMCCR_CSR_Msk (0x1U << ETH_MMCCR_CSR_Pos) /*!< 0x00000002 */ #define ETH_MMCCR_CSR ETH_MMCCR_CSR_Msk /* Counter Stop Rollover */ #define ETH_MMCCR_CR_Pos (0U) #define ETH_MMCCR_CR_Msk (0x1U << ETH_MMCCR_CR_Pos) /*!< 0x00000001 */ #define ETH_MMCCR_CR ETH_MMCCR_CR_Msk /* Counters Reset */ /* Bit definition for Ethernet MMC Receive Interrupt Register */ #define ETH_MMCRIR_RGUFS_Pos (17U) #define ETH_MMCRIR_RGUFS_Msk (0x1U << ETH_MMCRIR_RGUFS_Pos) /*!< 0x00020000 */ #define ETH_MMCRIR_RGUFS ETH_MMCRIR_RGUFS_Msk /* Set when Rx good unicast frames counter reaches half the maximum value */ #define ETH_MMCRIR_RFAES_Pos (6U) #define ETH_MMCRIR_RFAES_Msk (0x1U << ETH_MMCRIR_RFAES_Pos) /*!< 0x00000040 */ #define ETH_MMCRIR_RFAES ETH_MMCRIR_RFAES_Msk /* Set when Rx alignment error counter reaches half the maximum value */ #define ETH_MMCRIR_RFCES_Pos (5U) #define ETH_MMCRIR_RFCES_Msk (0x1U << ETH_MMCRIR_RFCES_Pos) /*!< 0x00000020 */ #define ETH_MMCRIR_RFCES ETH_MMCRIR_RFCES_Msk /* Set when Rx crc error counter reaches half the maximum value */ /* Bit definition for Ethernet MMC Transmit Interrupt Register */ #define ETH_MMCTIR_TGFS_Pos (21U) #define ETH_MMCTIR_TGFS_Msk (0x1U << ETH_MMCTIR_TGFS_Pos) /*!< 0x00200000 */ #define ETH_MMCTIR_TGFS ETH_MMCTIR_TGFS_Msk /* Set when Tx good frame count counter reaches half the maximum value */ #define ETH_MMCTIR_TGFMSCS_Pos (15U) #define ETH_MMCTIR_TGFMSCS_Msk (0x1U << ETH_MMCTIR_TGFMSCS_Pos) /*!< 0x00008000 */ #define ETH_MMCTIR_TGFMSCS ETH_MMCTIR_TGFMSCS_Msk /* Set when Tx good multi col counter reaches half the maximum value */ #define ETH_MMCTIR_TGFSCS_Pos (14U) #define ETH_MMCTIR_TGFSCS_Msk (0x1U << ETH_MMCTIR_TGFSCS_Pos) /*!< 0x00004000 */ #define ETH_MMCTIR_TGFSCS ETH_MMCTIR_TGFSCS_Msk /* Set when Tx good single col counter reaches half the maximum value */ /* Bit definition for Ethernet MMC Receive Interrupt Mask Register */ #define ETH_MMCRIMR_RGUFM_Pos (17U) #define ETH_MMCRIMR_RGUFM_Msk (0x1U << ETH_MMCRIMR_RGUFM_Pos) /*!< 0x00020000 */ #define ETH_MMCRIMR_RGUFM ETH_MMCRIMR_RGUFM_Msk /* Mask the interrupt when Rx good unicast frames counter reaches half the maximum value */ #define ETH_MMCRIMR_RFAEM_Pos (6U) #define ETH_MMCRIMR_RFAEM_Msk (0x1U << ETH_MMCRIMR_RFAEM_Pos) /*!< 0x00000040 */ #define ETH_MMCRIMR_RFAEM ETH_MMCRIMR_RFAEM_Msk /* Mask the interrupt when when Rx alignment error counter reaches half the maximum value */ #define ETH_MMCRIMR_RFCEM_Pos (5U) #define ETH_MMCRIMR_RFCEM_Msk (0x1U << ETH_MMCRIMR_RFCEM_Pos) /*!< 0x00000020 */ #define ETH_MMCRIMR_RFCEM ETH_MMCRIMR_RFCEM_Msk /* Mask the interrupt when Rx crc error counter reaches half the maximum value */ /* Bit definition for Ethernet MMC Transmit Interrupt Mask Register */ #define ETH_MMCTIMR_TGFM_Pos (21U) #define ETH_MMCTIMR_TGFM_Msk (0x1U << ETH_MMCTIMR_TGFM_Pos) /*!< 0x00200000 */ #define ETH_MMCTIMR_TGFM ETH_MMCTIMR_TGFM_Msk /* Mask the interrupt when Tx good frame count counter reaches half the maximum value */ #define ETH_MMCTIMR_TGFMSCM_Pos (15U) #define ETH_MMCTIMR_TGFMSCM_Msk (0x1U << ETH_MMCTIMR_TGFMSCM_Pos) /*!< 0x00008000 */ #define ETH_MMCTIMR_TGFMSCM ETH_MMCTIMR_TGFMSCM_Msk /* Mask the interrupt when Tx good multi col counter reaches half the maximum value */ #define ETH_MMCTIMR_TGFSCM_Pos (14U) #define ETH_MMCTIMR_TGFSCM_Msk (0x1U << ETH_MMCTIMR_TGFSCM_Pos) /*!< 0x00004000 */ #define ETH_MMCTIMR_TGFSCM ETH_MMCTIMR_TGFSCM_Msk /* Mask the interrupt when Tx good single col counter reaches half the maximum value */ /* Bit definition for Ethernet MMC Transmitted Good Frames after Single Collision Counter Register */ #define ETH_MMCTGFSCCR_TGFSCC_Pos (0U) #define ETH_MMCTGFSCCR_TGFSCC_Msk (0xFFFFFFFFU << ETH_MMCTGFSCCR_TGFSCC_Pos) /*!< 0xFFFFFFFF */ #define ETH_MMCTGFSCCR_TGFSCC ETH_MMCTGFSCCR_TGFSCC_Msk /* Number of successfully transmitted frames after a single collision in Half-duplex mode. */ /* Bit definition for Ethernet MMC Transmitted Good Frames after More than a Single Collision Counter Register */ #define ETH_MMCTGFMSCCR_TGFMSCC_Pos (0U) #define ETH_MMCTGFMSCCR_TGFMSCC_Msk (0xFFFFFFFFU << ETH_MMCTGFMSCCR_TGFMSCC_Pos) /*!< 0xFFFFFFFF */ #define ETH_MMCTGFMSCCR_TGFMSCC ETH_MMCTGFMSCCR_TGFMSCC_Msk /* Number of successfully transmitted frames after more than a single collision in Half-duplex mode. */ /* Bit definition for Ethernet MMC Transmitted Good Frames Counter Register */ #define ETH_MMCTGFCR_TGFC_Pos (0U) #define ETH_MMCTGFCR_TGFC_Msk (0xFFFFFFFFU << ETH_MMCTGFCR_TGFC_Pos) /*!< 0xFFFFFFFF */ #define ETH_MMCTGFCR_TGFC ETH_MMCTGFCR_TGFC_Msk /* Number of good frames transmitted. */ /* Bit definition for Ethernet MMC Received Frames with CRC Error Counter Register */ #define ETH_MMCRFCECR_RFCEC_Pos (0U) #define ETH_MMCRFCECR_RFCEC_Msk (0xFFFFFFFFU << ETH_MMCRFCECR_RFCEC_Pos) /*!< 0xFFFFFFFF */ #define ETH_MMCRFCECR_RFCEC ETH_MMCRFCECR_RFCEC_Msk /* Number of frames received with CRC error. */ /* Bit definition for Ethernet MMC Received Frames with Alignement Error Counter Register */ #define ETH_MMCRFAECR_RFAEC_Pos (0U) #define ETH_MMCRFAECR_RFAEC_Msk (0xFFFFFFFFU << ETH_MMCRFAECR_RFAEC_Pos) /*!< 0xFFFFFFFF */ #define ETH_MMCRFAECR_RFAEC ETH_MMCRFAECR_RFAEC_Msk /* Number of frames received with alignment (dribble) error */ /* Bit definition for Ethernet MMC Received Good Unicast Frames Counter Register */ #define ETH_MMCRGUFCR_RGUFC_Pos (0U) #define ETH_MMCRGUFCR_RGUFC_Msk (0xFFFFFFFFU << ETH_MMCRGUFCR_RGUFC_Pos) /*!< 0xFFFFFFFF */ #define ETH_MMCRGUFCR_RGUFC ETH_MMCRGUFCR_RGUFC_Msk /* Number of good unicast frames received. */ /******************************************************************************/ /* Ethernet PTP Registers bits definition */ /******************************************************************************/ /* Bit definition for Ethernet PTP Time Stamp Contol Register */ #define ETH_PTPTSCR_TSCNT_Pos (16U) #define ETH_PTPTSCR_TSCNT_Msk (0x3U << ETH_PTPTSCR_TSCNT_Pos) /*!< 0x00030000 */ #define ETH_PTPTSCR_TSCNT ETH_PTPTSCR_TSCNT_Msk /* Time stamp clock node type */ #define ETH_PTPTSSR_TSSMRME_Pos (15U) #define ETH_PTPTSSR_TSSMRME_Msk (0x1U << ETH_PTPTSSR_TSSMRME_Pos) /*!< 0x00008000 */ #define ETH_PTPTSSR_TSSMRME ETH_PTPTSSR_TSSMRME_Msk /* Time stamp snapshot for message relevant to master enable */ #define ETH_PTPTSSR_TSSEME_Pos (14U) #define ETH_PTPTSSR_TSSEME_Msk (0x1U << ETH_PTPTSSR_TSSEME_Pos) /*!< 0x00004000 */ #define ETH_PTPTSSR_TSSEME ETH_PTPTSSR_TSSEME_Msk /* Time stamp snapshot for event message enable */ #define ETH_PTPTSSR_TSSIPV4FE_Pos (13U) #define ETH_PTPTSSR_TSSIPV4FE_Msk (0x1U << ETH_PTPTSSR_TSSIPV4FE_Pos) /*!< 0x00002000 */ #define ETH_PTPTSSR_TSSIPV4FE ETH_PTPTSSR_TSSIPV4FE_Msk /* Time stamp snapshot for IPv4 frames enable */ #define ETH_PTPTSSR_TSSIPV6FE_Pos (12U) #define ETH_PTPTSSR_TSSIPV6FE_Msk (0x1U << ETH_PTPTSSR_TSSIPV6FE_Pos) /*!< 0x00001000 */ #define ETH_PTPTSSR_TSSIPV6FE ETH_PTPTSSR_TSSIPV6FE_Msk /* Time stamp snapshot for IPv6 frames enable */ #define ETH_PTPTSSR_TSSPTPOEFE_Pos (11U) #define ETH_PTPTSSR_TSSPTPOEFE_Msk (0x1U << ETH_PTPTSSR_TSSPTPOEFE_Pos) /*!< 0x00000800 */ #define ETH_PTPTSSR_TSSPTPOEFE ETH_PTPTSSR_TSSPTPOEFE_Msk /* Time stamp snapshot for PTP over ethernet frames enable */ #define ETH_PTPTSSR_TSPTPPSV2E_Pos (10U) #define ETH_PTPTSSR_TSPTPPSV2E_Msk (0x1U << ETH_PTPTSSR_TSPTPPSV2E_Pos) /*!< 0x00000400 */ #define ETH_PTPTSSR_TSPTPPSV2E ETH_PTPTSSR_TSPTPPSV2E_Msk /* Time stamp PTP packet snooping for version2 format enable */ #define ETH_PTPTSSR_TSSSR_Pos (9U) #define ETH_PTPTSSR_TSSSR_Msk (0x1U << ETH_PTPTSSR_TSSSR_Pos) /*!< 0x00000200 */ #define ETH_PTPTSSR_TSSSR ETH_PTPTSSR_TSSSR_Msk /* Time stamp Sub-seconds rollover */ #define ETH_PTPTSSR_TSSARFE_Pos (8U) #define ETH_PTPTSSR_TSSARFE_Msk (0x1U << ETH_PTPTSSR_TSSARFE_Pos) /*!< 0x00000100 */ #define ETH_PTPTSSR_TSSARFE ETH_PTPTSSR_TSSARFE_Msk /* Time stamp snapshot for all received frames enable */ #define ETH_PTPTSCR_TSARU_Pos (5U) #define ETH_PTPTSCR_TSARU_Msk (0x1U << ETH_PTPTSCR_TSARU_Pos) /*!< 0x00000020 */ #define ETH_PTPTSCR_TSARU ETH_PTPTSCR_TSARU_Msk /* Addend register update */ #define ETH_PTPTSCR_TSITE_Pos (4U) #define ETH_PTPTSCR_TSITE_Msk (0x1U << ETH_PTPTSCR_TSITE_Pos) /*!< 0x00000010 */ #define ETH_PTPTSCR_TSITE ETH_PTPTSCR_TSITE_Msk /* Time stamp interrupt trigger enable */ #define ETH_PTPTSCR_TSSTU_Pos (3U) #define ETH_PTPTSCR_TSSTU_Msk (0x1U << ETH_PTPTSCR_TSSTU_Pos) /*!< 0x00000008 */ #define ETH_PTPTSCR_TSSTU ETH_PTPTSCR_TSSTU_Msk /* Time stamp update */ #define ETH_PTPTSCR_TSSTI_Pos (2U) #define ETH_PTPTSCR_TSSTI_Msk (0x1U << ETH_PTPTSCR_TSSTI_Pos) /*!< 0x00000004 */ #define ETH_PTPTSCR_TSSTI ETH_PTPTSCR_TSSTI_Msk /* Time stamp initialize */ #define ETH_PTPTSCR_TSFCU_Pos (1U) #define ETH_PTPTSCR_TSFCU_Msk (0x1U << ETH_PTPTSCR_TSFCU_Pos) /*!< 0x00000002 */ #define ETH_PTPTSCR_TSFCU ETH_PTPTSCR_TSFCU_Msk /* Time stamp fine or coarse update */ #define ETH_PTPTSCR_TSE_Pos (0U) #define ETH_PTPTSCR_TSE_Msk (0x1U << ETH_PTPTSCR_TSE_Pos) /*!< 0x00000001 */ #define ETH_PTPTSCR_TSE ETH_PTPTSCR_TSE_Msk /* Time stamp enable */ /* Bit definition for Ethernet PTP Sub-Second Increment Register */ #define ETH_PTPSSIR_STSSI_Pos (0U) #define ETH_PTPSSIR_STSSI_Msk (0xFFU << ETH_PTPSSIR_STSSI_Pos) /*!< 0x000000FF */ #define ETH_PTPSSIR_STSSI ETH_PTPSSIR_STSSI_Msk /* System time Sub-second increment value */ /* Bit definition for Ethernet PTP Time Stamp High Register */ #define ETH_PTPTSHR_STS_Pos (0U) #define ETH_PTPTSHR_STS_Msk (0xFFFFFFFFU << ETH_PTPTSHR_STS_Pos) /*!< 0xFFFFFFFF */ #define ETH_PTPTSHR_STS ETH_PTPTSHR_STS_Msk /* System Time second */ /* Bit definition for Ethernet PTP Time Stamp Low Register */ #define ETH_PTPTSLR_STPNS_Pos (31U) #define ETH_PTPTSLR_STPNS_Msk (0x1U << ETH_PTPTSLR_STPNS_Pos) /*!< 0x80000000 */ #define ETH_PTPTSLR_STPNS ETH_PTPTSLR_STPNS_Msk /* System Time Positive or negative time */ #define ETH_PTPTSLR_STSS_Pos (0U) #define ETH_PTPTSLR_STSS_Msk (0x7FFFFFFFU << ETH_PTPTSLR_STSS_Pos) /*!< 0x7FFFFFFF */ #define ETH_PTPTSLR_STSS ETH_PTPTSLR_STSS_Msk /* System Time sub-seconds */ /* Bit definition for Ethernet PTP Time Stamp High Update Register */ #define ETH_PTPTSHUR_TSUS_Pos (0U) #define ETH_PTPTSHUR_TSUS_Msk (0xFFFFFFFFU << ETH_PTPTSHUR_TSUS_Pos) /*!< 0xFFFFFFFF */ #define ETH_PTPTSHUR_TSUS ETH_PTPTSHUR_TSUS_Msk /* Time stamp update seconds */ /* Bit definition for Ethernet PTP Time Stamp Low Update Register */ #define ETH_PTPTSLUR_TSUPNS_Pos (31U) #define ETH_PTPTSLUR_TSUPNS_Msk (0x1U << ETH_PTPTSLUR_TSUPNS_Pos) /*!< 0x80000000 */ #define ETH_PTPTSLUR_TSUPNS ETH_PTPTSLUR_TSUPNS_Msk /* Time stamp update Positive or negative time */ #define ETH_PTPTSLUR_TSUSS_Pos (0U) #define ETH_PTPTSLUR_TSUSS_Msk (0x7FFFFFFFU << ETH_PTPTSLUR_TSUSS_Pos) /*!< 0x7FFFFFFF */ #define ETH_PTPTSLUR_TSUSS ETH_PTPTSLUR_TSUSS_Msk /* Time stamp update sub-seconds */ /* Bit definition for Ethernet PTP Time Stamp Addend Register */ #define ETH_PTPTSAR_TSA_Pos (0U) #define ETH_PTPTSAR_TSA_Msk (0xFFFFFFFFU << ETH_PTPTSAR_TSA_Pos) /*!< 0xFFFFFFFF */ #define ETH_PTPTSAR_TSA ETH_PTPTSAR_TSA_Msk /* Time stamp addend */ /* Bit definition for Ethernet PTP Target Time High Register */ #define ETH_PTPTTHR_TTSH_Pos (0U) #define ETH_PTPTTHR_TTSH_Msk (0xFFFFFFFFU << ETH_PTPTTHR_TTSH_Pos) /*!< 0xFFFFFFFF */ #define ETH_PTPTTHR_TTSH ETH_PTPTTHR_TTSH_Msk /* Target time stamp high */ /* Bit definition for Ethernet PTP Target Time Low Register */ #define ETH_PTPTTLR_TTSL_Pos (0U) #define ETH_PTPTTLR_TTSL_Msk (0xFFFFFFFFU << ETH_PTPTTLR_TTSL_Pos) /*!< 0xFFFFFFFF */ #define ETH_PTPTTLR_TTSL ETH_PTPTTLR_TTSL_Msk /* Target time stamp low */ /* Bit definition for Ethernet PTP Time Stamp Status Register */ #define ETH_PTPTSSR_TSTTR_Pos (5U) #define ETH_PTPTSSR_TSTTR_Msk (0x1U << ETH_PTPTSSR_TSTTR_Pos) /*!< 0x00000020 */ #define ETH_PTPTSSR_TSTTR ETH_PTPTSSR_TSTTR_Msk /* Time stamp target time reached */ #define ETH_PTPTSSR_TSSO_Pos (4U) #define ETH_PTPTSSR_TSSO_Msk (0x1U << ETH_PTPTSSR_TSSO_Pos) /*!< 0x00000010 */ #define ETH_PTPTSSR_TSSO ETH_PTPTSSR_TSSO_Msk /* Time stamp seconds overflow */ /******************************************************************************/ /* Ethernet DMA Registers bits definition */ /******************************************************************************/ /* Bit definition for Ethernet DMA Bus Mode Register */ #define ETH_DMABMR_AAB_Pos (25U) #define ETH_DMABMR_AAB_Msk (0x1U << ETH_DMABMR_AAB_Pos) /*!< 0x02000000 */ #define ETH_DMABMR_AAB ETH_DMABMR_AAB_Msk /* Address-Aligned beats */ #define ETH_DMABMR_FPM_Pos (24U) #define ETH_DMABMR_FPM_Msk (0x1U << ETH_DMABMR_FPM_Pos) /*!< 0x01000000 */ #define ETH_DMABMR_FPM ETH_DMABMR_FPM_Msk /* 4xPBL mode */ #define ETH_DMABMR_USP_Pos (23U) #define ETH_DMABMR_USP_Msk (0x1U << ETH_DMABMR_USP_Pos) /*!< 0x00800000 */ #define ETH_DMABMR_USP ETH_DMABMR_USP_Msk /* Use separate PBL */ #define ETH_DMABMR_RDP_Pos (17U) #define ETH_DMABMR_RDP_Msk (0x3FU << ETH_DMABMR_RDP_Pos) /*!< 0x007E0000 */ #define ETH_DMABMR_RDP ETH_DMABMR_RDP_Msk /* RxDMA PBL */ #define ETH_DMABMR_RDP_1Beat 0x00020000U /* maximum number of beats to be transferred in one RxDMA transaction is 1 */ #define ETH_DMABMR_RDP_2Beat 0x00040000U /* maximum number of beats to be transferred in one RxDMA transaction is 2 */ #define ETH_DMABMR_RDP_4Beat 0x00080000U /* maximum number of beats to be transferred in one RxDMA transaction is 4 */ #define ETH_DMABMR_RDP_8Beat 0x00100000U /* maximum number of beats to be transferred in one RxDMA transaction is 8 */ #define ETH_DMABMR_RDP_16Beat 0x00200000U /* maximum number of beats to be transferred in one RxDMA transaction is 16 */ #define ETH_DMABMR_RDP_32Beat 0x00400000U /* maximum number of beats to be transferred in one RxDMA transaction is 32 */ #define ETH_DMABMR_RDP_4xPBL_4Beat 0x01020000U /* maximum number of beats to be transferred in one RxDMA transaction is 4 */ #define ETH_DMABMR_RDP_4xPBL_8Beat 0x01040000U /* maximum number of beats to be transferred in one RxDMA transaction is 8 */ #define ETH_DMABMR_RDP_4xPBL_16Beat 0x01080000U /* maximum number of beats to be transferred in one RxDMA transaction is 16 */ #define ETH_DMABMR_RDP_4xPBL_32Beat 0x01100000U /* maximum number of beats to be transferred in one RxDMA transaction is 32 */ #define ETH_DMABMR_RDP_4xPBL_64Beat 0x01200000U /* maximum number of beats to be transferred in one RxDMA transaction is 64 */ #define ETH_DMABMR_RDP_4xPBL_128Beat 0x01400000U /* maximum number of beats to be transferred in one RxDMA transaction is 128 */ #define ETH_DMABMR_FB_Pos (16U) #define ETH_DMABMR_FB_Msk (0x1U << ETH_DMABMR_FB_Pos) /*!< 0x00010000 */ #define ETH_DMABMR_FB ETH_DMABMR_FB_Msk /* Fixed Burst */ #define ETH_DMABMR_RTPR_Pos (14U) #define ETH_DMABMR_RTPR_Msk (0x3U << ETH_DMABMR_RTPR_Pos) /*!< 0x0000C000 */ #define ETH_DMABMR_RTPR ETH_DMABMR_RTPR_Msk /* Rx Tx priority ratio */ #define ETH_DMABMR_RTPR_1_1 0x00000000U /* Rx Tx priority ratio */ #define ETH_DMABMR_RTPR_2_1 0x00004000U /* Rx Tx priority ratio */ #define ETH_DMABMR_RTPR_3_1 0x00008000U /* Rx Tx priority ratio */ #define ETH_DMABMR_RTPR_4_1 0x0000C000U /* Rx Tx priority ratio */ #define ETH_DMABMR_PBL_Pos (8U) #define ETH_DMABMR_PBL_Msk (0x3FU << ETH_DMABMR_PBL_Pos) /*!< 0x00003F00 */ #define ETH_DMABMR_PBL ETH_DMABMR_PBL_Msk /* Programmable burst length */ #define ETH_DMABMR_PBL_1Beat 0x00000100U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */ #define ETH_DMABMR_PBL_2Beat 0x00000200U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */ #define ETH_DMABMR_PBL_4Beat 0x00000400U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */ #define ETH_DMABMR_PBL_8Beat 0x00000800U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */ #define ETH_DMABMR_PBL_16Beat 0x00001000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */ #define ETH_DMABMR_PBL_32Beat 0x00002000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */ #define ETH_DMABMR_PBL_4xPBL_4Beat 0x01000100U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */ #define ETH_DMABMR_PBL_4xPBL_8Beat 0x01000200U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */ #define ETH_DMABMR_PBL_4xPBL_16Beat 0x01000400U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */ #define ETH_DMABMR_PBL_4xPBL_32Beat 0x01000800U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */ #define ETH_DMABMR_PBL_4xPBL_64Beat 0x01001000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */ #define ETH_DMABMR_PBL_4xPBL_128Beat 0x01002000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */ #define ETH_DMABMR_EDE_Pos (7U) #define ETH_DMABMR_EDE_Msk (0x1U << ETH_DMABMR_EDE_Pos) /*!< 0x00000080 */ #define ETH_DMABMR_EDE ETH_DMABMR_EDE_Msk /* Enhanced Descriptor Enable */ #define ETH_DMABMR_DSL_Pos (2U) #define ETH_DMABMR_DSL_Msk (0x1FU << ETH_DMABMR_DSL_Pos) /*!< 0x0000007C */ #define ETH_DMABMR_DSL ETH_DMABMR_DSL_Msk /* Descriptor Skip Length */ #define ETH_DMABMR_DA_Pos (1U) #define ETH_DMABMR_DA_Msk (0x1U << ETH_DMABMR_DA_Pos) /*!< 0x00000002 */ #define ETH_DMABMR_DA ETH_DMABMR_DA_Msk /* DMA arbitration scheme */ #define ETH_DMABMR_SR_Pos (0U) #define ETH_DMABMR_SR_Msk (0x1U << ETH_DMABMR_SR_Pos) /*!< 0x00000001 */ #define ETH_DMABMR_SR ETH_DMABMR_SR_Msk /* Software reset */ /* Bit definition for Ethernet DMA Transmit Poll Demand Register */ #define ETH_DMATPDR_TPD_Pos (0U) #define ETH_DMATPDR_TPD_Msk (0xFFFFFFFFU << ETH_DMATPDR_TPD_Pos) /*!< 0xFFFFFFFF */ #define ETH_DMATPDR_TPD ETH_DMATPDR_TPD_Msk /* Transmit poll demand */ /* Bit definition for Ethernet DMA Receive Poll Demand Register */ #define ETH_DMARPDR_RPD_Pos (0U) #define ETH_DMARPDR_RPD_Msk (0xFFFFFFFFU << ETH_DMARPDR_RPD_Pos) /*!< 0xFFFFFFFF */ #define ETH_DMARPDR_RPD ETH_DMARPDR_RPD_Msk /* Receive poll demand */ /* Bit definition for Ethernet DMA Receive Descriptor List Address Register */ #define ETH_DMARDLAR_SRL_Pos (0U) #define ETH_DMARDLAR_SRL_Msk (0xFFFFFFFFU << ETH_DMARDLAR_SRL_Pos) /*!< 0xFFFFFFFF */ #define ETH_DMARDLAR_SRL ETH_DMARDLAR_SRL_Msk /* Start of receive list */ /* Bit definition for Ethernet DMA Transmit Descriptor List Address Register */ #define ETH_DMATDLAR_STL_Pos (0U) #define ETH_DMATDLAR_STL_Msk (0xFFFFFFFFU << ETH_DMATDLAR_STL_Pos) /*!< 0xFFFFFFFF */ #define ETH_DMATDLAR_STL ETH_DMATDLAR_STL_Msk /* Start of transmit list */ /* Bit definition for Ethernet DMA Status Register */ #define ETH_DMASR_TSTS_Pos (29U) #define ETH_DMASR_TSTS_Msk (0x1U << ETH_DMASR_TSTS_Pos) /*!< 0x20000000 */ #define ETH_DMASR_TSTS ETH_DMASR_TSTS_Msk /* Time-stamp trigger status */ #define ETH_DMASR_PMTS_Pos (28U) #define ETH_DMASR_PMTS_Msk (0x1U << ETH_DMASR_PMTS_Pos) /*!< 0x10000000 */ #define ETH_DMASR_PMTS ETH_DMASR_PMTS_Msk /* PMT status */ #define ETH_DMASR_MMCS_Pos (27U) #define ETH_DMASR_MMCS_Msk (0x1U << ETH_DMASR_MMCS_Pos) /*!< 0x08000000 */ #define ETH_DMASR_MMCS ETH_DMASR_MMCS_Msk /* MMC status */ #define ETH_DMASR_EBS_Pos (23U) #define ETH_DMASR_EBS_Msk (0x7U << ETH_DMASR_EBS_Pos) /*!< 0x03800000 */ #define ETH_DMASR_EBS ETH_DMASR_EBS_Msk /* Error bits status */ /* combination with EBS[2:0] for GetFlagStatus function */ #define ETH_DMASR_EBS_DescAccess_Pos (25U) #define ETH_DMASR_EBS_DescAccess_Msk (0x1U << ETH_DMASR_EBS_DescAccess_Pos) /*!< 0x02000000 */ #define ETH_DMASR_EBS_DescAccess ETH_DMASR_EBS_DescAccess_Msk /* Error bits 0-data buffer, 1-desc. access */ #define ETH_DMASR_EBS_ReadTransf_Pos (24U) #define ETH_DMASR_EBS_ReadTransf_Msk (0x1U << ETH_DMASR_EBS_ReadTransf_Pos) /*!< 0x01000000 */ #define ETH_DMASR_EBS_ReadTransf ETH_DMASR_EBS_ReadTransf_Msk /* Error bits 0-write trnsf, 1-read transfr */ #define ETH_DMASR_EBS_DataTransfTx_Pos (23U) #define ETH_DMASR_EBS_DataTransfTx_Msk (0x1U << ETH_DMASR_EBS_DataTransfTx_Pos) /*!< 0x00800000 */ #define ETH_DMASR_EBS_DataTransfTx ETH_DMASR_EBS_DataTransfTx_Msk /* Error bits 0-Rx DMA, 1-Tx DMA */ #define ETH_DMASR_TPS_Pos (20U) #define ETH_DMASR_TPS_Msk (0x7U << ETH_DMASR_TPS_Pos) /*!< 0x00700000 */ #define ETH_DMASR_TPS ETH_DMASR_TPS_Msk /* Transmit process state */ #define ETH_DMASR_TPS_Stopped 0x00000000U /* Stopped - Reset or Stop Tx Command issued */ #define ETH_DMASR_TPS_Fetching_Pos (20U) #define ETH_DMASR_TPS_Fetching_Msk (0x1U << ETH_DMASR_TPS_Fetching_Pos) /*!< 0x00100000 */ #define ETH_DMASR_TPS_Fetching ETH_DMASR_TPS_Fetching_Msk /* Running - fetching the Tx descriptor */ #define ETH_DMASR_TPS_Waiting_Pos (21U) #define ETH_DMASR_TPS_Waiting_Msk (0x1U << ETH_DMASR_TPS_Waiting_Pos) /*!< 0x00200000 */ #define ETH_DMASR_TPS_Waiting ETH_DMASR_TPS_Waiting_Msk /* Running - waiting for status */ #define ETH_DMASR_TPS_Reading_Pos (20U) #define ETH_DMASR_TPS_Reading_Msk (0x3U << ETH_DMASR_TPS_Reading_Pos) /*!< 0x00300000 */ #define ETH_DMASR_TPS_Reading ETH_DMASR_TPS_Reading_Msk /* Running - reading the data from host memory */ #define ETH_DMASR_TPS_Suspended_Pos (21U) #define ETH_DMASR_TPS_Suspended_Msk (0x3U << ETH_DMASR_TPS_Suspended_Pos) /*!< 0x00600000 */ #define ETH_DMASR_TPS_Suspended ETH_DMASR_TPS_Suspended_Msk /* Suspended - Tx Descriptor unavailabe */ #define ETH_DMASR_TPS_Closing_Pos (20U) #define ETH_DMASR_TPS_Closing_Msk (0x7U << ETH_DMASR_TPS_Closing_Pos) /*!< 0x00700000 */ #define ETH_DMASR_TPS_Closing ETH_DMASR_TPS_Closing_Msk /* Running - closing Rx descriptor */ #define ETH_DMASR_RPS_Pos (17U) #define ETH_DMASR_RPS_Msk (0x7U << ETH_DMASR_RPS_Pos) /*!< 0x000E0000 */ #define ETH_DMASR_RPS ETH_DMASR_RPS_Msk /* Receive process state */ #define ETH_DMASR_RPS_Stopped 0x00000000U /* Stopped - Reset or Stop Rx Command issued */ #define ETH_DMASR_RPS_Fetching_Pos (17U) #define ETH_DMASR_RPS_Fetching_Msk (0x1U << ETH_DMASR_RPS_Fetching_Pos) /*!< 0x00020000 */ #define ETH_DMASR_RPS_Fetching ETH_DMASR_RPS_Fetching_Msk /* Running - fetching the Rx descriptor */ #define ETH_DMASR_RPS_Waiting_Pos (17U) #define ETH_DMASR_RPS_Waiting_Msk (0x3U << ETH_DMASR_RPS_Waiting_Pos) /*!< 0x00060000 */ #define ETH_DMASR_RPS_Waiting ETH_DMASR_RPS_Waiting_Msk /* Running - waiting for packet */ #define ETH_DMASR_RPS_Suspended_Pos (19U) #define ETH_DMASR_RPS_Suspended_Msk (0x1U << ETH_DMASR_RPS_Suspended_Pos) /*!< 0x00080000 */ #define ETH_DMASR_RPS_Suspended ETH_DMASR_RPS_Suspended_Msk /* Suspended - Rx Descriptor unavailable */ #define ETH_DMASR_RPS_Closing_Pos (17U) #define ETH_DMASR_RPS_Closing_Msk (0x5U << ETH_DMASR_RPS_Closing_Pos) /*!< 0x000A0000 */ #define ETH_DMASR_RPS_Closing ETH_DMASR_RPS_Closing_Msk /* Running - closing descriptor */ #define ETH_DMASR_RPS_Queuing_Pos (17U) #define ETH_DMASR_RPS_Queuing_Msk (0x7U << ETH_DMASR_RPS_Queuing_Pos) /*!< 0x000E0000 */ #define ETH_DMASR_RPS_Queuing ETH_DMASR_RPS_Queuing_Msk /* Running - queuing the recieve frame into host memory */ #define ETH_DMASR_NIS_Pos (16U) #define ETH_DMASR_NIS_Msk (0x1U << ETH_DMASR_NIS_Pos) /*!< 0x00010000 */ #define ETH_DMASR_NIS ETH_DMASR_NIS_Msk /* Normal interrupt summary */ #define ETH_DMASR_AIS_Pos (15U) #define ETH_DMASR_AIS_Msk (0x1U << ETH_DMASR_AIS_Pos) /*!< 0x00008000 */ #define ETH_DMASR_AIS ETH_DMASR_AIS_Msk /* Abnormal interrupt summary */ #define ETH_DMASR_ERS_Pos (14U) #define ETH_DMASR_ERS_Msk (0x1U << ETH_DMASR_ERS_Pos) /*!< 0x00004000 */ #define ETH_DMASR_ERS ETH_DMASR_ERS_Msk /* Early receive status */ #define ETH_DMASR_FBES_Pos (13U) #define ETH_DMASR_FBES_Msk (0x1U << ETH_DMASR_FBES_Pos) /*!< 0x00002000 */ #define ETH_DMASR_FBES ETH_DMASR_FBES_Msk /* Fatal bus error status */ #define ETH_DMASR_ETS_Pos (10U) #define ETH_DMASR_ETS_Msk (0x1U << ETH_DMASR_ETS_Pos) /*!< 0x00000400 */ #define ETH_DMASR_ETS ETH_DMASR_ETS_Msk /* Early transmit status */ #define ETH_DMASR_RWTS_Pos (9U) #define ETH_DMASR_RWTS_Msk (0x1U << ETH_DMASR_RWTS_Pos) /*!< 0x00000200 */ #define ETH_DMASR_RWTS ETH_DMASR_RWTS_Msk /* Receive watchdog timeout status */ #define ETH_DMASR_RPSS_Pos (8U) #define ETH_DMASR_RPSS_Msk (0x1U << ETH_DMASR_RPSS_Pos) /*!< 0x00000100 */ #define ETH_DMASR_RPSS ETH_DMASR_RPSS_Msk /* Receive process stopped status */ #define ETH_DMASR_RBUS_Pos (7U) #define ETH_DMASR_RBUS_Msk (0x1U << ETH_DMASR_RBUS_Pos) /*!< 0x00000080 */ #define ETH_DMASR_RBUS ETH_DMASR_RBUS_Msk /* Receive buffer unavailable status */ #define ETH_DMASR_RS_Pos (6U) #define ETH_DMASR_RS_Msk (0x1U << ETH_DMASR_RS_Pos) /*!< 0x00000040 */ #define ETH_DMASR_RS ETH_DMASR_RS_Msk /* Receive status */ #define ETH_DMASR_TUS_Pos (5U) #define ETH_DMASR_TUS_Msk (0x1U << ETH_DMASR_TUS_Pos) /*!< 0x00000020 */ #define ETH_DMASR_TUS ETH_DMASR_TUS_Msk /* Transmit underflow status */ #define ETH_DMASR_ROS_Pos (4U) #define ETH_DMASR_ROS_Msk (0x1U << ETH_DMASR_ROS_Pos) /*!< 0x00000010 */ #define ETH_DMASR_ROS ETH_DMASR_ROS_Msk /* Receive overflow status */ #define ETH_DMASR_TJTS_Pos (3U) #define ETH_DMASR_TJTS_Msk (0x1U << ETH_DMASR_TJTS_Pos) /*!< 0x00000008 */ #define ETH_DMASR_TJTS ETH_DMASR_TJTS_Msk /* Transmit jabber timeout status */ #define ETH_DMASR_TBUS_Pos (2U) #define ETH_DMASR_TBUS_Msk (0x1U << ETH_DMASR_TBUS_Pos) /*!< 0x00000004 */ #define ETH_DMASR_TBUS ETH_DMASR_TBUS_Msk /* Transmit buffer unavailable status */ #define ETH_DMASR_TPSS_Pos (1U) #define ETH_DMASR_TPSS_Msk (0x1U << ETH_DMASR_TPSS_Pos) /*!< 0x00000002 */ #define ETH_DMASR_TPSS ETH_DMASR_TPSS_Msk /* Transmit process stopped status */ #define ETH_DMASR_TS_Pos (0U) #define ETH_DMASR_TS_Msk (0x1U << ETH_DMASR_TS_Pos) /*!< 0x00000001 */ #define ETH_DMASR_TS ETH_DMASR_TS_Msk /* Transmit status */ /* Bit definition for Ethernet DMA Operation Mode Register */ #define ETH_DMAOMR_DTCEFD_Pos (26U) #define ETH_DMAOMR_DTCEFD_Msk (0x1U << ETH_DMAOMR_DTCEFD_Pos) /*!< 0x04000000 */ #define ETH_DMAOMR_DTCEFD ETH_DMAOMR_DTCEFD_Msk /* Disable Dropping of TCP/IP checksum error frames */ #define ETH_DMAOMR_RSF_Pos (25U) #define ETH_DMAOMR_RSF_Msk (0x1U << ETH_DMAOMR_RSF_Pos) /*!< 0x02000000 */ #define ETH_DMAOMR_RSF ETH_DMAOMR_RSF_Msk /* Receive store and forward */ #define ETH_DMAOMR_DFRF_Pos (24U) #define ETH_DMAOMR_DFRF_Msk (0x1U << ETH_DMAOMR_DFRF_Pos) /*!< 0x01000000 */ #define ETH_DMAOMR_DFRF ETH_DMAOMR_DFRF_Msk /* Disable flushing of received frames */ #define ETH_DMAOMR_TSF_Pos (21U) #define ETH_DMAOMR_TSF_Msk (0x1U << ETH_DMAOMR_TSF_Pos) /*!< 0x00200000 */ #define ETH_DMAOMR_TSF ETH_DMAOMR_TSF_Msk /* Transmit store and forward */ #define ETH_DMAOMR_FTF_Pos (20U) #define ETH_DMAOMR_FTF_Msk (0x1U << ETH_DMAOMR_FTF_Pos) /*!< 0x00100000 */ #define ETH_DMAOMR_FTF ETH_DMAOMR_FTF_Msk /* Flush transmit FIFO */ #define ETH_DMAOMR_TTC_Pos (14U) #define ETH_DMAOMR_TTC_Msk (0x7U << ETH_DMAOMR_TTC_Pos) /*!< 0x0001C000 */ #define ETH_DMAOMR_TTC ETH_DMAOMR_TTC_Msk /* Transmit threshold control */ #define ETH_DMAOMR_TTC_64Bytes 0x00000000U /* threshold level of the MTL Transmit FIFO is 64 Bytes */ #define ETH_DMAOMR_TTC_128Bytes 0x00004000U /* threshold level of the MTL Transmit FIFO is 128 Bytes */ #define ETH_DMAOMR_TTC_192Bytes 0x00008000U /* threshold level of the MTL Transmit FIFO is 192 Bytes */ #define ETH_DMAOMR_TTC_256Bytes 0x0000C000U /* threshold level of the MTL Transmit FIFO is 256 Bytes */ #define ETH_DMAOMR_TTC_40Bytes 0x00010000U /* threshold level of the MTL Transmit FIFO is 40 Bytes */ #define ETH_DMAOMR_TTC_32Bytes 0x00014000U /* threshold level of the MTL Transmit FIFO is 32 Bytes */ #define ETH_DMAOMR_TTC_24Bytes 0x00018000U /* threshold level of the MTL Transmit FIFO is 24 Bytes */ #define ETH_DMAOMR_TTC_16Bytes 0x0001C000U /* threshold level of the MTL Transmit FIFO is 16 Bytes */ #define ETH_DMAOMR_ST_Pos (13U) #define ETH_DMAOMR_ST_Msk (0x1U << ETH_DMAOMR_ST_Pos) /*!< 0x00002000 */ #define ETH_DMAOMR_ST ETH_DMAOMR_ST_Msk /* Start/stop transmission command */ #define ETH_DMAOMR_FEF_Pos (7U) #define ETH_DMAOMR_FEF_Msk (0x1U << ETH_DMAOMR_FEF_Pos) /*!< 0x00000080 */ #define ETH_DMAOMR_FEF ETH_DMAOMR_FEF_Msk /* Forward error frames */ #define ETH_DMAOMR_FUGF_Pos (6U) #define ETH_DMAOMR_FUGF_Msk (0x1U << ETH_DMAOMR_FUGF_Pos) /*!< 0x00000040 */ #define ETH_DMAOMR_FUGF ETH_DMAOMR_FUGF_Msk /* Forward undersized good frames */ #define ETH_DMAOMR_RTC_Pos (3U) #define ETH_DMAOMR_RTC_Msk (0x3U << ETH_DMAOMR_RTC_Pos) /*!< 0x00000018 */ #define ETH_DMAOMR_RTC ETH_DMAOMR_RTC_Msk /* receive threshold control */ #define ETH_DMAOMR_RTC_64Bytes 0x00000000U /* threshold level of the MTL Receive FIFO is 64 Bytes */ #define ETH_DMAOMR_RTC_32Bytes 0x00000008U /* threshold level of the MTL Receive FIFO is 32 Bytes */ #define ETH_DMAOMR_RTC_96Bytes 0x00000010U /* threshold level of the MTL Receive FIFO is 96 Bytes */ #define ETH_DMAOMR_RTC_128Bytes 0x00000018U /* threshold level of the MTL Receive FIFO is 128 Bytes */ #define ETH_DMAOMR_OSF_Pos (2U) #define ETH_DMAOMR_OSF_Msk (0x1U << ETH_DMAOMR_OSF_Pos) /*!< 0x00000004 */ #define ETH_DMAOMR_OSF ETH_DMAOMR_OSF_Msk /* operate on second frame */ #define ETH_DMAOMR_SR_Pos (1U) #define ETH_DMAOMR_SR_Msk (0x1U << ETH_DMAOMR_SR_Pos) /*!< 0x00000002 */ #define ETH_DMAOMR_SR ETH_DMAOMR_SR_Msk /* Start/stop receive */ /* Bit definition for Ethernet DMA Interrupt Enable Register */ #define ETH_DMAIER_NISE_Pos (16U) #define ETH_DMAIER_NISE_Msk (0x1U << ETH_DMAIER_NISE_Pos) /*!< 0x00010000 */ #define ETH_DMAIER_NISE ETH_DMAIER_NISE_Msk /* Normal interrupt summary enable */ #define ETH_DMAIER_AISE_Pos (15U) #define ETH_DMAIER_AISE_Msk (0x1U << ETH_DMAIER_AISE_Pos) /*!< 0x00008000 */ #define ETH_DMAIER_AISE ETH_DMAIER_AISE_Msk /* Abnormal interrupt summary enable */ #define ETH_DMAIER_ERIE_Pos (14U) #define ETH_DMAIER_ERIE_Msk (0x1U << ETH_DMAIER_ERIE_Pos) /*!< 0x00004000 */ #define ETH_DMAIER_ERIE ETH_DMAIER_ERIE_Msk /* Early receive interrupt enable */ #define ETH_DMAIER_FBEIE_Pos (13U) #define ETH_DMAIER_FBEIE_Msk (0x1U << ETH_DMAIER_FBEIE_Pos) /*!< 0x00002000 */ #define ETH_DMAIER_FBEIE ETH_DMAIER_FBEIE_Msk /* Fatal bus error interrupt enable */ #define ETH_DMAIER_ETIE_Pos (10U) #define ETH_DMAIER_ETIE_Msk (0x1U << ETH_DMAIER_ETIE_Pos) /*!< 0x00000400 */ #define ETH_DMAIER_ETIE ETH_DMAIER_ETIE_Msk /* Early transmit interrupt enable */ #define ETH_DMAIER_RWTIE_Pos (9U) #define ETH_DMAIER_RWTIE_Msk (0x1U << ETH_DMAIER_RWTIE_Pos) /*!< 0x00000200 */ #define ETH_DMAIER_RWTIE ETH_DMAIER_RWTIE_Msk /* Receive watchdog timeout interrupt enable */ #define ETH_DMAIER_RPSIE_Pos (8U) #define ETH_DMAIER_RPSIE_Msk (0x1U << ETH_DMAIER_RPSIE_Pos) /*!< 0x00000100 */ #define ETH_DMAIER_RPSIE ETH_DMAIER_RPSIE_Msk /* Receive process stopped interrupt enable */ #define ETH_DMAIER_RBUIE_Pos (7U) #define ETH_DMAIER_RBUIE_Msk (0x1U << ETH_DMAIER_RBUIE_Pos) /*!< 0x00000080 */ #define ETH_DMAIER_RBUIE ETH_DMAIER_RBUIE_Msk /* Receive buffer unavailable interrupt enable */ #define ETH_DMAIER_RIE_Pos (6U) #define ETH_DMAIER_RIE_Msk (0x1U << ETH_DMAIER_RIE_Pos) /*!< 0x00000040 */ #define ETH_DMAIER_RIE ETH_DMAIER_RIE_Msk /* Receive interrupt enable */ #define ETH_DMAIER_TUIE_Pos (5U) #define ETH_DMAIER_TUIE_Msk (0x1U << ETH_DMAIER_TUIE_Pos) /*!< 0x00000020 */ #define ETH_DMAIER_TUIE ETH_DMAIER_TUIE_Msk /* Transmit Underflow interrupt enable */ #define ETH_DMAIER_ROIE_Pos (4U) #define ETH_DMAIER_ROIE_Msk (0x1U << ETH_DMAIER_ROIE_Pos) /*!< 0x00000010 */ #define ETH_DMAIER_ROIE ETH_DMAIER_ROIE_Msk /* Receive Overflow interrupt enable */ #define ETH_DMAIER_TJTIE_Pos (3U) #define ETH_DMAIER_TJTIE_Msk (0x1U << ETH_DMAIER_TJTIE_Pos) /*!< 0x00000008 */ #define ETH_DMAIER_TJTIE ETH_DMAIER_TJTIE_Msk /* Transmit jabber timeout interrupt enable */ #define ETH_DMAIER_TBUIE_Pos (2U) #define ETH_DMAIER_TBUIE_Msk (0x1U << ETH_DMAIER_TBUIE_Pos) /*!< 0x00000004 */ #define ETH_DMAIER_TBUIE ETH_DMAIER_TBUIE_Msk /* Transmit buffer unavailable interrupt enable */ #define ETH_DMAIER_TPSIE_Pos (1U) #define ETH_DMAIER_TPSIE_Msk (0x1U << ETH_DMAIER_TPSIE_Pos) /*!< 0x00000002 */ #define ETH_DMAIER_TPSIE ETH_DMAIER_TPSIE_Msk /* Transmit process stopped interrupt enable */ #define ETH_DMAIER_TIE_Pos (0U) #define ETH_DMAIER_TIE_Msk (0x1U << ETH_DMAIER_TIE_Pos) /*!< 0x00000001 */ #define ETH_DMAIER_TIE ETH_DMAIER_TIE_Msk /* Transmit interrupt enable */ /* Bit definition for Ethernet DMA Missed Frame and Buffer Overflow Counter Register */ #define ETH_DMAMFBOCR_OFOC_Pos (28U) #define ETH_DMAMFBOCR_OFOC_Msk (0x1U << ETH_DMAMFBOCR_OFOC_Pos) /*!< 0x10000000 */ #define ETH_DMAMFBOCR_OFOC ETH_DMAMFBOCR_OFOC_Msk /* Overflow bit for FIFO overflow counter */ #define ETH_DMAMFBOCR_MFA_Pos (17U) #define ETH_DMAMFBOCR_MFA_Msk (0x7FFU << ETH_DMAMFBOCR_MFA_Pos) /*!< 0x0FFE0000 */ #define ETH_DMAMFBOCR_MFA ETH_DMAMFBOCR_MFA_Msk /* Number of frames missed by the application */ #define ETH_DMAMFBOCR_OMFC_Pos (16U) #define ETH_DMAMFBOCR_OMFC_Msk (0x1U << ETH_DMAMFBOCR_OMFC_Pos) /*!< 0x00010000 */ #define ETH_DMAMFBOCR_OMFC ETH_DMAMFBOCR_OMFC_Msk /* Overflow bit for missed frame counter */ #define ETH_DMAMFBOCR_MFC_Pos (0U) #define ETH_DMAMFBOCR_MFC_Msk (0xFFFFU << ETH_DMAMFBOCR_MFC_Pos) /*!< 0x0000FFFF */ #define ETH_DMAMFBOCR_MFC ETH_DMAMFBOCR_MFC_Msk /* Number of frames missed by the controller */ /* Bit definition for Ethernet DMA Current Host Transmit Descriptor Register */ #define ETH_DMACHTDR_HTDAP_Pos (0U) #define ETH_DMACHTDR_HTDAP_Msk (0xFFFFFFFFU << ETH_DMACHTDR_HTDAP_Pos) /*!< 0xFFFFFFFF */ #define ETH_DMACHTDR_HTDAP ETH_DMACHTDR_HTDAP_Msk /* Host transmit descriptor address pointer */ /* Bit definition for Ethernet DMA Current Host Receive Descriptor Register */ #define ETH_DMACHRDR_HRDAP_Pos (0U) #define ETH_DMACHRDR_HRDAP_Msk (0xFFFFFFFFU << ETH_DMACHRDR_HRDAP_Pos) /*!< 0xFFFFFFFF */ #define ETH_DMACHRDR_HRDAP ETH_DMACHRDR_HRDAP_Msk /* Host receive descriptor address pointer */ /* Bit definition for Ethernet DMA Current Host Transmit Buffer Address Register */ #define ETH_DMACHTBAR_HTBAP_Pos (0U) #define ETH_DMACHTBAR_HTBAP_Msk (0xFFFFFFFFU << ETH_DMACHTBAR_HTBAP_Pos) /*!< 0xFFFFFFFF */ #define ETH_DMACHTBAR_HTBAP ETH_DMACHTBAR_HTBAP_Msk /* Host transmit buffer address pointer */ /* Bit definition for Ethernet DMA Current Host Receive Buffer Address Register */ #define ETH_DMACHRBAR_HRBAP_Pos (0U) #define ETH_DMACHRBAR_HRBAP_Msk (0xFFFFFFFFU << ETH_DMACHRBAR_HRBAP_Pos) /*!< 0xFFFFFFFF */ #define ETH_DMACHRBAR_HRBAP ETH_DMACHRBAR_HRBAP_Msk /* Host receive buffer address pointer */ /******************************************************************************/ /* */ /* USB_OTG */ /* */ /******************************************************************************/ /******************** Bit definition for USB_OTG_GOTGCTL register ***********/ #define USB_OTG_GOTGCTL_SRQSCS_Pos (0U) #define USB_OTG_GOTGCTL_SRQSCS_Msk (0x1U << USB_OTG_GOTGCTL_SRQSCS_Pos) /*!< 0x00000001 */ #define USB_OTG_GOTGCTL_SRQSCS USB_OTG_GOTGCTL_SRQSCS_Msk /*!< Session request success */ #define USB_OTG_GOTGCTL_SRQ_Pos (1U) #define USB_OTG_GOTGCTL_SRQ_Msk (0x1U << USB_OTG_GOTGCTL_SRQ_Pos) /*!< 0x00000002 */ #define USB_OTG_GOTGCTL_SRQ USB_OTG_GOTGCTL_SRQ_Msk /*!< Session request */ #define USB_OTG_GOTGCTL_VBVALOEN_Pos (2U) #define USB_OTG_GOTGCTL_VBVALOEN_Msk (0x1U << USB_OTG_GOTGCTL_VBVALOEN_Pos) /*!< 0x00000004 */ #define USB_OTG_GOTGCTL_VBVALOEN USB_OTG_GOTGCTL_VBVALOEN_Msk /*!< VBUS valid override enable */ #define USB_OTG_GOTGCTL_VBVALOVAL_Pos (3U) #define USB_OTG_GOTGCTL_VBVALOVAL_Msk (0x1U << USB_OTG_GOTGCTL_VBVALOVAL_Pos) /*!< 0x00000008 */ #define USB_OTG_GOTGCTL_VBVALOVAL USB_OTG_GOTGCTL_VBVALOVAL_Msk /*!< VBUS valid override value */ #define USB_OTG_GOTGCTL_AVALOEN_Pos (4U) #define USB_OTG_GOTGCTL_AVALOEN_Msk (0x1U << USB_OTG_GOTGCTL_AVALOEN_Pos) /*!< 0x00000010 */ #define USB_OTG_GOTGCTL_AVALOEN USB_OTG_GOTGCTL_AVALOEN_Msk /*!< A-peripheral session valid override enable */ #define USB_OTG_GOTGCTL_AVALOVAL_Pos (5U) #define USB_OTG_GOTGCTL_AVALOVAL_Msk (0x1U << USB_OTG_GOTGCTL_AVALOVAL_Pos) /*!< 0x00000020 */ #define USB_OTG_GOTGCTL_AVALOVAL USB_OTG_GOTGCTL_AVALOVAL_Msk /*!< A-peripheral session valid override value */ #define USB_OTG_GOTGCTL_BVALOEN_Pos (6U) #define USB_OTG_GOTGCTL_BVALOEN_Msk (0x1U << USB_OTG_GOTGCTL_BVALOEN_Pos) /*!< 0x00000040 */ #define USB_OTG_GOTGCTL_BVALOEN USB_OTG_GOTGCTL_BVALOEN_Msk /*!< B-peripheral session valid override enable */ #define USB_OTG_GOTGCTL_BVALOVAL_Pos (7U) #define USB_OTG_GOTGCTL_BVALOVAL_Msk (0x1U << USB_OTG_GOTGCTL_BVALOVAL_Pos) /*!< 0x00000080 */ #define USB_OTG_GOTGCTL_BVALOVAL USB_OTG_GOTGCTL_BVALOVAL_Msk /*!< B-peripheral session valid override value */ #define USB_OTG_GOTGCTL_HNGSCS_Pos (8U) #define USB_OTG_GOTGCTL_HNGSCS_Msk (0x1U << USB_OTG_GOTGCTL_HNGSCS_Pos) /*!< 0x00000100 */ #define USB_OTG_GOTGCTL_HNGSCS USB_OTG_GOTGCTL_HNGSCS_Msk /*!< Host set HNP enable */ #define USB_OTG_GOTGCTL_HNPRQ_Pos (9U) #define USB_OTG_GOTGCTL_HNPRQ_Msk (0x1U << USB_OTG_GOTGCTL_HNPRQ_Pos) /*!< 0x00000200 */ #define USB_OTG_GOTGCTL_HNPRQ USB_OTG_GOTGCTL_HNPRQ_Msk /*!< HNP request */ #define USB_OTG_GOTGCTL_HSHNPEN_Pos (10U) #define USB_OTG_GOTGCTL_HSHNPEN_Msk (0x1U << USB_OTG_GOTGCTL_HSHNPEN_Pos) /*!< 0x00000400 */ #define USB_OTG_GOTGCTL_HSHNPEN USB_OTG_GOTGCTL_HSHNPEN_Msk /*!< Host set HNP enable */ #define USB_OTG_GOTGCTL_DHNPEN_Pos (11U) #define USB_OTG_GOTGCTL_DHNPEN_Msk (0x1U << USB_OTG_GOTGCTL_DHNPEN_Pos) /*!< 0x00000800 */ #define USB_OTG_GOTGCTL_DHNPEN USB_OTG_GOTGCTL_DHNPEN_Msk /*!< Device HNP enabled */ #define USB_OTG_GOTGCTL_EHEN_Pos (12U) #define USB_OTG_GOTGCTL_EHEN_Msk (0x1U << USB_OTG_GOTGCTL_EHEN_Pos) /*!< 0x00001000 */ #define USB_OTG_GOTGCTL_EHEN USB_OTG_GOTGCTL_EHEN_Msk /*!< Embedded host enable */ #define USB_OTG_GOTGCTL_CIDSTS_Pos (16U) #define USB_OTG_GOTGCTL_CIDSTS_Msk (0x1U << USB_OTG_GOTGCTL_CIDSTS_Pos) /*!< 0x00010000 */ #define USB_OTG_GOTGCTL_CIDSTS USB_OTG_GOTGCTL_CIDSTS_Msk /*!< Connector ID status */ #define USB_OTG_GOTGCTL_DBCT_Pos (17U) #define USB_OTG_GOTGCTL_DBCT_Msk (0x1U << USB_OTG_GOTGCTL_DBCT_Pos) /*!< 0x00020000 */ #define USB_OTG_GOTGCTL_DBCT USB_OTG_GOTGCTL_DBCT_Msk /*!< Long/short debounce time */ #define USB_OTG_GOTGCTL_ASVLD_Pos (18U) #define USB_OTG_GOTGCTL_ASVLD_Msk (0x1U << USB_OTG_GOTGCTL_ASVLD_Pos) /*!< 0x00040000 */ #define USB_OTG_GOTGCTL_ASVLD USB_OTG_GOTGCTL_ASVLD_Msk /*!< A-session valid */ #define USB_OTG_GOTGCTL_BSESVLD_Pos (19U) #define USB_OTG_GOTGCTL_BSESVLD_Msk (0x1U << USB_OTG_GOTGCTL_BSESVLD_Pos) /*!< 0x00080000 */ #define USB_OTG_GOTGCTL_BSESVLD USB_OTG_GOTGCTL_BSESVLD_Msk /*!< B-session valid */ #define USB_OTG_GOTGCTL_OTGVER_Pos (20U) #define USB_OTG_GOTGCTL_OTGVER_Msk (0x1U << USB_OTG_GOTGCTL_OTGVER_Pos) /*!< 0x00100000 */ #define USB_OTG_GOTGCTL_OTGVER USB_OTG_GOTGCTL_OTGVER_Msk /*!< OTG version */ /******************** Bit definition forUSB_OTG_HCFG register ********************/ #define USB_OTG_HCFG_FSLSPCS_Pos (0U) #define USB_OTG_HCFG_FSLSPCS_Msk (0x3U << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000003 */ #define USB_OTG_HCFG_FSLSPCS USB_OTG_HCFG_FSLSPCS_Msk /*!< FS/LS PHY clock select */ #define USB_OTG_HCFG_FSLSPCS_0 (0x1U << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000001 */ #define USB_OTG_HCFG_FSLSPCS_1 (0x2U << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000002 */ #define USB_OTG_HCFG_FSLSS_Pos (2U) #define USB_OTG_HCFG_FSLSS_Msk (0x1U << USB_OTG_HCFG_FSLSS_Pos) /*!< 0x00000004 */ #define USB_OTG_HCFG_FSLSS USB_OTG_HCFG_FSLSS_Msk /*!< FS- and LS-only support */ /******************** Bit definition for USB_OTG_DCFG register ********************/ #define USB_OTG_DCFG_DSPD_Pos (0U) #define USB_OTG_DCFG_DSPD_Msk (0x3U << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000003 */ #define USB_OTG_DCFG_DSPD USB_OTG_DCFG_DSPD_Msk /*!< Device speed */ #define USB_OTG_DCFG_DSPD_0 (0x1U << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000001 */ #define USB_OTG_DCFG_DSPD_1 (0x2U << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000002 */ #define USB_OTG_DCFG_NZLSOHSK_Pos (2U) #define USB_OTG_DCFG_NZLSOHSK_Msk (0x1U << USB_OTG_DCFG_NZLSOHSK_Pos) /*!< 0x00000004 */ #define USB_OTG_DCFG_NZLSOHSK USB_OTG_DCFG_NZLSOHSK_Msk /*!< Nonzero-length status OUT handshake */ #define USB_OTG_DCFG_DAD_Pos (4U) #define USB_OTG_DCFG_DAD_Msk (0x7FU << USB_OTG_DCFG_DAD_Pos) /*!< 0x000007F0 */ #define USB_OTG_DCFG_DAD USB_OTG_DCFG_DAD_Msk /*!< Device address */ #define USB_OTG_DCFG_DAD_0 (0x01U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000010 */ #define USB_OTG_DCFG_DAD_1 (0x02U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000020 */ #define USB_OTG_DCFG_DAD_2 (0x04U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000040 */ #define USB_OTG_DCFG_DAD_3 (0x08U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000080 */ #define USB_OTG_DCFG_DAD_4 (0x10U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000100 */ #define USB_OTG_DCFG_DAD_5 (0x20U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000200 */ #define USB_OTG_DCFG_DAD_6 (0x40U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000400 */ #define USB_OTG_DCFG_PFIVL_Pos (11U) #define USB_OTG_DCFG_PFIVL_Msk (0x3U << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001800 */ #define USB_OTG_DCFG_PFIVL USB_OTG_DCFG_PFIVL_Msk /*!< Periodic (micro)frame interval */ #define USB_OTG_DCFG_PFIVL_0 (0x1U << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00000800 */ #define USB_OTG_DCFG_PFIVL_1 (0x2U << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001000 */ #define USB_OTG_DCFG_PERSCHIVL_Pos (24U) #define USB_OTG_DCFG_PERSCHIVL_Msk (0x3U << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x03000000 */ #define USB_OTG_DCFG_PERSCHIVL USB_OTG_DCFG_PERSCHIVL_Msk /*!< Periodic scheduling interval */ #define USB_OTG_DCFG_PERSCHIVL_0 (0x1U << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x01000000 */ #define USB_OTG_DCFG_PERSCHIVL_1 (0x2U << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x02000000 */ /******************** Bit definition for USB_OTG_PCGCR register ********************/ #define USB_OTG_PCGCR_STPPCLK_Pos (0U) #define USB_OTG_PCGCR_STPPCLK_Msk (0x1U << USB_OTG_PCGCR_STPPCLK_Pos) /*!< 0x00000001 */ #define USB_OTG_PCGCR_STPPCLK USB_OTG_PCGCR_STPPCLK_Msk /*!< Stop PHY clock */ #define USB_OTG_PCGCR_GATEHCLK_Pos (1U) #define USB_OTG_PCGCR_GATEHCLK_Msk (0x1U << USB_OTG_PCGCR_GATEHCLK_Pos) /*!< 0x00000002 */ #define USB_OTG_PCGCR_GATEHCLK USB_OTG_PCGCR_GATEHCLK_Msk /*!< Gate HCLK */ #define USB_OTG_PCGCR_PHYSUSP_Pos (4U) #define USB_OTG_PCGCR_PHYSUSP_Msk (0x1U << USB_OTG_PCGCR_PHYSUSP_Pos) /*!< 0x00000010 */ #define USB_OTG_PCGCR_PHYSUSP USB_OTG_PCGCR_PHYSUSP_Msk /*!< PHY suspended */ /******************** Bit definition for USB_OTG_GOTGINT register ********************/ #define USB_OTG_GOTGINT_SEDET_Pos (2U) #define USB_OTG_GOTGINT_SEDET_Msk (0x1U << USB_OTG_GOTGINT_SEDET_Pos) /*!< 0x00000004 */ #define USB_OTG_GOTGINT_SEDET USB_OTG_GOTGINT_SEDET_Msk /*!< Session end detected */ #define USB_OTG_GOTGINT_SRSSCHG_Pos (8U) #define USB_OTG_GOTGINT_SRSSCHG_Msk (0x1U << USB_OTG_GOTGINT_SRSSCHG_Pos) /*!< 0x00000100 */ #define USB_OTG_GOTGINT_SRSSCHG USB_OTG_GOTGINT_SRSSCHG_Msk /*!< Session request success status change */ #define USB_OTG_GOTGINT_HNSSCHG_Pos (9U) #define USB_OTG_GOTGINT_HNSSCHG_Msk (0x1U << USB_OTG_GOTGINT_HNSSCHG_Pos) /*!< 0x00000200 */ #define USB_OTG_GOTGINT_HNSSCHG USB_OTG_GOTGINT_HNSSCHG_Msk /*!< Host negotiation success status change */ #define USB_OTG_GOTGINT_HNGDET_Pos (17U) #define USB_OTG_GOTGINT_HNGDET_Msk (0x1U << USB_OTG_GOTGINT_HNGDET_Pos) /*!< 0x00020000 */ #define USB_OTG_GOTGINT_HNGDET USB_OTG_GOTGINT_HNGDET_Msk /*!< Host negotiation detected */ #define USB_OTG_GOTGINT_ADTOCHG_Pos (18U) #define USB_OTG_GOTGINT_ADTOCHG_Msk (0x1U << USB_OTG_GOTGINT_ADTOCHG_Pos) /*!< 0x00040000 */ #define USB_OTG_GOTGINT_ADTOCHG USB_OTG_GOTGINT_ADTOCHG_Msk /*!< A-device timeout change */ #define USB_OTG_GOTGINT_DBCDNE_Pos (19U) #define USB_OTG_GOTGINT_DBCDNE_Msk (0x1U << USB_OTG_GOTGINT_DBCDNE_Pos) /*!< 0x00080000 */ #define USB_OTG_GOTGINT_DBCDNE USB_OTG_GOTGINT_DBCDNE_Msk /*!< Debounce done */ #define USB_OTG_GOTGINT_IDCHNG_Pos (20U) #define USB_OTG_GOTGINT_IDCHNG_Msk (0x1U << USB_OTG_GOTGINT_IDCHNG_Pos) /*!< 0x00100000 */ #define USB_OTG_GOTGINT_IDCHNG USB_OTG_GOTGINT_IDCHNG_Msk /*!< Change in ID pin input value */ /******************** Bit definition for USB_OTG_DCTL register ********************/ #define USB_OTG_DCTL_RWUSIG_Pos (0U) #define USB_OTG_DCTL_RWUSIG_Msk (0x1U << USB_OTG_DCTL_RWUSIG_Pos) /*!< 0x00000001 */ #define USB_OTG_DCTL_RWUSIG USB_OTG_DCTL_RWUSIG_Msk /*!< Remote wakeup signaling */ #define USB_OTG_DCTL_SDIS_Pos (1U) #define USB_OTG_DCTL_SDIS_Msk (0x1U << USB_OTG_DCTL_SDIS_Pos) /*!< 0x00000002 */ #define USB_OTG_DCTL_SDIS USB_OTG_DCTL_SDIS_Msk /*!< Soft disconnect */ #define USB_OTG_DCTL_GINSTS_Pos (2U) #define USB_OTG_DCTL_GINSTS_Msk (0x1U << USB_OTG_DCTL_GINSTS_Pos) /*!< 0x00000004 */ #define USB_OTG_DCTL_GINSTS USB_OTG_DCTL_GINSTS_Msk /*!< Global IN NAK status */ #define USB_OTG_DCTL_GONSTS_Pos (3U) #define USB_OTG_DCTL_GONSTS_Msk (0x1U << USB_OTG_DCTL_GONSTS_Pos) /*!< 0x00000008 */ #define USB_OTG_DCTL_GONSTS USB_OTG_DCTL_GONSTS_Msk /*!< Global OUT NAK status */ #define USB_OTG_DCTL_TCTL_Pos (4U) #define USB_OTG_DCTL_TCTL_Msk (0x7U << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000070 */ #define USB_OTG_DCTL_TCTL USB_OTG_DCTL_TCTL_Msk /*!< Test control */ #define USB_OTG_DCTL_TCTL_0 (0x1U << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000010 */ #define USB_OTG_DCTL_TCTL_1 (0x2U << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000020 */ #define USB_OTG_DCTL_TCTL_2 (0x4U << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000040 */ #define USB_OTG_DCTL_SGINAK_Pos (7U) #define USB_OTG_DCTL_SGINAK_Msk (0x1U << USB_OTG_DCTL_SGINAK_Pos) /*!< 0x00000080 */ #define USB_OTG_DCTL_SGINAK USB_OTG_DCTL_SGINAK_Msk /*!< Set global IN NAK */ #define USB_OTG_DCTL_CGINAK_Pos (8U) #define USB_OTG_DCTL_CGINAK_Msk (0x1U << USB_OTG_DCTL_CGINAK_Pos) /*!< 0x00000100 */ #define USB_OTG_DCTL_CGINAK USB_OTG_DCTL_CGINAK_Msk /*!< Clear global IN NAK */ #define USB_OTG_DCTL_SGONAK_Pos (9U) #define USB_OTG_DCTL_SGONAK_Msk (0x1U << USB_OTG_DCTL_SGONAK_Pos) /*!< 0x00000200 */ #define USB_OTG_DCTL_SGONAK USB_OTG_DCTL_SGONAK_Msk /*!< Set global OUT NAK */ #define USB_OTG_DCTL_CGONAK_Pos (10U) #define USB_OTG_DCTL_CGONAK_Msk (0x1U << USB_OTG_DCTL_CGONAK_Pos) /*!< 0x00000400 */ #define USB_OTG_DCTL_CGONAK USB_OTG_DCTL_CGONAK_Msk /*!< Clear global OUT NAK */ #define USB_OTG_DCTL_POPRGDNE_Pos (11U) #define USB_OTG_DCTL_POPRGDNE_Msk (0x1U << USB_OTG_DCTL_POPRGDNE_Pos) /*!< 0x00000800 */ #define USB_OTG_DCTL_POPRGDNE USB_OTG_DCTL_POPRGDNE_Msk /*!< Power-on programming done */ /******************** Bit definition for USB_OTG_HFIR register ********************/ #define USB_OTG_HFIR_FRIVL_Pos (0U) #define USB_OTG_HFIR_FRIVL_Msk (0xFFFFU << USB_OTG_HFIR_FRIVL_Pos) /*!< 0x0000FFFF */ #define USB_OTG_HFIR_FRIVL USB_OTG_HFIR_FRIVL_Msk /*!< Frame interval */ /******************** Bit definition for USB_OTG_HFNUM register ********************/ #define USB_OTG_HFNUM_FRNUM_Pos (0U) #define USB_OTG_HFNUM_FRNUM_Msk (0xFFFFU << USB_OTG_HFNUM_FRNUM_Pos) /*!< 0x0000FFFF */ #define USB_OTG_HFNUM_FRNUM USB_OTG_HFNUM_FRNUM_Msk /*!< Frame number */ #define USB_OTG_HFNUM_FTREM_Pos (16U) #define USB_OTG_HFNUM_FTREM_Msk (0xFFFFU << USB_OTG_HFNUM_FTREM_Pos) /*!< 0xFFFF0000 */ #define USB_OTG_HFNUM_FTREM USB_OTG_HFNUM_FTREM_Msk /*!< Frame time remaining */ /******************** Bit definition for USB_OTG_DSTS register ********************/ #define USB_OTG_DSTS_SUSPSTS_Pos (0U) #define USB_OTG_DSTS_SUSPSTS_Msk (0x1U << USB_OTG_DSTS_SUSPSTS_Pos) /*!< 0x00000001 */ #define USB_OTG_DSTS_SUSPSTS USB_OTG_DSTS_SUSPSTS_Msk /*!< Suspend status */ #define USB_OTG_DSTS_ENUMSPD_Pos (1U) #define USB_OTG_DSTS_ENUMSPD_Msk (0x3U << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000006 */ #define USB_OTG_DSTS_ENUMSPD USB_OTG_DSTS_ENUMSPD_Msk /*!< Enumerated speed */ #define USB_OTG_DSTS_ENUMSPD_0 (0x1U << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000002 */ #define USB_OTG_DSTS_ENUMSPD_1 (0x2U << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000004 */ #define USB_OTG_DSTS_EERR_Pos (3U) #define USB_OTG_DSTS_EERR_Msk (0x1U << USB_OTG_DSTS_EERR_Pos) /*!< 0x00000008 */ #define USB_OTG_DSTS_EERR USB_OTG_DSTS_EERR_Msk /*!< Erratic error */ #define USB_OTG_DSTS_FNSOF_Pos (8U) #define USB_OTG_DSTS_FNSOF_Msk (0x3FFFU << USB_OTG_DSTS_FNSOF_Pos) /*!< 0x003FFF00 */ #define USB_OTG_DSTS_FNSOF USB_OTG_DSTS_FNSOF_Msk /*!< Frame number of the received SOF */ /******************** Bit definition for USB_OTG_GAHBCFG register ********************/ #define USB_OTG_GAHBCFG_GINT_Pos (0U) #define USB_OTG_GAHBCFG_GINT_Msk (0x1U << USB_OTG_GAHBCFG_GINT_Pos) /*!< 0x00000001 */ #define USB_OTG_GAHBCFG_GINT USB_OTG_GAHBCFG_GINT_Msk /*!< Global interrupt mask */ #define USB_OTG_GAHBCFG_HBSTLEN_Pos (1U) #define USB_OTG_GAHBCFG_HBSTLEN_Msk (0xFU << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x0000001E */ #define USB_OTG_GAHBCFG_HBSTLEN USB_OTG_GAHBCFG_HBSTLEN_Msk /*!< Burst length/type */ #define USB_OTG_GAHBCFG_HBSTLEN_0 (0x0U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< Single */ #define USB_OTG_GAHBCFG_HBSTLEN_1 (0x1U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR */ #define USB_OTG_GAHBCFG_HBSTLEN_2 (0x3U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR4 */ #define USB_OTG_GAHBCFG_HBSTLEN_3 (0x5U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR8 */ #define USB_OTG_GAHBCFG_HBSTLEN_4 (0x7U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR16 */ #define USB_OTG_GAHBCFG_DMAEN_Pos (5U) #define USB_OTG_GAHBCFG_DMAEN_Msk (0x1U << USB_OTG_GAHBCFG_DMAEN_Pos) /*!< 0x00000020 */ #define USB_OTG_GAHBCFG_DMAEN USB_OTG_GAHBCFG_DMAEN_Msk /*!< DMA enable */ #define USB_OTG_GAHBCFG_TXFELVL_Pos (7U) #define USB_OTG_GAHBCFG_TXFELVL_Msk (0x1U << USB_OTG_GAHBCFG_TXFELVL_Pos) /*!< 0x00000080 */ #define USB_OTG_GAHBCFG_TXFELVL USB_OTG_GAHBCFG_TXFELVL_Msk /*!< TxFIFO empty level */ #define USB_OTG_GAHBCFG_PTXFELVL_Pos (8U) #define USB_OTG_GAHBCFG_PTXFELVL_Msk (0x1U << USB_OTG_GAHBCFG_PTXFELVL_Pos) /*!< 0x00000100 */ #define USB_OTG_GAHBCFG_PTXFELVL USB_OTG_GAHBCFG_PTXFELVL_Msk /*!< Periodic TxFIFO empty level */ /******************** Bit definition for USB_OTG_GUSBCFG register ********************/ #define USB_OTG_GUSBCFG_TOCAL_Pos (0U) #define USB_OTG_GUSBCFG_TOCAL_Msk (0x7U << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000007 */ #define USB_OTG_GUSBCFG_TOCAL USB_OTG_GUSBCFG_TOCAL_Msk /*!< FS timeout calibration */ #define USB_OTG_GUSBCFG_TOCAL_0 (0x1U << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000001 */ #define USB_OTG_GUSBCFG_TOCAL_1 (0x2U << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000002 */ #define USB_OTG_GUSBCFG_TOCAL_2 (0x4U << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000004 */ #define USB_OTG_GUSBCFG_PHYSEL_Pos (6U) #define USB_OTG_GUSBCFG_PHYSEL_Msk (0x1U << USB_OTG_GUSBCFG_PHYSEL_Pos) /*!< 0x00000040 */ #define USB_OTG_GUSBCFG_PHYSEL USB_OTG_GUSBCFG_PHYSEL_Msk /*!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */ #define USB_OTG_GUSBCFG_SRPCAP_Pos (8U) #define USB_OTG_GUSBCFG_SRPCAP_Msk (0x1U << USB_OTG_GUSBCFG_SRPCAP_Pos) /*!< 0x00000100 */ #define USB_OTG_GUSBCFG_SRPCAP USB_OTG_GUSBCFG_SRPCAP_Msk /*!< SRP-capable */ #define USB_OTG_GUSBCFG_HNPCAP_Pos (9U) #define USB_OTG_GUSBCFG_HNPCAP_Msk (0x1U << USB_OTG_GUSBCFG_HNPCAP_Pos) /*!< 0x00000200 */ #define USB_OTG_GUSBCFG_HNPCAP USB_OTG_GUSBCFG_HNPCAP_Msk /*!< HNP-capable */ #define USB_OTG_GUSBCFG_TRDT_Pos (10U) #define USB_OTG_GUSBCFG_TRDT_Msk (0xFU << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00003C00 */ #define USB_OTG_GUSBCFG_TRDT USB_OTG_GUSBCFG_TRDT_Msk /*!< USB turnaround time */ #define USB_OTG_GUSBCFG_TRDT_0 (0x1U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000400 */ #define USB_OTG_GUSBCFG_TRDT_1 (0x2U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000800 */ #define USB_OTG_GUSBCFG_TRDT_2 (0x4U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00001000 */ #define USB_OTG_GUSBCFG_TRDT_3 (0x8U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00002000 */ #define USB_OTG_GUSBCFG_PHYLPCS_Pos (15U) #define USB_OTG_GUSBCFG_PHYLPCS_Msk (0x1U << USB_OTG_GUSBCFG_PHYLPCS_Pos) /*!< 0x00008000 */ #define USB_OTG_GUSBCFG_PHYLPCS USB_OTG_GUSBCFG_PHYLPCS_Msk /*!< PHY Low-power clock select */ #define USB_OTG_GUSBCFG_ULPIFSLS_Pos (17U) #define USB_OTG_GUSBCFG_ULPIFSLS_Msk (0x1U << USB_OTG_GUSBCFG_ULPIFSLS_Pos) /*!< 0x00020000 */ #define USB_OTG_GUSBCFG_ULPIFSLS USB_OTG_GUSBCFG_ULPIFSLS_Msk /*!< ULPI FS/LS select */ #define USB_OTG_GUSBCFG_ULPIAR_Pos (18U) #define USB_OTG_GUSBCFG_ULPIAR_Msk (0x1U << USB_OTG_GUSBCFG_ULPIAR_Pos) /*!< 0x00040000 */ #define USB_OTG_GUSBCFG_ULPIAR USB_OTG_GUSBCFG_ULPIAR_Msk /*!< ULPI Auto-resume */ #define USB_OTG_GUSBCFG_ULPICSM_Pos (19U) #define USB_OTG_GUSBCFG_ULPICSM_Msk (0x1U << USB_OTG_GUSBCFG_ULPICSM_Pos) /*!< 0x00080000 */ #define USB_OTG_GUSBCFG_ULPICSM USB_OTG_GUSBCFG_ULPICSM_Msk /*!< ULPI Clock SuspendM */ #define USB_OTG_GUSBCFG_ULPIEVBUSD_Pos (20U) #define USB_OTG_GUSBCFG_ULPIEVBUSD_Msk (0x1U << USB_OTG_GUSBCFG_ULPIEVBUSD_Pos) /*!< 0x00100000 */ #define USB_OTG_GUSBCFG_ULPIEVBUSD USB_OTG_GUSBCFG_ULPIEVBUSD_Msk /*!< ULPI External VBUS Drive */ #define USB_OTG_GUSBCFG_ULPIEVBUSI_Pos (21U) #define USB_OTG_GUSBCFG_ULPIEVBUSI_Msk (0x1U << USB_OTG_GUSBCFG_ULPIEVBUSI_Pos) /*!< 0x00200000 */ #define USB_OTG_GUSBCFG_ULPIEVBUSI USB_OTG_GUSBCFG_ULPIEVBUSI_Msk /*!< ULPI external VBUS indicator */ #define USB_OTG_GUSBCFG_TSDPS_Pos (22U) #define USB_OTG_GUSBCFG_TSDPS_Msk (0x1U << USB_OTG_GUSBCFG_TSDPS_Pos) /*!< 0x00400000 */ #define USB_OTG_GUSBCFG_TSDPS USB_OTG_GUSBCFG_TSDPS_Msk /*!< TermSel DLine pulsing selection */ #define USB_OTG_GUSBCFG_PCCI_Pos (23U) #define USB_OTG_GUSBCFG_PCCI_Msk (0x1U << USB_OTG_GUSBCFG_PCCI_Pos) /*!< 0x00800000 */ #define USB_OTG_GUSBCFG_PCCI USB_OTG_GUSBCFG_PCCI_Msk /*!< Indicator complement */ #define USB_OTG_GUSBCFG_PTCI_Pos (24U) #define USB_OTG_GUSBCFG_PTCI_Msk (0x1U << USB_OTG_GUSBCFG_PTCI_Pos) /*!< 0x01000000 */ #define USB_OTG_GUSBCFG_PTCI USB_OTG_GUSBCFG_PTCI_Msk /*!< Indicator pass through */ #define USB_OTG_GUSBCFG_ULPIIPD_Pos (25U) #define USB_OTG_GUSBCFG_ULPIIPD_Msk (0x1U << USB_OTG_GUSBCFG_ULPIIPD_Pos) /*!< 0x02000000 */ #define USB_OTG_GUSBCFG_ULPIIPD USB_OTG_GUSBCFG_ULPIIPD_Msk /*!< ULPI interface protect disable */ #define USB_OTG_GUSBCFG_FHMOD_Pos (29U) #define USB_OTG_GUSBCFG_FHMOD_Msk (0x1U << USB_OTG_GUSBCFG_FHMOD_Pos) /*!< 0x20000000 */ #define USB_OTG_GUSBCFG_FHMOD USB_OTG_GUSBCFG_FHMOD_Msk /*!< Forced host mode */ #define USB_OTG_GUSBCFG_FDMOD_Pos (30U) #define USB_OTG_GUSBCFG_FDMOD_Msk (0x1U << USB_OTG_GUSBCFG_FDMOD_Pos) /*!< 0x40000000 */ #define USB_OTG_GUSBCFG_FDMOD USB_OTG_GUSBCFG_FDMOD_Msk /*!< Forced peripheral mode */ #define USB_OTG_GUSBCFG_CTXPKT_Pos (31U) #define USB_OTG_GUSBCFG_CTXPKT_Msk (0x1U << USB_OTG_GUSBCFG_CTXPKT_Pos) /*!< 0x80000000 */ #define USB_OTG_GUSBCFG_CTXPKT USB_OTG_GUSBCFG_CTXPKT_Msk /*!< Corrupt Tx packet */ /******************** Bit definition for USB_OTG_GRSTCTL register ********************/ #define USB_OTG_GRSTCTL_CSRST_Pos (0U) #define USB_OTG_GRSTCTL_CSRST_Msk (0x1U << USB_OTG_GRSTCTL_CSRST_Pos) /*!< 0x00000001 */ #define USB_OTG_GRSTCTL_CSRST USB_OTG_GRSTCTL_CSRST_Msk /*!< Core soft reset */ #define USB_OTG_GRSTCTL_HSRST_Pos (1U) #define USB_OTG_GRSTCTL_HSRST_Msk (0x1U << USB_OTG_GRSTCTL_HSRST_Pos) /*!< 0x00000002 */ #define USB_OTG_GRSTCTL_HSRST USB_OTG_GRSTCTL_HSRST_Msk /*!< HCLK soft reset */ #define USB_OTG_GRSTCTL_FCRST_Pos (2U) #define USB_OTG_GRSTCTL_FCRST_Msk (0x1U << USB_OTG_GRSTCTL_FCRST_Pos) /*!< 0x00000004 */ #define USB_OTG_GRSTCTL_FCRST USB_OTG_GRSTCTL_FCRST_Msk /*!< Host frame counter reset */ #define USB_OTG_GRSTCTL_RXFFLSH_Pos (4U) #define USB_OTG_GRSTCTL_RXFFLSH_Msk (0x1U << USB_OTG_GRSTCTL_RXFFLSH_Pos) /*!< 0x00000010 */ #define USB_OTG_GRSTCTL_RXFFLSH USB_OTG_GRSTCTL_RXFFLSH_Msk /*!< RxFIFO flush */ #define USB_OTG_GRSTCTL_TXFFLSH_Pos (5U) #define USB_OTG_GRSTCTL_TXFFLSH_Msk (0x1U << USB_OTG_GRSTCTL_TXFFLSH_Pos) /*!< 0x00000020 */ #define USB_OTG_GRSTCTL_TXFFLSH USB_OTG_GRSTCTL_TXFFLSH_Msk /*!< TxFIFO flush */ #define USB_OTG_GRSTCTL_TXFNUM_Pos (6U) #define USB_OTG_GRSTCTL_TXFNUM_Msk (0x1FU << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x000007C0 */ #define USB_OTG_GRSTCTL_TXFNUM USB_OTG_GRSTCTL_TXFNUM_Msk /*!< TxFIFO number */ #define USB_OTG_GRSTCTL_TXFNUM_0 (0x01U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000040 */ #define USB_OTG_GRSTCTL_TXFNUM_1 (0x02U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000080 */ #define USB_OTG_GRSTCTL_TXFNUM_2 (0x04U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000100 */ #define USB_OTG_GRSTCTL_TXFNUM_3 (0x08U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000200 */ #define USB_OTG_GRSTCTL_TXFNUM_4 (0x10U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000400 */ #define USB_OTG_GRSTCTL_DMAREQ_Pos (30U) #define USB_OTG_GRSTCTL_DMAREQ_Msk (0x1U << USB_OTG_GRSTCTL_DMAREQ_Pos) /*!< 0x40000000 */ #define USB_OTG_GRSTCTL_DMAREQ USB_OTG_GRSTCTL_DMAREQ_Msk /*!< DMA request signal */ #define USB_OTG_GRSTCTL_AHBIDL_Pos (31U) #define USB_OTG_GRSTCTL_AHBIDL_Msk (0x1U << USB_OTG_GRSTCTL_AHBIDL_Pos) /*!< 0x80000000 */ #define USB_OTG_GRSTCTL_AHBIDL USB_OTG_GRSTCTL_AHBIDL_Msk /*!< AHB master idle */ /******************** Bit definition for USB_OTG_DIEPMSK register ********************/ #define USB_OTG_DIEPMSK_XFRCM_Pos (0U) #define USB_OTG_DIEPMSK_XFRCM_Msk (0x1U << USB_OTG_DIEPMSK_XFRCM_Pos) /*!< 0x00000001 */ #define USB_OTG_DIEPMSK_XFRCM USB_OTG_DIEPMSK_XFRCM_Msk /*!< Transfer completed interrupt mask */ #define USB_OTG_DIEPMSK_EPDM_Pos (1U) #define USB_OTG_DIEPMSK_EPDM_Msk (0x1U << USB_OTG_DIEPMSK_EPDM_Pos) /*!< 0x00000002 */ #define USB_OTG_DIEPMSK_EPDM USB_OTG_DIEPMSK_EPDM_Msk /*!< Endpoint disabled interrupt mask */ #define USB_OTG_DIEPMSK_TOM_Pos (3U) #define USB_OTG_DIEPMSK_TOM_Msk (0x1U << USB_OTG_DIEPMSK_TOM_Pos) /*!< 0x00000008 */ #define USB_OTG_DIEPMSK_TOM USB_OTG_DIEPMSK_TOM_Msk /*!< Timeout condition mask (nonisochronous endpoints) */ #define USB_OTG_DIEPMSK_ITTXFEMSK_Pos (4U) #define USB_OTG_DIEPMSK_ITTXFEMSK_Msk (0x1U << USB_OTG_DIEPMSK_ITTXFEMSK_Pos) /*!< 0x00000010 */ #define USB_OTG_DIEPMSK_ITTXFEMSK USB_OTG_DIEPMSK_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */ #define USB_OTG_DIEPMSK_INEPNMM_Pos (5U) #define USB_OTG_DIEPMSK_INEPNMM_Msk (0x1U << USB_OTG_DIEPMSK_INEPNMM_Pos) /*!< 0x00000020 */ #define USB_OTG_DIEPMSK_INEPNMM USB_OTG_DIEPMSK_INEPNMM_Msk /*!< IN token received with EP mismatch mask */ #define USB_OTG_DIEPMSK_INEPNEM_Pos (6U) #define USB_OTG_DIEPMSK_INEPNEM_Msk (0x1U << USB_OTG_DIEPMSK_INEPNEM_Pos) /*!< 0x00000040 */ #define USB_OTG_DIEPMSK_INEPNEM USB_OTG_DIEPMSK_INEPNEM_Msk /*!< IN endpoint NAK effective mask */ #define USB_OTG_DIEPMSK_TXFURM_Pos (8U) #define USB_OTG_DIEPMSK_TXFURM_Msk (0x1U << USB_OTG_DIEPMSK_TXFURM_Pos) /*!< 0x00000100 */ #define USB_OTG_DIEPMSK_TXFURM USB_OTG_DIEPMSK_TXFURM_Msk /*!< FIFO underrun mask */ #define USB_OTG_DIEPMSK_BIM_Pos (9U) #define USB_OTG_DIEPMSK_BIM_Msk (0x1U << USB_OTG_DIEPMSK_BIM_Pos) /*!< 0x00000200 */ #define USB_OTG_DIEPMSK_BIM USB_OTG_DIEPMSK_BIM_Msk /*!< BNA interrupt mask */ /******************** Bit definition for USB_OTG_HPTXSTS register ********************/ #define USB_OTG_HPTXSTS_PTXFSAVL_Pos (0U) #define USB_OTG_HPTXSTS_PTXFSAVL_Msk (0xFFFFU << USB_OTG_HPTXSTS_PTXFSAVL_Pos) /*!< 0x0000FFFF */ #define USB_OTG_HPTXSTS_PTXFSAVL USB_OTG_HPTXSTS_PTXFSAVL_Msk /*!< Periodic transmit data FIFO space available */ #define USB_OTG_HPTXSTS_PTXQSAV_Pos (16U) #define USB_OTG_HPTXSTS_PTXQSAV_Msk (0xFFU << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00FF0000 */ #define USB_OTG_HPTXSTS_PTXQSAV USB_OTG_HPTXSTS_PTXQSAV_Msk /*!< Periodic transmit request queue space available */ #define USB_OTG_HPTXSTS_PTXQSAV_0 (0x01U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00010000 */ #define USB_OTG_HPTXSTS_PTXQSAV_1 (0x02U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00020000 */ #define USB_OTG_HPTXSTS_PTXQSAV_2 (0x04U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00040000 */ #define USB_OTG_HPTXSTS_PTXQSAV_3 (0x08U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00080000 */ #define USB_OTG_HPTXSTS_PTXQSAV_4 (0x10U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00100000 */ #define USB_OTG_HPTXSTS_PTXQSAV_5 (0x20U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00200000 */ #define USB_OTG_HPTXSTS_PTXQSAV_6 (0x40U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00400000 */ #define USB_OTG_HPTXSTS_PTXQSAV_7 (0x80U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00800000 */ #define USB_OTG_HPTXSTS_PTXQTOP_Pos (24U) #define USB_OTG_HPTXSTS_PTXQTOP_Msk (0xFFU << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0xFF000000 */ #define USB_OTG_HPTXSTS_PTXQTOP USB_OTG_HPTXSTS_PTXQTOP_Msk /*!< Top of the periodic transmit request queue */ #define USB_OTG_HPTXSTS_PTXQTOP_0 (0x01U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x01000000 */ #define USB_OTG_HPTXSTS_PTXQTOP_1 (0x02U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x02000000 */ #define USB_OTG_HPTXSTS_PTXQTOP_2 (0x04U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x04000000 */ #define USB_OTG_HPTXSTS_PTXQTOP_3 (0x08U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x08000000 */ #define USB_OTG_HPTXSTS_PTXQTOP_4 (0x10U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x10000000 */ #define USB_OTG_HPTXSTS_PTXQTOP_5 (0x20U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x20000000 */ #define USB_OTG_HPTXSTS_PTXQTOP_6 (0x40U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x40000000 */ #define USB_OTG_HPTXSTS_PTXQTOP_7 (0x80U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x80000000 */ /******************** Bit definition for USB_OTG_HAINT register ********************/ #define USB_OTG_HAINT_HAINT_Pos (0U) #define USB_OTG_HAINT_HAINT_Msk (0xFFFFU << USB_OTG_HAINT_HAINT_Pos) /*!< 0x0000FFFF */ #define USB_OTG_HAINT_HAINT USB_OTG_HAINT_HAINT_Msk /*!< Channel interrupts */ /******************** Bit definition for USB_OTG_DOEPMSK register ********************/ #define USB_OTG_DOEPMSK_XFRCM_Pos (0U) #define USB_OTG_DOEPMSK_XFRCM_Msk (0x1U << USB_OTG_DOEPMSK_XFRCM_Pos) /*!< 0x00000001 */ #define USB_OTG_DOEPMSK_XFRCM USB_OTG_DOEPMSK_XFRCM_Msk /*!< Transfer completed interrupt mask */ #define USB_OTG_DOEPMSK_EPDM_Pos (1U) #define USB_OTG_DOEPMSK_EPDM_Msk (0x1U << USB_OTG_DOEPMSK_EPDM_Pos) /*!< 0x00000002 */ #define USB_OTG_DOEPMSK_EPDM USB_OTG_DOEPMSK_EPDM_Msk /*!< Endpoint disabled interrupt mask */ #define USB_OTG_DOEPMSK_STUPM_Pos (3U) #define USB_OTG_DOEPMSK_STUPM_Msk (0x1U << USB_OTG_DOEPMSK_STUPM_Pos) /*!< 0x00000008 */ #define USB_OTG_DOEPMSK_STUPM USB_OTG_DOEPMSK_STUPM_Msk /*!< SETUP phase done mask */ #define USB_OTG_DOEPMSK_OTEPDM_Pos (4U) #define USB_OTG_DOEPMSK_OTEPDM_Msk (0x1U << USB_OTG_DOEPMSK_OTEPDM_Pos) /*!< 0x00000010 */ #define USB_OTG_DOEPMSK_OTEPDM USB_OTG_DOEPMSK_OTEPDM_Msk /*!< OUT token received when endpoint disabled mask */ #define USB_OTG_DOEPMSK_OTEPSPRM_Pos (5U) #define USB_OTG_DOEPMSK_OTEPSPRM_Msk (0x1U << USB_OTG_DOEPMSK_OTEPSPRM_Pos) /*!< 0x00000020 */ #define USB_OTG_DOEPMSK_OTEPSPRM USB_OTG_DOEPMSK_OTEPSPRM_Msk /*!< Status Phase Received mask */ #define USB_OTG_DOEPMSK_B2BSTUP_Pos (6U) #define USB_OTG_DOEPMSK_B2BSTUP_Msk (0x1U << USB_OTG_DOEPMSK_B2BSTUP_Pos) /*!< 0x00000040 */ #define USB_OTG_DOEPMSK_B2BSTUP USB_OTG_DOEPMSK_B2BSTUP_Msk /*!< Back-to-back SETUP packets received mask */ #define USB_OTG_DOEPMSK_OPEM_Pos (8U) #define USB_OTG_DOEPMSK_OPEM_Msk (0x1U << USB_OTG_DOEPMSK_OPEM_Pos) /*!< 0x00000100 */ #define USB_OTG_DOEPMSK_OPEM USB_OTG_DOEPMSK_OPEM_Msk /*!< OUT packet error mask */ #define USB_OTG_DOEPMSK_BOIM_Pos (9U) #define USB_OTG_DOEPMSK_BOIM_Msk (0x1U << USB_OTG_DOEPMSK_BOIM_Pos) /*!< 0x00000200 */ #define USB_OTG_DOEPMSK_BOIM USB_OTG_DOEPMSK_BOIM_Msk /*!< BNA interrupt mask */ /******************** Bit definition for USB_OTG_GINTSTS register ********************/ #define USB_OTG_GINTSTS_CMOD_Pos (0U) #define USB_OTG_GINTSTS_CMOD_Msk (0x1U << USB_OTG_GINTSTS_CMOD_Pos) /*!< 0x00000001 */ #define USB_OTG_GINTSTS_CMOD USB_OTG_GINTSTS_CMOD_Msk /*!< Current mode of operation */ #define USB_OTG_GINTSTS_MMIS_Pos (1U) #define USB_OTG_GINTSTS_MMIS_Msk (0x1U << USB_OTG_GINTSTS_MMIS_Pos) /*!< 0x00000002 */ #define USB_OTG_GINTSTS_MMIS USB_OTG_GINTSTS_MMIS_Msk /*!< Mode mismatch interrupt */ #define USB_OTG_GINTSTS_OTGINT_Pos (2U) #define USB_OTG_GINTSTS_OTGINT_Msk (0x1U << USB_OTG_GINTSTS_OTGINT_Pos) /*!< 0x00000004 */ #define USB_OTG_GINTSTS_OTGINT USB_OTG_GINTSTS_OTGINT_Msk /*!< OTG interrupt */ #define USB_OTG_GINTSTS_SOF_Pos (3U) #define USB_OTG_GINTSTS_SOF_Msk (0x1U << USB_OTG_GINTSTS_SOF_Pos) /*!< 0x00000008 */ #define USB_OTG_GINTSTS_SOF USB_OTG_GINTSTS_SOF_Msk /*!< Start of frame */ #define USB_OTG_GINTSTS_RXFLVL_Pos (4U) #define USB_OTG_GINTSTS_RXFLVL_Msk (0x1U << USB_OTG_GINTSTS_RXFLVL_Pos) /*!< 0x00000010 */ #define USB_OTG_GINTSTS_RXFLVL USB_OTG_GINTSTS_RXFLVL_Msk /*!< RxFIFO nonempty */ #define USB_OTG_GINTSTS_NPTXFE_Pos (5U) #define USB_OTG_GINTSTS_NPTXFE_Msk (0x1U << USB_OTG_GINTSTS_NPTXFE_Pos) /*!< 0x00000020 */ #define USB_OTG_GINTSTS_NPTXFE USB_OTG_GINTSTS_NPTXFE_Msk /*!< Nonperiodic TxFIFO empty */ #define USB_OTG_GINTSTS_GINAKEFF_Pos (6U) #define USB_OTG_GINTSTS_GINAKEFF_Msk (0x1U << USB_OTG_GINTSTS_GINAKEFF_Pos) /*!< 0x00000040 */ #define USB_OTG_GINTSTS_GINAKEFF USB_OTG_GINTSTS_GINAKEFF_Msk /*!< Global IN nonperiodic NAK effective */ #define USB_OTG_GINTSTS_BOUTNAKEFF_Pos (7U) #define USB_OTG_GINTSTS_BOUTNAKEFF_Msk (0x1U << USB_OTG_GINTSTS_BOUTNAKEFF_Pos) /*!< 0x00000080 */ #define USB_OTG_GINTSTS_BOUTNAKEFF USB_OTG_GINTSTS_BOUTNAKEFF_Msk /*!< Global OUT NAK effective */ #define USB_OTG_GINTSTS_ESUSP_Pos (10U) #define USB_OTG_GINTSTS_ESUSP_Msk (0x1U << USB_OTG_GINTSTS_ESUSP_Pos) /*!< 0x00000400 */ #define USB_OTG_GINTSTS_ESUSP USB_OTG_GINTSTS_ESUSP_Msk /*!< Early suspend */ #define USB_OTG_GINTSTS_USBSUSP_Pos (11U) #define USB_OTG_GINTSTS_USBSUSP_Msk (0x1U << USB_OTG_GINTSTS_USBSUSP_Pos) /*!< 0x00000800 */ #define USB_OTG_GINTSTS_USBSUSP USB_OTG_GINTSTS_USBSUSP_Msk /*!< USB suspend */ #define USB_OTG_GINTSTS_USBRST_Pos (12U) #define USB_OTG_GINTSTS_USBRST_Msk (0x1U << USB_OTG_GINTSTS_USBRST_Pos) /*!< 0x00001000 */ #define USB_OTG_GINTSTS_USBRST USB_OTG_GINTSTS_USBRST_Msk /*!< USB reset */ #define USB_OTG_GINTSTS_ENUMDNE_Pos (13U) #define USB_OTG_GINTSTS_ENUMDNE_Msk (0x1U << USB_OTG_GINTSTS_ENUMDNE_Pos) /*!< 0x00002000 */ #define USB_OTG_GINTSTS_ENUMDNE USB_OTG_GINTSTS_ENUMDNE_Msk /*!< Enumeration done */ #define USB_OTG_GINTSTS_ISOODRP_Pos (14U) #define USB_OTG_GINTSTS_ISOODRP_Msk (0x1U << USB_OTG_GINTSTS_ISOODRP_Pos) /*!< 0x00004000 */ #define USB_OTG_GINTSTS_ISOODRP USB_OTG_GINTSTS_ISOODRP_Msk /*!< Isochronous OUT packet dropped interrupt */ #define USB_OTG_GINTSTS_EOPF_Pos (15U) #define USB_OTG_GINTSTS_EOPF_Msk (0x1U << USB_OTG_GINTSTS_EOPF_Pos) /*!< 0x00008000 */ #define USB_OTG_GINTSTS_EOPF USB_OTG_GINTSTS_EOPF_Msk /*!< End of periodic frame interrupt */ #define USB_OTG_GINTSTS_IEPINT_Pos (18U) #define USB_OTG_GINTSTS_IEPINT_Msk (0x1U << USB_OTG_GINTSTS_IEPINT_Pos) /*!< 0x00040000 */ #define USB_OTG_GINTSTS_IEPINT USB_OTG_GINTSTS_IEPINT_Msk /*!< IN endpoint interrupt */ #define USB_OTG_GINTSTS_OEPINT_Pos (19U) #define USB_OTG_GINTSTS_OEPINT_Msk (0x1U << USB_OTG_GINTSTS_OEPINT_Pos) /*!< 0x00080000 */ #define USB_OTG_GINTSTS_OEPINT USB_OTG_GINTSTS_OEPINT_Msk /*!< OUT endpoint interrupt */ #define USB_OTG_GINTSTS_IISOIXFR_Pos (20U) #define USB_OTG_GINTSTS_IISOIXFR_Msk (0x1U << USB_OTG_GINTSTS_IISOIXFR_Pos) /*!< 0x00100000 */ #define USB_OTG_GINTSTS_IISOIXFR USB_OTG_GINTSTS_IISOIXFR_Msk /*!< Incomplete isochronous IN transfer */ #define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos (21U) #define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk (0x1U << USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos) /*!< 0x00200000 */ #define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk /*!< Incomplete periodic transfer */ #define USB_OTG_GINTSTS_DATAFSUSP_Pos (22U) #define USB_OTG_GINTSTS_DATAFSUSP_Msk (0x1U << USB_OTG_GINTSTS_DATAFSUSP_Pos) /*!< 0x00400000 */ #define USB_OTG_GINTSTS_DATAFSUSP USB_OTG_GINTSTS_DATAFSUSP_Msk /*!< Data fetch suspended */ #define USB_OTG_GINTSTS_RSTDET_Pos (23U) #define USB_OTG_GINTSTS_RSTDET_Msk (0x1U << USB_OTG_GINTSTS_RSTDET_Pos) /*!< 0x00800000 */ #define USB_OTG_GINTSTS_RSTDET USB_OTG_GINTSTS_RSTDET_Msk /*!< Reset detected interrupt */ #define USB_OTG_GINTSTS_HPRTINT_Pos (24U) #define USB_OTG_GINTSTS_HPRTINT_Msk (0x1U << USB_OTG_GINTSTS_HPRTINT_Pos) /*!< 0x01000000 */ #define USB_OTG_GINTSTS_HPRTINT USB_OTG_GINTSTS_HPRTINT_Msk /*!< Host port interrupt */ #define USB_OTG_GINTSTS_HCINT_Pos (25U) #define USB_OTG_GINTSTS_HCINT_Msk (0x1U << USB_OTG_GINTSTS_HCINT_Pos) /*!< 0x02000000 */ #define USB_OTG_GINTSTS_HCINT USB_OTG_GINTSTS_HCINT_Msk /*!< Host channels interrupt */ #define USB_OTG_GINTSTS_PTXFE_Pos (26U) #define USB_OTG_GINTSTS_PTXFE_Msk (0x1U << USB_OTG_GINTSTS_PTXFE_Pos) /*!< 0x04000000 */ #define USB_OTG_GINTSTS_PTXFE USB_OTG_GINTSTS_PTXFE_Msk /*!< Periodic TxFIFO empty */ #define USB_OTG_GINTSTS_LPMINT_Pos (27U) #define USB_OTG_GINTSTS_LPMINT_Msk (0x1U << USB_OTG_GINTSTS_LPMINT_Pos) /*!< 0x08000000 */ #define USB_OTG_GINTSTS_LPMINT USB_OTG_GINTSTS_LPMINT_Msk /*!< LPM interrupt */ #define USB_OTG_GINTSTS_CIDSCHG_Pos (28U) #define USB_OTG_GINTSTS_CIDSCHG_Msk (0x1U << USB_OTG_GINTSTS_CIDSCHG_Pos) /*!< 0x10000000 */ #define USB_OTG_GINTSTS_CIDSCHG USB_OTG_GINTSTS_CIDSCHG_Msk /*!< Connector ID status change */ #define USB_OTG_GINTSTS_DISCINT_Pos (29U) #define USB_OTG_GINTSTS_DISCINT_Msk (0x1U << USB_OTG_GINTSTS_DISCINT_Pos) /*!< 0x20000000 */ #define USB_OTG_GINTSTS_DISCINT USB_OTG_GINTSTS_DISCINT_Msk /*!< Disconnect detected interrupt */ #define USB_OTG_GINTSTS_SRQINT_Pos (30U) #define USB_OTG_GINTSTS_SRQINT_Msk (0x1U << USB_OTG_GINTSTS_SRQINT_Pos) /*!< 0x40000000 */ #define USB_OTG_GINTSTS_SRQINT USB_OTG_GINTSTS_SRQINT_Msk /*!< Session request/new session detected interrupt */ #define USB_OTG_GINTSTS_WKUINT_Pos (31U) #define USB_OTG_GINTSTS_WKUINT_Msk (0x1U << USB_OTG_GINTSTS_WKUINT_Pos) /*!< 0x80000000 */ #define USB_OTG_GINTSTS_WKUINT USB_OTG_GINTSTS_WKUINT_Msk /*!< Resume/remote wakeup detected interrupt */ /******************** Bit definition for USB_OTG_GINTMSK register ********************/ #define USB_OTG_GINTMSK_MMISM_Pos (1U) #define USB_OTG_GINTMSK_MMISM_Msk (0x1U << USB_OTG_GINTMSK_MMISM_Pos) /*!< 0x00000002 */ #define USB_OTG_GINTMSK_MMISM USB_OTG_GINTMSK_MMISM_Msk /*!< Mode mismatch interrupt mask */ #define USB_OTG_GINTMSK_OTGINT_Pos (2U) #define USB_OTG_GINTMSK_OTGINT_Msk (0x1U << USB_OTG_GINTMSK_OTGINT_Pos) /*!< 0x00000004 */ #define USB_OTG_GINTMSK_OTGINT USB_OTG_GINTMSK_OTGINT_Msk /*!< OTG interrupt mask */ #define USB_OTG_GINTMSK_SOFM_Pos (3U) #define USB_OTG_GINTMSK_SOFM_Msk (0x1U << USB_OTG_GINTMSK_SOFM_Pos) /*!< 0x00000008 */ #define USB_OTG_GINTMSK_SOFM USB_OTG_GINTMSK_SOFM_Msk /*!< Start of frame mask */ #define USB_OTG_GINTMSK_RXFLVLM_Pos (4U) #define USB_OTG_GINTMSK_RXFLVLM_Msk (0x1U << USB_OTG_GINTMSK_RXFLVLM_Pos) /*!< 0x00000010 */ #define USB_OTG_GINTMSK_RXFLVLM USB_OTG_GINTMSK_RXFLVLM_Msk /*!< Receive FIFO nonempty mask */ #define USB_OTG_GINTMSK_NPTXFEM_Pos (5U) #define USB_OTG_GINTMSK_NPTXFEM_Msk (0x1U << USB_OTG_GINTMSK_NPTXFEM_Pos) /*!< 0x00000020 */ #define USB_OTG_GINTMSK_NPTXFEM USB_OTG_GINTMSK_NPTXFEM_Msk /*!< Nonperiodic TxFIFO empty mask */ #define USB_OTG_GINTMSK_GINAKEFFM_Pos (6U) #define USB_OTG_GINTMSK_GINAKEFFM_Msk (0x1U << USB_OTG_GINTMSK_GINAKEFFM_Pos) /*!< 0x00000040 */ #define USB_OTG_GINTMSK_GINAKEFFM USB_OTG_GINTMSK_GINAKEFFM_Msk /*!< Global nonperiodic IN NAK effective mask */ #define USB_OTG_GINTMSK_GONAKEFFM_Pos (7U) #define USB_OTG_GINTMSK_GONAKEFFM_Msk (0x1U << USB_OTG_GINTMSK_GONAKEFFM_Pos) /*!< 0x00000080 */ #define USB_OTG_GINTMSK_GONAKEFFM USB_OTG_GINTMSK_GONAKEFFM_Msk /*!< Global OUT NAK effective mask */ #define USB_OTG_GINTMSK_ESUSPM_Pos (10U) #define USB_OTG_GINTMSK_ESUSPM_Msk (0x1U << USB_OTG_GINTMSK_ESUSPM_Pos) /*!< 0x00000400 */ #define USB_OTG_GINTMSK_ESUSPM USB_OTG_GINTMSK_ESUSPM_Msk /*!< Early suspend mask */ #define USB_OTG_GINTMSK_USBSUSPM_Pos (11U) #define USB_OTG_GINTMSK_USBSUSPM_Msk (0x1U << USB_OTG_GINTMSK_USBSUSPM_Pos) /*!< 0x00000800 */ #define USB_OTG_GINTMSK_USBSUSPM USB_OTG_GINTMSK_USBSUSPM_Msk /*!< USB suspend mask */ #define USB_OTG_GINTMSK_USBRST_Pos (12U) #define USB_OTG_GINTMSK_USBRST_Msk (0x1U << USB_OTG_GINTMSK_USBRST_Pos) /*!< 0x00001000 */ #define USB_OTG_GINTMSK_USBRST USB_OTG_GINTMSK_USBRST_Msk /*!< USB reset mask */ #define USB_OTG_GINTMSK_ENUMDNEM_Pos (13U) #define USB_OTG_GINTMSK_ENUMDNEM_Msk (0x1U << USB_OTG_GINTMSK_ENUMDNEM_Pos) /*!< 0x00002000 */ #define USB_OTG_GINTMSK_ENUMDNEM USB_OTG_GINTMSK_ENUMDNEM_Msk /*!< Enumeration done mask */ #define USB_OTG_GINTMSK_ISOODRPM_Pos (14U) #define USB_OTG_GINTMSK_ISOODRPM_Msk (0x1U << USB_OTG_GINTMSK_ISOODRPM_Pos) /*!< 0x00004000 */ #define USB_OTG_GINTMSK_ISOODRPM USB_OTG_GINTMSK_ISOODRPM_Msk /*!< Isochronous OUT packet dropped interrupt mask */ #define USB_OTG_GINTMSK_EOPFM_Pos (15U) #define USB_OTG_GINTMSK_EOPFM_Msk (0x1U << USB_OTG_GINTMSK_EOPFM_Pos) /*!< 0x00008000 */ #define USB_OTG_GINTMSK_EOPFM USB_OTG_GINTMSK_EOPFM_Msk /*!< End of periodic frame interrupt mask */ #define USB_OTG_GINTMSK_EPMISM_Pos (17U) #define USB_OTG_GINTMSK_EPMISM_Msk (0x1U << USB_OTG_GINTMSK_EPMISM_Pos) /*!< 0x00020000 */ #define USB_OTG_GINTMSK_EPMISM USB_OTG_GINTMSK_EPMISM_Msk /*!< Endpoint mismatch interrupt mask */ #define USB_OTG_GINTMSK_IEPINT_Pos (18U) #define USB_OTG_GINTMSK_IEPINT_Msk (0x1U << USB_OTG_GINTMSK_IEPINT_Pos) /*!< 0x00040000 */ #define USB_OTG_GINTMSK_IEPINT USB_OTG_GINTMSK_IEPINT_Msk /*!< IN endpoints interrupt mask */ #define USB_OTG_GINTMSK_OEPINT_Pos (19U) #define USB_OTG_GINTMSK_OEPINT_Msk (0x1U << USB_OTG_GINTMSK_OEPINT_Pos) /*!< 0x00080000 */ #define USB_OTG_GINTMSK_OEPINT USB_OTG_GINTMSK_OEPINT_Msk /*!< OUT endpoints interrupt mask */ #define USB_OTG_GINTMSK_IISOIXFRM_Pos (20U) #define USB_OTG_GINTMSK_IISOIXFRM_Msk (0x1U << USB_OTG_GINTMSK_IISOIXFRM_Pos) /*!< 0x00100000 */ #define USB_OTG_GINTMSK_IISOIXFRM USB_OTG_GINTMSK_IISOIXFRM_Msk /*!< Incomplete isochronous IN transfer mask */ #define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos (21U) #define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk (0x1U << USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos) /*!< 0x00200000 */ #define USB_OTG_GINTMSK_PXFRM_IISOOXFRM USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk /*!< Incomplete periodic transfer mask */ #define USB_OTG_GINTMSK_FSUSPM_Pos (22U) #define USB_OTG_GINTMSK_FSUSPM_Msk (0x1U << USB_OTG_GINTMSK_FSUSPM_Pos) /*!< 0x00400000 */ #define USB_OTG_GINTMSK_FSUSPM USB_OTG_GINTMSK_FSUSPM_Msk /*!< Data fetch suspended mask */ #define USB_OTG_GINTMSK_RSTDEM_Pos (23U) #define USB_OTG_GINTMSK_RSTDEM_Msk (0x1U << USB_OTG_GINTMSK_RSTDEM_Pos) /*!< 0x00800000 */ #define USB_OTG_GINTMSK_RSTDEM USB_OTG_GINTMSK_RSTDEM_Msk /*!< Reset detected interrupt mask */ #define USB_OTG_GINTMSK_PRTIM_Pos (24U) #define USB_OTG_GINTMSK_PRTIM_Msk (0x1U << USB_OTG_GINTMSK_PRTIM_Pos) /*!< 0x01000000 */ #define USB_OTG_GINTMSK_PRTIM USB_OTG_GINTMSK_PRTIM_Msk /*!< Host port interrupt mask */ #define USB_OTG_GINTMSK_HCIM_Pos (25U) #define USB_OTG_GINTMSK_HCIM_Msk (0x1U << USB_OTG_GINTMSK_HCIM_Pos) /*!< 0x02000000 */ #define USB_OTG_GINTMSK_HCIM USB_OTG_GINTMSK_HCIM_Msk /*!< Host channels interrupt mask */ #define USB_OTG_GINTMSK_PTXFEM_Pos (26U) #define USB_OTG_GINTMSK_PTXFEM_Msk (0x1U << USB_OTG_GINTMSK_PTXFEM_Pos) /*!< 0x04000000 */ #define USB_OTG_GINTMSK_PTXFEM USB_OTG_GINTMSK_PTXFEM_Msk /*!< Periodic TxFIFO empty mask */ #define USB_OTG_GINTMSK_LPMINTM_Pos (27U) #define USB_OTG_GINTMSK_LPMINTM_Msk (0x1U << USB_OTG_GINTMSK_LPMINTM_Pos) /*!< 0x08000000 */ #define USB_OTG_GINTMSK_LPMINTM USB_OTG_GINTMSK_LPMINTM_Msk /*!< LPM interrupt Mask */ #define USB_OTG_GINTMSK_CIDSCHGM_Pos (28U) #define USB_OTG_GINTMSK_CIDSCHGM_Msk (0x1U << USB_OTG_GINTMSK_CIDSCHGM_Pos) /*!< 0x10000000 */ #define USB_OTG_GINTMSK_CIDSCHGM USB_OTG_GINTMSK_CIDSCHGM_Msk /*!< Connector ID status change mask */ #define USB_OTG_GINTMSK_DISCINT_Pos (29U) #define USB_OTG_GINTMSK_DISCINT_Msk (0x1U << USB_OTG_GINTMSK_DISCINT_Pos) /*!< 0x20000000 */ #define USB_OTG_GINTMSK_DISCINT USB_OTG_GINTMSK_DISCINT_Msk /*!< Disconnect detected interrupt mask */ #define USB_OTG_GINTMSK_SRQIM_Pos (30U) #define USB_OTG_GINTMSK_SRQIM_Msk (0x1U << USB_OTG_GINTMSK_SRQIM_Pos) /*!< 0x40000000 */ #define USB_OTG_GINTMSK_SRQIM USB_OTG_GINTMSK_SRQIM_Msk /*!< Session request/new session detected interrupt mask */ #define USB_OTG_GINTMSK_WUIM_Pos (31U) #define USB_OTG_GINTMSK_WUIM_Msk (0x1U << USB_OTG_GINTMSK_WUIM_Pos) /*!< 0x80000000 */ #define USB_OTG_GINTMSK_WUIM USB_OTG_GINTMSK_WUIM_Msk /*!< Resume/remote wakeup detected interrupt mask */ /******************** Bit definition for USB_OTG_DAINT register ********************/ #define USB_OTG_DAINT_IEPINT_Pos (0U) #define USB_OTG_DAINT_IEPINT_Msk (0xFFFFU << USB_OTG_DAINT_IEPINT_Pos) /*!< 0x0000FFFF */ #define USB_OTG_DAINT_IEPINT USB_OTG_DAINT_IEPINT_Msk /*!< IN endpoint interrupt bits */ #define USB_OTG_DAINT_OEPINT_Pos (16U) #define USB_OTG_DAINT_OEPINT_Msk (0xFFFFU << USB_OTG_DAINT_OEPINT_Pos) /*!< 0xFFFF0000 */ #define USB_OTG_DAINT_OEPINT USB_OTG_DAINT_OEPINT_Msk /*!< OUT endpoint interrupt bits */ /******************** Bit definition for USB_OTG_HAINTMSK register ********************/ #define USB_OTG_HAINTMSK_HAINTM_Pos (0U) #define USB_OTG_HAINTMSK_HAINTM_Msk (0xFFFFU << USB_OTG_HAINTMSK_HAINTM_Pos) /*!< 0x0000FFFF */ #define USB_OTG_HAINTMSK_HAINTM USB_OTG_HAINTMSK_HAINTM_Msk /*!< Channel interrupt mask */ /******************** Bit definition for USB_OTG_GRXSTSP register ********************/ #define USB_OTG_GRXSTSP_EPNUM_Pos (0U) #define USB_OTG_GRXSTSP_EPNUM_Msk (0xFU << USB_OTG_GRXSTSP_EPNUM_Pos) /*!< 0x0000000F */ #define USB_OTG_GRXSTSP_EPNUM USB_OTG_GRXSTSP_EPNUM_Msk /*!< IN EP interrupt mask bits */ #define USB_OTG_GRXSTSP_BCNT_Pos (4U) #define USB_OTG_GRXSTSP_BCNT_Msk (0x7FFU << USB_OTG_GRXSTSP_BCNT_Pos) /*!< 0x00007FF0 */ #define USB_OTG_GRXSTSP_BCNT USB_OTG_GRXSTSP_BCNT_Msk /*!< OUT EP interrupt mask bits */ #define USB_OTG_GRXSTSP_DPID_Pos (15U) #define USB_OTG_GRXSTSP_DPID_Msk (0x3U << USB_OTG_GRXSTSP_DPID_Pos) /*!< 0x00018000 */ #define USB_OTG_GRXSTSP_DPID USB_OTG_GRXSTSP_DPID_Msk /*!< OUT EP interrupt mask bits */ #define USB_OTG_GRXSTSP_PKTSTS_Pos (17U) #define USB_OTG_GRXSTSP_PKTSTS_Msk (0xFU << USB_OTG_GRXSTSP_PKTSTS_Pos) /*!< 0x001E0000 */ #define USB_OTG_GRXSTSP_PKTSTS USB_OTG_GRXSTSP_PKTSTS_Msk /*!< OUT EP interrupt mask bits */ /******************** Bit definition for USB_OTG_DAINTMSK register ********************/ #define USB_OTG_DAINTMSK_IEPM_Pos (0U) #define USB_OTG_DAINTMSK_IEPM_Msk (0xFFFFU << USB_OTG_DAINTMSK_IEPM_Pos) /*!< 0x0000FFFF */ #define USB_OTG_DAINTMSK_IEPM USB_OTG_DAINTMSK_IEPM_Msk /*!< IN EP interrupt mask bits */ #define USB_OTG_DAINTMSK_OEPM_Pos (16U) #define USB_OTG_DAINTMSK_OEPM_Msk (0xFFFFU << USB_OTG_DAINTMSK_OEPM_Pos) /*!< 0xFFFF0000 */ #define USB_OTG_DAINTMSK_OEPM USB_OTG_DAINTMSK_OEPM_Msk /*!< OUT EP interrupt mask bits */ /******************** Bit definition for USB_OTG_GRXFSIZ register ********************/ #define USB_OTG_GRXFSIZ_RXFD_Pos (0U) #define USB_OTG_GRXFSIZ_RXFD_Msk (0xFFFFU << USB_OTG_GRXFSIZ_RXFD_Pos) /*!< 0x0000FFFF */ #define USB_OTG_GRXFSIZ_RXFD USB_OTG_GRXFSIZ_RXFD_Msk /*!< RxFIFO depth */ /******************** Bit definition for USB_OTG_DVBUSDIS register ********************/ #define USB_OTG_DVBUSDIS_VBUSDT_Pos (0U) #define USB_OTG_DVBUSDIS_VBUSDT_Msk (0xFFFFU << USB_OTG_DVBUSDIS_VBUSDT_Pos) /*!< 0x0000FFFF */ #define USB_OTG_DVBUSDIS_VBUSDT USB_OTG_DVBUSDIS_VBUSDT_Msk /*!< Device VBUS discharge time */ /******************** Bit definition for OTG register ********************/ #define USB_OTG_NPTXFSA_Pos (0U) #define USB_OTG_NPTXFSA_Msk (0xFFFFU << USB_OTG_NPTXFSA_Pos) /*!< 0x0000FFFF */ #define USB_OTG_NPTXFSA USB_OTG_NPTXFSA_Msk /*!< Nonperiodic transmit RAM start address */ #define USB_OTG_NPTXFD_Pos (16U) #define USB_OTG_NPTXFD_Msk (0xFFFFU << USB_OTG_NPTXFD_Pos) /*!< 0xFFFF0000 */ #define USB_OTG_NPTXFD USB_OTG_NPTXFD_Msk /*!< Nonperiodic TxFIFO depth */ #define USB_OTG_TX0FSA_Pos (0U) #define USB_OTG_TX0FSA_Msk (0xFFFFU << USB_OTG_TX0FSA_Pos) /*!< 0x0000FFFF */ #define USB_OTG_TX0FSA USB_OTG_TX0FSA_Msk /*!< Endpoint 0 transmit RAM start address */ #define USB_OTG_TX0FD_Pos (16U) #define USB_OTG_TX0FD_Msk (0xFFFFU << USB_OTG_TX0FD_Pos) /*!< 0xFFFF0000 */ #define USB_OTG_TX0FD USB_OTG_TX0FD_Msk /*!< Endpoint 0 TxFIFO depth */ /******************** Bit definition forUSB_OTG_DVBUSPULSE register ********************/ #define USB_OTG_DVBUSPULSE_DVBUSP_Pos (0U) #define USB_OTG_DVBUSPULSE_DVBUSP_Msk (0xFFFU << USB_OTG_DVBUSPULSE_DVBUSP_Pos) /*!< 0x00000FFF */ #define USB_OTG_DVBUSPULSE_DVBUSP USB_OTG_DVBUSPULSE_DVBUSP_Msk /*!< Device VBUS pulsing time */ /******************** Bit definition for USB_OTG_GNPTXSTS register ********************/ #define USB_OTG_GNPTXSTS_NPTXFSAV_Pos (0U) #define USB_OTG_GNPTXSTS_NPTXFSAV_Msk (0xFFFFU << USB_OTG_GNPTXSTS_NPTXFSAV_Pos) /*!< 0x0000FFFF */ #define USB_OTG_GNPTXSTS_NPTXFSAV USB_OTG_GNPTXSTS_NPTXFSAV_Msk /*!< Nonperiodic TxFIFO space available */ #define USB_OTG_GNPTXSTS_NPTQXSAV_Pos (16U) #define USB_OTG_GNPTXSTS_NPTQXSAV_Msk (0xFFU << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00FF0000 */ #define USB_OTG_GNPTXSTS_NPTQXSAV USB_OTG_GNPTXSTS_NPTQXSAV_Msk /*!< Nonperiodic transmit request queue space available */ #define USB_OTG_GNPTXSTS_NPTQXSAV_0 (0x01U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00010000 */ #define USB_OTG_GNPTXSTS_NPTQXSAV_1 (0x02U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00020000 */ #define USB_OTG_GNPTXSTS_NPTQXSAV_2 (0x04U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00040000 */ #define USB_OTG_GNPTXSTS_NPTQXSAV_3 (0x08U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00080000 */ #define USB_OTG_GNPTXSTS_NPTQXSAV_4 (0x10U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00100000 */ #define USB_OTG_GNPTXSTS_NPTQXSAV_5 (0x20U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00200000 */ #define USB_OTG_GNPTXSTS_NPTQXSAV_6 (0x40U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00400000 */ #define USB_OTG_GNPTXSTS_NPTQXSAV_7 (0x80U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00800000 */ #define USB_OTG_GNPTXSTS_NPTXQTOP_Pos (24U) #define USB_OTG_GNPTXSTS_NPTXQTOP_Msk (0x7FU << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x7F000000 */ #define USB_OTG_GNPTXSTS_NPTXQTOP USB_OTG_GNPTXSTS_NPTXQTOP_Msk /*!< Top of the nonperiodic transmit request queue */ #define USB_OTG_GNPTXSTS_NPTXQTOP_0 (0x01U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x01000000 */ #define USB_OTG_GNPTXSTS_NPTXQTOP_1 (0x02U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x02000000 */ #define USB_OTG_GNPTXSTS_NPTXQTOP_2 (0x04U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x04000000 */ #define USB_OTG_GNPTXSTS_NPTXQTOP_3 (0x08U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x08000000 */ #define USB_OTG_GNPTXSTS_NPTXQTOP_4 (0x10U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x10000000 */ #define USB_OTG_GNPTXSTS_NPTXQTOP_5 (0x20U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x20000000 */ #define USB_OTG_GNPTXSTS_NPTXQTOP_6 (0x40U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x40000000 */ /******************** Bit definition for USB_OTG_DTHRCTL register ********************/ #define USB_OTG_DTHRCTL_NONISOTHREN_Pos (0U) #define USB_OTG_DTHRCTL_NONISOTHREN_Msk (0x1U << USB_OTG_DTHRCTL_NONISOTHREN_Pos) /*!< 0x00000001 */ #define USB_OTG_DTHRCTL_NONISOTHREN USB_OTG_DTHRCTL_NONISOTHREN_Msk /*!< Nonisochronous IN endpoints threshold enable */ #define USB_OTG_DTHRCTL_ISOTHREN_Pos (1U) #define USB_OTG_DTHRCTL_ISOTHREN_Msk (0x1U << USB_OTG_DTHRCTL_ISOTHREN_Pos) /*!< 0x00000002 */ #define USB_OTG_DTHRCTL_ISOTHREN USB_OTG_DTHRCTL_ISOTHREN_Msk /*!< ISO IN endpoint threshold enable */ #define USB_OTG_DTHRCTL_TXTHRLEN_Pos (2U) #define USB_OTG_DTHRCTL_TXTHRLEN_Msk (0x1FFU << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x000007FC */ #define USB_OTG_DTHRCTL_TXTHRLEN USB_OTG_DTHRCTL_TXTHRLEN_Msk /*!< Transmit threshold length */ #define USB_OTG_DTHRCTL_TXTHRLEN_0 (0x001U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000004 */ #define USB_OTG_DTHRCTL_TXTHRLEN_1 (0x002U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000008 */ #define USB_OTG_DTHRCTL_TXTHRLEN_2 (0x004U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000010 */ #define USB_OTG_DTHRCTL_TXTHRLEN_3 (0x008U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000020 */ #define USB_OTG_DTHRCTL_TXTHRLEN_4 (0x010U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000040 */ #define USB_OTG_DTHRCTL_TXTHRLEN_5 (0x020U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000080 */ #define USB_OTG_DTHRCTL_TXTHRLEN_6 (0x040U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000100 */ #define USB_OTG_DTHRCTL_TXTHRLEN_7 (0x080U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000200 */ #define USB_OTG_DTHRCTL_TXTHRLEN_8 (0x100U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000400 */ #define USB_OTG_DTHRCTL_RXTHREN_Pos (16U) #define USB_OTG_DTHRCTL_RXTHREN_Msk (0x1U << USB_OTG_DTHRCTL_RXTHREN_Pos) /*!< 0x00010000 */ #define USB_OTG_DTHRCTL_RXTHREN USB_OTG_DTHRCTL_RXTHREN_Msk /*!< Receive threshold enable */ #define USB_OTG_DTHRCTL_RXTHRLEN_Pos (17U) #define USB_OTG_DTHRCTL_RXTHRLEN_Msk (0x1FFU << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x03FE0000 */ #define USB_OTG_DTHRCTL_RXTHRLEN USB_OTG_DTHRCTL_RXTHRLEN_Msk /*!< Receive threshold length */ #define USB_OTG_DTHRCTL_RXTHRLEN_0 (0x001U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00020000 */ #define USB_OTG_DTHRCTL_RXTHRLEN_1 (0x002U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00040000 */ #define USB_OTG_DTHRCTL_RXTHRLEN_2 (0x004U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00080000 */ #define USB_OTG_DTHRCTL_RXTHRLEN_3 (0x008U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00100000 */ #define USB_OTG_DTHRCTL_RXTHRLEN_4 (0x010U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00200000 */ #define USB_OTG_DTHRCTL_RXTHRLEN_5 (0x020U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00400000 */ #define USB_OTG_DTHRCTL_RXTHRLEN_6 (0x040U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00800000 */ #define USB_OTG_DTHRCTL_RXTHRLEN_7 (0x080U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x01000000 */ #define USB_OTG_DTHRCTL_RXTHRLEN_8 (0x100U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x02000000 */ #define USB_OTG_DTHRCTL_ARPEN_Pos (27U) #define USB_OTG_DTHRCTL_ARPEN_Msk (0x1U << USB_OTG_DTHRCTL_ARPEN_Pos) /*!< 0x08000000 */ #define USB_OTG_DTHRCTL_ARPEN USB_OTG_DTHRCTL_ARPEN_Msk /*!< Arbiter parking enable */ /******************** Bit definition for USB_OTG_DIEPEMPMSK register ********************/ #define USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos (0U) #define USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk (0xFFFFU << USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos) /*!< 0x0000FFFF */ #define USB_OTG_DIEPEMPMSK_INEPTXFEM USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk /*!< IN EP Tx FIFO empty interrupt mask bits */ /******************** Bit definition for USB_OTG_DEACHINT register ********************/ #define USB_OTG_DEACHINT_IEP1INT_Pos (1U) #define USB_OTG_DEACHINT_IEP1INT_Msk (0x1U << USB_OTG_DEACHINT_IEP1INT_Pos) /*!< 0x00000002 */ #define USB_OTG_DEACHINT_IEP1INT USB_OTG_DEACHINT_IEP1INT_Msk /*!< IN endpoint 1interrupt bit */ #define USB_OTG_DEACHINT_OEP1INT_Pos (17U) #define USB_OTG_DEACHINT_OEP1INT_Msk (0x1U << USB_OTG_DEACHINT_OEP1INT_Pos) /*!< 0x00020000 */ #define USB_OTG_DEACHINT_OEP1INT USB_OTG_DEACHINT_OEP1INT_Msk /*!< OUT endpoint 1 interrupt bit */ /******************** Bit definition for USB_OTG_GCCFG register ********************/ #define USB_OTG_GCCFG_PWRDWN_Pos (16U) #define USB_OTG_GCCFG_PWRDWN_Msk (0x1U << USB_OTG_GCCFG_PWRDWN_Pos) /*!< 0x00010000 */ #define USB_OTG_GCCFG_PWRDWN USB_OTG_GCCFG_PWRDWN_Msk /*!< Power down */ #define USB_OTG_GCCFG_VBDEN_Pos (21U) #define USB_OTG_GCCFG_VBDEN_Msk (0x1U << USB_OTG_GCCFG_VBDEN_Pos) /*!< 0x00200000 */ #define USB_OTG_GCCFG_VBDEN USB_OTG_GCCFG_VBDEN_Msk /*!< USB VBUS Detection Enable */ /******************** Bit definition forUSB_OTG_DEACHINTMSK register ********************/ #define USB_OTG_DEACHINTMSK_IEP1INTM_Pos (1U) #define USB_OTG_DEACHINTMSK_IEP1INTM_Msk (0x1U << USB_OTG_DEACHINTMSK_IEP1INTM_Pos) /*!< 0x00000002 */ #define USB_OTG_DEACHINTMSK_IEP1INTM USB_OTG_DEACHINTMSK_IEP1INTM_Msk /*!< IN Endpoint 1 interrupt mask bit */ #define USB_OTG_DEACHINTMSK_OEP1INTM_Pos (17U) #define USB_OTG_DEACHINTMSK_OEP1INTM_Msk (0x1U << USB_OTG_DEACHINTMSK_OEP1INTM_Pos) /*!< 0x00020000 */ #define USB_OTG_DEACHINTMSK_OEP1INTM USB_OTG_DEACHINTMSK_OEP1INTM_Msk /*!< OUT Endpoint 1 interrupt mask bit */ /******************** Bit definition for USB_OTG_CID register ********************/ #define USB_OTG_CID_PRODUCT_ID_Pos (0U) #define USB_OTG_CID_PRODUCT_ID_Msk (0xFFFFFFFFU << USB_OTG_CID_PRODUCT_ID_Pos) /*!< 0xFFFFFFFF */ #define USB_OTG_CID_PRODUCT_ID USB_OTG_CID_PRODUCT_ID_Msk /*!< Product ID field */ /******************** Bit definition for USB_OTG_GLPMCFG register ********************/ #define USB_OTG_GLPMCFG_LPMEN_Pos (0U) #define USB_OTG_GLPMCFG_LPMEN_Msk (0x1U << USB_OTG_GLPMCFG_LPMEN_Pos) /*!< 0x00000001 */ #define USB_OTG_GLPMCFG_LPMEN USB_OTG_GLPMCFG_LPMEN_Msk /*!< LPM support enable */ #define USB_OTG_GLPMCFG_LPMACK_Pos (1U) #define USB_OTG_GLPMCFG_LPMACK_Msk (0x1U << USB_OTG_GLPMCFG_LPMACK_Pos) /*!< 0x00000002 */ #define USB_OTG_GLPMCFG_LPMACK USB_OTG_GLPMCFG_LPMACK_Msk /*!< LPM Token acknowledge enable */ #define USB_OTG_GLPMCFG_BESL_Pos (2U) #define USB_OTG_GLPMCFG_BESL_Msk (0xFU << USB_OTG_GLPMCFG_BESL_Pos) /*!< 0x0000003C */ #define USB_OTG_GLPMCFG_BESL USB_OTG_GLPMCFG_BESL_Msk /*!< BESL value received with last ACKed LPM Token */ #define USB_OTG_GLPMCFG_REMWAKE_Pos (6U) #define USB_OTG_GLPMCFG_REMWAKE_Msk (0x1U << USB_OTG_GLPMCFG_REMWAKE_Pos) /*!< 0x00000040 */ #define USB_OTG_GLPMCFG_REMWAKE USB_OTG_GLPMCFG_REMWAKE_Msk /*!< bRemoteWake value received with last ACKed LPM Token */ #define USB_OTG_GLPMCFG_L1SSEN_Pos (7U) #define USB_OTG_GLPMCFG_L1SSEN_Msk (0x1U << USB_OTG_GLPMCFG_L1SSEN_Pos) /*!< 0x00000080 */ #define USB_OTG_GLPMCFG_L1SSEN USB_OTG_GLPMCFG_L1SSEN_Msk /*!< L1 shallow sleep enable */ #define USB_OTG_GLPMCFG_BESLTHRS_Pos (8U) #define USB_OTG_GLPMCFG_BESLTHRS_Msk (0xFU << USB_OTG_GLPMCFG_BESLTHRS_Pos) /*!< 0x00000F00 */ #define USB_OTG_GLPMCFG_BESLTHRS USB_OTG_GLPMCFG_BESLTHRS_Msk /*!< BESL threshold */ #define USB_OTG_GLPMCFG_L1DSEN_Pos (12U) #define USB_OTG_GLPMCFG_L1DSEN_Msk (0x1U << USB_OTG_GLPMCFG_L1DSEN_Pos) /*!< 0x00001000 */ #define USB_OTG_GLPMCFG_L1DSEN USB_OTG_GLPMCFG_L1DSEN_Msk /*!< L1 deep sleep enable */ #define USB_OTG_GLPMCFG_LPMRSP_Pos (13U) #define USB_OTG_GLPMCFG_LPMRSP_Msk (0x3U << USB_OTG_GLPMCFG_LPMRSP_Pos) /*!< 0x00006000 */ #define USB_OTG_GLPMCFG_LPMRSP USB_OTG_GLPMCFG_LPMRSP_Msk /*!< LPM response */ #define USB_OTG_GLPMCFG_SLPSTS_Pos (15U) #define USB_OTG_GLPMCFG_SLPSTS_Msk (0x1U << USB_OTG_GLPMCFG_SLPSTS_Pos) /*!< 0x00008000 */ #define USB_OTG_GLPMCFG_SLPSTS USB_OTG_GLPMCFG_SLPSTS_Msk /*!< Port sleep status */ #define USB_OTG_GLPMCFG_L1RSMOK_Pos (16U) #define USB_OTG_GLPMCFG_L1RSMOK_Msk (0x1U << USB_OTG_GLPMCFG_L1RSMOK_Pos) /*!< 0x00010000 */ #define USB_OTG_GLPMCFG_L1RSMOK USB_OTG_GLPMCFG_L1RSMOK_Msk /*!< Sleep State Resume OK */ #define USB_OTG_GLPMCFG_LPMCHIDX_Pos (17U) #define USB_OTG_GLPMCFG_LPMCHIDX_Msk (0xFU << USB_OTG_GLPMCFG_LPMCHIDX_Pos) /*!< 0x001E0000 */ #define USB_OTG_GLPMCFG_LPMCHIDX USB_OTG_GLPMCFG_LPMCHIDX_Msk /*!< LPM Channel Index */ #define USB_OTG_GLPMCFG_LPMRCNT_Pos (21U) #define USB_OTG_GLPMCFG_LPMRCNT_Msk (0x7U << USB_OTG_GLPMCFG_LPMRCNT_Pos) /*!< 0x00E00000 */ #define USB_OTG_GLPMCFG_LPMRCNT USB_OTG_GLPMCFG_LPMRCNT_Msk /*!< LPM retry count */ #define USB_OTG_GLPMCFG_SNDLPM_Pos (24U) #define USB_OTG_GLPMCFG_SNDLPM_Msk (0x1U << USB_OTG_GLPMCFG_SNDLPM_Pos) /*!< 0x01000000 */ #define USB_OTG_GLPMCFG_SNDLPM USB_OTG_GLPMCFG_SNDLPM_Msk /*!< Send LPM transaction */ #define USB_OTG_GLPMCFG_LPMRCNTSTS_Pos (25U) #define USB_OTG_GLPMCFG_LPMRCNTSTS_Msk (0x7U << USB_OTG_GLPMCFG_LPMRCNTSTS_Pos) /*!< 0x0E000000 */ #define USB_OTG_GLPMCFG_LPMRCNTSTS USB_OTG_GLPMCFG_LPMRCNTSTS_Msk /*!< LPM retry count status */ #define USB_OTG_GLPMCFG_ENBESL_Pos (28U) #define USB_OTG_GLPMCFG_ENBESL_Msk (0x1U << USB_OTG_GLPMCFG_ENBESL_Pos) /*!< 0x10000000 */ #define USB_OTG_GLPMCFG_ENBESL USB_OTG_GLPMCFG_ENBESL_Msk /*!< Enable best effort service latency */ /******************** Bit definition for USB_OTG_DIEPEACHMSK1 register ********************/ #define USB_OTG_DIEPEACHMSK1_XFRCM_Pos (0U) #define USB_OTG_DIEPEACHMSK1_XFRCM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */ #define USB_OTG_DIEPEACHMSK1_XFRCM USB_OTG_DIEPEACHMSK1_XFRCM_Msk /*!< Transfer completed interrupt mask */ #define USB_OTG_DIEPEACHMSK1_EPDM_Pos (1U) #define USB_OTG_DIEPEACHMSK1_EPDM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_EPDM_Pos) /*!< 0x00000002 */ #define USB_OTG_DIEPEACHMSK1_EPDM USB_OTG_DIEPEACHMSK1_EPDM_Msk /*!< Endpoint disabled interrupt mask */ #define USB_OTG_DIEPEACHMSK1_TOM_Pos (3U) #define USB_OTG_DIEPEACHMSK1_TOM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_TOM_Pos) /*!< 0x00000008 */ #define USB_OTG_DIEPEACHMSK1_TOM USB_OTG_DIEPEACHMSK1_TOM_Msk /*!< Timeout condition mask (nonisochronous endpoints) */ #define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos (4U) #define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk (0x1U << USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */ #define USB_OTG_DIEPEACHMSK1_ITTXFEMSK USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */ #define USB_OTG_DIEPEACHMSK1_INEPNMM_Pos (5U) #define USB_OTG_DIEPEACHMSK1_INEPNMM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */ #define USB_OTG_DIEPEACHMSK1_INEPNMM USB_OTG_DIEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask */ #define USB_OTG_DIEPEACHMSK1_INEPNEM_Pos (6U) #define USB_OTG_DIEPEACHMSK1_INEPNEM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_INEPNEM_Pos) /*!< 0x00000040 */ #define USB_OTG_DIEPEACHMSK1_INEPNEM USB_OTG_DIEPEACHMSK1_INEPNEM_Msk /*!< IN endpoint NAK effective mask */ #define USB_OTG_DIEPEACHMSK1_TXFURM_Pos (8U) #define USB_OTG_DIEPEACHMSK1_TXFURM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_TXFURM_Pos) /*!< 0x00000100 */ #define USB_OTG_DIEPEACHMSK1_TXFURM USB_OTG_DIEPEACHMSK1_TXFURM_Msk /*!< FIFO underrun mask */ #define USB_OTG_DIEPEACHMSK1_BIM_Pos (9U) #define USB_OTG_DIEPEACHMSK1_BIM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_BIM_Pos) /*!< 0x00000200 */ #define USB_OTG_DIEPEACHMSK1_BIM USB_OTG_DIEPEACHMSK1_BIM_Msk /*!< BNA interrupt mask */ #define USB_OTG_DIEPEACHMSK1_NAKM_Pos (13U) #define USB_OTG_DIEPEACHMSK1_NAKM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */ #define USB_OTG_DIEPEACHMSK1_NAKM USB_OTG_DIEPEACHMSK1_NAKM_Msk /*!< NAK interrupt mask */ /******************** Bit definition for USB_OTG_HPRT register ********************/ #define USB_OTG_HPRT_PCSTS_Pos (0U) #define USB_OTG_HPRT_PCSTS_Msk (0x1U << USB_OTG_HPRT_PCSTS_Pos) /*!< 0x00000001 */ #define USB_OTG_HPRT_PCSTS USB_OTG_HPRT_PCSTS_Msk /*!< Port connect status */ #define USB_OTG_HPRT_PCDET_Pos (1U) #define USB_OTG_HPRT_PCDET_Msk (0x1U << USB_OTG_HPRT_PCDET_Pos) /*!< 0x00000002 */ #define USB_OTG_HPRT_PCDET USB_OTG_HPRT_PCDET_Msk /*!< Port connect detected */ #define USB_OTG_HPRT_PENA_Pos (2U) #define USB_OTG_HPRT_PENA_Msk (0x1U << USB_OTG_HPRT_PENA_Pos) /*!< 0x00000004 */ #define USB_OTG_HPRT_PENA USB_OTG_HPRT_PENA_Msk /*!< Port enable */ #define USB_OTG_HPRT_PENCHNG_Pos (3U) #define USB_OTG_HPRT_PENCHNG_Msk (0x1U << USB_OTG_HPRT_PENCHNG_Pos) /*!< 0x00000008 */ #define USB_OTG_HPRT_PENCHNG USB_OTG_HPRT_PENCHNG_Msk /*!< Port enable/disable change */ #define USB_OTG_HPRT_POCA_Pos (4U) #define USB_OTG_HPRT_POCA_Msk (0x1U << USB_OTG_HPRT_POCA_Pos) /*!< 0x00000010 */ #define USB_OTG_HPRT_POCA USB_OTG_HPRT_POCA_Msk /*!< Port overcurrent active */ #define USB_OTG_HPRT_POCCHNG_Pos (5U) #define USB_OTG_HPRT_POCCHNG_Msk (0x1U << USB_OTG_HPRT_POCCHNG_Pos) /*!< 0x00000020 */ #define USB_OTG_HPRT_POCCHNG USB_OTG_HPRT_POCCHNG_Msk /*!< Port overcurrent change */ #define USB_OTG_HPRT_PRES_Pos (6U) #define USB_OTG_HPRT_PRES_Msk (0x1U << USB_OTG_HPRT_PRES_Pos) /*!< 0x00000040 */ #define USB_OTG_HPRT_PRES USB_OTG_HPRT_PRES_Msk /*!< Port resume */ #define USB_OTG_HPRT_PSUSP_Pos (7U) #define USB_OTG_HPRT_PSUSP_Msk (0x1U << USB_OTG_HPRT_PSUSP_Pos) /*!< 0x00000080 */ #define USB_OTG_HPRT_PSUSP USB_OTG_HPRT_PSUSP_Msk /*!< Port suspend */ #define USB_OTG_HPRT_PRST_Pos (8U) #define USB_OTG_HPRT_PRST_Msk (0x1U << USB_OTG_HPRT_PRST_Pos) /*!< 0x00000100 */ #define USB_OTG_HPRT_PRST USB_OTG_HPRT_PRST_Msk /*!< Port reset */ #define USB_OTG_HPRT_PLSTS_Pos (10U) #define USB_OTG_HPRT_PLSTS_Msk (0x3U << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000C00 */ #define USB_OTG_HPRT_PLSTS USB_OTG_HPRT_PLSTS_Msk /*!< Port line status */ #define USB_OTG_HPRT_PLSTS_0 (0x1U << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000400 */ #define USB_OTG_HPRT_PLSTS_1 (0x2U << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000800 */ #define USB_OTG_HPRT_PPWR_Pos (12U) #define USB_OTG_HPRT_PPWR_Msk (0x1U << USB_OTG_HPRT_PPWR_Pos) /*!< 0x00001000 */ #define USB_OTG_HPRT_PPWR USB_OTG_HPRT_PPWR_Msk /*!< Port power */ #define USB_OTG_HPRT_PTCTL_Pos (13U) #define USB_OTG_HPRT_PTCTL_Msk (0xFU << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x0001E000 */ #define USB_OTG_HPRT_PTCTL USB_OTG_HPRT_PTCTL_Msk /*!< Port test control */ #define USB_OTG_HPRT_PTCTL_0 (0x1U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00002000 */ #define USB_OTG_HPRT_PTCTL_1 (0x2U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00004000 */ #define USB_OTG_HPRT_PTCTL_2 (0x4U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00008000 */ #define USB_OTG_HPRT_PTCTL_3 (0x8U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00010000 */ #define USB_OTG_HPRT_PSPD_Pos (17U) #define USB_OTG_HPRT_PSPD_Msk (0x3U << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00060000 */ #define USB_OTG_HPRT_PSPD USB_OTG_HPRT_PSPD_Msk /*!< Port speed */ #define USB_OTG_HPRT_PSPD_0 (0x1U << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00020000 */ #define USB_OTG_HPRT_PSPD_1 (0x2U << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00040000 */ /******************** Bit definition for USB_OTG_DOEPEACHMSK1 register ********************/ #define USB_OTG_DOEPEACHMSK1_XFRCM_Pos (0U) #define USB_OTG_DOEPEACHMSK1_XFRCM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */ #define USB_OTG_DOEPEACHMSK1_XFRCM USB_OTG_DOEPEACHMSK1_XFRCM_Msk /*!< Transfer completed interrupt mask */ #define USB_OTG_DOEPEACHMSK1_EPDM_Pos (1U) #define USB_OTG_DOEPEACHMSK1_EPDM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_EPDM_Pos) /*!< 0x00000002 */ #define USB_OTG_DOEPEACHMSK1_EPDM USB_OTG_DOEPEACHMSK1_EPDM_Msk /*!< Endpoint disabled interrupt mask */ #define USB_OTG_DOEPEACHMSK1_TOM_Pos (3U) #define USB_OTG_DOEPEACHMSK1_TOM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_TOM_Pos) /*!< 0x00000008 */ #define USB_OTG_DOEPEACHMSK1_TOM USB_OTG_DOEPEACHMSK1_TOM_Msk /*!< Timeout condition mask */ #define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos (4U) #define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk (0x1U << USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */ #define USB_OTG_DOEPEACHMSK1_ITTXFEMSK USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */ #define USB_OTG_DOEPEACHMSK1_INEPNMM_Pos (5U) #define USB_OTG_DOEPEACHMSK1_INEPNMM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */ #define USB_OTG_DOEPEACHMSK1_INEPNMM USB_OTG_DOEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask */ #define USB_OTG_DOEPEACHMSK1_INEPNEM_Pos (6U) #define USB_OTG_DOEPEACHMSK1_INEPNEM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_INEPNEM_Pos) /*!< 0x00000040 */ #define USB_OTG_DOEPEACHMSK1_INEPNEM USB_OTG_DOEPEACHMSK1_INEPNEM_Msk /*!< IN endpoint NAK effective mask */ #define USB_OTG_DOEPEACHMSK1_TXFURM_Pos (8U) #define USB_OTG_DOEPEACHMSK1_TXFURM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_TXFURM_Pos) /*!< 0x00000100 */ #define USB_OTG_DOEPEACHMSK1_TXFURM USB_OTG_DOEPEACHMSK1_TXFURM_Msk /*!< OUT packet error mask */ #define USB_OTG_DOEPEACHMSK1_BIM_Pos (9U) #define USB_OTG_DOEPEACHMSK1_BIM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_BIM_Pos) /*!< 0x00000200 */ #define USB_OTG_DOEPEACHMSK1_BIM USB_OTG_DOEPEACHMSK1_BIM_Msk /*!< BNA interrupt mask */ #define USB_OTG_DOEPEACHMSK1_BERRM_Pos (12U) #define USB_OTG_DOEPEACHMSK1_BERRM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_BERRM_Pos) /*!< 0x00001000 */ #define USB_OTG_DOEPEACHMSK1_BERRM USB_OTG_DOEPEACHMSK1_BERRM_Msk /*!< Bubble error interrupt mask */ #define USB_OTG_DOEPEACHMSK1_NAKM_Pos (13U) #define USB_OTG_DOEPEACHMSK1_NAKM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */ #define USB_OTG_DOEPEACHMSK1_NAKM USB_OTG_DOEPEACHMSK1_NAKM_Msk /*!< NAK interrupt mask */ #define USB_OTG_DOEPEACHMSK1_NYETM_Pos (14U) #define USB_OTG_DOEPEACHMSK1_NYETM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_NYETM_Pos) /*!< 0x00004000 */ #define USB_OTG_DOEPEACHMSK1_NYETM USB_OTG_DOEPEACHMSK1_NYETM_Msk /*!< NYET interrupt mask */ /******************** Bit definition for USB_OTG_HPTXFSIZ register ********************/ #define USB_OTG_HPTXFSIZ_PTXSA_Pos (0U) #define USB_OTG_HPTXFSIZ_PTXSA_Msk (0xFFFFU << USB_OTG_HPTXFSIZ_PTXSA_Pos) /*!< 0x0000FFFF */ #define USB_OTG_HPTXFSIZ_PTXSA USB_OTG_HPTXFSIZ_PTXSA_Msk /*!< Host periodic TxFIFO start address */ #define USB_OTG_HPTXFSIZ_PTXFD_Pos (16U) #define USB_OTG_HPTXFSIZ_PTXFD_Msk (0xFFFFU << USB_OTG_HPTXFSIZ_PTXFD_Pos) /*!< 0xFFFF0000 */ #define USB_OTG_HPTXFSIZ_PTXFD USB_OTG_HPTXFSIZ_PTXFD_Msk /*!< Host periodic TxFIFO depth */ /******************** Bit definition for USB_OTG_DIEPCTL register ********************/ #define USB_OTG_DIEPCTL_MPSIZ_Pos (0U) #define USB_OTG_DIEPCTL_MPSIZ_Msk (0x7FFU << USB_OTG_DIEPCTL_MPSIZ_Pos) /*!< 0x000007FF */ #define USB_OTG_DIEPCTL_MPSIZ USB_OTG_DIEPCTL_MPSIZ_Msk /*!< Maximum packet size */ #define USB_OTG_DIEPCTL_USBAEP_Pos (15U) #define USB_OTG_DIEPCTL_USBAEP_Msk (0x1U << USB_OTG_DIEPCTL_USBAEP_Pos) /*!< 0x00008000 */ #define USB_OTG_DIEPCTL_USBAEP USB_OTG_DIEPCTL_USBAEP_Msk /*!< USB active endpoint */ #define USB_OTG_DIEPCTL_EONUM_DPID_Pos (16U) #define USB_OTG_DIEPCTL_EONUM_DPID_Msk (0x1U << USB_OTG_DIEPCTL_EONUM_DPID_Pos) /*!< 0x00010000 */ #define USB_OTG_DIEPCTL_EONUM_DPID USB_OTG_DIEPCTL_EONUM_DPID_Msk /*!< Even/odd frame */ #define USB_OTG_DIEPCTL_NAKSTS_Pos (17U) #define USB_OTG_DIEPCTL_NAKSTS_Msk (0x1U << USB_OTG_DIEPCTL_NAKSTS_Pos) /*!< 0x00020000 */ #define USB_OTG_DIEPCTL_NAKSTS USB_OTG_DIEPCTL_NAKSTS_Msk /*!< NAK status */ #define USB_OTG_DIEPCTL_EPTYP_Pos (18U) #define USB_OTG_DIEPCTL_EPTYP_Msk (0x3U << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x000C0000 */ #define USB_OTG_DIEPCTL_EPTYP USB_OTG_DIEPCTL_EPTYP_Msk /*!< Endpoint type */ #define USB_OTG_DIEPCTL_EPTYP_0 (0x1U << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x00040000 */ #define USB_OTG_DIEPCTL_EPTYP_1 (0x2U << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x00080000 */ #define USB_OTG_DIEPCTL_STALL_Pos (21U) #define USB_OTG_DIEPCTL_STALL_Msk (0x1U << USB_OTG_DIEPCTL_STALL_Pos) /*!< 0x00200000 */ #define USB_OTG_DIEPCTL_STALL USB_OTG_DIEPCTL_STALL_Msk /*!< STALL handshake */ #define USB_OTG_DIEPCTL_TXFNUM_Pos (22U) #define USB_OTG_DIEPCTL_TXFNUM_Msk (0xFU << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x03C00000 */ #define USB_OTG_DIEPCTL_TXFNUM USB_OTG_DIEPCTL_TXFNUM_Msk /*!< TxFIFO number */ #define USB_OTG_DIEPCTL_TXFNUM_0 (0x1U << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x00400000 */ #define USB_OTG_DIEPCTL_TXFNUM_1 (0x2U << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x00800000 */ #define USB_OTG_DIEPCTL_TXFNUM_2 (0x4U << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x01000000 */ #define USB_OTG_DIEPCTL_TXFNUM_3 (0x8U << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x02000000 */ #define USB_OTG_DIEPCTL_CNAK_Pos (26U) #define USB_OTG_DIEPCTL_CNAK_Msk (0x1U << USB_OTG_DIEPCTL_CNAK_Pos) /*!< 0x04000000 */ #define USB_OTG_DIEPCTL_CNAK USB_OTG_DIEPCTL_CNAK_Msk /*!< Clear NAK */ #define USB_OTG_DIEPCTL_SNAK_Pos (27U) #define USB_OTG_DIEPCTL_SNAK_Msk (0x1U << USB_OTG_DIEPCTL_SNAK_Pos) /*!< 0x08000000 */ #define USB_OTG_DIEPCTL_SNAK USB_OTG_DIEPCTL_SNAK_Msk /*!< Set NAK */ #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos (28U) #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk (0x1U << USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */ #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */ #define USB_OTG_DIEPCTL_SODDFRM_Pos (29U) #define USB_OTG_DIEPCTL_SODDFRM_Msk (0x1U << USB_OTG_DIEPCTL_SODDFRM_Pos) /*!< 0x20000000 */ #define USB_OTG_DIEPCTL_SODDFRM USB_OTG_DIEPCTL_SODDFRM_Msk /*!< Set odd frame */ #define USB_OTG_DIEPCTL_EPDIS_Pos (30U) #define USB_OTG_DIEPCTL_EPDIS_Msk (0x1U << USB_OTG_DIEPCTL_EPDIS_Pos) /*!< 0x40000000 */ #define USB_OTG_DIEPCTL_EPDIS USB_OTG_DIEPCTL_EPDIS_Msk /*!< Endpoint disable */ #define USB_OTG_DIEPCTL_EPENA_Pos (31U) #define USB_OTG_DIEPCTL_EPENA_Msk (0x1U << USB_OTG_DIEPCTL_EPENA_Pos) /*!< 0x80000000 */ #define USB_OTG_DIEPCTL_EPENA USB_OTG_DIEPCTL_EPENA_Msk /*!< Endpoint enable */ /******************** Bit definition for USB_OTG_HCCHAR register ********************/ #define USB_OTG_HCCHAR_MPSIZ_Pos (0U) #define USB_OTG_HCCHAR_MPSIZ_Msk (0x7FFU << USB_OTG_HCCHAR_MPSIZ_Pos) /*!< 0x000007FF */ #define USB_OTG_HCCHAR_MPSIZ USB_OTG_HCCHAR_MPSIZ_Msk /*!< Maximum packet size */ #define USB_OTG_HCCHAR_EPNUM_Pos (11U) #define USB_OTG_HCCHAR_EPNUM_Msk (0xFU << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00007800 */ #define USB_OTG_HCCHAR_EPNUM USB_OTG_HCCHAR_EPNUM_Msk /*!< Endpoint number */ #define USB_OTG_HCCHAR_EPNUM_0 (0x1U << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00000800 */ #define USB_OTG_HCCHAR_EPNUM_1 (0x2U << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00001000 */ #define USB_OTG_HCCHAR_EPNUM_2 (0x4U << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00002000 */ #define USB_OTG_HCCHAR_EPNUM_3 (0x8U << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00004000 */ #define USB_OTG_HCCHAR_EPDIR_Pos (15U) #define USB_OTG_HCCHAR_EPDIR_Msk (0x1U << USB_OTG_HCCHAR_EPDIR_Pos) /*!< 0x00008000 */ #define USB_OTG_HCCHAR_EPDIR USB_OTG_HCCHAR_EPDIR_Msk /*!< Endpoint direction */ #define USB_OTG_HCCHAR_LSDEV_Pos (17U) #define USB_OTG_HCCHAR_LSDEV_Msk (0x1U << USB_OTG_HCCHAR_LSDEV_Pos) /*!< 0x00020000 */ #define USB_OTG_HCCHAR_LSDEV USB_OTG_HCCHAR_LSDEV_Msk /*!< Low-speed device */ #define USB_OTG_HCCHAR_EPTYP_Pos (18U) #define USB_OTG_HCCHAR_EPTYP_Msk (0x3U << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x000C0000 */ #define USB_OTG_HCCHAR_EPTYP USB_OTG_HCCHAR_EPTYP_Msk /*!< Endpoint type */ #define USB_OTG_HCCHAR_EPTYP_0 (0x1U << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00040000 */ #define USB_OTG_HCCHAR_EPTYP_1 (0x2U << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00080000 */ #define USB_OTG_HCCHAR_MC_Pos (20U) #define USB_OTG_HCCHAR_MC_Msk (0x3U << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00300000 */ #define USB_OTG_HCCHAR_MC USB_OTG_HCCHAR_MC_Msk /*!< Multi Count (MC) / Error Count (EC) */ #define USB_OTG_HCCHAR_MC_0 (0x1U << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00100000 */ #define USB_OTG_HCCHAR_MC_1 (0x2U << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00200000 */ #define USB_OTG_HCCHAR_DAD_Pos (22U) #define USB_OTG_HCCHAR_DAD_Msk (0x7FU << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x1FC00000 */ #define USB_OTG_HCCHAR_DAD USB_OTG_HCCHAR_DAD_Msk /*!< Device address */ #define USB_OTG_HCCHAR_DAD_0 (0x01U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x00400000 */ #define USB_OTG_HCCHAR_DAD_1 (0x02U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x00800000 */ #define USB_OTG_HCCHAR_DAD_2 (0x04U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x01000000 */ #define USB_OTG_HCCHAR_DAD_3 (0x08U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x02000000 */ #define USB_OTG_HCCHAR_DAD_4 (0x10U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x04000000 */ #define USB_OTG_HCCHAR_DAD_5 (0x20U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x08000000 */ #define USB_OTG_HCCHAR_DAD_6 (0x40U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x10000000 */ #define USB_OTG_HCCHAR_ODDFRM_Pos (29U) #define USB_OTG_HCCHAR_ODDFRM_Msk (0x1U << USB_OTG_HCCHAR_ODDFRM_Pos) /*!< 0x20000000 */ #define USB_OTG_HCCHAR_ODDFRM USB_OTG_HCCHAR_ODDFRM_Msk /*!< Odd frame */ #define USB_OTG_HCCHAR_CHDIS_Pos (30U) #define USB_OTG_HCCHAR_CHDIS_Msk (0x1U << USB_OTG_HCCHAR_CHDIS_Pos) /*!< 0x40000000 */ #define USB_OTG_HCCHAR_CHDIS USB_OTG_HCCHAR_CHDIS_Msk /*!< Channel disable */ #define USB_OTG_HCCHAR_CHENA_Pos (31U) #define USB_OTG_HCCHAR_CHENA_Msk (0x1U << USB_OTG_HCCHAR_CHENA_Pos) /*!< 0x80000000 */ #define USB_OTG_HCCHAR_CHENA USB_OTG_HCCHAR_CHENA_Msk /*!< Channel enable */ /******************** Bit definition for USB_OTG_HCSPLT register ********************/ #define USB_OTG_HCSPLT_PRTADDR_Pos (0U) #define USB_OTG_HCSPLT_PRTADDR_Msk (0x7FU << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x0000007F */ #define USB_OTG_HCSPLT_PRTADDR USB_OTG_HCSPLT_PRTADDR_Msk /*!< Port address */ #define USB_OTG_HCSPLT_PRTADDR_0 (0x01U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000001 */ #define USB_OTG_HCSPLT_PRTADDR_1 (0x02U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000002 */ #define USB_OTG_HCSPLT_PRTADDR_2 (0x04U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000004 */ #define USB_OTG_HCSPLT_PRTADDR_3 (0x08U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000008 */ #define USB_OTG_HCSPLT_PRTADDR_4 (0x10U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000010 */ #define USB_OTG_HCSPLT_PRTADDR_5 (0x20U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000020 */ #define USB_OTG_HCSPLT_PRTADDR_6 (0x40U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000040 */ #define USB_OTG_HCSPLT_HUBADDR_Pos (7U) #define USB_OTG_HCSPLT_HUBADDR_Msk (0x7FU << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00003F80 */ #define USB_OTG_HCSPLT_HUBADDR USB_OTG_HCSPLT_HUBADDR_Msk /*!< Hub address */ #define USB_OTG_HCSPLT_HUBADDR_0 (0x01U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000080 */ #define USB_OTG_HCSPLT_HUBADDR_1 (0x02U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000100 */ #define USB_OTG_HCSPLT_HUBADDR_2 (0x04U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000200 */ #define USB_OTG_HCSPLT_HUBADDR_3 (0x08U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000400 */ #define USB_OTG_HCSPLT_HUBADDR_4 (0x10U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000800 */ #define USB_OTG_HCSPLT_HUBADDR_5 (0x20U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00001000 */ #define USB_OTG_HCSPLT_HUBADDR_6 (0x40U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00002000 */ #define USB_OTG_HCSPLT_XACTPOS_Pos (14U) #define USB_OTG_HCSPLT_XACTPOS_Msk (0x3U << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x0000C000 */ #define USB_OTG_HCSPLT_XACTPOS USB_OTG_HCSPLT_XACTPOS_Msk /*!< XACTPOS */ #define USB_OTG_HCSPLT_XACTPOS_0 (0x1U << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x00004000 */ #define USB_OTG_HCSPLT_XACTPOS_1 (0x2U << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x00008000 */ #define USB_OTG_HCSPLT_COMPLSPLT_Pos (16U) #define USB_OTG_HCSPLT_COMPLSPLT_Msk (0x1U << USB_OTG_HCSPLT_COMPLSPLT_Pos) /*!< 0x00010000 */ #define USB_OTG_HCSPLT_COMPLSPLT USB_OTG_HCSPLT_COMPLSPLT_Msk /*!< Do complete split */ #define USB_OTG_HCSPLT_SPLITEN_Pos (31U) #define USB_OTG_HCSPLT_SPLITEN_Msk (0x1U << USB_OTG_HCSPLT_SPLITEN_Pos) /*!< 0x80000000 */ #define USB_OTG_HCSPLT_SPLITEN USB_OTG_HCSPLT_SPLITEN_Msk /*!< Split enable */ /******************** Bit definition for USB_OTG_HCINT register ********************/ #define USB_OTG_HCINT_XFRC_Pos (0U) #define USB_OTG_HCINT_XFRC_Msk (0x1U << USB_OTG_HCINT_XFRC_Pos) /*!< 0x00000001 */ #define USB_OTG_HCINT_XFRC USB_OTG_HCINT_XFRC_Msk /*!< Transfer completed */ #define USB_OTG_HCINT_CHH_Pos (1U) #define USB_OTG_HCINT_CHH_Msk (0x1U << USB_OTG_HCINT_CHH_Pos) /*!< 0x00000002 */ #define USB_OTG_HCINT_CHH USB_OTG_HCINT_CHH_Msk /*!< Channel halted */ #define USB_OTG_HCINT_AHBERR_Pos (2U) #define USB_OTG_HCINT_AHBERR_Msk (0x1U << USB_OTG_HCINT_AHBERR_Pos) /*!< 0x00000004 */ #define USB_OTG_HCINT_AHBERR USB_OTG_HCINT_AHBERR_Msk /*!< AHB error */ #define USB_OTG_HCINT_STALL_Pos (3U) #define USB_OTG_HCINT_STALL_Msk (0x1U << USB_OTG_HCINT_STALL_Pos) /*!< 0x00000008 */ #define USB_OTG_HCINT_STALL USB_OTG_HCINT_STALL_Msk /*!< STALL response received interrupt */ #define USB_OTG_HCINT_NAK_Pos (4U) #define USB_OTG_HCINT_NAK_Msk (0x1U << USB_OTG_HCINT_NAK_Pos) /*!< 0x00000010 */ #define USB_OTG_HCINT_NAK USB_OTG_HCINT_NAK_Msk /*!< NAK response received interrupt */ #define USB_OTG_HCINT_ACK_Pos (5U) #define USB_OTG_HCINT_ACK_Msk (0x1U << USB_OTG_HCINT_ACK_Pos) /*!< 0x00000020 */ #define USB_OTG_HCINT_ACK USB_OTG_HCINT_ACK_Msk /*!< ACK response received/transmitted interrupt */ #define USB_OTG_HCINT_NYET_Pos (6U) #define USB_OTG_HCINT_NYET_Msk (0x1U << USB_OTG_HCINT_NYET_Pos) /*!< 0x00000040 */ #define USB_OTG_HCINT_NYET USB_OTG_HCINT_NYET_Msk /*!< Response received interrupt */ #define USB_OTG_HCINT_TXERR_Pos (7U) #define USB_OTG_HCINT_TXERR_Msk (0x1U << USB_OTG_HCINT_TXERR_Pos) /*!< 0x00000080 */ #define USB_OTG_HCINT_TXERR USB_OTG_HCINT_TXERR_Msk /*!< Transaction error */ #define USB_OTG_HCINT_BBERR_Pos (8U) #define USB_OTG_HCINT_BBERR_Msk (0x1U << USB_OTG_HCINT_BBERR_Pos) /*!< 0x00000100 */ #define USB_OTG_HCINT_BBERR USB_OTG_HCINT_BBERR_Msk /*!< Babble error */ #define USB_OTG_HCINT_FRMOR_Pos (9U) #define USB_OTG_HCINT_FRMOR_Msk (0x1U << USB_OTG_HCINT_FRMOR_Pos) /*!< 0x00000200 */ #define USB_OTG_HCINT_FRMOR USB_OTG_HCINT_FRMOR_Msk /*!< Frame overrun */ #define USB_OTG_HCINT_DTERR_Pos (10U) #define USB_OTG_HCINT_DTERR_Msk (0x1U << USB_OTG_HCINT_DTERR_Pos) /*!< 0x00000400 */ #define USB_OTG_HCINT_DTERR USB_OTG_HCINT_DTERR_Msk /*!< Data toggle error */ /******************** Bit definition for USB_OTG_DIEPINT register ********************/ #define USB_OTG_DIEPINT_XFRC_Pos (0U) #define USB_OTG_DIEPINT_XFRC_Msk (0x1U << USB_OTG_DIEPINT_XFRC_Pos) /*!< 0x00000001 */ #define USB_OTG_DIEPINT_XFRC USB_OTG_DIEPINT_XFRC_Msk /*!< Transfer completed interrupt */ #define USB_OTG_DIEPINT_EPDISD_Pos (1U) #define USB_OTG_DIEPINT_EPDISD_Msk (0x1U << USB_OTG_DIEPINT_EPDISD_Pos) /*!< 0x00000002 */ #define USB_OTG_DIEPINT_EPDISD USB_OTG_DIEPINT_EPDISD_Msk /*!< Endpoint disabled interrupt */ #define USB_OTG_DIEPINT_TOC_Pos (3U) #define USB_OTG_DIEPINT_TOC_Msk (0x1U << USB_OTG_DIEPINT_TOC_Pos) /*!< 0x00000008 */ #define USB_OTG_DIEPINT_TOC USB_OTG_DIEPINT_TOC_Msk /*!< Timeout condition */ #define USB_OTG_DIEPINT_ITTXFE_Pos (4U) #define USB_OTG_DIEPINT_ITTXFE_Msk (0x1U << USB_OTG_DIEPINT_ITTXFE_Pos) /*!< 0x00000010 */ #define USB_OTG_DIEPINT_ITTXFE USB_OTG_DIEPINT_ITTXFE_Msk /*!< IN token received when TxFIFO is empty */ #define USB_OTG_DIEPINT_INEPNE_Pos (6U) #define USB_OTG_DIEPINT_INEPNE_Msk (0x1U << USB_OTG_DIEPINT_INEPNE_Pos) /*!< 0x00000040 */ #define USB_OTG_DIEPINT_INEPNE USB_OTG_DIEPINT_INEPNE_Msk /*!< IN endpoint NAK effective */ #define USB_OTG_DIEPINT_TXFE_Pos (7U) #define USB_OTG_DIEPINT_TXFE_Msk (0x1U << USB_OTG_DIEPINT_TXFE_Pos) /*!< 0x00000080 */ #define USB_OTG_DIEPINT_TXFE USB_OTG_DIEPINT_TXFE_Msk /*!< Transmit FIFO empty */ #define USB_OTG_DIEPINT_TXFIFOUDRN_Pos (8U) #define USB_OTG_DIEPINT_TXFIFOUDRN_Msk (0x1U << USB_OTG_DIEPINT_TXFIFOUDRN_Pos) /*!< 0x00000100 */ #define USB_OTG_DIEPINT_TXFIFOUDRN USB_OTG_DIEPINT_TXFIFOUDRN_Msk /*!< Transmit Fifo Underrun */ #define USB_OTG_DIEPINT_BNA_Pos (9U) #define USB_OTG_DIEPINT_BNA_Msk (0x1U << USB_OTG_DIEPINT_BNA_Pos) /*!< 0x00000200 */ #define USB_OTG_DIEPINT_BNA USB_OTG_DIEPINT_BNA_Msk /*!< Buffer not available interrupt */ #define USB_OTG_DIEPINT_PKTDRPSTS_Pos (11U) #define USB_OTG_DIEPINT_PKTDRPSTS_Msk (0x1U << USB_OTG_DIEPINT_PKTDRPSTS_Pos) /*!< 0x00000800 */ #define USB_OTG_DIEPINT_PKTDRPSTS USB_OTG_DIEPINT_PKTDRPSTS_Msk /*!< Packet dropped status */ #define USB_OTG_DIEPINT_BERR_Pos (12U) #define USB_OTG_DIEPINT_BERR_Msk (0x1U << USB_OTG_DIEPINT_BERR_Pos) /*!< 0x00001000 */ #define USB_OTG_DIEPINT_BERR USB_OTG_DIEPINT_BERR_Msk /*!< Babble error interrupt */ #define USB_OTG_DIEPINT_NAK_Pos (13U) #define USB_OTG_DIEPINT_NAK_Msk (0x1U << USB_OTG_DIEPINT_NAK_Pos) /*!< 0x00002000 */ #define USB_OTG_DIEPINT_NAK USB_OTG_DIEPINT_NAK_Msk /*!< NAK interrupt */ /******************** Bit definition forUSB_OTG_HCINTMSK register ********************/ #define USB_OTG_HCINTMSK_XFRCM_Pos (0U) #define USB_OTG_HCINTMSK_XFRCM_Msk (0x1U << USB_OTG_HCINTMSK_XFRCM_Pos) /*!< 0x00000001 */ #define USB_OTG_HCINTMSK_XFRCM USB_OTG_HCINTMSK_XFRCM_Msk /*!< Transfer completed mask */ #define USB_OTG_HCINTMSK_CHHM_Pos (1U) #define USB_OTG_HCINTMSK_CHHM_Msk (0x1U << USB_OTG_HCINTMSK_CHHM_Pos) /*!< 0x00000002 */ #define USB_OTG_HCINTMSK_CHHM USB_OTG_HCINTMSK_CHHM_Msk /*!< Channel halted mask */ #define USB_OTG_HCINTMSK_AHBERR_Pos (2U) #define USB_OTG_HCINTMSK_AHBERR_Msk (0x1U << USB_OTG_HCINTMSK_AHBERR_Pos) /*!< 0x00000004 */ #define USB_OTG_HCINTMSK_AHBERR USB_OTG_HCINTMSK_AHBERR_Msk /*!< AHB error */ #define USB_OTG_HCINTMSK_STALLM_Pos (3U) #define USB_OTG_HCINTMSK_STALLM_Msk (0x1U << USB_OTG_HCINTMSK_STALLM_Pos) /*!< 0x00000008 */ #define USB_OTG_HCINTMSK_STALLM USB_OTG_HCINTMSK_STALLM_Msk /*!< STALL response received interrupt mask */ #define USB_OTG_HCINTMSK_NAKM_Pos (4U) #define USB_OTG_HCINTMSK_NAKM_Msk (0x1U << USB_OTG_HCINTMSK_NAKM_Pos) /*!< 0x00000010 */ #define USB_OTG_HCINTMSK_NAKM USB_OTG_HCINTMSK_NAKM_Msk /*!< NAK response received interrupt mask */ #define USB_OTG_HCINTMSK_ACKM_Pos (5U) #define USB_OTG_HCINTMSK_ACKM_Msk (0x1U << USB_OTG_HCINTMSK_ACKM_Pos) /*!< 0x00000020 */ #define USB_OTG_HCINTMSK_ACKM USB_OTG_HCINTMSK_ACKM_Msk /*!< ACK response received/transmitted interrupt mask */ #define USB_OTG_HCINTMSK_NYET_Pos (6U) #define USB_OTG_HCINTMSK_NYET_Msk (0x1U << USB_OTG_HCINTMSK_NYET_Pos) /*!< 0x00000040 */ #define USB_OTG_HCINTMSK_NYET USB_OTG_HCINTMSK_NYET_Msk /*!< response received interrupt mask */ #define USB_OTG_HCINTMSK_TXERRM_Pos (7U) #define USB_OTG_HCINTMSK_TXERRM_Msk (0x1U << USB_OTG_HCINTMSK_TXERRM_Pos) /*!< 0x00000080 */ #define USB_OTG_HCINTMSK_TXERRM USB_OTG_HCINTMSK_TXERRM_Msk /*!< Transaction error mask */ #define USB_OTG_HCINTMSK_BBERRM_Pos (8U) #define USB_OTG_HCINTMSK_BBERRM_Msk (0x1U << USB_OTG_HCINTMSK_BBERRM_Pos) /*!< 0x00000100 */ #define USB_OTG_HCINTMSK_BBERRM USB_OTG_HCINTMSK_BBERRM_Msk /*!< Babble error mask */ #define USB_OTG_HCINTMSK_FRMORM_Pos (9U) #define USB_OTG_HCINTMSK_FRMORM_Msk (0x1U << USB_OTG_HCINTMSK_FRMORM_Pos) /*!< 0x00000200 */ #define USB_OTG_HCINTMSK_FRMORM USB_OTG_HCINTMSK_FRMORM_Msk /*!< Frame overrun mask */ #define USB_OTG_HCINTMSK_DTERRM_Pos (10U) #define USB_OTG_HCINTMSK_DTERRM_Msk (0x1U << USB_OTG_HCINTMSK_DTERRM_Pos) /*!< 0x00000400 */ #define USB_OTG_HCINTMSK_DTERRM USB_OTG_HCINTMSK_DTERRM_Msk /*!< Data toggle error mask */ /******************** Bit definition for USB_OTG_DIEPTSIZ register ********************/ #define USB_OTG_DIEPTSIZ_XFRSIZ_Pos (0U) #define USB_OTG_DIEPTSIZ_XFRSIZ_Msk (0x7FFFFU << USB_OTG_DIEPTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */ #define USB_OTG_DIEPTSIZ_XFRSIZ USB_OTG_DIEPTSIZ_XFRSIZ_Msk /*!< Transfer size */ #define USB_OTG_DIEPTSIZ_PKTCNT_Pos (19U) #define USB_OTG_DIEPTSIZ_PKTCNT_Msk (0x3FFU << USB_OTG_DIEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */ #define USB_OTG_DIEPTSIZ_PKTCNT USB_OTG_DIEPTSIZ_PKTCNT_Msk /*!< Packet count */ #define USB_OTG_DIEPTSIZ_MULCNT_Pos (29U) #define USB_OTG_DIEPTSIZ_MULCNT_Msk (0x3U << USB_OTG_DIEPTSIZ_MULCNT_Pos) /*!< 0x60000000 */ #define USB_OTG_DIEPTSIZ_MULCNT USB_OTG_DIEPTSIZ_MULCNT_Msk /*!< Packet count */ /******************** Bit definition for USB_OTG_HCTSIZ register ********************/ #define USB_OTG_HCTSIZ_XFRSIZ_Pos (0U) #define USB_OTG_HCTSIZ_XFRSIZ_Msk (0x7FFFFU << USB_OTG_HCTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */ #define USB_OTG_HCTSIZ_XFRSIZ USB_OTG_HCTSIZ_XFRSIZ_Msk /*!< Transfer size */ #define USB_OTG_HCTSIZ_PKTCNT_Pos (19U) #define USB_OTG_HCTSIZ_PKTCNT_Msk (0x3FFU << USB_OTG_HCTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */ #define USB_OTG_HCTSIZ_PKTCNT USB_OTG_HCTSIZ_PKTCNT_Msk /*!< Packet count */ #define USB_OTG_HCTSIZ_DOPING_Pos (31U) #define USB_OTG_HCTSIZ_DOPING_Msk (0x1U << USB_OTG_HCTSIZ_DOPING_Pos) /*!< 0x80000000 */ #define USB_OTG_HCTSIZ_DOPING USB_OTG_HCTSIZ_DOPING_Msk /*!< Do PING */ #define USB_OTG_HCTSIZ_DPID_Pos (29U) #define USB_OTG_HCTSIZ_DPID_Msk (0x3U << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x60000000 */ #define USB_OTG_HCTSIZ_DPID USB_OTG_HCTSIZ_DPID_Msk /*!< Data PID */ #define USB_OTG_HCTSIZ_DPID_0 (0x1U << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x20000000 */ #define USB_OTG_HCTSIZ_DPID_1 (0x2U << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x40000000 */ /******************** Bit definition for USB_OTG_DIEPDMA register ********************/ #define USB_OTG_DIEPDMA_DMAADDR_Pos (0U) #define USB_OTG_DIEPDMA_DMAADDR_Msk (0xFFFFFFFFU << USB_OTG_DIEPDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */ #define USB_OTG_DIEPDMA_DMAADDR USB_OTG_DIEPDMA_DMAADDR_Msk /*!< DMA address */ /******************** Bit definition for USB_OTG_HCDMA register ********************/ #define USB_OTG_HCDMA_DMAADDR_Pos (0U) #define USB_OTG_HCDMA_DMAADDR_Msk (0xFFFFFFFFU << USB_OTG_HCDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */ #define USB_OTG_HCDMA_DMAADDR USB_OTG_HCDMA_DMAADDR_Msk /*!< DMA address */ /******************** Bit definition for USB_OTG_DTXFSTS register ********************/ #define USB_OTG_DTXFSTS_INEPTFSAV_Pos (0U) #define USB_OTG_DTXFSTS_INEPTFSAV_Msk (0xFFFFU << USB_OTG_DTXFSTS_INEPTFSAV_Pos) /*!< 0x0000FFFF */ #define USB_OTG_DTXFSTS_INEPTFSAV USB_OTG_DTXFSTS_INEPTFSAV_Msk /*!< IN endpoint TxFIFO space available */ /******************** Bit definition for USB_OTG_DIEPTXF register ********************/ #define USB_OTG_DIEPTXF_INEPTXSA_Pos (0U) #define USB_OTG_DIEPTXF_INEPTXSA_Msk (0xFFFFU << USB_OTG_DIEPTXF_INEPTXSA_Pos) /*!< 0x0000FFFF */ #define USB_OTG_DIEPTXF_INEPTXSA USB_OTG_DIEPTXF_INEPTXSA_Msk /*!< IN endpoint FIFOx transmit RAM start address */ #define USB_OTG_DIEPTXF_INEPTXFD_Pos (16U) #define USB_OTG_DIEPTXF_INEPTXFD_Msk (0xFFFFU << USB_OTG_DIEPTXF_INEPTXFD_Pos) /*!< 0xFFFF0000 */ #define USB_OTG_DIEPTXF_INEPTXFD USB_OTG_DIEPTXF_INEPTXFD_Msk /*!< IN endpoint TxFIFO depth */ /******************** Bit definition for USB_OTG_DOEPCTL register ********************/ #define USB_OTG_DOEPCTL_MPSIZ_Pos (0U) #define USB_OTG_DOEPCTL_MPSIZ_Msk (0x7FFU << USB_OTG_DOEPCTL_MPSIZ_Pos) /*!< 0x000007FF */ #define USB_OTG_DOEPCTL_MPSIZ USB_OTG_DOEPCTL_MPSIZ_Msk /*!< Maximum packet size */ /*!<Bit 1 */ #define USB_OTG_DOEPCTL_USBAEP_Pos (15U) #define USB_OTG_DOEPCTL_USBAEP_Msk (0x1U << USB_OTG_DOEPCTL_USBAEP_Pos) /*!< 0x00008000 */ #define USB_OTG_DOEPCTL_USBAEP USB_OTG_DOEPCTL_USBAEP_Msk /*!< USB active endpoint */ #define USB_OTG_DOEPCTL_NAKSTS_Pos (17U) #define USB_OTG_DOEPCTL_NAKSTS_Msk (0x1U << USB_OTG_DOEPCTL_NAKSTS_Pos) /*!< 0x00020000 */ #define USB_OTG_DOEPCTL_NAKSTS USB_OTG_DOEPCTL_NAKSTS_Msk /*!< NAK status */ #define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos (28U) #define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk (0x1U << USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */ #define USB_OTG_DOEPCTL_SD0PID_SEVNFRM USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */ #define USB_OTG_DOEPCTL_SODDFRM_Pos (29U) #define USB_OTG_DOEPCTL_SODDFRM_Msk (0x1U << USB_OTG_DOEPCTL_SODDFRM_Pos) /*!< 0x20000000 */ #define USB_OTG_DOEPCTL_SODDFRM USB_OTG_DOEPCTL_SODDFRM_Msk /*!< Set odd frame */ #define USB_OTG_DOEPCTL_EPTYP_Pos (18U) #define USB_OTG_DOEPCTL_EPTYP_Msk (0x3U << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x000C0000 */ #define USB_OTG_DOEPCTL_EPTYP USB_OTG_DOEPCTL_EPTYP_Msk /*!< Endpoint type */ #define USB_OTG_DOEPCTL_EPTYP_0 (0x1U << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x00040000 */ #define USB_OTG_DOEPCTL_EPTYP_1 (0x2U << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x00080000 */ #define USB_OTG_DOEPCTL_SNPM_Pos (20U) #define USB_OTG_DOEPCTL_SNPM_Msk (0x1U << USB_OTG_DOEPCTL_SNPM_Pos) /*!< 0x00100000 */ #define USB_OTG_DOEPCTL_SNPM USB_OTG_DOEPCTL_SNPM_Msk /*!< Snoop mode */ #define USB_OTG_DOEPCTL_STALL_Pos (21U) #define USB_OTG_DOEPCTL_STALL_Msk (0x1U << USB_OTG_DOEPCTL_STALL_Pos) /*!< 0x00200000 */ #define USB_OTG_DOEPCTL_STALL USB_OTG_DOEPCTL_STALL_Msk /*!< STALL handshake */ #define USB_OTG_DOEPCTL_CNAK_Pos (26U) #define USB_OTG_DOEPCTL_CNAK_Msk (0x1U << USB_OTG_DOEPCTL_CNAK_Pos) /*!< 0x04000000 */ #define USB_OTG_DOEPCTL_CNAK USB_OTG_DOEPCTL_CNAK_Msk /*!< Clear NAK */ #define USB_OTG_DOEPCTL_SNAK_Pos (27U) #define USB_OTG_DOEPCTL_SNAK_Msk (0x1U << USB_OTG_DOEPCTL_SNAK_Pos) /*!< 0x08000000 */ #define USB_OTG_DOEPCTL_SNAK USB_OTG_DOEPCTL_SNAK_Msk /*!< Set NAK */ #define USB_OTG_DOEPCTL_EPDIS_Pos (30U) #define USB_OTG_DOEPCTL_EPDIS_Msk (0x1U << USB_OTG_DOEPCTL_EPDIS_Pos) /*!< 0x40000000 */ #define USB_OTG_DOEPCTL_EPDIS USB_OTG_DOEPCTL_EPDIS_Msk /*!< Endpoint disable */ #define USB_OTG_DOEPCTL_EPENA_Pos (31U) #define USB_OTG_DOEPCTL_EPENA_Msk (0x1U << USB_OTG_DOEPCTL_EPENA_Pos) /*!< 0x80000000 */ #define USB_OTG_DOEPCTL_EPENA USB_OTG_DOEPCTL_EPENA_Msk /*!< Endpoint enable */ /******************** Bit definition for USB_OTG_DOEPINT register ********************/ #define USB_OTG_DOEPINT_XFRC_Pos (0U) #define USB_OTG_DOEPINT_XFRC_Msk (0x1U << USB_OTG_DOEPINT_XFRC_Pos) /*!< 0x00000001 */ #define USB_OTG_DOEPINT_XFRC USB_OTG_DOEPINT_XFRC_Msk /*!< Transfer completed interrupt */ #define USB_OTG_DOEPINT_EPDISD_Pos (1U) #define USB_OTG_DOEPINT_EPDISD_Msk (0x1U << USB_OTG_DOEPINT_EPDISD_Pos) /*!< 0x00000002 */ #define USB_OTG_DOEPINT_EPDISD USB_OTG_DOEPINT_EPDISD_Msk /*!< Endpoint disabled interrupt */ #define USB_OTG_DOEPINT_STUP_Pos (3U) #define USB_OTG_DOEPINT_STUP_Msk (0x1U << USB_OTG_DOEPINT_STUP_Pos) /*!< 0x00000008 */ #define USB_OTG_DOEPINT_STUP USB_OTG_DOEPINT_STUP_Msk /*!< SETUP phase done */ #define USB_OTG_DOEPINT_OTEPDIS_Pos (4U) #define USB_OTG_DOEPINT_OTEPDIS_Msk (0x1U << USB_OTG_DOEPINT_OTEPDIS_Pos) /*!< 0x00000010 */ #define USB_OTG_DOEPINT_OTEPDIS USB_OTG_DOEPINT_OTEPDIS_Msk /*!< OUT token received when endpoint disabled */ #define USB_OTG_DOEPINT_OTEPSPR_Pos (5U) #define USB_OTG_DOEPINT_OTEPSPR_Msk (0x1U << USB_OTG_DOEPINT_OTEPSPR_Pos) /*!< 0x00000020 */ #define USB_OTG_DOEPINT_OTEPSPR USB_OTG_DOEPINT_OTEPSPR_Msk /*!< Status Phase Received For Control Write */ #define USB_OTG_DOEPINT_B2BSTUP_Pos (6U) #define USB_OTG_DOEPINT_B2BSTUP_Msk (0x1U << USB_OTG_DOEPINT_B2BSTUP_Pos) /*!< 0x00000040 */ #define USB_OTG_DOEPINT_B2BSTUP USB_OTG_DOEPINT_B2BSTUP_Msk /*!< Back-to-back SETUP packets received */ #define USB_OTG_DOEPINT_NYET_Pos (14U) #define USB_OTG_DOEPINT_NYET_Msk (0x1U << USB_OTG_DOEPINT_NYET_Pos) /*!< 0x00004000 */ #define USB_OTG_DOEPINT_NYET USB_OTG_DOEPINT_NYET_Msk /*!< NYET interrupt */ /******************** Bit definition for USB_OTG_DOEPTSIZ register ********************/ #define USB_OTG_DOEPTSIZ_XFRSIZ_Pos (0U) #define USB_OTG_DOEPTSIZ_XFRSIZ_Msk (0x7FFFFU << USB_OTG_DOEPTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */ #define USB_OTG_DOEPTSIZ_XFRSIZ USB_OTG_DOEPTSIZ_XFRSIZ_Msk /*!< Transfer size */ #define USB_OTG_DOEPTSIZ_PKTCNT_Pos (19U) #define USB_OTG_DOEPTSIZ_PKTCNT_Msk (0x3FFU << USB_OTG_DOEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */ #define USB_OTG_DOEPTSIZ_PKTCNT USB_OTG_DOEPTSIZ_PKTCNT_Msk /*!< Packet count */ #define USB_OTG_DOEPTSIZ_STUPCNT_Pos (29U) #define USB_OTG_DOEPTSIZ_STUPCNT_Msk (0x3U << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x60000000 */ #define USB_OTG_DOEPTSIZ_STUPCNT USB_OTG_DOEPTSIZ_STUPCNT_Msk /*!< SETUP packet count */ #define USB_OTG_DOEPTSIZ_STUPCNT_0 (0x1U << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x20000000 */ #define USB_OTG_DOEPTSIZ_STUPCNT_1 (0x2U << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x40000000 */ /******************** Bit definition for PCGCCTL register ********************/ #define USB_OTG_PCGCCTL_STOPCLK_Pos (0U) #define USB_OTG_PCGCCTL_STOPCLK_Msk (0x1U << USB_OTG_PCGCCTL_STOPCLK_Pos) /*!< 0x00000001 */ #define USB_OTG_PCGCCTL_STOPCLK USB_OTG_PCGCCTL_STOPCLK_Msk /*!< SETUP packet count */ #define USB_OTG_PCGCCTL_GATECLK_Pos (1U) #define USB_OTG_PCGCCTL_GATECLK_Msk (0x1U << USB_OTG_PCGCCTL_GATECLK_Pos) /*!< 0x00000002 */ #define USB_OTG_PCGCCTL_GATECLK USB_OTG_PCGCCTL_GATECLK_Msk /*!<Bit 0 */ #define USB_OTG_PCGCCTL_PHYSUSP_Pos (4U) #define USB_OTG_PCGCCTL_PHYSUSP_Msk (0x1U << USB_OTG_PCGCCTL_PHYSUSP_Pos) /*!< 0x00000010 */ #define USB_OTG_PCGCCTL_PHYSUSP USB_OTG_PCGCCTL_PHYSUSP_Msk /*!<Bit 1 */ /* Legacy define */ /******************** Bit definition for OTG register ********************/ #define USB_OTG_CHNUM_Pos (0U) #define USB_OTG_CHNUM_Msk (0xFU << USB_OTG_CHNUM_Pos) /*!< 0x0000000F */ #define USB_OTG_CHNUM USB_OTG_CHNUM_Msk /*!< Channel number */ #define USB_OTG_CHNUM_0 (0x1U << USB_OTG_CHNUM_Pos) /*!< 0x00000001 */ #define USB_OTG_CHNUM_1 (0x2U << USB_OTG_CHNUM_Pos) /*!< 0x00000002 */ #define USB_OTG_CHNUM_2 (0x4U << USB_OTG_CHNUM_Pos) /*!< 0x00000004 */ #define USB_OTG_CHNUM_3 (0x8U << USB_OTG_CHNUM_Pos) /*!< 0x00000008 */ #define USB_OTG_BCNT_Pos (4U) #define USB_OTG_BCNT_Msk (0x7FFU << USB_OTG_BCNT_Pos) /*!< 0x00007FF0 */ #define USB_OTG_BCNT USB_OTG_BCNT_Msk /*!< Byte count */ #define USB_OTG_DPID_Pos (15U) #define USB_OTG_DPID_Msk (0x3U << USB_OTG_DPID_Pos) /*!< 0x00018000 */ #define USB_OTG_DPID USB_OTG_DPID_Msk /*!< Data PID */ #define USB_OTG_DPID_0 (0x1U << USB_OTG_DPID_Pos) /*!< 0x00008000 */ #define USB_OTG_DPID_1 (0x2U << USB_OTG_DPID_Pos) /*!< 0x00010000 */ #define USB_OTG_PKTSTS_Pos (17U) #define USB_OTG_PKTSTS_Msk (0xFU << USB_OTG_PKTSTS_Pos) /*!< 0x001E0000 */ #define USB_OTG_PKTSTS USB_OTG_PKTSTS_Msk /*!< Packet status */ #define USB_OTG_PKTSTS_0 (0x1U << USB_OTG_PKTSTS_Pos) /*!< 0x00020000 */ #define USB_OTG_PKTSTS_1 (0x2U << USB_OTG_PKTSTS_Pos) /*!< 0x00040000 */ #define USB_OTG_PKTSTS_2 (0x4U << USB_OTG_PKTSTS_Pos) /*!< 0x00080000 */ #define USB_OTG_PKTSTS_3 (0x8U << USB_OTG_PKTSTS_Pos) /*!< 0x00100000 */ #define USB_OTG_EPNUM_Pos (0U) #define USB_OTG_EPNUM_Msk (0xFU << USB_OTG_EPNUM_Pos) /*!< 0x0000000F */ #define USB_OTG_EPNUM USB_OTG_EPNUM_Msk /*!< Endpoint number */ #define USB_OTG_EPNUM_0 (0x1U << USB_OTG_EPNUM_Pos) /*!< 0x00000001 */ #define USB_OTG_EPNUM_1 (0x2U << USB_OTG_EPNUM_Pos) /*!< 0x00000002 */ #define USB_OTG_EPNUM_2 (0x4U << USB_OTG_EPNUM_Pos) /*!< 0x00000004 */ #define USB_OTG_EPNUM_3 (0x8U << USB_OTG_EPNUM_Pos) /*!< 0x00000008 */ #define USB_OTG_FRMNUM_Pos (21U) #define USB_OTG_FRMNUM_Msk (0xFU << USB_OTG_FRMNUM_Pos) /*!< 0x01E00000 */ #define USB_OTG_FRMNUM USB_OTG_FRMNUM_Msk /*!< Frame number */ #define USB_OTG_FRMNUM_0 (0x1U << USB_OTG_FRMNUM_Pos) /*!< 0x00200000 */ #define USB_OTG_FRMNUM_1 (0x2U << USB_OTG_FRMNUM_Pos) /*!< 0x00400000 */ #define USB_OTG_FRMNUM_2 (0x4U << USB_OTG_FRMNUM_Pos) /*!< 0x00800000 */ #define USB_OTG_FRMNUM_3 (0x8U << USB_OTG_FRMNUM_Pos) /*!< 0x01000000 */ /** * @} */ /** * @} */ /** @addtogroup Exported_macros * @{ */ /******************************* ADC Instances ********************************/ #define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1) || \ ((INSTANCE) == ADC2) || \ ((INSTANCE) == ADC3)) #define IS_ADC_MULTIMODE_MASTER_INSTANCE(INSTANCE) ((INSTANCE) == ADC1) #define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC123_COMMON) /******************************* CAN Instances ********************************/ #define IS_CAN_ALL_INSTANCE(INSTANCE) (((INSTANCE) == CAN1) || \ ((INSTANCE) == CAN2)) /******************************* CRC Instances ********************************/ #define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC) /******************************* DAC Instances ********************************/ #define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC1) /******************************* DCMI Instances *******************************/ #define IS_DCMI_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DCMI) /******************************* DMA2D Instances *******************************/ #define IS_DMA2D_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DMA2D) /******************************** DMA Instances *******************************/ #define IS_DMA_STREAM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0) || \ ((INSTANCE) == DMA1_Stream1) || \ ((INSTANCE) == DMA1_Stream2) || \ ((INSTANCE) == DMA1_Stream3) || \ ((INSTANCE) == DMA1_Stream4) || \ ((INSTANCE) == DMA1_Stream5) || \ ((INSTANCE) == DMA1_Stream6) || \ ((INSTANCE) == DMA1_Stream7) || \ ((INSTANCE) == DMA2_Stream0) || \ ((INSTANCE) == DMA2_Stream1) || \ ((INSTANCE) == DMA2_Stream2) || \ ((INSTANCE) == DMA2_Stream3) || \ ((INSTANCE) == DMA2_Stream4) || \ ((INSTANCE) == DMA2_Stream5) || \ ((INSTANCE) == DMA2_Stream6) || \ ((INSTANCE) == DMA2_Stream7)) /******************************* GPIO Instances *******************************/ #define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \ ((INSTANCE) == GPIOB) || \ ((INSTANCE) == GPIOC) || \ ((INSTANCE) == GPIOD) || \ ((INSTANCE) == GPIOE) || \ ((INSTANCE) == GPIOF) || \ ((INSTANCE) == GPIOG) || \ ((INSTANCE) == GPIOH) || \ ((INSTANCE) == GPIOI) || \ ((INSTANCE) == GPIOJ) || \ ((INSTANCE) == GPIOK)) /******************************** I2C Instances *******************************/ #define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \ ((INSTANCE) == I2C2) || \ ((INSTANCE) == I2C3)) /******************************* SMBUS Instances ******************************/ #define IS_SMBUS_ALL_INSTANCE IS_I2C_ALL_INSTANCE /******************************** I2S Instances *******************************/ #define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI2) || \ ((INSTANCE) == SPI3)) /*************************** I2S Extended Instances ***************************/ #define IS_I2S_EXT_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2S2ext)|| \ ((INSTANCE) == I2S3ext)) /* Legacy Defines */ #define IS_I2S_ALL_INSTANCE_EXT IS_I2S_EXT_ALL_INSTANCE /****************************** LTDC Instances ********************************/ #define IS_LTDC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == LTDC) /******************************* RNG Instances ********************************/ #define IS_RNG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RNG) /****************************** RTC Instances *********************************/ #define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC) /******************************* SAI Instances ********************************/ #define IS_SAI_ALL_INSTANCE(PERIPH) (((PERIPH) == SAI1_Block_A) || \ ((PERIPH) == SAI1_Block_B)) /* Legacy define */ #define IS_SAI_BLOCK_PERIPH IS_SAI_ALL_INSTANCE /******************************** SPI Instances *******************************/ #define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \ ((INSTANCE) == SPI2) || \ ((INSTANCE) == SPI3) || \ ((INSTANCE) == SPI4) || \ ((INSTANCE) == SPI5) || \ ((INSTANCE) == SPI6)) /****************** TIM Instances : All supported instances *******************/ #define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ ((INSTANCE) == TIM2) || \ ((INSTANCE) == TIM3) || \ ((INSTANCE) == TIM4) || \ ((INSTANCE) == TIM5) || \ ((INSTANCE) == TIM6) || \ ((INSTANCE) == TIM7) || \ ((INSTANCE) == TIM8) || \ ((INSTANCE) == TIM9) || \ ((INSTANCE) == TIM10)|| \ ((INSTANCE) == TIM11)|| \ ((INSTANCE) == TIM12)|| \ ((INSTANCE) == TIM13)|| \ ((INSTANCE) == TIM14)) /************* TIM Instances : at least 1 capture/compare channel *************/ #define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ ((INSTANCE) == TIM2) || \ ((INSTANCE) == TIM3) || \ ((INSTANCE) == TIM4) || \ ((INSTANCE) == TIM5) || \ ((INSTANCE) == TIM8) || \ ((INSTANCE) == TIM9) || \ ((INSTANCE) == TIM10) || \ ((INSTANCE) == TIM11) || \ ((INSTANCE) == TIM12) || \ ((INSTANCE) == TIM13) || \ ((INSTANCE) == TIM14)) /************ TIM Instances : at least 2 capture/compare channels *************/ #define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ ((INSTANCE) == TIM2) || \ ((INSTANCE) == TIM3) || \ ((INSTANCE) == TIM4) || \ ((INSTANCE) == TIM5) || \ ((INSTANCE) == TIM8) || \ ((INSTANCE) == TIM9) || \ ((INSTANCE) == TIM12)) /************ TIM Instances : at least 3 capture/compare channels *************/ #define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ ((INSTANCE) == TIM2) || \ ((INSTANCE) == TIM3) || \ ((INSTANCE) == TIM4) || \ ((INSTANCE) == TIM5) || \ ((INSTANCE) == TIM8)) /************ TIM Instances : at least 4 capture/compare channels *************/ #define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ ((INSTANCE) == TIM2) || \ ((INSTANCE) == TIM3) || \ ((INSTANCE) == TIM4) || \ ((INSTANCE) == TIM5) || \ ((INSTANCE) == TIM8)) /******************** TIM Instances : Advanced-control timers *****************/ #define IS_TIM_ADVANCED_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ ((INSTANCE) == TIM8)) /******************* TIM Instances : Timer input XOR function *****************/ #define IS_TIM_XOR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ ((INSTANCE) == TIM2) || \ ((INSTANCE) == TIM3) || \ ((INSTANCE) == TIM4) || \ ((INSTANCE) == TIM5) || \ ((INSTANCE) == TIM8)) /****************** TIM Instances : DMA requests generation (UDE) *************/ #define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ ((INSTANCE) == TIM2) || \ ((INSTANCE) == TIM3) || \ ((INSTANCE) == TIM4) || \ ((INSTANCE) == TIM5) || \ ((INSTANCE) == TIM6) || \ ((INSTANCE) == TIM7) || \ ((INSTANCE) == TIM8)) /************ TIM Instances : DMA requests generation (CCxDE) *****************/ #define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ ((INSTANCE) == TIM2) || \ ((INSTANCE) == TIM3) || \ ((INSTANCE) == TIM4) || \ ((INSTANCE) == TIM5) || \ ((INSTANCE) == TIM8)) /************ TIM Instances : DMA requests generation (COMDE) *****************/ #define IS_TIM_CCDMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ ((INSTANCE) == TIM2) || \ ((INSTANCE) == TIM3) || \ ((INSTANCE) == TIM4) || \ ((INSTANCE) == TIM5) || \ ((INSTANCE) == TIM8)) /******************** TIM Instances : DMA burst feature ***********************/ #define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ ((INSTANCE) == TIM2) || \ ((INSTANCE) == TIM3) || \ ((INSTANCE) == TIM4) || \ ((INSTANCE) == TIM5) || \ ((INSTANCE) == TIM8)) /****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/ #define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ ((INSTANCE) == TIM2) || \ ((INSTANCE) == TIM3) || \ ((INSTANCE) == TIM4) || \ ((INSTANCE) == TIM5) || \ ((INSTANCE) == TIM6) || \ ((INSTANCE) == TIM7) || \ ((INSTANCE) == TIM8)) /*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/ #define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ ((INSTANCE) == TIM2) || \ ((INSTANCE) == TIM3) || \ ((INSTANCE) == TIM4) || \ ((INSTANCE) == TIM5) || \ ((INSTANCE) == TIM8) || \ ((INSTANCE) == TIM9) || \ ((INSTANCE) == TIM12)) /********************** TIM Instances : 32 bit Counter ************************/ #define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)(((INSTANCE) == TIM2) || \ ((INSTANCE) == TIM5)) /***************** TIM Instances : external trigger input availabe ************/ #define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ ((INSTANCE) == TIM2) || \ ((INSTANCE) == TIM3) || \ ((INSTANCE) == TIM4) || \ ((INSTANCE) == TIM5) || \ ((INSTANCE) == TIM8)) /****************** TIM Instances : remapping capability **********************/ #define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \ ((INSTANCE) == TIM5) || \ ((INSTANCE) == TIM11)) /******************* TIM Instances : output(s) available **********************/ #define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \ ((((INSTANCE) == TIM1) && \ (((CHANNEL) == TIM_CHANNEL_1) || \ ((CHANNEL) == TIM_CHANNEL_2) || \ ((CHANNEL) == TIM_CHANNEL_3) || \ ((CHANNEL) == TIM_CHANNEL_4))) \ || \ (((INSTANCE) == TIM2) && \ (((CHANNEL) == TIM_CHANNEL_1) || \ ((CHANNEL) == TIM_CHANNEL_2) || \ ((CHANNEL) == TIM_CHANNEL_3) || \ ((CHANNEL) == TIM_CHANNEL_4))) \ || \ (((INSTANCE) == TIM3) && \ (((CHANNEL) == TIM_CHANNEL_1) || \ ((CHANNEL) == TIM_CHANNEL_2) || \ ((CHANNEL) == TIM_CHANNEL_3) || \ ((CHANNEL) == TIM_CHANNEL_4))) \ || \ (((INSTANCE) == TIM4) && \ (((CHANNEL) == TIM_CHANNEL_1) || \ ((CHANNEL) == TIM_CHANNEL_2) || \ ((CHANNEL) == TIM_CHANNEL_3) || \ ((CHANNEL) == TIM_CHANNEL_4))) \ || \ (((INSTANCE) == TIM5) && \ (((CHANNEL) == TIM_CHANNEL_1) || \ ((CHANNEL) == TIM_CHANNEL_2) || \ ((CHANNEL) == TIM_CHANNEL_3) || \ ((CHANNEL) == TIM_CHANNEL_4))) \ || \ (((INSTANCE) == TIM8) && \ (((CHANNEL) == TIM_CHANNEL_1) || \ ((CHANNEL) == TIM_CHANNEL_2) || \ ((CHANNEL) == TIM_CHANNEL_3) || \ ((CHANNEL) == TIM_CHANNEL_4))) \ || \ (((INSTANCE) == TIM9) && \ (((CHANNEL) == TIM_CHANNEL_1) || \ ((CHANNEL) == TIM_CHANNEL_2))) \ || \ (((INSTANCE) == TIM10) && \ (((CHANNEL) == TIM_CHANNEL_1))) \ || \ (((INSTANCE) == TIM11) && \ (((CHANNEL) == TIM_CHANNEL_1))) \ || \ (((INSTANCE) == TIM12) && \ (((CHANNEL) == TIM_CHANNEL_1) || \ ((CHANNEL) == TIM_CHANNEL_2))) \ || \ (((INSTANCE) == TIM13) && \ (((CHANNEL) == TIM_CHANNEL_1))) \ || \ (((INSTANCE) == TIM14) && \ (((CHANNEL) == TIM_CHANNEL_1)))) /************ TIM Instances : complementary output(s) available ***************/ #define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \ ((((INSTANCE) == TIM1) && \ (((CHANNEL) == TIM_CHANNEL_1) || \ ((CHANNEL) == TIM_CHANNEL_2) || \ ((CHANNEL) == TIM_CHANNEL_3))) \ || \ (((INSTANCE) == TIM8) && \ (((CHANNEL) == TIM_CHANNEL_1) || \ ((CHANNEL) == TIM_CHANNEL_2) || \ ((CHANNEL) == TIM_CHANNEL_3)))) /****************** TIM Instances : supporting counting mode selection ********/ #define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ ((INSTANCE) == TIM2) || \ ((INSTANCE) == TIM3) || \ ((INSTANCE) == TIM4) || \ ((INSTANCE) == TIM5) || \ ((INSTANCE) == TIM8)) /****************** TIM Instances : supporting clock division *****************/ #define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ ((INSTANCE) == TIM2) || \ ((INSTANCE) == TIM3) || \ ((INSTANCE) == TIM4) || \ ((INSTANCE) == TIM5) || \ ((INSTANCE) == TIM8) || \ ((INSTANCE) == TIM9) || \ ((INSTANCE) == TIM10)|| \ ((INSTANCE) == TIM11)|| \ ((INSTANCE) == TIM12)|| \ ((INSTANCE) == TIM13)|| \ ((INSTANCE) == TIM14)) /****************** TIM Instances : supporting commutation event generation ***/ #define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)|| \ ((INSTANCE) == TIM8)) /****************** TIM Instances : supporting OCxREF clear *******************/ #define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ ((INSTANCE) == TIM2) || \ ((INSTANCE) == TIM3) || \ ((INSTANCE) == TIM4) || \ ((INSTANCE) == TIM5) || \ ((INSTANCE) == TIM8)) /****** TIM Instances : supporting external clock mode 1 for ETRF input *******/ #define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ ((INSTANCE) == TIM2) || \ ((INSTANCE) == TIM3) || \ ((INSTANCE) == TIM4) || \ ((INSTANCE) == TIM5) || \ ((INSTANCE) == TIM8) || \ ((INSTANCE) == TIM9) || \ ((INSTANCE) == TIM12)) /****** TIM Instances : supporting external clock mode 2 for ETRF input *******/ #define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ ((INSTANCE) == TIM2) || \ ((INSTANCE) == TIM3) || \ ((INSTANCE) == TIM4) || \ ((INSTANCE) == TIM5) || \ ((INSTANCE) == TIM8)) /****************** TIM Instances : supporting repetition counter *************/ #define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ ((INSTANCE) == TIM8)) /****************** TIM Instances : supporting encoder interface **************/ #define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ ((INSTANCE) == TIM2) || \ ((INSTANCE) == TIM3) || \ ((INSTANCE) == TIM4) || \ ((INSTANCE) == TIM5) || \ ((INSTANCE) == TIM8) || \ ((INSTANCE) == TIM9) || \ ((INSTANCE) == TIM12)) /****************** TIM Instances : supporting Hall sensor interface **********/ #define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ ((INSTANCE) == TIM2) || \ ((INSTANCE) == TIM3) || \ ((INSTANCE) == TIM4) || \ ((INSTANCE) == TIM5) || \ ((INSTANCE) == TIM8)) /****************** TIM Instances : supporting the break function *************/ #define IS_TIM_BREAK_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ ((INSTANCE) == TIM8)) /******************** USART Instances : Synchronous mode **********************/ #define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ ((INSTANCE) == USART2) || \ ((INSTANCE) == USART3) || \ ((INSTANCE) == USART6)) /******************** UART Instances : Half-Duplex mode **********************/ #define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ ((INSTANCE) == USART2) || \ ((INSTANCE) == USART3) || \ ((INSTANCE) == UART4) || \ ((INSTANCE) == UART5) || \ ((INSTANCE) == USART6) || \ ((INSTANCE) == UART7) || \ ((INSTANCE) == UART8)) /* Legacy defines */ #define IS_UART_INSTANCE IS_UART_HALFDUPLEX_INSTANCE /****************** UART Instances : Hardware Flow control ********************/ #define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ ((INSTANCE) == USART2) || \ ((INSTANCE) == USART3) || \ ((INSTANCE) == USART6)) /******************** UART Instances : LIN mode **********************/ #define IS_UART_LIN_INSTANCE IS_UART_HALFDUPLEX_INSTANCE /********************* UART Instances : Smart card mode ***********************/ #define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ ((INSTANCE) == USART2) || \ ((INSTANCE) == USART3) || \ ((INSTANCE) == USART6)) /*********************** UART Instances : IRDA mode ***************************/ #define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ ((INSTANCE) == USART2) || \ ((INSTANCE) == USART3) || \ ((INSTANCE) == UART4) || \ ((INSTANCE) == UART5) || \ ((INSTANCE) == USART6) || \ ((INSTANCE) == UART7) || \ ((INSTANCE) == UART8)) /*********************** PCD Instances ****************************************/ #define IS_PCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS) || \ ((INSTANCE) == USB_OTG_HS)) /*********************** HCD Instances ****************************************/ #define IS_HCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS) || \ ((INSTANCE) == USB_OTG_HS)) /****************************** SDIO Instances ********************************/ #define IS_SDIO_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SDIO) /****************************** IWDG Instances ********************************/ #define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG) /****************************** WWDG Instances ********************************/ #define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG) /****************************** QSPI Instances ********************************/ #define IS_QSPI_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == QUADSPI) /****************************** USB Exported Constants ************************/ #define USB_OTG_FS_HOST_MAX_CHANNEL_NBR 12U #define USB_OTG_FS_MAX_IN_ENDPOINTS 6U /* Including EP0 */ #define USB_OTG_FS_MAX_OUT_ENDPOINTS 6U /* Including EP0 */ #define USB_OTG_FS_TOTAL_FIFO_SIZE 1280U /* in Bytes */ #define USB_OTG_HS_HOST_MAX_CHANNEL_NBR 16U #define USB_OTG_HS_MAX_IN_ENDPOINTS 8U /* Including EP0 */ #define USB_OTG_HS_MAX_OUT_ENDPOINTS 8U /* Including EP0 */ #define USB_OTG_HS_TOTAL_FIFO_SIZE 4096U /* in Bytes */ /* * @brief Specific devices reset values definitions */ #define RCC_PLLCFGR_RST_VALUE 0x24003010U #define RCC_PLLI2SCFGR_RST_VALUE 0x24003000U #define RCC_PLLSAICFGR_RST_VALUE 0x24003000U #define RCC_MAX_FREQUENCY 180000000U /*!< Max frequency of family in Hz*/ #define RCC_MAX_FREQUENCY_SCALE1 RCC_MAX_FREQUENCY /*!< Maximum frequency for system clock at power scale1, in Hz */ #define RCC_MAX_FREQUENCY_SCALE2 168000000U /*!< Maximum frequency for system clock at power scale2, in Hz */ #define RCC_MAX_FREQUENCY_SCALE3 120000000U /*!< Maximum frequency for system clock at power scale3, in Hz */ #define RCC_PLLVCO_OUTPUT_MIN 192000000U /*!< Frequency min for PLLVCO output, in Hz */ #define RCC_PLLVCO_INPUT_MIN 950000U /*!< Frequency min for PLLVCO input, in Hz */ #define RCC_PLLVCO_INPUT_MAX 2100000U /*!< Frequency max for PLLVCO input, in Hz */ #define RCC_PLLVCO_OUTPUT_MAX 432000000U /*!< Frequency max for PLLVCO output, in Hz */ #define RCC_PLLN_MIN_VALUE 50U #define RCC_PLLN_MAX_VALUE 432U #define FLASH_SCALE1_LATENCY1_FREQ 30000000U /*!< HCLK frequency to set FLASH latency 1 in power scale 1 */ #define FLASH_SCALE1_LATENCY2_FREQ 60000000U /*!< HCLK frequency to set FLASH latency 2 in power scale 1 */ #define FLASH_SCALE1_LATENCY3_FREQ 90000000U /*!< HCLK frequency to set FLASH latency 3 in power scale 1 */ #define FLASH_SCALE1_LATENCY4_FREQ 120000000U /*!< HCLK frequency to set FLASH latency 4 in power scale 1 */ #define FLASH_SCALE1_LATENCY5_FREQ 150000000U /*!< HCLK frequency to set FLASH latency 5 in power scale 1 */ #define FLASH_SCALE2_LATENCY1_FREQ 30000000U /*!< HCLK frequency to set FLASH latency 1 in power scale 2 */ #define FLASH_SCALE2_LATENCY2_FREQ 60000000U /*!< HCLK frequency to set FLASH latency 2 in power scale 2 */ #define FLASH_SCALE2_LATENCY3_FREQ 90000000U /*!< HCLK frequency to set FLASH latency 3 in power scale 2 */ #define FLASH_SCALE2_LATENCY4_FREQ 12000000U /*!< HCLK frequency to set FLASH latency 4 in power scale 2 */ #define FLASH_SCALE2_LATENCY5_FREQ 150000000U /*!< HCLK frequency to set FLASH latency 5 in power scale 2 */ #define FLASH_SCALE3_LATENCY1_FREQ 30000000U /*!< HCLK frequency to set FLASH latency 1 in power scale 3 */ #define FLASH_SCALE3_LATENCY2_FREQ 60000000U /*!< HCLK frequency to set FLASH latency 2 in power scale 3 */ #define FLASH_SCALE3_LATENCY3_FREQ 90000000U /*!< HCLK frequency to set FLASH latency 3 in power scale 3 */ /******************************************************************************/ /* For a painless codes migration between the STM32F4xx device product */ /* lines, the aliases defined below are put in place to overcome the */ /* differences in the interrupt handlers and IRQn definitions. */ /* No need to update developed interrupt code when moving across */ /* product lines within the same STM32F4 Family */ /******************************************************************************/ /* Aliases for __IRQn */ #define FSMC_IRQn FMC_IRQn /* Aliases for __IRQHandler */ #define FSMC_IRQHandler FMC_IRQHandler /** * @} */ /** * @} */ /** * @} */ #ifdef __cplusplus } #endif /* __cplusplus */ #endif /* __STM32F469xx_H */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/