/**+
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  ******************************************************************************+
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  * @file    stm32f4xx_hal_cec.h+
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  * @author  MCD Application Team+
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  * @brief   Header file of CEC HAL module.+
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  ******************************************************************************+
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  * @attention+
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  *+
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  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>+
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  *+
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  * Redistribution and use in source and binary forms, with or without modification,+
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  * are permitted provided that the following conditions are met:+
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  *   1. Redistributions of source code must retain the above copyright notice,+
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  *      this list of conditions and the following disclaimer.+
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  *   2. Redistributions in binary form must reproduce the above copyright notice,+
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  *      this list of conditions and the following disclaimer in the documentation+
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  *      and/or other materials provided with the distribution.+
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  *   3. Neither the name of STMicroelectronics nor the names of its contributors+
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  *      may be used to endorse or promote products derived from this software+
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  *      without specific prior written permission.+
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  *+
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  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"+
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  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE+
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  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE+
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  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE+
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  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL+
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  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR+
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  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER+
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  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,+
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  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE+
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  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.+
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  *+
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  ******************************************************************************  +
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  */+
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+
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/* Define to prevent recursive inclusion -------------------------------------*/+
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#ifndef __STM32F4xx_HAL_CEC_H+
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#define __STM32F4xx_HAL_CEC_H+
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+
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#ifdef __cplusplus+
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 extern "C" {+
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#endif+
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+
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#if defined(STM32F446xx)+
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/* Includes ------------------------------------------------------------------*/+
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#include "stm32f4xx_hal_def.h"+
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+
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/** @addtogroup STM32F4xx_HAL_Driver+
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  * @{+
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  */+
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+
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/** @addtogroup CEC+
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  * @{+
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  */+
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+
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/* Exported types ------------------------------------------------------------*/ +
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/** @defgroup CEC_Exported_Types CEC Exported Types+
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  * @{+
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  */+
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  +
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/** +
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  * @brief CEC Init Structure definition  +
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  */ +
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typedef struct+
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{+
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  uint32_t SignalFreeTime;               /*!< Set SFT field, specifies the Signal Free Time.+
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                                              It can be one of @ref CEC_Signal_Free_Time +
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                                              and belongs to the set {0,...,7} where  +
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                                              0x0 is the default configuration +
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                                              else means 0.5 + (SignalFreeTime - 1) nominal data bit periods */+
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+
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  uint32_t Tolerance;                    /*!< Set RXTOL bit, specifies the tolerance accepted on the received waveforms,+
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                                              it can be a value of @ref CEC_Tolerance : it is either CEC_STANDARD_TOLERANCE +
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                                              or CEC_EXTENDED_TOLERANCE */+
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+
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  uint32_t BRERxStop;                    /*!< Set BRESTP bit @ref CEC_BRERxStop : specifies whether or not a Bit Rising Error stops the reception. +
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                                              CEC_NO_RX_STOP_ON_BRE: reception is not stopped. +
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                                              CEC_RX_STOP_ON_BRE:    reception is stopped. */+
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+
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  uint32_t BREErrorBitGen;               /*!< Set BREGEN bit @ref CEC_BREErrorBitGen : specifies whether or not an Error-Bit is generated on the+
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                                              CEC line upon Bit Rising Error detection.+
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                                              CEC_BRE_ERRORBIT_NO_GENERATION: no error-bit generation.+
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                                              CEC_BRE_ERRORBIT_GENERATION:    error-bit generation if BRESTP is set. */+
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                                              +
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  uint32_t LBPEErrorBitGen;              /*!< Set LBPEGEN bit @ref CEC_LBPEErrorBitGen : specifies whether or not an Error-Bit is generated on the+
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                                              CEC line upon Long Bit Period Error detection.+
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                                              CEC_LBPE_ERRORBIT_NO_GENERATION:  no error-bit generation. +
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                                              CEC_LBPE_ERRORBIT_GENERATION:     error-bit generation. */  +
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                                              +
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  uint32_t BroadcastMsgNoErrorBitGen;    /*!< Set BRDNOGEN bit @ref CEC_BroadCastMsgErrorBitGen : allows to avoid an Error-Bit generation on the CEC line+
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                                              upon an error detected on a broadcast message. +
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                                              +
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                                              It supersedes BREGEN and LBPEGEN bits for a broadcast message error handling. It can take two values:+
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                                              +
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                                              1) CEC_BROADCASTERROR_ERRORBIT_GENERATION.+
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                                                 a) BRE detection: error-bit generation on the CEC line if BRESTP=CEC_RX_STOP_ON_BRE +
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                                                    and BREGEN=CEC_BRE_ERRORBIT_NO_GENERATION.+
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                                                 b) LBPE detection: error-bit generation on the CEC line +
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                                                    if LBPGEN=CEC_LBPE_ERRORBIT_NO_GENERATION.+
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                                                    +
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                                              2) CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION.+
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                                                 no error-bit generation in case neither a) nor b) are satisfied. Additionally,+
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                                                 there is no error-bit generation in case of Short Bit Period Error detection in +
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                                                 a broadcast message while LSTN bit is set. */+
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 +
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  uint32_t SignalFreeTimeOption;         /*!< Set SFTOP bit @ref CEC_SFT_Option : specifies when SFT timer starts.+
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                                              CEC_SFT_START_ON_TXSOM SFT:    timer starts when TXSOM is set by software.+
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                                              CEC_SFT_START_ON_TX_RX_END:  SFT timer starts automatically at the end of message transmission/reception. */+
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  +
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  uint32_t ListenMode;                   /*!< Set LSTN bit @ref CEC_Listening_Mode : specifies device listening mode. It can take two values:+
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  +
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                                              CEC_REDUCED_LISTENING_MODE: CEC peripheral receives only message addressed to its +
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                                                own address (OAR). Messages addressed to different destination are ignored. +
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                                                Broadcast messages are always received.+
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                                                +
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                                              CEC_FULL_LISTENING_MODE: CEC peripheral receives messages addressed to its own +
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                                                address (OAR) with positive acknowledge. Messages addressed to different destination +
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                                                are received, but without interfering with the CEC bus: no acknowledge sent.  */+
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+
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  uint16_t  OwnAddress;                 /*!< Own addresses configuration+
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                                             This parameter can be a value of @ref CEC_OWN_ADDRESS */+
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  +
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  uint8_t  *RxBuffer;                    /*!< CEC Rx buffer pointeur */+
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  +
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+
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}CEC_InitTypeDef;+
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+
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/** +
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  * @brief HAL CEC State structures definition +
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  * @note  HAL CEC State value is a combination of 2 different substates: gState and RxState.+
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  *        - gState contains CEC state information related to global Handle management +
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  *          and also information related to Tx operations.+
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  *          gState value coding follow below described bitmap :+
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  *          b7 (not used)+
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  *             x  : Should be set to 0+
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  *          b6  Error information +
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  *             0  : No Error+
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  *             1  : Error+
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  *          b5     IP initilisation status+
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  *             0  : Reset (IP not initialized)+
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  *             1  : Init done (IP initialized. HAL CEC Init function already called)+
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  *          b4-b3  (not used)+
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  *             xx : Should be set to 00+
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  *          b2     Intrinsic process state+
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  *             0  : Ready+
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  *             1  : Busy (IP busy with some configuration or internal operations)+
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  *          b1     (not used)+
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  *             x  : Should be set to 0+
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  *          b0     Tx state+
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  *             0  : Ready (no Tx operation ongoing)+
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  *             1  : Busy (Tx operation ongoing)+
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  *        - RxState contains information related to Rx operations.+
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  *          RxState value coding follow below described bitmap :+
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  *          b7-b6  (not used)+
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  *             xx : Should be set to 00+
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  *          b5     IP initilisation status+
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  *             0  : Reset (IP not initialized)+
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  *             1  : Init done (IP initialized)+
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  *          b4-b2  (not used)+
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  *            xxx : Should be set to 000+
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  *          b1     Rx state+
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  *             0  : Ready (no Rx operation ongoing)+
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  *             1  : Busy (Rx operation ongoing)+
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  *          b0     (not used)+
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  *             x  : Should be set to 0.  +
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  */ +
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typedef enum+
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{+
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  HAL_CEC_STATE_RESET             = 0x00U,    /*!< Peripheral is not yet Initialized +
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                                                   Value is allowed for gState and RxState             */+
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  HAL_CEC_STATE_READY             = 0x20U,    /*!< Peripheral Initialized and ready for use+
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                                                   Value is allowed for gState and RxState             */+
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  HAL_CEC_STATE_BUSY              = 0x24U,    /*!< an internal process is ongoing+
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                                                   Value is allowed for gState only                    */+
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  HAL_CEC_STATE_BUSY_RX           = 0x22U,    /*!< Data Reception process is ongoing+
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                                                   Value is allowed for RxState only                   */+
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  HAL_CEC_STATE_BUSY_TX           = 0x21U,    /*!< Data Transmission process is ongoing +
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                                                   Value is allowed for gState only                    */+
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  HAL_CEC_STATE_ERROR             = 0x60U     /*!< Error Value is allowed for gState only              */+
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}HAL_CEC_StateTypeDef;+
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+
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/** +
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  * @brief  CEC handle Structure definition  +
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  */  +
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typedef struct+
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{+
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  CEC_TypeDef             *Instance;      /*!< CEC registers base address */+
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  +
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  CEC_InitTypeDef         Init;           /*!< CEC communication parameters */+
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  +
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  uint8_t                 *pTxBuffPtr;    /*!< Pointer to CEC Tx transfer Buffer */+
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  +
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  uint16_t                TxXferCount;    /*!< CEC Tx Transfer Counter */+
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  +
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  uint16_t                RxXferSize;     /*!< CEC Rx Transfer size, 0: header received only */+
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  +
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  HAL_LockTypeDef         Lock;           /*!< Locking object */+
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+
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  HAL_CEC_StateTypeDef    gState;         /*!< CEC state information related to global Handle management +
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                                               and also related to Tx operations.+
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                                               This parameter can be a value of @ref HAL_CEC_StateTypeDef */+
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  +
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  HAL_CEC_StateTypeDef    RxState;        /*!< CEC state information related to Rx operations.+
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                                               This parameter can be a value of @ref HAL_CEC_StateTypeDef */+
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  +
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  uint32_t                ErrorCode;      /*!< For errors handling purposes, copy of ISR register +
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                                               in case error is reported */    +
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}CEC_HandleTypeDef;+
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/**+
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  * @}+
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  */+
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+
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/* Exported constants --------------------------------------------------------*/+
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/** @defgroup CEC_Exported_Constants CEC Exported Constants+
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  * @{+
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  */+
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+
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/** @defgroup CEC_Error_Code CEC Error Code+
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  * @{+
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  */ +
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#define HAL_CEC_ERROR_NONE    0x00000000U            /*!< no error                      */+
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#define HAL_CEC_ERROR_RXOVR   CEC_ISR_RXOVR          /*!< CEC Rx-Overrun                */+
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#define HAL_CEC_ERROR_BRE     CEC_ISR_BRE            /*!< CEC Rx Bit Rising Error       */+
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#define HAL_CEC_ERROR_SBPE    CEC_ISR_SBPE           /*!< CEC Rx Short Bit period Error */+
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#define HAL_CEC_ERROR_LBPE    CEC_ISR_LBPE           /*!< CEC Rx Long Bit period Error  */+
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#define HAL_CEC_ERROR_RXACKE  CEC_ISR_RXACKE         /*!< CEC Rx Missing Acknowledge    */+
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#define HAL_CEC_ERROR_ARBLST  CEC_ISR_ARBLST         /*!< CEC Arbitration Lost          */+
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#define HAL_CEC_ERROR_TXUDR   CEC_ISR_TXUDR          /*!< CEC Tx-Buffer Underrun        */+
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#define HAL_CEC_ERROR_TXERR   CEC_ISR_TXERR          /*!< CEC Tx-Error                  */+
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#define HAL_CEC_ERROR_TXACKE  CEC_ISR_TXACKE         /*!< CEC Tx Missing Acknowledge    */+
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/**+
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  * @}+
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  */+
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       +
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/** @defgroup CEC_Signal_Free_Time  CEC Signal Free Time setting parameter+
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  * @{+
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  */+
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#define CEC_DEFAULT_SFT                    0x00000000U+
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#define CEC_0_5_BITPERIOD_SFT              0x00000001U+
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#define CEC_1_5_BITPERIOD_SFT              0x00000002U+
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#define CEC_2_5_BITPERIOD_SFT              0x00000003U+
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#define CEC_3_5_BITPERIOD_SFT              0x00000004U+
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#define CEC_4_5_BITPERIOD_SFT              0x00000005U+
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#define CEC_5_5_BITPERIOD_SFT              0x00000006U+
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#define CEC_6_5_BITPERIOD_SFT              0x00000007U+
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/**+
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  * @}+
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  */+
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+
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/** @defgroup CEC_Tolerance CEC Receiver Tolerance+
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  * @{+
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  */+
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#define CEC_STANDARD_TOLERANCE             0x00000000U+
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#define CEC_EXTENDED_TOLERANCE             ((uint32_t)CEC_CFGR_RXTOL)+
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/**+
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  * @}+
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  */ +
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+
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/** @defgroup CEC_BRERxStop CEC Reception Stop on Error+
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  * @{+
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  */+
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#define CEC_NO_RX_STOP_ON_BRE             0x00000000U+
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#define CEC_RX_STOP_ON_BRE                ((uint32_t)CEC_CFGR_BRESTP)+
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/**+
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  * @}+
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  */            +
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             +
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/** @defgroup CEC_BREErrorBitGen  CEC Error Bit Generation if Bit Rise Error reported+
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  * @{+
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  */ +
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#define CEC_BRE_ERRORBIT_NO_GENERATION     0x00000000U+
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#define CEC_BRE_ERRORBIT_GENERATION        ((uint32_t)CEC_CFGR_BREGEN)+
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/**+
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  * @}+
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  */ +
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                        +
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/** @defgroup CEC_LBPEErrorBitGen  CEC Error Bit Generation if Long Bit Period Error reported+
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  * @{+
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  */ +
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#define CEC_LBPE_ERRORBIT_NO_GENERATION     0x00000000U+
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#define CEC_LBPE_ERRORBIT_GENERATION        ((uint32_t)CEC_CFGR_LBPEGEN)+
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/**+
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  * @}+
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  */    +
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+
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/** @defgroup CEC_BroadCastMsgErrorBitGen  CEC Error Bit Generation on Broadcast message+
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  * @{+
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  */ +
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#define CEC_BROADCASTERROR_ERRORBIT_GENERATION     0x00000000U+
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#define CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION  ((uint32_t)CEC_CFGR_BRDNOGEN)+
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/**+
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  * @}+
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  */+
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  +
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/** @defgroup CEC_SFT_Option     CEC Signal Free Time start option+
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  * @{+
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  */ +
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#define CEC_SFT_START_ON_TXSOM           0x00000000U+
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#define CEC_SFT_START_ON_TX_RX_END       ((uint32_t)CEC_CFGR_SFTOPT)+
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/**+
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  * @}+
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  */+
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  +
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/** @defgroup CEC_Listening_Mode    CEC Listening mode option+
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  * @{+
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  */ +
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#define CEC_REDUCED_LISTENING_MODE          0x00000000U+
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#define CEC_FULL_LISTENING_MODE             ((uint32_t)CEC_CFGR_LSTN)+
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/**+
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  * @}+
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  */+
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  +
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/** @defgroup CEC_OAR_Position   CEC Device Own Address position in CEC CFGR register     +
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  * @{+
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  */+
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#define CEC_CFGR_OAR_LSB_POS            16U+
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/**+
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  * @}+
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  */+
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  +
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/** @defgroup CEC_Initiator_Position   CEC Initiator logical address position in message header     +
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  * @{+
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  */+
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#define CEC_INITIATOR_LSB_POS           4U+
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/**+
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  * @}+
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  */+
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+
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/** @defgroup CEC_OWN_ADDRESS   CEC Own Address    +
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  * @{+
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  */+
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#define CEC_OWN_ADDRESS_NONE           ((uint16_t)0x0000)   /* Reset value */+
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#define CEC_OWN_ADDRESS_0              ((uint16_t)0x0001)   /* Logical Address 0 */+
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#define CEC_OWN_ADDRESS_1              ((uint16_t)0x0002)   /* Logical Address 1 */+
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#define CEC_OWN_ADDRESS_2              ((uint16_t)0x0004)   /* Logical Address 2 */+
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#define CEC_OWN_ADDRESS_3              ((uint16_t)0x0008)   /* Logical Address 3 */+
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#define CEC_OWN_ADDRESS_4              ((uint16_t)0x0010)   /* Logical Address 4 */+
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#define CEC_OWN_ADDRESS_5              ((uint16_t)0x0020)   /* Logical Address 5 */+
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#define CEC_OWN_ADDRESS_6              ((uint16_t)0x0040)   /* Logical Address 6 */+
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#define CEC_OWN_ADDRESS_7              ((uint16_t)0x0080)   /* Logical Address 7 */+
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#define CEC_OWN_ADDRESS_8              ((uint16_t)0x0100)   /* Logical Address 9 */+
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#define CEC_OWN_ADDRESS_9              ((uint16_t)0x0200)   /* Logical Address 10 */+
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#define CEC_OWN_ADDRESS_10             ((uint16_t)0x0400)   /* Logical Address 11 */+
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#define CEC_OWN_ADDRESS_11             ((uint16_t)0x0800)   /* Logical Address 12 */+
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#define CEC_OWN_ADDRESS_12             ((uint16_t)0x1000)   /* Logical Address 13 */+
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#define CEC_OWN_ADDRESS_13             ((uint16_t)0x2000)   /* Logical Address 14 */+
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#define CEC_OWN_ADDRESS_14             ((uint16_t)0x4000)   /* Logical Address 15 */+
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/**+
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  * @}+
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  */+
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    +
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/** @defgroup CEC_Interrupts_Definitions  CEC Interrupts definition+
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  * @{+
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  */+
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#define CEC_IT_TXACKE                   CEC_IER_TXACKEIE+
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#define CEC_IT_TXERR                    CEC_IER_TXERRIE+
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#define CEC_IT_TXUDR                    CEC_IER_TXUDRIE+
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#define CEC_IT_TXEND                    CEC_IER_TXENDIE+
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#define CEC_IT_TXBR                     CEC_IER_TXBRIE+
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#define CEC_IT_ARBLST                   CEC_IER_ARBLSTIE+
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#define CEC_IT_RXACKE                   CEC_IER_RXACKEIE+
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#define CEC_IT_LBPE                     CEC_IER_LBPEIE+
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#define CEC_IT_SBPE                     CEC_IER_SBPEIE+
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#define CEC_IT_BRE                      CEC_IER_BREIE+
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#define CEC_IT_RXOVR                    CEC_IER_RXOVRIE+
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#define CEC_IT_RXEND                    CEC_IER_RXENDIE+
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#define CEC_IT_RXBR                     CEC_IER_RXBRIE+
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/**+
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  * @}+
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  */+
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+
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/** @defgroup CEC_Flags_Definitions  CEC Flags definition+
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  * @{+
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  */+
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#define CEC_FLAG_TXACKE                 CEC_ISR_TXACKE+
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#define CEC_FLAG_TXERR                  CEC_ISR_TXERR+
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#define CEC_FLAG_TXUDR                  CEC_ISR_TXUDR+
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#define CEC_FLAG_TXEND                  CEC_ISR_TXEND+
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#define CEC_FLAG_TXBR                   CEC_ISR_TXBR+
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#define CEC_FLAG_ARBLST                 CEC_ISR_ARBLST+
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#define CEC_FLAG_RXACKE                 CEC_ISR_RXACKE+
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#define CEC_FLAG_LBPE                   CEC_ISR_LBPE+
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#define CEC_FLAG_SBPE                   CEC_ISR_SBPE+
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#define CEC_FLAG_BRE                    CEC_ISR_BRE+
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#define CEC_FLAG_RXOVR                  CEC_ISR_RXOVR+
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#define CEC_FLAG_RXEND                  CEC_ISR_RXEND+
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#define CEC_FLAG_RXBR                   CEC_ISR_RXBR+
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/**+
−
  * @}+
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  */+
−
  +
−
/** @defgroup CEC_ALL_ERROR CEC all RX or TX errors flags +
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  * @{+
−
  */+
−
#define CEC_ISR_ALL_ERROR              ((uint32_t)CEC_ISR_RXOVR|CEC_ISR_BRE|CEC_ISR_SBPE|CEC_ISR_LBPE|CEC_ISR_RXACKE|\+
−
                                                  CEC_ISR_ARBLST|CEC_ISR_TXUDR|CEC_ISR_TXERR|CEC_ISR_TXACKE)+
−
/**+
−
  * @}+
−
  */+
−
+
−
/** @defgroup CEC_IER_ALL_RX CEC all RX errors interrupts enabling flag +
−
  * @{+
−
  */+
−
#define CEC_IER_RX_ALL_ERR              ((uint32_t)CEC_IER_RXACKEIE|CEC_IER_LBPEIE|CEC_IER_SBPEIE|CEC_IER_BREIE|CEC_IER_RXOVRIE)+
−
/**+
−
  * @}+
−
  */+
−
  +
−
/** @defgroup CEC_IER_ALL_TX CEC all TX errors interrupts enabling flag +
−
  * @{+
−
  */+
−
#define CEC_IER_TX_ALL_ERR              ((uint32_t)CEC_IER_TXACKEIE|CEC_IER_TXERRIE|CEC_IER_TXUDRIE|CEC_IER_ARBLSTIE)+
−
/**+
−
  * @}+
−
  */+
−
  +
−
/**+
−
  * @}+
−
  */  +
−
  +
−
/* Exported macros -----------------------------------------------------------*/+
−
/** @defgroup CEC_Exported_Macros CEC Exported Macros+
−
  * @{+
−
  */+
−
+
−
/** @brief  Reset CEC handle gstate & RxState+
−
  * @param  __HANDLE__ CEC handle.+
−
  * @retval None+
−
  */+
−
#define __HAL_CEC_RESET_HANDLE_STATE(__HANDLE__) do{                                                   \+
−
                                                       (__HANDLE__)->gState = HAL_CEC_STATE_RESET;     \+
−
                                                       (__HANDLE__)->RxState = HAL_CEC_STATE_RESET;    \+
−
                                                     } while(0)+
−
+
−
/** @brief  Checks whether or not the specified CEC interrupt flag is set.+
−
  * @param  __HANDLE__ specifies the CEC Handle.+
−
  * @param  __FLAG__ specifies the flag to check.+
−
  *            @arg CEC_FLAG_TXACKE: Tx Missing acknowledge Error+
−
  *            @arg CEC_FLAG_TXERR: Tx Error.+
−
  *            @arg CEC_FLAG_TXUDR: Tx-Buffer Underrun.+
−
  *            @arg CEC_FLAG_TXEND: End of transmission (successful transmission of the last byte).+
−
  *            @arg CEC_FLAG_TXBR: Tx-Byte Request.+
−
  *            @arg CEC_FLAG_ARBLST: Arbitration Lost+
−
  *            @arg CEC_FLAG_RXACKE: Rx-Missing Acknowledge +
−
  *            @arg CEC_FLAG_LBPE: Rx Long period Error+
−
  *            @arg CEC_FLAG_SBPE: Rx Short period Error+
−
  *            @arg CEC_FLAG_BRE: Rx Bit Rising Error+
−
  *            @arg CEC_FLAG_RXOVR: Rx Overrun.+
−
  *            @arg CEC_FLAG_RXEND: End Of Reception.+
−
  *            @arg CEC_FLAG_RXBR: Rx-Byte Received.      +
−
  * @retval ITStatus+
−
  */+
−
#define __HAL_CEC_GET_FLAG(__HANDLE__, __FLAG__)        ((__HANDLE__)->Instance->ISR & (__FLAG__)) +
−
+
−
/** @brief  Clears the interrupt or status flag when raised (write at 1)+
−
  * @param  __HANDLE__ specifies the CEC Handle.+
−
  * @param  __FLAG__ specifies the interrupt/status flag to clear.+
−
  *        This parameter can be one of the following values:+
−
  *            @arg CEC_FLAG_TXACKE: Tx Missing acknowledge Error+
−
  *            @arg CEC_FLAG_TXERR: Tx Error.+
−
  *            @arg CEC_FLAG_TXUDR: Tx-Buffer Underrun.+
−
  *            @arg CEC_FLAG_TXEND: End of transmission (successful transmission of the last byte).+
−
  *            @arg CEC_FLAG_TXBR: Tx-Byte Request.+
−
  *            @arg CEC_FLAG_ARBLST: Arbitration Lost+
−
  *            @arg CEC_FLAG_RXACKE: Rx-Missing Acknowledge +
−
  *            @arg CEC_FLAG_LBPE: Rx Long period Error+
−
  *            @arg CEC_FLAG_SBPE: Rx Short period Error+
−
  *            @arg CEC_FLAG_BRE: Rx Bit Rising Error+
−
  *            @arg CEC_FLAG_RXOVR: Rx Overrun.+
−
  *            @arg CEC_FLAG_RXEND: End Of Reception.+
−
  *            @arg CEC_FLAG_RXBR: Rx-Byte Received. +
−
  * @retval none  +
−
  */+
−
#define __HAL_CEC_CLEAR_FLAG(__HANDLE__, __FLAG__)         ((__HANDLE__)->Instance->ISR |= (__FLAG__)) +
−
+
−
/** @brief  Enables the specified CEC interrupt.+
−
  * @param  __HANDLE__ specifies the CEC Handle.+
−
  * @param  __INTERRUPT__ specifies the CEC interrupt to enable.+
−
  *          This parameter can be one of the following values:+
−
  *            @arg CEC_IT_TXACKE: Tx Missing acknowledge Error IT Enable +
−
  *            @arg CEC_IT_TXERR: Tx Error IT Enable +
−
  *            @arg CEC_IT_TXUDR: Tx-Buffer Underrun IT Enable +
−
  *            @arg CEC_IT_TXEND: End of transmission IT Enable +
−
  *            @arg CEC_IT_TXBR: Tx-Byte Request IT Enable +
−
  *            @arg CEC_IT_ARBLST: Arbitration Lost IT Enable +
−
  *            @arg CEC_IT_RXACKE: Rx-Missing Acknowledge IT Enable +
−
  *            @arg CEC_IT_LBPE: Rx Long period Error IT Enable +
−
  *            @arg CEC_IT_SBPE: Rx Short period Error IT Enable +
−
  *            @arg CEC_IT_BRE: Rx Bit Rising Error IT Enable +
−
  *            @arg CEC_IT_RXOVR: Rx Overrun IT Enable +
−
  *            @arg CEC_IT_RXEND: End Of Reception IT Enable +
−
  *            @arg CEC_IT_RXBR: Rx-Byte Received IT Enable                          +
−
  * @retval none+
−
  */+
−
#define __HAL_CEC_ENABLE_IT(__HANDLE__, __INTERRUPT__)     ((__HANDLE__)->Instance->IER |= (__INTERRUPT__))  +
−
+
−
/** @brief  Disables the specified CEC interrupt.+
−
  * @param  __HANDLE__ specifies the CEC Handle.+
−
  * @param  __INTERRUPT__ specifies the CEC interrupt to disable.+
−
  *          This parameter can be one of the following values:+
−
  *            @arg CEC_IT_TXACKE: Tx Missing acknowledge Error IT Enable +
−
  *            @arg CEC_IT_TXERR: Tx Error IT Enable +
−
  *            @arg CEC_IT_TXUDR: Tx-Buffer Underrun IT Enable +
−
  *            @arg CEC_IT_TXEND: End of transmission IT Enable +
−
  *            @arg CEC_IT_TXBR: Tx-Byte Request IT Enable +
−
  *            @arg CEC_IT_ARBLST: Arbitration Lost IT Enable +
−
  *            @arg CEC_IT_RXACKE: Rx-Missing Acknowledge IT Enable +
−
  *            @arg CEC_IT_LBPE: Rx Long period Error IT Enable +
−
  *            @arg CEC_IT_SBPE: Rx Short period Error IT Enable +
−
  *            @arg CEC_IT_BRE: Rx Bit Rising Error IT Enable +
−
  *            @arg CEC_IT_RXOVR: Rx Overrun IT Enable +
−
  *            @arg CEC_IT_RXEND: End Of Reception IT Enable +
−
  *            @arg CEC_IT_RXBR: Rx-Byte Received IT Enable                   +
−
  * @retval none+
−
  */   +
−
#define __HAL_CEC_DISABLE_IT(__HANDLE__, __INTERRUPT__)    ((__HANDLE__)->Instance->IER &= (~(__INTERRUPT__)))  +
−
+
−
/** @brief  Checks whether or not the specified CEC interrupt is enabled.+
−
  * @param  __HANDLE__ specifies the CEC Handle.+
−
  * @param  __INTERRUPT__ specifies the CEC interrupt to check.+
−
  *          This parameter can be one of the following values:+
−
  *            @arg CEC_IT_TXACKE: Tx Missing acknowledge Error IT Enable +
−
  *            @arg CEC_IT_TXERR: Tx Error IT Enable +
−
  *            @arg CEC_IT_TXUDR: Tx-Buffer Underrun IT Enable +
−
  *            @arg CEC_IT_TXEND: End of transmission IT Enable +
−
  *            @arg CEC_IT_TXBR: Tx-Byte Request IT Enable +
−
  *            @arg CEC_IT_ARBLST: Arbitration Lost IT Enable +
−
  *            @arg CEC_IT_RXACKE: Rx-Missing Acknowledge IT Enable +
−
  *            @arg CEC_IT_LBPE: Rx Long period Error IT Enable +
−
  *            @arg CEC_IT_SBPE: Rx Short period Error IT Enable +
−
  *            @arg CEC_IT_BRE: Rx Bit Rising Error IT Enable +
−
  *            @arg CEC_IT_RXOVR: Rx Overrun IT Enable +
−
  *            @arg CEC_IT_RXEND: End Of Reception IT Enable +
−
  *            @arg CEC_IT_RXBR: Rx-Byte Received IT Enable                  +
−
  * @retval FlagStatus  +
−
  */+
−
#define __HAL_CEC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER & (__INTERRUPT__))+
−
+
−
/** @brief  Enables the CEC device+
−
  * @param  __HANDLE__ specifies the CEC Handle.               +
−
  * @retval none +
−
  */+
−
#define __HAL_CEC_ENABLE(__HANDLE__)                   ((__HANDLE__)->Instance->CR |=  CEC_CR_CECEN)+
−
+
−
/** @brief  Disables the CEC device+
−
  * @param  __HANDLE__ specifies the CEC Handle.               +
−
  * @retval none +
−
  */+
−
#define __HAL_CEC_DISABLE(__HANDLE__)                  ((__HANDLE__)->Instance->CR &=  ~CEC_CR_CECEN)+
−
+
−
/** @brief  Set Transmission Start flag+
−
  * @param  __HANDLE__ specifies the CEC Handle.               +
−
  * @retval none +
−
  */+
−
#define __HAL_CEC_FIRST_BYTE_TX_SET(__HANDLE__)        ((__HANDLE__)->Instance->CR |=  CEC_CR_TXSOM)+
−
+
−
/** @brief  Set Transmission End flag+
−
  * @param  __HANDLE__ specifies the CEC Handle.               +
−
  * @retval none +
−
  * If the CEC message consists of only one byte, TXEOM must be set before of TXSOM.  +
−
  */+
−
#define __HAL_CEC_LAST_BYTE_TX_SET(__HANDLE__)         ((__HANDLE__)->Instance->CR |=  CEC_CR_TXEOM)+
−
+
−
/** @brief  Get Transmission Start flag+
−
  * @param  __HANDLE__ specifies the CEC Handle.               +
−
  * @retval FlagStatus +
−
  */+
−
#define __HAL_CEC_GET_TRANSMISSION_START_FLAG(__HANDLE__) ((__HANDLE__)->Instance->CR & CEC_CR_TXSOM)+
−
+
−
/** @brief  Get Transmission End flag+
−
  * @param  __HANDLE__ specifies the CEC Handle.               +
−
  * @retval FlagStatus +
−
  */+
−
#define __HAL_CEC_GET_TRANSMISSION_END_FLAG(__HANDLE__)   ((__HANDLE__)->Instance->CR & CEC_CR_TXEOM)   +
−
+
−
/** @brief  Clear OAR register+
−
  * @param  __HANDLE__ specifies the CEC Handle.               +
−
  * @retval none +
−
  */+
−
#define __HAL_CEC_CLEAR_OAR(__HANDLE__)   CLEAR_BIT((__HANDLE__)->Instance->CFGR, CEC_CFGR_OAR)+
−
+
−
/** @brief  Set OAR register (without resetting previously set address in case of multi-address mode)+
−
  *          To reset OAR, __HAL_CEC_CLEAR_OAR() needs to be called beforehand+
−
  * @param  __HANDLE__ specifies the CEC Handle. +
−
  * @param  __ADDRESS__ Own Address value (CEC logical address is identified by bit position)                   +
−
  * @retval none +
−
  */+
−
#define __HAL_CEC_SET_OAR(__HANDLE__,__ADDRESS__)   SET_BIT((__HANDLE__)->Instance->CFGR, (__ADDRESS__)<< CEC_CFGR_OAR_LSB_POS)+
−
+
−
/**+
−
  * @}+
−
  */                       +
−
+
−
/* Exported functions --------------------------------------------------------*/+
−
/** @addtogroup CEC_Exported_Functions+
−
  * @{+
−
  */+
−
+
−
/** @addtogroup CEC_Exported_Functions_Group1+
−
  * @{+
−
  */+
−
/* Initialization and de-initialization functions  ****************************/+
−
HAL_StatusTypeDef HAL_CEC_Init(CEC_HandleTypeDef *hcec);+
−
HAL_StatusTypeDef HAL_CEC_DeInit(CEC_HandleTypeDef *hcec);+
−
HAL_StatusTypeDef HAL_CEC_SetDeviceAddress(CEC_HandleTypeDef *hcec, uint16_t CEC_OwnAddress);+
−
void HAL_CEC_MspInit(CEC_HandleTypeDef *hcec);+
−
void HAL_CEC_MspDeInit(CEC_HandleTypeDef *hcec);+
−
/**+
−
  * @}+
−
  */+
−
+
−
/** @addtogroup CEC_Exported_Functions_Group2+
−
  * @{+
−
  */+
−
/* I/O operation functions  ***************************************************/+
−
HAL_StatusTypeDef HAL_CEC_Transmit_IT(CEC_HandleTypeDef *hcec, uint8_t InitiatorAddress,uint8_t DestinationAddress, uint8_t *pData, uint32_t Size);+
−
uint32_t HAL_CEC_GetLastReceivedFrameSize(CEC_HandleTypeDef *hcec);+
−
void HAL_CEC_ChangeRxBuffer(CEC_HandleTypeDef *hcec, uint8_t* Rxbuffer);+
−
void HAL_CEC_IRQHandler(CEC_HandleTypeDef *hcec);+
−
void HAL_CEC_TxCpltCallback(CEC_HandleTypeDef *hcec);+
−
void HAL_CEC_RxCpltCallback(CEC_HandleTypeDef *hcec, uint32_t RxFrameSize);+
−
void HAL_CEC_ErrorCallback(CEC_HandleTypeDef *hcec);+
−
/**+
−
  * @}+
−
  */+
−
+
−
/** @addtogroup CEC_Exported_Functions_Group3+
−
  * @{+
−
  */+
−
/* Peripheral State functions  ************************************************/+
−
HAL_CEC_StateTypeDef HAL_CEC_GetState(CEC_HandleTypeDef *hcec);+
−
uint32_t HAL_CEC_GetError(CEC_HandleTypeDef *hcec);+
−
/**+
−
  * @}+
−
  */+
−
+
−
/**+
−
  * @}+
−
  */+
−
  +
−
/* Private types -------------------------------------------------------------*/+
−
/** @defgroup CEC_Private_Types CEC Private Types+
−
  * @{+
−
  */+
−
+
−
/**+
−
  * @}+
−
  */ +
−
+
−
/* Private variables ---------------------------------------------------------*/+
−
/** @defgroup CEC_Private_Variables CEC Private Variables+
−
  * @{+
−
  */+
−
  +
−
/**+
−
  * @}+
−
  */ +
−
+
−
/* Private constants ---------------------------------------------------------*/+
−
/** @defgroup CEC_Private_Constants CEC Private Constants+
−
  * @{+
−
  */+
−
+
−
/**+
−
  * @}+
−
  */ +
−
+
−
/* Private macros ------------------------------------------------------------*/+
−
/** @defgroup CEC_Private_Macros CEC Private Macros+
−
  * @{+
−
  */+
−
  +
−
#define IS_CEC_SIGNALFREETIME(__SFT__)     ((__SFT__) <= CEC_CFGR_SFT)  +
−
+
−
#define IS_CEC_TOLERANCE(__RXTOL__)        (((__RXTOL__) == CEC_STANDARD_TOLERANCE) || \+
−
                                            ((__RXTOL__) == CEC_EXTENDED_TOLERANCE))+
−
+
−
#define IS_CEC_BRERXSTOP(__BRERXSTOP__)   (((__BRERXSTOP__) == CEC_NO_RX_STOP_ON_BRE) || \+
−
                                           ((__BRERXSTOP__) == CEC_RX_STOP_ON_BRE))+
−
+
−
#define IS_CEC_BREERRORBITGEN(__ERRORBITGEN__) (((__ERRORBITGEN__) == CEC_BRE_ERRORBIT_NO_GENERATION) || \+
−
                                                ((__ERRORBITGEN__) == CEC_BRE_ERRORBIT_GENERATION))+
−
+
−
#define IS_CEC_LBPEERRORBITGEN(__ERRORBITGEN__) (((__ERRORBITGEN__) == CEC_LBPE_ERRORBIT_NO_GENERATION) || \+
−
                                                 ((__ERRORBITGEN__) == CEC_LBPE_ERRORBIT_GENERATION))+
−
+
−
#define IS_CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION(__ERRORBITGEN__) (((__ERRORBITGEN__) == CEC_BROADCASTERROR_ERRORBIT_GENERATION) || \+
−
                                                                       ((__ERRORBITGEN__) == CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION))+
−
+
−
#define IS_CEC_SFTOP(__SFTOP__)          (((__SFTOP__) == CEC_SFT_START_ON_TXSOM) || \+
−
                                          ((__SFTOP__) == CEC_SFT_START_ON_TX_RX_END))+
−
+
−
#define IS_CEC_LISTENING_MODE(__MODE__)     (((__MODE__) == CEC_REDUCED_LISTENING_MODE) || \+
−
                                             ((__MODE__) == CEC_FULL_LISTENING_MODE))+
−
+
−
/** @brief Check CEC message size.+
−
  *       The message size is the payload size: without counting the header, +
−
  *       it varies from 0 byte (ping operation, one header only, no payload) to +
−
  *       15 bytes (1 opcode and up to 14 operands following the header). +
−
  * @param  __SIZE__ CEC message size.               +
−
  * @retval Test result (TRUE or FALSE).+
−
  */+
−
#define IS_CEC_MSGSIZE(__SIZE__) ((__SIZE__) <= 0x10U)  +
−
                                                 +
−
/** @brief Check CEC device Own Address Register (OAR) setting.+
−
  *        OAR address is written in a 15-bit field within CEC_CFGR register. +
−
  * @param  __ADDRESS__ CEC own address.               +
−
  * @retval Test result (TRUE or FALSE).+
−
  */+
−
#define IS_CEC_OWN_ADDRESS(__ADDRESS__) ((__ADDRESS__) <= 0x7FFFU)+
−
+
−
/** @brief Check CEC initiator or destination logical address setting.+
−
  *        Initiator and destination addresses are coded over 4 bits. +
−
  * @param  __ADDRESS__ CEC initiator or logical address.               +
−
  * @retval Test result (TRUE or FALSE).+
−
  */+
−
#define IS_CEC_ADDRESS(__ADDRESS__) ((__ADDRESS__) <= 0x0FU) +
−
/**+
−
  * @}+
−
  */+
−
/* Private functions ---------------------------------------------------------*/+
−
/** @defgroup CEC_Private_Functions CEC Private Functions+
−
  * @{+
−
  */+
−
  +
−
/**+
−
  * @}+
−
  */+
−
  +
−
/**+
−
  * @}+
−
  */ +
−
+
−
/**+
−
  * @}+
−
  */ +
−
#endif /* STM32F446xx */+
−
  +
−
#ifdef __cplusplus+
−
}+
−
#endif+
−
+
−
#endif /* __STM32F4xx_HAL_CEC_H */+
−
+
−
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/+
−