Mercurial > public > ostc4
diff Common/Drivers/CMSIS/CMSIS_END_USER_LICENCE_AGREEMENT.rtf @ 128:c78bcbd5deda FlipDisplay
Added current STM32 standandard libraries in version independend folder structure
| author | Ideenmodellierer |
|---|---|
| date | Sun, 17 Feb 2019 21:12:22 +0100 |
| parents | |
| children |
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--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/Common/Drivers/CMSIS/CMSIS_END_USER_LICENCE_AGREEMENT.rtf Sun Feb 17 21:12:22 2019 +0100 @@ -0,0 +1,911 @@ +{\rtf1\adeflang1025\ansi\ansicpg1252\uc1\adeff0\deff0\stshfdbch37\stshfloch37\stshfhich37\stshfbi0\deflang2057\deflangfe2057\themelang2057\themelangfe0\themelangcs0{\fonttbl{\f0\fbidi \froman\fcharset0\fprq2{\*\panose 02020603050405020304}Times New Roman;}{\f1\fbidi \fswiss\fcharset0\fprq2{\*\panose 020b0604020202020204}Arial;} +{\f2\fbidi \fmodern\fcharset0\fprq1{\*\panose 02070309020205020404}Courier New;}{\f3\fbidi \froman\fcharset2\fprq2{\*\panose 05050102010706020507}Symbol;}{\f10\fbidi \fnil\fcharset2\fprq2{\*\panose 05000000000000000000}Wingdings;} +{\f14\fbidi \froman\fcharset136\fprq2{\*\panose 02020500000000000000}PMingLiU{\*\falt \'b7\'73\'b2\'d3\'a9\'fa\'c5\'e9};}{\f34\fbidi \froman\fcharset0\fprq2{\*\panose 02040503050406030204}Cambria Math;} +{\f37\fbidi \fswiss\fcharset0\fprq2{\*\panose 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?;}{\levelnumbers;} +\f3\fs20\fbias0 \fi-360\li720\jclisttab\tx720\lin720 }{\listlevel\levelnfc23\levelnfcn23\leveljc0\leveljcn0\levelfollow0\levelstartat1\lvltentative\levelspace0\levelindent0{\leveltext\'01o;}{\levelnumbers;}\f2\fs20\fbias0 \levelpicture0\fi-360\li1440 +\jclisttab\tx1440\lin1440 }{\listlevel\levelnfc23\levelnfcn23\leveljc0\leveljcn0\levelfollow0\levelstartat1\lvltentative\levelspace0\levelindent0{\leveltext\'01\u-3929 ?;}{\levelnumbers;}\f10\fs20\fbias0 \fi-360\li2160\jclisttab\tx2160\lin2160 } +{\listlevel\levelnfc23\levelnfcn23\leveljc0\leveljcn0\levelfollow0\levelstartat1\lvltentative\levelspace0\levelindent0{\leveltext\'01\u-3929 ?;}{\levelnumbers;}\f10\fs20\fbias0 \fi-360\li2880\jclisttab\tx2880\lin2880 }{\listlevel\levelnfc23\levelnfcn23 +\leveljc0\leveljcn0\levelfollow0\levelstartat1\lvltentative\levelspace0\levelindent0{\leveltext\'01\u-3929 ?;}{\levelnumbers;}\f10\fs20\fbias0 \fi-360\li3600\jclisttab\tx3600\lin3600 }{\listlevel\levelnfc23\levelnfcn23\leveljc0\leveljcn0\levelfollow0 +\levelstartat1\lvltentative\levelspace0\levelindent0{\leveltext\'01\u-3929 ?;}{\levelnumbers;}\f10\fs20\fbias0 \fi-360\li4320\jclisttab\tx4320\lin4320 }{\listlevel\levelnfc23\levelnfcn23\leveljc0\leveljcn0\levelfollow0\levelstartat1\lvltentative +\levelspace0\levelindent0{\leveltext\'01\u-3929 ?;}{\levelnumbers;}\f10\fs20\fbias0 \fi-360\li5040\jclisttab\tx5040\lin5040 }{\listlevel\levelnfc23\levelnfcn23\leveljc0\leveljcn0\levelfollow0\levelstartat1\lvltentative\levelspace0\levelindent0{\leveltext +\'01\u-3929 ?;}{\levelnumbers;}\f10\fs20\fbias0 \fi-360\li5760\jclisttab\tx5760\lin5760 }{\listlevel\levelnfc23\levelnfcn23\leveljc0\leveljcn0\levelfollow0\levelstartat1\lvltentative\levelspace0\levelindent0{\leveltext\'01\u-3929 ?;}{\levelnumbers;} +\f10\fs20\fbias0 \fi-360\li6480\jclisttab\tx6480\lin6480 }{\listname ;}\listid891499942}{\list\listtemplateid-2106560774\listhybrid{\listlevel\levelnfc3\levelnfcn3\leveljc0\leveljcn0\levelfollow0\levelstartat1\levelspace0\levelindent0{\leveltext +\'02\'00.;}{\levelnumbers\'01;}\rtlch\fcs1 \af0 \ltrch\fcs0 \fbias0 \fi-360\li720\lin720 }{\listlevel\levelnfc4\levelnfcn4\leveljc0\leveljcn0\levelfollow0\levelstartat1\lvltentative\levelspace0\levelindent0{\leveltext\'02\'01.;}{\levelnumbers\'01;} +\rtlch\fcs1 \af0 \ltrch\fcs0 \fi-360\li1440\lin1440 }{\listlevel\levelnfc2\levelnfcn2\leveljc2\leveljcn2\levelfollow0\levelstartat1\lvltentative\levelspace0\levelindent0{\leveltext\'02\'02.;}{\levelnumbers\'01;}\rtlch\fcs1 \af0 \ltrch\fcs0 +\fi-180\li2160\lin2160 }{\listlevel\levelnfc0\levelnfcn0\leveljc0\leveljcn0\levelfollow0\levelstartat1\lvltentative\levelspace0\levelindent0{\leveltext\'02\'03.;}{\levelnumbers\'01;}\rtlch\fcs1 \af0 \ltrch\fcs0 \fi-360\li2880\lin2880 }{\listlevel +\levelnfc4\levelnfcn4\leveljc0\leveljcn0\levelfollow0\levelstartat1\lvltentative\levelspace0\levelindent0{\leveltext\'02\'04.;}{\levelnumbers\'01;}\rtlch\fcs1 \af0 \ltrch\fcs0 \fi-360\li3600\lin3600 }{\listlevel\levelnfc2\levelnfcn2\leveljc2\leveljcn2 +\levelfollow0\levelstartat1\lvltentative\levelspace0\levelindent0{\leveltext\'02\'05.;}{\levelnumbers\'01;}\rtlch\fcs1 \af0 \ltrch\fcs0 \fi-180\li4320\lin4320 }{\listlevel\levelnfc0\levelnfcn0\leveljc0\leveljcn0\levelfollow0\levelstartat1\lvltentative +\levelspace0\levelindent0{\leveltext\'02\'06.;}{\levelnumbers\'01;}\rtlch\fcs1 \af0 \ltrch\fcs0 \fi-360\li5040\lin5040 }{\listlevel\levelnfc4\levelnfcn4\leveljc0\leveljcn0\levelfollow0\levelstartat1\lvltentative\levelspace0\levelindent0{\leveltext +\'02\'07.;}{\levelnumbers\'01;}\rtlch\fcs1 \af0 \ltrch\fcs0 \fi-360\li5760\lin5760 }{\listlevel\levelnfc2\levelnfcn2\leveljc2\leveljcn2\levelfollow0\levelstartat1\lvltentative\levelspace0\levelindent0{\leveltext\'02\'08.;}{\levelnumbers\'01;}\rtlch\fcs1 +\af0 \ltrch\fcs0 \fi-180\li6480\lin6480 }{\listname ;}\listid939029968}{\list\listtemplateid1475657882\listhybrid{\listlevel\levelnfc23\levelnfcn23\leveljc0\leveljcn0\levelfollow0\levelstartat2\levelspace0\levelindent0{\leveltext\'01-;}{\levelnumbers;} +\loch\af1\hich\af1\dbch\af0\fbias0 \fi-360\li1440\lin1440 }{\listlevel\levelnfc23\levelnfcn23\leveljc0\leveljcn0\levelfollow0\levelstartat1\levelspace0\levelindent0{\leveltext\'01o;}{\levelnumbers;}\f2\fbias0 \fi-360\li2160\lin2160 }{\listlevel\levelnfc23 +\levelnfcn23\leveljc0\leveljcn0\levelfollow0\levelstartat1\lvltentative\levelspace0\levelindent0{\leveltext\'01\u-3929 ?;}{\levelnumbers;}\f10\fbias0 \fi-360\li2880\lin2880 }{\listlevel\levelnfc23\levelnfcn23\leveljc0\leveljcn0\levelfollow0\levelstartat1 +\lvltentative\levelspace0\levelindent0{\leveltext\'01\u-3913 ?;}{\levelnumbers;}\f3\fbias0 \fi-360\li3600\lin3600 }{\listlevel\levelnfc23\levelnfcn23\leveljc0\leveljcn0\levelfollow0\levelstartat1\lvltentative\levelspace0\levelindent0{\leveltext +\'01o;}{\levelnumbers;}\f2\fbias0 \fi-360\li4320\lin4320 }{\listlevel\levelnfc23\levelnfcn23\leveljc0\leveljcn0\levelfollow0\levelstartat1\lvltentative\levelspace0\levelindent0{\leveltext\'01\u-3929 ?;}{\levelnumbers;}\f10\fbias0 \fi-360\li5040\lin5040 } +{\listlevel\levelnfc23\levelnfcn23\leveljc0\leveljcn0\levelfollow0\levelstartat1\lvltentative\levelspace0\levelindent0{\leveltext\'01\u-3913 ?;}{\levelnumbers;}\f3\fbias0 \fi-360\li5760\lin5760 }{\listlevel\levelnfc23\levelnfcn23\leveljc0\leveljcn0 +\levelfollow0\levelstartat1\lvltentative\levelspace0\levelindent0{\leveltext\'01o;}{\levelnumbers;}\f2\fbias0 \fi-360\li6480\lin6480 }{\listlevel\levelnfc23\levelnfcn23\leveljc0\leveljcn0\levelfollow0\levelstartat1\lvltentative\levelspace0\levelindent0 +{\leveltext\'01\u-3929 ?;}{\levelnumbers;}\f10\fbias0 \fi-360\li7200\lin7200 }{\listname ;}\listid1080055287}{\list\listtemplateid345380616\listhybrid{\listlevel\levelnfc2\levelnfcn2\leveljc0\leveljcn0\levelfollow0\levelstartat2\levelspace0\levelindent0 +{\leveltext\'03(\'00);}{\levelnumbers\'02;}\rtlch\fcs1 \af0 \ltrch\fcs0 \fbias0 \fi-720\li1864\lin1864 }{\listlevel\levelnfc4\levelnfcn4\leveljc0\leveljcn0\levelfollow0\levelstartat1\lvltentative\levelspace0\levelindent0{\leveltext +\'02\'01.;}{\levelnumbers\'01;}\rtlch\fcs1 \af0 \ltrch\fcs0 \fi-360\li2224\lin2224 }{\listlevel\levelnfc2\levelnfcn2\leveljc2\leveljcn2\levelfollow0\levelstartat1\lvltentative\levelspace0\levelindent0{\leveltext\'02\'02.;}{\levelnumbers\'01;}\rtlch\fcs1 +\af0 \ltrch\fcs0 \fi-180\li2944\lin2944 }{\listlevel\levelnfc0\levelnfcn0\leveljc0\leveljcn0\levelfollow0\levelstartat1\lvltentative\levelspace0\levelindent0{\leveltext\'02\'03.;}{\levelnumbers\'01;}\rtlch\fcs1 \af0 \ltrch\fcs0 \fi-360\li3664\lin3664 } +{\listlevel\levelnfc4\levelnfcn4\leveljc0\leveljcn0\levelfollow0\levelstartat1\lvltentative\levelspace0\levelindent0{\leveltext\'02\'04.;}{\levelnumbers\'01;}\rtlch\fcs1 \af0 \ltrch\fcs0 \fi-360\li4384\lin4384 }{\listlevel\levelnfc2\levelnfcn2\leveljc2 +\leveljcn2\levelfollow0\levelstartat1\lvltentative\levelspace0\levelindent0{\leveltext\'02\'05.;}{\levelnumbers\'01;}\rtlch\fcs1 \af0 \ltrch\fcs0 \fi-180\li5104\lin5104 }{\listlevel\levelnfc0\levelnfcn0\leveljc0\leveljcn0\levelfollow0\levelstartat1 +\lvltentative\levelspace0\levelindent0{\leveltext\'02\'06.;}{\levelnumbers\'01;}\rtlch\fcs1 \af0 \ltrch\fcs0 \fi-360\li5824\lin5824 }{\listlevel\levelnfc4\levelnfcn4\leveljc0\leveljcn0\levelfollow0\levelstartat1\lvltentative\levelspace0\levelindent0 +{\leveltext\'02\'07.;}{\levelnumbers\'01;}\rtlch\fcs1 \af0 \ltrch\fcs0 \fi-360\li6544\lin6544 }{\listlevel\levelnfc2\levelnfcn2\leveljc2\leveljcn2\levelfollow0\levelstartat1\lvltentative\levelspace0\levelindent0{\leveltext\'02\'08.;}{\levelnumbers\'01;} +\rtlch\fcs1 \af0 \ltrch\fcs0 \fi-180\li7264\lin7264 }{\listname ;}\listid1198470673}{\list\listtemplateid-1488150726\listhybrid{\listlevel\levelnfc2\levelnfcn2\leveljc0\leveljcn0\levelfollow0\levelstartat1\levelspace0\levelindent0{\leveltext +\'03(\'00);}{\levelnumbers\'02;}\rtlch\fcs1 \af0 \ltrch\fcs0 \fbias0 \fi-720\li1080\lin1080 }{\listlevel\levelnfc4\levelnfcn4\leveljc0\leveljcn0\levelfollow0\levelstartat1\lvltentative\levelspace0\levelindent0{\leveltext\'02\'01.;}{\levelnumbers\'01;} +\rtlch\fcs1 \af0 \ltrch\fcs0 \fi-360\li1440\lin1440 }{\listlevel\levelnfc2\levelnfcn2\leveljc2\leveljcn2\levelfollow0\levelstartat1\lvltentative\levelspace0\levelindent0{\leveltext\'02\'02.;}{\levelnumbers\'01;}\rtlch\fcs1 \af0 \ltrch\fcs0 +\fi-180\li2160\lin2160 }{\listlevel\levelnfc0\levelnfcn0\leveljc0\leveljcn0\levelfollow0\levelstartat1\lvltentative\levelspace0\levelindent0{\leveltext\'02\'03.;}{\levelnumbers\'01;}\rtlch\fcs1 \af0 \ltrch\fcs0 \fi-360\li2880\lin2880 }{\listlevel +\levelnfc4\levelnfcn4\leveljc0\leveljcn0\levelfollow0\levelstartat1\lvltentative\levelspace0\levelindent0{\leveltext\'02\'04.;}{\levelnumbers\'01;}\rtlch\fcs1 \af0 \ltrch\fcs0 \fi-360\li3600\lin3600 }{\listlevel\levelnfc2\levelnfcn2\leveljc2\leveljcn2 +\levelfollow0\levelstartat1\lvltentative\levelspace0\levelindent0{\leveltext\'02\'05.;}{\levelnumbers\'01;}\rtlch\fcs1 \af0 \ltrch\fcs0 \fi-180\li4320\lin4320 }{\listlevel\levelnfc0\levelnfcn0\leveljc0\leveljcn0\levelfollow0\levelstartat1\lvltentative +\levelspace0\levelindent0{\leveltext\'02\'06.;}{\levelnumbers\'01;}\rtlch\fcs1 \af0 \ltrch\fcs0 \fi-360\li5040\lin5040 }{\listlevel\levelnfc4\levelnfcn4\leveljc0\leveljcn0\levelfollow0\levelstartat1\lvltentative\levelspace0\levelindent0{\leveltext +\'02\'07.;}{\levelnumbers\'01;}\rtlch\fcs1 \af0 \ltrch\fcs0 \fi-360\li5760\lin5760 }{\listlevel\levelnfc2\levelnfcn2\leveljc2\leveljcn2\levelfollow0\levelstartat1\lvltentative\levelspace0\levelindent0{\leveltext\'02\'08.;}{\levelnumbers\'01;}\rtlch\fcs1 +\af0 \ltrch\fcs0 \fi-180\li6480\lin6480 }{\listname ;}\listid1264800667}{\list\listtemplateid1709371634{\listlevel\levelnfc0\levelnfcn0\leveljc0\leveljcn0\levelfollow0\levelstartat1\levelspace0\levelindent0{\leveltext\'01\'00;}{\levelnumbers\'01;} +\rtlch\fcs1 \af0 \ltrch\fcs0 \fbias0 \fi-360\li360\lin360 }{\listlevel\levelnfc0\levelnfcn0\leveljc0\leveljcn0\levelfollow0\levelstartat2\levelspace0\levelindent0{\leveltext\'03\'00.\'01;}{\levelnumbers\'01\'03;}\rtlch\fcs1 \af0 \ltrch\fcs0 \fbias0 +\fi-360\li360\lin360 }{\listlevel\levelnfc0\levelnfcn0\leveljc0\leveljcn0\levelfollow0\levelstartat1\levelspace0\levelindent0{\leveltext\'05\'00.\'01.\'02;}{\levelnumbers\'01\'03\'05;}\rtlch\fcs1 \af0 \ltrch\fcs0 \fbias0 \fi-720\li720\lin720 }{\listlevel +\levelnfc0\levelnfcn0\leveljc0\leveljcn0\levelfollow0\levelstartat1\levelspace0\levelindent0{\leveltext\'07\'00.\'01.\'02.\'03;}{\levelnumbers\'01\'03\'05\'07;}\rtlch\fcs1 \af0 \ltrch\fcs0 \fbias0 \fi-720\li720\lin720 }{\listlevel\levelnfc0\levelnfcn0 +\leveljc0\leveljcn0\levelfollow0\levelstartat1\levelspace0\levelindent0{\leveltext\'09\'00.\'01.\'02.\'03.\'04;}{\levelnumbers\'01\'03\'05\'07\'09;}\rtlch\fcs1 \af0 \ltrch\fcs0 \fbias0 \fi-720\li720\lin720 }{\listlevel\levelnfc0\levelnfcn0\leveljc0 +\leveljcn0\levelfollow0\levelstartat1\levelspace0\levelindent0{\leveltext\'0b\'00.\'01.\'02.\'03.\'04.\'05;}{\levelnumbers\'01\'03\'05\'07\'09\'0b;}\rtlch\fcs1 \af0 \ltrch\fcs0 \fbias0 \fi-1080\li1080\lin1080 }{\listlevel\levelnfc0\levelnfcn0\leveljc0 +\leveljcn0\levelfollow0\levelstartat1\levelspace0\levelindent0{\leveltext\'0d\'00.\'01.\'02.\'03.\'04.\'05.\'06;}{\levelnumbers\'01\'03\'05\'07\'09\'0b\'0d;}\rtlch\fcs1 \af0 \ltrch\fcs0 \fbias0 \fi-1080\li1080\lin1080 }{\listlevel\levelnfc0\levelnfcn0 +\leveljc0\leveljcn0\levelfollow0\levelstartat1\levelspace0\levelindent0{\leveltext\'0f\'00.\'01.\'02.\'03.\'04.\'05.\'06.\'07;}{\levelnumbers\'01\'03\'05\'07\'09\'0b\'0d\'0f;}\rtlch\fcs1 \af0 \ltrch\fcs0 \fbias0 \fi-1440\li1440\lin1440 }{\listlevel +\levelnfc0\levelnfcn0\leveljc0\leveljcn0\levelfollow0\levelstartat1\levelspace0\levelindent0{\leveltext\'11\'00.\'01.\'02.\'03.\'04.\'05.\'06.\'07.\'08;}{\levelnumbers\'01\'03\'05\'07\'09\'0b\'0d\'0f\'11;}\rtlch\fcs1 \af0 \ltrch\fcs0 \fbias0 +\fi-1440\li1440\lin1440 }{\listname ;}\listid1335182434}{\list\listtemplateid-1861725538\listhybrid{\listlevel\levelnfc3\levelnfcn3\leveljc0\leveljcn0\levelfollow0\levelstartat1\levelspace0\levelindent0{\leveltext\'02\'00.;}{\levelnumbers\'01;} +\rtlch\fcs1 \af0 \ltrch\fcs0 \fbias0 \fi-360\li720\lin720 }{\listlevel\levelnfc4\levelnfcn4\leveljc0\leveljcn0\levelfollow0\levelstartat1\lvltentative\levelspace0\levelindent0{\leveltext\'02\'01.;}{\levelnumbers\'01;}\rtlch\fcs1 \af0 \ltrch\fcs0 +\fi-360\li1440\lin1440 }{\listlevel\levelnfc2\levelnfcn2\leveljc2\leveljcn2\levelfollow0\levelstartat1\lvltentative\levelspace0\levelindent0{\leveltext\'02\'02.;}{\levelnumbers\'01;}\rtlch\fcs1 \af0 \ltrch\fcs0 \fi-180\li2160\lin2160 }{\listlevel +\levelnfc0\levelnfcn0\leveljc0\leveljcn0\levelfollow0\levelstartat1\lvltentative\levelspace0\levelindent0{\leveltext\'02\'03.;}{\levelnumbers\'01;}\rtlch\fcs1 \af0 \ltrch\fcs0 \fi-360\li2880\lin2880 }{\listlevel\levelnfc4\levelnfcn4\leveljc0\leveljcn0 +\levelfollow0\levelstartat1\lvltentative\levelspace0\levelindent0{\leveltext\'02\'04.;}{\levelnumbers\'01;}\rtlch\fcs1 \af0 \ltrch\fcs0 \fi-360\li3600\lin3600 }{\listlevel\levelnfc2\levelnfcn2\leveljc2\leveljcn2\levelfollow0\levelstartat1\lvltentative +\levelspace0\levelindent0{\leveltext\'02\'05.;}{\levelnumbers\'01;}\rtlch\fcs1 \af0 \ltrch\fcs0 \fi-180\li4320\lin4320 }{\listlevel\levelnfc0\levelnfcn0\leveljc0\leveljcn0\levelfollow0\levelstartat1\lvltentative\levelspace0\levelindent0{\leveltext +\'02\'06.;}{\levelnumbers\'01;}\rtlch\fcs1 \af0 \ltrch\fcs0 \fi-360\li5040\lin5040 }{\listlevel\levelnfc4\levelnfcn4\leveljc0\leveljcn0\levelfollow0\levelstartat1\lvltentative\levelspace0\levelindent0{\leveltext\'02\'07.;}{\levelnumbers\'01;}\rtlch\fcs1 +\af0 \ltrch\fcs0 \fi-360\li5760\lin5760 }{\listlevel\levelnfc2\levelnfcn2\leveljc2\leveljcn2\levelfollow0\levelstartat1\lvltentative\levelspace0\levelindent0{\leveltext\'02\'08.;}{\levelnumbers\'01;}\rtlch\fcs1 \af0 \ltrch\fcs0 \fi-180\li6480\lin6480 } +{\listname ;}\listid1556695208}{\list\listtemplateid-301287646\listhybrid{\listlevel\levelnfc4\levelnfcn4\leveljc0\leveljcn0\levelfollow0\levelstartat1\levelspace0\levelindent0{\leveltext\'03(\'00);}{\levelnumbers\'02;}\rtlch\fcs1 \af0 \ltrch\fcs0 +\cf1\dbch\af0\fbias0 \fi-360\li720\lin720 }{\listlevel\levelnfc4\levelnfcn4\leveljc0\leveljcn0\levelfollow0\levelstartat1\lvltentative\levelspace0\levelindent0{\leveltext\'02\'01.;}{\levelnumbers\'01;}\rtlch\fcs1 \af0 \ltrch\fcs0 \fi-360\li1440\lin1440 } +{\listlevel\levelnfc2\levelnfcn2\leveljc2\leveljcn2\levelfollow0\levelstartat1\lvltentative\levelspace0\levelindent0{\leveltext\'02\'02.;}{\levelnumbers\'01;}\rtlch\fcs1 \af0 \ltrch\fcs0 \fi-180\li2160\lin2160 }{\listlevel\levelnfc0\levelnfcn0\leveljc0 +\leveljcn0\levelfollow0\levelstartat1\lvltentative\levelspace0\levelindent0{\leveltext\'02\'03.;}{\levelnumbers\'01;}\rtlch\fcs1 \af0 \ltrch\fcs0 \fi-360\li2880\lin2880 }{\listlevel\levelnfc4\levelnfcn4\leveljc0\leveljcn0\levelfollow0\levelstartat1 +\lvltentative\levelspace0\levelindent0{\leveltext\'02\'04.;}{\levelnumbers\'01;}\rtlch\fcs1 \af0 \ltrch\fcs0 \fi-360\li3600\lin3600 }{\listlevel\levelnfc2\levelnfcn2\leveljc2\leveljcn2\levelfollow0\levelstartat1\lvltentative\levelspace0\levelindent0 +{\leveltext\'02\'05.;}{\levelnumbers\'01;}\rtlch\fcs1 \af0 \ltrch\fcs0 \fi-180\li4320\lin4320 }{\listlevel\levelnfc0\levelnfcn0\leveljc0\leveljcn0\levelfollow0\levelstartat1\lvltentative\levelspace0\levelindent0{\leveltext\'02\'06.;}{\levelnumbers\'01;} +\rtlch\fcs1 \af0 \ltrch\fcs0 \fi-360\li5040\lin5040 }{\listlevel\levelnfc4\levelnfcn4\leveljc0\leveljcn0\levelfollow0\levelstartat1\lvltentative\levelspace0\levelindent0{\leveltext\'02\'07.;}{\levelnumbers\'01;}\rtlch\fcs1 \af0 \ltrch\fcs0 +\fi-360\li5760\lin5760 }{\listlevel\levelnfc2\levelnfcn2\leveljc2\leveljcn2\levelfollow0\levelstartat1\lvltentative\levelspace0\levelindent0{\leveltext\'02\'08.;}{\levelnumbers\'01;}\rtlch\fcs1 \af0 \ltrch\fcs0 \fi-180\li6480\lin6480 }{\listname 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+\fs18\loch\af1\hich\af1\dbch\af1\insrsid14553496 \hich\af1\dbch\af1\loch\f1 NUMPAGES}}{\fldrslt {\rtlch\fcs1 \af1 \ltrch\fcs0 \fs18\lang1024\langfe1024\loch\af1\hich\af1\dbch\af1\noproof\insrsid2044820 \hich\af1\dbch\af1\loch\f1 5}}}\sectd \ltrsect +\linex0\endnhere\sectdefaultcl\sftnbj {\rtlch\fcs1 \af1 \ltrch\fcs0 \fs18\loch\af1\hich\af1\dbch\af1\insrsid14553496 \cell \cell }\pard \ltrpar\ql \li0\ri0\widctlpar\intbl\wrapdefault\aspalpha\aspnum\faauto\adjustright\rin0\lin0 {\rtlch\fcs1 \af1 +\ltrch\fcs0 \fs18\loch\af1\hich\af1\dbch\af1\insrsid14553496 \trowd \irow0\irowband0\lastrow \ltrrow\ts11\trgaph108\trrh240\trleft-108\trftsWidth1\trautofit1\trpaddl108\trpaddr108\trpaddfl3\trpaddfr3\tblind0\tblindtype3 \clvertalt\clbrdrt\brdrtbl \clbrdrl +\brdrtbl \clbrdrb\brdrtbl \clbrdrr\brdrtbl \cltxlrtb\clftsWidth3\clwWidth4513\clshdrawnil \cellx4405\clvertalt\clbrdrt\brdrtbl \clbrdrl\brdrtbl \clbrdrb\brdrtbl \clbrdrr\brdrtbl \cltxlrtb\clftsWidth3\clwWidth4513\clshdrawnil \cellx8918\row }\pard \ltrpar +\ql \li0\ri0\sa200\sl276\slmult1\widctlpar\wrapdefault\aspalpha\aspnum\faauto\adjustright\rin0\lin0\itap0 {\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid14553496 +\par }}{\*\pnseclvl1\pnucrm\pnstart1\pnindent720\pnhang {\pntxta .}}{\*\pnseclvl2\pnucltr\pnstart1\pnindent720\pnhang {\pntxta .}}{\*\pnseclvl3\pndec\pnstart1\pnindent720\pnhang {\pntxta .}}{\*\pnseclvl4\pnlcltr\pnstart1\pnindent720\pnhang {\pntxta )}} +{\*\pnseclvl5\pndec\pnstart1\pnindent720\pnhang {\pntxtb (}{\pntxta )}}{\*\pnseclvl6\pnlcltr\pnstart1\pnindent720\pnhang {\pntxtb (}{\pntxta )}}{\*\pnseclvl7\pnlcrm\pnstart1\pnindent720\pnhang {\pntxtb (}{\pntxta )}}{\*\pnseclvl8 +\pnlcltr\pnstart1\pnindent720\pnhang {\pntxtb (}{\pntxta )}}{\*\pnseclvl9\pnlcrm\pnstart1\pnindent720\pnhang {\pntxtb (}{\pntxta )}}\pard\plain \ltrpar\qj \li0\ri0\sa240\widctlpar +\tx916\tx1832\tx2748\tx3664\tx4580\tx5496\tx6412\tx7328\tx8244\tx9160\tx10076\tx10992\tx11908\tx12824\tx13740\tx14656\wrapdefault\aspalpha\aspnum\faauto\adjustright\rin0\lin0\itap0\pararsid14553496 \cbpat8 \rtlch\fcs1 \af0\afs22\alang1025 \ltrch\fcs0 +\fs22\lang2057\langfe1033\loch\af37\hich\af37\dbch\af37\cgrid\langnp2057\langfenp1033 {\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid15280636 END USER LICENCE AGREEMENT FOR THE }{\rtlch\fcs1 +\af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 CORTEX MICROCONTROLLER SOFTWARE INTERFACE STANDARD (CMSIS) DELIVERABLES }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 +\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid15280636 +\par THIS END USER LICENCE AGREEMENT ("LICENCE") IS A LEGAL AGREEMENT BETWEEN YOU (EITHER A }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid5861575 +SINGLE INDIVIDUAL, OR SINGLE LEGAL ENTITY) AND ARM LIMITED ("ARM") FOR THE USE OF THE CMSIS }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 DELIVERABLES}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 +\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid5861575 . ARM IS ONLY WILLING TO LICENSE THE }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 CMSIS DELIVERABLES }{\rtlch\fcs1 +\af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid5861575 TO YOU ON CONDITION THAT YOU ACCEPT ALL OF THE}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 +\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid15280636 TERMS IN THIS LICENCE. BY CLICKING "I AGREE", OR BY INSTALLING OR OTHERWISE USING OR COPYING THE }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 +\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 CMSIS DELIVERABLES }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid15280636 +YOU INDICATE THAT YOU AGREE TO BE BOUND BY ALL THE TERMS OF THIS LICENCE. IF YOU DO NOT AGREE TO THE TERMS OF THIS LICENCE, ARM IS UNWILLING TO LICENSE YOU TO USE }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 +\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 OF }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid15280636 THE }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 +\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 CMSIS DELIVERABLES}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid15280636 AND YOU MAY NOT INSTALL, USE OR COPY THE }{\rtlch\fcs1 +\af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 CMSIS DELIVERABLES}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid15280636 . +\par }\pard \ltrpar\qj \li0\ri0\sa200\sl276\slmult1\widctlpar\wrapdefault\aspalpha\aspnum\faauto\adjustright\rin0\lin0\itap0\pararsid14553496 {\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 \'93Deliverables\'94 + means (i) the CMSIS Deliverables; (ii) CMSIS-DAP Specification; (iii) CMSIS-DAP Firmware; and (iv) RDDI DLL. +\par \'93CMSIS-DAP Specification\'94 means any documentation defining the application programming interface, naming and coding conventions of the Cortex Microcontroller Software Interface Standard Debug Access Port (\'93CMSIS-DAP\'94). }{\rtlch\fcs1 +\af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid14553496\charrsid4029239 \hich\af1\dbch\af37\loch\f1 \hich\f1 Notwithstanding the foregoing, \'93}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid14553496 \hich\af1\dbch\af37\loch\f1 CMSIS-DAP }{\rtlch\fcs1 +\af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid14553496\charrsid4029239 \hich\af1\dbch\af37\loch\f1 \hich\f1 Specification\'94\loch\f1 shall not include}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid14553496 \hich\af1\dbch\af37\loch\f1 :}{\rtlch\fcs1 +\af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid14553496\charrsid4029239 \hich\af1\dbch\af37\loch\f1 (i) the implementation of other published specifications referenced in th}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid14553496 +\hich\af1\dbch\af37\loch\f1 e}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid14553496\charrsid4029239 \hich\af1\dbch\af37\loch\f1 }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid14553496 \hich\af1\dbch\af37\loch\f1 CMSIS-DAP }{\rtlch\fcs1 +\af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid14553496\charrsid4029239 \hich\af1\dbch\af37\loch\f1 Specific\hich\af1\dbch\af37\loch\f1 ation; }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid14553496 \hich\af1\dbch\af37\loch\f1 and }{\rtlch\fcs1 \af1\afs18 +\ltrch\fcs0 \f1\fs18\insrsid14553496\charrsid4029239 \hich\af1\dbch\af37\loch\f1 (ii) any enabling technologies that may be necessary to make or use any product or portion}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid14553496 +\hich\af1\dbch\af37\loch\f1 s}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid14553496\charrsid4029239 \hich\af1\dbch\af37\loch\f1 thereof that complies with the }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid14553496 +\hich\af1\dbch\af37\loch\f1 CMSIS-DAP }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid14553496\charrsid4029239 \hich\af1\dbch\af37\loch\f1 Specification, but are not themselves expressly set forth in th}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 +\f1\fs18\insrsid14553496 \hich\af1\dbch\af37\loch\f1 e}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid14553496\charrsid4029239 \hich\af1\dbch\af37\loch\f1 }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid14553496 \hich\af1\dbch\af37\loch\f1 +CMSIS-DAP }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid14553496\charrsid4029239 \hich\af1\dbch\af37\loch\f1 Specification (e.g. compiler front en\hich\af1\dbch\af37\loch\f1 +ds, code generators, back ends, libraries or other compiler, assembler or linker technologies; validation or debug software or hardware; applications, operating system or driver software; RISC architecture; }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 +\f1\fs18\insrsid14553496 \hich\af1\dbch\af37\loch\f1 and }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid14553496\charrsid4029239 \hich\af1\dbch\af37\loch\f1 processor microarchitecture)}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid14553496 +\hich\af1\dbch\af37\loch\f1 . }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid14553496\charrsid4029239 \hich\af1\dbch\af37\loch\f1 }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid14553496 +\par }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 \'93}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid14553496\charrsid11929640 \hich\af1\dbch\af37\loch\f1 CMSIS-DAP Fi\hich\af1\dbch\af37\loch\f1 +rmware}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 \'94 + means the C programming language source code accompanying this Licence which implements the functionality of the application programming interface as defined in the CMSIS-DAP Specification and any updates, patches and modifications ARM may make ava +ilable under the terms of this Licence. +\par \'93CMSIS Deliverables\'94 means the following components: (i) CMSIS-CORE; (ii) CMSIS-DRIVER; (iii) CMSIS-DSP; (iv) CMSIS-PACK; (v) CMSIS-RTOS API; and (vi) CMSIS-SVD . +\par }\pard \ltrpar\qj \li0\ri0\sa200\sl276\slmult1\widctlpar\tx0\wrapdefault\aspalpha\aspnum\faauto\adjustright\rin0\lin0\itap0\pararsid14553496 {\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 \'93CMSIS-CORE +\'94 means the specification defining the application programming interface, naming and coding conventions for the Cortex-M processor cores. +\par \'94}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid14553496\charrsid488451 \hich\af1\dbch\af37\loch\f1 CMSIS-DRIVER}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 \'94}{\rtlch\fcs1 \af0 \ltrch\fcs0 +\insrsid14553496 \hich\af37\dbch\af37\loch\f37 }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid14553496\charrsid488451 \hich\af1\dbch\af37\loch\f1 means the specification defining }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid14553496 +\hich\af1\dbch\af37\loch\f1 a generic}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid14553496\charrsid488451 \hich\af1\dbch\af37\loch\f1 }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid14553496 \hich\af1\dbch\af37\loch\f1 p}{\rtlch\fcs1 +\af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid14553496\charrsid488451 \hich\af1\dbch\af37\loch\f1 eripheral }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid14553496 \hich\af1\dbch\af37\loch\f1 d}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 +\f1\fs18\insrsid14553496\charrsid488451 \hich\af1\dbch\af37\loch\f1 river application programming interface, naming and coding conventions}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid14553496 . +\par }\pard \ltrpar\qj \li0\ri0\sa200\sl276\slmult1\widctlpar\wrapdefault\aspalpha\aspnum\faauto\adjustright\rin0\lin0\itap0\pararsid14553496 {\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 \'93CMSIS-DSP\'94 + means the digital signal process (DSP) library specification defining the application programming interface of a DSP library implementation}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 +\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid15023647 .}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 +\par }\pard \ltrpar\qj \li0\ri0\sa200\sl276\slmult1\widctlpar\tx0\wrapdefault\aspalpha\aspnum\faauto\adjustright\rin0\lin0\itap0\pararsid14553496 {\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 \'93}{ +\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid14553496\charrsid13240697 \hich\af1\dbch\af37\loch\f1 CMSIS-PACK}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 \'94}{\rtlch\fcs1 \af0 \ltrch\fcs0 +\insrsid14553496\charrsid13240697 \hich\af37\dbch\af37\loch\f37 }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid14553496\charrsid13240697 \hich\af1\dbch\af37\loch\f1 means the specification defining a software pack file format}{\rtlch\fcs1 +\af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid14553496 \hich\af1\dbch\af37\loch\f1 , verification utility, }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid14553496\charrsid13240697 \hich\af1\dbch\af37\loch\f1 and the associated XML +\hich\af1\dbch\af37\loch\f1 schema file}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid14553496\charrsid13240697 .}{\rtlch\fcs1 \af0 \ltrch\fcs0 \insrsid14553496 +\par }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 \'93CMSIS-RTOS API\'94 + means the real-time operating system (RTOS) specification defining a generic application programming interface layer for a RTOS system}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid15023647 .}{ +\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 +\par }\pard \ltrpar\qj \li0\ri0\sa200\sl276\slmult1\widctlpar\wrapdefault\aspalpha\aspnum\faauto\adjustright\rin0\lin0\itap0\pararsid14553496 {\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 \'93CMSIS-SVD\'94 }{ +\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid9306407 means }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 +the specification defining the System View Description (SVD), verification utility, }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf17\lang1033\langfe2057\langnp1033\langfenp2057\insrsid14553496\charrsid9306407 and associated XML}{\rtlch\fcs1 \af1\afs18 +\ltrch\fcs0 \f1\fs18\cf17\lang1033\langfe2057\langnp1033\langfenp2057\insrsid14553496 schema}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf17\lang1033\langfe2057\langnp1033\langfenp2057\insrsid14553496\charrsid9306407 files. }{\rtlch\fcs1 \af1\afs18 +\ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid9306407 +\par }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 \'93Firmware\'94 means firmware that complies with the CMSIS-DAP Specification. +\par \'93RDDI DLL\'94 means the reference implementation of a device driver }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid6236778 accompanying this Licence}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 +\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 in object code form and any updates, patch +es and modifications ARM may agree to make available under the terms of this Licence and is used with targets containing microprocessors manufactured or simulated under licence from ARM. +\par \'93Separate Files\'94 means the components }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid10227990 identified}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 +\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 in the Schedule.}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid3618484 .}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 +\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 +\par \'93Target Connection Product\'94 means a target connection product that complies with the CMSIS-DAP Specification and is used on or with a target containing microprocessors manufactured or simulated under licence from ARM. +\par }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid14553496\charrsid5577184 \hich\af1\dbch\af37\loch\f1 +Notwithstanding the foregoing, the Deliverables shall not include: (i) the implementation of other published specifications referenced in the Deliverables; (ii) any enabling technologies that may be necessary to make or use any product or portion thereof +\hich\af1\dbch\af37\loch\f1 +that complies with the Deliverables, but are not themselves expressly set forth in the Deliverables (e.g. compiler front ends, code generators, back ends, libraries or other compiler, assembler or linker technologies; validation or debug software or hard +\hich\af1\dbch\af37\loch\f1 w\hich\af1\dbch\af37\loch\f1 +are; applications, operating system or driver software; RISC architecture; processor microarchitecture); (iii) maskworks and physical layouts of integrated circuit designs; or (iv) RTL or other high level representations of integrated circuit designs.}{ +\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid14553496 +\par }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 +\par }\pard \ltrpar\qj \li0\ri0\sa240\widctlpar\tx916\tx1832\tx2748\tx3664\tx4580\tx5496\tx6412\tx7328\tx8244\tx9160\tx10076\tx10992\tx11908\tx12824\tx13740\tx14656\wrapdefault\aspalpha\aspnum\faauto\adjustright\rin0\lin0\itap0\pararsid14553496 \cbpat8 { +\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid15280636 1. LICENCE GRANTS. +\par }\pard \ltrpar\qj \li0\ri0\widctlpar\tx916\tx1832\tx2748\tx3664\tx4580\tx5496\tx6412\tx7328\tx8244\tx9160\tx10076\tx10992\tx11908\tx12824\tx13740\tx14656\wrapdefault\aspalpha\aspnum\faauto\adjustright\rin0\lin0\itap0\pararsid14553496 \cbpat8 {\rtlch\fcs1 +\af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 1.1}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid15280636 }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 +\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 CMSIS DELIVERABLES +\par }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid6756135 ARM hereby grants to you, subject to the terms and conditions of this Licence, a non-exclusive, non-transferable }{\rtlch\fcs1 \af1\afs18 +\ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid1317547 licence, to use and copy the }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 CMSIS D}{\rtlch\fcs1 \af1\afs18 +\ltrch\fcs0 \f1\fs18\insrsid14553496 \hich\af1\dbch\af37\loch\f1 eliverables}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 +\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid6756135 for the purpose of: }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 +\par }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid6756135 +\par }\pard \ltrpar\qj \li0\ri0\sa200\sl276\slmult1\widctlpar +\tx426\tx916\tx1832\tx2748\tx3664\tx4580\tx5496\tx6412\tx7328\tx8244\tx9160\tx10076\tx10992\tx11908\tx12824\tx13740\tx14656\wrapdefault\aspalpha\aspnum\faauto\adjustright\rin0\lin0\itap0\pararsid14553496 \cbpat8 {\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 +\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid6756135 (i) subject to clause 1.}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 5(i)}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 +\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid6756135 , developing, having developed, manufacturing, having manufactured, offering to sell, selling, supplying or otherwise distributing products that comply with the }{\rtlch\fcs1 +\af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 CMSIS D}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid14553496 \hich\af1\dbch\af37\loch\f1 eliverables}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 +\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid6756135 ; and +\par }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid1317547 (ii) distributing and having distributed (directly or through your customers and authorised distributors) the CMSIS-D}{\rtlch\fcs1 +\af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid14553496 \hich\af1\dbch\af37\loch\f1 eliverables}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid1317547 unmodified, with the products}{\rtlch\fcs1 +\af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid6756135 you have developed under }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 Clause 1.1 (i) }{\rtlch\fcs1 +\af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid6756135 provided you preserve any copyright notices which are included with the CMSIS}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 +\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 D}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid14553496 \hich\af1\dbch\af37\loch\f1 eliverables}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 +\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid6756135 . }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 +\par 1.2 CMSIS-DAP SPECIFICATION +\par }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid15280636 ARM hereby grants to you, subject to the terms and conditions of this Licence, a non-exclusive, non-transferable licence, to }{\rtlch\fcs1 +\af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid3605578 use and copy the CMSIS}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 -DAP }{\rtlch\fcs1 \af1\afs18 +\ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid6386005 Specification}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 for the purposes of: +\par }\pard \ltrpar\qj \fi-567\li567\ri0\sl276\slmult1\widctlpar\tx567\tx5496\tx6412\tx7328\tx8244\tx9160\tx10076\tx10992\tx11908\tx12824\tx13740\tx14656\wrapdefault\aspalpha\aspnum\faauto\adjustright\rin0\lin567\itap0\pararsid14553496 \cbpat8 {\rtlch\fcs1 +\af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 (a)\tab }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid11225765 +developing, having developed, manufacturing, having manufactured, offering to sell, selling, supplying}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 +, distributing or having distributed a Target Connection Product}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\lang1024\langfe1024\noproof\insrsid14553496 \hich\af1\dbch\af37\loch\f1 ;}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 +\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 +\par }\pard \ltrpar\qj \fi-567\li567\ri0\sl276\slmult1\widctlpar\tx4580\tx5496\tx6412\tx7328\tx8244\tx9160\tx10076\tx10992\tx11908\tx12824\tx13740\tx14656\wrapdefault\aspalpha\aspnum\faauto\adjustright\rin0\lin567\itap0\pararsid14553496 \cbpat8 {\rtlch\fcs1 +\af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 (b)\tab }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid11225765 developing, having developed, }{\rtlch\fcs1 +\af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 subject to clause 1.5(ii) }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid11225765 +offering to sell, selling, supplying}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 , }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid11225765 +distributing}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 or having distributed }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\lang1024\langfe1024\noproof\insrsid14553496 \hich\af1\dbch\af37\loch\f1 +(directly or through your cus\hich\af1\dbch\af37\loch\f1 tomers and authorised distributors) }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 Firmware to run on a Target Connection Product; and +\par }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid4549827 (c)}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 \tab subject to clause 1.5(ii), }{ +\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid4549827 distributing }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 and }{\rtlch\fcs1 \af1\afs18 +\ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid4549827 having distributed }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\lang1024\langfe1024\noproof\insrsid14553496 \hich\af1\dbch\af37\loch\f1 +(directly or through your customers and authorised distributors) }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid4549827 the CMSIS}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 +\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 -}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid4549827 DAP }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 +\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid14559761 Specification unmodified}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 ,}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 +\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid14559761 with}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid4549827 }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 +\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 either or both the}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid4549827 Target Connection Products and Firmware}{\rtlch\fcs1 +\af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 , developed under the licences granted in this Clause 1.2}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 +\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid4549827 .}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 +\par }\pard \ltrpar\qj \li0\ri0\sa200\sl276\slmult1\widctlpar +\tx426\tx916\tx1832\tx2748\tx3664\tx4580\tx5496\tx6412\tx7328\tx8244\tx9160\tx10076\tx10992\tx11908\tx12824\tx13740\tx14656\wrapdefault\aspalpha\aspnum\faauto\adjustright\rin0\lin0\itap0\pararsid14553496 \cbpat8 {\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 +\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 +\par 1.3 CMSIS-DAP FIRMWARE +\par }\pard \ltrpar\qj \li0\ri0\sl276\slmult1\widctlpar\tx916\tx1832\tx2748\tx3664\tx4580\tx5496\tx6412\tx7328\tx8244\tx9160\tx10076\tx10992\tx11908\tx12824\tx13740\tx14656\wrapdefault\aspalpha\aspnum\faauto\adjustright\rin0\lin0\itap0\pararsid14553496 +\cbpat8 {\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid14553496 \hich\af1\dbch\af37\loch\f1 ARM hereby grants to you, subject to the terms and conditions of this Licence, a non-exclusive, non-trans\hich\af1\dbch\af37\loch\f1 ferable licence, to: + +\par }\pard \ltrpar\qj \fi-567\li567\ri0\sl276\slmult1\widctlpar +\tx916\tx1832\tx2748\tx3664\tx4580\tx5496\tx6412\tx7328\tx8244\tx9160\tx10076\tx10992\tx11908\tx12824\tx13740\tx14656\wrapdefault\aspalpha\aspnum\faauto\adjustright\rin0\lin567\itap0\pararsid14553496 \cbpat8 {\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 +\f1\fs18\insrsid14553496 \hich\af1\dbch\af37\loch\f1 (a)\tab }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid14553496\charrsid10356267 \hich\af1\dbch\af37\loch\f1 use, copy}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid14553496\charrsid2558325 +\hich\af1\dbch\af37\loch\f1 , and modify the }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid14553496 \hich\af1\dbch\af37\loch\f1 CMSIS-DAP Firmware }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 +for the purposes of developing and having developed }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid8745136 firmware to run on}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 +\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 a Target Connection Product; and +\par (b)\tab subject to clause 1.5(ii), offer to sell, selling, }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid5058240 supply}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 +\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 , supplying, }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid8745136 distributing}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 +\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 or having distributed }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\lang1024\langfe1024\noproof\insrsid14553496 \hich\af1\dbch\af37\loch\f1 +(directly or through your customers and authorised distributors)}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 CMSIS-DAP Firmware or any modified version created under Clause 1.3 (a) }{\rtlch\fcs1 +\af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid8745136 in}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid6192099 object code form only }{\rtlch\fcs1 +\af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 to run on a Target Connection Product. }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid9913780 }{\rtlch\fcs1 +\af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 +\par +\par }\pard \ltrpar\qj \li0\ri0\sa200\sl276\slmult1\widctlpar +\tx426\tx916\tx1832\tx2748\tx3664\tx4580\tx5496\tx6412\tx7328\tx8244\tx9160\tx10076\tx10992\tx11908\tx12824\tx13740\tx14656\wrapdefault\aspalpha\aspnum\faauto\adjustright\rin0\lin0\itap0\pararsid14553496 \cbpat8 {\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 +\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 1.4 RDDI DLL +\par }\pard \ltrpar\qj \li0\ri0\sl276\slmult1\widctlpar\tx916\tx1832\tx2748\tx3664\tx4580\tx5496\tx6412\tx7328\tx8244\tx9160\tx10076\tx10992\tx11908\tx12824\tx13740\tx14656\wrapdefault\aspalpha\aspnum\faauto\adjustright\rin0\lin0\itap0\pararsid14553496 +\cbpat8 {\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 ARM hereby grants to you, subject to the terms and conditions of this Licence, a non-exclusive, non-transferable licence, to: +\par }\pard \ltrpar\qj \fi-567\li567\ri0\sl276\slmult1\widctlpar +\tx916\tx1832\tx2748\tx3664\tx4580\tx5496\tx6412\tx7328\tx8244\tx9160\tx10076\tx10992\tx11908\tx12824\tx13740\tx14656\wrapdefault\aspalpha\aspnum\faauto\adjustright\rin0\lin567\itap0\pararsid14553496 \cbpat8 {\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 +\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 (a)\tab use and copy the RDDI DLL for the purpose }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid13793259 of connecting }{ +\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 a Target Connection Product }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid11805076 +running CMSIS-DAP compatible firmware }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 (either the Firmware or the firmware created pursuant to Clause 1.3) }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 +\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid11805076 to }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 software debug tools installed on }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 +\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid11805076 a host }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 computer running a Windows platform}{\rtlch\fcs1 \af1\afs18 +\ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid11805076 ; and}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 +\par (b)\tab subject to clause 1.5(ii), offer to sell, selling, supplying, distributing or having distributed }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\lang1024\langfe1024\noproof\insrsid14553496 \hich\af1\dbch\af37\loch\f1 (directly or +\hich\af1\dbch\af37\loch\f1 through your customers and authorised distributors) }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 the RDDI DLL in object code form only. +\par }\pard \ltrpar\qj \li0\ri0\sa200\sl276\slmult1\widctlpar +\tx426\tx916\tx1832\tx2748\tx3664\tx4580\tx5496\tx6412\tx7328\tx8244\tx9160\tx10076\tx10992\tx11908\tx12824\tx13740\tx14656\wrapdefault\aspalpha\aspnum\faauto\adjustright\rin0\lin0\itap0\pararsid14553496 \cbpat8 {\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 +\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid6756135 +\par }\pard \ltrpar\qj \li0\ri0\widctlpar\tx916\tx1832\tx2748\tx3664\tx4580\tx5496\tx6412\tx7328\tx8244\tx9160\tx10076\tx10992\tx11908\tx12824\tx13740\tx14656\wrapdefault\aspalpha\aspnum\faauto\adjustright\rin0\lin0\itap0\pararsid14553496 \cbpat8 {\rtlch\fcs1 +\af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 1.5}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid15280636 CONDITIONS ON REDISTRIBUTION}{\rtlch\fcs1 +\af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 .}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid15280636 }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 +\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 +\par +\par }\pard \ltrpar\qj \li0\ri0\sa200\sl276\slmult1\widctlpar\tx916\tx1832\tx2748\tx3664\tx4580\tx5496\tx6412\tx7328\tx8244\tx9160\tx10076\tx10992\tx11908\tx12824\tx13740\tx14656\wrapdefault\aspalpha\aspnum\faauto\adjustright\rin0\lin0\itap0\pararsid14553496 +\cbpat8 {\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\lang1024\langfe1024\noproof\insrsid14553496 \hich\af1\dbch\af37\loch\f1 (i) }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\lang1024\langfe1024\noproof\insrsid14553496\charrsid1928237 +\hich\af1\dbch\af37\loch\f1 If you distribute (directly or through your customers and authorised distributors) the products you have created pursuant \hich\af1\dbch\af37\loch\f1 to Clause 1.1}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 +\f1\fs18\lang1024\langfe1024\noproof\insrsid14553496 \hich\af1\dbch\af37\loch\f1 }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\lang1024\langfe1024\noproof\insrsid14553496\charrsid1928237 \hich\af1\dbch\af37\loch\f1 (i) you agree: (a) not to use ARM +\hich\f1 \rquote \loch\f1 s name, logo or trademarks to market any or all of the }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid1928237 products created under Clause 1.1 (i); }{\rtlch\fcs1 +\af1\afs18 \ltrch\fcs0 \f1\fs18\lang1024\langfe1024\noproof\insrsid14553496\charrsid1928237 \hich\af1\dbch\af37\loch\f1 (b) }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\lang1024\langfe1024\noproof\insrsid14553496 \hich\af1\dbch\af37\loch\f1 to }{ +\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\lang1024\langfe1024\noproof\insrsid14553496\charrsid1928237 \hich\af1\dbch\af37\loch\f1 pr}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\lang1024\langfe1024\noproof\insrsid14553496 \hich\af1\dbch\af37\loch\f1 e}{ +\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\lang1024\langfe1024\noproof\insrsid14553496\charrsid1928237 \hich\af1\dbch\af37\loch\f1 serve any copyright notices included in the }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 +\f1\fs18\lang1024\langfe1024\noproof\insrsid14553496 \hich\af1\dbch\af37\loch\f1 CMSIS D}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid14553496 \hich\af1\dbch\af37\loch\f1 eliverables}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 +\f1\fs18\lang1024\langfe1024\noproof\insrsid14553496\charrsid1928237 \hich\af1\dbch\af37\loch\f1 ; and (c) to ensure your customers and aut\hich\af1\dbch\af37\loch\f1 horised distributors comply with this Clause 1.}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 +\f1\fs18\lang1024\langfe1024\noproof\insrsid14553496 \hich\af1\dbch\af37\loch\f1 5(i)}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\lang1024\langfe1024\noproof\insrsid14553496\charrsid1928237 .}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 +\f1\fs18\lang1024\langfe1024\noproof\insrsid14553496 \hich\af1\dbch\af37\loch\f1 +\par }\pard \ltrpar\qj \li0\ri0\sa200\sl276\slmult1\widctlpar\wrapdefault\aspalpha\aspnum\faauto\adjustright\rin0\lin0\itap0\pararsid14553496 {\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\lang1024\langfe1024\noproof\insrsid14553496 \hich\af1\dbch\af37\loch\f1 +(ii) If you are authorised and choose to distribute (directly or through your customers and authorised distributors) the }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid4549827 CMSIS}{\rtlch\fcs1 +\af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 -}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid4549827 DAP }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 +\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid14559761 Specification}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 , }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 +\f1\fs18\lang1024\langfe1024\noproof\insrsid14553496 \hich\af1\dbch\af37\loch\f1 Firmware, CMSIS-DAP Firmware or any modified version \hich\af1\dbch\af37\loch\f1 +thereof, or the RDDI DLL, you agree; (a) to ensure that they are licensed for use with targets containing microprocessors manufactured or simulated under licence from ARM; (b) to preserve any copyright notices which are included with the }{\rtlch\fcs1 +\af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid4549827 CMSIS}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 -}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 +\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid4549827 DAP }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid14559761 Specification}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 +\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 , CMSIS-DAP Firmware}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\lang1024\langfe1024\noproof\insrsid14553496 \hich\af1\dbch\af37\loch\f1 +, and include valid copyright notices in; (i) any modified version of the }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 CMSIS-DAP Firmware}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 +\f1\fs18\lang1024\langfe1024\noproof\insrsid14553496 \hich\af1\dbch\af37\loch\f1 ; and (ii) the Firmware; (c) not to use ARM\hich\f1 \rquote \loch\f1 s name, logo or trademarks to market -any or all of the }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 +\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid4549827 CMSIS}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 -}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 +\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid4549827 DAP }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid14559761 Specification}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 +\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 , Firmware,}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\lang1024\langfe1024\noproof\insrsid14553496 \hich\af1\dbch\af37\loch\f1 CMSI\hich\af1\dbch\af37\loch\f1 +S-DAP Firmware or any modified version therof, the RDDI DLL or the Target Connection Products; and (d) to ensure your customers and authorised distributors comply with this Clause 1.5(ii). +\par }\pard \ltrpar\qj \li0\ri0\sa200\sl276\slmult1\widctlpar\tx916\tx1832\tx2748\tx3664\tx4580\tx5496\tx6412\tx7328\tx8244\tx9160\tx10076\tx10992\tx11908\tx12824\tx13740\tx14656\wrapdefault\aspalpha\aspnum\faauto\adjustright\rin0\lin0\itap0\pararsid14553496 +\cbpat8 {\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 +\par }\pard \ltrpar\qj \li0\ri0\sa240\widctlpar\tx916\tx1832\tx2748\tx3664\tx4580\tx5496\tx6412\tx7328\tx8244\tx9160\tx10076\tx10992\tx11908\tx12824\tx13740\tx14656\wrapdefault\aspalpha\aspnum\faauto\adjustright\rin0\lin0\itap0\pararsid14553496 \cbpat8 { +\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid15280636 2. RESTRICTIONS ON USE OF THE}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 DELIVERABLES +}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid15280636 . +\par }\pard \ltrpar\qj \li0\ri0\sa200\sl276\slmult1\widctlpar\tx916\tx1832\tx2748\tx3664\tx4580\tx5496\tx6412\tx7328\tx8244\tx9160\tx10076\tx10992\tx11908\tx12824\tx13740\tx14656\wrapdefault\aspalpha\aspnum\faauto\adjustright\rin0\lin0\itap0\pararsid14553496 +\cbpat8 {\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid15280636 PERMITTED USERS: The }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 +Deliverables }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid15280636 shall be used only by you (either a single individual, or single legal entity) your employees, or by your }{\rtlch\fcs1 +\af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 on-site }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid15280636 +bona fide sub-contractors for whose acts and omissions you hereby agree to be responsible to ARM}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 for}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 +\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid15280636 to the same extent as }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 you are for }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 +\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid15280636 your employees, and provided always that such sub-contractors}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 :}{\rtlch\fcs1 +\af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid15280636 (i) are contractually obligated to use the }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 +Deliverables }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid15280636 only for your benefit}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 ;}{ +\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid15280636 and (i}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 i}{\rtlch\fcs1 \af1\afs18 +\ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid15280636 ) agree to assign all their work product and any rights they create therein in the supply of such work to you. +\par COPYRIGHT AND RESERVATION OF RIGHTS}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid14488502 : The }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 +\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 Deliverables}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid14488502 + are owned by ARM or its licensors and are protected by copyright and other intellectual property laws and international treaties. The }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 Deliverables}{ +\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid14488502 are licensed not sold. Except as expressly licensed herein, you acquire no right, title or interest in the }{\rtlch\fcs1 \af1\afs18 +\ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 Deliverables}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid14488502 + or any intellectual property therein. In no event shall the licences granted herein be construed as granting you, expressly or by implication, estoppels or otherwise, a licence to use any ARM technology except the }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 +\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 Deliverables}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid14488502 .}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 +\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid15280636 +\par }\pard \ltrpar\qj \li0\ri0\sa240\widctlpar\tx916\tx1832\tx2748\tx3664\tx4580\tx5496\tx6412\tx7328\tx8244\tx9160\tx10076\tx10992\tx11908\tx12824\tx13740\tx14656\wrapdefault\aspalpha\aspnum\faauto\adjustright\rin0\lin0\itap0\pararsid14553496 \cbpat8 { +\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid15280636 }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 3}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 +\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid15280636 . SUPPORT. +\par ARM is not obligated to support the }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 Deliverables but}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 +\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid15280636 may do so entirely at ARM's discretion. +\par }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 4}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid15280636 . }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 +\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 NO }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid15280636 WARRANT}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 +\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 Y.}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid15280636 +\par YOU AGREE THAT THE }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 DELIVERABLES ARE}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid15280636 + LICENSED "AS IS", AND THAT ARM EXPRESSLY DISCLA +IMS ALL REPRESENTATIONS, WARRANTIES, CONDITIONS OR OTHER TERMS, EXPRESS, IMPLIED OR STATUTORY, INCLUDING WITHOUT LIMITATION THE IMPLIED WARRANTIES OF NON-INFRINGEMENT, SATISFACTORY QUALITY, AND FITNESS FOR A PARTICULAR PURPOSE.}{\rtlch\fcs1 \af1\afs18 +\ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 THE DELIVERABLES MAY CONTAIN ERRORS. }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid14553496 +\par }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 5}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid15280636 . LIMITATION OF LIABILITY. +\par THE MAXIMUM LIABILITY OF ARM TO YOU IN AGGREGATE FOR ALL CLAIMS MADE AGAINST ARM IN CONTRACT}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 ,}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 +\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid15280636 TORT OR OTHERWISE UNDER OR IN CONNECTION WITH THE SUBJECT MATTER OF THIS LICENCE SHALL NOT EXCEED }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 +\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 THE GREATER OF (I) }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid15280636 THE TO +TAL OF SUMS PAID BY YOU TO ARM (IF ANY) FOR THIS LICENCE}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 AND (II) US$10.00}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 +\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid15280636 .}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 + THE LIMITATIONS, EXCLUSIONS AND DISCLAIMERS IN THIS LICENCE SHALL APPLY TO THE MAXIMUM EXTENT ALLOWED BY APPLICABLE LAW. +\par }\pard \ltrpar\qj \li0\ri0\sa200\sl276\slmult1\widctlpar\wrapdefault\aspalpha\aspnum\faauto\adjustright\rin0\lin0\itap0\pararsid14553496 {\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\lang1024\langfe1024\noproof\insrsid14553496 \hich\af1\dbch\af37\loch\f1 6 +}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\lang1024\langfe1024\noproof\insrsid14553496\charrsid13830602 \hich\af1\dbch\af37\loch\f1 . THIRD PARTY RIGHTS.}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid14553496\charrsid13830602 +\par }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\lang1024\langfe1024\noproof\insrsid14553496\charrsid13830602 \hich\af1\dbch\af37\loch\f1 The Separate Files are delivered su\hich\af1\dbch\af37\loch\f1 \hich\f1 +bject to and your use is governed by their own separate licence agreements. This Licence does not apply to such Separate Files and they are not included in the term \'93}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 +\f1\fs18\lang1024\langfe1024\noproof\insrsid14553496 \hich\af1\dbch\af37\loch\f1 Deliverables}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\lang1024\langfe1024\noproof\insrsid14553496\charrsid13830602 \loch\af1\dbch\af37\hich\f1 \'94\loch\f1 + under this Licence. You agree to comply with all terms and conditions impose\hich\af1\dbch\af37\loch\f1 \hich\f1 d on you in respect of such Separate Files including those identified in the Schedule (\'93\loch\f1 \hich\f1 Third Party Terms\'94\loch\f1 +). +\par \hich\af1\dbch\af37\loch\f1 ARM HEREBY DISCLAIMS ANY AND ALL WARRANTIES EXPRESS OR IMPLIED FROM ANY THIRD PARTIES REGARDING ANY SEPARATE FILES, ANY THIRD PARTY MATERIALS INC\hich\af1\dbch\af37\loch\f1 \hich\f1 +LUDED IN THE SOFTWARE, ANY THIRD PARTY MATERIALS FROM WHICH THE SOFTWARE IS DERIVED (COLLECTIVELY \'93\loch\f1 \hich\f1 OTHER CODE\'94\loch\f1 +), AND THE USE OF ANY OR ALL THE OTHER CODE IN CONNECTION WITH THE SOFTWARE, INCLUDING (WITHOUT LIMITATION) ANY WARRANTIES OF SATISFACTORY QUALIT\hich\af1\dbch\af37\loch\f1 Y\hich\af1\dbch\af37\loch\f1 OR FITNESS FOR A PARTICULAR PURPOSE. +\par \hich\af1\dbch\af37\loch\f1 NO THIRD PARTY LICENSORS OF OTHER CODE SHALL HAVE ANY LIABILITY FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING WITHOUT LIMITATION LOST PROFITS), HOWEVER CAUSED AND WHETHER +\hich\af1\dbch\af37\loch\f1 + MADE UNDER CONTRACT, TORT OR OTHER LEGAL THEORY, ARISING IN ANY WAY OUT OF THE USE OR DISTRIBUTION OF THE OTHER CODE OR THE EXERCISE OF ANY RIGHTS GRANTED UNDER EITHER OR BOTH THIS LICENCE AND THE LEGAL TERMS APPLICABLE TO ANY SEPARATE FILES, EVEN IF ADV +\hich\af1\dbch\af37\loch\f1 I\hich\af1\dbch\af37\loch\f1 SED OF THE POSSIBILITY OF SUCH DAMAGES. +\par }\pard \ltrpar\qj \li0\ri0\sa240\widctlpar\tx916\tx1832\tx2748\tx3664\tx4580\tx5496\tx6412\tx7328\tx8244\tx9160\tx10076\tx10992\tx11908\tx12824\tx13740\tx14656\wrapdefault\aspalpha\aspnum\faauto\adjustright\rin0\lin0\itap0\pararsid14553496 \cbpat8 { +\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 7}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid15280636 . U.S. GOVERNMENT END USERS. +\par US Government Restrictions: Use, duplication, reproduction, release, modification, disclosure or transfer of this commercial product and accompanying documentation is restricted in accordance with the terms of this Licence. +\par }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 8}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid15280636 . TERM AND TERMINATION. +\par }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 8.1 }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid15280636 +This Licence shall remain in force until terminated }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 in accordance with the terms of Clause 8.2 or Clause 8.3 below}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 +\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid15280636 . }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 +\par 8.2 }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid15280636 Without prejudice to any of its other rights if you are in breach of + any of the terms and conditions of this Licence then ARM may terminate this Licence immediately upon giving written notice to you}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid7630822 +. You may terminate this Licence at any time. }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 +\par }\pard \ltrpar\qj \li0\ri0\sa200\sl276\slmult1\widctlpar\wrapdefault\aspalpha\aspnum\faauto\adjustright\rin0\lin0\itap0\pararsid14553496 {\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid14553496\charrsid7106724 \hich\af1\dbch\af37\loch\f1 +8.3 This Licence shall immediately terminate and shall be unavailable to you i\hich\af1\dbch\af37\loch\f1 +f you or any party affiliated to you asserts any patents against ARM, ARM affiliates, third parties who have a valid licence from ARM for the Deliverables, or any customers or distributors of any of them based upon a claim that your (or your affiliate) pa +\hich\af1\dbch\af37\loch\f1 t\hich\af1\dbch\af37\loch\f1 ent is Necessary to implement the }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid14553496 \hich\af1\dbch\af37\loch\f1 Deliverables}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 +\f1\fs18\insrsid14553496\charrsid7106724 \hich\af1\dbch\af37\loch\f1 . In this Licence}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid14553496 \hich\af1\dbch\af37\loch\f1 :}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid14553496\charrsid7106724 +\hich\af1\dbch\af37\loch\f1 (i) "affiliate" means any entity controlling, controlled by or under common control with a party (in fact or in law, via voting securities, management control or otherwise) and "affiliated" s\hich\af1\dbch\af37\loch\f1 +hall be construed accordingly; (ii) "assert" means to allege infringement in legal or administrative proceedings, or proceedings before any other competent trade, arbitral or international authority; }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 +\f1\fs18\insrsid14553496 \hich\af1\dbch\af37\loch\f1 and }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid14553496\charrsid7106724 \hich\af1\dbch\af37\loch\f1 \hich\f1 (iii) \'93\loch\f1 \hich\f1 Necessary\'94\loch\f1 + means with respect to any claims o\hich\af1\dbch\af37\loch\f1 f any patent, those claims which, without the appropriate permission of the patent owner, will be infringed when implementing the }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid14553496 +\hich\af1\dbch\af37\loch\f1 Deliverables }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid14553496\charrsid7106724 \hich\af1\dbch\af37\loch\f1 because no alternative, commercially reasonable, non-infringing way of implementing the }{\rtlch\fcs1 +\af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid14553496 \hich\af1\dbch\af37\loch\f1 Deliverables }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid14553496\charrsid7106724 \hich\af1\dbch\af37\loch\f1 is known.}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 +\f1\fs18\insrsid14553496\charrsid5900444 \hich\af1\dbch\af37\loch\f1 }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid14553496 +\par }\pard \ltrpar\qj \li0\ri0\sa240\widctlpar\tx916\tx1832\tx2748\tx3664\tx4580\tx5496\tx6412\tx7328\tx8244\tx9160\tx10076\tx10992\tx11908\tx12824\tx13740\tx14656\wrapdefault\aspalpha\aspnum\faauto\adjustright\rin0\lin0\itap0\pararsid14553496 \cbpat8 { +\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 8.4 }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid7630822 Upon termination of this Licence,}{ +\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid15280636 you shall stop }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid15098396 +using the }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 Deliverables}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid15098396 + and destroy all copies of the }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 Deliverables}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 +\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid15098396 in your possession. The provisions of clauses 5, 6, 7, 8 and 9 shall survive termination of this Licence.}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 +\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid15280636 +\par }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 9}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid15280636 . GENERAL. +\par This Licence is governed by English Law. Except where ARM agrees otherwise in a written contract signed by you and ARM, this is the only agreement between you and ARM relating to the }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 +\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 Deliverables}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid15280636 + and it may only be modified by written agreement between you and ARM. Except a +s expressly agreed in writing, this Licence may not be modified by purchase orders, advertising or other representation by any person. If any clause or sentence in this Licence is held by a court of law to be illegal or unenforceable the remaining provisi +o +ns of this Licence shall not be affected thereby. The failure by ARM to enforce any of the provisions of this Licence, unless waived in writing, shall not constitute a waiver of ARM's rights to enforce such provision or any other provision of this Licence + in the future.}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 This Licence may not be assigned without the prior written consent of ARM. +\par }\pard \ltrpar\qc \li0\ri0\sa240\widctlpar\tx916\tx1832\tx2748\tx3664\tx4580\tx5496\tx6412\tx7328\tx8244\tx9160\tx10076\tx10992\tx11908\tx12824\tx13740\tx14656\wrapdefault\aspalpha\aspnum\faauto\adjustright\rin0\lin0\itap0\pararsid14553496 \cbpat8 { +\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 \page SCHEDULE +\par }\pard \ltrpar\qj \li0\ri0\sa240\widctlpar\tx916\tx1832\tx2748\tx3664\tx4580\tx5496\tx6412\tx7328\tx8244\tx9160\tx10076\tx10992\tx11908\tx12824\tx13740\tx14656\wrapdefault\aspalpha\aspnum\faauto\adjustright\rin0\lin0\itap0\pararsid14553496 \cbpat8 { +\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 Separate Files +\par }\pard \ltrpar\qj \li0\ri0\sa200\sl276\slmult1\widctlpar\wrapdefault\aspalpha\aspnum\faauto\adjustright\rin0\lin0\itap0\pararsid14553496 {\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 The }{\rtlch\fcs1 +\af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid15098396 package }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 also }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 +\f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid15098396 includes the components}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 contained in the following directories}{\rtlch\fcs1 +\af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid15098396 :}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 +\par {\listtext\pard\plain\ltrpar \rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\insrsid14553496 \hich\af1\dbch\af0\loch\f1 (a)\tab}}\pard \ltrpar +\qj \fi-360\li720\ri0\widctlpar\wrapdefault\aspalpha\aspnum\faauto\ls16\adjustright\rin0\lin720\itap0\pararsid14553496 {\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 ./}{\rtlch\fcs1 \af1\afs18 +\ltrch\fcs0 \f1\fs18\insrsid14553496\charrsid7090778 \hich\af1\dbch\af37\loch\f1 CMSIS}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid14553496 \hich\af1\dbch\af37\loch\f1 /}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid14553496\charrsid7090778 +\hich\af1\dbch\af37\loch\f1 DSP_Lib}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid14553496 \hich\af1\dbch\af37\loch\f1 - }{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496\charrsid15098396 +DSP Library sources and examples}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid14553496 \hich\af1\dbch\af37\loch\f1 ; +\par {\listtext\pard\plain\ltrpar \rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\insrsid14553496 \hich\af1\dbch\af0\loch\f1 (b)\tab}}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\cf1\lang2057\langfe2057\langfenp2057\insrsid14553496 ./}{\rtlch\fcs1 \af1\afs18 +\ltrch\fcs0 \f1\fs18\insrsid14553496\charrsid7090778 \hich\af1\dbch\af37\loch\f1 CMS\hich\af1\dbch\af37\loch\f1 IS}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid14553496 \hich\af1\dbch\af37\loch\f1 /}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 +\f1\fs18\insrsid14553496\charrsid7090778 \hich\af1\dbch\af37\loch\f1 Include}{\rtlch\fcs1 \af1\afs18 \ltrch\fcs0 \f1\fs18\insrsid14553496 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