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Update of configuration and projectfiles to support new library folder structure
author Ideenmodellierer
date Sun, 17 Feb 2019 21:29:38 +0100
parents 5f11787b4f42
children bc6c90e20d9e
comparison
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130:b7689d9e888a 131:f35e53ef04e0
53 #define STM32F4xx_HAL_CONF_H 53 #define STM32F4xx_HAL_CONF_H
54 54
55 /* Exported constants --------------------------------------------------------*/ 55 /* Exported constants --------------------------------------------------------*/
56 56
57 /* ######################### Hardware Selection ############################## */ 57 /* ######################### Hardware Selection ############################## */
58 #define STM32F429xx 58 /* #define STM32F429xx definition is now done in preprocessor*/
59 59
60 /* ########################## Module Selection ############################## */ 60 /* ########################## Module Selection ############################## */
61 /** 61 /**
62 * @brief This is the list of modules to be used in the HAL driver 62 * @brief This is the list of modules to be used in the HAL driver
63 */ 63 */
105 * @brief Adjust the value of External High Speed oscillator (HSE) used in your application. 105 * @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
106 * This value is used by the RCC HAL module to compute the system frequency 106 * This value is used by the RCC HAL module to compute the system frequency
107 * (when HSE is used as system clock source, directly or through the PLL). 107 * (when HSE is used as system clock source, directly or through the PLL).
108 */ 108 */
109 #if !defined (HSE_VALUE) 109 #if !defined (HSE_VALUE)
110 #define HSE_VALUE ((uint32_t)8000000) /*!< Value of the External oscillator in Hz */ 110 #define HSE_VALUE ((uint32_t)8000000U) /*!< Value of the External oscillator in Hz */
111 #endif /* HSE_VALUE */ 111 #endif /* HSE_VALUE */
112 112
113 #if !defined (HSE_STARTUP_TIMEOUT) 113 #if !defined (HSE_STARTUP_TIMEOUT)
114 #define HSE_STARTUP_TIMEOUT ((uint32_t)5000) /*!< Time out for HSE start up, in ms */ 114 #define HSE_STARTUP_TIMEOUT ((uint32_t)5000U) /*!< Time out for HSE start up, in ms */
115 #endif /* HSE_STARTUP_TIMEOUT */ 115 #endif /* HSE_STARTUP_TIMEOUT */
116 116
117 /** 117 /**
118 * @brief Internal High Speed oscillator (HSI) value. 118 * @brief Internal High Speed oscillator (HSI) value.
119 * This value is used by the RCC HAL module to compute the system frequency 119 * This value is used by the RCC HAL module to compute the system frequency
120 * (when HSI is used as system clock source, directly or through the PLL). 120 * (when HSI is used as system clock source, directly or through the PLL).
121 */ 121 */
122 #if !defined (HSI_VALUE) 122 #if !defined (HSI_VALUE)
123 #define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/ 123 #define HSI_VALUE ((uint32_t)16000000U) /*!< Value of the Internal oscillator in Hz*/
124 #endif /* HSI_VALUE */ 124 #endif /* HSI_VALUE */
125 125
126 /** 126 /**
127 * @brief Internal Low Speed oscillator (LSI) value. 127 * @brief Internal Low Speed oscillator (LSI) value.
128 */ 128 */
129 #if !defined (LSI_VALUE) 129 #if !defined (LSI_VALUE)
130 #define LSI_VALUE ((uint32_t)40000) 130 #define LSI_VALUE ((uint32_t)40000U)
131 #endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz 131 #endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz
132 The real value may vary depending on the variations 132 The real value may vary depending on the variations
133 in voltage and temperature. */ 133 in voltage and temperature. */
134 /** 134 /**
135 * @brief External Low Speed oscillator (LSE) value. 135 * @brief External Low Speed oscillator (LSE) value.
136 */ 136 */
137 #if !defined (LSE_VALUE) 137 #if !defined (LSE_VALUE)
138 #define LSE_VALUE ((uint32_t)32768) /*!< Value of the External Low Speed oscillator in Hz */ 138 #define LSE_VALUE ((uint32_t)32768) /*!< Value of the External Low Speed oscillator in Hz */
139 #endif /* LSE_VALUE */ 139 #endif /* LSE_VALUE */
140 140
141 #if !defined (LSE_STARTUP_TIMEOUT)
142 #define LSE_STARTUP_TIMEOUT 5000U /*!< Time out for LSE start up, in ms */
143 #endif /* LSE_STARTUP_TIMEOUT */
144
141 /** 145 /**
142 * @brief External clock source for I2S peripheral 146 * @brief External clock source for I2S peripheral
143 * This value is used by the I2S HAL module to compute the I2S clock source 147 * This value is used by the I2S HAL module to compute the I2S clock source
144 * frequency, this source is inserted directly through I2S_CKIN pad. 148 * frequency, this source is inserted directly through I2S_CKIN pad.
145 */ 149 */
146 #if !defined (EXTERNAL_CLOCK_VALUE) 150 #if !defined (EXTERNAL_CLOCK_VALUE)
147 #define EXTERNAL_CLOCK_VALUE ((uint32_t)12288000) /*!< Value of the External audio frequency in Hz*/ 151 #define EXTERNAL_CLOCK_VALUE ((uint32_t)12288000U) /*!< Value of the External audio frequency in Hz*/
148 #endif /* EXTERNAL_CLOCK_VALUE */ 152 #endif /* EXTERNAL_CLOCK_VALUE */
149 153
150 /* Tip: To avoid modifying this file each time you need to use different HSE, 154 /* Tip: To avoid modifying this file each time you need to use different HSE,
151 === you can define the HSE value in your toolchain compiler preprocessor. */ 155 === you can define the HSE value in your toolchain compiler preprocessor. */
152 156
153 /* ########################### System Configuration ######################### */ 157 /* ########################### System Configuration ######################### */
154 /** 158 /**
155 * @brief This is the HAL system configuration section 159 * @brief This is the HAL system configuration section
156 */ 160 */
157 161
158 #define VDD_VALUE ((uint32_t)3300) /*!< Value of VDD in mv */ 162 #define VDD_VALUE ((uint32_t)3300U) /*!< Value of VDD in mv */
159 #define TICK_INT_PRIORITY ((uint32_t)0) /*!< tick interrupt priority */ 163 #define TICK_INT_PRIORITY ((uint32_t)0) /*!< tick interrupt priority */
160 #define USE_RTOS 0 164 #define USE_RTOS 0
161 #define PREFETCH_ENABLE 1 165 #define PREFETCH_ENABLE 1
162 #define INSTRUCTION_CACHE_ENABLE 1 166 #define INSTRUCTION_CACHE_ENABLE 1
163 #define DATA_CACHE_ENABLE 1 167 #define DATA_CACHE_ENABLE 1
172 /* ################## Ethernet peripheral configuration ##################### */ 176 /* ################## Ethernet peripheral configuration ##################### */
173 177
174 /* Section 1 : Ethernet peripheral configuration */ 178 /* Section 1 : Ethernet peripheral configuration */
175 179
176 /* MAC ADDRESS: MAC_ADDR0:MAC_ADDR1:MAC_ADDR2:MAC_ADDR3:MAC_ADDR4:MAC_ADDR5 */ 180 /* MAC ADDRESS: MAC_ADDR0:MAC_ADDR1:MAC_ADDR2:MAC_ADDR3:MAC_ADDR4:MAC_ADDR5 */
177 #define MAC_ADDR0 2 181 #define MAC_ADDR0 2U
178 #define MAC_ADDR1 0 182 #define MAC_ADDR1 0U
179 #define MAC_ADDR2 0 183 #define MAC_ADDR2 0U
180 #define MAC_ADDR3 0 184 #define MAC_ADDR3 0U
181 #define MAC_ADDR4 0 185 #define MAC_ADDR4 0U
182 #define MAC_ADDR5 0 186 #define MAC_ADDR5 0U
183 187
184 /* Definition of the Ethernet driver buffers size and count */ 188 /* Definition of the Ethernet driver buffers size and count */
185 #define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for receive */ 189 #define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for receive */
186 #define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for transmit */ 190 #define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for transmit */
187 #define ETH_RXBUFNB ((uint32_t)4) /* 4 Rx buffers of size ETH_RX_BUF_SIZE */ 191 #define ETH_RXBUFNB ((uint32_t)4) /* 4 Rx buffers of size ETH_RX_BUF_SIZE */
188 #define ETH_TXBUFNB ((uint32_t)4) /* 4 Tx buffers of size ETH_TX_BUF_SIZE */ 192 #define ETH_TXBUFNB ((uint32_t)4) /* 4 Tx buffers of size ETH_TX_BUF_SIZE */
189 193
190 /* Section 2: PHY configuration section */ 194 /* Section 2: PHY configuration section */
191 195
192 /* DP83848 PHY Address*/ 196 /* DP83848 PHY Address*/
193 #define DP83848_PHY_ADDRESS 0x01 197 #define DP83848_PHY_ADDRESS 0x01U
194 /* PHY Reset delay these values are based on a 1 ms Systick interrupt*/ 198 /* PHY Reset delay these values are based on a 1 ms Systick interrupt*/
195 #define PHY_RESET_DELAY ((uint32_t)0x000000FF) 199 #define PHY_RESET_DELAY ((uint32_t)0x000000FFU)
196 /* PHY Configuration delay */ 200 /* PHY Configuration delay */
197 #define PHY_CONFIG_DELAY ((uint32_t)0x00000FFF) 201 #define PHY_CONFIG_DELAY ((uint32_t)0x00000FFFU)
198 202
199 #define PHY_READ_TO ((uint32_t)0x0000FFFF) 203 #define PHY_READ_TO ((uint32_t)0x0000FFFFU)
200 #define PHY_WRITE_TO ((uint32_t)0x0000FFFF) 204 #define PHY_WRITE_TO ((uint32_t)0x0000FFFFU)
201 205
202 /* Section 3: Common PHY Registers */ 206 /* Section 3: Common PHY Registers */
203 207
204 #define PHY_BCR ((uint16_t)0x00) /*!< Transceiver Basic Control Register */ 208 #define PHY_BCR ((uint16_t)0x0000) /*!< Transceiver Basic Control Register */
205 #define PHY_BSR ((uint16_t)0x01) /*!< Transceiver Basic Status Register */ 209 #define PHY_BSR ((uint16_t)0x0001) /*!< Transceiver Basic Status Register */
206 210
207 #define PHY_RESET ((uint16_t)0x8000) /*!< PHY Reset */ 211 #define PHY_RESET ((uint16_t)0x8000) /*!< PHY Reset */
208 #define PHY_LOOPBACK ((uint16_t)0x4000) /*!< Select loop-back mode */ 212 #define PHY_LOOPBACK ((uint16_t)0x4000) /*!< Select loop-back mode */
209 #define PHY_FULLDUPLEX_100M ((uint16_t)0x2100) /*!< Set the full-duplex mode at 100 Mb/s */ 213 #define PHY_FULLDUPLEX_100M ((uint16_t)0x2100) /*!< Set the full-duplex mode at 100 Mb/s */
210 #define PHY_HALFDUPLEX_100M ((uint16_t)0x2000) /*!< Set the half-duplex mode at 100 Mb/s */ 214 #define PHY_HALFDUPLEX_100M ((uint16_t)0x2000) /*!< Set the half-duplex mode at 100 Mb/s */
219 #define PHY_LINKED_STATUS ((uint16_t)0x0004) /*!< Valid link established */ 223 #define PHY_LINKED_STATUS ((uint16_t)0x0004) /*!< Valid link established */
220 #define PHY_JABBER_DETECTION ((uint16_t)0x0002) /*!< Jabber condition detected */ 224 #define PHY_JABBER_DETECTION ((uint16_t)0x0002) /*!< Jabber condition detected */
221 225
222 /* Section 4: Extended PHY Registers */ 226 /* Section 4: Extended PHY Registers */
223 227
224 #define PHY_SR ((uint16_t)0x10) /*!< PHY status register Offset */ 228 #define PHY_SR ((uint16_t)0x0010) /*!< PHY status register Offset */
225 #define PHY_MICR ((uint16_t)0x11) /*!< MII Interrupt Control Register */ 229 #define PHY_MICR ((uint16_t)0x0011) /*!< MII Interrupt Control Register */
226 #define PHY_MISR ((uint16_t)0x12) /*!< MII Interrupt Status and Misc. Control Register */ 230 #define PHY_MISR ((uint16_t)0x0012) /*!< MII Interrupt Status and Misc. Control Register */
227 231
228 #define PHY_LINK_STATUS ((uint16_t)0x0001) /*!< PHY Link mask */ 232 #define PHY_LINK_STATUS ((uint16_t)0x0001) /*!< PHY Link mask */
229 #define PHY_SPEED_STATUS ((uint16_t)0x0002) /*!< PHY Speed mask */ 233 #define PHY_SPEED_STATUS ((uint16_t)0x0002) /*!< PHY Speed mask */
230 #define PHY_DUPLEX_STATUS ((uint16_t)0x0004) /*!< PHY Duplex mask */ 234 #define PHY_DUPLEX_STATUS ((uint16_t)0x0004) /*!< PHY Duplex mask */
231 235