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ADD GPL License ...
author jDG
date Tue, 23 Jan 2018 17:29:40 +0100
parents 97eafbcb81a9
children 7801c5d8a562
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29:3a98f9e7ca58 30:ea1003f63e44
1 ///////////////////////////////////////////////////////////////////////////////
2 /// -*- coding: UTF-8 -*-
3 ///
4 /// \file BootLoader/Src/base_bootlader.c
5 /// \brief he beginning of it all. main() is part of this.
6 /// \author heinrichs/weikamp, Christian Weikamp
7 /// \date 26-February-2014
8 ///
9 /// $Id$
10 ///////////////////////////////////////////////////////////////////////////////
11 /// \par Copyright (c) 2014-2018 Heinrichs Weikamp gmbh
12 ///
13 /// This program is free software: you can redistribute it and/or modify
14 /// it under the terms of the GNU General Public License as published by
15 /// the Free Software Foundation, either version 3 of the License, or
16 /// (at your option) any later version.
17 ///
18 /// This program is distributed in the hope that it will be useful,
19 /// but WITHOUT ANY WARRANTY; without even the implied warranty of
20 /// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 /// GNU General Public License for more details.
22 ///
23 /// You should have received a copy of the GNU General Public License
24 /// along with this program. If not, see <http://www.gnu.org/licenses/>.
25 //////////////////////////////////////////////////////////////////////////////
1 /** 26 /**
2 ****************************************************************************** 27 * @detail The beginning of it all. main() is part of this.
3 * @copyright heinrichs weikamp
4 * @file base_bootlader.c
5 * @author heinrichs/weikamp, Christian Weikamp
6 * @date 26-February-2014
7 * @version V1.0.4
8 * @since 09-Jan-2016
9 * @brief The beginning of it all. main() is part of this.
10 * + Do the inits for hardware 28 * + Do the inits for hardware
11 * + check for button press or update process reset trigger 29 * + check for button press or update process reset trigger
12 * + Do the inits for sub-systems like menu, dive screen etc. 30 * + Do the inits for sub-systems like menu, dive screen etc.
13 * + Start IRQs 31 * + Start IRQs
14 * + Start MainTasks not in IRQs 32 * + Start MainTasks not in IRQs
15 * @bug 33 * @bug
16 * @warning 34 * @warning
17 @verbatim 35 @verbatim
18 36
19 ============================================================================== 37 ==============================================================================
20 ##### bootloader specific ##### 38 ##### bootloader specific #####
21 ============================================================================== 39 ==============================================================================
22 40
23 151130 chsw sleep on button3 41 151130 chsw sleep on button3
24 (MX_tell_reset_logik_alles_ok() + DataEX_call() in endlos loop) 42 (MX_tell_reset_logik_alles_ok() + DataEX_call() in endlos loop)
25 43
26 ============================================================================== 44 ==============================================================================
27 ##### bootloader specific ##### 45 ##### bootloader specific #####
28 ============================================================================== 46 ==============================================================================
29 47
30 Bootloader info is set right here in this file. 48 Bootloader info is set right here in this file.
31 The location is 0x0800A000 instead of 0x08050000 (firmware) 49 The location is 0x0800A000 instead of 0x08050000 (firmware)
32 50
33 on system reset (Menu Start Bootloader in firmware) the update process 51 on system reset (Menu Start Bootloader in firmware) the update process
34 is started automatically if no button is pressed 52 is started automatically if no button is pressed
35 53
36 if the right button is pressed the bootloader menu is started 54 if the right button is pressed the bootloader menu is started
37 55
38 after update process (with update or empty) cleaning of EEPROM is started 56 after update process (with update or empty) cleaning of EEPROM is started
39 afterwards the watchdog reset starts without activating the update process 57 afterwards the watchdog reset starts without activating the update process
40 58
41 bluetooth chip is started in tComm on start of the mini bootloader firmware 59 bluetooth chip is started in tComm on start of the mini bootloader firmware
42 60
43 SMALLCPU_CSB_PIN must be re-set to 0 to communicate with small CPU / CPU2 / RTE 61 SMALLCPU_CSB_PIN must be re-set to 0 to communicate with small CPU / CPU2 / RTE
44 62
45 for RealTerm to send file / firmware, Delays has to be increased to 0 63 for RealTerm to send file / firmware, Delays has to be increased to 0
46 64
47 RTE update / SPI1 with DMA gave IBUSERR, now it is working fine :-) 150828 65 RTE update / SPI1 with DMA gave IBUSERR, now it is working fine :-) 150828
48 ============================================================================== 66 ==============================================================================
49 from standard firmware, parts might be invalid here: 67 from standard firmware, parts might be invalid here:
50 ============================================================================== 68 ==============================================================================
51 ##### IRQs ##### 69 ##### IRQs #####
52 ============================================================================== 70 ==============================================================================
53 [..] The IRQs are very important and most functions should only run there. 71 [..] The IRQs are very important and most functions should only run there.
54 72
55 PreemptPriority are as follows 73 PreemptPriority are as follows
56 (#) 2 (low) sprintf _only_ here. Don't use in maintask or anywhere else. 74 (#) 2 (low) sprintf _only_ here. Don't use in maintask or anywhere else.
57 Called by Buttons und Timer3 75 Called by Buttons und Timer3
58 Timer3 is 1/10 second 76 Timer3 is 1/10 second
66 Three levelAmbients are available (2 low,1 mid,0 high) 84 Three levelAmbients are available (2 low,1 mid,0 high)
67 85
68 The STM32F4 has 4bits for IRQ levelAmbients, divided 2/2 in this code 86 The STM32F4 has 4bits for IRQ levelAmbients, divided 2/2 in this code
69 with the NVIC_PRIORITYGROUP_2 setting. 87 with the NVIC_PRIORITYGROUP_2 setting.
70 88
71 ============================================================================== 89 ==============================================================================
72 ##### MainTask ##### 90 ##### MainTask #####
73 ============================================================================== 91 ==============================================================================
74 [..] For everthing slow without importance to be 'in time'. 92 [..] For everthing slow without importance to be 'in time'.
75 Like VPM and Buehlmann. 93 Like VPM and Buehlmann.
76 No sprintf and probably no GFX_SetFramesTopBottom() stuff neither. 94 No sprintf and probably no GFX_SetFramesTopBottom() stuff neither.
77 If sprintf is called while sprintf is executed it blows up everything. 95 If sprintf is called while sprintf is executed it blows up everything.
78 96
79 ============================================================================== 97 ==============================================================================
80 ##### Frames / the external SDRAM ##### 98 ##### Frames / the external SDRAM #####
81 ============================================================================== 99 ==============================================================================
82 [..] The SDRAM is handled by getFrame() and releaseFrame(). 100 [..] The SDRAM is handled by getFrame() and releaseFrame().
83 Each frame with 800*480*2 Bytes. 101 Each frame with 800*480*2 Bytes.
84 Be carefull to release every frame 102 Be carefull to release every frame
85 otherwise there will be a memory leakage over time. 103 otherwise there will be a memory leakage over time.
86 housekeepingFrame() in the MainTask takes care of cleaning the frames. 104 housekeepingFrame() in the MainTask takes care of cleaning the frames.
87 All frames are filled with 0x00. This will be transparent with color of 105 All frames are filled with 0x00. This will be transparent with color of
88 CLUT_Font020 (is CLUT 0) if the alpha is set for a 16bit pair. 106 CLUT_Font020 (is CLUT 0) if the alpha is set for a 16bit pair.
89 housekeepingFrame() delays the cleaning of frames still used as screen 107 housekeepingFrame() delays the cleaning of frames still used as screen
90 buffer to prevent flickering. 108 buffer to prevent flickering.
91 109
92 ============================================================================== 110 ==============================================================================
93 ##### Display ##### 111 ##### Display #####
94 ============================================================================== 112 ==============================================================================
95 [..] There is a Top layer, Bottom layer and background color. 113 [..] There is a Top layer, Bottom layer and background color.
96 All are perfectly alpha-blended by hardware. 114 All are perfectly alpha-blended by hardware.
97 115
98 (#) top layer has 800x480 option function calls only 116 (#) top layer has 800x480 option function calls only
99 as it is not used for cursors here 117 as it is not used for cursors here
100 (#) bottom layer has free size and start option to be used 118 (#) bottom layer has free size and start option to be used
132 see GFX_write_string() to get an overview of the controls 150 see GFX_write_string() to get an overview of the controls
133 as well as the command list in gfx_engine.h 151 as well as the command list in gfx_engine.h
134 There is no clear before writing, text overlay is always on. 152 There is no clear before writing, text overlay is always on.
135 Many options to have LargeFont.SmallFont for numbers etc. 153 Many options to have LargeFont.SmallFont for numbers etc.
136 154
137 ============================================================================== 155 ==============================================================================
138 ##### Update, DualBoot and build-in FLASH memory usage ##### 156 ##### Update, DualBoot and build-in FLASH memory usage #####
139 ============================================================================== 157 ==============================================================================
140 [..] Boot0 pin, Boot1/PB2 pin and BFB2 software bit control the behaviour. 158 [..] Boot0 pin, Boot1/PB2 pin and BFB2 software bit control the behaviour.
141 PB2 should be tied to GND. 159 PB2 should be tied to GND.
142 Boot0 == VDD -> bootloader on start, otherwise boot from Bank1 or Bank2 160 Boot0 == VDD -> bootloader on start, otherwise boot from Bank1 or Bank2
143 depending on BFB2. 161 depending on BFB2.
144 Bank2 contains the Fonts and should contain a proper test code in future 162 Bank2 contains the Fonts and should contain a proper test code in future
145 Bank1 is the main code (Bank1 is 1 MB too, usage as of Oct. 14 is 200 KB) 163 Bank1 is the main code (Bank1 is 1 MB too, usage as of Oct. 14 is 200 KB)
146 [..] Bootloader should be either UART or USB (on FS pins _only_) 164 [..] Bootloader should be either UART or USB (on FS pins _only_)
147 USB HS to FS like on the Eval board does not work. 165 USB HS to FS like on the Eval board does not work.
148 [..] Bootloader for the smaller CPU2 is implemented via the SPI used for DMA copy. 166 [..] Bootloader for the smaller CPU2 is implemented via the SPI used for DMA copy.
149 167
150 ============================================================================== 168 ==============================================================================
151 ##### Connection to CPU2 (STM32F411 as of Oct.14 ##### 169 ##### Connection to CPU2 (STM32F411 as of Oct.14 #####
152 ============================================================================== 170 ==============================================================================
153 [..] Connected via SPI and DMA for every purpose. 171 [..] Connected via SPI and DMA for every purpose.
154 two entire arrays are transfered for data security reasons 172 two entire arrays are transfered for data security reasons
155 with respect to master (STM32F429) might interrupt internal 173 with respect to master (STM32F429) might interrupt internal
156 data copy in CPU2 (like hi byte, low byte, etc.). 174 data copy in CPU2 (like hi byte, low byte, etc.).
157 [..] The entire life data is calculated in CPU2. Like tissues, CNS,... 175 [..] The entire life data is calculated in CPU2. Like tissues, CNS,...
158 Therefore the main unit is _not_ necessarily a Real Time system. 176 Therefore the main unit is _not_ necessarily a Real Time system.
159 Simulation on the main unit can be executed without disrupting life data. 177 Simulation on the main unit can be executed without disrupting life data.
160 [..] SPI is triggered and timed by calling DataEX_call() in data_exchange_main.c 178 [..] SPI is triggered and timed by calling DataEX_call() in data_exchange_main.c
161 DataEX_copy_to_LifeData() does the transfer from buffer to variables used. 179 DataEX_copy_to_LifeData() does the transfer from buffer to variables used.
162 180
163 ============================================================================== 181 ==============================================================================
164 ##### Menu, MenuEdit, Info ##### 182 ##### Menu, MenuEdit, Info #####
165 ============================================================================== 183 ==============================================================================
166 [..] tMenu.c, tMenuEdit.c and tInfo.c is the system used. 184 [..] tMenu.c, tMenuEdit.c and tInfo.c is the system used.
167 logbook is part of Info not Menu. 185 logbook is part of Info not Menu.
168 The Info Menu is accessed by button 'Back' 186 The Info Menu is accessed by button 'Back'
169 The regular Menu is accessed by button 'Enter' 187 The regular Menu is accessed by button 'Enter'
170 [..] Menu content is kept in frame memory for fast access. 188 [..] Menu content is kept in frame memory for fast access.
171 There is no need to build pages if the 'Enter' button is pressed. 189 There is no need to build pages if the 'Enter' button is pressed.
173 [..] Button control for new pages (and pages in general) have to implemented 191 [..] Button control for new pages (and pages in general) have to implemented
174 in tMenu.c, tMenuEdit.c or tInfo.c 192 in tMenu.c, tMenuEdit.c or tInfo.c
175 193
176 [..] ToDo (Oct. 14) Timeout for menus via Timer3 / IRQ 2 194 [..] ToDo (Oct. 14) Timeout for menus via Timer3 / IRQ 2
177 195
178 ============================================================================== 196 ==============================================================================
179 ##### specials ##### 197 ##### specials #####
180 ============================================================================== 198 ==============================================================================
181 [..] There was code for vector graphics from great demos 199 [..] There was code for vector graphics from great demos
182 (peridiummmm and jupiter) that can be fitted again 200 (peridiummmm and jupiter) that can be fitted again
183 201
184 @endverbatim 202 @endverbatim
185 ****************************************************************************** 203 ******************************************************************************
186 * @attention 204 */
187 *
188 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
189 *
190 ******************************************************************************
191 */
192 205
193 /* Includes ------------------------------------------------------------------*/ 206 /* Includes ------------------------------------------------------------------*/
194 #include "base_bootloader.h" 207 #include "base_bootloader.h"
195 208
196 // From Bootloader/Inc: 209 // From Bootloader/Inc:
220 233
221 // From AC6 support: 234 // From AC6 support:
222 #include <stdio.h> 235 #include <stdio.h>
223 #include <string.h> // for memcopy 236 #include <string.h> // for memcopy
224 237
225 /** @addtogroup OSTC 4
226 * @{
227 */
228
229 /* Private typedef -----------------------------------------------------------*/
230 /* Private define ------------------------------------------------------------*/ 238 /* Private define ------------------------------------------------------------*/
231 #define BUFFER_SIZE ((uint32_t)0x00177000) 239 #define BUFFER_SIZE ((uint32_t)0x00177000)
232 #define WRITE_READ_ADDR ((uint32_t)0x0000) 240 #define WRITE_READ_ADDR ((uint32_t)0x0000)
233 #define REFRESH_COUNT ((uint32_t)0x0569) /* SDRAM refresh counter (90Mhz SD clock) */ 241 #define REFRESH_COUNT ((uint32_t)0x0569) /* SDRAM refresh counter (90Mhz SD clock) */
234 242
236 /* Private variables ---------------------------------------------------------*/ 244 /* Private variables ---------------------------------------------------------*/
237 uint8_t returnFromCommCleanUpRequest = 0; 245 uint8_t returnFromCommCleanUpRequest = 0;
238 246
239 const SFirmwareData bootloader_FirmwareData __attribute__(( section(".bootloader_firmware_data") )) = 247 const SFirmwareData bootloader_FirmwareData __attribute__(( section(".bootloader_firmware_data") )) =
240 { 248 {
241 .versionFirst = 1, 249 .versionFirst = 1,
242 .versionSecond = 0, 250 .versionSecond = 0,
243 .versionThird = 1, 251 .versionThird = 1,
244 .versionBeta = 1, 252 .versionBeta = 1,
245 253
246 /* 4 bytes with trailing 0 */ 254 /* 4 bytes with trailing 0 */
247 .signature = "cw", 255 .signature = "cw",
248 256
249 .release_year = 16, 257 .release_year = 16,
250 .release_month = 4, 258 .release_month = 4,
251 .release_day = 8, 259 .release_day = 8,
252 .release_sub = 0, 260 .release_sub = 0,
253 261
254 /* max 48 with trailing 0 */ 262 /* max 48 with trailing 0 */
255 .release_info ="tComm with all", 263 .release_info ="tComm with all",
256 264
257 /* for safety reasons and coming functions*/ 265 /* for safety reasons and coming functions*/
258 .magic[0] = FIRMWARE_MAGIC_FIRST, 266 .magic[0] = FIRMWARE_MAGIC_FIRST,
259 .magic[1] = FIRMWARE_MAGIC_SECOND, 267 .magic[1] = FIRMWARE_MAGIC_SECOND,
260 .magic[2] = FIRMWARE_MAGIC_FIRMWARE, /* the magic byte */ 268 .magic[2] = FIRMWARE_MAGIC_FIRMWARE, /* the magic byte */
261 .magic[3] = FIRMWARE_MAGIC_END 269 .magic[3] = FIRMWARE_MAGIC_END
350 struct __FILE { int handle; }; 358 struct __FILE { int handle; };
351 FILE __stdout; 359 FILE __stdout;
352 FILE __stdin; 360 FILE __stdin;
353 361
354 int fputc(int ch, FILE *f) { 362 int fputc(int ch, FILE *f) {
355 if (DEMCR & TRCENA) { 363 if (DEMCR & TRCENA) {
356 while (ITM_Port32(0) == 0); 364 while (ITM_Port32(0) == 0);
357 ITM_Port8(0) = ch; 365 ITM_Port8(0) = ch;
358 } 366 }
359 return(ch); 367 return(ch);
360 } 368 }
361 */ 369 */
362 370
363 /* Private functions ---------------------------------------------------------*/ 371 /* Private functions ---------------------------------------------------------*/
364 372
365 /** 373 /**
366 * @brief Main program 374 * @brief Main program
367 * @param None 375 * @param None
368 * @retval None 376 * @retval None
369 */ 377 */
370 378
371 void GPIO_test_I2C_lines(void) 379 void GPIO_test_I2C_lines(void)
372 { 380 {
373 GPIO_InitTypeDef GPIO_InitStructure; 381 GPIO_InitTypeDef GPIO_InitStructure;
374 __GPIOA_CLK_ENABLE(); 382 __GPIOA_CLK_ENABLE();
375 __GPIOG_CLK_ENABLE(); 383 __GPIOG_CLK_ENABLE();
376 GPIO_InitStructure.Pin = GPIO_PIN_7; 384 GPIO_InitStructure.Pin = GPIO_PIN_7;
377 GPIO_InitStructure.Mode = GPIO_MODE_OUTPUT_PP; 385 GPIO_InitStructure.Mode = GPIO_MODE_OUTPUT_PP;
378 GPIO_InitStructure.Pull = GPIO_PULLUP; 386 GPIO_InitStructure.Pull = GPIO_PULLUP;
379 GPIO_InitStructure.Speed = GPIO_SPEED_LOW; 387 GPIO_InitStructure.Speed = GPIO_SPEED_LOW;
380 HAL_GPIO_Init(GPIOG, &GPIO_InitStructure); 388 HAL_GPIO_Init(GPIOG, &GPIO_InitStructure);
381 GPIO_InitStructure.Pin = GPIO_PIN_3; 389 GPIO_InitStructure.Pin = GPIO_PIN_3;
382 HAL_GPIO_Init(GPIOA, &GPIO_InitStructure); 390 HAL_GPIO_Init(GPIOA, &GPIO_InitStructure);
383 391
384 while(1) 392 while(1)
385 { 393 {
386 HAL_GPIO_WritePin(GPIOG,GPIO_PIN_7,GPIO_PIN_SET); 394 HAL_GPIO_WritePin(GPIOG,GPIO_PIN_7,GPIO_PIN_SET);
387 HAL_GPIO_WritePin(GPIOA,GPIO_PIN_3,GPIO_PIN_RESET); 395 HAL_GPIO_WritePin(GPIOA,GPIO_PIN_3,GPIO_PIN_RESET);
388 HAL_Delay(10); 396 HAL_Delay(10);
389 HAL_GPIO_WritePin(GPIOG,GPIO_PIN_7,GPIO_PIN_RESET); 397 HAL_GPIO_WritePin(GPIOG,GPIO_PIN_7,GPIO_PIN_RESET);
390 HAL_GPIO_WritePin(GPIOA,GPIO_PIN_3,GPIO_PIN_SET); 398 HAL_GPIO_WritePin(GPIOA,GPIO_PIN_3,GPIO_PIN_SET);
391 HAL_Delay(10); 399 HAL_Delay(10);
392 } 400 }
393 } 401 }
394 402
395 403
396 int main(void) 404 int main(void)
397 { 405 {
398 406
399 /* 407 /*
400 HAL_Init(); 408 HAL_Init();
401 SystemClock_Config(); 409 SystemClock_Config();
402 GPIO_test_I2C_lines(); 410 GPIO_test_I2C_lines();
403 */ 411 */
404 uint32_t pLayerInvisible; 412 uint32_t pLayerInvisible;
405 uint32_t firmware_load_result; 413 uint32_t firmware_load_result;
406 uint8_t magicbyte = 0; 414 uint8_t magicbyte = 0;
407 uint8_t callForUpdate; 415 uint8_t callForUpdate;
408 uint8_t status = 0; 416 uint8_t status = 0;
409 char textVersion[32]; 417 char textVersion[32];
410 uint8_t ptr; 418 uint8_t ptr;
411 uint32_t pOffset; 419 uint32_t pOffset;
412 420
413 set_globalState(StBoot0); 421 set_globalState(StBoot0);
414 422
415 HAL_Init(); 423 HAL_Init();
416 HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_2); 424 HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_2);
417 425
418 /* feedback for the user 426 /* feedback for the user
419 * aber sehr unsch�n beim Warmstart 427 * aber sehr unsch�n beim Warmstart
420 * da das letzte Bild noch lange nachleuchtet */ 428 * da das letzte Bild noch lange nachleuchtet */
421 // MX_GPIO_Backlight_max_static_only_Init(); 429 // MX_GPIO_Backlight_max_static_only_Init();
422 430
423 431
424 /* button press is only 40 to 50 us low */ 432 /* button press is only 40 to 50 us low */
481 } 489 }
482 } 490 }
483 } 491 }
484 } 492 }
485 } 493 }
486 494
487 if((i == 0) && (callForUpdate == 0)) 495 if((i == 0) && (callForUpdate == 0))
488 firmware_JumpTo_Application(); 496 firmware_JumpTo_Application();
489 497
490 SystemClock_Config(); 498 SystemClock_Config();
491 499
492 MX_GPIO_Init(); 500 MX_GPIO_Init();
493 MX_Bluetooth_PowerOn(); 501 MX_Bluetooth_PowerOn();
494 MX_SPI_Init(); 502 MX_SPI_Init();
495 SDRAM_Config(); 503 SDRAM_Config();
496 HAL_Delay(100); 504 HAL_Delay(100);
497 505
686 tInfo_newpage("Bootloader 160602"); 694 tInfo_newpage("Bootloader 160602");
687 tInfo_write("start bluetooth"); 695 tInfo_write("start bluetooth");
688 tInfo_write(""); 696 tInfo_write("");
689 tInfo_write(textVersion); 697 tInfo_write(textVersion);
690 tInfo_write(""); 698 tInfo_write("");
691 699
692 TIM_init(); 700 TIM_init();
693 MX_UART_Init(); 701 MX_UART_Init();
694 MX_Bluetooth_PowerOn(); 702 MX_Bluetooth_PowerOn();
695 tComm_Set_Bluetooth_Name(0); 703 tComm_Set_Bluetooth_Name(0);
696 704
697 tComm_init(); 705 tComm_init();
698 set_globalState_Base(); 706 set_globalState_Base();
699 707
700 GFX_start_VSYNC_IRQ(); 708 GFX_start_VSYNC_IRQ();
701 709
702 EXTILine_Buttons_Config(); 710 EXTILine_Buttons_Config();
703 /* 711 /*
704 uint8_t* pBuffer1 = (uint8_t*)getFrame(20); 712 uint8_t* pBuffer1 = (uint8_t*)getFrame(20);
705 firmware_load_result = ext_flash_read_firmware(pBuffer1,768000); 713 firmware_load_result = ext_flash_read_firmware(pBuffer1,768000);
706 714
707 if((firmware_load_result > 0) && (firmware_load_result < 768000)) 715 if((firmware_load_result > 0) && (firmware_load_result < 768000))
708 { 716 {
709 firmware_eraseFlashMemory(); 717 firmware_eraseFlashMemory();
710 firmware_programFlashMemory(pBuffer1,firmware_load_result); 718 firmware_programFlashMemory(pBuffer1,firmware_load_result);
711 // not for testing 719 // not for testing
712 //ext_flash_erase_firmware_if_not_empty(); 720 //ext_flash_erase_firmware_if_not_empty();
713 reset_to_firmware_using_Watchdog(); 721 reset_to_firmware_using_Watchdog();
714 } 722 }
715 */ 723 */
716 while(1) 724 while(1)
717 { 725 {
718 // if(bootToBootloader) 726 // if(bootToBootloader)
719 // DualBootToBootloader(); 727 // DualBootToBootloader();
720 728
721 if(bootToBootloader) 729 if(bootToBootloader)
722 reset_to_update_using_system_reset(); 730 reset_to_update_using_system_reset();
723 731
724 tComm_control(); // will stop while loop if tComm Mode started until exit from UART 732 tComm_control(); // will stop while loop if tComm Mode started until exit from UART
725 }; 733 };
726 } 734 }
727 735
728 736
750 tInfo_write(""); 758 tInfo_write("");
751 tInfo_write(""); 759 tInfo_write("");
752 tInfo_write(""); 760 tInfo_write("");
753 tInfo_write(""); 761 tInfo_write("");
754 } 762 }
755 763
756 get_globalStateList(&status); 764 get_globalStateList(&status);
757 765
758 switch(status.base) 766 switch(status.base)
759 { 767 {
760 case BaseComm: 768 case BaseComm:
769 void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin) 777 void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin)
770 { 778 {
771 uint8_t action; 779 uint8_t action;
772 SStateList status; 780 SStateList status;
773 static uint8_t counterToPreventSleep = 0; 781 static uint8_t counterToPreventSleep = 0;
774 if(GPIO_Pin == VSYNC_IRQ_PIN) // rechts, unten 782 if(GPIO_Pin == VSYNC_IRQ_PIN) // rechts, unten
775 { 783 {
776 GFX_change_LTDC(); 784 GFX_change_LTDC();
777 housekeepingFrame(); 785 housekeepingFrame();
778 if(counterToPreventSleep < 250) 786 if(counterToPreventSleep < 250)
779 counterToPreventSleep++; 787 counterToPreventSleep++;
780 else 788 else
781 if(counterToPreventSleep != 255) 789 if(counterToPreventSleep != 255)
782 { 790 {
783 counterToPreventSleep = 255; 791 counterToPreventSleep = 255;
784 } 792 }
785 793
786 return; 794 return;
787 } 795 }
788 796
789 time_without_button_pressed_deciseconds = 0; 797 time_without_button_pressed_deciseconds = 0;
790 798
791 if(GFX_logoStatus() != 0) 799 if(GFX_logoStatus() != 0)
792 return; 800 return;
793 801
794 if(GPIO_Pin == BUTTON_BACK_PIN) // links 802 if(GPIO_Pin == BUTTON_BACK_PIN) // links
795 action = ACTION_BUTTON_BACK; 803 action = ACTION_BUTTON_BACK;
796 else 804 else
797 if(GPIO_Pin == BUTTON_ENTER_PIN) // mitte 805 if(GPIO_Pin == BUTTON_ENTER_PIN) // mitte
798 action = ACTION_BUTTON_ENTER; 806 action = ACTION_BUTTON_ENTER;
799 else 807 else
800 if(GPIO_Pin == BUTTON_NEXT_PIN) // rechts 808 if(GPIO_Pin == BUTTON_NEXT_PIN) // rechts
801 action = ACTION_BUTTON_NEXT; 809 action = ACTION_BUTTON_NEXT;
802 #ifdef BUTTON_CUSTOM_PIN 810 #ifdef BUTTON_CUSTOM_PIN
803 else 811 else
804 if(GPIO_Pin == BUTTON_CUSTOM_PIN) // extra 812 if(GPIO_Pin == BUTTON_CUSTOM_PIN) // extra
805 action = ACTION_BUTTON_CUSTOM; 813 action = ACTION_BUTTON_CUSTOM;
806 #endif 814 #endif
807 else 815 else
808 action = 0; 816 action = 0;
809 get_globalStateList(&status); 817 get_globalStateList(&status);
814 if(action == ACTION_BUTTON_BACK) 822 if(action == ACTION_BUTTON_BACK)
815 { 823 {
816 reset_to_firmware_using_Watchdog(); 824 reset_to_firmware_using_Watchdog();
817 } 825 }
818 break; 826 break;
819 827
820 default: 828 default:
821 if((action == ACTION_BUTTON_NEXT) && (counterToPreventSleep == 255) && (get_globalState() == StS)) 829 if((action == ACTION_BUTTON_NEXT) && (counterToPreventSleep == 255) && (get_globalState() == StS))
822 { 830 {
823 while(1) 831 while(1)
824 { 832 {
934 } 942 }
935 943
936 944
937 void get_RTC_DateTime(RTC_DateTypeDef * sdatestructureget, RTC_TimeTypeDef * stimestructureget) 945 void get_RTC_DateTime(RTC_DateTypeDef * sdatestructureget, RTC_TimeTypeDef * stimestructureget)
938 { 946 {
939 /* Get the RTC current Time */ 947 /* Get the RTC current Time */
940 if(sdatestructureget) 948 if(sdatestructureget)
941 HAL_RTC_GetTime(&RtcHandle, stimestructureget, FORMAT_BIN); 949 HAL_RTC_GetTime(&RtcHandle, stimestructureget, FORMAT_BIN);
942 /* Get the RTC current Date */ 950 /* Get the RTC current Date */
943 if(stimestructureget) 951 if(stimestructureget)
944 HAL_RTC_GetDate(&RtcHandle, sdatestructureget, FORMAT_BIN); 952 HAL_RTC_GetDate(&RtcHandle, sdatestructureget, FORMAT_BIN);
945 } 953 }
946 954
947 955
964 972
965 static void TIM_init(void) 973 static void TIM_init(void)
966 { 974 {
967 uint16_t uwPrescalerValue = 0; 975 uint16_t uwPrescalerValue = 0;
968 976
969 uwPrescalerValue = (uint32_t) ((SystemCoreClock /2) / 10000) - 1; 977 uwPrescalerValue = (uint32_t) ((SystemCoreClock /2) / 10000) - 1;
970 978
971 /* Set TIMx instance */ 979 /* Set TIMx instance */
972 TimHandle.Instance = TIMx; 980 TimHandle.Instance = TIMx;
973 981
974 /* Initialize TIM3 peripheral as follows: 982 /* Initialize TIM3 peripheral as follows:
975 + Period = 10000 - 1 983 + Period = 10000 - 1
976 + Prescaler = ((SystemCoreClock/2)/10000) - 1 984 + Prescaler = ((SystemCoreClock/2)/10000) - 1
977 + ClockDivision = 0 985 + ClockDivision = 0
978 + Counter direction = Up 986 + Counter direction = Up
979 */ 987 */
980 TimHandle.Init.Period = 1000 - 1; 988 TimHandle.Init.Period = 1000 - 1;
981 TimHandle.Init.Prescaler = uwPrescalerValue; 989 TimHandle.Init.Prescaler = uwPrescalerValue;
982 TimHandle.Init.ClockDivision = 0; 990 TimHandle.Init.ClockDivision = 0;
983 TimHandle.Init.CounterMode = TIM_COUNTERMODE_UP; 991 TimHandle.Init.CounterMode = TIM_COUNTERMODE_UP;
984 if(HAL_TIM_Base_Init(&TimHandle) != HAL_OK) 992 if(HAL_TIM_Base_Init(&TimHandle) != HAL_OK)
985 { 993 {
986 /* Initialization Error */ 994 /* Initialization Error */
987 Error_Handler(); 995 Error_Handler();
988 } 996 }
989 997
990 /*##-2- Start the TIM Base generation in interrupt mode ####################*/ 998 /*##-2- Start the TIM Base generation in interrupt mode ####################*/
991 /* Start Channel1 */ 999 /* Start Channel1 */
992 if(HAL_TIM_Base_Start_IT(&TimHandle) != HAL_OK) 1000 if(HAL_TIM_Base_Start_IT(&TimHandle) != HAL_OK)
993 { 1001 {
994 /* Starting Error */ 1002 /* Starting Error */
995 Error_Handler(); 1003 Error_Handler();
996 } 1004 }
997 } 1005 }
998 1006
999 #ifndef TIM_BACKLIGHT 1007 #ifndef TIM_BACKLIGHT
1000 /* 1008 /*
1001 static void TIM_BACKLIGHT_adjust(void) 1009 static void TIM_BACKLIGHT_adjust(void)
1010 static void TIM_BACKLIGHT_adjust(void) 1018 static void TIM_BACKLIGHT_adjust(void)
1011 { 1019 {
1012 1020
1013 TIM_OC_InitTypeDef sConfig; 1021 TIM_OC_InitTypeDef sConfig;
1014 sConfig.OCMode = TIM_OCMODE_PWM1; 1022 sConfig.OCMode = TIM_OCMODE_PWM1;
1015 sConfig.OCPolarity = TIM_OCPOLARITY_HIGH; 1023 sConfig.OCPolarity = TIM_OCPOLARITY_HIGH;
1016 sConfig.OCFastMode = TIM_OCFAST_DISABLE; 1024 sConfig.OCFastMode = TIM_OCFAST_DISABLE;
1017 sConfig.Pulse = 600; 1025 sConfig.Pulse = 600;
1018 1026
1019 HAL_TIM_PWM_ConfigChannel(&TimBacklightHandle, &sConfig, TIM_BACKLIGHT_CHANNEL); 1027 HAL_TIM_PWM_ConfigChannel(&TimBacklightHandle, &sConfig, TIM_BACKLIGHT_CHANNEL);
1020 HAL_TIM_PWM_Start(&TimBacklightHandle, TIM_BACKLIGHT_CHANNEL); 1028 HAL_TIM_PWM_Start(&TimBacklightHandle, TIM_BACKLIGHT_CHANNEL);
1021 } 1029 }
1023 static void TIM_BACKLIGHT_init(void) 1031 static void TIM_BACKLIGHT_init(void)
1024 { 1032 {
1025 uint32_t uwPrescalerValue = 0; 1033 uint32_t uwPrescalerValue = 0;
1026 TIM_OC_InitTypeDef sConfig; 1034 TIM_OC_InitTypeDef sConfig;
1027 1035
1028 uwPrescalerValue = (uint32_t) ((SystemCoreClock /2) / 18000000) - 1; 1036 uwPrescalerValue = (uint32_t) ((SystemCoreClock /2) / 18000000) - 1;
1029 1037
1030 TimBacklightHandle.Instance = TIM_BACKLIGHT; 1038 TimBacklightHandle.Instance = TIM_BACKLIGHT;
1031 1039
1032 // Initialize TIM3 peripheral as follows: 30 kHz 1040 // Initialize TIM3 peripheral as follows: 30 kHz
1033 1041
1034 TimBacklightHandle.Init.Period = 600 - 1; 1042 TimBacklightHandle.Init.Period = 600 - 1;
1035 TimBacklightHandle.Init.Prescaler = uwPrescalerValue; 1043 TimBacklightHandle.Init.Prescaler = uwPrescalerValue;
1036 TimBacklightHandle.Init.ClockDivision = 0; 1044 TimBacklightHandle.Init.ClockDivision = 0;
1037 TimBacklightHandle.Init.CounterMode = TIM_COUNTERMODE_UP; 1045 TimBacklightHandle.Init.CounterMode = TIM_COUNTERMODE_UP;
1038 HAL_TIM_PWM_Init(&TimBacklightHandle); 1046 HAL_TIM_PWM_Init(&TimBacklightHandle);
1039 1047
1040 sConfig.OCMode = TIM_OCMODE_PWM1; 1048 sConfig.OCMode = TIM_OCMODE_PWM1;
1041 sConfig.OCPolarity = TIM_OCPOLARITY_HIGH; 1049 sConfig.OCPolarity = TIM_OCPOLARITY_HIGH;
1042 sConfig.OCFastMode = TIM_OCFAST_DISABLE; 1050 sConfig.OCFastMode = TIM_OCFAST_DISABLE;
1043 sConfig.Pulse = 50 * 6; 1051 sConfig.Pulse = 50 * 6;
1044 1052
1045 HAL_TIM_PWM_ConfigChannel(&TimBacklightHandle, &sConfig, TIM_BACKLIGHT_CHANNEL); 1053 HAL_TIM_PWM_ConfigChannel(&TimBacklightHandle, &sConfig, TIM_BACKLIGHT_CHANNEL);
1046 HAL_TIM_PWM_Start(&TimBacklightHandle, TIM_BACKLIGHT_CHANNEL); 1054 HAL_TIM_PWM_Start(&TimBacklightHandle, TIM_BACKLIGHT_CHANNEL);
1047 } 1055 }
1048 #endif 1056 #endif
1049 1057
1050 /* Configure RTC prescaler and RTC data registers */ 1058 /* Configure RTC prescaler and RTC data registers */
1051 /* RTC configured as follow: 1059 /* RTC configured as follow:
1052 - Hour Format = Format 24 1060 - Hour Format = Format 24
1053 - Asynch Prediv = Value according to source clock 1061 - Asynch Prediv = Value according to source clock
1054 - Synch Prediv = Value according to source clock 1062 - Synch Prediv = Value according to source clock
1055 - OutPut = Output Disable 1063 - OutPut = Output Disable
1056 - OutPutPolarity = High Polarity 1064 - OutPutPolarity = High Polarity
1057 - OutPutType = Open Drain */ 1065 - OutPutType = Open Drain */
1058 /*#define RTC_ASYNCH_PREDIV 0x7F LSE as RTC clock */ 1066 /*#define RTC_ASYNCH_PREDIV 0x7F LSE as RTC clock */
1059 /*LSE: #define RTC_SYNCH_PREDIV 0x00FF LSE as RTC clock */ 1067 /*LSE: #define RTC_SYNCH_PREDIV 0x00FF LSE as RTC clock */
1060 /*LSI: #define RTC_SYNCH_PREDIV 0x0130 LSI as RTC clock */ 1068 /*LSI: #define RTC_SYNCH_PREDIV 0x0130 LSI as RTC clock */
1061 /* 1069 /*
1062 static void RTC_init(void) 1070 static void RTC_init(void)
1063 { 1071 {
1064 RtcHandle.Instance = RTC; 1072 RtcHandle.Instance = RTC;
1065 1073
1066 1074
1067 RtcHandle.Init.HourFormat = RTC_HOURFORMAT_24; 1075 RtcHandle.Init.HourFormat = RTC_HOURFORMAT_24;
1068 RtcHandle.Init.AsynchPrediv = 0x7F; 1076 RtcHandle.Init.AsynchPrediv = 0x7F;
1069 RtcHandle.Init.SynchPrediv = 0x0130; 1077 RtcHandle.Init.SynchPrediv = 0x0130;
1070 RtcHandle.Init.OutPut = RTC_OUTPUT_DISABLE; 1078 RtcHandle.Init.OutPut = RTC_OUTPUT_DISABLE;
1071 RtcHandle.Init.OutPutPolarity = RTC_OUTPUT_POLARITY_HIGH; 1079 RtcHandle.Init.OutPutPolarity = RTC_OUTPUT_POLARITY_HIGH;
1072 RtcHandle.Init.OutPutType = RTC_OUTPUT_TYPE_OPENDRAIN; 1080 RtcHandle.Init.OutPutType = RTC_OUTPUT_TYPE_OPENDRAIN;
1073 1081
1074 if(HAL_RTC_Init(&RtcHandle) != HAL_OK) 1082 if(HAL_RTC_Init(&RtcHandle) != HAL_OK)
1075 { 1083 {
1076 Error_Handler(); 1084 Error_Handler();
1077 } 1085 }
1078 } 1086 }
1079 */ 1087 */
1080 1088
1081 static void EXTILine_Buttons_Config(void) 1089 static void EXTILine_Buttons_Config(void)
1082 { 1090 {
1083 GPIO_InitTypeDef GPIO_InitStructure; 1091 GPIO_InitTypeDef GPIO_InitStructure;
1084 1092
1085 BUTTON_ENTER_GPIO_ENABLE(); 1093 BUTTON_ENTER_GPIO_ENABLE();
1086 BUTTON_NEXT_GPIO_ENABLE(); 1094 BUTTON_NEXT_GPIO_ENABLE();
1087 BUTTON_BACK_GPIO_ENABLE(); 1095 BUTTON_BACK_GPIO_ENABLE();
1088 1096
1089 /* Configure pin as weak PULLUP input */ 1097 /* Configure pin as weak PULLUP input */
1090 /* buttons */ 1098 /* buttons */
1091 GPIO_InitStructure.Mode = GPIO_MODE_IT_RISING; 1099 GPIO_InitStructure.Mode = GPIO_MODE_IT_RISING;
1092 GPIO_InitStructure.Pull = GPIO_NOPULL; 1100 GPIO_InitStructure.Pull = GPIO_NOPULL;
1093 GPIO_InitStructure.Speed = GPIO_SPEED_LOW; 1101 GPIO_InitStructure.Speed = GPIO_SPEED_LOW;
1094 1102
1095 GPIO_InitStructure.Pin = BUTTON_ENTER_PIN; 1103 GPIO_InitStructure.Pin = BUTTON_ENTER_PIN;
1096 HAL_GPIO_Init(BUTTON_ENTER_GPIO_PORT, &GPIO_InitStructure); 1104 HAL_GPIO_Init(BUTTON_ENTER_GPIO_PORT, &GPIO_InitStructure);
1097 1105
1098 GPIO_InitStructure.Pin = BUTTON_NEXT_PIN; 1106 GPIO_InitStructure.Pin = BUTTON_NEXT_PIN;
1099 HAL_GPIO_Init(BUTTON_NEXT_GPIO_PORT, &GPIO_InitStructure); 1107 HAL_GPIO_Init(BUTTON_NEXT_GPIO_PORT, &GPIO_InitStructure);
1100 1108
1101 GPIO_InitStructure.Pin = BUTTON_BACK_PIN; 1109 GPIO_InitStructure.Pin = BUTTON_BACK_PIN;
1102 HAL_GPIO_Init(BUTTON_BACK_GPIO_PORT, &GPIO_InitStructure); 1110 HAL_GPIO_Init(BUTTON_BACK_GPIO_PORT, &GPIO_InitStructure);
1103 1111
1104 /* Enable and set EXTI Line0 Interrupt to the lowest priority */ 1112 /* Enable and set EXTI Line0 Interrupt to the lowest priority */
1105 HAL_NVIC_SetPriority(BUTTON_ENTER_EXTI_IRQn, 2, 0); 1113 HAL_NVIC_SetPriority(BUTTON_ENTER_EXTI_IRQn, 2, 0);
1106 HAL_NVIC_SetPriority(BUTTON_NEXT_EXTI_IRQn, 2, 0); 1114 HAL_NVIC_SetPriority(BUTTON_NEXT_EXTI_IRQn, 2, 0);
1107 HAL_NVIC_SetPriority(BUTTON_BACK_EXTI_IRQn, 2, 0); 1115 HAL_NVIC_SetPriority(BUTTON_BACK_EXTI_IRQn, 2, 0);
1108 HAL_NVIC_EnableIRQ(BUTTON_ENTER_EXTI_IRQn); 1116 HAL_NVIC_EnableIRQ(BUTTON_ENTER_EXTI_IRQn);
1109 HAL_NVIC_EnableIRQ(BUTTON_NEXT_EXTI_IRQn); 1117 HAL_NVIC_EnableIRQ(BUTTON_NEXT_EXTI_IRQn);
1110 HAL_NVIC_EnableIRQ(BUTTON_BACK_EXTI_IRQn); 1118 HAL_NVIC_EnableIRQ(BUTTON_BACK_EXTI_IRQn);
1111 1119
1112 #ifdef BUTTON_CUSTOM_PIN 1120 #ifdef BUTTON_CUSTOM_PIN
1113 BUTTON_CUSTOM_GPIO_ENABLE(); 1121 BUTTON_CUSTOM_GPIO_ENABLE();
1114 GPIO_InitStructure.Pin = BUTTON_CUSTOM_PIN; 1122 GPIO_InitStructure.Pin = BUTTON_CUSTOM_PIN;
1115 HAL_GPIO_Init(BUTTON_CUSTOM_GPIO_PORT, &GPIO_InitStructure); 1123 HAL_GPIO_Init(BUTTON_CUSTOM_GPIO_PORT, &GPIO_InitStructure);
1116 HAL_NVIC_SetPriority(BUTTON_CUSTOM_EXTI_IRQn, 2, 0); 1124 HAL_NVIC_SetPriority(BUTTON_CUSTOM_EXTI_IRQn, 2, 0);
1117 HAL_NVIC_EnableIRQ(BUTTON_CUSTOM_EXTI_IRQn); 1125 HAL_NVIC_EnableIRQ(BUTTON_CUSTOM_EXTI_IRQn);
1118 #endif 1126 #endif
1119 } 1127 }
1120 1128
1121 1129
1122 /** 1130 /**
1123 * @brief System Clock Configuration 1131 * @brief System Clock Configuration
1124 * The system Clock is configured as follow : 1132 * The system Clock is configured as follow :
1125 * System Clock source = PLL (HSE) 1133 * System Clock source = PLL (HSE)
1126 * SYSCLK(Hz) = 180000000 1134 * SYSCLK(Hz) = 180000000
1127 * HCLK(Hz) = 180000000 1135 * HCLK(Hz) = 180000000
1128 * AHB Prescaler = 1 1136 * AHB Prescaler = 1
1129 * APB1 Prescaler = 4 1137 * APB1 Prescaler = 4
1130 * APB2 Prescaler = 2 1138 * APB2 Prescaler = 2
1131 * HSE Frequency(Hz) = 8000000 1139 * HSE Frequency(Hz) = 8000000
1132 * PLL_M = 8 1140 * PLL_M = 8
1133 * PLL_N = 360 1141 * PLL_N = 360
1134 * PLL_P = 2 1142 * PLL_P = 2
1135 * PLL_Q = 7 1143 * PLL_Q = 7
1136 * VDD(V) = 3.3 1144 * VDD(V) = 3.3
1137 * Main regulator output voltage = Scale1 mode 1145 * Main regulator output voltage = Scale1 mode
1138 * Flash Latency(WS) = 5 1146 * Flash Latency(WS) = 5
1139 * The LTDC Clock is configured as follow : 1147 * The LTDC Clock is configured as follow :
1140 * PLLSAIN = 192 1148 * PLLSAIN = 192
1141 * PLLSAIR = 4 1149 * PLLSAIR = 4
1142 * PLLSAIDivR = 8 1150 * PLLSAIDivR = 8
1143 * @param None 1151 * @param None
1144 * @retval None 1152 * @retval None
1145 */ 1153 */
1146 static void SystemClock_Config(void) 1154 static void SystemClock_Config(void)
1147 { 1155 {
1148 RCC_ClkInitTypeDef RCC_ClkInitStruct; 1156 RCC_ClkInitTypeDef RCC_ClkInitStruct;
1149 RCC_OscInitTypeDef RCC_OscInitStruct; 1157 RCC_OscInitTypeDef RCC_OscInitStruct;
1150 RCC_PeriphCLKInitTypeDef PeriphClkInitStruct; 1158 RCC_PeriphCLKInitTypeDef PeriphClkInitStruct;
1151 1159
1152 /* Enable Power Control clock */ 1160 /* Enable Power Control clock */
1153 __PWR_CLK_ENABLE(); 1161 __PWR_CLK_ENABLE();
1154 1162
1155 /* The voltage scaling allows optimizing the power consumption when the device is 1163 /* The voltage scaling allows optimizing the power consumption when the device is
1156 clocked below the maximum system frequency, to update the voltage scaling value 1164 clocked below the maximum system frequency, to update the voltage scaling value
1157 regarding system frequency refer to product datasheet. */ 1165 regarding system frequency refer to product datasheet. */
1158 __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); 1166 __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
1159 1167
1160 /*##-1- System Clock Configuration #########################################*/ 1168 /*##-1- System Clock Configuration #########################################*/
1161 /* Enable HSE Oscillator and activate PLL with HSE as source */ 1169 /* Enable HSE Oscillator and activate PLL with HSE as source */
1162 RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; 1170 RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
1163 RCC_OscInitStruct.HSEState = RCC_HSE_ON; 1171 RCC_OscInitStruct.HSEState = RCC_HSE_ON;
1164 RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; 1172 RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
1165 RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; 1173 RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
1166 RCC_OscInitStruct.PLL.PLLM = 8; 1174 RCC_OscInitStruct.PLL.PLLM = 8;
1167 RCC_OscInitStruct.PLL.PLLN = 336;//360; 1175 RCC_OscInitStruct.PLL.PLLN = 336;//360;
1168 RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; 1176 RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
1169 RCC_OscInitStruct.PLL.PLLQ = 7; 1177 RCC_OscInitStruct.PLL.PLLQ = 7;
1170 HAL_RCC_OscConfig(&RCC_OscInitStruct); 1178 HAL_RCC_OscConfig(&RCC_OscInitStruct);
1171 1179
1172 // HAL_PWREx_ActivateOverDrive(); 1180 // HAL_PWREx_ActivateOverDrive();
1173 HAL_PWREx_DeactivateOverDrive(); 1181 HAL_PWREx_DeactivateOverDrive();
1174 /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 1182 /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2
1175 clocks dividers */ 1183 clocks dividers */
1176 RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2); 1184 RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
1177 RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; 1185 RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
1178 RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; 1186 RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
1179 RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4; 1187 RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4;
1180 RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2; 1188 RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2;
1181 HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_8);//FLASH_LATENCY_5); 1189 HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_8);//FLASH_LATENCY_5);
1182 1190
1183 /*##-2- LTDC Clock Configuration ###########################################*/ 1191 /*##-2- LTDC Clock Configuration ###########################################*/
1184 /* LCD clock configuration */ 1192 /* LCD clock configuration */
1185 /* PLLSAI_VCO Input = HSE_VALUE/PLL_M = 1 Mhz */ 1193 /* PLLSAI_VCO Input = HSE_VALUE/PLL_M = 1 Mhz */
1186 /* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN = 192 Mhz */ 1194 /* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN = 192 Mhz */
1187 /* PLLLCDCLK = PLLSAI_VCO Output/PLLSAIR = 192/4 = 48 Mhz */ 1195 /* PLLLCDCLK = PLLSAI_VCO Output/PLLSAIR = 192/4 = 48 Mhz */
1188 /* LTDC clock frequency = PLLLCDCLK / RCC_PLLSAIDIVR_8 = 48/8 = 6 Mhz */ 1196 /* LTDC clock frequency = PLLLCDCLK / RCC_PLLSAIDIVR_8 = 48/8 = 6 Mhz */
1189 1197
1190 /* neu: 8MHz/8*300/5/8 = 7,5 MHz = 19,5 Hz bei 800 x 480 */ 1198 /* neu: 8MHz/8*300/5/8 = 7,5 MHz = 19,5 Hz bei 800 x 480 */
1191 PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_LTDC; 1199 PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_LTDC;
1192 PeriphClkInitStruct.PLLSAI.PLLSAIN = 300;//192; 1200 PeriphClkInitStruct.PLLSAI.PLLSAIN = 300;//192;
1193 PeriphClkInitStruct.PLLSAI.PLLSAIR = 5;//4; 1201 PeriphClkInitStruct.PLLSAI.PLLSAIR = 5;//4;
1194 PeriphClkInitStruct.PLLSAIDivR = RCC_PLLSAIDIVR_8;//RCC_PLLSAIDIVR_4;// RCC_PLLSAIDIVR_2; // RCC_PLLSAIDIVR_8 1202 PeriphClkInitStruct.PLLSAIDivR = RCC_PLLSAIDIVR_8;//RCC_PLLSAIDIVR_4;// RCC_PLLSAIDIVR_2; // RCC_PLLSAIDIVR_8
1195 HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct); 1203 HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct);
1196 } 1204 }
1197 1205
1198 1206
1199 /** 1207 /**
1200 * @brief This function is executed in case of error occurrence. 1208 * @brief This function is executed in case of error occurrence.
1201 * @param None 1209 * @param None
1202 * @retval None 1210 * @retval None
1203 */ 1211 */
1204 static void Error_Handler(void) 1212 static void Error_Handler(void)
1205 { 1213 {
1206 /* Turn LED3 on */ 1214 /* Turn LED3 on */
1207 // BSP_LED_On(LED3); 1215 // BSP_LED_On(LED3);
1208 while(1) 1216 while(1)
1209 { 1217 {
1210 } 1218 }
1211 } 1219 }
1212 1220
1213 /** 1221 /**
1214 * @brief Perform the SDRAM exernal memory inialization sequence 1222 * @brief Perform the SDRAM exernal memory inialization sequence
1215 * @param hsdram: SDRAM handle 1223 * @param hsdram: SDRAM handle
1216 * @param Command: Pointer to SDRAM command structure 1224 * @param Command: Pointer to SDRAM command structure
1217 * @retval None 1225 * @retval None
1218 */ 1226 */
1219 static void SDRAM_Initialization_Sequence(SDRAM_HandleTypeDef *hsdram, FMC_SDRAM_CommandTypeDef *Command) 1227 static void SDRAM_Initialization_Sequence(SDRAM_HandleTypeDef *hsdram, FMC_SDRAM_CommandTypeDef *Command)
1220 { 1228 {
1221 __IO uint32_t tmpmrd =0; 1229 __IO uint32_t tmpmrd =0;
1222 /* Step 3: Configure a clock configuration enable command */ 1230 /* Step 3: Configure a clock configuration enable command */
1223 Command->CommandMode = FMC_SDRAM_CMD_CLK_ENABLE; 1231 Command->CommandMode = FMC_SDRAM_CMD_CLK_ENABLE;
1224 Command->CommandTarget = FMC_SDRAM_CMD_TARGET_BANK2; 1232 Command->CommandTarget = FMC_SDRAM_CMD_TARGET_BANK2;
1225 Command->AutoRefreshNumber = 1; 1233 Command->AutoRefreshNumber = 1;
1226 Command->ModeRegisterDefinition = 0; 1234 Command->ModeRegisterDefinition = 0;
1227 1235
1228 /* Send the command */ 1236 /* Send the command */
1229 HAL_SDRAM_SendCommand(hsdram, Command, 0x1000); 1237 HAL_SDRAM_SendCommand(hsdram, Command, 0x1000);
1230 1238
1231 /* Step 4: Insert 100 ms delay */ 1239 /* Step 4: Insert 100 ms delay */
1232 HAL_Delay(100); 1240 HAL_Delay(100);
1233 1241
1234 /* Step 5: Configure a PALL (precharge all) command */ 1242 /* Step 5: Configure a PALL (precharge all) command */
1235 Command->CommandMode = FMC_SDRAM_CMD_PALL; 1243 Command->CommandMode = FMC_SDRAM_CMD_PALL;
1236 Command->CommandTarget = FMC_SDRAM_CMD_TARGET_BANK2; 1244 Command->CommandTarget = FMC_SDRAM_CMD_TARGET_BANK2;
1237 Command->AutoRefreshNumber = 1; 1245 Command->AutoRefreshNumber = 1;
1238 Command->ModeRegisterDefinition = 0; 1246 Command->ModeRegisterDefinition = 0;
1239 1247
1240 /* Send the command */ 1248 /* Send the command */
1241 HAL_SDRAM_SendCommand(hsdram, Command, 0x1000); 1249 HAL_SDRAM_SendCommand(hsdram, Command, 0x1000);
1242 1250
1243 /* Step 6 : Configure a Auto-Refresh command */ 1251 /* Step 6 : Configure a Auto-Refresh command */
1244 Command->CommandMode = FMC_SDRAM_CMD_AUTOREFRESH_MODE; 1252 Command->CommandMode = FMC_SDRAM_CMD_AUTOREFRESH_MODE;
1245 Command->CommandTarget = FMC_SDRAM_CMD_TARGET_BANK2; 1253 Command->CommandTarget = FMC_SDRAM_CMD_TARGET_BANK2;
1246 Command->AutoRefreshNumber = 4; 1254 Command->AutoRefreshNumber = 4;
1247 Command->ModeRegisterDefinition = 0; 1255 Command->ModeRegisterDefinition = 0;
1248 1256
1249 /* Send the command */ 1257 /* Send the command */
1250 HAL_SDRAM_SendCommand(hsdram, Command, 0x1000); 1258 HAL_SDRAM_SendCommand(hsdram, Command, 0x1000);
1251 1259
1252 /* Step 7: Program the external memory mode register */ 1260 /* Step 7: Program the external memory mode register */
1253 tmpmrd = (uint32_t)SDRAM_MODEREG_BURST_LENGTH_2 | 1261 tmpmrd = (uint32_t)SDRAM_MODEREG_BURST_LENGTH_2 |
1254 SDRAM_MODEREG_BURST_TYPE_SEQUENTIAL | 1262 SDRAM_MODEREG_BURST_TYPE_SEQUENTIAL |
1255 SDRAM_MODEREG_CAS_LATENCY_3 | 1263 SDRAM_MODEREG_CAS_LATENCY_3 |
1256 SDRAM_MODEREG_OPERATING_MODE_STANDARD | 1264 SDRAM_MODEREG_OPERATING_MODE_STANDARD |
1257 SDRAM_MODEREG_WRITEBURST_MODE_SINGLE; 1265 SDRAM_MODEREG_WRITEBURST_MODE_SINGLE;
1258 1266
1259 Command->CommandMode = FMC_SDRAM_CMD_LOAD_MODE; 1267 Command->CommandMode = FMC_SDRAM_CMD_LOAD_MODE;
1260 Command->CommandTarget = FMC_SDRAM_CMD_TARGET_BANK2; 1268 Command->CommandTarget = FMC_SDRAM_CMD_TARGET_BANK2;
1261 Command->AutoRefreshNumber = 1; 1269 Command->AutoRefreshNumber = 1;
1262 Command->ModeRegisterDefinition = tmpmrd; 1270 Command->ModeRegisterDefinition = tmpmrd;
1263 1271
1264 /* Send the command */ 1272 /* Send the command */
1265 HAL_SDRAM_SendCommand(hsdram, Command, 0x1000); 1273 HAL_SDRAM_SendCommand(hsdram, Command, 0x1000);
1266 1274
1267 /* Step 8: Set the refresh rate counter */ 1275 /* Step 8: Set the refresh rate counter */
1268 /* (15.62 us x Freq) - 20 */ 1276 /* (15.62 us x Freq) - 20 */
1269 /* neu: (8 us x Freq) - 20 */ 1277 /* neu: (8 us x Freq) - 20 */
1270 /* Set the device refresh counter */ 1278 /* Set the device refresh counter */
1271 HAL_SDRAM_ProgramRefreshRate(hsdram, REFRESH_COUNT); 1279 HAL_SDRAM_ProgramRefreshRate(hsdram, REFRESH_COUNT);
1272 } 1280 }
1273 1281
1274 /* 1282 /*
1275 static void DualBoot(void) 1283 static void DualBoot(void)
1276 { 1284 {
1277 // Set BFB2 bit to enable boot from Flash Bank2 1285 // Set BFB2 bit to enable boot from Flash Bank2
1278 // Allow Access to Flash control registers and user Falsh 1286 // Allow Access to Flash control registers and user Falsh
1279 HAL_FLASH_Unlock(); 1287 HAL_FLASH_Unlock();
1280 1288
1281 // Allow Access to option bytes sector 1289 // Allow Access to option bytes sector
1282 HAL_FLASH_OB_Unlock(); 1290 HAL_FLASH_OB_Unlock();
1283 1291
1284 // Get the Dual boot configuration status 1292 // Get the Dual boot configuration status
1285 AdvOBInit.OptionType = OBEX_BOOTCONFIG; 1293 AdvOBInit.OptionType = OBEX_BOOTCONFIG;
1286 HAL_FLASHEx_AdvOBGetConfig(&AdvOBInit); 1294 HAL_FLASHEx_AdvOBGetConfig(&AdvOBInit);
1287 1295
1288 // Enable/Disable dual boot feature 1296 // Enable/Disable dual boot feature
1289 if (((AdvOBInit.BootConfig) & (FLASH_OPTCR_BFB2)) == FLASH_OPTCR_BFB2) 1297 if (((AdvOBInit.BootConfig) & (FLASH_OPTCR_BFB2)) == FLASH_OPTCR_BFB2)
1290 { 1298 {
1291 AdvOBInit.BootConfig = OB_DUAL_BOOT_DISABLE; 1299 AdvOBInit.BootConfig = OB_DUAL_BOOT_DISABLE;
1292 HAL_FLASHEx_AdvOBProgram (&AdvOBInit); 1300 HAL_FLASHEx_AdvOBProgram (&AdvOBInit);
1293 } 1301 }
1294 else 1302 else
1295 { 1303 {
1296 AdvOBInit.BootConfig = OB_DUAL_BOOT_ENABLE; 1304 AdvOBInit.BootConfig = OB_DUAL_BOOT_ENABLE;
1297 HAL_FLASHEx_AdvOBProgram (&AdvOBInit); 1305 HAL_FLASHEx_AdvOBProgram (&AdvOBInit);
1298 } 1306 }
1299 1307
1300 // Start the Option Bytes programming process 1308 // Start the Option Bytes programming process
1301 if (HAL_FLASH_OB_Launch() != HAL_OK) 1309 if (HAL_FLASH_OB_Launch() != HAL_OK)
1302 { 1310 {
1303 // User can add here some code to deal with this error 1311 // User can add here some code to deal with this error
1304 while (1) 1312 while (1)
1305 { 1313 {
1306 } 1314 }
1307 } 1315 }
1308 // Prevent Access to option bytes sector 1316 // Prevent Access to option bytes sector
1309 HAL_FLASH_OB_Lock(); 1317 HAL_FLASH_OB_Lock();
1310 1318
1311 // Disable the Flash option control register access (recommended to protect 1319 // Disable the Flash option control register access (recommended to protect
1312 // the option Bytes against possible unwanted operations) 1320 // the option Bytes against possible unwanted operations)
1313 HAL_FLASH_Lock(); 1321 HAL_FLASH_Lock();
1314 1322
1315 // Initiates a system reset request to reset the MCU 1323 // Initiates a system reset request to reset the MCU
1316 reset_to_firmware_using_Watchdog(); 1324 reset_to_firmware_using_Watchdog();
1317 } 1325 }
1318 */ 1326 */
1319 /** 1327 /**
1320 ****************************************************************************** 1328 ******************************************************************************
1321 ****************************************************************************** 1329 ******************************************************************************
1322 ****************************************************************************** 1330 ******************************************************************************
1323 */ 1331 */
1324 1332
1325 1333
1326 /** 1334 /**
1327 * @brief DMA2D configuration. 1335 * @brief DMA2D configuration.
1328 * @note This function Configure tha DMA2D peripheral : 1336 * @note This function Configure tha DMA2D peripheral :
1329 * 1) Configure the transfer mode : memory to memory W/ pixel format conversion 1337 * 1) Configure the transfer mode : memory to memory W/ pixel format conversion
1330 * 2) Configure the output color mode as ARGB4444 1338 * 2) Configure the output color mode as ARGB4444
1331 * 3) Configure the output memory address at SRAM memory 1339 * 3) Configure the output memory address at SRAM memory
1332 * 4) Configure the data size : 320x120 (pixels) 1340 * 4) Configure the data size : 320x120 (pixels)
1333 * 5) Configure the input color mode as ARGB8888 1341 * 5) Configure the input color mode as ARGB8888
1334 * 6) Configure the input memory address at FLASH memory 1342 * 6) Configure the input memory address at FLASH memory
1335 * @retval 1343 * @retval
1336 * None 1344 * None
1337 */ 1345 */
1338 1346
1339 static void SDRAM_Config(void) 1347 static void SDRAM_Config(void)
1340 { 1348 {
1341 /*##-1- Configure the SDRAM device #########################################*/ 1349 /*##-1- Configure the SDRAM device #########################################*/
1342 /* SDRAM device configuration */ 1350 /* SDRAM device configuration */
1343 hsdram.Instance = FMC_SDRAM_DEVICE; 1351 hsdram.Instance = FMC_SDRAM_DEVICE;
1344 1352
1345 /* Timing configuration for 90 Mhz of SD clock frequency (180Mhz/2) */ 1353 /* Timing configuration for 90 Mhz of SD clock frequency (180Mhz/2) */
1346 /* TMRD: 2 Clock cycles */ 1354 /* TMRD: 2 Clock cycles */
1347 SDRAM_Timing.LoadToActiveDelay = 2; 1355 SDRAM_Timing.LoadToActiveDelay = 2;
1348 /* TXSR: min=70ns (6x11.90ns) */ 1356 /* TXSR: min=70ns (6x11.90ns) */
1349 SDRAM_Timing.ExitSelfRefreshDelay = 7; 1357 SDRAM_Timing.ExitSelfRefreshDelay = 7;
1350 /* TRAS: min=42ns (4x11.90ns) max=120k (ns) */ 1358 /* TRAS: min=42ns (4x11.90ns) max=120k (ns) */
1351 SDRAM_Timing.SelfRefreshTime = 4; 1359 SDRAM_Timing.SelfRefreshTime = 4;
1352 /* TRC: min=63 (6x11.90ns) */ 1360 /* TRC: min=63 (6x11.90ns) */
1353 SDRAM_Timing.RowCycleDelay = 7; 1361 SDRAM_Timing.RowCycleDelay = 7;
1354 /* TWR: 2 Clock cycles */ 1362 /* TWR: 2 Clock cycles */
1355 SDRAM_Timing.WriteRecoveryTime = 2; 1363 SDRAM_Timing.WriteRecoveryTime = 2;
1356 /* TRP: 15ns => 2x11.90ns */ 1364 /* TRP: 15ns => 2x11.90ns */
1357 SDRAM_Timing.RPDelay = 2; 1365 SDRAM_Timing.RPDelay = 2;
1358 /* TRCD: 15ns => 2x11.90ns */ 1366 /* TRCD: 15ns => 2x11.90ns */
1359 SDRAM_Timing.RCDDelay = 2; 1367 SDRAM_Timing.RCDDelay = 2;
1360 1368
1361 hsdram.Init.SDBank = FMC_SDRAM_BANK2; 1369 hsdram.Init.SDBank = FMC_SDRAM_BANK2;
1362 hsdram.Init.ColumnBitsNumber = FMC_SDRAM_COLUMN_BITS_NUM_9; 1370 hsdram.Init.ColumnBitsNumber = FMC_SDRAM_COLUMN_BITS_NUM_9;
1363 hsdram.Init.RowBitsNumber = FMC_SDRAM_ROW_BITS_NUM_13; 1371 hsdram.Init.RowBitsNumber = FMC_SDRAM_ROW_BITS_NUM_13;
1364 hsdram.Init.MemoryDataWidth = SDRAM_MEMORY_WIDTH; 1372 hsdram.Init.MemoryDataWidth = SDRAM_MEMORY_WIDTH;
1365 hsdram.Init.InternalBankNumber = FMC_SDRAM_INTERN_BANKS_NUM_4; 1373 hsdram.Init.InternalBankNumber = FMC_SDRAM_INTERN_BANKS_NUM_4;
1366 hsdram.Init.CASLatency = FMC_SDRAM_CAS_LATENCY_3; 1374 hsdram.Init.CASLatency = FMC_SDRAM_CAS_LATENCY_3;
1367 hsdram.Init.WriteProtection = FMC_SDRAM_WRITE_PROTECTION_DISABLE; 1375 hsdram.Init.WriteProtection = FMC_SDRAM_WRITE_PROTECTION_DISABLE;
1368 hsdram.Init.SDClockPeriod = SDCLOCK_PERIOD; 1376 hsdram.Init.SDClockPeriod = SDCLOCK_PERIOD;
1369 hsdram.Init.ReadBurst = FMC_SDRAM_RBURST_DISABLE; 1377 hsdram.Init.ReadBurst = FMC_SDRAM_RBURST_DISABLE;
1370 hsdram.Init.ReadPipeDelay = FMC_SDRAM_RPIPE_DELAY_1; 1378 hsdram.Init.ReadPipeDelay = FMC_SDRAM_RPIPE_DELAY_1;
1371 1379
1372 /* Initialize the SDRAM controller */ 1380 /* Initialize the SDRAM controller */
1373 if(HAL_SDRAM_Init(&hsdram, &SDRAM_Timing) != HAL_OK) 1381 if(HAL_SDRAM_Init(&hsdram, &SDRAM_Timing) != HAL_OK)
1374 { 1382 {
1375 /* Initialization Error */ 1383 /* Initialization Error */
1376 Error_Handler(); 1384 Error_Handler();
1377 } 1385 }
1378 1386
1379 /* Program the SDRAM external device */ 1387 /* Program the SDRAM external device */
1380 SDRAM_Initialization_Sequence(&hsdram, &command); 1388 SDRAM_Initialization_Sequence(&hsdram, &command);
1381 } 1389 }
1382 1390
1383 1391
1384 uint8_t checkResetForFirmwareUpdate(void) 1392 uint8_t checkResetForFirmwareUpdate(void)
1385 { 1393 {
1386 uint32_t backupRegisterContent; 1394 uint32_t backupRegisterContent;
1387 1395
1388 RTC_HandleTypeDef RtcHandle; 1396 RTC_HandleTypeDef RtcHandle;
1389 RtcHandle.Instance = RTC; 1397 RtcHandle.Instance = RTC;
1390 backupRegisterContent = HAL_RTCEx_BKUPRead(&RtcHandle,RTC_BKP_DR0); 1398 backupRegisterContent = HAL_RTCEx_BKUPRead(&RtcHandle,RTC_BKP_DR0);
1391 1399
1392 if(backupRegisterContent == 0x12345678) 1400 if(backupRegisterContent == 0x12345678)
1393 return 1; 1401 return 1;
1394 else 1402 else
1395 return 0; 1403 return 0;
1396 } 1404 }
1397 1405
1398 void DeleteResetToFirmwareUpdateRegister(void) 1406 void DeleteResetToFirmwareUpdateRegister(void)
1399 { 1407 {
1400 RTC_HandleTypeDef RtcHandle; 1408 RTC_HandleTypeDef RtcHandle;
1401 RtcHandle.Instance = RTC; 1409 RtcHandle.Instance = RTC;
1402 __HAL_RTC_WRITEPROTECTION_DISABLE(&RtcHandle); 1410 __HAL_RTC_WRITEPROTECTION_DISABLE(&RtcHandle);
1403 HAL_RTCEx_BKUPWrite(&RtcHandle,RTC_BKP_DR0,0x00); 1411 HAL_RTCEx_BKUPWrite(&RtcHandle,RTC_BKP_DR0,0x00);
1404 __HAL_RTC_WRITEPROTECTION_ENABLE(&RtcHandle); 1412 __HAL_RTC_WRITEPROTECTION_ENABLE(&RtcHandle);
1405 } 1413 }
1406 1414
1407 #ifdef USE_FULL_ASSERT 1415 #ifdef USE_FULL_ASSERT
1408 1416
1409 /** 1417 /**
1410 * @brief Reports the name of the source file and the source line number 1418 * @brief Reports the name of the source file and the source line number
1411 * where the assert_param error has occurred. 1419 * where the assert_param error has occurred.
1412 * @param file: pointer to the source file name 1420 * @param file: pointer to the source file name
1413 * @param line: assert_param error line source number 1421 * @param line: assert_param error line source number
1414 * @retval None 1422 * @retval None
1415 */ 1423 */
1416 void assert_failed(uint8_t* file, uint32_t line) 1424 void assert_failed(uint8_t* file, uint32_t line)
1417 { 1425 {
1418 /* User can add his own implementation to report the file name and line number, 1426 /* User can add his own implementation to report the file name and line number,
1419 ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ 1427 ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
1420 1428
1421 /* Infinite loop */ 1429 /* Infinite loop */
1422 while (1) 1430 while (1)
1423 { 1431 {
1424 } 1432 }
1425 } 1433 }
1426 #endif 1434 #endif
1427 1435
1428 /* 1436 /*
1429 static void DualBootToBootloader(void) 1437 static void DualBootToBootloader(void)
1430 { 1438 {
1431 // Set BFB2 bit to enable boot from Flash Bank2 1439 // Set BFB2 bit to enable boot from Flash Bank2
1432 // Allow Access to Flash control registers and user Falsh 1440 // Allow Access to Flash control registers and user Falsh
1433 HAL_FLASH_Unlock(); 1441 HAL_FLASH_Unlock();
1434 1442
1435 // Allow Access to option bytes sector 1443 // Allow Access to option bytes sector
1436 HAL_FLASH_OB_Unlock(); 1444 HAL_FLASH_OB_Unlock();
1437 1445
1438 // Get the Dual boot configuration status 1446 // Get the Dual boot configuration status
1439 AdvOBInit.OptionType = OPTIONBYTE_BOOTCONFIG; 1447 AdvOBInit.OptionType = OPTIONBYTE_BOOTCONFIG;
1440 HAL_FLASHEx_AdvOBGetConfig(&AdvOBInit); 1448 HAL_FLASHEx_AdvOBGetConfig(&AdvOBInit);
1441 1449
1442 // Enable/Disable dual boot feature 1450 // Enable/Disable dual boot feature
1443 if (((AdvOBInit.BootConfig) & (FLASH_OPTCR_BFB2)) == FLASH_OPTCR_BFB2) 1451 if (((AdvOBInit.BootConfig) & (FLASH_OPTCR_BFB2)) == FLASH_OPTCR_BFB2)
1444 { 1452 {
1445 AdvOBInit.BootConfig = OB_DUAL_BOOT_DISABLE; 1453 AdvOBInit.BootConfig = OB_DUAL_BOOT_DISABLE;
1446 HAL_FLASHEx_AdvOBProgram (&AdvOBInit); 1454 HAL_FLASHEx_AdvOBProgram (&AdvOBInit);
1447 if (HAL_FLASH_OB_Launch() != HAL_OK)
1448 {
1449 while (1)
1450 {
1451 }
1452 }
1453 }
1454 else
1455 {
1456
1457 AdvOBInit.BootConfig = OB_DUAL_BOOT_ENABLE;
1458 HAL_FLASHEx_AdvOBProgram (&AdvOBInit);
1459 if (HAL_FLASH_OB_Launch() != HAL_OK) 1455 if (HAL_FLASH_OB_Launch() != HAL_OK)
1460 { 1456 {
1461 while (1) 1457 while (1)
1462 { 1458 {
1463 } 1459 }
1464 } 1460 }
1465 } 1461 }
1466 1462 else
1467 // Prevent Access to option bytes sector 1463 {
1468 HAL_FLASH_OB_Lock(); 1464
1469 1465 AdvOBInit.BootConfig = OB_DUAL_BOOT_ENABLE;
1470 / Disable the Flash option control register access (recommended to protect 1466 HAL_FLASHEx_AdvOBProgram (&AdvOBInit);
1471 // the option Bytes against possible unwanted operations) 1467 if (HAL_FLASH_OB_Launch() != HAL_OK)
1472 HAL_FLASH_Lock(); 1468 {
1473 1469 while (1)
1474 // Initiates a system reset request to reset the MCU 1470 {
1475 reset_to_firmware_using_Watchdog(); 1471 }
1472 }
1473 }
1474
1475 // Prevent Access to option bytes sector
1476 HAL_FLASH_OB_Lock();
1477
1478 / Disable the Flash option control register access (recommended to protect
1479 // the option Bytes against possible unwanted operations)
1480 HAL_FLASH_Lock();
1481
1482 // Initiates a system reset request to reset the MCU
1483 reset_to_firmware_using_Watchdog();
1476 } 1484 }
1477 */ 1485 */
1478 1486
1479 void reset_to_update_using_system_reset(void) 1487 void reset_to_update_using_system_reset(void)
1480 { 1488 {
1483 } 1491 }
1484 1492
1485 void reset_to_firmware_using_Watchdog(void) 1493 void reset_to_firmware_using_Watchdog(void)
1486 { 1494 {
1487 __HAL_RCC_CLEAR_RESET_FLAGS(); 1495 __HAL_RCC_CLEAR_RESET_FLAGS();
1488 __HAL_RCC_WWDG_CLK_ENABLE(); 1496 __HAL_RCC_WWDG_CLK_ENABLE();
1489 1497
1490 WWDG_HandleTypeDef WwdgHandle; 1498 WWDG_HandleTypeDef WwdgHandle;
1491 WwdgHandle.Instance = WWDG; 1499 WwdgHandle.Instance = WWDG;
1492 1500
1493 WwdgHandle.Init.Prescaler = WWDG_PRESCALER_8; 1501 WwdgHandle.Init.Prescaler = WWDG_PRESCALER_8;
1494 WwdgHandle.Init.Window = 80; 1502 WwdgHandle.Init.Window = 80;
1495 WwdgHandle.Init.Counter = 127; 1503 WwdgHandle.Init.Counter = 127;
1496 1504
1497 HAL_WWDG_Init(&WwdgHandle); 1505 HAL_WWDG_Init(&WwdgHandle);
1498 HAL_WWDG_Start(&WwdgHandle); 1506 HAL_WWDG_Start(&WwdgHandle);
1499 while(1); 1507 while(1);
1500 } 1508 }
1501 1509
1502 1510
1503 void set_returnFromComm(void) 1511 void set_returnFromComm(void)
1504 { 1512 {
1505 returnFromCommCleanUpRequest = 1; 1513 returnFromCommCleanUpRequest = 1;
1506 } 1514 }
1507 1515
1508 /**
1509 * @}
1510 */
1511
1512 /**
1513 * @}
1514 */
1515
1516 /************************ (C) COPYRIGHT heinrichs weikamp *****END OF FILE****/ 1516 /************************ (C) COPYRIGHT heinrichs weikamp *****END OF FILE****/