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comparison Common/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_utils.c @ 160:e3ca52b8e7fa

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Merge with FlipDisplay
author heinrichsweikamp
date Thu, 07 Mar 2019 15:06:43 +0100
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80:cc2bb7bb8456 160:e3ca52b8e7fa
1 /**
2 ******************************************************************************
3 * @file stm32f4xx_ll_utils.c
4 * @author MCD Application Team
5 * @brief UTILS LL module driver.
6 ******************************************************************************
7 * @attention
8 *
9 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
10 *
11 * Redistribution and use in source and binary forms, with or without modification,
12 * are permitted provided that the following conditions are met:
13 * 1. Redistributions of source code must retain the above copyright notice,
14 * this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright notice,
16 * this list of conditions and the following disclaimer in the documentation
17 * and/or other materials provided with the distribution.
18 * 3. Neither the name of STMicroelectronics nor the names of its contributors
19 * may be used to endorse or promote products derived from this software
20 * without specific prior written permission.
21 *
22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
23 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
25 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
29 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32 *
33 ******************************************************************************
34 */
35 /* Includes ------------------------------------------------------------------*/
36 #include "stm32f4xx_ll_utils.h"
37 #include "stm32f4xx_ll_rcc.h"
38 #include "stm32f4xx_ll_system.h"
39 #include "stm32f4xx_ll_pwr.h"
40 #ifdef USE_FULL_ASSERT
41 #include "stm32_assert.h"
42 #else
43 #define assert_param(expr) ((void)0U)
44 #endif /* USE_FULL_ASSERT */
45
46 /** @addtogroup STM32F4xx_LL_Driver
47 * @{
48 */
49
50 /** @addtogroup UTILS_LL
51 * @{
52 */
53
54 /* Private types -------------------------------------------------------------*/
55 /* Private variables ---------------------------------------------------------*/
56 /* Private constants ---------------------------------------------------------*/
57 /** @addtogroup UTILS_LL_Private_Constants
58 * @{
59 */
60 #if defined(RCC_MAX_FREQUENCY_SCALE1)
61 #define UTILS_MAX_FREQUENCY_SCALE1 RCC_MAX_FREQUENCY /*!< Maximum frequency for system clock at power scale1, in Hz */
62 #endif /*RCC_MAX_FREQUENCY_SCALE1 */
63 #define UTILS_MAX_FREQUENCY_SCALE2 RCC_MAX_FREQUENCY_SCALE2 /*!< Maximum frequency for system clock at power scale2, in Hz */
64 #if defined(RCC_MAX_FREQUENCY_SCALE3)
65 #define UTILS_MAX_FREQUENCY_SCALE3 RCC_MAX_FREQUENCY_SCALE3 /*!< Maximum frequency for system clock at power scale3, in Hz */
66 #endif /* MAX_FREQUENCY_SCALE3 */
67
68 /* Defines used for PLL range */
69 #define UTILS_PLLVCO_INPUT_MIN RCC_PLLVCO_INPUT_MIN /*!< Frequency min for PLLVCO input, in Hz */
70 #define UTILS_PLLVCO_INPUT_MAX RCC_PLLVCO_INPUT_MAX /*!< Frequency max for PLLVCO input, in Hz */
71 #define UTILS_PLLVCO_OUTPUT_MIN RCC_PLLVCO_OUTPUT_MIN /*!< Frequency min for PLLVCO output, in Hz */
72 #define UTILS_PLLVCO_OUTPUT_MAX RCC_PLLVCO_OUTPUT_MAX /*!< Frequency max for PLLVCO output, in Hz */
73
74 /* Defines used for HSE range */
75 #define UTILS_HSE_FREQUENCY_MIN 4000000U /*!< Frequency min for HSE frequency, in Hz */
76 #define UTILS_HSE_FREQUENCY_MAX 26000000U /*!< Frequency max for HSE frequency, in Hz */
77
78 /* Defines used for FLASH latency according to HCLK Frequency */
79 #if defined(FLASH_SCALE1_LATENCY1_FREQ)
80 #define UTILS_SCALE1_LATENCY1_FREQ FLASH_SCALE1_LATENCY1_FREQ /*!< HCLK frequency to set FLASH latency 1 in power scale 1 */
81 #endif
82 #if defined(FLASH_SCALE1_LATENCY2_FREQ)
83 #define UTILS_SCALE1_LATENCY2_FREQ FLASH_SCALE1_LATENCY2_FREQ /*!< HCLK frequency to set FLASH latency 2 in power scale 1 */
84 #endif
85 #if defined(FLASH_SCALE1_LATENCY3_FREQ)
86 #define UTILS_SCALE1_LATENCY3_FREQ FLASH_SCALE1_LATENCY3_FREQ /*!< HCLK frequency to set FLASH latency 3 in power scale 1 */
87 #endif
88 #if defined(FLASH_SCALE1_LATENCY4_FREQ)
89 #define UTILS_SCALE1_LATENCY4_FREQ FLASH_SCALE1_LATENCY4_FREQ /*!< HCLK frequency to set FLASH latency 4 in power scale 1 */
90 #endif
91 #if defined(FLASH_SCALE1_LATENCY5_FREQ)
92 #define UTILS_SCALE1_LATENCY5_FREQ FLASH_SCALE1_LATENCY5_FREQ /*!< HCLK frequency to set FLASH latency 5 in power scale 1 */
93 #endif
94 #define UTILS_SCALE2_LATENCY1_FREQ FLASH_SCALE2_LATENCY1_FREQ /*!< HCLK frequency to set FLASH latency 1 in power scale 2 */
95 #define UTILS_SCALE2_LATENCY2_FREQ FLASH_SCALE2_LATENCY2_FREQ /*!< HCLK frequency to set FLASH latency 2 in power scale 2 */
96 #if defined(FLASH_SCALE2_LATENCY3_FREQ)
97 #define UTILS_SCALE2_LATENCY3_FREQ FLASH_SCALE2_LATENCY3_FREQ /*!< HCLK frequency to set FLASH latency 2 in power scale 2 */
98 #endif
99 #if defined(FLASH_SCALE2_LATENCY4_FREQ)
100 #define UTILS_SCALE2_LATENCY4_FREQ FLASH_SCALE2_LATENCY4_FREQ /*!< HCLK frequency to set FLASH latency 4 in power scale 2 */
101 #endif
102 #if defined(FLASH_SCALE2_LATENCY5_FREQ)
103 #define UTILS_SCALE2_LATENCY5_FREQ FLASH_SCALE2_LATENCY5_FREQ /*!< HCLK frequency to set FLASH latency 5 in power scale 2 */
104 #endif
105 #if defined(FLASH_SCALE3_LATENCY1_FREQ)
106 #define UTILS_SCALE3_LATENCY1_FREQ FLASH_SCALE3_LATENCY1_FREQ /*!< HCLK frequency to set FLASH latency 1 in power scale 3 */
107 #endif
108 #if defined(FLASH_SCALE3_LATENCY2_FREQ)
109 #define UTILS_SCALE3_LATENCY2_FREQ FLASH_SCALE3_LATENCY2_FREQ /*!< HCLK frequency to set FLASH latency 2 in power scale 3 */
110 #endif
111 #if defined(FLASH_SCALE3_LATENCY3_FREQ)
112 #define UTILS_SCALE3_LATENCY3_FREQ FLASH_SCALE3_LATENCY3_FREQ /*!< HCLK frequency to set FLASH latency 3 in power scale 3 */
113 #endif
114 #if defined(FLASH_SCALE3_LATENCY4_FREQ)
115 #define UTILS_SCALE3_LATENCY4_FREQ FLASH_SCALE3_LATENCY4_FREQ /*!< HCLK frequency to set FLASH latency 4 in power scale 3 */
116 #endif
117 #if defined(FLASH_SCALE3_LATENCY5_FREQ)
118 #define UTILS_SCALE3_LATENCY5_FREQ FLASH_SCALE3_LATENCY5_FREQ /*!< HCLK frequency to set FLASH latency 5 in power scale 3 */
119 #endif
120 /**
121 * @}
122 */
123
124 /* Private macros ------------------------------------------------------------*/
125 /** @addtogroup UTILS_LL_Private_Macros
126 * @{
127 */
128 #define IS_LL_UTILS_SYSCLK_DIV(__VALUE__) (((__VALUE__) == LL_RCC_SYSCLK_DIV_1) \
129 || ((__VALUE__) == LL_RCC_SYSCLK_DIV_2) \
130 || ((__VALUE__) == LL_RCC_SYSCLK_DIV_4) \
131 || ((__VALUE__) == LL_RCC_SYSCLK_DIV_8) \
132 || ((__VALUE__) == LL_RCC_SYSCLK_DIV_16) \
133 || ((__VALUE__) == LL_RCC_SYSCLK_DIV_64) \
134 || ((__VALUE__) == LL_RCC_SYSCLK_DIV_128) \
135 || ((__VALUE__) == LL_RCC_SYSCLK_DIV_256) \
136 || ((__VALUE__) == LL_RCC_SYSCLK_DIV_512))
137
138 #define IS_LL_UTILS_APB1_DIV(__VALUE__) (((__VALUE__) == LL_RCC_APB1_DIV_1) \
139 || ((__VALUE__) == LL_RCC_APB1_DIV_2) \
140 || ((__VALUE__) == LL_RCC_APB1_DIV_4) \
141 || ((__VALUE__) == LL_RCC_APB1_DIV_8) \
142 || ((__VALUE__) == LL_RCC_APB1_DIV_16))
143
144 #define IS_LL_UTILS_APB2_DIV(__VALUE__) (((__VALUE__) == LL_RCC_APB2_DIV_1) \
145 || ((__VALUE__) == LL_RCC_APB2_DIV_2) \
146 || ((__VALUE__) == LL_RCC_APB2_DIV_4) \
147 || ((__VALUE__) == LL_RCC_APB2_DIV_8) \
148 || ((__VALUE__) == LL_RCC_APB2_DIV_16))
149
150 #define IS_LL_UTILS_PLLM_VALUE(__VALUE__) (((__VALUE__) == LL_RCC_PLLM_DIV_2) \
151 || ((__VALUE__) == LL_RCC_PLLM_DIV_3) \
152 || ((__VALUE__) == LL_RCC_PLLM_DIV_4) \
153 || ((__VALUE__) == LL_RCC_PLLM_DIV_5) \
154 || ((__VALUE__) == LL_RCC_PLLM_DIV_6) \
155 || ((__VALUE__) == LL_RCC_PLLM_DIV_7) \
156 || ((__VALUE__) == LL_RCC_PLLM_DIV_8) \
157 || ((__VALUE__) == LL_RCC_PLLM_DIV_9) \
158 || ((__VALUE__) == LL_RCC_PLLM_DIV_10) \
159 || ((__VALUE__) == LL_RCC_PLLM_DIV_11) \
160 || ((__VALUE__) == LL_RCC_PLLM_DIV_12) \
161 || ((__VALUE__) == LL_RCC_PLLM_DIV_13) \
162 || ((__VALUE__) == LL_RCC_PLLM_DIV_14) \
163 || ((__VALUE__) == LL_RCC_PLLM_DIV_15) \
164 || ((__VALUE__) == LL_RCC_PLLM_DIV_16) \
165 || ((__VALUE__) == LL_RCC_PLLM_DIV_17) \
166 || ((__VALUE__) == LL_RCC_PLLM_DIV_18) \
167 || ((__VALUE__) == LL_RCC_PLLM_DIV_19) \
168 || ((__VALUE__) == LL_RCC_PLLM_DIV_20) \
169 || ((__VALUE__) == LL_RCC_PLLM_DIV_21) \
170 || ((__VALUE__) == LL_RCC_PLLM_DIV_22) \
171 || ((__VALUE__) == LL_RCC_PLLM_DIV_23) \
172 || ((__VALUE__) == LL_RCC_PLLM_DIV_24) \
173 || ((__VALUE__) == LL_RCC_PLLM_DIV_25) \
174 || ((__VALUE__) == LL_RCC_PLLM_DIV_26) \
175 || ((__VALUE__) == LL_RCC_PLLM_DIV_27) \
176 || ((__VALUE__) == LL_RCC_PLLM_DIV_28) \
177 || ((__VALUE__) == LL_RCC_PLLM_DIV_29) \
178 || ((__VALUE__) == LL_RCC_PLLM_DIV_30) \
179 || ((__VALUE__) == LL_RCC_PLLM_DIV_31) \
180 || ((__VALUE__) == LL_RCC_PLLM_DIV_32) \
181 || ((__VALUE__) == LL_RCC_PLLM_DIV_33) \
182 || ((__VALUE__) == LL_RCC_PLLM_DIV_34) \
183 || ((__VALUE__) == LL_RCC_PLLM_DIV_35) \
184 || ((__VALUE__) == LL_RCC_PLLM_DIV_36) \
185 || ((__VALUE__) == LL_RCC_PLLM_DIV_37) \
186 || ((__VALUE__) == LL_RCC_PLLM_DIV_38) \
187 || ((__VALUE__) == LL_RCC_PLLM_DIV_39) \
188 || ((__VALUE__) == LL_RCC_PLLM_DIV_40) \
189 || ((__VALUE__) == LL_RCC_PLLM_DIV_41) \
190 || ((__VALUE__) == LL_RCC_PLLM_DIV_42) \
191 || ((__VALUE__) == LL_RCC_PLLM_DIV_43) \
192 || ((__VALUE__) == LL_RCC_PLLM_DIV_44) \
193 || ((__VALUE__) == LL_RCC_PLLM_DIV_45) \
194 || ((__VALUE__) == LL_RCC_PLLM_DIV_46) \
195 || ((__VALUE__) == LL_RCC_PLLM_DIV_47) \
196 || ((__VALUE__) == LL_RCC_PLLM_DIV_48) \
197 || ((__VALUE__) == LL_RCC_PLLM_DIV_49) \
198 || ((__VALUE__) == LL_RCC_PLLM_DIV_50) \
199 || ((__VALUE__) == LL_RCC_PLLM_DIV_51) \
200 || ((__VALUE__) == LL_RCC_PLLM_DIV_52) \
201 || ((__VALUE__) == LL_RCC_PLLM_DIV_53) \
202 || ((__VALUE__) == LL_RCC_PLLM_DIV_54) \
203 || ((__VALUE__) == LL_RCC_PLLM_DIV_55) \
204 || ((__VALUE__) == LL_RCC_PLLM_DIV_56) \
205 || ((__VALUE__) == LL_RCC_PLLM_DIV_57) \
206 || ((__VALUE__) == LL_RCC_PLLM_DIV_58) \
207 || ((__VALUE__) == LL_RCC_PLLM_DIV_59) \
208 || ((__VALUE__) == LL_RCC_PLLM_DIV_60) \
209 || ((__VALUE__) == LL_RCC_PLLM_DIV_61) \
210 || ((__VALUE__) == LL_RCC_PLLM_DIV_62) \
211 || ((__VALUE__) == LL_RCC_PLLM_DIV_63))
212
213 #define IS_LL_UTILS_PLLN_VALUE(__VALUE__) ((RCC_PLLN_MIN_VALUE <= (__VALUE__)) && ((__VALUE__) <= RCC_PLLN_MAX_VALUE))
214
215 #define IS_LL_UTILS_PLLP_VALUE(__VALUE__) (((__VALUE__) == LL_RCC_PLLP_DIV_2) \
216 || ((__VALUE__) == LL_RCC_PLLP_DIV_4) \
217 || ((__VALUE__) == LL_RCC_PLLP_DIV_6) \
218 || ((__VALUE__) == LL_RCC_PLLP_DIV_8))
219
220 #define IS_LL_UTILS_PLLVCO_INPUT(__VALUE__) ((UTILS_PLLVCO_INPUT_MIN <= (__VALUE__)) && ((__VALUE__) <= UTILS_PLLVCO_INPUT_MAX))
221
222 #define IS_LL_UTILS_PLLVCO_OUTPUT(__VALUE__) ((UTILS_PLLVCO_OUTPUT_MIN <= (__VALUE__)) && ((__VALUE__) <= UTILS_PLLVCO_OUTPUT_MAX))
223
224 #if !defined(RCC_MAX_FREQUENCY_SCALE1)
225 #define IS_LL_UTILS_PLL_FREQUENCY(__VALUE__) ((LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE2) ? ((__VALUE__) <= UTILS_MAX_FREQUENCY_SCALE2) : \
226 ((__VALUE__) <= UTILS_MAX_FREQUENCY_SCALE3))
227
228 #elif defined(RCC_MAX_FREQUENCY_SCALE3)
229 #define IS_LL_UTILS_PLL_FREQUENCY(__VALUE__) ((LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE1) ? ((__VALUE__) <= UTILS_MAX_FREQUENCY_SCALE1) : \
230 (LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE2) ? ((__VALUE__) <= UTILS_MAX_FREQUENCY_SCALE2) : \
231 ((__VALUE__) <= UTILS_MAX_FREQUENCY_SCALE3))
232
233 #else
234 #define IS_LL_UTILS_PLL_FREQUENCY(__VALUE__) ((LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE1) ? ((__VALUE__) <= UTILS_MAX_FREQUENCY_SCALE1) : \
235 ((__VALUE__) <= UTILS_MAX_FREQUENCY_SCALE2))
236
237 #endif /* RCC_MAX_FREQUENCY_SCALE1*/
238 #define IS_LL_UTILS_HSE_BYPASS(__STATE__) (((__STATE__) == LL_UTILS_HSEBYPASS_ON) \
239 || ((__STATE__) == LL_UTILS_HSEBYPASS_OFF))
240
241 #define IS_LL_UTILS_HSE_FREQUENCY(__FREQUENCY__) (((__FREQUENCY__) >= UTILS_HSE_FREQUENCY_MIN) && ((__FREQUENCY__) <= UTILS_HSE_FREQUENCY_MAX))
242 /**
243 * @}
244 */
245 /* Private function prototypes -----------------------------------------------*/
246 /** @defgroup UTILS_LL_Private_Functions UTILS Private functions
247 * @{
248 */
249 static uint32_t UTILS_GetPLLOutputFrequency(uint32_t PLL_InputFrequency,
250 LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct);
251 static ErrorStatus UTILS_SetFlashLatency(uint32_t HCLK_Frequency);
252 static ErrorStatus UTILS_EnablePLLAndSwitchSystem(uint32_t SYSCLK_Frequency, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct);
253 static ErrorStatus UTILS_PLL_IsBusy(void);
254 /**
255 * @}
256 */
257
258 /* Exported functions --------------------------------------------------------*/
259 /** @addtogroup UTILS_LL_Exported_Functions
260 * @{
261 */
262
263 /** @addtogroup UTILS_LL_EF_DELAY
264 * @{
265 */
266
267 /**
268 * @brief This function configures the Cortex-M SysTick source to have 1ms time base.
269 * @note When a RTOS is used, it is recommended to avoid changing the Systick
270 * configuration by calling this function, for a delay use rather osDelay RTOS service.
271 * @param HCLKFrequency HCLK frequency in Hz
272 * @note HCLK frequency can be calculated thanks to RCC helper macro or function @ref LL_RCC_GetSystemClocksFreq
273 * @retval None
274 */
275 void LL_Init1msTick(uint32_t HCLKFrequency)
276 {
277 /* Use frequency provided in argument */
278 LL_InitTick(HCLKFrequency, 1000U);
279 }
280
281 /**
282 * @brief This function provides accurate delay (in milliseconds) based
283 * on SysTick counter flag
284 * @note When a RTOS is used, it is recommended to avoid using blocking delay
285 * and use rather osDelay service.
286 * @note To respect 1ms timebase, user should call @ref LL_Init1msTick function which
287 * will configure Systick to 1ms
288 * @param Delay specifies the delay time length, in milliseconds.
289 * @retval None
290 */
291 void LL_mDelay(uint32_t Delay)
292 {
293 __IO uint32_t tmp = SysTick->CTRL; /* Clear the COUNTFLAG first */
294 /* Add this code to indicate that local variable is not used */
295 ((void)tmp);
296
297 /* Add a period to guaranty minimum wait */
298 if(Delay < LL_MAX_DELAY)
299 {
300 Delay++;
301 }
302
303 while (Delay)
304 {
305 if((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) != 0U)
306 {
307 Delay--;
308 }
309 }
310 }
311
312 /**
313 * @}
314 */
315
316 /** @addtogroup UTILS_EF_SYSTEM
317 * @brief System Configuration functions
318 *
319 @verbatim
320 ===============================================================================
321 ##### System Configuration functions #####
322 ===============================================================================
323 [..]
324 System, AHB and APB buses clocks configuration
325
326 (+) The maximum frequency of the SYSCLK, HCLK, PCLK1 and PCLK2 is 180000000 Hz.
327 @endverbatim
328 @internal
329 Depending on the device voltage range, the maximum frequency should be
330 adapted accordingly to the Refenece manual.
331 @endinternal
332 * @{
333 */
334
335 /**
336 * @brief This function sets directly SystemCoreClock CMSIS variable.
337 * @note Variable can be calculated also through SystemCoreClockUpdate function.
338 * @param HCLKFrequency HCLK frequency in Hz (can be calculated thanks to RCC helper macro)
339 * @retval None
340 */
341 void LL_SetSystemCoreClock(uint32_t HCLKFrequency)
342 {
343 /* HCLK clock frequency */
344 SystemCoreClock = HCLKFrequency;
345 }
346
347 /**
348 * @brief This function configures system clock at maximum frequency with HSI as clock source of the PLL
349 * @note The application need to ensure that PLL is disabled.
350 * @note Function is based on the following formula:
351 * - PLL output frequency = (((HSI frequency / PLLM) * PLLN) / PLLP)
352 * - PLLM: ensure that the VCO input frequency ranges from @ref RCC_PLLVCO_INPUT_MIN to @ref RCC_PLLVCO_INPUT_MAX (PLLVCO_input = HSI frequency / PLLM)
353 * - PLLN: ensure that the VCO output frequency is between @ref RCC_PLLVCO_OUTPUT_MIN and @ref RCC_PLLVCO_OUTPUT_MAX (PLLVCO_output = PLLVCO_input * PLLN)
354 * - PLLP: ensure that max frequency at 180000000 Hz is reach (PLLVCO_output / PLLP)
355 * @param UTILS_PLLInitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains
356 * the configuration information for the PLL.
357 * @param UTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains
358 * the configuration information for the BUS prescalers.
359 * @retval An ErrorStatus enumeration value:
360 * - SUCCESS: Max frequency configuration done
361 * - ERROR: Max frequency configuration not done
362 */
363 ErrorStatus LL_PLL_ConfigSystemClock_HSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct,
364 LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct)
365 {
366 ErrorStatus status = SUCCESS;
367 uint32_t pllfreq = 0U;
368
369 /* Check if one of the PLL is enabled */
370 if(UTILS_PLL_IsBusy() == SUCCESS)
371 {
372 /* Calculate the new PLL output frequency */
373 pllfreq = UTILS_GetPLLOutputFrequency(HSI_VALUE, UTILS_PLLInitStruct);
374
375 /* Enable HSI if not enabled */
376 if(LL_RCC_HSI_IsReady() != 1U)
377 {
378 LL_RCC_HSI_Enable();
379 while (LL_RCC_HSI_IsReady() != 1U)
380 {
381 /* Wait for HSI ready */
382 }
383 }
384
385 /* Configure PLL */
386 LL_RCC_PLL_ConfigDomain_SYS(LL_RCC_PLLSOURCE_HSI, UTILS_PLLInitStruct->PLLM, UTILS_PLLInitStruct->PLLN,
387 UTILS_PLLInitStruct->PLLP);
388
389 /* Enable PLL and switch system clock to PLL */
390 status = UTILS_EnablePLLAndSwitchSystem(pllfreq, UTILS_ClkInitStruct);
391 }
392 else
393 {
394 /* Current PLL configuration cannot be modified */
395 status = ERROR;
396 }
397
398 return status;
399 }
400
401 /**
402 * @brief This function configures system clock with HSE as clock source of the PLL
403 * @note The application need to ensure that PLL is disabled.
404 * - PLL output frequency = (((HSI frequency / PLLM) * PLLN) / PLLP)
405 * - PLLM: ensure that the VCO input frequency ranges from @ref RCC_PLLVCO_INPUT_MIN to @ref RCC_PLLVCO_INPUT_MAX (PLLVCO_input = HSI frequency / PLLM)
406 * - PLLN: ensure that the VCO output frequency is between @ref RCC_PLLVCO_OUTPUT_MIN and @ref RCC_PLLVCO_OUTPUT_MAX (PLLVCO_output = PLLVCO_input * PLLN)
407 * - PLLP: ensure that max frequency at 180000000 Hz is reach (PLLVCO_output / PLLP)
408 * @param HSEFrequency Value between Min_Data = 4000000 and Max_Data = 26000000
409 * @param HSEBypass This parameter can be one of the following values:
410 * @arg @ref LL_UTILS_HSEBYPASS_ON
411 * @arg @ref LL_UTILS_HSEBYPASS_OFF
412 * @param UTILS_PLLInitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains
413 * the configuration information for the PLL.
414 * @param UTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains
415 * the configuration information for the BUS prescalers.
416 * @retval An ErrorStatus enumeration value:
417 * - SUCCESS: Max frequency configuration done
418 * - ERROR: Max frequency configuration not done
419 */
420 ErrorStatus LL_PLL_ConfigSystemClock_HSE(uint32_t HSEFrequency, uint32_t HSEBypass,
421 LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct)
422 {
423 ErrorStatus status = SUCCESS;
424 uint32_t pllfreq = 0U;
425
426 /* Check the parameters */
427 assert_param(IS_LL_UTILS_HSE_FREQUENCY(HSEFrequency));
428 assert_param(IS_LL_UTILS_HSE_BYPASS(HSEBypass));
429
430 /* Check if one of the PLL is enabled */
431 if(UTILS_PLL_IsBusy() == SUCCESS)
432 {
433 /* Calculate the new PLL output frequency */
434 pllfreq = UTILS_GetPLLOutputFrequency(HSEFrequency, UTILS_PLLInitStruct);
435
436 /* Enable HSE if not enabled */
437 if(LL_RCC_HSE_IsReady() != 1U)
438 {
439 /* Check if need to enable HSE bypass feature or not */
440 if(HSEBypass == LL_UTILS_HSEBYPASS_ON)
441 {
442 LL_RCC_HSE_EnableBypass();
443 }
444 else
445 {
446 LL_RCC_HSE_DisableBypass();
447 }
448
449 /* Enable HSE */
450 LL_RCC_HSE_Enable();
451 while (LL_RCC_HSE_IsReady() != 1U)
452 {
453 /* Wait for HSE ready */
454 }
455 }
456
457 /* Configure PLL */
458 LL_RCC_PLL_ConfigDomain_SYS(LL_RCC_PLLSOURCE_HSE, UTILS_PLLInitStruct->PLLM, UTILS_PLLInitStruct->PLLN,
459 UTILS_PLLInitStruct->PLLP);
460
461 /* Enable PLL and switch system clock to PLL */
462 status = UTILS_EnablePLLAndSwitchSystem(pllfreq, UTILS_ClkInitStruct);
463 }
464 else
465 {
466 /* Current PLL configuration cannot be modified */
467 status = ERROR;
468 }
469
470 return status;
471 }
472
473 /**
474 * @}
475 */
476
477 /**
478 * @}
479 */
480
481 /** @addtogroup UTILS_LL_Private_Functions
482 * @{
483 */
484 /**
485 * @brief Update number of Flash wait states in line with new frequency and current
486 voltage range.
487 * @note This Function support ONLY devices with supply voltage (voltage range) between 2.7V and 3.6V
488 * @param HCLK_Frequency HCLK frequency
489 * @retval An ErrorStatus enumeration value:
490 * - SUCCESS: Latency has been modified
491 * - ERROR: Latency cannot be modified
492 */
493 static ErrorStatus UTILS_SetFlashLatency(uint32_t HCLK_Frequency)
494 {
495 ErrorStatus status = SUCCESS;
496
497 uint32_t latency = LL_FLASH_LATENCY_0; /* default value 0WS */
498
499 /* Frequency cannot be equal to 0 */
500 if(HCLK_Frequency == 0U)
501 {
502 status = ERROR;
503 }
504 else
505 {
506 if(LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE1)
507 {
508 #if defined (UTILS_SCALE1_LATENCY5_FREQ)
509 if((HCLK_Frequency > UTILS_SCALE1_LATENCY5_FREQ)&&(latency == LL_FLASH_LATENCY_0))
510 {
511 latency = LL_FLASH_LATENCY_5;
512 }
513 #endif /*UTILS_SCALE1_LATENCY5_FREQ */
514 #if defined (UTILS_SCALE1_LATENCY4_FREQ)
515 if((HCLK_Frequency > UTILS_SCALE1_LATENCY4_FREQ)&&(latency == LL_FLASH_LATENCY_0))
516 {
517 latency = LL_FLASH_LATENCY_4;
518 }
519 #endif /* UTILS_SCALE1_LATENCY4_FREQ */
520 #if defined (UTILS_SCALE1_LATENCY3_FREQ)
521 if((HCLK_Frequency > UTILS_SCALE1_LATENCY3_FREQ)&&(latency == LL_FLASH_LATENCY_0))
522 {
523 latency = LL_FLASH_LATENCY_3;
524 }
525 #endif /* UTILS_SCALE1_LATENCY3_FREQ */
526 #if defined (UTILS_SCALE1_LATENCY2_FREQ)
527 if((HCLK_Frequency > UTILS_SCALE1_LATENCY2_FREQ)&&(latency == LL_FLASH_LATENCY_0))
528 {
529 latency = LL_FLASH_LATENCY_2;
530 }
531 else
532 {
533 if((HCLK_Frequency > UTILS_SCALE1_LATENCY1_FREQ)&&(latency == LL_FLASH_LATENCY_0))
534 {
535 latency = LL_FLASH_LATENCY_1;
536 }
537 }
538 #endif /* UTILS_SCALE1_LATENCY2_FREQ */
539 }
540 if(LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE2)
541 {
542 #if defined (UTILS_SCALE2_LATENCY5_FREQ)
543 if((HCLK_Frequency > UTILS_SCALE2_LATENCY5_FREQ)&&(latency == LL_FLASH_LATENCY_0))
544 {
545 latency = LL_FLASH_LATENCY_5;
546 }
547 #endif /*UTILS_SCALE1_LATENCY5_FREQ */
548 #if defined (UTILS_SCALE2_LATENCY4_FREQ)
549 if((HCLK_Frequency > UTILS_SCALE2_LATENCY4_FREQ)&&(latency == LL_FLASH_LATENCY_0))
550 {
551 latency = LL_FLASH_LATENCY_4;
552 }
553 #endif /*UTILS_SCALE1_LATENCY4_FREQ */
554 #if defined (UTILS_SCALE2_LATENCY3_FREQ)
555 if((HCLK_Frequency > UTILS_SCALE2_LATENCY3_FREQ)&&(latency == LL_FLASH_LATENCY_0))
556 {
557 latency = LL_FLASH_LATENCY_3;
558 }
559 #endif /*UTILS_SCALE1_LATENCY3_FREQ */
560 if((HCLK_Frequency > UTILS_SCALE2_LATENCY2_FREQ)&&(latency == LL_FLASH_LATENCY_0))
561 {
562 latency = LL_FLASH_LATENCY_2;
563 }
564 else
565 {
566 if((HCLK_Frequency > UTILS_SCALE2_LATENCY1_FREQ)&&(latency == LL_FLASH_LATENCY_0))
567 {
568 latency = LL_FLASH_LATENCY_1;
569 }
570 }
571 }
572 #if defined (LL_PWR_REGU_VOLTAGE_SCALE3)
573 if(LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE3)
574 {
575 #if defined (UTILS_SCALE3_LATENCY3_FREQ)
576 if((HCLK_Frequency > UTILS_SCALE3_LATENCY3_FREQ)&&(latency == LL_FLASH_LATENCY_0))
577 {
578 latency = LL_FLASH_LATENCY_3;
579 }
580 #endif /*UTILS_SCALE1_LATENCY3_FREQ */
581 #if defined (UTILS_SCALE3_LATENCY2_FREQ)
582 if((HCLK_Frequency > UTILS_SCALE3_LATENCY2_FREQ)&&(latency == LL_FLASH_LATENCY_0))
583 {
584 latency = LL_FLASH_LATENCY_2;
585 }
586 else
587 {
588 if((HCLK_Frequency > UTILS_SCALE3_LATENCY1_FREQ)&&(latency == LL_FLASH_LATENCY_0))
589 {
590 latency = LL_FLASH_LATENCY_1;
591 }
592 }
593 }
594 #endif /*UTILS_SCALE1_LATENCY2_FREQ */
595 #endif /* LL_PWR_REGU_VOLTAGE_SCALE3 */
596
597 LL_FLASH_SetLatency(latency);
598
599 /* Check that the new number of wait states is taken into account to access the Flash
600 memory by reading the FLASH_ACR register */
601 if(LL_FLASH_GetLatency() != latency)
602 {
603 status = ERROR;
604 }
605 }
606 return status;
607 }
608
609 /**
610 * @brief Function to check that PLL can be modified
611 * @param PLL_InputFrequency PLL input frequency (in Hz)
612 * @param UTILS_PLLInitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains
613 * the configuration information for the PLL.
614 * @retval PLL output frequency (in Hz)
615 */
616 static uint32_t UTILS_GetPLLOutputFrequency(uint32_t PLL_InputFrequency, LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct)
617 {
618 uint32_t pllfreq = 0U;
619
620 /* Check the parameters */
621 assert_param(IS_LL_UTILS_PLLM_VALUE(UTILS_PLLInitStruct->PLLM));
622 assert_param(IS_LL_UTILS_PLLN_VALUE(UTILS_PLLInitStruct->PLLN));
623 assert_param(IS_LL_UTILS_PLLP_VALUE(UTILS_PLLInitStruct->PLLP));
624
625 /* Check different PLL parameters according to RM */
626 /* - PLLM: ensure that the VCO input frequency ranges from @ref UTILS_PLLVCO_INPUT_MIN to @ref UTILS_PLLVCO_INPUT_MAX MHz. */
627 pllfreq = PLL_InputFrequency / (UTILS_PLLInitStruct->PLLM & (RCC_PLLCFGR_PLLM >> RCC_PLLCFGR_PLLM_Pos));
628 assert_param(IS_LL_UTILS_PLLVCO_INPUT(pllfreq));
629
630 /* - PLLN: ensure that the VCO output frequency is between @ref UTILS_PLLVCO_OUTPUT_MIN and @ref UTILS_PLLVCO_OUTPUT_MAX .*/
631 pllfreq = pllfreq * (UTILS_PLLInitStruct->PLLN & (RCC_PLLCFGR_PLLN >> RCC_PLLCFGR_PLLN_Pos));
632 assert_param(IS_LL_UTILS_PLLVCO_OUTPUT(pllfreq));
633
634 /* - PLLP: ensure that max frequency at @ref RCC_MAX_FREQUENCY Hz is reached */
635 pllfreq = pllfreq / (((UTILS_PLLInitStruct->PLLP >> RCC_PLLCFGR_PLLP_Pos) + 1) * 2);
636 assert_param(IS_LL_UTILS_PLL_FREQUENCY(pllfreq));
637
638 return pllfreq;
639 }
640
641 /**
642 * @brief Function to check that PLL can be modified
643 * @retval An ErrorStatus enumeration value:
644 * - SUCCESS: PLL modification can be done
645 * - ERROR: PLL is busy
646 */
647 static ErrorStatus UTILS_PLL_IsBusy(void)
648 {
649 ErrorStatus status = SUCCESS;
650
651 /* Check if PLL is busy*/
652 if(LL_RCC_PLL_IsReady() != 0U)
653 {
654 /* PLL configuration cannot be modified */
655 status = ERROR;
656 }
657
658 #if defined(RCC_PLLSAI_SUPPORT)
659 /* Check if PLLSAI is busy*/
660 if(LL_RCC_PLLSAI_IsReady() != 0U)
661 {
662 /* PLLSAI1 configuration cannot be modified */
663 status = ERROR;
664 }
665 #endif /*RCC_PLLSAI_SUPPORT*/
666 #if defined(RCC_PLLI2S_SUPPORT)
667 /* Check if PLLI2S is busy*/
668 if(LL_RCC_PLLI2S_IsReady() != 0U)
669 {
670 /* PLLI2S configuration cannot be modified */
671 status = ERROR;
672 }
673 #endif /*RCC_PLLI2S_SUPPORT*/
674 return status;
675 }
676
677 /**
678 * @brief Function to enable PLL and switch system clock to PLL
679 * @param SYSCLK_Frequency SYSCLK frequency
680 * @param UTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains
681 * the configuration information for the BUS prescalers.
682 * @retval An ErrorStatus enumeration value:
683 * - SUCCESS: No problem to switch system to PLL
684 * - ERROR: Problem to switch system to PLL
685 */
686 static ErrorStatus UTILS_EnablePLLAndSwitchSystem(uint32_t SYSCLK_Frequency, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct)
687 {
688 ErrorStatus status = SUCCESS;
689 uint32_t hclk_frequency = 0U;
690
691 assert_param(IS_LL_UTILS_SYSCLK_DIV(UTILS_ClkInitStruct->AHBCLKDivider));
692 assert_param(IS_LL_UTILS_APB1_DIV(UTILS_ClkInitStruct->APB1CLKDivider));
693 assert_param(IS_LL_UTILS_APB2_DIV(UTILS_ClkInitStruct->APB2CLKDivider));
694
695 /* Calculate HCLK frequency */
696 hclk_frequency = __LL_RCC_CALC_HCLK_FREQ(SYSCLK_Frequency, UTILS_ClkInitStruct->AHBCLKDivider);
697
698 /* Increasing the number of wait states because of higher CPU frequency */
699 if(SystemCoreClock < hclk_frequency)
700 {
701 /* Set FLASH latency to highest latency */
702 status = UTILS_SetFlashLatency(hclk_frequency);
703 }
704
705 /* Update system clock configuration */
706 if(status == SUCCESS)
707 {
708 /* Enable PLL */
709 LL_RCC_PLL_Enable();
710 while (LL_RCC_PLL_IsReady() != 1U)
711 {
712 /* Wait for PLL ready */
713 }
714
715 /* Sysclk activation on the main PLL */
716 LL_RCC_SetAHBPrescaler(UTILS_ClkInitStruct->AHBCLKDivider);
717 LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_PLL);
718 while (LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_PLL)
719 {
720 /* Wait for system clock switch to PLL */
721 }
722
723 /* Set APB1 & APB2 prescaler*/
724 LL_RCC_SetAPB1Prescaler(UTILS_ClkInitStruct->APB1CLKDivider);
725 LL_RCC_SetAPB2Prescaler(UTILS_ClkInitStruct->APB2CLKDivider);
726 }
727
728 /* Decreasing the number of wait states because of lower CPU frequency */
729 if(SystemCoreClock > hclk_frequency)
730 {
731 /* Set FLASH latency to lowest latency */
732 status = UTILS_SetFlashLatency(hclk_frequency);
733 }
734
735 /* Update SystemCoreClock variable */
736 if(status == SUCCESS)
737 {
738 LL_SetSystemCoreClock(hclk_frequency);
739 }
740
741 return status;
742 }
743
744 /**
745 * @}
746 */
747
748 /**
749 * @}
750 */
751
752 /**
753 * @}
754 */
755
756 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/