Mercurial > public > ostc4

comparison Common/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_fmc.c @ 160:e3ca52b8e7fa

Find changesets by keywords (author, files, the commit message), revision number or hash, or revset expression.
Merge with FlipDisplay
author heinrichsweikamp
date Thu, 07 Mar 2019 15:06:43 +0100
parents c78bcbd5deda
children
comparison
equal deleted inserted replaced
80:cc2bb7bb8456 160:e3ca52b8e7fa
1 /**
2 ******************************************************************************
3 * @file stm32f4xx_ll_fmc.c
4 * @author MCD Application Team
5 * @brief FMC Low Layer HAL module driver.
6 *
7 * This file provides firmware functions to manage the following
8 * functionalities of the Flexible Memory Controller (FMC) peripheral memories:
9 * + Initialization/de-initialization functions
10 * + Peripheral Control functions
11 * + Peripheral State functions
12 *
13 @verbatim
14 ==============================================================================
15 ##### FMC peripheral features #####
16 ==============================================================================
17 [..] The Flexible memory controller (FMC) includes three memory controllers:
18 (+) The NOR/PSRAM memory controller
19 (+) The NAND/PC Card memory controller
20 (+) The Synchronous DRAM (SDRAM) controller
21
22 [..] The FMC functional block makes the interface with synchronous and asynchronous static
23 memories, SDRAM memories, and 16-bit PC memory cards. Its main purposes are:
24 (+) to translate AHB transactions into the appropriate external device protocol
25 (+) to meet the access time requirements of the external memory devices
26
27 [..] All external memories share the addresses, data and control signals with the controller.
28 Each external device is accessed by means of a unique Chip Select. The FMC performs
29 only one access at a time to an external device.
30 The main features of the FMC controller are the following:
31 (+) Interface with static-memory mapped devices including:
32 (++) Static random access memory (SRAM)
33 (++) Read-only memory (ROM)
34 (++) NOR Flash memory/OneNAND Flash memory
35 (++) PSRAM (4 memory banks)
36 (++) 16-bit PC Card compatible devices
37 (++) Two banks of NAND Flash memory with ECC hardware to check up to 8 Kbytes of
38 data
39 (+) Interface with synchronous DRAM (SDRAM) memories
40 (+) Independent Chip Select control for each memory bank
41 (+) Independent configuration for each memory bank
42
43 @endverbatim
44 ******************************************************************************
45 * @attention
46 *
47 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
48 *
49 * Redistribution and use in source and binary forms, with or without modification,
50 * are permitted provided that the following conditions are met:
51 * 1. Redistributions of source code must retain the above copyright notice,
52 * this list of conditions and the following disclaimer.
53 * 2. Redistributions in binary form must reproduce the above copyright notice,
54 * this list of conditions and the following disclaimer in the documentation
55 * and/or other materials provided with the distribution.
56 * 3. Neither the name of STMicroelectronics nor the names of its contributors
57 * may be used to endorse or promote products derived from this software
58 * without specific prior written permission.
59 *
60 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
61 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
62 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
63 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
64 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
65 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
66 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
67 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
68 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
69 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
70 *
71 ******************************************************************************
72 */
73
74 /* Includes ------------------------------------------------------------------*/
75 #include "stm32f4xx_hal.h"
76
77 /** @addtogroup STM32F4xx_HAL_Driver
78 * @{
79 */
80
81 /** @defgroup FMC_LL FMC Low Layer
82 * @brief FMC driver modules
83 * @{
84 */
85
86 #if defined (HAL_SRAM_MODULE_ENABLED) || defined(HAL_NOR_MODULE_ENABLED) || defined(HAL_NAND_MODULE_ENABLED) || defined(HAL_PCCARD_MODULE_ENABLED) || defined(HAL_SDRAM_MODULE_ENABLED)
87
88 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
89
90 /* Private typedef -----------------------------------------------------------*/
91 /* Private define ------------------------------------------------------------*/
92 /* Private macro -------------------------------------------------------------*/
93 /* Private variables ---------------------------------------------------------*/
94 /* Private function prototypes -----------------------------------------------*/
95 /* Private functions ---------------------------------------------------------*/
96 /** @addtogroup FMC_LL_Private_Functions
97 * @{
98 */
99
100 /** @addtogroup FMC_LL_NORSRAM
101 * @brief NORSRAM Controller functions
102 *
103 @verbatim
104 ==============================================================================
105 ##### How to use NORSRAM device driver #####
106 ==============================================================================
107
108 [..]
109 This driver contains a set of APIs to interface with the FMC NORSRAM banks in order
110 to run the NORSRAM external devices.
111
112 (+) FMC NORSRAM bank reset using the function FMC_NORSRAM_DeInit()
113 (+) FMC NORSRAM bank control configuration using the function FMC_NORSRAM_Init()
114 (+) FMC NORSRAM bank timing configuration using the function FMC_NORSRAM_Timing_Init()
115 (+) FMC NORSRAM bank extended timing configuration using the function
116 FMC_NORSRAM_Extended_Timing_Init()
117 (+) FMC NORSRAM bank enable/disable write operation using the functions
118 FMC_NORSRAM_WriteOperation_Enable()/FMC_NORSRAM_WriteOperation_Disable()
119
120
121 @endverbatim
122 * @{
123 */
124
125 /** @addtogroup FMC_LL_NORSRAM_Private_Functions_Group1
126 * @brief Initialization and Configuration functions
127 *
128 @verbatim
129 ==============================================================================
130 ##### Initialization and de_initialization functions #####
131 ==============================================================================
132 [..]
133 This section provides functions allowing to:
134 (+) Initialize and configure the FMC NORSRAM interface
135 (+) De-initialize the FMC NORSRAM interface
136 (+) Configure the FMC clock and associated GPIOs
137
138 @endverbatim
139 * @{
140 */
141
142 /**
143 * @brief Initialize the FMC_NORSRAM device according to the specified
144 * control parameters in the FMC_NORSRAM_InitTypeDef
145 * @param Device Pointer to NORSRAM device instance
146 * @param Init Pointer to NORSRAM Initialization structure
147 * @retval HAL status
148 */
149 HAL_StatusTypeDef FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_InitTypeDef* Init)
150 {
151 uint32_t tmpr = 0U;
152
153 /* Check the parameters */
154 assert_param(IS_FMC_NORSRAM_DEVICE(Device));
155 assert_param(IS_FMC_NORSRAM_BANK(Init->NSBank));
156 assert_param(IS_FMC_MUX(Init->DataAddressMux));
157 assert_param(IS_FMC_MEMORY(Init->MemoryType));
158 assert_param(IS_FMC_NORSRAM_MEMORY_WIDTH(Init->MemoryDataWidth));
159 assert_param(IS_FMC_BURSTMODE(Init->BurstAccessMode));
160 assert_param(IS_FMC_WAIT_POLARITY(Init->WaitSignalPolarity));
161 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
162 assert_param(IS_FMC_WRAP_MODE(Init->WrapMode));
163 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
164 assert_param(IS_FMC_WAIT_SIGNAL_ACTIVE(Init->WaitSignalActive));
165 assert_param(IS_FMC_WRITE_OPERATION(Init->WriteOperation));
166 assert_param(IS_FMC_WAITE_SIGNAL(Init->WaitSignal));
167 assert_param(IS_FMC_EXTENDED_MODE(Init->ExtendedMode));
168 assert_param(IS_FMC_ASYNWAIT(Init->AsynchronousWait));
169 assert_param(IS_FMC_WRITE_BURST(Init->WriteBurst));
170 assert_param(IS_FMC_CONTINOUS_CLOCK(Init->ContinuousClock));
171 assert_param(IS_FMC_PAGESIZE(Init->PageSize));
172 #if defined (STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
173 assert_param(IS_FMC_WRITE_FIFO(Init->WriteFifo));
174 #endif /* STM32F446xx || STM32F469xx || STM32F479xx */
175
176 /* Get the BTCR register value */
177 tmpr = Device->BTCR[Init->NSBank];
178
179 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
180 /* Clear MBKEN, MUXEN, MTYP, MWID, FACCEN, BURSTEN, WAITPOL, WRAPMOD, WAITCFG, WREN,
181 WAITEN, EXTMOD, ASYNCWAIT, CPSIZE, CBURSTRW and CCLKEN bits */
182 tmpr &= ((uint32_t)~(FMC_BCR1_MBKEN | FMC_BCR1_MUXEN | FMC_BCR1_MTYP | \
183 FMC_BCR1_MWID | FMC_BCR1_FACCEN | FMC_BCR1_BURSTEN | \
184 FMC_BCR1_WAITPOL | FMC_BCR1_WRAPMOD | FMC_BCR1_WAITCFG | \
185 FMC_BCR1_WREN | FMC_BCR1_WAITEN | FMC_BCR1_EXTMOD | \
186 FMC_BCR1_ASYNCWAIT | FMC_BCR1_CPSIZE | FMC_BCR1_CBURSTRW | \
187 FMC_BCR1_CCLKEN));
188
189 /* Set NORSRAM device control parameters */
190 tmpr |= (uint32_t)(Init->DataAddressMux |\
191 Init->MemoryType |\
192 Init->MemoryDataWidth |\
193 Init->BurstAccessMode |\
194 Init->WaitSignalPolarity |\
195 Init->WrapMode |\
196 Init->WaitSignalActive |\
197 Init->WriteOperation |\
198 Init->WaitSignal |\
199 Init->ExtendedMode |\
200 Init->AsynchronousWait |\
201 Init->PageSize |\
202 Init->WriteBurst |\
203 Init->ContinuousClock);
204 #else /* defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) */
205 /* Clear MBKEN, MUXEN, MTYP, MWID, FACCEN, BURSTEN, WAITPOL, CPSIZE, WAITCFG, WREN,
206 WAITEN, EXTMOD, ASYNCWAIT, CBURSTRW, CCLKEN and WFDIS bits */
207 tmpr &= ((uint32_t)~(FMC_BCR1_MBKEN | FMC_BCR1_MUXEN | FMC_BCR1_MTYP | \
208 FMC_BCR1_MWID | FMC_BCR1_FACCEN | FMC_BCR1_BURSTEN | \
209 FMC_BCR1_WAITPOL | FMC_BCR1_WAITCFG | FMC_BCR1_CPSIZE | \
210 FMC_BCR1_WREN | FMC_BCR1_WAITEN | FMC_BCR1_EXTMOD | \
211 FMC_BCR1_ASYNCWAIT | FMC_BCR1_CBURSTRW | FMC_BCR1_CCLKEN | \
212 FMC_BCR1_WFDIS));
213
214 /* Set NORSRAM device control parameters */
215 tmpr |= (uint32_t)(Init->DataAddressMux |\
216 Init->MemoryType |\
217 Init->MemoryDataWidth |\
218 Init->BurstAccessMode |\
219 Init->WaitSignalPolarity |\
220 Init->WaitSignalActive |\
221 Init->WriteOperation |\
222 Init->WaitSignal |\
223 Init->ExtendedMode |\
224 Init->AsynchronousWait |\
225 Init->WriteBurst |\
226 Init->ContinuousClock |\
227 Init->PageSize |\
228 Init->WriteFifo);
229 #endif /* defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) */
230
231 if(Init->MemoryType == FMC_MEMORY_TYPE_NOR)
232 {
233 tmpr |= (uint32_t)FMC_NORSRAM_FLASH_ACCESS_ENABLE;
234 }
235
236 Device->BTCR[Init->NSBank] = tmpr;
237
238 /* Configure synchronous mode when Continuous clock is enabled for bank2..4 */
239 if((Init->ContinuousClock == FMC_CONTINUOUS_CLOCK_SYNC_ASYNC) && (Init->NSBank != FMC_NORSRAM_BANK1))
240 {
241 Device->BTCR[FMC_NORSRAM_BANK1] |= (uint32_t)(Init->ContinuousClock);
242 }
243
244 #if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
245 if(Init->NSBank != FMC_NORSRAM_BANK1)
246 {
247 Device->BTCR[FMC_NORSRAM_BANK1] |= (uint32_t)(Init->WriteFifo);
248 }
249 #endif /* STM32F446xx || STM32F469xx || STM32F479xx */
250
251 return HAL_OK;
252 }
253
254 /**
255 * @brief DeInitialize the FMC_NORSRAM peripheral
256 * @param Device Pointer to NORSRAM device instance
257 * @param ExDevice Pointer to NORSRAM extended mode device instance
258 * @param Bank NORSRAM bank number
259 * @retval HAL status
260 */
261 HAL_StatusTypeDef FMC_NORSRAM_DeInit(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank)
262 {
263 /* Check the parameters */
264 assert_param(IS_FMC_NORSRAM_DEVICE(Device));
265 assert_param(IS_FMC_NORSRAM_EXTENDED_DEVICE(ExDevice));
266 assert_param(IS_FMC_NORSRAM_BANK(Bank));
267
268 /* Disable the FMC_NORSRAM device */
269 __FMC_NORSRAM_DISABLE(Device, Bank);
270
271 /* De-initialize the FMC_NORSRAM device */
272 /* FMC_NORSRAM_BANK1 */
273 if(Bank == FMC_NORSRAM_BANK1)
274 {
275 Device->BTCR[Bank] = 0x000030DBU;
276 }
277 /* FMC_NORSRAM_BANK2, FMC_NORSRAM_BANK3 or FMC_NORSRAM_BANK4 */
278 else
279 {
280 Device->BTCR[Bank] = 0x000030D2U;
281 }
282
283 Device->BTCR[Bank + 1U] = 0x0FFFFFFFU;
284 ExDevice->BWTR[Bank] = 0x0FFFFFFFU;
285
286 return HAL_OK;
287 }
288
289 /**
290 * @brief Initialize the FMC_NORSRAM Timing according to the specified
291 * parameters in the FMC_NORSRAM_TimingTypeDef
292 * @param Device Pointer to NORSRAM device instance
293 * @param Timing Pointer to NORSRAM Timing structure
294 * @param Bank NORSRAM bank number
295 * @retval HAL status
296 */
297 HAL_StatusTypeDef FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank)
298 {
299 uint32_t tmpr = 0U;
300
301 /* Check the parameters */
302 assert_param(IS_FMC_NORSRAM_DEVICE(Device));
303 assert_param(IS_FMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime));
304 assert_param(IS_FMC_ADDRESS_HOLD_TIME(Timing->AddressHoldTime));
305 assert_param(IS_FMC_DATASETUP_TIME(Timing->DataSetupTime));
306 assert_param(IS_FMC_TURNAROUND_TIME(Timing->BusTurnAroundDuration));
307 assert_param(IS_FMC_CLK_DIV(Timing->CLKDivision));
308 assert_param(IS_FMC_DATA_LATENCY(Timing->DataLatency));
309 assert_param(IS_FMC_ACCESS_MODE(Timing->AccessMode));
310 assert_param(IS_FMC_NORSRAM_BANK(Bank));
311
312 /* Get the BTCR register value */
313 tmpr = Device->BTCR[Bank + 1U];
314
315 /* Clear ADDSET, ADDHLD, DATAST, BUSTURN, CLKDIV, DATLAT and ACCMOD bits */
316 tmpr &= ((uint32_t)~(FMC_BTR1_ADDSET | FMC_BTR1_ADDHLD | FMC_BTR1_DATAST | \
317 FMC_BTR1_BUSTURN | FMC_BTR1_CLKDIV | FMC_BTR1_DATLAT | \
318 FMC_BTR1_ACCMOD));
319
320 /* Set FMC_NORSRAM device timing parameters */
321 tmpr |= (uint32_t)(Timing->AddressSetupTime |\
322 ((Timing->AddressHoldTime) << 4U) |\
323 ((Timing->DataSetupTime) << 8U) |\
324 ((Timing->BusTurnAroundDuration) << 16U) |\
325 (((Timing->CLKDivision) - 1U) << 20U) |\
326 (((Timing->DataLatency) - 2U) << 24U) |\
327 (Timing->AccessMode));
328
329 Device->BTCR[Bank + 1U] = tmpr;
330
331 /* Configure Clock division value (in NORSRAM bank 1) when continuous clock is enabled */
332 if(HAL_IS_BIT_SET(Device->BTCR[FMC_NORSRAM_BANK1], FMC_BCR1_CCLKEN))
333 {
334 tmpr = (uint32_t)(Device->BTCR[FMC_NORSRAM_BANK1 + 1U] & ~(0x0FU << 20U));
335 tmpr |= (uint32_t)(((Timing->CLKDivision) - 1U) << 20U);
336 Device->BTCR[FMC_NORSRAM_BANK1 + 1U] = tmpr;
337 }
338
339 return HAL_OK;
340 }
341
342 /**
343 * @brief Initialize the FMC_NORSRAM Extended mode Timing according to the specified
344 * parameters in the FMC_NORSRAM_TimingTypeDef
345 * @param Device Pointer to NORSRAM device instance
346 * @param Timing Pointer to NORSRAM Timing structure
347 * @param Bank NORSRAM bank number
348 * @retval HAL status
349 */
350 HAL_StatusTypeDef FMC_NORSRAM_Extended_Timing_Init(FMC_NORSRAM_EXTENDED_TypeDef *Device, FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, uint32_t ExtendedMode)
351 {
352 uint32_t tmpr = 0U;
353
354 /* Check the parameters */
355 assert_param(IS_FMC_EXTENDED_MODE(ExtendedMode));
356
357 /* Set NORSRAM device timing register for write configuration, if extended mode is used */
358 if(ExtendedMode == FMC_EXTENDED_MODE_ENABLE)
359 {
360 /* Check the parameters */
361 assert_param(IS_FMC_NORSRAM_EXTENDED_DEVICE(Device));
362 assert_param(IS_FMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime));
363 assert_param(IS_FMC_ADDRESS_HOLD_TIME(Timing->AddressHoldTime));
364 assert_param(IS_FMC_DATASETUP_TIME(Timing->DataSetupTime));
365 assert_param(IS_FMC_TURNAROUND_TIME(Timing->BusTurnAroundDuration));
366 assert_param(IS_FMC_ACCESS_MODE(Timing->AccessMode));
367 assert_param(IS_FMC_NORSRAM_BANK(Bank));
368
369 /* Get the BWTR register value */
370 tmpr = Device->BWTR[Bank];
371
372 /* Clear ADDSET, ADDHLD, DATAST, BUSTURN and ACCMOD bits */
373 tmpr &= ((uint32_t)~(FMC_BWTR1_ADDSET | FMC_BWTR1_ADDHLD | FMC_BWTR1_DATAST | \
374 FMC_BWTR1_BUSTURN | FMC_BWTR1_ACCMOD));
375
376 tmpr |= (uint32_t)(Timing->AddressSetupTime |\
377 ((Timing->AddressHoldTime) << 4U) |\
378 ((Timing->DataSetupTime) << 8U) |\
379 ((Timing->BusTurnAroundDuration) << 16U) |\
380 (Timing->AccessMode));
381
382 Device->BWTR[Bank] = tmpr;
383 }
384 else
385 {
386 Device->BWTR[Bank] = 0x0FFFFFFFU;
387 }
388
389 return HAL_OK;
390 }
391 /**
392 * @}
393 */
394
395 /** @addtogroup FMC_LL_NORSRAM_Private_Functions_Group2
396 * @brief management functions
397 *
398 @verbatim
399 ==============================================================================
400 ##### FMC_NORSRAM Control functions #####
401 ==============================================================================
402 [..]
403 This subsection provides a set of functions allowing to control dynamically
404 the FMC NORSRAM interface.
405
406 @endverbatim
407 * @{
408 */
409 /**
410 * @brief Enables dynamically FMC_NORSRAM write operation.
411 * @param Device Pointer to NORSRAM device instance
412 * @param Bank NORSRAM bank number
413 * @retval HAL status
414 */
415 HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Enable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank)
416 {
417 /* Check the parameters */
418 assert_param(IS_FMC_NORSRAM_DEVICE(Device));
419 assert_param(IS_FMC_NORSRAM_BANK(Bank));
420
421 /* Enable write operation */
422 Device->BTCR[Bank] |= FMC_WRITE_OPERATION_ENABLE;
423
424 return HAL_OK;
425 }
426
427 /**
428 * @brief Disables dynamically FMC_NORSRAM write operation.
429 * @param Device Pointer to NORSRAM device instance
430 * @param Bank NORSRAM bank number
431 * @retval HAL status
432 */
433 HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Disable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank)
434 {
435 /* Check the parameters */
436 assert_param(IS_FMC_NORSRAM_DEVICE(Device));
437 assert_param(IS_FMC_NORSRAM_BANK(Bank));
438
439 /* Disable write operation */
440 Device->BTCR[Bank] &= ~FMC_WRITE_OPERATION_ENABLE;
441
442 return HAL_OK;
443 }
444
445 /**
446 * @}
447 */
448
449 /**
450 * @}
451 */
452
453 /** @addtogroup FMC_LL_NAND
454 * @brief NAND Controller functions
455 *
456 @verbatim
457 ==============================================================================
458 ##### How to use NAND device driver #####
459 ==============================================================================
460 [..]
461 This driver contains a set of APIs to interface with the FMC NAND banks in order
462 to run the NAND external devices.
463
464 (+) FMC NAND bank reset using the function FMC_NAND_DeInit()
465 (+) FMC NAND bank control configuration using the function FMC_NAND_Init()
466 (+) FMC NAND bank common space timing configuration using the function
467 FMC_NAND_CommonSpace_Timing_Init()
468 (+) FMC NAND bank attribute space timing configuration using the function
469 FMC_NAND_AttributeSpace_Timing_Init()
470 (+) FMC NAND bank enable/disable ECC correction feature using the functions
471 FMC_NAND_ECC_Enable()/FMC_NAND_ECC_Disable()
472 (+) FMC NAND bank get ECC correction code using the function FMC_NAND_GetECC()
473
474 @endverbatim
475 * @{
476 */
477
478 #if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
479 /** @defgroup HAL_FMC_NAND_Group1 Initialization/de-initialization functions
480 * @brief Initialization and Configuration functions
481 *
482 @verbatim
483 ==============================================================================
484 ##### Initialization and de_initialization functions #####
485 ==============================================================================
486 [..]
487 This section provides functions allowing to:
488 (+) Initialize and configure the FMC NAND interface
489 (+) De-initialize the FMC NAND interface
490 (+) Configure the FMC clock and associated GPIOs
491
492 @endverbatim
493 * @{
494 */
495
496 /**
497 * @brief Initializes the FMC_NAND device according to the specified
498 * control parameters in the FMC_NAND_HandleTypeDef
499 * @param Device Pointer to NAND device instance
500 * @param Init Pointer to NAND Initialization structure
501 * @retval HAL status
502 */
503 HAL_StatusTypeDef FMC_NAND_Init(FMC_NAND_TypeDef *Device, FMC_NAND_InitTypeDef *Init)
504 {
505 uint32_t tmpr = 0U;
506
507 /* Check the parameters */
508 assert_param(IS_FMC_NAND_DEVICE(Device));
509 assert_param(IS_FMC_NAND_BANK(Init->NandBank));
510 assert_param(IS_FMC_WAIT_FEATURE(Init->Waitfeature));
511 assert_param(IS_FMC_NAND_MEMORY_WIDTH(Init->MemoryDataWidth));
512 assert_param(IS_FMC_ECC_STATE(Init->EccComputation));
513 assert_param(IS_FMC_ECCPAGE_SIZE(Init->ECCPageSize));
514 assert_param(IS_FMC_TCLR_TIME(Init->TCLRSetupTime));
515 assert_param(IS_FMC_TAR_TIME(Init->TARSetupTime));
516
517 /* Get the NAND bank register value */
518 tmpr = Device->PCR;
519
520 /* Clear PWAITEN, PBKEN, PTYP, PWID, ECCEN, TCLR, TAR and ECCPS bits */
521 tmpr &= ((uint32_t)~(FMC_PCR_PWAITEN | FMC_PCR_PBKEN | FMC_PCR_PTYP | \
522 FMC_PCR_PWID | FMC_PCR_ECCEN | FMC_PCR_TCLR | \
523 FMC_PCR_TAR | FMC_PCR_ECCPS));
524
525 /* Set NAND device control parameters */
526 tmpr |= (uint32_t)(Init->Waitfeature |\
527 FMC_PCR_MEMORY_TYPE_NAND |\
528 Init->MemoryDataWidth |\
529 Init->EccComputation |\
530 Init->ECCPageSize |\
531 ((Init->TCLRSetupTime) << 9U) |\
532 ((Init->TARSetupTime) << 13U));
533
534 /* NAND bank registers configuration */
535 Device->PCR = tmpr;
536
537 return HAL_OK;
538 }
539
540 /**
541 * @brief Initializes the FMC_NAND Common space Timing according to the specified
542 * parameters in the FMC_NAND_PCC_TimingTypeDef
543 * @param Device Pointer to NAND device instance
544 * @param Timing Pointer to NAND timing structure
545 * @param Bank NAND bank number
546 * @retval HAL status
547 */
548 HAL_StatusTypeDef FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank)
549 {
550 uint32_t tmpr = 0U;
551
552 /* Check the parameters */
553 assert_param(IS_FMC_NAND_DEVICE(Device));
554 assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime));
555 assert_param(IS_FMC_WAIT_TIME(Timing->WaitSetupTime));
556 assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime));
557 assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime));
558 assert_param(IS_FMC_NAND_BANK(Bank));
559
560 /* Get the NAND bank 2 register value */
561 tmpr = Device->PMEM;
562
563
564 /* Clear MEMSETx, MEMWAITx, MEMHOLDx and MEMHIZx bits */
565 tmpr &= ((uint32_t)~(FMC_PMEM_MEMSET2 | FMC_PMEM_MEMWAIT2 | FMC_PMEM_MEMHOLD2 | \
566 FMC_PMEM_MEMHIZ2));
567
568 /* Set FMC_NAND device timing parameters */
569 tmpr |= (uint32_t)(Timing->SetupTime |\
570 ((Timing->WaitSetupTime) << 8U) |\
571 ((Timing->HoldSetupTime) << 16U) |\
572 ((Timing->HiZSetupTime) << 24U)
573 );
574
575 /* NAND bank registers configuration */
576 Device->PMEM = tmpr;
577
578 return HAL_OK;
579 }
580
581 /**
582 * @brief Initializes the FMC_NAND Attribute space Timing according to the specified
583 * parameters in the FMC_NAND_PCC_TimingTypeDef
584 * @param Device Pointer to NAND device instance
585 * @param Timing Pointer to NAND timing structure
586 * @param Bank NAND bank number
587 * @retval HAL status
588 */
589 HAL_StatusTypeDef FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank)
590 {
591 uint32_t tmpr = 0U;
592
593 /* Check the parameters */
594 assert_param(IS_FMC_NAND_DEVICE(Device));
595 assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime));
596 assert_param(IS_FMC_WAIT_TIME(Timing->WaitSetupTime));
597 assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime));
598 assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime));
599 assert_param(IS_FMC_NAND_BANK(Bank));
600
601 /* Get the NAND bank register value */
602 tmpr = Device->PATT;
603
604 /* Clear ATTSETx, ATTWAITx, ATTHOLDx and ATTHIZx bits */
605 tmpr &= ((uint32_t)~(FMC_PATT_ATTSET2 | FMC_PATT_ATTWAIT2 | FMC_PATT_ATTHOLD2 | \
606 FMC_PATT_ATTHIZ2));
607
608 /* Set FMC_NAND device timing parameters */
609 tmpr |= (uint32_t)(Timing->SetupTime |\
610 ((Timing->WaitSetupTime) << 8U) |\
611 ((Timing->HoldSetupTime) << 16U) |\
612 ((Timing->HiZSetupTime) << 24U));
613
614 /* NAND bank registers configuration */
615 Device->PATT = tmpr;
616
617 return HAL_OK;
618 }
619
620
621 /**
622 * @brief DeInitializes the FMC_NAND device
623 * @param Device Pointer to NAND device instance
624 * @param Bank NAND bank number
625 * @retval HAL status
626 */
627 HAL_StatusTypeDef FMC_NAND_DeInit(FMC_NAND_TypeDef *Device, uint32_t Bank)
628 {
629 /* Check the parameters */
630 assert_param(IS_FMC_NAND_DEVICE(Device));
631 assert_param(IS_FMC_NAND_BANK(Bank));
632
633 /* Disable the NAND Bank */
634 __FMC_NAND_DISABLE(Device, Bank);
635
636 /* De-initialize the NAND Bank */
637 /* Set the FMC_NAND_BANK registers to their reset values */
638 Device->PCR = 0x00000018U;
639 Device->SR = 0x00000040U;
640 Device->PMEM = 0xFCFCFCFCU;
641 Device->PATT = 0xFCFCFCFCU;
642
643 return HAL_OK;
644 }
645
646 /**
647 * @}
648 */
649
650
651 /** @defgroup HAL_FMC_NAND_Group2 Control functions
652 * @brief management functions
653 *
654 @verbatim
655 ==============================================================================
656 ##### FMC_NAND Control functions #####
657 ==============================================================================
658 [..]
659 This subsection provides a set of functions allowing to control dynamically
660 the FMC NAND interface.
661
662 @endverbatim
663 * @{
664 */
665
666
667 /**
668 * @brief Enables dynamically FMC_NAND ECC feature.
669 * @param Device Pointer to NAND device instance
670 * @param Bank NAND bank number
671 * @retval HAL status
672 */
673 HAL_StatusTypeDef FMC_NAND_ECC_Enable(FMC_NAND_TypeDef *Device, uint32_t Bank)
674 {
675 /* Check the parameters */
676 assert_param(IS_FMC_NAND_DEVICE(Device));
677 assert_param(IS_FMC_NAND_BANK(Bank));
678
679 /* Enable ECC feature */
680 Device->PCR |= FMC_PCR_ECCEN;
681
682 return HAL_OK;
683 }
684
685
686 /**
687 * @brief Disables dynamically FMC_NAND ECC feature.
688 * @param Device Pointer to NAND device instance
689 * @param Bank NAND bank number
690 * @retval HAL status
691 */
692 HAL_StatusTypeDef FMC_NAND_ECC_Disable(FMC_NAND_TypeDef *Device, uint32_t Bank)
693 {
694 /* Check the parameters */
695 assert_param(IS_FMC_NAND_DEVICE(Device));
696 assert_param(IS_FMC_NAND_BANK(Bank));
697
698 /* Disable ECC feature */
699 Device->PCR &= ~FMC_PCR_ECCEN;
700
701 return HAL_OK;
702 }
703
704 /**
705 * @brief Disables dynamically FMC_NAND ECC feature.
706 * @param Device Pointer to NAND device instance
707 * @param ECCval Pointer to ECC value
708 * @param Bank NAND bank number
709 * @param Timeout Timeout wait value
710 * @retval HAL status
711 */
712 HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, uint32_t Timeout)
713 {
714 uint32_t tickstart = 0U;
715
716 /* Check the parameters */
717 assert_param(IS_FMC_NAND_DEVICE(Device));
718 assert_param(IS_FMC_NAND_BANK(Bank));
719
720 /* Get tick */
721 tickstart = HAL_GetTick();
722
723 /* Wait until FIFO is empty */
724 while(__FMC_NAND_GET_FLAG(Device, Bank, FMC_FLAG_FEMPT) == RESET)
725 {
726 /* Check for the Timeout */
727 if(Timeout != HAL_MAX_DELAY)
728 {
729 if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
730 {
731 return HAL_TIMEOUT;
732 }
733 }
734 }
735
736 /* Get the ECCR register value */
737 *ECCval = (uint32_t)Device->ECCR;
738
739 return HAL_OK;
740 }
741
742 /**
743 * @}
744 */
745
746 #else /* defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) */
747 /** @defgroup HAL_FMC_NAND_Group1 Initialization/de-initialization functions
748 * @brief Initialization and Configuration functions
749 *
750 @verbatim
751 ==============================================================================
752 ##### Initialization and de_initialization functions #####
753 ==============================================================================
754 [..]
755 This section provides functions allowing to:
756 (+) Initialize and configure the FMC NAND interface
757 (+) De-initialize the FMC NAND interface
758 (+) Configure the FMC clock and associated GPIOs
759
760 @endverbatim
761 * @{
762 */
763 /**
764 * @brief Initializes the FMC_NAND device according to the specified
765 * control parameters in the FMC_NAND_HandleTypeDef
766 * @param Device Pointer to NAND device instance
767 * @param Init Pointer to NAND Initialization structure
768 * @retval HAL status
769 */
770 HAL_StatusTypeDef FMC_NAND_Init(FMC_NAND_TypeDef *Device, FMC_NAND_InitTypeDef *Init)
771 {
772 uint32_t tmpr = 0U;
773
774 /* Check the parameters */
775 assert_param(IS_FMC_NAND_DEVICE(Device));
776 assert_param(IS_FMC_NAND_BANK(Init->NandBank));
777 assert_param(IS_FMC_WAIT_FEATURE(Init->Waitfeature));
778 assert_param(IS_FMC_NAND_MEMORY_WIDTH(Init->MemoryDataWidth));
779 assert_param(IS_FMC_ECC_STATE(Init->EccComputation));
780 assert_param(IS_FMC_ECCPAGE_SIZE(Init->ECCPageSize));
781 assert_param(IS_FMC_TCLR_TIME(Init->TCLRSetupTime));
782 assert_param(IS_FMC_TAR_TIME(Init->TARSetupTime));
783
784 if(Init->NandBank == FMC_NAND_BANK2)
785 {
786 /* Get the NAND bank 2 register value */
787 tmpr = Device->PCR2;
788 }
789 else
790 {
791 /* Get the NAND bank 3 register value */
792 tmpr = Device->PCR3;
793 }
794
795 /* Clear PWAITEN, PBKEN, PTYP, PWID, ECCEN, TCLR, TAR and ECCPS bits */
796 tmpr &= ((uint32_t)~(FMC_PCR2_PWAITEN | FMC_PCR2_PBKEN | FMC_PCR2_PTYP | \
797 FMC_PCR2_PWID | FMC_PCR2_ECCEN | FMC_PCR2_TCLR | \
798 FMC_PCR2_TAR | FMC_PCR2_ECCPS));
799
800 /* Set NAND device control parameters */
801 tmpr |= (uint32_t)(Init->Waitfeature |\
802 FMC_PCR_MEMORY_TYPE_NAND |\
803 Init->MemoryDataWidth |\
804 Init->EccComputation |\
805 Init->ECCPageSize |\
806 ((Init->TCLRSetupTime) << 9U) |\
807 ((Init->TARSetupTime) << 13U));
808
809 if(Init->NandBank == FMC_NAND_BANK2)
810 {
811 /* NAND bank 2 registers configuration */
812 Device->PCR2 = tmpr;
813 }
814 else
815 {
816 /* NAND bank 3 registers configuration */
817 Device->PCR3 = tmpr;
818 }
819
820 return HAL_OK;
821
822 }
823
824 /**
825 * @brief Initializes the FMC_NAND Common space Timing according to the specified
826 * parameters in the FMC_NAND_PCC_TimingTypeDef
827 * @param Device Pointer to NAND device instance
828 * @param Timing Pointer to NAND timing structure
829 * @param Bank NAND bank number
830 * @retval HAL status
831 */
832 HAL_StatusTypeDef FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank)
833 {
834 uint32_t tmpr = 0U;
835
836 /* Check the parameters */
837 assert_param(IS_FMC_NAND_DEVICE(Device));
838 assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime));
839 assert_param(IS_FMC_WAIT_TIME(Timing->WaitSetupTime));
840 assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime));
841 assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime));
842 assert_param(IS_FMC_NAND_BANK(Bank));
843
844 if(Bank == FMC_NAND_BANK2)
845 {
846 /* Get the NAND bank 2 register value */
847 tmpr = Device->PMEM2;
848 }
849 else
850 {
851 /* Get the NAND bank 3 register value */
852 tmpr = Device->PMEM3;
853 }
854
855 /* Clear MEMSETx, MEMWAITx, MEMHOLDx and MEMHIZx bits */
856 tmpr &= ((uint32_t)~(FMC_PMEM2_MEMSET2 | FMC_PMEM2_MEMWAIT2 | FMC_PMEM2_MEMHOLD2 | \
857 FMC_PMEM2_MEMHIZ2));
858
859 /* Set FMC_NAND device timing parameters */
860 tmpr |= (uint32_t)(Timing->SetupTime |\
861 ((Timing->WaitSetupTime) << 8U) |\
862 ((Timing->HoldSetupTime) << 16U) |\
863 ((Timing->HiZSetupTime) << 24U)
864 );
865
866 if(Bank == FMC_NAND_BANK2)
867 {
868 /* NAND bank 2 registers configuration */
869 Device->PMEM2 = tmpr;
870 }
871 else
872 {
873 /* NAND bank 3 registers configuration */
874 Device->PMEM3 = tmpr;
875 }
876
877 return HAL_OK;
878 }
879
880 /**
881 * @brief Initializes the FMC_NAND Attribute space Timing according to the specified
882 * parameters in the FMC_NAND_PCC_TimingTypeDef
883 * @param Device Pointer to NAND device instance
884 * @param Timing Pointer to NAND timing structure
885 * @param Bank NAND bank number
886 * @retval HAL status
887 */
888 HAL_StatusTypeDef FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank)
889 {
890 uint32_t tmpr = 0U;
891
892 /* Check the parameters */
893 assert_param(IS_FMC_NAND_DEVICE(Device));
894 assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime));
895 assert_param(IS_FMC_WAIT_TIME(Timing->WaitSetupTime));
896 assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime));
897 assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime));
898 assert_param(IS_FMC_NAND_BANK(Bank));
899
900 if(Bank == FMC_NAND_BANK2)
901 {
902 /* Get the NAND bank 2 register value */
903 tmpr = Device->PATT2;
904 }
905 else
906 {
907 /* Get the NAND bank 3 register value */
908 tmpr = Device->PATT3;
909 }
910
911 /* Clear ATTSETx, ATTWAITx, ATTHOLDx and ATTHIZx bits */
912 tmpr &= ((uint32_t)~(FMC_PATT2_ATTSET2 | FMC_PATT2_ATTWAIT2 | FMC_PATT2_ATTHOLD2 | \
913 FMC_PATT2_ATTHIZ2));
914
915 /* Set FMC_NAND device timing parameters */
916 tmpr |= (uint32_t)(Timing->SetupTime |\
917 ((Timing->WaitSetupTime) << 8U) |\
918 ((Timing->HoldSetupTime) << 16U) |\
919 ((Timing->HiZSetupTime) << 24U));
920
921 if(Bank == FMC_NAND_BANK2)
922 {
923 /* NAND bank 2 registers configuration */
924 Device->PATT2 = tmpr;
925 }
926 else
927 {
928 /* NAND bank 3 registers configuration */
929 Device->PATT3 = tmpr;
930 }
931
932 return HAL_OK;
933 }
934
935 /**
936 * @brief DeInitializes the FMC_NAND device
937 * @param Device Pointer to NAND device instance
938 * @param Bank NAND bank number
939 * @retval HAL status
940 */
941 HAL_StatusTypeDef FMC_NAND_DeInit(FMC_NAND_TypeDef *Device, uint32_t Bank)
942 {
943 /* Check the parameters */
944 assert_param(IS_FMC_NAND_DEVICE(Device));
945 assert_param(IS_FMC_NAND_BANK(Bank));
946
947 /* Disable the NAND Bank */
948 __FMC_NAND_DISABLE(Device, Bank);
949
950 /* De-initialize the NAND Bank */
951 if(Bank == FMC_NAND_BANK2)
952 {
953 /* Set the FMC_NAND_BANK2 registers to their reset values */
954 Device->PCR2 = 0x00000018U;
955 Device->SR2 = 0x00000040U;
956 Device->PMEM2 = 0xFCFCFCFCU;
957 Device->PATT2 = 0xFCFCFCFCU;
958 }
959 /* FMC_Bank3_NAND */
960 else
961 {
962 /* Set the FMC_NAND_BANK3 registers to their reset values */
963 Device->PCR3 = 0x00000018U;
964 Device->SR3 = 0x00000040U;
965 Device->PMEM3 = 0xFCFCFCFCU;
966 Device->PATT3 = 0xFCFCFCFCU;
967 }
968
969 return HAL_OK;
970 }
971
972 /**
973 * @}
974 */
975
976 /** @addtogroup FMC_LL_NAND_Private_Functions_Group2
977 * @brief management functions
978 *
979 @verbatim
980 ==============================================================================
981 ##### FMC_NAND Control functions #####
982 ==============================================================================
983 [..]
984 This subsection provides a set of functions allowing to control dynamically
985 the FMC NAND interface.
986
987 @endverbatim
988 * @{
989 */
990 /**
991 * @brief Enables dynamically FMC_NAND ECC feature.
992 * @param Device Pointer to NAND device instance
993 * @param Bank NAND bank number
994 * @retval HAL status
995 */
996 HAL_StatusTypeDef FMC_NAND_ECC_Enable(FMC_NAND_TypeDef *Device, uint32_t Bank)
997 {
998 /* Check the parameters */
999 assert_param(IS_FMC_NAND_DEVICE(Device));
1000 assert_param(IS_FMC_NAND_BANK(Bank));
1001
1002 /* Enable ECC feature */
1003 if(Bank == FMC_NAND_BANK2)
1004 {
1005 Device->PCR2 |= FMC_PCR2_ECCEN;
1006 }
1007 else
1008 {
1009 Device->PCR3 |= FMC_PCR3_ECCEN;
1010 }
1011
1012 return HAL_OK;
1013 }
1014
1015 /**
1016 * @brief Disables dynamically FMC_NAND ECC feature.
1017 * @param Device Pointer to NAND device instance
1018 * @param Bank NAND bank number
1019 * @retval HAL status
1020 */
1021 HAL_StatusTypeDef FMC_NAND_ECC_Disable(FMC_NAND_TypeDef *Device, uint32_t Bank)
1022 {
1023 /* Check the parameters */
1024 assert_param(IS_FMC_NAND_DEVICE(Device));
1025 assert_param(IS_FMC_NAND_BANK(Bank));
1026
1027 /* Disable ECC feature */
1028 if(Bank == FMC_NAND_BANK2)
1029 {
1030 Device->PCR2 &= ~FMC_PCR2_ECCEN;
1031 }
1032 else
1033 {
1034 Device->PCR3 &= ~FMC_PCR3_ECCEN;
1035 }
1036
1037 return HAL_OK;
1038 }
1039
1040 /**
1041 * @brief Disables dynamically FMC_NAND ECC feature.
1042 * @param Device Pointer to NAND device instance
1043 * @param ECCval Pointer to ECC value
1044 * @param Bank NAND bank number
1045 * @param Timeout Timeout wait value
1046 * @retval HAL status
1047 */
1048 HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, uint32_t Timeout)
1049 {
1050 uint32_t tickstart = 0U;
1051
1052 /* Check the parameters */
1053 assert_param(IS_FMC_NAND_DEVICE(Device));
1054 assert_param(IS_FMC_NAND_BANK(Bank));
1055
1056 /* Get tick */
1057 tickstart = HAL_GetTick();
1058
1059 /* Wait until FIFO is empty */
1060 while(__FMC_NAND_GET_FLAG(Device, Bank, FMC_FLAG_FEMPT) == RESET)
1061 {
1062 /* Check for the Timeout */
1063 if(Timeout != HAL_MAX_DELAY)
1064 {
1065 if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
1066 {
1067 return HAL_TIMEOUT;
1068 }
1069 }
1070 }
1071
1072 if(Bank == FMC_NAND_BANK2)
1073 {
1074 /* Get the ECCR2 register value */
1075 *ECCval = (uint32_t)Device->ECCR2;
1076 }
1077 else
1078 {
1079 /* Get the ECCR3 register value */
1080 *ECCval = (uint32_t)Device->ECCR3;
1081 }
1082
1083 return HAL_OK;
1084 }
1085
1086 /**
1087 * @}
1088 */
1089
1090 #endif /* defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) */
1091 /**
1092 * @}
1093 */
1094
1095 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
1096 /** @addtogroup FMC_LL_PCCARD
1097 * @brief PCCARD Controller functions
1098 *
1099 @verbatim
1100 ==============================================================================
1101 ##### How to use PCCARD device driver #####
1102 ==============================================================================
1103 [..]
1104 This driver contains a set of APIs to interface with the FMC PCCARD bank in order
1105 to run the PCCARD/compact flash external devices.
1106
1107 (+) FMC PCCARD bank reset using the function FMC_PCCARD_DeInit()
1108 (+) FMC PCCARD bank control configuration using the function FMC_PCCARD_Init()
1109 (+) FMC PCCARD bank common space timing configuration using the function
1110 FMC_PCCARD_CommonSpace_Timing_Init()
1111 (+) FMC PCCARD bank attribute space timing configuration using the function
1112 FMC_PCCARD_AttributeSpace_Timing_Init()
1113 (+) FMC PCCARD bank IO space timing configuration using the function
1114 FMC_PCCARD_IOSpace_Timing_Init()
1115 @endverbatim
1116 * @{
1117 */
1118
1119 /** @addtogroup FMC_LL_PCCARD_Private_Functions_Group1
1120 * @brief Initialization and Configuration functions
1121 *
1122 @verbatim
1123 ==============================================================================
1124 ##### Initialization and de_initialization functions #####
1125 ==============================================================================
1126 [..]
1127 This section provides functions allowing to:
1128 (+) Initialize and configure the FMC PCCARD interface
1129 (+) De-initialize the FMC PCCARD interface
1130 (+) Configure the FMC clock and associated GPIOs
1131
1132 @endverbatim
1133 * @{
1134 */
1135
1136 /**
1137 * @brief Initializes the FMC_PCCARD device according to the specified
1138 * control parameters in the FMC_PCCARD_HandleTypeDef
1139 * @param Device Pointer to PCCARD device instance
1140 * @param Init Pointer to PCCARD Initialization structure
1141 * @retval HAL status
1142 */
1143 HAL_StatusTypeDef FMC_PCCARD_Init(FMC_PCCARD_TypeDef *Device, FMC_PCCARD_InitTypeDef *Init)
1144 {
1145 uint32_t tmpr = 0U;
1146
1147 /* Check the parameters */
1148 assert_param(IS_FMC_PCCARD_DEVICE(Device));
1149 assert_param(IS_FMC_WAIT_FEATURE(Init->Waitfeature));
1150 assert_param(IS_FMC_TCLR_TIME(Init->TCLRSetupTime));
1151 assert_param(IS_FMC_TAR_TIME(Init->TARSetupTime));
1152
1153 /* Get PCCARD control register value */
1154 tmpr = Device->PCR4;
1155
1156 /* Clear TAR, TCLR, PWAITEN and PWID bits */
1157 tmpr &= ((uint32_t)~(FMC_PCR4_TAR | FMC_PCR4_TCLR | FMC_PCR4_PWAITEN | \
1158 FMC_PCR4_PWID | FMC_PCR4_PTYP));
1159
1160 /* Set FMC_PCCARD device control parameters */
1161 tmpr |= (uint32_t)(Init->Waitfeature |\
1162 FMC_NAND_PCC_MEM_BUS_WIDTH_16 |\
1163 (Init->TCLRSetupTime << 9U) |\
1164 (Init->TARSetupTime << 13U));
1165
1166 Device->PCR4 = tmpr;
1167
1168 return HAL_OK;
1169 }
1170
1171 /**
1172 * @brief Initializes the FMC_PCCARD Common space Timing according to the specified
1173 * parameters in the FMC_NAND_PCC_TimingTypeDef
1174 * @param Device Pointer to PCCARD device instance
1175 * @param Timing Pointer to PCCARD timing structure
1176 * @retval HAL status
1177 */
1178 HAL_StatusTypeDef FMC_PCCARD_CommonSpace_Timing_Init(FMC_PCCARD_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing)
1179 {
1180 uint32_t tmpr = 0U;
1181
1182 /* Check the parameters */
1183 assert_param(IS_FMC_PCCARD_DEVICE(Device));
1184 assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime));
1185 assert_param(IS_FMC_WAIT_TIME(Timing->WaitSetupTime));
1186 assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime));
1187 assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime));
1188
1189 /* Get PCCARD common space timing register value */
1190 tmpr = Device->PMEM4;
1191
1192 /* Clear MEMSETx, MEMWAITx, MEMHOLDx and MEMHIZx bits */
1193 tmpr &= ((uint32_t)~(FMC_PMEM4_MEMSET4 | FMC_PMEM4_MEMWAIT4 | FMC_PMEM4_MEMHOLD4 | \
1194 FMC_PMEM4_MEMHIZ4));
1195 /* Set PCCARD timing parameters */
1196 tmpr |= (uint32_t)(Timing->SetupTime |\
1197 ((Timing->WaitSetupTime) << 8U) |\
1198 ((Timing->HoldSetupTime) << 16U) |\
1199 ((Timing->HiZSetupTime) << 24U));
1200
1201 Device->PMEM4 = tmpr;
1202
1203 return HAL_OK;
1204 }
1205
1206 /**
1207 * @brief Initializes the FMC_PCCARD Attribute space Timing according to the specified
1208 * parameters in the FMC_NAND_PCC_TimingTypeDef
1209 * @param Device Pointer to PCCARD device instance
1210 * @param Timing Pointer to PCCARD timing structure
1211 * @retval HAL status
1212 */
1213 HAL_StatusTypeDef FMC_PCCARD_AttributeSpace_Timing_Init(FMC_PCCARD_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing)
1214 {
1215 uint32_t tmpr = 0U;
1216
1217 /* Check the parameters */
1218 assert_param(IS_FMC_PCCARD_DEVICE(Device));
1219 assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime));
1220 assert_param(IS_FMC_WAIT_TIME(Timing->WaitSetupTime));
1221 assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime));
1222 assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime));
1223
1224 /* Get PCCARD timing parameters */
1225 tmpr = Device->PATT4;
1226
1227 /* Clear ATTSETx, ATTWAITx, ATTHOLDx and ATTHIZx bits */
1228 tmpr &= ((uint32_t)~(FMC_PATT4_ATTSET4 | FMC_PATT4_ATTWAIT4 | FMC_PATT4_ATTHOLD4 | \
1229 FMC_PATT4_ATTHIZ4));
1230
1231 /* Set PCCARD timing parameters */
1232 tmpr |= (uint32_t)(Timing->SetupTime |\
1233 ((Timing->WaitSetupTime) << 8U) |\
1234 ((Timing->HoldSetupTime) << 16U) |\
1235 ((Timing->HiZSetupTime) << 24U));
1236 Device->PATT4 = tmpr;
1237
1238 return HAL_OK;
1239 }
1240
1241 /**
1242 * @brief Initializes the FMC_PCCARD IO space Timing according to the specified
1243 * parameters in the FMC_NAND_PCC_TimingTypeDef
1244 * @param Device Pointer to PCCARD device instance
1245 * @param Timing Pointer to PCCARD timing structure
1246 * @retval HAL status
1247 */
1248 HAL_StatusTypeDef FMC_PCCARD_IOSpace_Timing_Init(FMC_PCCARD_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing)
1249 {
1250 uint32_t tmpr = 0;
1251
1252 /* Check the parameters */
1253 assert_param(IS_FMC_PCCARD_DEVICE(Device));
1254 assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime));
1255 assert_param(IS_FMC_WAIT_TIME(Timing->WaitSetupTime));
1256 assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime));
1257 assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime));
1258
1259 /* Get FMC_PCCARD device timing parameters */
1260 tmpr = Device->PIO4;
1261
1262 /* Clear IOSET4, IOWAIT4, IOHOLD4 and IOHIZ4 bits */
1263 tmpr &= ((uint32_t)~(FMC_PIO4_IOSET4 | FMC_PIO4_IOWAIT4 | FMC_PIO4_IOHOLD4 | \
1264 FMC_PIO4_IOHIZ4));
1265
1266 /* Set FMC_PCCARD device timing parameters */
1267 tmpr |= (uint32_t)(Timing->SetupTime |\
1268 ((Timing->WaitSetupTime) << 8U) |\
1269 ((Timing->HoldSetupTime) << 16U) |\
1270 ((Timing->HiZSetupTime) << 24U));
1271
1272 Device->PIO4 = tmpr;
1273
1274 return HAL_OK;
1275 }
1276
1277 /**
1278 * @brief DeInitializes the FMC_PCCARD device
1279 * @param Device Pointer to PCCARD device instance
1280 * @retval HAL status
1281 */
1282 HAL_StatusTypeDef FMC_PCCARD_DeInit(FMC_PCCARD_TypeDef *Device)
1283 {
1284 /* Check the parameters */
1285 assert_param(IS_FMC_PCCARD_DEVICE(Device));
1286
1287 /* Disable the FMC_PCCARD device */
1288 __FMC_PCCARD_DISABLE(Device);
1289
1290 /* De-initialize the FMC_PCCARD device */
1291 Device->PCR4 = 0x00000018U;
1292 Device->SR4 = 0x00000000U;
1293 Device->PMEM4 = 0xFCFCFCFCU;
1294 Device->PATT4 = 0xFCFCFCFCU;
1295 Device->PIO4 = 0xFCFCFCFCU;
1296
1297 return HAL_OK;
1298 }
1299
1300 /**
1301 * @}
1302 */
1303 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
1304
1305
1306 /** @addtogroup FMC_LL_SDRAM
1307 * @brief SDRAM Controller functions
1308 *
1309 @verbatim
1310 ==============================================================================
1311 ##### How to use SDRAM device driver #####
1312 ==============================================================================
1313 [..]
1314 This driver contains a set of APIs to interface with the FMC SDRAM banks in order
1315 to run the SDRAM external devices.
1316
1317 (+) FMC SDRAM bank reset using the function FMC_SDRAM_DeInit()
1318 (+) FMC SDRAM bank control configuration using the function FMC_SDRAM_Init()
1319 (+) FMC SDRAM bank timing configuration using the function FMC_SDRAM_Timing_Init()
1320 (+) FMC SDRAM bank enable/disable write operation using the functions
1321 FMC_SDRAM_WriteOperation_Enable()/FMC_SDRAM_WriteOperation_Disable()
1322 (+) FMC SDRAM bank send command using the function FMC_SDRAM_SendCommand()
1323
1324 @endverbatim
1325 * @{
1326 */
1327
1328 /** @addtogroup FMC_LL_SDRAM_Private_Functions_Group1
1329 * @brief Initialization and Configuration functions
1330 *
1331 @verbatim
1332 ==============================================================================
1333 ##### Initialization and de_initialization functions #####
1334 ==============================================================================
1335 [..]
1336 This section provides functions allowing to:
1337 (+) Initialize and configure the FMC SDRAM interface
1338 (+) De-initialize the FMC SDRAM interface
1339 (+) Configure the FMC clock and associated GPIOs
1340
1341 @endverbatim
1342 * @{
1343 */
1344
1345 /**
1346 * @brief Initializes the FMC_SDRAM device according to the specified
1347 * control parameters in the FMC_SDRAM_InitTypeDef
1348 * @param Device Pointer to SDRAM device instance
1349 * @param Init Pointer to SDRAM Initialization structure
1350 * @retval HAL status
1351 */
1352 HAL_StatusTypeDef FMC_SDRAM_Init(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_InitTypeDef *Init)
1353 {
1354 uint32_t tmpr1 = 0U;
1355 uint32_t tmpr2 = 0U;
1356
1357 /* Check the parameters */
1358 assert_param(IS_FMC_SDRAM_DEVICE(Device));
1359 assert_param(IS_FMC_SDRAM_BANK(Init->SDBank));
1360 assert_param(IS_FMC_COLUMNBITS_NUMBER(Init->ColumnBitsNumber));
1361 assert_param(IS_FMC_ROWBITS_NUMBER(Init->RowBitsNumber));
1362 assert_param(IS_FMC_SDMEMORY_WIDTH(Init->MemoryDataWidth));
1363 assert_param(IS_FMC_INTERNALBANK_NUMBER(Init->InternalBankNumber));
1364 assert_param(IS_FMC_CAS_LATENCY(Init->CASLatency));
1365 assert_param(IS_FMC_WRITE_PROTECTION(Init->WriteProtection));
1366 assert_param(IS_FMC_SDCLOCK_PERIOD(Init->SDClockPeriod));
1367 assert_param(IS_FMC_READ_BURST(Init->ReadBurst));
1368 assert_param(IS_FMC_READPIPE_DELAY(Init->ReadPipeDelay));
1369
1370 /* Set SDRAM bank configuration parameters */
1371 if (Init->SDBank != FMC_SDRAM_BANK2)
1372 {
1373 tmpr1 = Device->SDCR[FMC_SDRAM_BANK1];
1374
1375 /* Clear NC, NR, MWID, NB, CAS, WP, SDCLK, RBURST, and RPIPE bits */
1376 tmpr1 &= ((uint32_t)~(FMC_SDCR1_NC | FMC_SDCR1_NR | FMC_SDCR1_MWID | \
1377 FMC_SDCR1_NB | FMC_SDCR1_CAS | FMC_SDCR1_WP | \
1378 FMC_SDCR1_SDCLK | FMC_SDCR1_RBURST | FMC_SDCR1_RPIPE));
1379
1380
1381 tmpr1 |= (uint32_t)(Init->ColumnBitsNumber |\
1382 Init->RowBitsNumber |\
1383 Init->MemoryDataWidth |\
1384 Init->InternalBankNumber |\
1385 Init->CASLatency |\
1386 Init->WriteProtection |\
1387 Init->SDClockPeriod |\
1388 Init->ReadBurst |\
1389 Init->ReadPipeDelay
1390 );
1391 Device->SDCR[FMC_SDRAM_BANK1] = tmpr1;
1392 }
1393 else /* FMC_Bank2_SDRAM */
1394 {
1395 tmpr1 = Device->SDCR[FMC_SDRAM_BANK1];
1396
1397 /* Clear NC, NR, MWID, NB, CAS, WP, SDCLK, RBURST, and RPIPE bits */
1398 tmpr1 &= ((uint32_t)~(FMC_SDCR1_SDCLK | FMC_SDCR1_RBURST | FMC_SDCR1_RPIPE));
1399
1400 tmpr1 |= (uint32_t)(Init->SDClockPeriod |\
1401 Init->ReadBurst |\
1402 Init->ReadPipeDelay);
1403
1404 tmpr2 = Device->SDCR[FMC_SDRAM_BANK2];
1405
1406 /* Clear NC, NR, MWID, NB, CAS, WP, SDCLK, RBURST, and RPIPE bits */
1407 tmpr2 &= ((uint32_t)~(FMC_SDCR1_NC | FMC_SDCR1_NR | FMC_SDCR1_MWID | \
1408 FMC_SDCR1_NB | FMC_SDCR1_CAS | FMC_SDCR1_WP | \
1409 FMC_SDCR1_SDCLK | FMC_SDCR1_RBURST | FMC_SDCR1_RPIPE));
1410
1411 tmpr2 |= (uint32_t)(Init->ColumnBitsNumber |\
1412 Init->RowBitsNumber |\
1413 Init->MemoryDataWidth |\
1414 Init->InternalBankNumber |\
1415 Init->CASLatency |\
1416 Init->WriteProtection);
1417
1418 Device->SDCR[FMC_SDRAM_BANK1] = tmpr1;
1419 Device->SDCR[FMC_SDRAM_BANK2] = tmpr2;
1420 }
1421
1422 return HAL_OK;
1423 }
1424
1425 /**
1426 * @brief Initializes the FMC_SDRAM device timing according to the specified
1427 * parameters in the FMC_SDRAM_TimingTypeDef
1428 * @param Device Pointer to SDRAM device instance
1429 * @param Timing Pointer to SDRAM Timing structure
1430 * @param Bank SDRAM bank number
1431 * @retval HAL status
1432 */
1433 HAL_StatusTypeDef FMC_SDRAM_Timing_Init(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_TimingTypeDef *Timing, uint32_t Bank)
1434 {
1435 uint32_t tmpr1 = 0U;
1436 uint32_t tmpr2 = 0U;
1437
1438 /* Check the parameters */
1439 assert_param(IS_FMC_SDRAM_DEVICE(Device));
1440 assert_param(IS_FMC_LOADTOACTIVE_DELAY(Timing->LoadToActiveDelay));
1441 assert_param(IS_FMC_EXITSELFREFRESH_DELAY(Timing->ExitSelfRefreshDelay));
1442 assert_param(IS_FMC_SELFREFRESH_TIME(Timing->SelfRefreshTime));
1443 assert_param(IS_FMC_ROWCYCLE_DELAY(Timing->RowCycleDelay));
1444 assert_param(IS_FMC_WRITE_RECOVERY_TIME(Timing->WriteRecoveryTime));
1445 assert_param(IS_FMC_RP_DELAY(Timing->RPDelay));
1446 assert_param(IS_FMC_RCD_DELAY(Timing->RCDDelay));
1447 assert_param(IS_FMC_SDRAM_BANK(Bank));
1448
1449 /* Set SDRAM device timing parameters */
1450 if (Bank != FMC_SDRAM_BANK2)
1451 {
1452 tmpr1 = Device->SDTR[FMC_SDRAM_BANK1];
1453
1454 /* Clear TMRD, TXSR, TRAS, TRC, TWR, TRP and TRCD bits */
1455 tmpr1 &= ((uint32_t)~(FMC_SDTR1_TMRD | FMC_SDTR1_TXSR | FMC_SDTR1_TRAS | \
1456 FMC_SDTR1_TRC | FMC_SDTR1_TWR | FMC_SDTR1_TRP | \
1457 FMC_SDTR1_TRCD));
1458
1459 tmpr1 |= (uint32_t)(((Timing->LoadToActiveDelay)-1U) |\
1460 (((Timing->ExitSelfRefreshDelay)-1U) << 4U) |\
1461 (((Timing->SelfRefreshTime)-1U) << 8U) |\
1462 (((Timing->RowCycleDelay)-1U) << 12U) |\
1463 (((Timing->WriteRecoveryTime)-1U) <<16U) |\
1464 (((Timing->RPDelay)-1U) << 20U) |\
1465 (((Timing->RCDDelay)-1U) << 24U));
1466 Device->SDTR[FMC_SDRAM_BANK1] = tmpr1;
1467 }
1468 else /* FMC_Bank2_SDRAM */
1469 {
1470 tmpr1 = Device->SDTR[FMC_SDRAM_BANK1];
1471
1472 /* Clear TRC and TRP bits */
1473 tmpr1 &= ((uint32_t)~(FMC_SDTR1_TRC | FMC_SDTR1_TRP));
1474
1475 tmpr1 |= (uint32_t)((((Timing->RowCycleDelay)-1U) << 12U) |\
1476 (((Timing->RPDelay)-1U) << 20U));
1477
1478 tmpr2 = Device->SDTR[FMC_SDRAM_BANK2];
1479
1480 /* Clear TMRD, TXSR, TRAS, TRC, TWR, TRP and TRCD bits */
1481 tmpr2 &= ((uint32_t)~(FMC_SDTR1_TMRD | FMC_SDTR1_TXSR | FMC_SDTR1_TRAS | \
1482 FMC_SDTR1_TRC | FMC_SDTR1_TWR | FMC_SDTR1_TRP | \
1483 FMC_SDTR1_TRCD));
1484
1485 tmpr2 |= (uint32_t)((((Timing->LoadToActiveDelay)-1U) |\
1486 (((Timing->ExitSelfRefreshDelay)-1U) << 4U) |\
1487 (((Timing->SelfRefreshTime)-1U) << 8U) |\
1488 (((Timing->WriteRecoveryTime)-1U) <<16U) |\
1489 (((Timing->RCDDelay)-1U) << 24U)));
1490
1491 Device->SDTR[FMC_SDRAM_BANK1] = tmpr1;
1492 Device->SDTR[FMC_SDRAM_BANK2] = tmpr2;
1493 }
1494 return HAL_OK;
1495 }
1496
1497 /**
1498 * @brief DeInitializes the FMC_SDRAM peripheral
1499 * @param Device Pointer to SDRAM device instance
1500 * @retval HAL status
1501 */
1502 HAL_StatusTypeDef FMC_SDRAM_DeInit(FMC_SDRAM_TypeDef *Device, uint32_t Bank)
1503 {
1504 /* Check the parameters */
1505 assert_param(IS_FMC_SDRAM_DEVICE(Device));
1506 assert_param(IS_FMC_SDRAM_BANK(Bank));
1507
1508 /* De-initialize the SDRAM device */
1509 Device->SDCR[Bank] = 0x000002D0U;
1510 Device->SDTR[Bank] = 0x0FFFFFFFU;
1511 Device->SDCMR = 0x00000000U;
1512 Device->SDRTR = 0x00000000U;
1513 Device->SDSR = 0x00000000U;
1514
1515 return HAL_OK;
1516 }
1517
1518 /**
1519 * @}
1520 */
1521
1522 /** @addtogroup FMC_LL_SDRAMPrivate_Functions_Group2
1523 * @brief management functions
1524 *
1525 @verbatim
1526 ==============================================================================
1527 ##### FMC_SDRAM Control functions #####
1528 ==============================================================================
1529 [..]
1530 This subsection provides a set of functions allowing to control dynamically
1531 the FMC SDRAM interface.
1532
1533 @endverbatim
1534 * @{
1535 */
1536 /**
1537 * @brief Enables dynamically FMC_SDRAM write protection.
1538 * @param Device Pointer to SDRAM device instance
1539 * @param Bank SDRAM bank number
1540 * @retval HAL status
1541 */
1542 HAL_StatusTypeDef FMC_SDRAM_WriteProtection_Enable(FMC_SDRAM_TypeDef *Device, uint32_t Bank)
1543 {
1544 /* Check the parameters */
1545 assert_param(IS_FMC_SDRAM_DEVICE(Device));
1546 assert_param(IS_FMC_SDRAM_BANK(Bank));
1547
1548 /* Enable write protection */
1549 Device->SDCR[Bank] |= FMC_SDRAM_WRITE_PROTECTION_ENABLE;
1550
1551 return HAL_OK;
1552 }
1553
1554 /**
1555 * @brief Disables dynamically FMC_SDRAM write protection.
1556 * @param hsdram FMC_SDRAM handle
1557 * @retval HAL status
1558 */
1559 HAL_StatusTypeDef FMC_SDRAM_WriteProtection_Disable(FMC_SDRAM_TypeDef *Device, uint32_t Bank)
1560 {
1561 /* Check the parameters */
1562 assert_param(IS_FMC_SDRAM_DEVICE(Device));
1563 assert_param(IS_FMC_SDRAM_BANK(Bank));
1564
1565 /* Disable write protection */
1566 Device->SDCR[Bank] &= ~FMC_SDRAM_WRITE_PROTECTION_ENABLE;
1567
1568 return HAL_OK;
1569 }
1570
1571 /**
1572 * @brief Send Command to the FMC SDRAM bank
1573 * @param Device Pointer to SDRAM device instance
1574 * @param Command Pointer to SDRAM command structure
1575 * @param Timing Pointer to SDRAM Timing structure
1576 * @param Timeout Timeout wait value
1577 * @retval HAL state
1578 */
1579 HAL_StatusTypeDef FMC_SDRAM_SendCommand(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_CommandTypeDef *Command, uint32_t Timeout)
1580 {
1581 __IO uint32_t tmpr = 0U;
1582 uint32_t tickstart = 0U;
1583
1584 /* Check the parameters */
1585 assert_param(IS_FMC_SDRAM_DEVICE(Device));
1586 assert_param(IS_FMC_COMMAND_MODE(Command->CommandMode));
1587 assert_param(IS_FMC_COMMAND_TARGET(Command->CommandTarget));
1588 assert_param(IS_FMC_AUTOREFRESH_NUMBER(Command->AutoRefreshNumber));
1589 assert_param(IS_FMC_MODE_REGISTER(Command->ModeRegisterDefinition));
1590
1591 /* Set command register */
1592 tmpr = (uint32_t)((Command->CommandMode) |\
1593 (Command->CommandTarget) |\
1594 (((Command->AutoRefreshNumber)-1U) << 5U) |\
1595 ((Command->ModeRegisterDefinition) << 9U)
1596 );
1597
1598 Device->SDCMR = tmpr;
1599
1600 /* Get tick */
1601 tickstart = HAL_GetTick();
1602
1603 /* Wait until command is send */
1604 while(HAL_IS_BIT_SET(Device->SDSR, FMC_SDSR_BUSY))
1605 {
1606 /* Check for the Timeout */
1607 if(Timeout != HAL_MAX_DELAY)
1608 {
1609 if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
1610 {
1611 return HAL_TIMEOUT;
1612 }
1613 }
1614 }
1615
1616 return HAL_OK;
1617 }
1618
1619 /**
1620 * @brief Program the SDRAM Memory Refresh rate.
1621 * @param Device Pointer to SDRAM device instance
1622 * @param RefreshRate The SDRAM refresh rate value.
1623 * @retval HAL state
1624 */
1625 HAL_StatusTypeDef FMC_SDRAM_ProgramRefreshRate(FMC_SDRAM_TypeDef *Device, uint32_t RefreshRate)
1626 {
1627 /* Check the parameters */
1628 assert_param(IS_FMC_SDRAM_DEVICE(Device));
1629 assert_param(IS_FMC_REFRESH_RATE(RefreshRate));
1630
1631 /* Set the refresh rate in command register */
1632 Device->SDRTR |= (RefreshRate<<1U);
1633
1634 return HAL_OK;
1635 }
1636
1637 /**
1638 * @brief Set the Number of consecutive SDRAM Memory auto Refresh commands.
1639 * @param Device Pointer to SDRAM device instance
1640 * @param AutoRefreshNumber Specifies the auto Refresh number.
1641 * @retval None
1642 */
1643 HAL_StatusTypeDef FMC_SDRAM_SetAutoRefreshNumber(FMC_SDRAM_TypeDef *Device, uint32_t AutoRefreshNumber)
1644 {
1645 /* Check the parameters */
1646 assert_param(IS_FMC_SDRAM_DEVICE(Device));
1647 assert_param(IS_FMC_AUTOREFRESH_NUMBER(AutoRefreshNumber));
1648
1649 /* Set the Auto-refresh number in command register */
1650 Device->SDCMR |= (AutoRefreshNumber << 5U);
1651
1652 return HAL_OK;
1653 }
1654
1655 /**
1656 * @brief Returns the indicated FMC SDRAM bank mode status.
1657 * @param Device Pointer to SDRAM device instance
1658 * @param Bank Defines the FMC SDRAM bank. This parameter can be
1659 * FMC_Bank1_SDRAM or FMC_Bank2_SDRAM.
1660 * @retval The FMC SDRAM bank mode status, could be on of the following values:
1661 * FMC_SDRAM_NORMAL_MODE, FMC_SDRAM_SELF_REFRESH_MODE or
1662 * FMC_SDRAM_POWER_DOWN_MODE.
1663 */
1664 uint32_t FMC_SDRAM_GetModeStatus(FMC_SDRAM_TypeDef *Device, uint32_t Bank)
1665 {
1666 uint32_t tmpreg = 0U;
1667
1668 /* Check the parameters */
1669 assert_param(IS_FMC_SDRAM_DEVICE(Device));
1670 assert_param(IS_FMC_SDRAM_BANK(Bank));
1671
1672 /* Get the corresponding bank mode */
1673 if(Bank == FMC_SDRAM_BANK1)
1674 {
1675 tmpreg = (uint32_t)(Device->SDSR & FMC_SDSR_MODES1);
1676 }
1677 else
1678 {
1679 tmpreg = ((uint32_t)(Device->SDSR & FMC_SDSR_MODES2) >> 2U);
1680 }
1681
1682 /* Return the mode status */
1683 return tmpreg;
1684 }
1685
1686 /**
1687 * @}
1688 */
1689
1690 /**
1691 * @}
1692 */
1693
1694 /**
1695 * @}
1696 */
1697 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */
1698 #endif /* HAL_SRAM_MODULE_ENABLED || HAL_NOR_MODULE_ENABLED || HAL_NAND_MODULE_ENABLED || HAL_PCCARD_MODULE_ENABLED || HAL_SDRAM_MODULE_ENABLED */
1699
1700 /**
1701 * @}
1702 */
1703
1704 /**
1705 * @}
1706 */
1707
1708 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/