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comparison Common/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_qspi.c @ 160:e3ca52b8e7fa

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Merge with FlipDisplay
author heinrichsweikamp
date Thu, 07 Mar 2019 15:06:43 +0100
parents c78bcbd5deda
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80:cc2bb7bb8456 160:e3ca52b8e7fa
1 /**
2 ******************************************************************************
3 * @file stm32f4xx_hal_qspi.c
4 * @author MCD Application Team
5 * @brief QSPI HAL module driver.
6 * This file provides firmware functions to manage the following
7 * functionalities of the QuadSPI interface (QSPI).
8 * + Initialization and de-initialization functions
9 * + Indirect functional mode management
10 * + Memory-mapped functional mode management
11 * + Auto-polling functional mode management
12 * + Interrupts and flags management
13 * + DMA channel configuration for indirect functional mode
14 * + Errors management and abort functionality
15 *
16 *
17 @verbatim
18 ===============================================================================
19 ##### How to use this driver #####
20 ===============================================================================
21 [..]
22 *** Initialization ***
23 ======================
24 [..]
25 (#) As prerequisite, fill in the HAL_QSPI_MspInit() :
26 (++) Enable QuadSPI clock interface with __HAL_RCC_QSPI_CLK_ENABLE().
27 (++) Reset QuadSPI IP with __HAL_RCC_QSPI_FORCE_RESET() and __HAL_RCC_QSPI_RELEASE_RESET().
28 (++) Enable the clocks for the QuadSPI GPIOS with __HAL_RCC_GPIOx_CLK_ENABLE().
29 (++) Configure these QuadSPI pins in alternate mode using HAL_GPIO_Init().
30 (++) If interrupt mode is used, enable and configure QuadSPI global
31 interrupt with HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ().
32 (++) If DMA mode is used, enable the clocks for the QuadSPI DMA channel
33 with __HAL_RCC_DMAx_CLK_ENABLE(), configure DMA with HAL_DMA_Init(),
34 link it with QuadSPI handle using __HAL_LINKDMA(), enable and configure
35 DMA channel global interrupt with HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ().
36 (#) Configure the flash size, the clock prescaler, the fifo threshold, the
37 clock mode, the sample shifting and the CS high time using the HAL_QSPI_Init() function.
38
39 *** Indirect functional mode ***
40 ================================
41 [..]
42 (#) Configure the command sequence using the HAL_QSPI_Command() or HAL_QSPI_Command_IT()
43 functions :
44 (++) Instruction phase : the mode used and if present the instruction opcode.
45 (++) Address phase : the mode used and if present the size and the address value.
46 (++) Alternate-bytes phase : the mode used and if present the size and the alternate
47 bytes values.
48 (++) Dummy-cycles phase : the number of dummy cycles (mode used is same as data phase).
49 (++) Data phase : the mode used and if present the number of bytes.
50 (++) Double Data Rate (DDR) mode : the activation (or not) of this mode and the delay
51 if activated.
52 (++) Sending Instruction Only Once (SIOO) mode : the activation (or not) of this mode.
53 (#) If no data is required for the command, it is sent directly to the memory :
54 (++) In polling mode, the output of the function is done when the transfer is complete.
55 (++) In interrupt mode, HAL_QSPI_CmdCpltCallback() will be called when the transfer is complete.
56 (#) For the indirect write mode, use HAL_QSPI_Transmit(), HAL_QSPI_Transmit_DMA() or
57 HAL_QSPI_Transmit_IT() after the command configuration :
58 (++) In polling mode, the output of the function is done when the transfer is complete.
59 (++) In interrupt mode, HAL_QSPI_FifoThresholdCallback() will be called when the fifo threshold
60 is reached and HAL_QSPI_TxCpltCallback() will be called when the transfer is complete.
61 (++) In DMA mode, HAL_QSPI_TxHalfCpltCallback() will be called at the half transfer and
62 HAL_QSPI_TxCpltCallback() will be called when the transfer is complete.
63 (#) For the indirect read mode, use HAL_QSPI_Receive(), HAL_QSPI_Receive_DMA() or
64 HAL_QSPI_Receive_IT() after the command configuration :
65 (++) In polling mode, the output of the function is done when the transfer is complete.
66 (++) In interrupt mode, HAL_QSPI_FifoThresholdCallback() will be called when the fifo threshold
67 is reached and HAL_QSPI_RxCpltCallback() will be called when the transfer is complete.
68 (++) In DMA mode, HAL_QSPI_RxHalfCpltCallback() will be called at the half transfer and
69 HAL_QSPI_RxCpltCallback() will be called when the transfer is complete.
70
71 *** Auto-polling functional mode ***
72 ====================================
73 [..]
74 (#) Configure the command sequence and the auto-polling functional mode using the
75 HAL_QSPI_AutoPolling() or HAL_QSPI_AutoPolling_IT() functions :
76 (++) Instruction phase : the mode used and if present the instruction opcode.
77 (++) Address phase : the mode used and if present the size and the address value.
78 (++) Alternate-bytes phase : the mode used and if present the size and the alternate
79 bytes values.
80 (++) Dummy-cycles phase : the number of dummy cycles (mode used is same as data phase).
81 (++) Data phase : the mode used.
82 (++) Double Data Rate (DDR) mode : the activation (or not) of this mode and the delay
83 if activated.
84 (++) Sending Instruction Only Once (SIOO) mode : the activation (or not) of this mode.
85 (++) The size of the status bytes, the match value, the mask used, the match mode (OR/AND),
86 the polling interval and the automatic stop activation.
87 (#) After the configuration :
88 (++) In polling mode, the output of the function is done when the status match is reached. The
89 automatic stop is activated to avoid an infinite loop.
90 (++) In interrupt mode, HAL_QSPI_StatusMatchCallback() will be called each time the status match is reached.
91
92 *** Memory-mapped functional mode ***
93 =====================================
94 [..]
95 (#) Configure the command sequence and the memory-mapped functional mode using the
96 HAL_QSPI_MemoryMapped() functions :
97 (++) Instruction phase : the mode used and if present the instruction opcode.
98 (++) Address phase : the mode used and the size.
99 (++) Alternate-bytes phase : the mode used and if present the size and the alternate
100 bytes values.
101 (++) Dummy-cycles phase : the number of dummy cycles (mode used is same as data phase).
102 (++) Data phase : the mode used.
103 (++) Double Data Rate (DDR) mode : the activation (or not) of this mode and the delay
104 if activated.
105 (++) Sending Instruction Only Once (SIOO) mode : the activation (or not) of this mode.
106 (++) The timeout activation and the timeout period.
107 (#) After the configuration, the QuadSPI will be used as soon as an access on the AHB is done on
108 the address range. HAL_QSPI_TimeOutCallback() will be called when the timeout expires.
109
110 *** Errors management and abort functionality ***
111 ==================================================
112 [..]
113 (#) HAL_QSPI_GetError() function gives the error raised during the last operation.
114 (#) HAL_QSPI_Abort() and HAL_QSPI_AbortIT() functions aborts any on-going operation and
115 flushes the fifo :
116 (++) In polling mode, the output of the function is done when the transfer
117 complete bit is set and the busy bit cleared.
118 (++) In interrupt mode, HAL_QSPI_AbortCpltCallback() will be called when
119 the transfer complete bi is set.
120
121 *** Control functions ***
122 =========================
123 [..]
124 (#) HAL_QSPI_GetState() function gives the current state of the HAL QuadSPI driver.
125 (#) HAL_QSPI_SetTimeout() function configures the timeout value used in the driver.
126 (#) HAL_QSPI_SetFifoThreshold() function configures the threshold on the Fifo of the QSPI IP.
127 (#) HAL_QSPI_GetFifoThreshold() function gives the current of the Fifo's threshold
128
129 *** Workarounds linked to Silicon Limitation ***
130 ====================================================
131 [..]
132 (#) Workarounds Implemented inside HAL Driver
133 (++) Extra data written in the FIFO at the end of a read transfer
134
135 @endverbatim
136 ******************************************************************************
137 * @attention
138 *
139 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
140 *
141 * Redistribution and use in source and binary forms, with or without modification,
142 * are permitted provided that the following conditions are met:
143 * 1. Redistributions of source code must retain the above copyright notice,
144 * this list of conditions and the following disclaimer.
145 * 2. Redistributions in binary form must reproduce the above copyright notice,
146 * this list of conditions and the following disclaimer in the documentation
147 * and/or other materials provided with the distribution.
148 * 3. Neither the name of STMicroelectronics nor the names of its contributors
149 * may be used to endorse or promote products derived from this software
150 * without specific prior written permission.
151 *
152 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
153 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
154 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
155 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
156 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
157 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
158 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
159 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
160 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
161 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
162 *
163 ******************************************************************************
164 */
165
166 /* Includes ------------------------------------------------------------------*/
167 #include "stm32f4xx_hal.h"
168
169 /** @addtogroup STM32F4xx_HAL_Driver
170 * @{
171 */
172
173 /** @defgroup QSPI QSPI
174 * @brief QSPI HAL module driver
175 * @{
176 */
177 #ifdef HAL_QSPI_MODULE_ENABLED
178
179 #if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \
180 defined(STM32F412Rx) || defined(STM32F413xx) || defined(STM32F423xx)
181
182 /* Private typedef -----------------------------------------------------------*/
183 /* Private define ------------------------------------------------------------*/
184 /** @addtogroup QSPI_Private_Constants
185 * @{
186 */
187 #define QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE 0x00000000U /*!<Indirect write mode*/
188 #define QSPI_FUNCTIONAL_MODE_INDIRECT_READ ((uint32_t)QUADSPI_CCR_FMODE_0) /*!<Indirect read mode*/
189 #define QSPI_FUNCTIONAL_MODE_AUTO_POLLING ((uint32_t)QUADSPI_CCR_FMODE_1) /*!<Automatic polling mode*/
190 #define QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED ((uint32_t)QUADSPI_CCR_FMODE) /*!<Memory-mapped mode*/
191 /**
192 * @}
193 */
194
195 /* Private macro -------------------------------------------------------------*/
196 /** @addtogroup QSPI_Private_Macros QSPI Private Macros
197 * @{
198 */
199 #define IS_QSPI_FUNCTIONAL_MODE(MODE) (((MODE) == QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE) || \
200 ((MODE) == QSPI_FUNCTIONAL_MODE_INDIRECT_READ) || \
201 ((MODE) == QSPI_FUNCTIONAL_MODE_AUTO_POLLING) || \
202 ((MODE) == QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED))
203 /**
204 * @}
205 */
206
207 /* Private variables ---------------------------------------------------------*/
208 /* Private function prototypes -----------------------------------------------*/
209 /** @addtogroup QSPI_Private_Functions QSPI Private Functions
210 * @{
211 */
212 static void QSPI_DMARxCplt(DMA_HandleTypeDef *hdma);
213 static void QSPI_DMATxCplt(DMA_HandleTypeDef *hdma);
214 static void QSPI_DMARxHalfCplt(DMA_HandleTypeDef *hdma);
215 static void QSPI_DMATxHalfCplt(DMA_HandleTypeDef *hdma);
216 static void QSPI_DMAError(DMA_HandleTypeDef *hdma);
217 static void QSPI_DMAAbortCplt(DMA_HandleTypeDef *hdma);
218 static HAL_StatusTypeDef QSPI_WaitFlagStateUntilTimeout(QSPI_HandleTypeDef *hqspi, uint32_t Flag, FlagStatus State, uint32_t tickstart, uint32_t Timeout);
219 static void QSPI_Config(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uint32_t FunctionalMode);
220 /**
221 * @}
222 */
223
224 /* Exported functions ---------------------------------------------------------*/
225
226 /** @defgroup QSPI_Exported_Functions QSPI Exported Functions
227 * @{
228 */
229
230 /** @defgroup QSPI_Exported_Functions_Group1 Initialization/de-initialization functions
231 * @brief Initialization and Configuration functions
232 *
233 @verbatim
234 ===============================================================================
235 ##### Initialization and Configuration functions #####
236 ===============================================================================
237 [..]
238 This subsection provides a set of functions allowing to :
239 (+) Initialize the QuadSPI.
240 (+) De-initialize the QuadSPI.
241
242 @endverbatim
243 * @{
244 */
245
246 /**
247 * @brief Initializes the QSPI mode according to the specified parameters
248 * in the QSPI_InitTypeDef and creates the associated handle.
249 * @param hqspi qspi handle
250 * @retval HAL status
251 */
252 HAL_StatusTypeDef HAL_QSPI_Init(QSPI_HandleTypeDef *hqspi)
253 {
254 HAL_StatusTypeDef status = HAL_ERROR;
255 uint32_t tickstart = HAL_GetTick();
256
257 /* Check the QSPI handle allocation */
258 if(hqspi == NULL)
259 {
260 return HAL_ERROR;
261 }
262
263 /* Check the parameters */
264 assert_param(IS_QSPI_ALL_INSTANCE(hqspi->Instance));
265 assert_param(IS_QSPI_CLOCK_PRESCALER(hqspi->Init.ClockPrescaler));
266 assert_param(IS_QSPI_FIFO_THRESHOLD(hqspi->Init.FifoThreshold));
267 assert_param(IS_QSPI_SSHIFT(hqspi->Init.SampleShifting));
268 assert_param(IS_QSPI_FLASH_SIZE(hqspi->Init.FlashSize));
269 assert_param(IS_QSPI_CS_HIGH_TIME(hqspi->Init.ChipSelectHighTime));
270 assert_param(IS_QSPI_CLOCK_MODE(hqspi->Init.ClockMode));
271 assert_param(IS_QSPI_DUAL_FLASH_MODE(hqspi->Init.DualFlash));
272
273 if (hqspi->Init.DualFlash != QSPI_DUALFLASH_ENABLE )
274 {
275 assert_param(IS_QSPI_FLASH_ID(hqspi->Init.FlashID));
276 }
277
278 /* Process locked */
279 __HAL_LOCK(hqspi);
280
281 if(hqspi->State == HAL_QSPI_STATE_RESET)
282 {
283 /* Allocate lock resource and initialize it */
284 hqspi->Lock = HAL_UNLOCKED;
285
286 /* Init the low level hardware : GPIO, CLOCK */
287 HAL_QSPI_MspInit(hqspi);
288
289 /* Configure the default timeout for the QSPI memory access */
290 HAL_QSPI_SetTimeout(hqspi, HAL_QPSI_TIMEOUT_DEFAULT_VALUE);
291 }
292
293 /* Configure QSPI FIFO Threshold */
294 MODIFY_REG(hqspi->Instance->CR, QUADSPI_CR_FTHRES, ((hqspi->Init.FifoThreshold - 1U) << 8U));
295
296 /* Wait till BUSY flag reset */
297 status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, tickstart, hqspi->Timeout);
298
299 if(status == HAL_OK)
300 {
301
302 /* Configure QSPI Clock Prescaler and Sample Shift */
303 MODIFY_REG(hqspi->Instance->CR,(QUADSPI_CR_PRESCALER | QUADSPI_CR_SSHIFT | QUADSPI_CR_FSEL | QUADSPI_CR_DFM), ((hqspi->Init.ClockPrescaler << 24U)| hqspi->Init.SampleShifting | hqspi->Init.FlashID| hqspi->Init.DualFlash ));
304
305 /* Configure QSPI Flash Size, CS High Time and Clock Mode */
306 MODIFY_REG(hqspi->Instance->DCR, (QUADSPI_DCR_FSIZE | QUADSPI_DCR_CSHT | QUADSPI_DCR_CKMODE),
307 ((hqspi->Init.FlashSize << 16U) | hqspi->Init.ChipSelectHighTime | hqspi->Init.ClockMode));
308
309 /* Enable the QSPI peripheral */
310 __HAL_QSPI_ENABLE(hqspi);
311
312 /* Set QSPI error code to none */
313 hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
314
315 /* Initialize the QSPI state */
316 hqspi->State = HAL_QSPI_STATE_READY;
317 }
318
319 /* Release Lock */
320 __HAL_UNLOCK(hqspi);
321
322 /* Return function status */
323 return status;
324 }
325
326 /**
327 * @brief DeInitializes the QSPI peripheral
328 * @param hqspi qspi handle
329 * @retval HAL status
330 */
331 HAL_StatusTypeDef HAL_QSPI_DeInit(QSPI_HandleTypeDef *hqspi)
332 {
333 /* Check the QSPI handle allocation */
334 if(hqspi == NULL)
335 {
336 return HAL_ERROR;
337 }
338
339 /* Process locked */
340 __HAL_LOCK(hqspi);
341
342 /* Disable the QSPI Peripheral Clock */
343 __HAL_QSPI_DISABLE(hqspi);
344
345 /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */
346 HAL_QSPI_MspDeInit(hqspi);
347
348 /* Set QSPI error code to none */
349 hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
350
351 /* Initialize the QSPI state */
352 hqspi->State = HAL_QSPI_STATE_RESET;
353
354 /* Release Lock */
355 __HAL_UNLOCK(hqspi);
356
357 return HAL_OK;
358 }
359
360 /**
361 * @brief QSPI MSP Init
362 * @param hqspi QSPI handle
363 * @retval None
364 */
365 __weak void HAL_QSPI_MspInit(QSPI_HandleTypeDef *hqspi)
366 {
367 /* Prevent unused argument(s) compilation warning */
368 UNUSED(hqspi);
369
370 /* NOTE : This function should not be modified, when the callback is needed,
371 the HAL_QSPI_MspInit can be implemented in the user file
372 */
373 }
374
375 /**
376 * @brief QSPI MSP DeInit
377 * @param hqspi QSPI handle
378 * @retval None
379 */
380 __weak void HAL_QSPI_MspDeInit(QSPI_HandleTypeDef *hqspi)
381 {
382 /* Prevent unused argument(s) compilation warning */
383 UNUSED(hqspi);
384
385 /* NOTE : This function should not be modified, when the callback is needed,
386 the HAL_QSPI_MspDeInit can be implemented in the user file
387 */
388 }
389
390 /**
391 * @}
392 */
393
394 /** @defgroup QSPI_Exported_Functions_Group2 IO operation functions
395 * @brief QSPI Transmit/Receive functions
396 *
397 @verbatim
398 ===============================================================================
399 ##### IO operation functions #####
400 ===============================================================================
401 [..]
402 This subsection provides a set of functions allowing to :
403 (+) Handle the interrupts.
404 (+) Handle the command sequence.
405 (+) Transmit data in blocking, interrupt or DMA mode.
406 (+) Receive data in blocking, interrupt or DMA mode.
407 (+) Manage the auto-polling functional mode.
408 (+) Manage the memory-mapped functional mode.
409
410 @endverbatim
411 * @{
412 */
413
414 /**
415 * @brief This function handles QSPI interrupt request.
416 * @param hqspi QSPI handle
417 * @retval None.
418 */
419 void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi)
420 {
421 __IO uint32_t *data_reg;
422 uint32_t flag = READ_REG(hqspi->Instance->SR);
423 uint32_t itsource = READ_REG(hqspi->Instance->CR);
424
425 /* QSPI Fifo Threshold interrupt occurred ----------------------------------*/
426 if(((flag & QSPI_FLAG_FT)!= RESET) && ((itsource & QSPI_IT_FT)!= RESET))
427 {
428 data_reg = &hqspi->Instance->DR;
429
430 if(hqspi->State == HAL_QSPI_STATE_BUSY_INDIRECT_TX)
431 {
432 /* Transmission process */
433 while(__HAL_QSPI_GET_FLAG(hqspi, QSPI_FLAG_FT) != 0U)
434 {
435 if (hqspi->TxXferCount > 0U)
436 {
437 /* Fill the FIFO until it is full */
438 *(__IO uint8_t *)data_reg = *hqspi->pTxBuffPtr++;
439 hqspi->TxXferCount--;
440 }
441 else
442 {
443 /* No more data available for the transfer */
444 /* Disable the QSPI FIFO Threshold Interrupt */
445 __HAL_QSPI_DISABLE_IT(hqspi, QSPI_IT_FT);
446 break;
447 }
448 }
449 }
450 else if(hqspi->State == HAL_QSPI_STATE_BUSY_INDIRECT_RX)
451 {
452 /* Receiving Process */
453 while(__HAL_QSPI_GET_FLAG(hqspi, QSPI_FLAG_FT) != 0U)
454 {
455 if (hqspi->RxXferCount > 0U)
456 {
457 /* Read the FIFO until it is empty */
458 *hqspi->pRxBuffPtr++ = *(__IO uint8_t *)data_reg;
459 hqspi->RxXferCount--;
460 }
461 else
462 {
463 /* All data have been received for the transfer */
464 /* Disable the QSPI FIFO Threshold Interrupt */
465 __HAL_QSPI_DISABLE_IT(hqspi, QSPI_IT_FT);
466 break;
467 }
468 }
469 }
470
471 /* FIFO Threshold callback */
472 HAL_QSPI_FifoThresholdCallback(hqspi);
473 }
474
475 /* QSPI Transfer Complete interrupt occurred -------------------------------*/
476 else if(((flag & QSPI_FLAG_TC)!= RESET) && ((itsource & QSPI_IT_TC)!= RESET))
477 {
478 /* Clear interrupt */
479 WRITE_REG(hqspi->Instance->FCR, QSPI_FLAG_TC);
480
481 /* Disable the QSPI FIFO Threshold, Transfer Error and Transfer complete Interrupts */
482 __HAL_QSPI_DISABLE_IT(hqspi, QSPI_IT_TC | QSPI_IT_TE | QSPI_IT_FT);
483
484 /* Transfer complete callback */
485 if(hqspi->State == HAL_QSPI_STATE_BUSY_INDIRECT_TX)
486 {
487 if ((hqspi->Instance->CR & QUADSPI_CR_DMAEN)!= RESET)
488 {
489 /* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */
490 CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
491
492 /* Disable the DMA channel */
493 __HAL_DMA_DISABLE(hqspi->hdma);
494 }
495
496 /* Clear Busy bit */
497 HAL_QSPI_Abort_IT(hqspi);
498
499 /* Change state of QSPI */
500 hqspi->State = HAL_QSPI_STATE_READY;
501
502 /* TX Complete callback */
503 HAL_QSPI_TxCpltCallback(hqspi);
504 }
505 else if(hqspi->State == HAL_QSPI_STATE_BUSY_INDIRECT_RX)
506 {
507 if ((hqspi->Instance->CR & QUADSPI_CR_DMAEN)!= RESET)
508 {
509 /* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */
510 CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
511
512 /* Disable the DMA channel */
513 __HAL_DMA_DISABLE(hqspi->hdma);
514 }
515 else
516 {
517 data_reg = &hqspi->Instance->DR;
518 while(READ_BIT(hqspi->Instance->SR, QUADSPI_SR_FLEVEL) != 0U)
519 {
520 if (hqspi->RxXferCount > 0U)
521 {
522 /* Read the last data received in the FIFO until it is empty */
523 *hqspi->pRxBuffPtr++ = *(__IO uint8_t *)data_reg;
524 hqspi->RxXferCount--;
525 }
526 else
527 {
528 /* All data have been received for the transfer */
529 break;
530 }
531 }
532 }
533 /* Workaround - Extra data written in the FIFO at the end of a read transfer */
534 HAL_QSPI_Abort_IT(hqspi);
535
536 /* Change state of QSPI */
537 hqspi->State = HAL_QSPI_STATE_READY;
538
539 /* RX Complete callback */
540 HAL_QSPI_RxCpltCallback(hqspi);
541 }
542 else if(hqspi->State == HAL_QSPI_STATE_BUSY)
543 {
544 /* Change state of QSPI */
545 hqspi->State = HAL_QSPI_STATE_READY;
546
547 /* Command Complete callback */
548 HAL_QSPI_CmdCpltCallback(hqspi);
549 }
550 else if(hqspi->State == HAL_QSPI_STATE_ABORT)
551 {
552 /* Change state of QSPI */
553 hqspi->State = HAL_QSPI_STATE_READY;
554
555 if (hqspi->ErrorCode == HAL_QSPI_ERROR_NONE)
556 {
557 /* Abort called by the user */
558
559 /* Abort Complete callback */
560 HAL_QSPI_AbortCpltCallback(hqspi);
561 }
562 else
563 {
564 /* Abort due to an error (eg : DMA error) */
565
566 /* Error callback */
567 HAL_QSPI_ErrorCallback(hqspi);
568 }
569 }
570 }
571
572 /* QSPI Status Match interrupt occurred ------------------------------------*/
573 else if(((flag & QSPI_FLAG_SM)!= RESET) && ((itsource & QSPI_IT_SM)!= RESET))
574 {
575 /* Clear interrupt */
576 WRITE_REG(hqspi->Instance->FCR, QSPI_FLAG_SM);
577
578 /* Check if the automatic poll mode stop is activated */
579 if(READ_BIT(hqspi->Instance->CR, QUADSPI_CR_APMS) != 0U)
580 {
581 /* Disable the QSPI Transfer Error and Status Match Interrupts */
582 __HAL_QSPI_DISABLE_IT(hqspi, (QSPI_IT_SM | QSPI_IT_TE));
583
584 /* Change state of QSPI */
585 hqspi->State = HAL_QSPI_STATE_READY;
586 }
587
588 /* Status match callback */
589 HAL_QSPI_StatusMatchCallback(hqspi);
590 }
591
592 /* QSPI Transfer Error interrupt occurred ----------------------------------*/
593 else if(((flag & QSPI_FLAG_TE)!= RESET) && ((itsource & QSPI_IT_TE)!= RESET))
594 {
595 /* Clear interrupt */
596 WRITE_REG(hqspi->Instance->FCR, QSPI_FLAG_TE);
597
598 /* Disable all the QSPI Interrupts */
599 __HAL_QSPI_DISABLE_IT(hqspi, QSPI_IT_SM | QSPI_IT_TC | QSPI_IT_TE | QSPI_IT_FT);
600
601 /* Set error code */
602 hqspi->ErrorCode |= HAL_QSPI_ERROR_TRANSFER;
603
604 if ((hqspi->Instance->CR & QUADSPI_CR_DMAEN)!= RESET)
605 {
606 /* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */
607 CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
608
609 /* Disable the DMA channel */
610 hqspi->hdma->XferAbortCallback = QSPI_DMAAbortCplt;
611 HAL_DMA_Abort_IT(hqspi->hdma);
612 }
613 else
614 {
615 /* Change state of QSPI */
616 hqspi->State = HAL_QSPI_STATE_READY;
617
618 /* Error callback */
619 HAL_QSPI_ErrorCallback(hqspi);
620 }
621 }
622
623 /* QSPI Timeout interrupt occurred -----------------------------------------*/
624 else if(((flag & QSPI_FLAG_TO)!= RESET) && ((itsource & QSPI_IT_TO)!= RESET))
625 {
626 /* Clear interrupt */
627 WRITE_REG(hqspi->Instance->FCR, QSPI_FLAG_TO);
628
629 /* Time out callback */
630 HAL_QSPI_TimeOutCallback(hqspi);
631 }
632 }
633
634 /**
635 * @brief Sets the command configuration.
636 * @param hqspi QSPI handle
637 * @param cmd structure that contains the command configuration information
638 * @param Timeout Time out duration
639 * @note This function is used only in Indirect Read or Write Modes
640 * @retval HAL status
641 */
642 HAL_StatusTypeDef HAL_QSPI_Command(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uint32_t Timeout)
643 {
644 HAL_StatusTypeDef status = HAL_ERROR;
645 uint32_t tickstart = HAL_GetTick();
646
647 /* Check the parameters */
648 assert_param(IS_QSPI_INSTRUCTION_MODE(cmd->InstructionMode));
649 if (cmd->InstructionMode != QSPI_INSTRUCTION_NONE)
650 {
651 assert_param(IS_QSPI_INSTRUCTION(cmd->Instruction));
652 }
653
654 assert_param(IS_QSPI_ADDRESS_MODE(cmd->AddressMode));
655 if (cmd->AddressMode != QSPI_ADDRESS_NONE)
656 {
657 assert_param(IS_QSPI_ADDRESS_SIZE(cmd->AddressSize));
658 }
659
660 assert_param(IS_QSPI_ALTERNATE_BYTES_MODE(cmd->AlternateByteMode));
661 if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE)
662 {
663 assert_param(IS_QSPI_ALTERNATE_BYTES_SIZE(cmd->AlternateBytesSize));
664 }
665
666 assert_param(IS_QSPI_DUMMY_CYCLES(cmd->DummyCycles));
667 assert_param(IS_QSPI_DATA_MODE(cmd->DataMode));
668
669 assert_param(IS_QSPI_DDR_MODE(cmd->DdrMode));
670 assert_param(IS_QSPI_DDR_HHC(cmd->DdrHoldHalfCycle));
671 assert_param(IS_QSPI_SIOO_MODE(cmd->SIOOMode));
672
673 /* Process locked */
674 __HAL_LOCK(hqspi);
675
676 if(hqspi->State == HAL_QSPI_STATE_READY)
677 {
678 hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
679
680 /* Update QSPI state */
681 hqspi->State = HAL_QSPI_STATE_BUSY;
682
683 /* Wait till BUSY flag reset */
684 status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, tickstart, Timeout);
685
686 if (status == HAL_OK)
687 {
688 /* Call the configuration function */
689 QSPI_Config(hqspi, cmd, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE);
690
691 if (cmd->DataMode == QSPI_DATA_NONE)
692 {
693 /* When there is no data phase, the transfer start as soon as the configuration is done
694 so wait until TC flag is set to go back in idle state */
695 status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_TC, SET, tickstart, Timeout);
696
697 if (status == HAL_OK)
698 {
699 __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);
700
701 /* Update QSPI state */
702 hqspi->State = HAL_QSPI_STATE_READY;
703 }
704
705 }
706 else
707 {
708 /* Update QSPI state */
709 hqspi->State = HAL_QSPI_STATE_READY;
710 }
711 }
712 }
713 else
714 {
715 status = HAL_BUSY;
716 }
717
718 /* Process unlocked */
719 __HAL_UNLOCK(hqspi);
720
721 /* Return function status */
722 return status;
723 }
724
725 /**
726 * @brief Sets the command configuration in interrupt mode.
727 * @param hqspi QSPI handle
728 * @param cmd structure that contains the command configuration information
729 * @note This function is used only in Indirect Read or Write Modes
730 * @retval HAL status
731 */
732 HAL_StatusTypeDef HAL_QSPI_Command_IT(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd)
733 {
734 __IO uint32_t count = 0U;
735 HAL_StatusTypeDef status = HAL_OK;
736
737 /* Check the parameters */
738 assert_param(IS_QSPI_INSTRUCTION_MODE(cmd->InstructionMode));
739 if (cmd->InstructionMode != QSPI_INSTRUCTION_NONE)
740 {
741 assert_param(IS_QSPI_INSTRUCTION(cmd->Instruction));
742 }
743
744 assert_param(IS_QSPI_ADDRESS_MODE(cmd->AddressMode));
745 if (cmd->AddressMode != QSPI_ADDRESS_NONE)
746 {
747 assert_param(IS_QSPI_ADDRESS_SIZE(cmd->AddressSize));
748 }
749
750 assert_param(IS_QSPI_ALTERNATE_BYTES_MODE(cmd->AlternateByteMode));
751 if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE)
752 {
753 assert_param(IS_QSPI_ALTERNATE_BYTES_SIZE(cmd->AlternateBytesSize));
754 }
755
756 assert_param(IS_QSPI_DUMMY_CYCLES(cmd->DummyCycles));
757 assert_param(IS_QSPI_DATA_MODE(cmd->DataMode));
758
759 assert_param(IS_QSPI_DDR_MODE(cmd->DdrMode));
760 assert_param(IS_QSPI_DDR_HHC(cmd->DdrHoldHalfCycle));
761 assert_param(IS_QSPI_SIOO_MODE(cmd->SIOOMode));
762
763 /* Process locked */
764 __HAL_LOCK(hqspi);
765
766 if(hqspi->State == HAL_QSPI_STATE_READY)
767 {
768 hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
769
770 /* Update QSPI state */
771 hqspi->State = HAL_QSPI_STATE_BUSY;
772
773 /* Wait till BUSY flag reset */
774 count = (hqspi->Timeout) * (SystemCoreClock / 16U / 1000U);
775 do
776 {
777 if (count-- == 0U)
778 {
779 hqspi->State = HAL_QSPI_STATE_ERROR;
780 hqspi->ErrorCode |= HAL_QSPI_ERROR_TIMEOUT;
781 status = HAL_TIMEOUT;
782 }
783 }
784 while ((__HAL_QSPI_GET_FLAG(hqspi, QSPI_FLAG_BUSY)) != RESET);
785
786 if (status == HAL_OK)
787 {
788 if (cmd->DataMode == QSPI_DATA_NONE)
789 {
790 /* Clear interrupt */
791 __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TE | QSPI_FLAG_TC);
792 }
793
794 /* Call the configuration function */
795 QSPI_Config(hqspi, cmd, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE);
796
797 if (cmd->DataMode == QSPI_DATA_NONE)
798 {
799 /* When there is no data phase, the transfer start as soon as the configuration is done
800 so activate TC and TE interrupts */
801 /* Process unlocked */
802 __HAL_UNLOCK(hqspi);
803
804 /* Enable the QSPI Transfer Error Interrupt */
805 __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE | QSPI_IT_TC);
806 }
807 else
808 {
809 /* Update QSPI state */
810 hqspi->State = HAL_QSPI_STATE_READY;
811
812 /* Process unlocked */
813 __HAL_UNLOCK(hqspi);
814 }
815 }
816 else
817 {
818 /* Process unlocked */
819 __HAL_UNLOCK(hqspi);
820 }
821 }
822 else
823 {
824 status = HAL_BUSY;
825
826 /* Process unlocked */
827 __HAL_UNLOCK(hqspi);
828 }
829
830 /* Return function status */
831 return status;
832 }
833
834 /**
835 * @brief Transmit an amount of data in blocking mode.
836 * @param hqspi QSPI handle
837 * @param pData pointer to data buffer
838 * @param Timeout Time out duration
839 * @note This function is used only in Indirect Write Mode
840 * @retval HAL status
841 */
842 HAL_StatusTypeDef HAL_QSPI_Transmit(QSPI_HandleTypeDef *hqspi, uint8_t *pData, uint32_t Timeout)
843 {
844 HAL_StatusTypeDef status = HAL_OK;
845 uint32_t tickstart = HAL_GetTick();
846 __IO uint32_t *data_reg = &hqspi->Instance->DR;
847
848 /* Process locked */
849 __HAL_LOCK(hqspi);
850
851 if(hqspi->State == HAL_QSPI_STATE_READY)
852 {
853 hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
854
855 if(pData != NULL )
856 {
857 /* Update state */
858 hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_TX;
859
860 /* Configure counters and size of the handle */
861 hqspi->TxXferCount = READ_REG(hqspi->Instance->DLR) + 1U;
862 hqspi->TxXferSize = READ_REG(hqspi->Instance->DLR) + 1U;
863 hqspi->pTxBuffPtr = pData;
864
865 /* Configure QSPI: CCR register with functional as indirect write */
866 MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE);
867
868 while(hqspi->TxXferCount > 0U)
869 {
870 /* Wait until FT flag is set to send data */
871 status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_FT, SET, tickstart, Timeout);
872
873 if (status != HAL_OK)
874 {
875 break;
876 }
877
878 *(__IO uint8_t *)data_reg = *hqspi->pTxBuffPtr++;
879 hqspi->TxXferCount--;
880 }
881
882 if (status == HAL_OK)
883 {
884 /* Wait until TC flag is set to go back in idle state */
885 status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_TC, SET, tickstart, Timeout);
886
887 if (status == HAL_OK)
888 {
889 /* Clear Transfer Complete bit */
890 __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);
891
892 /* Clear Busy bit */
893 status = HAL_QSPI_Abort(hqspi);
894 }
895 }
896
897 /* Update QSPI state */
898 hqspi->State = HAL_QSPI_STATE_READY;
899 }
900 else
901 {
902 hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM;
903 status = HAL_ERROR;
904 }
905 }
906 else
907 {
908 status = HAL_BUSY;
909 }
910
911 /* Process unlocked */
912 __HAL_UNLOCK(hqspi);
913
914 return status;
915 }
916
917
918 /**
919 * @brief Receive an amount of data in blocking mode
920 * @param hqspi QSPI handle
921 * @param pData pointer to data buffer
922 * @param Timeout Time out duration
923 * @note This function is used only in Indirect Read Mode
924 * @retval HAL status
925 */
926 HAL_StatusTypeDef HAL_QSPI_Receive(QSPI_HandleTypeDef *hqspi, uint8_t *pData, uint32_t Timeout)
927 {
928 HAL_StatusTypeDef status = HAL_OK;
929 uint32_t tickstart = HAL_GetTick();
930 uint32_t addr_reg = READ_REG(hqspi->Instance->AR);
931 __IO uint32_t *data_reg = &hqspi->Instance->DR;
932
933 /* Process locked */
934 __HAL_LOCK(hqspi);
935
936 if(hqspi->State == HAL_QSPI_STATE_READY)
937 {
938 hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
939 if(pData != NULL )
940 {
941 /* Update state */
942 hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_RX;
943
944 /* Configure counters and size of the handle */
945 hqspi->RxXferCount = READ_REG(hqspi->Instance->DLR) + 1U;
946 hqspi->RxXferSize = READ_REG(hqspi->Instance->DLR) + 1U;
947 hqspi->pRxBuffPtr = pData;
948
949 /* Configure QSPI: CCR register with functional as indirect read */
950 MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_READ);
951
952 /* Start the transfer by re-writing the address in AR register */
953 WRITE_REG(hqspi->Instance->AR, addr_reg);
954
955 while(hqspi->RxXferCount > 0U)
956 {
957 /* Wait until FT or TC flag is set to read received data */
958 status = QSPI_WaitFlagStateUntilTimeout(hqspi, (QSPI_FLAG_FT | QSPI_FLAG_TC), SET, tickstart, Timeout);
959
960 if (status != HAL_OK)
961 {
962 break;
963 }
964
965 *hqspi->pRxBuffPtr++ = *(__IO uint8_t *)data_reg;
966 hqspi->RxXferCount--;
967 }
968
969 if (status == HAL_OK)
970 {
971 /* Wait until TC flag is set to go back in idle state */
972 status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_TC, SET, tickstart, Timeout);
973
974 if (status == HAL_OK)
975 {
976 /* Clear Transfer Complete bit */
977 __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);
978
979 /* Workaround - Extra data written in the FIFO at the end of a read transfer */
980 status = HAL_QSPI_Abort(hqspi);
981 }
982 }
983
984 /* Update QSPI state */
985 hqspi->State = HAL_QSPI_STATE_READY;
986 }
987 else
988 {
989 hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM;
990 status = HAL_ERROR;
991 }
992 }
993 else
994 {
995 status = HAL_BUSY;
996 }
997
998 /* Process unlocked */
999 __HAL_UNLOCK(hqspi);
1000
1001 return status;
1002 }
1003
1004 /**
1005 * @brief Send an amount of data in interrupt mode
1006 * @param hqspi QSPI handle
1007 * @param pData pointer to data buffer
1008 * @note This function is used only in Indirect Write Mode
1009 * @retval HAL status
1010 */
1011 HAL_StatusTypeDef HAL_QSPI_Transmit_IT(QSPI_HandleTypeDef *hqspi, uint8_t *pData)
1012 {
1013 HAL_StatusTypeDef status = HAL_OK;
1014
1015 /* Process locked */
1016 __HAL_LOCK(hqspi);
1017
1018 if(hqspi->State == HAL_QSPI_STATE_READY)
1019 {
1020 hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
1021 if(pData != NULL )
1022 {
1023 /* Update state */
1024 hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_TX;
1025
1026 /* Configure counters and size of the handle */
1027 hqspi->TxXferCount = READ_REG(hqspi->Instance->DLR) + 1U;
1028 hqspi->TxXferSize = READ_REG(hqspi->Instance->DLR) + 1U;
1029 hqspi->pTxBuffPtr = pData;
1030
1031 /* Configure QSPI: CCR register with functional as indirect write */
1032 MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE);
1033
1034 /* Clear interrupt */
1035 __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TE | QSPI_FLAG_TC);
1036
1037 /* Process unlocked */
1038 __HAL_UNLOCK(hqspi);
1039
1040 /* Enable the QSPI transfer error, FIFO threshold and transfer complete Interrupts */
1041 __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE | QSPI_IT_FT | QSPI_IT_TC);
1042
1043 }
1044 else
1045 {
1046 hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM;
1047 status = HAL_ERROR;
1048
1049 /* Process unlocked */
1050 __HAL_UNLOCK(hqspi);
1051 }
1052 }
1053 else
1054 {
1055 status = HAL_BUSY;
1056
1057 /* Process unlocked */
1058 __HAL_UNLOCK(hqspi);
1059 }
1060
1061 return status;
1062 }
1063
1064 /**
1065 * @brief Receive an amount of data in no-blocking mode with Interrupt
1066 * @param hqspi QSPI handle
1067 * @param pData pointer to data buffer
1068 * @note This function is used only in Indirect Read Mode
1069 * @retval HAL status
1070 */
1071 HAL_StatusTypeDef HAL_QSPI_Receive_IT(QSPI_HandleTypeDef *hqspi, uint8_t *pData)
1072 {
1073 HAL_StatusTypeDef status = HAL_OK;
1074 uint32_t addr_reg = READ_REG(hqspi->Instance->AR);
1075
1076 /* Process locked */
1077 __HAL_LOCK(hqspi);
1078
1079 if(hqspi->State == HAL_QSPI_STATE_READY)
1080 {
1081 hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
1082
1083 if(pData != NULL )
1084 {
1085 /* Update state */
1086 hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_RX;
1087
1088 /* Configure counters and size of the handle */
1089 hqspi->RxXferCount = READ_REG(hqspi->Instance->DLR) + 1U;
1090 hqspi->RxXferSize = READ_REG(hqspi->Instance->DLR) + 1U;
1091 hqspi->pRxBuffPtr = pData;
1092
1093 /* Configure QSPI: CCR register with functional as indirect read */
1094 MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_READ);
1095
1096 /* Start the transfer by re-writing the address in AR register */
1097 WRITE_REG(hqspi->Instance->AR, addr_reg);
1098
1099 /* Clear interrupt */
1100 __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TE | QSPI_FLAG_TC);
1101
1102 /* Process unlocked */
1103 __HAL_UNLOCK(hqspi);
1104
1105 /* Enable the QSPI transfer error, FIFO threshold and transfer complete Interrupts */
1106 __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE | QSPI_IT_FT | QSPI_IT_TC);
1107 }
1108 else
1109 {
1110 hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM;
1111 status = HAL_ERROR;
1112
1113 /* Process unlocked */
1114 __HAL_UNLOCK(hqspi);
1115 }
1116 }
1117 else
1118 {
1119 status = HAL_BUSY;
1120
1121 /* Process unlocked */
1122 __HAL_UNLOCK(hqspi);
1123 }
1124
1125 return status;
1126 }
1127
1128 /**
1129 * @brief Sends an amount of data in non blocking mode with DMA.
1130 * @param hqspi QSPI handle
1131 * @param pData pointer to data buffer
1132 * @note This function is used only in Indirect Write Mode
1133 * @note If DMA peripheral access is configured as halfword, the number
1134 * of data and the fifo threshold should be aligned on halfword
1135 * @note If DMA peripheral access is configured as word, the number
1136 * of data and the fifo threshold should be aligned on word
1137 * @retval HAL status
1138 */
1139 HAL_StatusTypeDef HAL_QSPI_Transmit_DMA(QSPI_HandleTypeDef *hqspi, uint8_t *pData)
1140 {
1141 HAL_StatusTypeDef status = HAL_OK;
1142 uint32_t *tmp;
1143 uint32_t data_size = (READ_REG(hqspi->Instance->DLR) + 1U);
1144
1145 /* Process locked */
1146 __HAL_LOCK(hqspi);
1147
1148 if(hqspi->State == HAL_QSPI_STATE_READY)
1149 {
1150 /* Clear the error code */
1151 hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
1152
1153 if(pData != NULL )
1154 {
1155 /* Configure counters of the handle */
1156 if (hqspi->hdma->Init.PeriphDataAlignment == DMA_PDATAALIGN_BYTE)
1157 {
1158 hqspi->TxXferCount = data_size;
1159 }
1160 else if (hqspi->hdma->Init.PeriphDataAlignment == DMA_PDATAALIGN_HALFWORD)
1161 {
1162 if (((data_size % 2U) != 0U) || ((hqspi->Init.FifoThreshold % 2U) != 0U))
1163 {
1164 /* The number of data or the fifo threshold is not aligned on halfword
1165 => no transfer possible with DMA peripheral access configured as halfword */
1166 hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM;
1167 status = HAL_ERROR;
1168
1169 /* Process unlocked */
1170 __HAL_UNLOCK(hqspi);
1171 }
1172 else
1173 {
1174 hqspi->TxXferCount = (data_size >> 1);
1175 }
1176 }
1177 else if (hqspi->hdma->Init.PeriphDataAlignment == DMA_PDATAALIGN_WORD)
1178 {
1179 if (((data_size % 4U) != 0U) || ((hqspi->Init.FifoThreshold % 4U) != 0U))
1180 {
1181 /* The number of data or the fifo threshold is not aligned on word
1182 => no transfer possible with DMA peripheral access configured as word */
1183 hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM;
1184 status = HAL_ERROR;
1185
1186 /* Process unlocked */
1187 __HAL_UNLOCK(hqspi);
1188 }
1189 else
1190 {
1191 hqspi->TxXferCount = (data_size >> 2U);
1192 }
1193 }
1194
1195 if (status == HAL_OK)
1196 {
1197 /* Update state */
1198 hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_TX;
1199
1200 /* Clear interrupt */
1201 __HAL_QSPI_CLEAR_FLAG(hqspi, (QSPI_FLAG_TE | QSPI_FLAG_TC));
1202
1203 /* Configure size and pointer of the handle */
1204 hqspi->TxXferSize = hqspi->TxXferCount;
1205 hqspi->pTxBuffPtr = pData;
1206
1207 /* Configure QSPI: CCR register with functional mode as indirect write */
1208 MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE);
1209
1210 /* Set the QSPI DMA transfer complete callback */
1211 hqspi->hdma->XferCpltCallback = QSPI_DMATxCplt;
1212
1213 /* Set the QSPI DMA Half transfer complete callback */
1214 hqspi->hdma->XferHalfCpltCallback = QSPI_DMATxHalfCplt;
1215
1216 /* Set the DMA error callback */
1217 hqspi->hdma->XferErrorCallback = QSPI_DMAError;
1218
1219 /* Clear the DMA abort callback */
1220 hqspi->hdma->XferAbortCallback = NULL;
1221
1222 #if defined (QSPI1_V2_1L)
1223 /* Bug "ES0305 section 2.1.8 In some specific cases, DMA2 data corruption occurs when managing
1224 AHB and APB2 peripherals in a concurrent way" Workaround Implementation:
1225 Change the following configuration of DMA peripheral
1226 - Enable peripheral increment
1227 - Disable memory increment
1228 - Set DMA direction as peripheral to memory mode */
1229
1230 /* Enable peripheral increment mode of the DMA */
1231 hqspi->hdma->Init.PeriphInc = DMA_PINC_ENABLE;
1232
1233 /* Disable memory increment mode of the DMA */
1234 hqspi->hdma->Init.MemInc = DMA_MINC_DISABLE;
1235
1236 /* Update peripheral/memory increment mode bits */
1237 MODIFY_REG(hqspi->hdma->Instance->CR, (DMA_SxCR_MINC | DMA_SxCR_PINC), (hqspi->hdma->Init.MemInc | hqspi->hdma->Init.PeriphInc));
1238
1239 /* Configure the direction of the DMA */
1240 hqspi->hdma->Init.Direction = DMA_PERIPH_TO_MEMORY;
1241 #else
1242 /* Configure the direction of the DMA */
1243 hqspi->hdma->Init.Direction = DMA_MEMORY_TO_PERIPH;
1244 #endif /* QSPI1_V2_1L */
1245
1246 /* Update direction mode bit */
1247 MODIFY_REG(hqspi->hdma->Instance->CR, DMA_SxCR_DIR, hqspi->hdma->Init.Direction);
1248
1249 /* Enable the QSPI transmit DMA Channel */
1250 tmp = (uint32_t*)&pData;
1251 HAL_DMA_Start_IT(hqspi->hdma, *(uint32_t*)tmp, (uint32_t)&hqspi->Instance->DR, hqspi->TxXferSize);
1252
1253 /* Process unlocked */
1254 __HAL_UNLOCK(hqspi);
1255
1256 /* Enable the QSPI transfer error Interrupt */
1257 __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE);
1258
1259 /* Enable the DMA transfer by setting the DMAEN bit in the QSPI CR register */
1260 SET_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
1261 }
1262 }
1263 else
1264 {
1265 hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM;
1266
1267 status = HAL_ERROR;
1268
1269 /* Process unlocked */
1270 __HAL_UNLOCK(hqspi);
1271 }
1272 }
1273 else
1274 {
1275 status = HAL_BUSY;
1276
1277 /* Process unlocked */
1278 __HAL_UNLOCK(hqspi);
1279 }
1280
1281 return status;
1282 }
1283
1284 /**
1285 * @brief Receives an amount of data in non blocking mode with DMA.
1286 * @param hqspi QSPI handle
1287 * @param pData pointer to data buffer.
1288 * @note This function is used only in Indirect Read Mode
1289 * @note If DMA peripheral access is configured as halfword, the number
1290 * of data and the fifo threshold should be aligned on halfword
1291 * @note If DMA peripheral access is configured as word, the number
1292 * of data and the fifo threshold should be aligned on word
1293 * @retval HAL status
1294 */
1295 HAL_StatusTypeDef HAL_QSPI_Receive_DMA(QSPI_HandleTypeDef *hqspi, uint8_t *pData)
1296 {
1297 HAL_StatusTypeDef status = HAL_OK;
1298 uint32_t *tmp;
1299 uint32_t addr_reg = READ_REG(hqspi->Instance->AR);
1300 uint32_t data_size = (READ_REG(hqspi->Instance->DLR) + 1U);
1301
1302 /* Process locked */
1303 __HAL_LOCK(hqspi);
1304
1305 if(hqspi->State == HAL_QSPI_STATE_READY)
1306 {
1307 hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
1308
1309 if(pData != NULL )
1310 {
1311 /* Configure counters of the handle */
1312 if (hqspi->hdma->Init.PeriphDataAlignment == DMA_PDATAALIGN_BYTE)
1313 {
1314 hqspi->RxXferCount = data_size;
1315 }
1316 else if (hqspi->hdma->Init.PeriphDataAlignment == DMA_PDATAALIGN_HALFWORD)
1317 {
1318 if (((data_size % 2U) != 0U) || ((hqspi->Init.FifoThreshold % 2U) != 0U))
1319 {
1320 /* The number of data or the fifo threshold is not aligned on halfword
1321 => no transfer possible with DMA peripheral access configured as halfword */
1322 hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM;
1323 status = HAL_ERROR;
1324
1325 /* Process unlocked */
1326 __HAL_UNLOCK(hqspi);
1327 }
1328 else
1329 {
1330 hqspi->RxXferCount = (data_size >> 1U);
1331 }
1332 }
1333 else if (hqspi->hdma->Init.PeriphDataAlignment == DMA_PDATAALIGN_WORD)
1334 {
1335 if (((data_size % 4U) != 0U) || ((hqspi->Init.FifoThreshold % 4U) != 0U))
1336 {
1337 /* The number of data or the fifo threshold is not aligned on word
1338 => no transfer possible with DMA peripheral access configured as word */
1339 hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM;
1340 status = HAL_ERROR;
1341
1342 /* Process unlocked */
1343 __HAL_UNLOCK(hqspi);
1344 }
1345 else
1346 {
1347 hqspi->RxXferCount = (data_size >> 2U);
1348 }
1349 }
1350
1351 if (status == HAL_OK)
1352 {
1353 /* Update state */
1354 hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_RX;
1355
1356 /* Clear interrupt */
1357 __HAL_QSPI_CLEAR_FLAG(hqspi, (QSPI_FLAG_TE | QSPI_FLAG_TC));
1358
1359 /* Configure size and pointer of the handle */
1360 hqspi->RxXferSize = hqspi->RxXferCount;
1361 hqspi->pRxBuffPtr = pData;
1362
1363 /* Set the QSPI DMA transfer complete callback */
1364 hqspi->hdma->XferCpltCallback = QSPI_DMARxCplt;
1365
1366 /* Set the QSPI DMA Half transfer complete callback */
1367 hqspi->hdma->XferHalfCpltCallback = QSPI_DMARxHalfCplt;
1368
1369 /* Set the DMA error callback */
1370 hqspi->hdma->XferErrorCallback = QSPI_DMAError;
1371
1372 /* Clear the DMA abort callback */
1373 hqspi->hdma->XferAbortCallback = NULL;
1374
1375 #if defined (QSPI1_V2_1L)
1376 /* Bug "ES0305 section 2.1.8 In some specific cases, DMA2 data corruption occurs when managing
1377 AHB and APB2 peripherals in a concurrent way" Workaround Implementation:
1378 Change the following configuration of DMA peripheral
1379 - Enable peripheral increment
1380 - Disable memory increment
1381 - Set DMA direction as memory to peripheral mode
1382 - 4 Extra words (32-bits) are added for read operation to guarantee
1383 the last data is transferred from DMA FIFO to RAM memory */
1384
1385 /* Enable peripheral increment of the DMA */
1386 hqspi->hdma->Init.PeriphInc = DMA_PINC_ENABLE;
1387
1388 /* Disable memory increment of the DMA */
1389 hqspi->hdma->Init.MemInc = DMA_MINC_DISABLE;
1390
1391 /* Update peripheral/memory increment mode bits */
1392 MODIFY_REG(hqspi->hdma->Instance->CR, (DMA_SxCR_MINC | DMA_SxCR_PINC), (hqspi->hdma->Init.MemInc | hqspi->hdma->Init.PeriphInc));
1393
1394 /* Configure the direction of the DMA */
1395 hqspi->hdma->Init.Direction = DMA_MEMORY_TO_PERIPH;
1396
1397 /* 4 Extra words (32-bits) are needed for read operation to guarantee
1398 the last data is transferred from DMA FIFO to RAM memory */
1399 WRITE_REG(hqspi->Instance->DLR, (data_size - 1U + 16U));
1400
1401 /* Update direction mode bit */
1402 MODIFY_REG(hqspi->hdma->Instance->CR, DMA_SxCR_DIR, hqspi->hdma->Init.Direction);
1403
1404 /* Configure QSPI: CCR register with functional as indirect read */
1405 MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_READ);
1406
1407 /* Start the transfer by re-writing the address in AR register */
1408 WRITE_REG(hqspi->Instance->AR, addr_reg);
1409
1410 /* Enable the DMA Channel */
1411 tmp = (uint32_t*)&pData;
1412 HAL_DMA_Start_IT(hqspi->hdma, (uint32_t)&hqspi->Instance->DR, *(uint32_t*)tmp, hqspi->RxXferSize);
1413
1414 /* Enable the DMA transfer by setting the DMAEN bit in the QSPI CR register */
1415 SET_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
1416
1417 /* Process unlocked */
1418 __HAL_UNLOCK(hqspi);
1419
1420 /* Enable the QSPI transfer error Interrupt */
1421 __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE);
1422 #else
1423 /* Configure the direction of the DMA */
1424 hqspi->hdma->Init.Direction = DMA_PERIPH_TO_MEMORY;
1425
1426 MODIFY_REG(hqspi->hdma->Instance->CR, DMA_SxCR_DIR, hqspi->hdma->Init.Direction);
1427
1428 /* Enable the DMA Channel */
1429 tmp = (uint32_t*)&pData;
1430 HAL_DMA_Start_IT(hqspi->hdma, (uint32_t)&hqspi->Instance->DR, *(uint32_t*)tmp, hqspi->RxXferSize);
1431
1432 /* Configure QSPI: CCR register with functional as indirect read */
1433 MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_READ);
1434
1435 /* Start the transfer by re-writing the address in AR register */
1436 WRITE_REG(hqspi->Instance->AR, addr_reg);
1437
1438 /* Process unlocked */
1439 __HAL_UNLOCK(hqspi);
1440
1441 /* Enable the QSPI transfer error Interrupt */
1442 __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE);
1443
1444 /* Enable the DMA transfer by setting the DMAEN bit in the QSPI CR register */
1445 SET_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
1446 #endif /* QSPI1_V2_1L */
1447 }
1448 }
1449 else
1450 {
1451 hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM;
1452 status = HAL_ERROR;
1453
1454 /* Process unlocked */
1455 __HAL_UNLOCK(hqspi);
1456 }
1457 }
1458 else
1459 {
1460 status = HAL_BUSY;
1461
1462 /* Process unlocked */
1463 __HAL_UNLOCK(hqspi);
1464 }
1465
1466 return status;
1467 }
1468
1469 /**
1470 * @brief Configure the QSPI Automatic Polling Mode in blocking mode.
1471 * @param hqspi QSPI handle
1472 * @param cmd structure that contains the command configuration information.
1473 * @param cfg structure that contains the polling configuration information.
1474 * @param Timeout Time out duration
1475 * @note This function is used only in Automatic Polling Mode
1476 * @retval HAL status
1477 */
1478 HAL_StatusTypeDef HAL_QSPI_AutoPolling(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_AutoPollingTypeDef *cfg, uint32_t Timeout)
1479 {
1480 HAL_StatusTypeDef status = HAL_ERROR;
1481 uint32_t tickstart = HAL_GetTick();
1482
1483 /* Check the parameters */
1484 assert_param(IS_QSPI_INSTRUCTION_MODE(cmd->InstructionMode));
1485 if (cmd->InstructionMode != QSPI_INSTRUCTION_NONE)
1486 {
1487 assert_param(IS_QSPI_INSTRUCTION(cmd->Instruction));
1488 }
1489
1490 assert_param(IS_QSPI_ADDRESS_MODE(cmd->AddressMode));
1491 if (cmd->AddressMode != QSPI_ADDRESS_NONE)
1492 {
1493 assert_param(IS_QSPI_ADDRESS_SIZE(cmd->AddressSize));
1494 }
1495
1496 assert_param(IS_QSPI_ALTERNATE_BYTES_MODE(cmd->AlternateByteMode));
1497 if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE)
1498 {
1499 assert_param(IS_QSPI_ALTERNATE_BYTES_SIZE(cmd->AlternateBytesSize));
1500 }
1501
1502 assert_param(IS_QSPI_DUMMY_CYCLES(cmd->DummyCycles));
1503 assert_param(IS_QSPI_DATA_MODE(cmd->DataMode));
1504
1505 assert_param(IS_QSPI_DDR_MODE(cmd->DdrMode));
1506 assert_param(IS_QSPI_DDR_HHC(cmd->DdrHoldHalfCycle));
1507 assert_param(IS_QSPI_SIOO_MODE(cmd->SIOOMode));
1508
1509 assert_param(IS_QSPI_INTERVAL(cfg->Interval));
1510 assert_param(IS_QSPI_STATUS_BYTES_SIZE(cfg->StatusBytesSize));
1511 assert_param(IS_QSPI_MATCH_MODE(cfg->MatchMode));
1512
1513 /* Process locked */
1514 __HAL_LOCK(hqspi);
1515
1516 if(hqspi->State == HAL_QSPI_STATE_READY)
1517 {
1518
1519 hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
1520
1521 /* Update state */
1522 hqspi->State = HAL_QSPI_STATE_BUSY_AUTO_POLLING;
1523
1524 /* Wait till BUSY flag reset */
1525 status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, tickstart, Timeout);
1526
1527 if (status == HAL_OK)
1528 {
1529 /* Configure QSPI: PSMAR register with the status match value */
1530 WRITE_REG(hqspi->Instance->PSMAR, cfg->Match);
1531
1532 /* Configure QSPI: PSMKR register with the status mask value */
1533 WRITE_REG(hqspi->Instance->PSMKR, cfg->Mask);
1534
1535 /* Configure QSPI: PIR register with the interval value */
1536 WRITE_REG(hqspi->Instance->PIR, cfg->Interval);
1537
1538 /* Configure QSPI: CR register with Match mode and Automatic stop enabled
1539 (otherwise there will be an infinite loop in blocking mode) */
1540 MODIFY_REG(hqspi->Instance->CR, (QUADSPI_CR_PMM | QUADSPI_CR_APMS),
1541 (cfg->MatchMode | QSPI_AUTOMATIC_STOP_ENABLE));
1542
1543 /* Call the configuration function */
1544 cmd->NbData = cfg->StatusBytesSize;
1545 QSPI_Config(hqspi, cmd, QSPI_FUNCTIONAL_MODE_AUTO_POLLING);
1546
1547 /* Wait until SM flag is set to go back in idle state */
1548 status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_SM, SET, tickstart, Timeout);
1549
1550 if (status == HAL_OK)
1551 {
1552 __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_SM);
1553
1554 /* Update state */
1555 hqspi->State = HAL_QSPI_STATE_READY;
1556 }
1557 }
1558 }
1559 else
1560 {
1561 status = HAL_BUSY;
1562 }
1563 /* Process unlocked */
1564 __HAL_UNLOCK(hqspi);
1565
1566 /* Return function status */
1567 return status;
1568 }
1569
1570 /**
1571 * @brief Configure the QSPI Automatic Polling Mode in non-blocking mode.
1572 * @param hqspi QSPI handle
1573 * @param cmd structure that contains the command configuration information.
1574 * @param cfg structure that contains the polling configuration information.
1575 * @note This function is used only in Automatic Polling Mode
1576 * @retval HAL status
1577 */
1578 HAL_StatusTypeDef HAL_QSPI_AutoPolling_IT(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_AutoPollingTypeDef *cfg)
1579 {
1580 __IO uint32_t count = 0U;
1581 HAL_StatusTypeDef status = HAL_OK;
1582
1583 /* Check the parameters */
1584 assert_param(IS_QSPI_INSTRUCTION_MODE(cmd->InstructionMode));
1585 if (cmd->InstructionMode != QSPI_INSTRUCTION_NONE)
1586 {
1587 assert_param(IS_QSPI_INSTRUCTION(cmd->Instruction));
1588 }
1589
1590 assert_param(IS_QSPI_ADDRESS_MODE(cmd->AddressMode));
1591 if (cmd->AddressMode != QSPI_ADDRESS_NONE)
1592 {
1593 assert_param(IS_QSPI_ADDRESS_SIZE(cmd->AddressSize));
1594 }
1595
1596 assert_param(IS_QSPI_ALTERNATE_BYTES_MODE(cmd->AlternateByteMode));
1597 if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE)
1598 {
1599 assert_param(IS_QSPI_ALTERNATE_BYTES_SIZE(cmd->AlternateBytesSize));
1600 }
1601
1602 assert_param(IS_QSPI_DUMMY_CYCLES(cmd->DummyCycles));
1603 assert_param(IS_QSPI_DATA_MODE(cmd->DataMode));
1604
1605 assert_param(IS_QSPI_DDR_MODE(cmd->DdrMode));
1606 assert_param(IS_QSPI_DDR_HHC(cmd->DdrHoldHalfCycle));
1607 assert_param(IS_QSPI_SIOO_MODE(cmd->SIOOMode));
1608
1609 assert_param(IS_QSPI_INTERVAL(cfg->Interval));
1610 assert_param(IS_QSPI_STATUS_BYTES_SIZE(cfg->StatusBytesSize));
1611 assert_param(IS_QSPI_MATCH_MODE(cfg->MatchMode));
1612 assert_param(IS_QSPI_AUTOMATIC_STOP(cfg->AutomaticStop));
1613
1614 /* Process locked */
1615 __HAL_LOCK(hqspi);
1616
1617 if(hqspi->State == HAL_QSPI_STATE_READY)
1618 {
1619 hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
1620
1621 /* Update state */
1622 hqspi->State = HAL_QSPI_STATE_BUSY_AUTO_POLLING;
1623
1624 /* Wait till BUSY flag reset */
1625 count = (hqspi->Timeout) * (SystemCoreClock / 16U / 1000U);
1626 do
1627 {
1628 if (count-- == 0U)
1629 {
1630 hqspi->State = HAL_QSPI_STATE_ERROR;
1631 hqspi->ErrorCode |= HAL_QSPI_ERROR_TIMEOUT;
1632 status = HAL_TIMEOUT;
1633 }
1634 }
1635 while ((__HAL_QSPI_GET_FLAG(hqspi, QSPI_FLAG_BUSY)) != RESET);
1636
1637 if (status == HAL_OK)
1638 {
1639 /* Configure QSPI: PSMAR register with the status match value */
1640 WRITE_REG(hqspi->Instance->PSMAR, cfg->Match);
1641
1642 /* Configure QSPI: PSMKR register with the status mask value */
1643 WRITE_REG(hqspi->Instance->PSMKR, cfg->Mask);
1644
1645 /* Configure QSPI: PIR register with the interval value */
1646 WRITE_REG(hqspi->Instance->PIR, cfg->Interval);
1647
1648 /* Configure QSPI: CR register with Match mode and Automatic stop mode */
1649 MODIFY_REG(hqspi->Instance->CR, (QUADSPI_CR_PMM | QUADSPI_CR_APMS),
1650 (cfg->MatchMode | cfg->AutomaticStop));
1651
1652 /* Clear interrupt */
1653 __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TE | QSPI_FLAG_SM);
1654
1655 /* Call the configuration function */
1656 cmd->NbData = cfg->StatusBytesSize;
1657 QSPI_Config(hqspi, cmd, QSPI_FUNCTIONAL_MODE_AUTO_POLLING);
1658
1659 /* Process unlocked */
1660 __HAL_UNLOCK(hqspi);
1661
1662 /* Enable the QSPI Transfer Error and status match Interrupt */
1663 __HAL_QSPI_ENABLE_IT(hqspi, (QSPI_IT_SM | QSPI_IT_TE));
1664
1665 }
1666 else
1667 {
1668 /* Process unlocked */
1669 __HAL_UNLOCK(hqspi);
1670 }
1671 }
1672 else
1673 {
1674 status = HAL_BUSY;
1675
1676 /* Process unlocked */
1677 __HAL_UNLOCK(hqspi);
1678 }
1679
1680 /* Return function status */
1681 return status;
1682 }
1683
1684 /**
1685 * @brief Configure the Memory Mapped mode.
1686 * @param hqspi QSPI handle
1687 * @param cmd structure that contains the command configuration information.
1688 * @param cfg structure that contains the memory mapped configuration information.
1689 * @note This function is used only in Memory mapped Mode
1690 * @retval HAL status
1691 */
1692 HAL_StatusTypeDef HAL_QSPI_MemoryMapped(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_MemoryMappedTypeDef *cfg)
1693 {
1694 HAL_StatusTypeDef status = HAL_ERROR;
1695 uint32_t tickstart = HAL_GetTick();
1696
1697 /* Check the parameters */
1698 assert_param(IS_QSPI_INSTRUCTION_MODE(cmd->InstructionMode));
1699 if (cmd->InstructionMode != QSPI_INSTRUCTION_NONE)
1700 {
1701 assert_param(IS_QSPI_INSTRUCTION(cmd->Instruction));
1702 }
1703
1704 assert_param(IS_QSPI_ADDRESS_MODE(cmd->AddressMode));
1705 if (cmd->AddressMode != QSPI_ADDRESS_NONE)
1706 {
1707 assert_param(IS_QSPI_ADDRESS_SIZE(cmd->AddressSize));
1708 }
1709
1710 assert_param(IS_QSPI_ALTERNATE_BYTES_MODE(cmd->AlternateByteMode));
1711 if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE)
1712 {
1713 assert_param(IS_QSPI_ALTERNATE_BYTES_SIZE(cmd->AlternateBytesSize));
1714 }
1715
1716 assert_param(IS_QSPI_DUMMY_CYCLES(cmd->DummyCycles));
1717 assert_param(IS_QSPI_DATA_MODE(cmd->DataMode));
1718
1719 assert_param(IS_QSPI_DDR_MODE(cmd->DdrMode));
1720 assert_param(IS_QSPI_DDR_HHC(cmd->DdrHoldHalfCycle));
1721 assert_param(IS_QSPI_SIOO_MODE(cmd->SIOOMode));
1722
1723 assert_param(IS_QSPI_TIMEOUT_ACTIVATION(cfg->TimeOutActivation));
1724
1725 /* Process locked */
1726 __HAL_LOCK(hqspi);
1727
1728 if(hqspi->State == HAL_QSPI_STATE_READY)
1729 {
1730 hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
1731
1732 /* Update state */
1733 hqspi->State = HAL_QSPI_STATE_BUSY_MEM_MAPPED;
1734
1735 /* Wait till BUSY flag reset */
1736 status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, tickstart, hqspi->Timeout);
1737
1738 if (status == HAL_OK)
1739 {
1740 /* Configure QSPI: CR register with timeout counter enable */
1741 MODIFY_REG(hqspi->Instance->CR, QUADSPI_CR_TCEN, cfg->TimeOutActivation);
1742
1743 if (cfg->TimeOutActivation == QSPI_TIMEOUT_COUNTER_ENABLE)
1744 {
1745 assert_param(IS_QSPI_TIMEOUT_PERIOD(cfg->TimeOutPeriod));
1746
1747 /* Configure QSPI: LPTR register with the low-power timeout value */
1748 WRITE_REG(hqspi->Instance->LPTR, cfg->TimeOutPeriod);
1749
1750 /* Clear interrupt */
1751 __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TO);
1752
1753 /* Enable the QSPI TimeOut Interrupt */
1754 __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TO);
1755 }
1756
1757 /* Call the configuration function */
1758 QSPI_Config(hqspi, cmd, QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED);
1759 }
1760 }
1761 else
1762 {
1763 status = HAL_BUSY;
1764 }
1765
1766 /* Process unlocked */
1767 __HAL_UNLOCK(hqspi);
1768
1769 /* Return function status */
1770 return status;
1771 }
1772
1773 /**
1774 * @brief Transfer Error callbacks
1775 * @param hqspi QSPI handle
1776 * @retval None
1777 */
1778 __weak void HAL_QSPI_ErrorCallback(QSPI_HandleTypeDef *hqspi)
1779 {
1780 /* Prevent unused argument(s) compilation warning */
1781 UNUSED(hqspi);
1782
1783 /* NOTE : This function Should not be modified, when the callback is needed,
1784 the HAL_QSPI_ErrorCallback could be implemented in the user file
1785 */
1786 }
1787
1788 /**
1789 * @brief Abort completed callback.
1790 * @param hqspi QSPI handle
1791 * @retval None
1792 */
1793 __weak void HAL_QSPI_AbortCpltCallback(QSPI_HandleTypeDef *hqspi)
1794 {
1795 /* Prevent unused argument(s) compilation warning */
1796 UNUSED(hqspi);
1797
1798 /* NOTE: This function should not be modified, when the callback is needed,
1799 the HAL_QSPI_AbortCpltCallback could be implemented in the user file
1800 */
1801 }
1802
1803 /**
1804 * @brief Command completed callback.
1805 * @param hqspi QSPI handle
1806 * @retval None
1807 */
1808 __weak void HAL_QSPI_CmdCpltCallback(QSPI_HandleTypeDef *hqspi)
1809 {
1810 /* Prevent unused argument(s) compilation warning */
1811 UNUSED(hqspi);
1812
1813 /* NOTE: This function Should not be modified, when the callback is needed,
1814 the HAL_QSPI_CmdCpltCallback could be implemented in the user file
1815 */
1816 }
1817
1818 /**
1819 * @brief Rx Transfer completed callbacks.
1820 * @param hqspi QSPI handle
1821 * @retval None
1822 */
1823 __weak void HAL_QSPI_RxCpltCallback(QSPI_HandleTypeDef *hqspi)
1824 {
1825 /* Prevent unused argument(s) compilation warning */
1826 UNUSED(hqspi);
1827
1828 /* NOTE: This function Should not be modified, when the callback is needed,
1829 the HAL_QSPI_RxCpltCallback could be implemented in the user file
1830 */
1831 }
1832
1833 /**
1834 * @brief Tx Transfer completed callbacks.
1835 * @param hqspi QSPI handle
1836 * @retval None
1837 */
1838 __weak void HAL_QSPI_TxCpltCallback(QSPI_HandleTypeDef *hqspi)
1839 {
1840 /* Prevent unused argument(s) compilation warning */
1841 UNUSED(hqspi);
1842
1843 /* NOTE: This function Should not be modified, when the callback is needed,
1844 the HAL_QSPI_TxCpltCallback could be implemented in the user file
1845 */
1846 }
1847
1848 /**
1849 * @brief Rx Half Transfer completed callbacks.
1850 * @param hqspi QSPI handle
1851 * @retval None
1852 */
1853 __weak void HAL_QSPI_RxHalfCpltCallback(QSPI_HandleTypeDef *hqspi)
1854 {
1855 /* Prevent unused argument(s) compilation warning */
1856 UNUSED(hqspi);
1857
1858 /* NOTE: This function Should not be modified, when the callback is needed,
1859 the HAL_QSPI_RxHalfCpltCallback could be implemented in the user file
1860 */
1861 }
1862
1863 /**
1864 * @brief Tx Half Transfer completed callbacks.
1865 * @param hqspi QSPI handle
1866 * @retval None
1867 */
1868 __weak void HAL_QSPI_TxHalfCpltCallback(QSPI_HandleTypeDef *hqspi)
1869 {
1870 /* Prevent unused argument(s) compilation warning */
1871 UNUSED(hqspi);
1872
1873 /* NOTE: This function Should not be modified, when the callback is needed,
1874 the HAL_QSPI_TxHalfCpltCallback could be implemented in the user file
1875 */
1876 }
1877
1878 /**
1879 * @brief FIFO Threshold callbacks
1880 * @param hqspi QSPI handle
1881 * @retval None
1882 */
1883 __weak void HAL_QSPI_FifoThresholdCallback(QSPI_HandleTypeDef *hqspi)
1884 {
1885 /* Prevent unused argument(s) compilation warning */
1886 UNUSED(hqspi);
1887
1888 /* NOTE : This function Should not be modified, when the callback is needed,
1889 the HAL_QSPI_FIFOThresholdCallback could be implemented in the user file
1890 */
1891 }
1892
1893 /**
1894 * @brief Status Match callbacks
1895 * @param hqspi QSPI handle
1896 * @retval None
1897 */
1898 __weak void HAL_QSPI_StatusMatchCallback(QSPI_HandleTypeDef *hqspi)
1899 {
1900 /* Prevent unused argument(s) compilation warning */
1901 UNUSED(hqspi);
1902
1903 /* NOTE : This function Should not be modified, when the callback is needed,
1904 the HAL_QSPI_StatusMatchCallback could be implemented in the user file
1905 */
1906 }
1907
1908 /**
1909 * @brief Timeout callbacks
1910 * @param hqspi QSPI handle
1911 * @retval None
1912 */
1913 __weak void HAL_QSPI_TimeOutCallback(QSPI_HandleTypeDef *hqspi)
1914 {
1915 /* Prevent unused argument(s) compilation warning */
1916 UNUSED(hqspi);
1917
1918 /* NOTE : This function Should not be modified, when the callback is needed,
1919 the HAL_QSPI_TimeOutCallback could be implemented in the user file
1920 */
1921 }
1922
1923 /**
1924 * @}
1925 */
1926
1927 /** @defgroup QSPI_Exported_Functions_Group3 Peripheral Control and State functions
1928 * @brief QSPI control and State functions
1929 *
1930 @verbatim
1931 ===============================================================================
1932 ##### Peripheral Control and State functions #####
1933 ===============================================================================
1934 [..]
1935 This subsection provides a set of functions allowing to :
1936 (+) Check in run-time the state of the driver.
1937 (+) Check the error code set during last operation.
1938 (+) Abort any operation.
1939
1940 @endverbatim
1941 * @{
1942 */
1943
1944 /**
1945 * @brief Return the QSPI handle state.
1946 * @param hqspi QSPI handle
1947 * @retval HAL state
1948 */
1949 HAL_QSPI_StateTypeDef HAL_QSPI_GetState(QSPI_HandleTypeDef *hqspi)
1950 {
1951 /* Return QSPI handle state */
1952 return hqspi->State;
1953 }
1954
1955 /**
1956 * @brief Return the QSPI error code
1957 * @param hqspi QSPI handle
1958 * @retval QSPI Error Code
1959 */
1960 uint32_t HAL_QSPI_GetError(QSPI_HandleTypeDef *hqspi)
1961 {
1962 return hqspi->ErrorCode;
1963 }
1964
1965 /**
1966 * @brief Abort the current transmission
1967 * @param hqspi QSPI handle
1968 * @retval HAL status
1969 */
1970 HAL_StatusTypeDef HAL_QSPI_Abort(QSPI_HandleTypeDef *hqspi)
1971 {
1972 HAL_StatusTypeDef status = HAL_OK;
1973 uint32_t tickstart = HAL_GetTick();
1974
1975 /* Check if the state is in one of the busy states */
1976 if ((hqspi->State & 0x2U) != 0U)
1977 {
1978 /* Process unlocked */
1979 __HAL_UNLOCK(hqspi);
1980
1981 if ((hqspi->Instance->CR & QUADSPI_CR_DMAEN)!= RESET)
1982 {
1983 /* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */
1984 CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
1985
1986 /* Abort DMA channel */
1987 status = HAL_DMA_Abort(hqspi->hdma);
1988 if(status != HAL_OK)
1989 {
1990 hqspi->ErrorCode |= HAL_QSPI_ERROR_DMA;
1991 }
1992 }
1993
1994 /* Configure QSPI: CR register with Abort request */
1995 SET_BIT(hqspi->Instance->CR, QUADSPI_CR_ABORT);
1996
1997 /* Wait until TC flag is set to go back in idle state */
1998 status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_TC, SET, tickstart, hqspi->Timeout);
1999
2000 if(status == HAL_OK)
2001 {
2002 __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);
2003
2004 /* Wait until BUSY flag is reset */
2005 status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, tickstart, hqspi->Timeout);
2006 }
2007
2008 if (status == HAL_OK)
2009 {
2010 /* Update state */
2011 hqspi->State = HAL_QSPI_STATE_READY;
2012 }
2013 }
2014
2015 return status;
2016 }
2017
2018 /**
2019 * @brief Abort the current transmission (non-blocking function)
2020 * @param hqspi QSPI handle
2021 * @retval HAL status
2022 */
2023 HAL_StatusTypeDef HAL_QSPI_Abort_IT(QSPI_HandleTypeDef *hqspi)
2024 {
2025 HAL_StatusTypeDef status = HAL_OK;
2026
2027 /* Check if the state is in one of the busy states */
2028 if ((hqspi->State & 0x2U) != 0U)
2029 {
2030 /* Process unlocked */
2031 __HAL_UNLOCK(hqspi);
2032
2033 /* Update QSPI state */
2034 hqspi->State = HAL_QSPI_STATE_ABORT;
2035
2036 /* Disable all interrupts */
2037 __HAL_QSPI_DISABLE_IT(hqspi, (QSPI_IT_TO | QSPI_IT_SM | QSPI_IT_FT | QSPI_IT_TC | QSPI_IT_TE));
2038
2039 if ((hqspi->Instance->CR & QUADSPI_CR_DMAEN)!= RESET)
2040 {
2041 /* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */
2042 CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
2043
2044 /* Abort DMA channel */
2045 hqspi->hdma->XferAbortCallback = QSPI_DMAAbortCplt;
2046 HAL_DMA_Abort_IT(hqspi->hdma);
2047 }
2048 else
2049 {
2050 /* Clear interrupt */
2051 __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);
2052
2053 /* Enable the QSPI Transfer Complete Interrupt */
2054 __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TC);
2055
2056 /* Configure QSPI: CR register with Abort request */
2057 SET_BIT(hqspi->Instance->CR, QUADSPI_CR_ABORT);
2058 }
2059 }
2060
2061 return status;
2062 }
2063
2064 /** @brief Set QSPI timeout
2065 * @param hqspi QSPI handle.
2066 * @param Timeout Timeout for the QSPI memory access.
2067 * @retval None
2068 */
2069 void HAL_QSPI_SetTimeout(QSPI_HandleTypeDef *hqspi, uint32_t Timeout)
2070 {
2071 hqspi->Timeout = Timeout;
2072 }
2073
2074 /** @brief Set QSPI Fifo threshold.
2075 * @param hqspi QSPI handle.
2076 * @param Threshold Threshold of the Fifo (value between 1 and 16).
2077 * @retval HAL status
2078 */
2079 HAL_StatusTypeDef HAL_QSPI_SetFifoThreshold(QSPI_HandleTypeDef *hqspi, uint32_t Threshold)
2080 {
2081 HAL_StatusTypeDef status = HAL_OK;
2082
2083 /* Process locked */
2084 __HAL_LOCK(hqspi);
2085
2086 if(hqspi->State == HAL_QSPI_STATE_READY)
2087 {
2088 /* Synchronize init structure with new FIFO threshold value */
2089 hqspi->Init.FifoThreshold = Threshold;
2090
2091 /* Configure QSPI FIFO Threshold */
2092 MODIFY_REG(hqspi->Instance->CR, QUADSPI_CR_FTHRES,
2093 ((hqspi->Init.FifoThreshold - 1U) << QUADSPI_CR_FTHRES_Pos));
2094 }
2095 else
2096 {
2097 status = HAL_BUSY;
2098 }
2099
2100 /* Process unlocked */
2101 __HAL_UNLOCK(hqspi);
2102
2103 /* Return function status */
2104 return status;
2105 }
2106
2107 /** @brief Get QSPI Fifo threshold.
2108 * @param hqspi QSPI handle.
2109 * @retval Fifo threshold (value between 1 and 16)
2110 */
2111 uint32_t HAL_QSPI_GetFifoThreshold(QSPI_HandleTypeDef *hqspi)
2112 {
2113 return ((READ_BIT(hqspi->Instance->CR, QUADSPI_CR_FTHRES) >> QUADSPI_CR_FTHRES_Pos) + 1U);
2114 }
2115
2116 /**
2117 * @}
2118 */
2119
2120 /* Private functions ---------------------------------------------------------*/
2121
2122 /**
2123 * @brief DMA QSPI receive process complete callback.
2124 * @param hdma DMA handle
2125 * @retval None
2126 */
2127 static void QSPI_DMARxCplt(DMA_HandleTypeDef *hdma)
2128 {
2129 QSPI_HandleTypeDef* hqspi = ( QSPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
2130 hqspi->RxXferCount = 0U;
2131
2132 /* Enable the QSPI transfer complete Interrupt */
2133 __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TC);
2134 }
2135
2136 /**
2137 * @brief DMA QSPI transmit process complete callback.
2138 * @param hdma DMA handle
2139 * @retval None
2140 */
2141 static void QSPI_DMATxCplt(DMA_HandleTypeDef *hdma)
2142 {
2143 QSPI_HandleTypeDef* hqspi = ( QSPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
2144 hqspi->TxXferCount = 0U;
2145
2146 /* Enable the QSPI transfer complete Interrupt */
2147 __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TC);
2148 }
2149
2150 /**
2151 * @brief DMA QSPI receive process half complete callback
2152 * @param hdma DMA handle
2153 * @retval None
2154 */
2155 static void QSPI_DMARxHalfCplt(DMA_HandleTypeDef *hdma)
2156 {
2157 QSPI_HandleTypeDef* hqspi = (QSPI_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
2158
2159 HAL_QSPI_RxHalfCpltCallback(hqspi);
2160 }
2161
2162 /**
2163 * @brief DMA QSPI transmit process half complete callback
2164 * @param hdma DMA handle
2165 * @retval None
2166 */
2167 static void QSPI_DMATxHalfCplt(DMA_HandleTypeDef *hdma)
2168 {
2169 QSPI_HandleTypeDef* hqspi = (QSPI_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
2170
2171 HAL_QSPI_TxHalfCpltCallback(hqspi);
2172 }
2173
2174 /**
2175 * @brief DMA QSPI communication error callback.
2176 * @param hdma DMA handle
2177 * @retval None
2178 */
2179 static void QSPI_DMAError(DMA_HandleTypeDef *hdma)
2180 {
2181 QSPI_HandleTypeDef* hqspi = ( QSPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
2182
2183 /* if DMA error is FIFO error ignore it */
2184 if(HAL_DMA_GetError(hdma) != HAL_DMA_ERROR_FE)
2185 {
2186 hqspi->RxXferCount = 0U;
2187 hqspi->TxXferCount = 0U;
2188 hqspi->ErrorCode |= HAL_QSPI_ERROR_DMA;
2189
2190 /* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */
2191 CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
2192
2193 /* Abort the QSPI */
2194 HAL_QSPI_Abort_IT(hqspi);
2195 }
2196 }
2197
2198 /**
2199 * @brief DMA QSPI abort complete callback.
2200 * @param hdma DMA handle
2201 * @retval None
2202 */
2203 static void QSPI_DMAAbortCplt(DMA_HandleTypeDef *hdma)
2204 {
2205 QSPI_HandleTypeDef* hqspi = ( QSPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
2206
2207 hqspi->RxXferCount = 0U;
2208 hqspi->TxXferCount = 0U;
2209
2210 if(hqspi->State == HAL_QSPI_STATE_ABORT)
2211 {
2212 /* DMA Abort called by QSPI abort */
2213 /* Clear interrupt */
2214 __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);
2215
2216 /* Enable the QSPI Transfer Complete Interrupt */
2217 __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TC);
2218
2219 /* Configure QSPI: CR register with Abort request */
2220 SET_BIT(hqspi->Instance->CR, QUADSPI_CR_ABORT);
2221 }
2222 else
2223 {
2224 /* DMA Abort called due to a transfer error interrupt */
2225 /* Change state of QSPI */
2226 hqspi->State = HAL_QSPI_STATE_READY;
2227
2228 /* Error callback */
2229 HAL_QSPI_ErrorCallback(hqspi);
2230 }
2231 }
2232 /**
2233 * @brief Wait for a flag state until timeout.
2234 * @param hqspi QSPI handle
2235 * @param Flag Flag checked
2236 * @param State Value of the flag expected
2237 * @param Timeout Duration of the time out
2238 * @param tickstart tick start value
2239 * @retval HAL status
2240 */
2241 static HAL_StatusTypeDef QSPI_WaitFlagStateUntilTimeout(QSPI_HandleTypeDef *hqspi, uint32_t Flag,
2242 FlagStatus State, uint32_t tickstart, uint32_t Timeout)
2243 {
2244 /* Wait until flag is in expected state */
2245 while((FlagStatus)(__HAL_QSPI_GET_FLAG(hqspi, Flag)) != State)
2246 {
2247 /* Check for the Timeout */
2248 if (Timeout != HAL_MAX_DELAY)
2249 {
2250 if((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout))
2251 {
2252 hqspi->State = HAL_QSPI_STATE_ERROR;
2253 hqspi->ErrorCode |= HAL_QSPI_ERROR_TIMEOUT;
2254
2255 return HAL_ERROR;
2256 }
2257 }
2258 }
2259 return HAL_OK;
2260 }
2261
2262 /**
2263 * @brief Configure the communication registers.
2264 * @param hqspi QSPI handle
2265 * @param cmd structure that contains the command configuration information
2266 * @param FunctionalMode functional mode to configured
2267 * This parameter can be one of the following values:
2268 * @arg QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE: Indirect write mode
2269 * @arg QSPI_FUNCTIONAL_MODE_INDIRECT_READ: Indirect read mode
2270 * @arg QSPI_FUNCTIONAL_MODE_AUTO_POLLING: Automatic polling mode
2271 * @arg QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED: Memory-mapped mode
2272 * @retval None
2273 */
2274 static void QSPI_Config(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uint32_t FunctionalMode)
2275 {
2276 assert_param(IS_QSPI_FUNCTIONAL_MODE(FunctionalMode));
2277
2278 if ((cmd->DataMode != QSPI_DATA_NONE) && (FunctionalMode != QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED))
2279 {
2280 /* Configure QSPI: DLR register with the number of data to read or write */
2281 WRITE_REG(hqspi->Instance->DLR, (cmd->NbData - 1U));
2282 }
2283
2284 if (cmd->InstructionMode != QSPI_INSTRUCTION_NONE)
2285 {
2286 if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE)
2287 {
2288 /* Configure QSPI: ABR register with alternate bytes value */
2289 WRITE_REG(hqspi->Instance->ABR, cmd->AlternateBytes);
2290
2291 if (cmd->AddressMode != QSPI_ADDRESS_NONE)
2292 {
2293 /*---- Command with instruction, address and alternate bytes ----*/
2294 /* Configure QSPI: CCR register with all communications parameters */
2295 WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode |
2296 cmd->DataMode | (cmd->DummyCycles << 18U) | cmd->AlternateBytesSize |
2297 cmd->AlternateByteMode | cmd->AddressSize | cmd->AddressMode |
2298 cmd->InstructionMode | cmd->Instruction | FunctionalMode));
2299
2300 if (FunctionalMode != QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED)
2301 {
2302 /* Configure QSPI: AR register with address value */
2303 WRITE_REG(hqspi->Instance->AR, cmd->Address);
2304 }
2305 }
2306 else
2307 {
2308 /*---- Command with instruction and alternate bytes ----*/
2309 /* Configure QSPI: CCR register with all communications parameters */
2310 WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode |
2311 cmd->DataMode | (cmd->DummyCycles << 18U) | cmd->AlternateBytesSize |
2312 cmd->AlternateByteMode | cmd->AddressMode | cmd->InstructionMode |
2313 cmd->Instruction | FunctionalMode));
2314 }
2315 }
2316 else
2317 {
2318 if (cmd->AddressMode != QSPI_ADDRESS_NONE)
2319 {
2320 /*---- Command with instruction and address ----*/
2321 /* Configure QSPI: CCR register with all communications parameters */
2322 WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode |
2323 cmd->DataMode | (cmd->DummyCycles << 18U) | cmd->AlternateByteMode |
2324 cmd->AddressSize | cmd->AddressMode | cmd->InstructionMode |
2325 cmd->Instruction | FunctionalMode));
2326
2327 if (FunctionalMode != QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED)
2328 {
2329 /* Configure QSPI: AR register with address value */
2330 WRITE_REG(hqspi->Instance->AR, cmd->Address);
2331 }
2332 }
2333 else
2334 {
2335 /*---- Command with only instruction ----*/
2336 /* Configure QSPI: CCR register with all communications parameters */
2337 WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode |
2338 cmd->DataMode | (cmd->DummyCycles << 18U) | cmd->AlternateByteMode |
2339 cmd->AddressMode | cmd->InstructionMode | cmd->Instruction |
2340 FunctionalMode));
2341 }
2342 }
2343 }
2344 else
2345 {
2346 if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE)
2347 {
2348 /* Configure QSPI: ABR register with alternate bytes value */
2349 WRITE_REG(hqspi->Instance->ABR, cmd->AlternateBytes);
2350
2351 if (cmd->AddressMode != QSPI_ADDRESS_NONE)
2352 {
2353 /*---- Command with address and alternate bytes ----*/
2354 /* Configure QSPI: CCR register with all communications parameters */
2355 WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode |
2356 cmd->DataMode | (cmd->DummyCycles << 18U) | cmd->AlternateBytesSize |
2357 cmd->AlternateByteMode | cmd->AddressSize | cmd->AddressMode |
2358 cmd->InstructionMode | FunctionalMode));
2359
2360 if (FunctionalMode != QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED)
2361 {
2362 /* Configure QSPI: AR register with address value */
2363 WRITE_REG(hqspi->Instance->AR, cmd->Address);
2364 }
2365 }
2366 else
2367 {
2368 /*---- Command with only alternate bytes ----*/
2369 /* Configure QSPI: CCR register with all communications parameters */
2370 WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode |
2371 cmd->DataMode | (cmd->DummyCycles << 18U) | cmd->AlternateBytesSize |
2372 cmd->AlternateByteMode | cmd->AddressMode | cmd->InstructionMode |
2373 FunctionalMode));
2374 }
2375 }
2376 else
2377 {
2378 if (cmd->AddressMode != QSPI_ADDRESS_NONE)
2379 {
2380 /*---- Command with only address ----*/
2381 /* Configure QSPI: CCR register with all communications parameters */
2382 WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode |
2383 cmd->DataMode | (cmd->DummyCycles << 18U) | cmd->AlternateByteMode |
2384 cmd->AddressSize | cmd->AddressMode | cmd->InstructionMode |
2385 FunctionalMode));
2386
2387 if (FunctionalMode != QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED)
2388 {
2389 /* Configure QSPI: AR register with address value */
2390 WRITE_REG(hqspi->Instance->AR, cmd->Address);
2391 }
2392 }
2393 else
2394 {
2395 /*---- Command with only data phase ----*/
2396 if (cmd->DataMode != QSPI_DATA_NONE)
2397 {
2398 /* Configure QSPI: CCR register with all communications parameters */
2399 WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode |
2400 cmd->DataMode | (cmd->DummyCycles << 18U) | cmd->AlternateByteMode |
2401 cmd->AddressMode | cmd->InstructionMode | FunctionalMode));
2402 }
2403 }
2404 }
2405 }
2406 }
2407 /**
2408 * @}
2409 */
2410 #endif /* STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx || STM32F412Rx
2411 STM32F413xx || STM32F423xx */
2412
2413 #endif /* HAL_QSPI_MODULE_ENABLED */
2414 /**
2415 * @}
2416 */
2417
2418 /**
2419 * @}
2420 */
2421
2422 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/