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comparison Common/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dsi.c @ 160:e3ca52b8e7fa

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Merge with FlipDisplay
author heinrichsweikamp
date Thu, 07 Mar 2019 15:06:43 +0100
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80:cc2bb7bb8456 160:e3ca52b8e7fa
1 /**
2 ******************************************************************************
3 * @file stm32f4xx_hal_dsi.c
4 * @author MCD Application Team
5 * @brief DSI HAL module driver.
6 * This file provides firmware functions to manage the following
7 * functionalities of the DSI peripheral:
8 * + Initialization and de-initialization functions
9 * + IO operation functions
10 * + Peripheral Control functions
11 * + Peripheral State and Errors functions
12 ******************************************************************************
13 * @attention
14 *
15 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
16 *
17 * Redistribution and use in source and binary forms, with or without modification,
18 * are permitted provided that the following conditions are met:
19 * 1. Redistributions of source code must retain the above copyright notice,
20 * this list of conditions and the following disclaimer.
21 * 2. Redistributions in binary form must reproduce the above copyright notice,
22 * this list of conditions and the following disclaimer in the documentation
23 * and/or other materials provided with the distribution.
24 * 3. Neither the name of STMicroelectronics nor the names of its contributors
25 * may be used to endorse or promote products derived from this software
26 * without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
29 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
30 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
31 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
32 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
34 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
35 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
36 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
37 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
38 *
39 ******************************************************************************
40 */
41
42 /* Includes ------------------------------------------------------------------*/
43 #include "stm32f4xx_hal.h"
44
45 /** @addtogroup STM32F4xx_HAL_Driver
46 * @{
47 */
48
49 #ifdef HAL_DSI_MODULE_ENABLED
50
51 #if defined(DSI)
52
53 /** @addtogroup DSI
54 * @{
55 */
56
57 /* Private types -------------------------------------------------------------*/
58 /* Private defines -----------------------------------------------------------*/
59 /** @addtogroup DSI_Private_Constants
60 * @{
61 */
62 #define DSI_TIMEOUT_VALUE ((uint32_t)1000U) /* 1s */
63
64 #define DSI_ERROR_ACK_MASK (DSI_ISR0_AE0 | DSI_ISR0_AE1 | DSI_ISR0_AE2 | DSI_ISR0_AE3 | \
65 DSI_ISR0_AE4 | DSI_ISR0_AE5 | DSI_ISR0_AE6 | DSI_ISR0_AE7 | \
66 DSI_ISR0_AE8 | DSI_ISR0_AE9 | DSI_ISR0_AE10 | DSI_ISR0_AE11 | \
67 DSI_ISR0_AE12 | DSI_ISR0_AE13 | DSI_ISR0_AE14 | DSI_ISR0_AE15)
68 #define DSI_ERROR_PHY_MASK (DSI_ISR0_PE0 | DSI_ISR0_PE1 | DSI_ISR0_PE2 | DSI_ISR0_PE3 | DSI_ISR0_PE4)
69 #define DSI_ERROR_TX_MASK DSI_ISR1_TOHSTX
70 #define DSI_ERROR_RX_MASK DSI_ISR1_TOLPRX
71 #define DSI_ERROR_ECC_MASK (DSI_ISR1_ECCSE | DSI_ISR1_ECCME)
72 #define DSI_ERROR_CRC_MASK DSI_ISR1_CRCE
73 #define DSI_ERROR_PSE_MASK DSI_ISR1_PSE
74 #define DSI_ERROR_EOT_MASK DSI_ISR1_EOTPE
75 #define DSI_ERROR_OVF_MASK DSI_ISR1_LPWRE
76 #define DSI_ERROR_GEN_MASK (DSI_ISR1_GCWRE | DSI_ISR1_GPWRE | DSI_ISR1_GPTXE | DSI_ISR1_GPRDE | DSI_ISR1_GPRXE)
77 /**
78 * @}
79 */
80
81 /* Private variables ---------------------------------------------------------*/
82 /* Private constants ---------------------------------------------------------*/
83 /* Private macros ------------------------------------------------------------*/
84 /* Private function prototypes -----------------------------------------------*/
85 static void DSI_ConfigPacketHeader(DSI_TypeDef *DSIx, uint32_t ChannelID, uint32_t DataType, uint32_t Data0, uint32_t Data1);
86
87 /* Private functions ---------------------------------------------------------*/
88 /**
89 * @brief Generic DSI packet header configuration
90 * @param DSIx Pointer to DSI register base
91 * @param ChannelID Virtual channel ID of the header packet
92 * @param DataType Packet data type of the header packet
93 * This parameter can be any value of :
94 * @ref DSI_SHORT_WRITE_PKT_Data_Type
95 * or @ref DSI_LONG_WRITE_PKT_Data_Type
96 * or @ref DSI_SHORT_READ_PKT_Data_Type
97 * or DSI_MAX_RETURN_PKT_SIZE
98 * @param Data0 Word count LSB
99 * @param Data1 Word count MSB
100 * @retval None
101 */
102 static void DSI_ConfigPacketHeader(DSI_TypeDef *DSIx,
103 uint32_t ChannelID,
104 uint32_t DataType,
105 uint32_t Data0,
106 uint32_t Data1)
107 {
108 /* Update the DSI packet header with new information */
109 DSIx->GHCR = (DataType | (ChannelID<<6U) | (Data0<<8U) | (Data1<<16U));
110 }
111
112 /* Exported functions --------------------------------------------------------*/
113 /** @addtogroup DSI_Exported_Functions
114 * @{
115 */
116
117 /** @defgroup DSI_Group1 Initialization and Configuration functions
118 * @brief Initialization and Configuration functions
119 *
120 @verbatim
121 ===============================================================================
122 ##### Initialization and Configuration functions #####
123 ===============================================================================
124 [..] This section provides functions allowing to:
125 (+) Initialize and configure the DSI
126 (+) De-initialize the DSI
127
128 @endverbatim
129 * @{
130 */
131
132 /**
133 * @brief Initializes the DSI according to the specified
134 * parameters in the DSI_InitTypeDef and create the associated handle.
135 * @param hdsi pointer to a DSI_HandleTypeDef structure that contains
136 * the configuration information for the DSI.
137 * @param PLLInit pointer to a DSI_PLLInitTypeDef structure that contains
138 * the PLL Clock structure definition for the DSI.
139 * @retval HAL status
140 */
141 HAL_StatusTypeDef HAL_DSI_Init(DSI_HandleTypeDef *hdsi, DSI_PLLInitTypeDef *PLLInit)
142 {
143 uint32_t tickstart;
144 uint32_t unitIntervalx4;
145 uint32_t tempIDF;
146
147 /* Check the DSI handle allocation */
148 if(hdsi == NULL)
149 {
150 return HAL_ERROR;
151 }
152
153 /* Check function parameters */
154 assert_param(IS_DSI_PLL_NDIV(PLLInit->PLLNDIV));
155 assert_param(IS_DSI_PLL_IDF(PLLInit->PLLIDF));
156 assert_param(IS_DSI_PLL_ODF(PLLInit->PLLODF));
157 assert_param(IS_DSI_AUTO_CLKLANE_CONTROL(hdsi->Init.AutomaticClockLaneControl));
158 assert_param(IS_DSI_NUMBER_OF_LANES(hdsi->Init.NumberOfLanes));
159
160 if(hdsi->State == HAL_DSI_STATE_RESET)
161 {
162 /* Initialize the low level hardware */
163 HAL_DSI_MspInit(hdsi);
164 }
165
166 /* Change DSI peripheral state */
167 hdsi->State = HAL_DSI_STATE_BUSY;
168
169 /**************** Turn on the regulator and enable the DSI PLL ****************/
170
171 /* Enable the regulator */
172 __HAL_DSI_REG_ENABLE(hdsi);
173
174 /* Get tick */
175 tickstart = HAL_GetTick();
176
177 /* Wait until the regulator is ready */
178 while(__HAL_DSI_GET_FLAG(hdsi, DSI_FLAG_RRS) == RESET)
179 {
180 /* Check for the Timeout */
181 if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE)
182 {
183 return HAL_TIMEOUT;
184 }
185 }
186
187 /* Set the PLL division factors */
188 hdsi->Instance->WRPCR &= ~(DSI_WRPCR_PLL_NDIV | DSI_WRPCR_PLL_IDF | DSI_WRPCR_PLL_ODF);
189 hdsi->Instance->WRPCR |= (((PLLInit->PLLNDIV)<<2U) | ((PLLInit->PLLIDF)<<11U) | ((PLLInit->PLLODF)<<16U));
190
191 /* Enable the DSI PLL */
192 __HAL_DSI_PLL_ENABLE(hdsi);
193
194 /* Get tick */
195 tickstart = HAL_GetTick();
196
197 /* Wait for the lock of the PLL */
198 while(__HAL_DSI_GET_FLAG(hdsi, DSI_FLAG_PLLLS) == RESET)
199 {
200 /* Check for the Timeout */
201 if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE)
202 {
203 return HAL_TIMEOUT;
204 }
205 }
206
207 /*************************** Set the PHY parameters ***************************/
208
209 /* D-PHY clock and digital enable*/
210 hdsi->Instance->PCTLR |= (DSI_PCTLR_CKE | DSI_PCTLR_DEN);
211
212 /* Clock lane configuration */
213 hdsi->Instance->CLCR &= ~(DSI_CLCR_DPCC | DSI_CLCR_ACR);
214 hdsi->Instance->CLCR |= (DSI_CLCR_DPCC | hdsi->Init.AutomaticClockLaneControl);
215
216 /* Configure the number of active data lanes */
217 hdsi->Instance->PCONFR &= ~DSI_PCONFR_NL;
218 hdsi->Instance->PCONFR |= hdsi->Init.NumberOfLanes;
219
220 /************************ Set the DSI clock parameters ************************/
221
222 /* Set the TX escape clock division factor */
223 hdsi->Instance->CCR &= ~DSI_CCR_TXECKDIV;
224 hdsi->Instance->CCR |= hdsi->Init.TXEscapeCkdiv;
225
226 /* Calculate the bit period in high-speed mode in unit of 0.25 ns (UIX4) */
227 /* The equation is : UIX4 = IntegerPart( (1000/F_PHY_Mhz) * 4 ) */
228 /* Where : F_PHY_Mhz = (NDIV * HSE_Mhz) / (IDF * ODF) */
229 tempIDF = (PLLInit->PLLIDF > 0U) ? PLLInit->PLLIDF : 1U;
230 unitIntervalx4 = (4000000U * tempIDF * (1U << PLLInit->PLLODF)) / ((HSE_VALUE/1000U) * PLLInit->PLLNDIV);
231
232 /* Set the bit period in high-speed mode */
233 hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_UIX4;
234 hdsi->Instance->WPCR[0U] |= unitIntervalx4;
235
236 /****************************** Error management *****************************/
237
238 /* Disable all error interrupts and reset the Error Mask */
239 hdsi->Instance->IER[0U] = 0U;
240 hdsi->Instance->IER[1U] = 0U;
241 hdsi->ErrorMsk = 0U;
242
243 /* Initialise the error code */
244 hdsi->ErrorCode = HAL_DSI_ERROR_NONE;
245
246 /* Initialize the DSI state*/
247 hdsi->State = HAL_DSI_STATE_READY;
248
249 return HAL_OK;
250 }
251
252 /**
253 * @brief De-initializes the DSI peripheral registers to their default reset
254 * values.
255 * @param hdsi pointer to a DSI_HandleTypeDef structure that contains
256 * the configuration information for the DSI.
257 * @retval HAL status
258 */
259 HAL_StatusTypeDef HAL_DSI_DeInit(DSI_HandleTypeDef *hdsi)
260 {
261 /* Check the DSI handle allocation */
262 if(hdsi == NULL)
263 {
264 return HAL_ERROR;
265 }
266
267 /* Change DSI peripheral state */
268 hdsi->State = HAL_DSI_STATE_BUSY;
269
270 /* Disable the DSI wrapper */
271 __HAL_DSI_WRAPPER_DISABLE(hdsi);
272
273 /* Disable the DSI host */
274 __HAL_DSI_DISABLE(hdsi);
275
276 /* D-PHY clock and digital disable */
277 hdsi->Instance->PCTLR &= ~(DSI_PCTLR_CKE | DSI_PCTLR_DEN);
278
279 /* Turn off the DSI PLL */
280 __HAL_DSI_PLL_DISABLE(hdsi);
281
282 /* Disable the regulator */
283 __HAL_DSI_REG_DISABLE(hdsi);
284
285 /* DeInit the low level hardware */
286 HAL_DSI_MspDeInit(hdsi);
287
288 /* Initialise the error code */
289 hdsi->ErrorCode = HAL_DSI_ERROR_NONE;
290
291 /* Initialize the DSI state*/
292 hdsi->State = HAL_DSI_STATE_RESET;
293
294 /* Release Lock */
295 __HAL_UNLOCK(hdsi);
296
297 return HAL_OK;
298 }
299
300 /**
301 * @brief Enable the error monitor flags
302 * @param hdsi pointer to a DSI_HandleTypeDef structure that contains
303 * the configuration information for the DSI.
304 * @param ActiveErrors indicates which error interrupts will be enabled.
305 * This parameter can be any combination of @ref DSI_Error_Data_Type.
306 * @retval HAL status
307 */
308 HAL_StatusTypeDef HAL_DSI_ConfigErrorMonitor(DSI_HandleTypeDef *hdsi, uint32_t ActiveErrors)
309 {
310 /* Process locked */
311 __HAL_LOCK(hdsi);
312
313 hdsi->Instance->IER[0U] = 0U;
314 hdsi->Instance->IER[1U] = 0U;
315
316 /* Store active errors to the handle */
317 hdsi->ErrorMsk = ActiveErrors;
318
319 if((ActiveErrors & HAL_DSI_ERROR_ACK) != RESET)
320 {
321 /* Enable the interrupt generation on selected errors */
322 hdsi->Instance->IER[0U] |= DSI_ERROR_ACK_MASK;
323 }
324
325 if((ActiveErrors & HAL_DSI_ERROR_PHY) != RESET)
326 {
327 /* Enable the interrupt generation on selected errors */
328 hdsi->Instance->IER[0U] |= DSI_ERROR_PHY_MASK;
329 }
330
331 if((ActiveErrors & HAL_DSI_ERROR_TX) != RESET)
332 {
333 /* Enable the interrupt generation on selected errors */
334 hdsi->Instance->IER[1U] |= DSI_ERROR_TX_MASK;
335 }
336
337 if((ActiveErrors & HAL_DSI_ERROR_RX) != RESET)
338 {
339 /* Enable the interrupt generation on selected errors */
340 hdsi->Instance->IER[1U] |= DSI_ERROR_RX_MASK;
341 }
342
343 if((ActiveErrors & HAL_DSI_ERROR_ECC) != RESET)
344 {
345 /* Enable the interrupt generation on selected errors */
346 hdsi->Instance->IER[1U] |= DSI_ERROR_ECC_MASK;
347 }
348
349 if((ActiveErrors & HAL_DSI_ERROR_CRC) != RESET)
350 {
351 /* Enable the interrupt generation on selected errors */
352 hdsi->Instance->IER[1U] |= DSI_ERROR_CRC_MASK;
353 }
354
355 if((ActiveErrors & HAL_DSI_ERROR_PSE) != RESET)
356 {
357 /* Enable the interrupt generation on selected errors */
358 hdsi->Instance->IER[1U] |= DSI_ERROR_PSE_MASK;
359 }
360
361 if((ActiveErrors & HAL_DSI_ERROR_EOT) != RESET)
362 {
363 /* Enable the interrupt generation on selected errors */
364 hdsi->Instance->IER[1U] |= DSI_ERROR_EOT_MASK;
365 }
366
367 if((ActiveErrors & HAL_DSI_ERROR_OVF) != RESET)
368 {
369 /* Enable the interrupt generation on selected errors */
370 hdsi->Instance->IER[1U] |= DSI_ERROR_OVF_MASK;
371 }
372
373 if((ActiveErrors & HAL_DSI_ERROR_GEN) != RESET)
374 {
375 /* Enable the interrupt generation on selected errors */
376 hdsi->Instance->IER[1U] |= DSI_ERROR_GEN_MASK;
377 }
378
379 /* Process Unlocked */
380 __HAL_UNLOCK(hdsi);
381
382 return HAL_OK;
383 }
384
385 /**
386 * @brief Initializes the DSI MSP.
387 * @param hdsi pointer to a DSI_HandleTypeDef structure that contains
388 * the configuration information for the DSI.
389 * @retval None
390 */
391 __weak void HAL_DSI_MspInit(DSI_HandleTypeDef* hdsi)
392 {
393 /* Prevent unused argument(s) compilation warning */
394 UNUSED(hdsi);
395 /* NOTE : This function Should not be modified, when the callback is needed,
396 the HAL_DSI_MspInit could be implemented in the user file
397 */
398 }
399
400 /**
401 * @brief De-initializes the DSI MSP.
402 * @param hdsi pointer to a DSI_HandleTypeDef structure that contains
403 * the configuration information for the DSI.
404 * @retval None
405 */
406 __weak void HAL_DSI_MspDeInit(DSI_HandleTypeDef* hdsi)
407 {
408 /* Prevent unused argument(s) compilation warning */
409 UNUSED(hdsi);
410 /* NOTE : This function Should not be modified, when the callback is needed,
411 the HAL_DSI_MspDeInit could be implemented in the user file
412 */
413 }
414
415 /**
416 * @}
417 */
418
419 /** @defgroup DSI_Group2 IO operation functions
420 * @brief IO operation functions
421 *
422 @verbatim
423 ===============================================================================
424 ##### IO operation functions #####
425 ===============================================================================
426 [..] This section provides function allowing to:
427 (+) Handle DSI interrupt request
428
429 @endverbatim
430 * @{
431 */
432 /**
433 * @brief Handles DSI interrupt request.
434 * @param hdsi pointer to a DSI_HandleTypeDef structure that contains
435 * the configuration information for the DSI.
436 * @retval HAL status
437 */
438 void HAL_DSI_IRQHandler(DSI_HandleTypeDef *hdsi)
439 {
440 uint32_t ErrorStatus0, ErrorStatus1;
441
442 /* Tearing Effect Interrupt management ***************************************/
443 if(__HAL_DSI_GET_FLAG(hdsi, DSI_FLAG_TE) != RESET)
444 {
445 if(__HAL_DSI_GET_IT_SOURCE(hdsi, DSI_IT_TE) != RESET)
446 {
447 /* Clear the Tearing Effect Interrupt Flag */
448 __HAL_DSI_CLEAR_FLAG(hdsi, DSI_FLAG_TE);
449
450 /* Tearing Effect Callback */
451 HAL_DSI_TearingEffectCallback(hdsi);
452 }
453 }
454
455 /* End of Refresh Interrupt management ***************************************/
456 if(__HAL_DSI_GET_FLAG(hdsi, DSI_FLAG_ER) != RESET)
457 {
458 if(__HAL_DSI_GET_IT_SOURCE(hdsi, DSI_IT_ER) != RESET)
459 {
460 /* Clear the End of Refresh Interrupt Flag */
461 __HAL_DSI_CLEAR_FLAG(hdsi, DSI_FLAG_ER);
462
463 /* End of Refresh Callback */
464 HAL_DSI_EndOfRefreshCallback(hdsi);
465 }
466 }
467
468 /* Error Interrupts management ***********************************************/
469 if(hdsi->ErrorMsk != 0U)
470 {
471 ErrorStatus0 = hdsi->Instance->ISR[0U];
472 ErrorStatus0 &= hdsi->Instance->IER[0U];
473 ErrorStatus1 = hdsi->Instance->ISR[1U];
474 ErrorStatus1 &= hdsi->Instance->IER[1U];
475
476 if((ErrorStatus0 & DSI_ERROR_ACK_MASK) != RESET)
477 {
478 hdsi->ErrorCode |= HAL_DSI_ERROR_ACK;
479 }
480
481 if((ErrorStatus0 & DSI_ERROR_PHY_MASK) != RESET)
482 {
483 hdsi->ErrorCode |= HAL_DSI_ERROR_PHY;
484 }
485
486 if((ErrorStatus1 & DSI_ERROR_TX_MASK) != RESET)
487 {
488 hdsi->ErrorCode |= HAL_DSI_ERROR_TX;
489 }
490
491 if((ErrorStatus1 & DSI_ERROR_RX_MASK) != RESET)
492 {
493 hdsi->ErrorCode |= HAL_DSI_ERROR_RX;
494 }
495
496 if((ErrorStatus1 & DSI_ERROR_ECC_MASK) != RESET)
497 {
498 hdsi->ErrorCode |= HAL_DSI_ERROR_ECC;
499 }
500
501 if((ErrorStatus1 & DSI_ERROR_CRC_MASK) != RESET)
502 {
503 hdsi->ErrorCode |= HAL_DSI_ERROR_CRC;
504 }
505
506 if((ErrorStatus1 & DSI_ERROR_PSE_MASK) != RESET)
507 {
508 hdsi->ErrorCode |= HAL_DSI_ERROR_PSE;
509 }
510
511 if((ErrorStatus1 & DSI_ERROR_EOT_MASK) != RESET)
512 {
513 hdsi->ErrorCode |= HAL_DSI_ERROR_EOT;
514 }
515
516 if((ErrorStatus1 & DSI_ERROR_OVF_MASK) != RESET)
517 {
518 hdsi->ErrorCode |= HAL_DSI_ERROR_OVF;
519 }
520
521 if((ErrorStatus1 & DSI_ERROR_GEN_MASK) != RESET)
522 {
523 hdsi->ErrorCode |= HAL_DSI_ERROR_GEN;
524 }
525
526 /* Check only selected errors */
527 if(hdsi->ErrorCode != HAL_DSI_ERROR_NONE)
528 {
529 /* DSI error interrupt user callback */
530 HAL_DSI_ErrorCallback(hdsi);
531 }
532 }
533 }
534
535 /**
536 * @brief Tearing Effect DSI callback.
537 * @param hdsi pointer to a DSI_HandleTypeDef structure that contains
538 * the configuration information for the DSI.
539 * @retval None
540 */
541 __weak void HAL_DSI_TearingEffectCallback(DSI_HandleTypeDef *hdsi)
542 {
543 /* Prevent unused argument(s) compilation warning */
544 UNUSED(hdsi);
545 /* NOTE : This function Should not be modified, when the callback is needed,
546 the HAL_DSI_TearingEffectCallback could be implemented in the user file
547 */
548 }
549
550 /**
551 * @brief End of Refresh DSI callback.
552 * @param hdsi pointer to a DSI_HandleTypeDef structure that contains
553 * the configuration information for the DSI.
554 * @retval None
555 */
556 __weak void HAL_DSI_EndOfRefreshCallback(DSI_HandleTypeDef *hdsi)
557 {
558 /* Prevent unused argument(s) compilation warning */
559 UNUSED(hdsi);
560 /* NOTE : This function Should not be modified, when the callback is needed,
561 the HAL_DSI_EndOfRefreshCallback could be implemented in the user file
562 */
563 }
564
565 /**
566 * @brief Operation Error DSI callback.
567 * @param hdsi pointer to a DSI_HandleTypeDef structure that contains
568 * the configuration information for the DSI.
569 * @retval None
570 */
571 __weak void HAL_DSI_ErrorCallback(DSI_HandleTypeDef *hdsi)
572 {
573 /* Prevent unused argument(s) compilation warning */
574 UNUSED(hdsi);
575 /* NOTE : This function Should not be modified, when the callback is needed,
576 the HAL_DSI_ErrorCallback could be implemented in the user file
577 */
578 }
579
580 /**
581 * @}
582 */
583
584 /** @defgroup DSI_Group3 Peripheral Control functions
585 * @brief Peripheral Control functions
586 *
587 @verbatim
588 ===============================================================================
589 ##### Peripheral Control functions #####
590 ===============================================================================
591 [..] This section provides functions allowing to:
592 (+) Configure the Generic interface read-back Virtual Channel ID
593 (+) Select video mode and configure the corresponding parameters
594 (+) Configure command transmission mode: High-speed or Low-power
595 (+) Configure the flow control
596 (+) Configure the DSI PHY timer
597 (+) Configure the DSI HOST timeout
598 (+) Configure the DSI HOST timeout
599 (+) Start/Stop the DSI module
600 (+) Refresh the display in command mode
601 (+) Controls the display color mode in Video mode
602 (+) Control the display shutdown in Video mode
603 (+) write short DCS or short Generic command
604 (+) write long DCS or long Generic command
605 (+) Read command (DCS or generic)
606 (+) Enter/Exit the Ultra Low Power Mode on data only (D-PHY PLL running)
607 (+) Enter/Exit the Ultra Low Power Mode on data only and clock (D-PHY PLL turned off)
608 (+) Start/Stop test pattern generation
609 (+) Slew-Rate And Delay Tuning
610 (+) Low-Power Reception Filter Tuning
611 (+) Activate an additional current path on all lanes to meet the SDDTx parameter
612 (+) Custom lane pins configuration
613 (+) Set custom timing for the PHY
614 (+) Force the Clock/Data Lane in TX Stop Mode
615 (+) Force LP Receiver in Low-Power Mode
616 (+) Force Data Lanes in RX Mode after a BTA
617 (+) Enable a pull-down on the lanes to prevent from floating states when unused
618 (+) Switch off the contention detection on data lanes
619
620 @endverbatim
621 * @{
622 */
623
624 /**
625 * @brief Configure the Generic interface read-back Virtual Channel ID.
626 * @param hdsi pointer to a DSI_HandleTypeDef structure that contains
627 * the configuration information for the DSI.
628 * @param VirtualChannelID Virtual channel ID
629 * @retval HAL status
630 */
631 HAL_StatusTypeDef HAL_DSI_SetGenericVCID(DSI_HandleTypeDef *hdsi, uint32_t VirtualChannelID)
632 {
633 /* Process locked */
634 __HAL_LOCK(hdsi);
635
636 /* Update the GVCID register */
637 hdsi->Instance->GVCIDR &= ~DSI_GVCIDR_VCID;
638 hdsi->Instance->GVCIDR |= VirtualChannelID;
639
640 /* Process unlocked */
641 __HAL_UNLOCK(hdsi);
642
643 return HAL_OK;
644 }
645
646 /**
647 * @brief Select video mode and configure the corresponding parameters
648 * @param hdsi pointer to a DSI_HandleTypeDef structure that contains
649 * the configuration information for the DSI.
650 * @param VidCfg pointer to a DSI_VidCfgTypeDef structure that contains
651 * the DSI video mode configuration parameters
652 * @retval HAL status
653 */
654 HAL_StatusTypeDef HAL_DSI_ConfigVideoMode(DSI_HandleTypeDef *hdsi, DSI_VidCfgTypeDef *VidCfg)
655 {
656 /* Process locked */
657 __HAL_LOCK(hdsi);
658
659 /* Check the parameters */
660 assert_param(IS_DSI_COLOR_CODING(VidCfg->ColorCoding));
661 assert_param(IS_DSI_VIDEO_MODE_TYPE(VidCfg->Mode));
662 assert_param(IS_DSI_LP_COMMAND(VidCfg->LPCommandEnable));
663 assert_param(IS_DSI_LP_HFP(VidCfg->LPHorizontalFrontPorchEnable));
664 assert_param(IS_DSI_LP_HBP(VidCfg->LPHorizontalBackPorchEnable));
665 assert_param(IS_DSI_LP_VACTIVE(VidCfg->LPVerticalActiveEnable));
666 assert_param(IS_DSI_LP_VFP(VidCfg->LPVerticalFrontPorchEnable));
667 assert_param(IS_DSI_LP_VBP(VidCfg->LPVerticalBackPorchEnable));
668 assert_param(IS_DSI_LP_VSYNC(VidCfg->LPVerticalSyncActiveEnable));
669 assert_param(IS_DSI_FBTAA(VidCfg->FrameBTAAcknowledgeEnable));
670 assert_param(IS_DSI_DE_POLARITY(VidCfg->DEPolarity));
671 assert_param(IS_DSI_VSYNC_POLARITY(VidCfg->VSPolarity));
672 assert_param(IS_DSI_HSYNC_POLARITY(VidCfg->HSPolarity));
673 /* Check the LooselyPacked variant only in 18-bit mode */
674 if(VidCfg->ColorCoding == DSI_RGB666)
675 {
676 assert_param(IS_DSI_LOOSELY_PACKED(VidCfg->LooselyPacked));
677 }
678
679 /* Select video mode by resetting CMDM and DSIM bits */
680 hdsi->Instance->MCR &= ~DSI_MCR_CMDM;
681 hdsi->Instance->WCFGR &= ~DSI_WCFGR_DSIM;
682
683 /* Configure the video mode transmission type */
684 hdsi->Instance->VMCR &= ~DSI_VMCR_VMT;
685 hdsi->Instance->VMCR |= VidCfg->Mode;
686
687 /* Configure the video packet size */
688 hdsi->Instance->VPCR &= ~DSI_VPCR_VPSIZE;
689 hdsi->Instance->VPCR |= VidCfg->PacketSize;
690
691 /* Set the chunks number to be transmitted through the DSI link */
692 hdsi->Instance->VCCR &= ~DSI_VCCR_NUMC;
693 hdsi->Instance->VCCR |= VidCfg->NumberOfChunks;
694
695 /* Set the size of the null packet */
696 hdsi->Instance->VNPCR &= ~DSI_VNPCR_NPSIZE;
697 hdsi->Instance->VNPCR |= VidCfg->NullPacketSize;
698
699 /* Select the virtual channel for the LTDC interface traffic */
700 hdsi->Instance->LVCIDR &= ~DSI_LVCIDR_VCID;
701 hdsi->Instance->LVCIDR |= VidCfg->VirtualChannelID;
702
703 /* Configure the polarity of control signals */
704 hdsi->Instance->LPCR &= ~(DSI_LPCR_DEP | DSI_LPCR_VSP | DSI_LPCR_HSP);
705 hdsi->Instance->LPCR |= (VidCfg->DEPolarity | VidCfg->VSPolarity | VidCfg->HSPolarity);
706
707 /* Select the color coding for the host */
708 hdsi->Instance->LCOLCR &= ~DSI_LCOLCR_COLC;
709 hdsi->Instance->LCOLCR |= VidCfg->ColorCoding;
710
711 /* Select the color coding for the wrapper */
712 hdsi->Instance->WCFGR &= ~DSI_WCFGR_COLMUX;
713 hdsi->Instance->WCFGR |= ((VidCfg->ColorCoding)<<1U);
714
715 /* Enable/disable the loosely packed variant to 18-bit configuration */
716 if(VidCfg->ColorCoding == DSI_RGB666)
717 {
718 hdsi->Instance->LCOLCR &= ~DSI_LCOLCR_LPE;
719 hdsi->Instance->LCOLCR |= VidCfg->LooselyPacked;
720 }
721
722 /* Set the Horizontal Synchronization Active (HSA) in lane byte clock cycles */
723 hdsi->Instance->VHSACR &= ~DSI_VHSACR_HSA;
724 hdsi->Instance->VHSACR |= VidCfg->HorizontalSyncActive;
725
726 /* Set the Horizontal Back Porch (HBP) in lane byte clock cycles */
727 hdsi->Instance->VHBPCR &= ~DSI_VHBPCR_HBP;
728 hdsi->Instance->VHBPCR |= VidCfg->HorizontalBackPorch;
729
730 /* Set the total line time (HLINE=HSA+HBP+HACT+HFP) in lane byte clock cycles */
731 hdsi->Instance->VLCR &= ~DSI_VLCR_HLINE;
732 hdsi->Instance->VLCR |= VidCfg->HorizontalLine;
733
734 /* Set the Vertical Synchronization Active (VSA) */
735 hdsi->Instance->VVSACR &= ~DSI_VVSACR_VSA;
736 hdsi->Instance->VVSACR |= VidCfg->VerticalSyncActive;
737
738 /* Set the Vertical Back Porch (VBP)*/
739 hdsi->Instance->VVBPCR &= ~DSI_VVBPCR_VBP;
740 hdsi->Instance->VVBPCR |= VidCfg->VerticalBackPorch;
741
742 /* Set the Vertical Front Porch (VFP)*/
743 hdsi->Instance->VVFPCR &= ~DSI_VVFPCR_VFP;
744 hdsi->Instance->VVFPCR |= VidCfg->VerticalFrontPorch;
745
746 /* Set the Vertical Active period*/
747 hdsi->Instance->VVACR &= ~DSI_VVACR_VA;
748 hdsi->Instance->VVACR |= VidCfg->VerticalActive;
749
750 /* Configure the command transmission mode */
751 hdsi->Instance->VMCR &= ~DSI_VMCR_LPCE;
752 hdsi->Instance->VMCR |= VidCfg->LPCommandEnable;
753
754 /* Low power largest packet size */
755 hdsi->Instance->LPMCR &= ~DSI_LPMCR_LPSIZE;
756 hdsi->Instance->LPMCR |= ((VidCfg->LPLargestPacketSize)<<16U);
757
758 /* Low power VACT largest packet size */
759 hdsi->Instance->LPMCR &= ~DSI_LPMCR_VLPSIZE;
760 hdsi->Instance->LPMCR |= VidCfg->LPVACTLargestPacketSize;
761
762 /* Enable LP transition in HFP period */
763 hdsi->Instance->VMCR &= ~DSI_VMCR_LPHFPE;
764 hdsi->Instance->VMCR |= VidCfg->LPHorizontalFrontPorchEnable;
765
766 /* Enable LP transition in HBP period */
767 hdsi->Instance->VMCR &= ~DSI_VMCR_LPHBPE;
768 hdsi->Instance->VMCR |= VidCfg->LPHorizontalBackPorchEnable;
769
770 /* Enable LP transition in VACT period */
771 hdsi->Instance->VMCR &= ~DSI_VMCR_LPVAE;
772 hdsi->Instance->VMCR |= VidCfg->LPVerticalActiveEnable;
773
774 /* Enable LP transition in VFP period */
775 hdsi->Instance->VMCR &= ~DSI_VMCR_LPVFPE;
776 hdsi->Instance->VMCR |= VidCfg->LPVerticalFrontPorchEnable;
777
778 /* Enable LP transition in VBP period */
779 hdsi->Instance->VMCR &= ~DSI_VMCR_LPVBPE;
780 hdsi->Instance->VMCR |= VidCfg->LPVerticalBackPorchEnable;
781
782 /* Enable LP transition in vertical sync period */
783 hdsi->Instance->VMCR &= ~DSI_VMCR_LPVSAE;
784 hdsi->Instance->VMCR |= VidCfg->LPVerticalSyncActiveEnable;
785
786 /* Enable the request for an acknowledge response at the end of a frame */
787 hdsi->Instance->VMCR &= ~DSI_VMCR_FBTAAE;
788 hdsi->Instance->VMCR |= VidCfg->FrameBTAAcknowledgeEnable;
789
790 /* Process unlocked */
791 __HAL_UNLOCK(hdsi);
792
793 return HAL_OK;
794 }
795
796 /**
797 * @brief Select adapted command mode and configure the corresponding parameters
798 * @param hdsi pointer to a DSI_HandleTypeDef structure that contains
799 * the configuration information for the DSI.
800 * @param CmdCfg pointer to a DSI_CmdCfgTypeDef structure that contains
801 * the DSI command mode configuration parameters
802 * @retval HAL status
803 */
804 HAL_StatusTypeDef HAL_DSI_ConfigAdaptedCommandMode(DSI_HandleTypeDef *hdsi, DSI_CmdCfgTypeDef *CmdCfg)
805 {
806 /* Process locked */
807 __HAL_LOCK(hdsi);
808
809 /* Check the parameters */
810 assert_param(IS_DSI_COLOR_CODING(CmdCfg->ColorCoding));
811 assert_param(IS_DSI_TE_SOURCE(CmdCfg->TearingEffectSource));
812 assert_param(IS_DSI_TE_POLARITY(CmdCfg->TearingEffectPolarity));
813 assert_param(IS_DSI_AUTOMATIC_REFRESH(CmdCfg->AutomaticRefresh));
814 assert_param(IS_DSI_VS_POLARITY(CmdCfg->VSyncPol));
815 assert_param(IS_DSI_TE_ACK_REQUEST(CmdCfg->TEAcknowledgeRequest));
816 assert_param(IS_DSI_DE_POLARITY(CmdCfg->DEPolarity));
817 assert_param(IS_DSI_VSYNC_POLARITY(CmdCfg->VSPolarity));
818 assert_param(IS_DSI_HSYNC_POLARITY(CmdCfg->HSPolarity));
819
820 /* Select command mode by setting CMDM and DSIM bits */
821 hdsi->Instance->MCR |= DSI_MCR_CMDM;
822 hdsi->Instance->WCFGR &= ~DSI_WCFGR_DSIM;
823 hdsi->Instance->WCFGR |= DSI_WCFGR_DSIM;
824
825 /* Select the virtual channel for the LTDC interface traffic */
826 hdsi->Instance->LVCIDR &= ~DSI_LVCIDR_VCID;
827 hdsi->Instance->LVCIDR |= CmdCfg->VirtualChannelID;
828
829 /* Configure the polarity of control signals */
830 hdsi->Instance->LPCR &= ~(DSI_LPCR_DEP | DSI_LPCR_VSP | DSI_LPCR_HSP);
831 hdsi->Instance->LPCR |= (CmdCfg->DEPolarity | CmdCfg->VSPolarity | CmdCfg->HSPolarity);
832
833 /* Select the color coding for the host */
834 hdsi->Instance->LCOLCR &= ~DSI_LCOLCR_COLC;
835 hdsi->Instance->LCOLCR |= CmdCfg->ColorCoding;
836
837 /* Select the color coding for the wrapper */
838 hdsi->Instance->WCFGR &= ~DSI_WCFGR_COLMUX;
839 hdsi->Instance->WCFGR |= ((CmdCfg->ColorCoding)<<1U);
840
841 /* Configure the maximum allowed size for write memory command */
842 hdsi->Instance->LCCR &= ~DSI_LCCR_CMDSIZE;
843 hdsi->Instance->LCCR |= CmdCfg->CommandSize;
844
845 /* Configure the tearing effect source and polarity and select the refresh mode */
846 hdsi->Instance->WCFGR &= ~(DSI_WCFGR_TESRC | DSI_WCFGR_TEPOL | DSI_WCFGR_AR | DSI_WCFGR_VSPOL);
847 hdsi->Instance->WCFGR |= (CmdCfg->TearingEffectSource | CmdCfg->TearingEffectPolarity | CmdCfg->AutomaticRefresh | CmdCfg->VSyncPol);
848
849 /* Configure the tearing effect acknowledge request */
850 hdsi->Instance->CMCR &= ~DSI_CMCR_TEARE;
851 hdsi->Instance->CMCR |= CmdCfg->TEAcknowledgeRequest;
852
853 /* Enable the Tearing Effect interrupt */
854 __HAL_DSI_ENABLE_IT(hdsi, DSI_IT_TE);
855
856 /* Enable the End of Refresh interrupt */
857 __HAL_DSI_ENABLE_IT(hdsi, DSI_IT_ER);
858
859 /* Process unlocked */
860 __HAL_UNLOCK(hdsi);
861
862 return HAL_OK;
863 }
864
865 /**
866 * @brief Configure command transmission mode: High-speed or Low-power
867 * and enable/disable acknowledge request after packet transmission
868 * @param hdsi pointer to a DSI_HandleTypeDef structure that contains
869 * the configuration information for the DSI.
870 * @param LPCmd pointer to a DSI_LPCmdTypeDef structure that contains
871 * the DSI command transmission mode configuration parameters
872 * @retval HAL status
873 */
874 HAL_StatusTypeDef HAL_DSI_ConfigCommand(DSI_HandleTypeDef *hdsi, DSI_LPCmdTypeDef *LPCmd)
875 {
876 /* Process locked */
877 __HAL_LOCK(hdsi);
878
879 assert_param(IS_DSI_LP_GSW0P(LPCmd->LPGenShortWriteNoP));
880 assert_param(IS_DSI_LP_GSW1P(LPCmd->LPGenShortWriteOneP));
881 assert_param(IS_DSI_LP_GSW2P(LPCmd->LPGenShortWriteTwoP));
882 assert_param(IS_DSI_LP_GSR0P(LPCmd->LPGenShortReadNoP));
883 assert_param(IS_DSI_LP_GSR1P(LPCmd->LPGenShortReadOneP));
884 assert_param(IS_DSI_LP_GSR2P(LPCmd->LPGenShortReadTwoP));
885 assert_param(IS_DSI_LP_GLW(LPCmd->LPGenLongWrite));
886 assert_param(IS_DSI_LP_DSW0P(LPCmd->LPDcsShortWriteNoP));
887 assert_param(IS_DSI_LP_DSW1P(LPCmd->LPDcsShortWriteOneP));
888 assert_param(IS_DSI_LP_DSR0P(LPCmd->LPDcsShortReadNoP));
889 assert_param(IS_DSI_LP_DLW(LPCmd->LPDcsLongWrite));
890 assert_param(IS_DSI_LP_MRDP(LPCmd->LPMaxReadPacket));
891 assert_param(IS_DSI_ACK_REQUEST(LPCmd->AcknowledgeRequest));
892
893 /* Select High-speed or Low-power for command transmission */
894 hdsi->Instance->CMCR &= ~(DSI_CMCR_GSW0TX |\
895 DSI_CMCR_GSW1TX |\
896 DSI_CMCR_GSW2TX |\
897 DSI_CMCR_GSR0TX |\
898 DSI_CMCR_GSR1TX |\
899 DSI_CMCR_GSR2TX |\
900 DSI_CMCR_GLWTX |\
901 DSI_CMCR_DSW0TX |\
902 DSI_CMCR_DSW1TX |\
903 DSI_CMCR_DSR0TX |\
904 DSI_CMCR_DLWTX |\
905 DSI_CMCR_MRDPS);
906 hdsi->Instance->CMCR |= (LPCmd->LPGenShortWriteNoP |\
907 LPCmd->LPGenShortWriteOneP |\
908 LPCmd->LPGenShortWriteTwoP |\
909 LPCmd->LPGenShortReadNoP |\
910 LPCmd->LPGenShortReadOneP |\
911 LPCmd->LPGenShortReadTwoP |\
912 LPCmd->LPGenLongWrite |\
913 LPCmd->LPDcsShortWriteNoP |\
914 LPCmd->LPDcsShortWriteOneP |\
915 LPCmd->LPDcsShortReadNoP |\
916 LPCmd->LPDcsLongWrite |\
917 LPCmd->LPMaxReadPacket);
918
919 /* Configure the acknowledge request after each packet transmission */
920 hdsi->Instance->CMCR &= ~DSI_CMCR_ARE;
921 hdsi->Instance->CMCR |= LPCmd->AcknowledgeRequest;
922
923 /* Process unlocked */
924 __HAL_UNLOCK(hdsi);
925
926 return HAL_OK;
927 }
928
929 /**
930 * @brief Configure the flow control parameters
931 * @param hdsi pointer to a DSI_HandleTypeDef structure that contains
932 * the configuration information for the DSI.
933 * @param FlowControl flow control feature(s) to be enabled.
934 * This parameter can be any combination of @ref DSI_FlowControl.
935 * @retval HAL status
936 */
937 HAL_StatusTypeDef HAL_DSI_ConfigFlowControl(DSI_HandleTypeDef *hdsi, uint32_t FlowControl)
938 {
939 /* Process locked */
940 __HAL_LOCK(hdsi);
941
942 /* Check the parameters */
943 assert_param(IS_DSI_FLOW_CONTROL(FlowControl));
944
945 /* Set the DSI Host Protocol Configuration Register */
946 hdsi->Instance->PCR &= ~DSI_FLOW_CONTROL_ALL;
947 hdsi->Instance->PCR |= FlowControl;
948
949 /* Process unlocked */
950 __HAL_UNLOCK(hdsi);
951
952 return HAL_OK;
953 }
954
955 /**
956 * @brief Configure the DSI PHY timer parameters
957 * @param hdsi pointer to a DSI_HandleTypeDef structure that contains
958 * the configuration information for the DSI.
959 * @param PhyTimers DSI_PHY_TimerTypeDef structure that contains
960 * the DSI PHY timing parameters
961 * @retval HAL status
962 */
963 HAL_StatusTypeDef HAL_DSI_ConfigPhyTimer(DSI_HandleTypeDef *hdsi, DSI_PHY_TimerTypeDef *PhyTimers)
964 {
965 uint32_t maxTime;
966 /* Process locked */
967 __HAL_LOCK(hdsi);
968
969 maxTime = (PhyTimers->ClockLaneLP2HSTime > PhyTimers->ClockLaneHS2LPTime)? PhyTimers->ClockLaneLP2HSTime: PhyTimers->ClockLaneHS2LPTime;
970
971 /* Clock lane timer configuration */
972
973 /* In Automatic Clock Lane control mode, the DSI Host can turn off the clock lane between two
974 High-Speed transmission.
975 To do so, the DSI Host calculates the time required for the clock lane to change from HighSpeed
976 to Low-Power and from Low-Power to High-Speed.
977 This timings are configured by the HS2LP_TIME and LP2HS_TIME in the DSI Host Clock Lane Timer Configuration Register (DSI_CLTCR).
978 But the DSI Host is not calculating LP2HS_TIME + HS2LP_TIME but 2 x HS2LP_TIME.
979
980 Workaround : Configure HS2LP_TIME and LP2HS_TIME with the same value being the max of HS2LP_TIME or LP2HS_TIME.
981 */
982 hdsi->Instance->CLTCR &= ~(DSI_CLTCR_LP2HS_TIME | DSI_CLTCR_HS2LP_TIME);
983 hdsi->Instance->CLTCR |= (maxTime | ((maxTime)<<16U));
984
985 /* Data lane timer configuration */
986 hdsi->Instance->DLTCR &= ~(DSI_DLTCR_MRD_TIME | DSI_DLTCR_LP2HS_TIME | DSI_DLTCR_HS2LP_TIME);
987 hdsi->Instance->DLTCR |= (PhyTimers->DataLaneMaxReadTime | ((PhyTimers->DataLaneLP2HSTime)<<16U) | ((PhyTimers->DataLaneHS2LPTime)<<24U));
988
989 /* Configure the wait period to request HS transmission after a stop state */
990 hdsi->Instance->PCONFR &= ~DSI_PCONFR_SW_TIME;
991 hdsi->Instance->PCONFR |= ((PhyTimers->StopWaitTime)<<8U);
992
993 /* Process unlocked */
994 __HAL_UNLOCK(hdsi);
995
996 return HAL_OK;
997 }
998
999 /**
1000 * @brief Configure the DSI HOST timeout parameters
1001 * @param hdsi pointer to a DSI_HandleTypeDef structure that contains
1002 * the configuration information for the DSI.
1003 * @param HostTimeouts DSI_HOST_TimeoutTypeDef structure that contains
1004 * the DSI host timeout parameters
1005 * @retval HAL status
1006 */
1007 HAL_StatusTypeDef HAL_DSI_ConfigHostTimeouts(DSI_HandleTypeDef *hdsi, DSI_HOST_TimeoutTypeDef *HostTimeouts)
1008 {
1009 /* Process locked */
1010 __HAL_LOCK(hdsi);
1011
1012 /* Set the timeout clock division factor */
1013 hdsi->Instance->CCR &= ~DSI_CCR_TOCKDIV;
1014 hdsi->Instance->CCR |= ((HostTimeouts->TimeoutCkdiv)<<8U);
1015
1016 /* High-speed transmission timeout */
1017 hdsi->Instance->TCCR[0U] &= ~DSI_TCCR0_HSTX_TOCNT;
1018 hdsi->Instance->TCCR[0U] |= ((HostTimeouts->HighSpeedTransmissionTimeout)<<16U);
1019
1020 /* Low-power reception timeout */
1021 hdsi->Instance->TCCR[0U] &= ~DSI_TCCR0_LPRX_TOCNT;
1022 hdsi->Instance->TCCR[0U] |= HostTimeouts->LowPowerReceptionTimeout;
1023
1024 /* High-speed read timeout */
1025 hdsi->Instance->TCCR[1U] &= ~DSI_TCCR1_HSRD_TOCNT;
1026 hdsi->Instance->TCCR[1U] |= HostTimeouts->HighSpeedReadTimeout;
1027
1028 /* Low-power read timeout */
1029 hdsi->Instance->TCCR[2U] &= ~DSI_TCCR2_LPRD_TOCNT;
1030 hdsi->Instance->TCCR[2U] |= HostTimeouts->LowPowerReadTimeout;
1031
1032 /* High-speed write timeout */
1033 hdsi->Instance->TCCR[3U] &= ~DSI_TCCR3_HSWR_TOCNT;
1034 hdsi->Instance->TCCR[3U] |= HostTimeouts->HighSpeedWriteTimeout;
1035
1036 /* High-speed write presp mode */
1037 hdsi->Instance->TCCR[3U] &= ~DSI_TCCR3_PM;
1038 hdsi->Instance->TCCR[3U] |= HostTimeouts->HighSpeedWritePrespMode;
1039
1040 /* Low-speed write timeout */
1041 hdsi->Instance->TCCR[4U] &= ~DSI_TCCR4_LPWR_TOCNT;
1042 hdsi->Instance->TCCR[4U] |= HostTimeouts->LowPowerWriteTimeout;
1043
1044 /* BTA timeout */
1045 hdsi->Instance->TCCR[5U] &= ~DSI_TCCR5_BTA_TOCNT;
1046 hdsi->Instance->TCCR[5U] |= HostTimeouts->BTATimeout;
1047
1048 /* Process unlocked */
1049 __HAL_UNLOCK(hdsi);
1050
1051 return HAL_OK;
1052 }
1053
1054 /**
1055 * @brief Start the DSI module
1056 * @param hdsi pointer to a DSI_HandleTypeDef structure that contains
1057 * the configuration information for the DSI.
1058 * @retval HAL status
1059 */
1060 HAL_StatusTypeDef HAL_DSI_Start(DSI_HandleTypeDef *hdsi)
1061 {
1062 /* Process locked */
1063 __HAL_LOCK(hdsi);
1064
1065 /* Enable the DSI host */
1066 __HAL_DSI_ENABLE(hdsi);
1067
1068 /* Enable the DSI wrapper */
1069 __HAL_DSI_WRAPPER_ENABLE(hdsi);
1070
1071 /* Process unlocked */
1072 __HAL_UNLOCK(hdsi);
1073
1074 return HAL_OK;
1075 }
1076
1077 /**
1078 * @brief Stop the DSI module
1079 * @param hdsi pointer to a DSI_HandleTypeDef structure that contains
1080 * the configuration information for the DSI.
1081 * @retval HAL status
1082 */
1083 HAL_StatusTypeDef HAL_DSI_Stop(DSI_HandleTypeDef *hdsi)
1084 {
1085 /* Process locked */
1086 __HAL_LOCK(hdsi);
1087
1088 /* Disable the DSI host */
1089 __HAL_DSI_DISABLE(hdsi);
1090
1091 /* Disable the DSI wrapper */
1092 __HAL_DSI_WRAPPER_DISABLE(hdsi);
1093
1094 /* Process unlocked */
1095 __HAL_UNLOCK(hdsi);
1096
1097 return HAL_OK;
1098 }
1099
1100 /**
1101 * @brief Refresh the display in command mode
1102 * @param hdsi pointer to a DSI_HandleTypeDef structure that contains
1103 * the configuration information for the DSI.
1104 * @retval HAL status
1105 */
1106 HAL_StatusTypeDef HAL_DSI_Refresh(DSI_HandleTypeDef *hdsi)
1107 {
1108 /* Process locked */
1109 __HAL_LOCK(hdsi);
1110
1111 /* Update the display */
1112 hdsi->Instance->WCR |= DSI_WCR_LTDCEN;
1113
1114 /* Process unlocked */
1115 __HAL_UNLOCK(hdsi);
1116
1117 return HAL_OK;
1118 }
1119
1120 /**
1121 * @brief Controls the display color mode in Video mode
1122 * @param hdsi pointer to a DSI_HandleTypeDef structure that contains
1123 * the configuration information for the DSI.
1124 * @param ColorMode Color mode (full or 8-colors).
1125 * This parameter can be any value of @ref DSI_Color_Mode
1126 * @retval HAL status
1127 */
1128 HAL_StatusTypeDef HAL_DSI_ColorMode(DSI_HandleTypeDef *hdsi, uint32_t ColorMode)
1129 {
1130 /* Process locked */
1131 __HAL_LOCK(hdsi);
1132
1133 /* Check the parameters */
1134 assert_param(IS_DSI_COLOR_MODE(ColorMode));
1135
1136 /* Update the display color mode */
1137 hdsi->Instance->WCR &= ~DSI_WCR_COLM;
1138 hdsi->Instance->WCR |= ColorMode;
1139
1140 /* Process unlocked */
1141 __HAL_UNLOCK(hdsi);
1142
1143 return HAL_OK;
1144 }
1145
1146 /**
1147 * @brief Control the display shutdown in Video mode
1148 * @param hdsi pointer to a DSI_HandleTypeDef structure that contains
1149 * the configuration information for the DSI.
1150 * @param Shutdown Shut-down (Display-ON or Display-OFF).
1151 * This parameter can be any value of @ref DSI_ShutDown
1152 * @retval HAL status
1153 */
1154 HAL_StatusTypeDef HAL_DSI_Shutdown(DSI_HandleTypeDef *hdsi, uint32_t Shutdown)
1155 {
1156 /* Process locked */
1157 __HAL_LOCK(hdsi);
1158
1159 /* Check the parameters */
1160 assert_param(IS_DSI_SHUT_DOWN(Shutdown));
1161
1162 /* Update the display Shutdown */
1163 hdsi->Instance->WCR &= ~DSI_WCR_SHTDN;
1164 hdsi->Instance->WCR |= Shutdown;
1165
1166 /* Process unlocked */
1167 __HAL_UNLOCK(hdsi);
1168
1169 return HAL_OK;
1170 }
1171
1172 /**
1173 * @brief write short DCS or short Generic command
1174 * @param hdsi pointer to a DSI_HandleTypeDef structure that contains
1175 * the configuration information for the DSI.
1176 * @param ChannelID Virtual channel ID.
1177 * @param Mode DSI short packet data type.
1178 * This parameter can be any value of @ref DSI_SHORT_WRITE_PKT_Data_Type.
1179 * @param Param1 DSC command or first generic parameter.
1180 * This parameter can be any value of @ref DSI_DCS_Command or a
1181 * generic command code.
1182 * @param Param2 DSC parameter or second generic parameter.
1183 * @retval HAL status
1184 */
1185 HAL_StatusTypeDef HAL_DSI_ShortWrite(DSI_HandleTypeDef *hdsi,
1186 uint32_t ChannelID,
1187 uint32_t Mode,
1188 uint32_t Param1,
1189 uint32_t Param2)
1190 {
1191 uint32_t tickstart;
1192
1193 /* Process locked */
1194 __HAL_LOCK(hdsi);
1195
1196 /* Check the parameters */
1197 assert_param(IS_DSI_SHORT_WRITE_PACKET_TYPE(Mode));
1198
1199 /* Get tick */
1200 tickstart = HAL_GetTick();
1201
1202 /* Wait for Command FIFO Empty */
1203 while((hdsi->Instance->GPSR & DSI_GPSR_CMDFE) == 0U)
1204 {
1205 /* Check for the Timeout */
1206 if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE)
1207 {
1208 /* Process Unlocked */
1209 __HAL_UNLOCK(hdsi);
1210
1211 return HAL_TIMEOUT;
1212 }
1213 }
1214
1215 /* Configure the packet to send a short DCS command with 0 or 1 parameter */
1216 DSI_ConfigPacketHeader(hdsi->Instance,
1217 ChannelID,
1218 Mode,
1219 Param1,
1220 Param2);
1221
1222 /* Process unlocked */
1223 __HAL_UNLOCK(hdsi);
1224
1225 return HAL_OK;
1226 }
1227
1228 /**
1229 * @brief write long DCS or long Generic command
1230 * @param hdsi pointer to a DSI_HandleTypeDef structure that contains
1231 * the configuration information for the DSI.
1232 * @param ChannelID Virtual channel ID.
1233 * @param Mode DSI long packet data type.
1234 * This parameter can be any value of @ref DSI_LONG_WRITE_PKT_Data_Type.
1235 * @param NbParams Number of parameters.
1236 * @param Param1 DSC command or first generic parameter.
1237 * This parameter can be any value of @ref DSI_DCS_Command or a
1238 * generic command code
1239 * @param ParametersTable Pointer to parameter values table.
1240 * @retval HAL status
1241 */
1242 HAL_StatusTypeDef HAL_DSI_LongWrite(DSI_HandleTypeDef *hdsi,
1243 uint32_t ChannelID,
1244 uint32_t Mode,
1245 uint32_t NbParams,
1246 uint32_t Param1,
1247 uint8_t* ParametersTable)
1248 {
1249 uint32_t uicounter, nbBytes, count;
1250 uint32_t tickstart;
1251 uint32_t fifoword;
1252 uint8_t* pparams = ParametersTable;
1253
1254 /* Process locked */
1255 __HAL_LOCK(hdsi);
1256
1257 /* Check the parameters */
1258 assert_param(IS_DSI_LONG_WRITE_PACKET_TYPE(Mode));
1259
1260 /* Get tick */
1261 tickstart = HAL_GetTick();
1262
1263 /* Wait for Command FIFO Empty */
1264 while((hdsi->Instance->GPSR & DSI_GPSR_CMDFE) == RESET)
1265 {
1266 /* Check for the Timeout */
1267 if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE)
1268 {
1269 /* Process Unlocked */
1270 __HAL_UNLOCK(hdsi);
1271
1272 return HAL_TIMEOUT;
1273 }
1274 }
1275
1276 /* Set the DCS code on payload byte 1, and the other parameters on the write FIFO command*/
1277 fifoword = Param1;
1278 nbBytes = (NbParams < 3U) ? NbParams : 3U;
1279
1280 for(count = 0U; count < nbBytes; count++)
1281 {
1282 fifoword |= (((uint32_t)(*(pparams + count))) << (8U + (8U*count)));
1283 }
1284 hdsi->Instance->GPDR = fifoword;
1285
1286 uicounter = NbParams - nbBytes;
1287 pparams += nbBytes;
1288 /* Set the Next parameters on the write FIFO command*/
1289 while(uicounter != 0U)
1290 {
1291 nbBytes = (uicounter < 4U) ? uicounter : 4U;
1292 fifoword = 0U;
1293 for(count = 0U; count < nbBytes; count++)
1294 {
1295 fifoword |= (((uint32_t)(*(pparams + count))) << (8U*count));
1296 }
1297 hdsi->Instance->GPDR = fifoword;
1298
1299 uicounter -= nbBytes;
1300 pparams += nbBytes;
1301 }
1302
1303 /* Configure the packet to send a long DCS command */
1304 DSI_ConfigPacketHeader(hdsi->Instance,
1305 ChannelID,
1306 Mode,
1307 ((NbParams+1U)&0x00FFU),
1308 (((NbParams+1U)&0xFF00U)>>8U));
1309
1310 /* Process unlocked */
1311 __HAL_UNLOCK(hdsi);
1312
1313 return HAL_OK;
1314 }
1315
1316 /**
1317 * @brief Read command (DCS or generic)
1318 * @param hdsi pointer to a DSI_HandleTypeDef structure that contains
1319 * the configuration information for the DSI.
1320 * @param ChannelNbr Virtual channel ID
1321 * @param Array pointer to a buffer to store the payload of a read back operation.
1322 * @param Size Data size to be read (in byte).
1323 * @param Mode DSI read packet data type.
1324 * This parameter can be any value of @ref DSI_SHORT_READ_PKT_Data_Type.
1325 * @param DCSCmd DCS get/read command.
1326 * @param ParametersTable Pointer to parameter values table.
1327 * @retval HAL status
1328 */
1329 HAL_StatusTypeDef HAL_DSI_Read(DSI_HandleTypeDef *hdsi,
1330 uint32_t ChannelNbr,
1331 uint8_t* Array,
1332 uint32_t Size,
1333 uint32_t Mode,
1334 uint32_t DCSCmd,
1335 uint8_t* ParametersTable)
1336 {
1337 uint32_t tickstart;
1338 uint8_t* pdata = Array;
1339 uint32_t datasize = Size;
1340
1341 /* Process locked */
1342 __HAL_LOCK(hdsi);
1343
1344 /* Check the parameters */
1345 assert_param(IS_DSI_READ_PACKET_TYPE(Mode));
1346
1347 if(datasize > 2U)
1348 {
1349 /* set max return packet size */
1350 if (HAL_DSI_ShortWrite(hdsi, ChannelNbr, DSI_MAX_RETURN_PKT_SIZE, ((datasize)&0xFFU), (((datasize)>>8U)&0xFFU)) != HAL_OK)
1351 {
1352 /* Process Unlocked */
1353 __HAL_UNLOCK(hdsi);
1354
1355 return HAL_ERROR;
1356 }
1357 }
1358
1359 /* Configure the packet to read command */
1360 if (Mode == DSI_DCS_SHORT_PKT_READ)
1361 {
1362 DSI_ConfigPacketHeader(hdsi->Instance, ChannelNbr, Mode, DCSCmd, 0U);
1363 }
1364 else if (Mode == DSI_GEN_SHORT_PKT_READ_P0)
1365 {
1366 DSI_ConfigPacketHeader(hdsi->Instance, ChannelNbr, Mode, 0U, 0U);
1367 }
1368 else if (Mode == DSI_GEN_SHORT_PKT_READ_P1)
1369 {
1370 DSI_ConfigPacketHeader(hdsi->Instance, ChannelNbr, Mode, ParametersTable[0U], 0U);
1371 }
1372 else if (Mode == DSI_GEN_SHORT_PKT_READ_P2)
1373 {
1374 DSI_ConfigPacketHeader(hdsi->Instance, ChannelNbr, Mode, ParametersTable[0U], ParametersTable[1U]);
1375 }
1376 else
1377 {
1378 /* Process Unlocked */
1379 __HAL_UNLOCK(hdsi);
1380
1381 return HAL_ERROR;
1382 }
1383
1384 /* Get tick */
1385 tickstart = HAL_GetTick();
1386
1387 /* Check that the payload read FIFO is not empty */
1388 while((hdsi->Instance->GPSR & DSI_GPSR_PRDFE) == DSI_GPSR_PRDFE)
1389 {
1390 /* Check for the Timeout */
1391 if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE)
1392 {
1393 /* Process Unlocked */
1394 __HAL_UNLOCK(hdsi);
1395
1396 return HAL_TIMEOUT;
1397 }
1398 }
1399
1400 /* Get the first byte */
1401 *((uint32_t *)pdata) = (hdsi->Instance->GPDR);
1402 if (datasize > 4U)
1403 {
1404 datasize -= 4U;
1405 pdata += 4U;
1406 }
1407 else
1408 {
1409 /* Process unlocked */
1410 __HAL_UNLOCK(hdsi);
1411
1412 return HAL_OK;
1413 }
1414
1415 /* Get tick */
1416 tickstart = HAL_GetTick();
1417
1418 /* Get the remaining bytes if any */
1419 while(((int)(datasize)) > 0)
1420 {
1421 if((hdsi->Instance->GPSR & DSI_GPSR_PRDFE) == 0U)
1422 {
1423 *((uint32_t *)pdata) = (hdsi->Instance->GPDR);
1424 datasize -= 4U;
1425 pdata += 4U;
1426 }
1427
1428 /* Check for the Timeout */
1429 if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE)
1430 {
1431 /* Process Unlocked */
1432 __HAL_UNLOCK(hdsi);
1433
1434 return HAL_TIMEOUT;
1435 }
1436 }
1437
1438 /* Process unlocked */
1439 __HAL_UNLOCK(hdsi);
1440
1441 return HAL_OK;
1442 }
1443
1444 /**
1445 * @brief Enter the ULPM (Ultra Low Power Mode) with the D-PHY PLL running
1446 * (only data lanes are in ULPM)
1447 * @param hdsi pointer to a DSI_HandleTypeDef structure that contains
1448 * the configuration information for the DSI.
1449 * @retval HAL status
1450 */
1451 HAL_StatusTypeDef HAL_DSI_EnterULPMData(DSI_HandleTypeDef *hdsi)
1452 {
1453 uint32_t tickstart;
1454
1455 /* Process locked */
1456 __HAL_LOCK(hdsi);
1457
1458 /* ULPS Request on Data Lanes */
1459 hdsi->Instance->PUCR |= DSI_PUCR_URDL;
1460
1461 /* Get tick */
1462 tickstart = HAL_GetTick();
1463
1464 /* Wait until the D-PHY active lanes enter into ULPM */
1465 if((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_ONE_DATA_LANE)
1466 {
1467 while((hdsi->Instance->PSR & DSI_PSR_UAN0) != RESET)
1468 {
1469 /* Check for the Timeout */
1470 if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE)
1471 {
1472 /* Process Unlocked */
1473 __HAL_UNLOCK(hdsi);
1474
1475 return HAL_TIMEOUT;
1476 }
1477 }
1478 }
1479 else if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_TWO_DATA_LANES)
1480 {
1481 while((hdsi->Instance->PSR & (DSI_PSR_UAN0 | DSI_PSR_UAN1)) != RESET)
1482 {
1483 /* Check for the Timeout */
1484 if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE)
1485 {
1486 /* Process Unlocked */
1487 __HAL_UNLOCK(hdsi);
1488
1489 return HAL_TIMEOUT;
1490 }
1491 }
1492 }
1493 else
1494 {
1495 /* Process unlocked */
1496 __HAL_UNLOCK(hdsi);
1497
1498 return HAL_ERROR;
1499 }
1500
1501 /* Process unlocked */
1502 __HAL_UNLOCK(hdsi);
1503
1504 return HAL_OK;
1505 }
1506
1507 /**
1508 * @brief Exit the ULPM (Ultra Low Power Mode) with the D-PHY PLL running
1509 * (only data lanes are in ULPM)
1510 * @param hdsi pointer to a DSI_HandleTypeDef structure that contains
1511 * the configuration information for the DSI.
1512 * @retval HAL status
1513 */
1514 HAL_StatusTypeDef HAL_DSI_ExitULPMData(DSI_HandleTypeDef *hdsi)
1515 {
1516 uint32_t tickstart;
1517
1518 /* Process locked */
1519 __HAL_LOCK(hdsi);
1520
1521 /* Exit ULPS on Data Lanes */
1522 hdsi->Instance->PUCR |= DSI_PUCR_UEDL;
1523
1524 /* Get tick */
1525 tickstart = HAL_GetTick();
1526
1527 /* Wait until all active lanes exit ULPM */
1528 if((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_ONE_DATA_LANE)
1529 {
1530 while((hdsi->Instance->PSR & DSI_PSR_UAN0) != DSI_PSR_UAN0)
1531 {
1532 /* Check for the Timeout */
1533 if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE)
1534 {
1535 /* Process Unlocked */
1536 __HAL_UNLOCK(hdsi);
1537
1538 return HAL_TIMEOUT;
1539 }
1540 }
1541 }
1542 else if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_TWO_DATA_LANES)
1543 {
1544 while((hdsi->Instance->PSR & (DSI_PSR_UAN0 | DSI_PSR_UAN1)) != (DSI_PSR_UAN0 | DSI_PSR_UAN1))
1545 {
1546 /* Check for the Timeout */
1547 if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE)
1548 {
1549 /* Process Unlocked */
1550 __HAL_UNLOCK(hdsi);
1551
1552 return HAL_TIMEOUT;
1553 }
1554 }
1555 }
1556 else
1557 {
1558 /* Process unlocked */
1559 __HAL_UNLOCK(hdsi);
1560
1561 return HAL_ERROR;
1562 }
1563
1564 /* wait for 1 ms*/
1565 HAL_Delay(1U);
1566
1567 /* De-assert the ULPM requests and the ULPM exit bits */
1568 hdsi->Instance->PUCR = 0U;
1569
1570 /* Process unlocked */
1571 __HAL_UNLOCK(hdsi);
1572
1573 return HAL_OK;
1574 }
1575
1576 /**
1577 * @brief Enter the ULPM (Ultra Low Power Mode) with the D-PHY PLL turned off
1578 * (both data and clock lanes are in ULPM)
1579 * @param hdsi pointer to a DSI_HandleTypeDef structure that contains
1580 * the configuration information for the DSI.
1581 * @retval HAL status
1582 */
1583 HAL_StatusTypeDef HAL_DSI_EnterULPM(DSI_HandleTypeDef *hdsi)
1584 {
1585 uint32_t tickstart;
1586
1587 /* Process locked */
1588 __HAL_LOCK(hdsi);
1589
1590 /* Clock lane configuration: no more HS request */
1591 hdsi->Instance->CLCR &= ~DSI_CLCR_DPCC;
1592
1593 /* Use system PLL as byte lane clock source before stopping DSIPHY clock source */
1594 __HAL_RCC_DSI_CONFIG(RCC_DSICLKSOURCE_PLLR);
1595
1596 /* ULPS Request on Clock and Data Lanes */
1597 hdsi->Instance->PUCR |= (DSI_PUCR_URCL | DSI_PUCR_URDL);
1598
1599 /* Get tick */
1600 tickstart = HAL_GetTick();
1601
1602 /* Wait until all active lanes exit ULPM */
1603 if((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_ONE_DATA_LANE)
1604 {
1605 while((hdsi->Instance->PSR & (DSI_PSR_UAN0 | DSI_PSR_UANC)) != RESET)
1606 {
1607 /* Check for the Timeout */
1608 if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE)
1609 {
1610 /* Process Unlocked */
1611 __HAL_UNLOCK(hdsi);
1612
1613 return HAL_TIMEOUT;
1614 }
1615 }
1616 }
1617 else if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_TWO_DATA_LANES)
1618 {
1619 while((hdsi->Instance->PSR & (DSI_PSR_UAN0 | DSI_PSR_UAN1 | DSI_PSR_UANC)) != RESET)
1620 {
1621 /* Check for the Timeout */
1622 if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE)
1623 {
1624 /* Process Unlocked */
1625 __HAL_UNLOCK(hdsi);
1626
1627 return HAL_TIMEOUT;
1628 }
1629 }
1630 }
1631 else
1632 {
1633 /* Process unlocked */
1634 __HAL_UNLOCK(hdsi);
1635
1636 return HAL_ERROR;
1637 }
1638
1639 /* Turn off the DSI PLL */
1640 __HAL_DSI_PLL_DISABLE(hdsi);
1641
1642 /* Process unlocked */
1643 __HAL_UNLOCK(hdsi);
1644
1645 return HAL_OK;
1646 }
1647
1648 /**
1649 * @brief Exit the ULPM (Ultra Low Power Mode) with the D-PHY PLL turned off
1650 * (both data and clock lanes are in ULPM)
1651 * @param hdsi pointer to a DSI_HandleTypeDef structure that contains
1652 * the configuration information for the DSI.
1653 * @retval HAL status
1654 */
1655 HAL_StatusTypeDef HAL_DSI_ExitULPM(DSI_HandleTypeDef *hdsi)
1656 {
1657 uint32_t tickstart;
1658
1659 /* Process locked */
1660 __HAL_LOCK(hdsi);
1661
1662 /* Turn on the DSI PLL */
1663 __HAL_DSI_PLL_ENABLE(hdsi);
1664
1665 /* Get tick */
1666 tickstart = HAL_GetTick();
1667
1668 /* Wait for the lock of the PLL */
1669 while(__HAL_DSI_GET_FLAG(hdsi, DSI_FLAG_PLLLS) == RESET)
1670 {
1671 /* Check for the Timeout */
1672 if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE)
1673 {
1674 /* Process Unlocked */
1675 __HAL_UNLOCK(hdsi);
1676
1677 return HAL_TIMEOUT;
1678 }
1679 }
1680
1681 /* Exit ULPS on Clock and Data Lanes */
1682 hdsi->Instance->PUCR |= (DSI_PUCR_UECL | DSI_PUCR_UEDL);
1683
1684 /* Get tick */
1685 tickstart = HAL_GetTick();
1686
1687 /* Wait until all active lanes exit ULPM */
1688 if((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_ONE_DATA_LANE)
1689 {
1690 while((hdsi->Instance->PSR & (DSI_PSR_UAN0 | DSI_PSR_UANC)) != (DSI_PSR_UAN0 | DSI_PSR_UANC))
1691 {
1692 /* Check for the Timeout */
1693 if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE)
1694 {
1695 /* Process Unlocked */
1696 __HAL_UNLOCK(hdsi);
1697
1698 return HAL_TIMEOUT;
1699 }
1700 }
1701 }
1702 else if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_TWO_DATA_LANES)
1703 {
1704 while((hdsi->Instance->PSR & (DSI_PSR_UAN0 | DSI_PSR_UAN1 | DSI_PSR_UANC)) != (DSI_PSR_UAN0 | DSI_PSR_UAN1 | DSI_PSR_UANC))
1705 {
1706 /* Check for the Timeout */
1707 if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE)
1708 {
1709 /* Process Unlocked */
1710 __HAL_UNLOCK(hdsi);
1711
1712 return HAL_TIMEOUT;
1713 }
1714 }
1715 }
1716 else
1717 {
1718 /* Process unlocked */
1719 __HAL_UNLOCK(hdsi);
1720
1721 return HAL_ERROR;
1722 }
1723
1724 /* wait for 1 ms */
1725 HAL_Delay(1U);
1726
1727 /* De-assert the ULPM requests and the ULPM exit bits */
1728 hdsi->Instance->PUCR = 0U;
1729
1730 /* Switch the lanbyteclock source in the RCC from system PLL to D-PHY */
1731 __HAL_RCC_DSI_CONFIG(RCC_DSICLKSOURCE_DSIPHY);
1732
1733 /* Restore clock lane configuration to HS */
1734 hdsi->Instance->CLCR |= DSI_CLCR_DPCC;
1735
1736 /* Process unlocked */
1737 __HAL_UNLOCK(hdsi);
1738
1739 return HAL_OK;
1740 }
1741
1742 /**
1743 * @brief Start test pattern generation
1744 * @param hdsi pointer to a DSI_HandleTypeDef structure that contains
1745 * the configuration information for the DSI.
1746 * @param Mode Pattern generator mode
1747 * This parameter can be one of the following values:
1748 * 0 : Color bars (horizontal or vertical)
1749 * 1 : BER pattern (vertical only)
1750 * @param Orientation Pattern generator orientation
1751 * This parameter can be one of the following values:
1752 * 0 : Vertical color bars
1753 * 1 : Horizontal color bars
1754 * @retval HAL status
1755 */
1756 HAL_StatusTypeDef HAL_DSI_PatternGeneratorStart(DSI_HandleTypeDef *hdsi, uint32_t Mode, uint32_t Orientation)
1757 {
1758 /* Process locked */
1759 __HAL_LOCK(hdsi);
1760
1761 /* Configure pattern generator mode and orientation */
1762 hdsi->Instance->VMCR &= ~(DSI_VMCR_PGM | DSI_VMCR_PGO);
1763 hdsi->Instance->VMCR |= ((Mode<<20U) | (Orientation<<24U));
1764
1765 /* Enable pattern generator by setting PGE bit */
1766 hdsi->Instance->VMCR |= DSI_VMCR_PGE;
1767
1768 /* Process unlocked */
1769 __HAL_UNLOCK(hdsi);
1770
1771 return HAL_OK;
1772 }
1773
1774 /**
1775 * @brief Stop test pattern generation
1776 * @param hdsi pointer to a DSI_HandleTypeDef structure that contains
1777 * the configuration information for the DSI.
1778 * @retval HAL status
1779 */
1780 HAL_StatusTypeDef HAL_DSI_PatternGeneratorStop(DSI_HandleTypeDef *hdsi)
1781 {
1782 /* Process locked */
1783 __HAL_LOCK(hdsi);
1784
1785 /* Disable pattern generator by clearing PGE bit */
1786 hdsi->Instance->VMCR &= ~DSI_VMCR_PGE;
1787
1788 /* Process unlocked */
1789 __HAL_UNLOCK(hdsi);
1790
1791 return HAL_OK;
1792 }
1793
1794 /**
1795 * @brief Set Slew-Rate And Delay Tuning
1796 * @param hdsi pointer to a DSI_HandleTypeDef structure that contains
1797 * the configuration information for the DSI.
1798 * @param CommDelay Communication delay to be adjusted.
1799 * This parameter can be any value of @ref DSI_Communication_Delay
1800 * @param Lane select between clock or data lanes.
1801 * This parameter can be any value of @ref DSI_Lane_Group
1802 * @param Value Custom value of the slew-rate or delay
1803 * @retval HAL status
1804 */
1805 HAL_StatusTypeDef HAL_DSI_SetSlewRateAndDelayTuning(DSI_HandleTypeDef *hdsi, uint32_t CommDelay, uint32_t Lane, uint32_t Value)
1806 {
1807 /* Process locked */
1808 __HAL_LOCK(hdsi);
1809
1810 /* Check function parameters */
1811 assert_param(IS_DSI_COMMUNICATION_DELAY(CommDelay));
1812 assert_param(IS_DSI_LANE_GROUP(Lane));
1813
1814 switch(CommDelay)
1815 {
1816 case DSI_SLEW_RATE_HSTX:
1817 if(Lane == DSI_CLOCK_LANE)
1818 {
1819 /* High-Speed Transmission Slew Rate Control on Clock Lane */
1820 hdsi->Instance->WPCR[1U] &= ~DSI_WPCR1_HSTXSRCCL;
1821 hdsi->Instance->WPCR[1U] |= Value<<16U;
1822 }
1823 else if(Lane == DSI_DATA_LANES)
1824 {
1825 /* High-Speed Transmission Slew Rate Control on Data Lanes */
1826 hdsi->Instance->WPCR[1U] &= ~DSI_WPCR1_HSTXSRCDL;
1827 hdsi->Instance->WPCR[1U] |= Value<<18U;
1828 }
1829 else
1830 {
1831 /* Process unlocked */
1832 __HAL_UNLOCK(hdsi);
1833
1834 return HAL_ERROR;
1835 }
1836 break;
1837 case DSI_SLEW_RATE_LPTX:
1838 if(Lane == DSI_CLOCK_LANE)
1839 {
1840 /* Low-Power transmission Slew Rate Compensation on Clock Lane */
1841 hdsi->Instance->WPCR[1U] &= ~DSI_WPCR1_LPSRCCL;
1842 hdsi->Instance->WPCR[1U] |= Value<<6U;
1843 }
1844 else if(Lane == DSI_DATA_LANES)
1845 {
1846 /* Low-Power transmission Slew Rate Compensation on Data Lanes */
1847 hdsi->Instance->WPCR[1U] &= ~DSI_WPCR1_LPSRCDL;
1848 hdsi->Instance->WPCR[1U] |= Value<<8U;
1849 }
1850 else
1851 {
1852 /* Process unlocked */
1853 __HAL_UNLOCK(hdsi);
1854
1855 return HAL_ERROR;
1856 }
1857 break;
1858 case DSI_HS_DELAY:
1859 if(Lane == DSI_CLOCK_LANE)
1860 {
1861 /* High-Speed Transmission Delay on Clock Lane */
1862 hdsi->Instance->WPCR[1U] &= ~DSI_WPCR1_HSTXDCL;
1863 hdsi->Instance->WPCR[1U] |= Value;
1864 }
1865 else if(Lane == DSI_DATA_LANES)
1866 {
1867 /* High-Speed Transmission Delay on Data Lanes */
1868 hdsi->Instance->WPCR[1U] &= ~DSI_WPCR1_HSTXDDL;
1869 hdsi->Instance->WPCR[1U] |= Value<<2U;
1870 }
1871 else
1872 {
1873 /* Process unlocked */
1874 __HAL_UNLOCK(hdsi);
1875
1876 return HAL_ERROR;
1877 }
1878 break;
1879 default:
1880 break;
1881 }
1882
1883 /* Process unlocked */
1884 __HAL_UNLOCK(hdsi);
1885
1886 return HAL_OK;
1887 }
1888
1889 /**
1890 * @brief Low-Power Reception Filter Tuning
1891 * @param hdsi pointer to a DSI_HandleTypeDef structure that contains
1892 * the configuration information for the DSI.
1893 * @param Frequency cutoff frequency of low-pass filter at the input of LPRX
1894 * @retval HAL status
1895 */
1896 HAL_StatusTypeDef HAL_DSI_SetLowPowerRXFilter(DSI_HandleTypeDef *hdsi, uint32_t Frequency)
1897 {
1898 /* Process locked */
1899 __HAL_LOCK(hdsi);
1900
1901 /* Low-Power RX low-pass Filtering Tuning */
1902 hdsi->Instance->WPCR[1U] &= ~DSI_WPCR1_LPRXFT;
1903 hdsi->Instance->WPCR[1U] |= Frequency<<25U;
1904
1905 /* Process unlocked */
1906 __HAL_UNLOCK(hdsi);
1907
1908 return HAL_OK;
1909 }
1910
1911 /**
1912 * @brief Activate an additional current path on all lanes to meet the SDDTx parameter
1913 * defined in the MIPI D-PHY specification
1914 * @param hdsi pointer to a DSI_HandleTypeDef structure that contains
1915 * the configuration information for the DSI.
1916 * @param State ENABLE or DISABLE
1917 * @retval HAL status
1918 */
1919 HAL_StatusTypeDef HAL_DSI_SetSDD(DSI_HandleTypeDef *hdsi, FunctionalState State)
1920 {
1921 /* Process locked */
1922 __HAL_LOCK(hdsi);
1923
1924 /* Check function parameters */
1925 assert_param(IS_FUNCTIONAL_STATE(State));
1926
1927 /* Activate/Disactivate additional current path on all lanes */
1928 hdsi->Instance->WPCR[1U] &= ~DSI_WPCR1_SDDC;
1929 hdsi->Instance->WPCR[1U] |= ((uint32_t)State << 12U);
1930
1931 /* Process unlocked */
1932 __HAL_UNLOCK(hdsi);
1933
1934 return HAL_OK;
1935 }
1936
1937 /**
1938 * @brief Custom lane pins configuration
1939 * @param hdsi pointer to a DSI_HandleTypeDef structure that contains
1940 * the configuration information for the DSI.
1941 * @param CustomLane Function to be applyed on selected lane.
1942 * This parameter can be any value of @ref DSI_CustomLane
1943 * @param Lane select between clock or data lane 0 or data lane 1.
1944 * This parameter can be any value of @ref DSI_Lane_Select
1945 * @param State ENABLE or DISABLE
1946 * @retval HAL status
1947 */
1948 HAL_StatusTypeDef HAL_DSI_SetLanePinsConfiguration(DSI_HandleTypeDef *hdsi, uint32_t CustomLane, uint32_t Lane, FunctionalState State)
1949 {
1950 /* Process locked */
1951 __HAL_LOCK(hdsi);
1952
1953 /* Check function parameters */
1954 assert_param(IS_DSI_CUSTOM_LANE(CustomLane));
1955 assert_param(IS_DSI_LANE(Lane));
1956 assert_param(IS_FUNCTIONAL_STATE(State));
1957
1958 switch(CustomLane)
1959 {
1960 case DSI_SWAP_LANE_PINS:
1961 if(Lane == DSI_CLK_LANE)
1962 {
1963 /* Swap pins on clock lane */
1964 hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_SWCL;
1965 hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 6U);
1966 }
1967 else if(Lane == DSI_DATA_LANE0)
1968 {
1969 /* Swap pins on data lane 0 */
1970 hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_SWDL0;
1971 hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 7U);
1972 }
1973 else if(Lane == DSI_DATA_LANE1)
1974 {
1975 /* Swap pins on data lane 1 */
1976 hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_SWDL1;
1977 hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 8U);
1978 }
1979 else
1980 {
1981 /* Process unlocked */
1982 __HAL_UNLOCK(hdsi);
1983
1984 return HAL_ERROR;
1985 }
1986 break;
1987 case DSI_INVERT_HS_SIGNAL:
1988 if(Lane == DSI_CLK_LANE)
1989 {
1990 /* Invert HS signal on clock lane */
1991 hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_HSICL;
1992 hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 9U);
1993 }
1994 else if(Lane == DSI_DATA_LANE0)
1995 {
1996 /* Invert HS signal on data lane 0 */
1997 hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_HSIDL0;
1998 hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 10U);
1999 }
2000 else if(Lane == DSI_DATA_LANE1)
2001 {
2002 /* Invert HS signal on data lane 1 */
2003 hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_HSIDL1;
2004 hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 11U);
2005 }
2006 else
2007 {
2008 /* Process unlocked */
2009 __HAL_UNLOCK(hdsi);
2010
2011 return HAL_ERROR;
2012 }
2013 break;
2014 default:
2015 break;
2016 }
2017
2018 /* Process unlocked */
2019 __HAL_UNLOCK(hdsi);
2020
2021 return HAL_OK;
2022 }
2023
2024 /**
2025 * @brief Set custom timing for the PHY
2026 * @param hdsi pointer to a DSI_HandleTypeDef structure that contains
2027 * the configuration information for the DSI.
2028 * @param Timing PHY timing to be adjusted.
2029 * This parameter can be any value of @ref DSI_PHY_Timing
2030 * @param State ENABLE or DISABLE
2031 * @param Value Custom value of the timing
2032 * @retval HAL status
2033 */
2034 HAL_StatusTypeDef HAL_DSI_SetPHYTimings(DSI_HandleTypeDef *hdsi, uint32_t Timing, FunctionalState State, uint32_t Value)
2035 {
2036 /* Process locked */
2037 __HAL_LOCK(hdsi);
2038
2039 /* Check function parameters */
2040 assert_param(IS_DSI_PHY_TIMING(Timing));
2041 assert_param(IS_FUNCTIONAL_STATE(State));
2042
2043 switch(Timing)
2044 {
2045 case DSI_TCLK_POST:
2046 /* Enable/Disable custom timing setting */
2047 hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_TCLKPOSTEN;
2048 hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 27U);
2049
2050 if(State != DISABLE)
2051 {
2052 /* Set custom value */
2053 hdsi->Instance->WPCR[4U] &= ~DSI_WPCR4_TCLKPOST;
2054 hdsi->Instance->WPCR[4U] |= Value & DSI_WPCR4_TCLKPOST;
2055 }
2056
2057 break;
2058 case DSI_TLPX_CLK:
2059 /* Enable/Disable custom timing setting */
2060 hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_TLPXCEN;
2061 hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 26U);
2062
2063 if(State != DISABLE)
2064 {
2065 /* Set custom value */
2066 hdsi->Instance->WPCR[3U] &= ~DSI_WPCR3_TLPXC;
2067 hdsi->Instance->WPCR[3U] |= (Value << 24U) & DSI_WPCR3_TLPXC;
2068 }
2069
2070 break;
2071 case DSI_THS_EXIT:
2072 /* Enable/Disable custom timing setting */
2073 hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_THSEXITEN;
2074 hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 25U);
2075
2076 if(State != DISABLE)
2077 {
2078 /* Set custom value */
2079 hdsi->Instance->WPCR[3U] &= ~DSI_WPCR3_THSEXIT;
2080 hdsi->Instance->WPCR[3U] |= (Value << 16U) & DSI_WPCR3_THSEXIT;
2081 }
2082
2083 break;
2084 case DSI_TLPX_DATA:
2085 /* Enable/Disable custom timing setting */
2086 hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_TLPXDEN;
2087 hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 24U);
2088
2089 if(State != DISABLE)
2090 {
2091 /* Set custom value */
2092 hdsi->Instance->WPCR[3U] &= ~DSI_WPCR3_TLPXD;
2093 hdsi->Instance->WPCR[3U] |= (Value << 8U) & DSI_WPCR3_TLPXD;
2094 }
2095
2096 break;
2097 case DSI_THS_ZERO:
2098 /* Enable/Disable custom timing setting */
2099 hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_THSZEROEN;
2100 hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 23U);
2101
2102 if(State != DISABLE)
2103 {
2104 /* Set custom value */
2105 hdsi->Instance->WPCR[3U] &= ~DSI_WPCR3_THSZERO;
2106 hdsi->Instance->WPCR[3U] |= Value & DSI_WPCR3_THSZERO;
2107 }
2108
2109 break;
2110 case DSI_THS_TRAIL:
2111 /* Enable/Disable custom timing setting */
2112 hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_THSTRAILEN;
2113 hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 22U);
2114
2115 if(State != DISABLE)
2116 {
2117 /* Set custom value */
2118 hdsi->Instance->WPCR[2U] &= ~DSI_WPCR2_THSTRAIL;
2119 hdsi->Instance->WPCR[2U] |= (Value << 24U) & DSI_WPCR2_THSTRAIL;
2120 }
2121
2122 break;
2123 case DSI_THS_PREPARE:
2124 /* Enable/Disable custom timing setting */
2125 hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_THSPREPEN;
2126 hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 21U);
2127
2128 if(State != DISABLE)
2129 {
2130 /* Set custom value */
2131 hdsi->Instance->WPCR[2U] &= ~DSI_WPCR2_THSPREP;
2132 hdsi->Instance->WPCR[2U] |= (Value << 16U) & DSI_WPCR2_THSPREP;
2133 }
2134
2135 break;
2136 case DSI_TCLK_ZERO:
2137 /* Enable/Disable custom timing setting */
2138 hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_TCLKZEROEN;
2139 hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 20U);
2140
2141 if(State != DISABLE)
2142 {
2143 /* Set custom value */
2144 hdsi->Instance->WPCR[2U] &= ~DSI_WPCR2_TCLKZERO;
2145 hdsi->Instance->WPCR[2U] |= (Value << 8U) & DSI_WPCR2_TCLKZERO;
2146 }
2147
2148 break;
2149 case DSI_TCLK_PREPARE:
2150 /* Enable/Disable custom timing setting */
2151 hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_TCLKPREPEN;
2152 hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 19U);
2153
2154 if(State != DISABLE)
2155 {
2156 /* Set custom value */
2157 hdsi->Instance->WPCR[2U] &= ~DSI_WPCR2_TCLKPREP;
2158 hdsi->Instance->WPCR[2U] |= Value & DSI_WPCR2_TCLKPREP;
2159 }
2160
2161 break;
2162 default:
2163 break;
2164 }
2165
2166 /* Process unlocked */
2167 __HAL_UNLOCK(hdsi);
2168
2169 return HAL_OK;
2170 }
2171
2172 /**
2173 * @brief Force the Clock/Data Lane in TX Stop Mode
2174 * @param hdsi pointer to a DSI_HandleTypeDef structure that contains
2175 * the configuration information for the DSI.
2176 * @param Lane select between clock or data lanes.
2177 * This parameter can be any value of @ref DSI_Lane_Group
2178 * @param State ENABLE or DISABLE
2179 * @retval HAL status
2180 */
2181 HAL_StatusTypeDef HAL_DSI_ForceTXStopMode(DSI_HandleTypeDef *hdsi, uint32_t Lane, FunctionalState State)
2182 {
2183 /* Process locked */
2184 __HAL_LOCK(hdsi);
2185
2186 /* Check function parameters */
2187 assert_param(IS_DSI_LANE_GROUP(Lane));
2188 assert_param(IS_FUNCTIONAL_STATE(State));
2189
2190 if(Lane == DSI_CLOCK_LANE)
2191 {
2192 /* Force/Unforce the Clock Lane in TX Stop Mode */
2193 hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_FTXSMCL;
2194 hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 12U);
2195 }
2196 else if(Lane == DSI_DATA_LANES)
2197 {
2198 /* Force/Unforce the Data Lanes in TX Stop Mode */
2199 hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_FTXSMDL;
2200 hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 13U);
2201 }
2202 else
2203 {
2204 /* Process unlocked */
2205 __HAL_UNLOCK(hdsi);
2206
2207 return HAL_ERROR;
2208 }
2209
2210 /* Process unlocked */
2211 __HAL_UNLOCK(hdsi);
2212
2213 return HAL_OK;
2214 }
2215
2216 /**
2217 * @brief Force LP Receiver in Low-Power Mode
2218 * @param hdsi pointer to a DSI_HandleTypeDef structure that contains
2219 * the configuration information for the DSI.
2220 * @param State ENABLE or DISABLE
2221 * @retval HAL status
2222 */
2223 HAL_StatusTypeDef HAL_DSI_ForceRXLowPower(DSI_HandleTypeDef *hdsi, FunctionalState State)
2224 {
2225 /* Process locked */
2226 __HAL_LOCK(hdsi);
2227
2228 /* Check function parameters */
2229 assert_param(IS_FUNCTIONAL_STATE(State));
2230
2231 /* Force/Unforce LP Receiver in Low-Power Mode */
2232 hdsi->Instance->WPCR[1U] &= ~DSI_WPCR1_FLPRXLPM;
2233 hdsi->Instance->WPCR[1U] |= ((uint32_t)State << 22U);
2234
2235 /* Process unlocked */
2236 __HAL_UNLOCK(hdsi);
2237
2238 return HAL_OK;
2239 }
2240
2241 /**
2242 * @brief Force Data Lanes in RX Mode after a BTA
2243 * @param hdsi pointer to a DSI_HandleTypeDef structure that contains
2244 * the configuration information for the DSI.
2245 * @param State ENABLE or DISABLE
2246 * @retval HAL status
2247 */
2248 HAL_StatusTypeDef HAL_DSI_ForceDataLanesInRX(DSI_HandleTypeDef *hdsi, FunctionalState State)
2249 {
2250 /* Process locked */
2251 __HAL_LOCK(hdsi);
2252
2253 /* Check function parameters */
2254 assert_param(IS_FUNCTIONAL_STATE(State));
2255
2256 /* Force Data Lanes in RX Mode */
2257 hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_TDDL;
2258 hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 16U);
2259
2260 /* Process unlocked */
2261 __HAL_UNLOCK(hdsi);
2262
2263 return HAL_OK;
2264 }
2265
2266 /**
2267 * @brief Enable a pull-down on the lanes to prevent from floating states when unused
2268 * @param hdsi pointer to a DSI_HandleTypeDef structure that contains
2269 * the configuration information for the DSI.
2270 * @param State ENABLE or DISABLE
2271 * @retval HAL status
2272 */
2273 HAL_StatusTypeDef HAL_DSI_SetPullDown(DSI_HandleTypeDef *hdsi, FunctionalState State)
2274 {
2275 /* Process locked */
2276 __HAL_LOCK(hdsi);
2277
2278 /* Check function parameters */
2279 assert_param(IS_FUNCTIONAL_STATE(State));
2280
2281 /* Enable/Disable pull-down on lanes */
2282 hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_PDEN;
2283 hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 18U);
2284
2285 /* Process unlocked */
2286 __HAL_UNLOCK(hdsi);
2287
2288 return HAL_OK;
2289 }
2290
2291 /**
2292 * @brief Switch off the contention detection on data lanes
2293 * @param hdsi pointer to a DSI_HandleTypeDef structure that contains
2294 * the configuration information for the DSI.
2295 * @param State ENABLE or DISABLE
2296 * @retval HAL status
2297 */
2298 HAL_StatusTypeDef HAL_DSI_SetContentionDetectionOff(DSI_HandleTypeDef *hdsi, FunctionalState State)
2299 {
2300 /* Process locked */
2301 __HAL_LOCK(hdsi);
2302
2303 /* Check function parameters */
2304 assert_param(IS_FUNCTIONAL_STATE(State));
2305
2306 /* Contention Detection on Data Lanes OFF */
2307 hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_CDOFFDL;
2308 hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 14U);
2309
2310 /* Process unlocked */
2311 __HAL_UNLOCK(hdsi);
2312
2313 return HAL_OK;
2314 }
2315
2316 /**
2317 * @}
2318 */
2319
2320 /** @defgroup DSI_Group4 Peripheral State and Errors functions
2321 * @brief Peripheral State and Errors functions
2322 *
2323 @verbatim
2324 ===============================================================================
2325 ##### Peripheral State and Errors functions #####
2326 ===============================================================================
2327 [..]
2328 This subsection provides functions allowing to
2329 (+) Check the DSI state.
2330 (+) Get error code.
2331
2332 @endverbatim
2333 * @{
2334 */
2335
2336 /**
2337 * @brief Return the DSI state
2338 * @param hdsi pointer to a DSI_HandleTypeDef structure that contains
2339 * the configuration information for the DSI.
2340 * @retval HAL state
2341 */
2342 HAL_DSI_StateTypeDef HAL_DSI_GetState(DSI_HandleTypeDef *hdsi)
2343 {
2344 return hdsi->State;
2345 }
2346
2347 /**
2348 * @brief Return the DSI error code
2349 * @param hdsi pointer to a DSI_HandleTypeDef structure that contains
2350 * the configuration information for the DSI.
2351 * @retval DSI Error Code
2352 */
2353 uint32_t HAL_DSI_GetError(DSI_HandleTypeDef *hdsi)
2354 {
2355 /* Get the error code */
2356 return hdsi->ErrorCode;
2357 }
2358
2359 /**
2360 * @}
2361 */
2362
2363 /**
2364 * @}
2365 */
2366
2367 /**
2368 * @}
2369 */
2370
2371 #endif /* DSI */
2372
2373 #endif /* HAL_DSI_MODULE_ENABLED */
2374
2375 /**
2376 * @}
2377 */
2378
2379 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/