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comparison Common/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_rcc.h @ 160:e3ca52b8e7fa

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Merge with FlipDisplay
author heinrichsweikamp
date Thu, 07 Mar 2019 15:06:43 +0100
parents c78bcbd5deda
children 4e10a3e087a1
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80:cc2bb7bb8456 160:e3ca52b8e7fa
1 /**
2 ******************************************************************************
3 * @file stm32f4xx_ll_rcc.h
4 * @author MCD Application Team
5 * @brief Header file of RCC LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
10 *
11 * Redistribution and use in source and binary forms, with or without modification,
12 * are permitted provided that the following conditions are met:
13 * 1. Redistributions of source code must retain the above copyright notice,
14 * this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright notice,
16 * this list of conditions and the following disclaimer in the documentation
17 * and/or other materials provided with the distribution.
18 * 3. Neither the name of STMicroelectronics nor the names of its contributors
19 * may be used to endorse or promote products derived from this software
20 * without specific prior written permission.
21 *
22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
23 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
25 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
29 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32 *
33 ******************************************************************************
34 */
35
36 /* Define to prevent recursive inclusion -------------------------------------*/
37 #ifndef __STM32F4xx_LL_RCC_H
38 #define __STM32F4xx_LL_RCC_H
39
40 #ifdef __cplusplus
41 extern "C" {
42 #endif
43
44 /* Includes ------------------------------------------------------------------*/
45 #include "stm32f4xx.h"
46
47 /** @addtogroup STM32F4xx_LL_Driver
48 * @{
49 */
50
51 #if defined(RCC)
52
53 /** @defgroup RCC_LL RCC
54 * @{
55 */
56
57 /* Private types -------------------------------------------------------------*/
58 /* Private variables ---------------------------------------------------------*/
59 /** @defgroup RCC_LL_Private_Variables RCC Private Variables
60 * @{
61 */
62
63 #if defined(RCC_DCKCFGR_PLLSAIDIVR)
64 static const uint8_t aRCC_PLLSAIDIVRPrescTable[4] = {2, 4, 8, 16};
65 #endif /* RCC_DCKCFGR_PLLSAIDIVR */
66
67 /**
68 * @}
69 */
70 /* Private constants ---------------------------------------------------------*/
71 /* Private macros ------------------------------------------------------------*/
72 #if defined(USE_FULL_LL_DRIVER)
73 /** @defgroup RCC_LL_Private_Macros RCC Private Macros
74 * @{
75 */
76 /**
77 * @}
78 */
79 #endif /*USE_FULL_LL_DRIVER*/
80 /* Exported types ------------------------------------------------------------*/
81 #if defined(USE_FULL_LL_DRIVER)
82 /** @defgroup RCC_LL_Exported_Types RCC Exported Types
83 * @{
84 */
85
86 /** @defgroup LL_ES_CLOCK_FREQ Clocks Frequency Structure
87 * @{
88 */
89
90 /**
91 * @brief RCC Clocks Frequency Structure
92 */
93 typedef struct
94 {
95 uint32_t SYSCLK_Frequency; /*!< SYSCLK clock frequency */
96 uint32_t HCLK_Frequency; /*!< HCLK clock frequency */
97 uint32_t PCLK1_Frequency; /*!< PCLK1 clock frequency */
98 uint32_t PCLK2_Frequency; /*!< PCLK2 clock frequency */
99 } LL_RCC_ClocksTypeDef;
100
101 /**
102 * @}
103 */
104
105 /**
106 * @}
107 */
108 #endif /* USE_FULL_LL_DRIVER */
109
110 /* Exported constants --------------------------------------------------------*/
111 /** @defgroup RCC_LL_Exported_Constants RCC Exported Constants
112 * @{
113 */
114
115 /** @defgroup RCC_LL_EC_OSC_VALUES Oscillator Values adaptation
116 * @brief Defines used to adapt values of different oscillators
117 * @note These values could be modified in the user environment according to
118 * HW set-up.
119 * @{
120 */
121 #if !defined (HSE_VALUE)
122 #define HSE_VALUE 25000000U /*!< Value of the HSE oscillator in Hz */
123 #endif /* HSE_VALUE */
124
125 #if !defined (HSI_VALUE)
126 #define HSI_VALUE 16000000U /*!< Value of the HSI oscillator in Hz */
127 #endif /* HSI_VALUE */
128
129 #if !defined (LSE_VALUE)
130 #define LSE_VALUE 32768U /*!< Value of the LSE oscillator in Hz */
131 #endif /* LSE_VALUE */
132
133 #if !defined (LSI_VALUE)
134 #define LSI_VALUE 32000U /*!< Value of the LSI oscillator in Hz */
135 #endif /* LSI_VALUE */
136
137 #if !defined (EXTERNAL_CLOCK_VALUE)
138 #define EXTERNAL_CLOCK_VALUE 12288000U /*!< Value of the I2S_CKIN external oscillator in Hz */
139 #endif /* EXTERNAL_CLOCK_VALUE */
140 /**
141 * @}
142 */
143
144 /** @defgroup RCC_LL_EC_CLEAR_FLAG Clear Flags Defines
145 * @brief Flags defines which can be used with LL_RCC_WriteReg function
146 * @{
147 */
148 #define LL_RCC_CIR_LSIRDYC RCC_CIR_LSIRDYC /*!< LSI Ready Interrupt Clear */
149 #define LL_RCC_CIR_LSERDYC RCC_CIR_LSERDYC /*!< LSE Ready Interrupt Clear */
150 #define LL_RCC_CIR_HSIRDYC RCC_CIR_HSIRDYC /*!< HSI Ready Interrupt Clear */
151 #define LL_RCC_CIR_HSERDYC RCC_CIR_HSERDYC /*!< HSE Ready Interrupt Clear */
152 #define LL_RCC_CIR_PLLRDYC RCC_CIR_PLLRDYC /*!< PLL Ready Interrupt Clear */
153 #if defined(RCC_PLLI2S_SUPPORT)
154 #define LL_RCC_CIR_PLLI2SRDYC RCC_CIR_PLLI2SRDYC /*!< PLLI2S Ready Interrupt Clear */
155 #endif /* RCC_PLLI2S_SUPPORT */
156 #if defined(RCC_PLLSAI_SUPPORT)
157 #define LL_RCC_CIR_PLLSAIRDYC RCC_CIR_PLLSAIRDYC /*!< PLLSAI Ready Interrupt Clear */
158 #endif /* RCC_PLLSAI_SUPPORT */
159 #define LL_RCC_CIR_CSSC RCC_CIR_CSSC /*!< Clock Security System Interrupt Clear */
160 /**
161 * @}
162 */
163
164 /** @defgroup RCC_LL_EC_GET_FLAG Get Flags Defines
165 * @brief Flags defines which can be used with LL_RCC_ReadReg function
166 * @{
167 */
168 #define LL_RCC_CIR_LSIRDYF RCC_CIR_LSIRDYF /*!< LSI Ready Interrupt flag */
169 #define LL_RCC_CIR_LSERDYF RCC_CIR_LSERDYF /*!< LSE Ready Interrupt flag */
170 #define LL_RCC_CIR_HSIRDYF RCC_CIR_HSIRDYF /*!< HSI Ready Interrupt flag */
171 #define LL_RCC_CIR_HSERDYF RCC_CIR_HSERDYF /*!< HSE Ready Interrupt flag */
172 #define LL_RCC_CIR_PLLRDYF RCC_CIR_PLLRDYF /*!< PLL Ready Interrupt flag */
173 #if defined(RCC_PLLI2S_SUPPORT)
174 #define LL_RCC_CIR_PLLI2SRDYF RCC_CIR_PLLI2SRDYF /*!< PLLI2S Ready Interrupt flag */
175 #endif /* RCC_PLLI2S_SUPPORT */
176 #if defined(RCC_PLLSAI_SUPPORT)
177 #define LL_RCC_CIR_PLLSAIRDYF RCC_CIR_PLLSAIRDYF /*!< PLLSAI Ready Interrupt flag */
178 #endif /* RCC_PLLSAI_SUPPORT */
179 #define LL_RCC_CIR_CSSF RCC_CIR_CSSF /*!< Clock Security System Interrupt flag */
180 #define LL_RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF /*!< Low-Power reset flag */
181 #define LL_RCC_CSR_PINRSTF RCC_CSR_PINRSTF /*!< PIN reset flag */
182 #define LL_RCC_CSR_PORRSTF RCC_CSR_PORRSTF /*!< POR/PDR reset flag */
183 #define LL_RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF /*!< Software Reset flag */
184 #define LL_RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF /*!< Independent Watchdog reset flag */
185 #define LL_RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF /*!< Window watchdog reset flag */
186 #if defined(RCC_CSR_BORRSTF)
187 #define LL_RCC_CSR_BORRSTF RCC_CSR_BORRSTF /*!< BOR reset flag */
188 #endif /* RCC_CSR_BORRSTF */
189 /**
190 * @}
191 */
192
193 /** @defgroup RCC_LL_EC_IT IT Defines
194 * @brief IT defines which can be used with LL_RCC_ReadReg and LL_RCC_WriteReg functions
195 * @{
196 */
197 #define LL_RCC_CIR_LSIRDYIE RCC_CIR_LSIRDYIE /*!< LSI Ready Interrupt Enable */
198 #define LL_RCC_CIR_LSERDYIE RCC_CIR_LSERDYIE /*!< LSE Ready Interrupt Enable */
199 #define LL_RCC_CIR_HSIRDYIE RCC_CIR_HSIRDYIE /*!< HSI Ready Interrupt Enable */
200 #define LL_RCC_CIR_HSERDYIE RCC_CIR_HSERDYIE /*!< HSE Ready Interrupt Enable */
201 #define LL_RCC_CIR_PLLRDYIE RCC_CIR_PLLRDYIE /*!< PLL Ready Interrupt Enable */
202 #if defined(RCC_PLLI2S_SUPPORT)
203 #define LL_RCC_CIR_PLLI2SRDYIE RCC_CIR_PLLI2SRDYIE /*!< PLLI2S Ready Interrupt Enable */
204 #endif /* RCC_PLLI2S_SUPPORT */
205 #if defined(RCC_PLLSAI_SUPPORT)
206 #define LL_RCC_CIR_PLLSAIRDYIE RCC_CIR_PLLSAIRDYIE /*!< PLLSAI Ready Interrupt Enable */
207 #endif /* RCC_PLLSAI_SUPPORT */
208 /**
209 * @}
210 */
211
212 /** @defgroup RCC_LL_EC_SYS_CLKSOURCE System clock switch
213 * @{
214 */
215 #define LL_RCC_SYS_CLKSOURCE_HSI RCC_CFGR_SW_HSI /*!< HSI selection as system clock */
216 #define LL_RCC_SYS_CLKSOURCE_HSE RCC_CFGR_SW_HSE /*!< HSE selection as system clock */
217 #define LL_RCC_SYS_CLKSOURCE_PLL RCC_CFGR_SW_PLL /*!< PLL selection as system clock */
218 #if defined(RCC_CFGR_SW_PLLR)
219 #define LL_RCC_SYS_CLKSOURCE_PLLR RCC_CFGR_SW_PLLR /*!< PLLR selection as system clock */
220 #endif /* RCC_CFGR_SW_PLLR */
221 /**
222 * @}
223 */
224
225 /** @defgroup RCC_LL_EC_SYS_CLKSOURCE_STATUS System clock switch status
226 * @{
227 */
228 #define LL_RCC_SYS_CLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI /*!< HSI used as system clock */
229 #define LL_RCC_SYS_CLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE /*!< HSE used as system clock */
230 #define LL_RCC_SYS_CLKSOURCE_STATUS_PLL RCC_CFGR_SWS_PLL /*!< PLL used as system clock */
231 #if defined(RCC_PLLR_SYSCLK_SUPPORT)
232 #define LL_RCC_SYS_CLKSOURCE_STATUS_PLLR RCC_CFGR_SWS_PLLR /*!< PLLR used as system clock */
233 #endif /* RCC_PLLR_SYSCLK_SUPPORT */
234 /**
235 * @}
236 */
237
238 /** @defgroup RCC_LL_EC_SYSCLK_DIV AHB prescaler
239 * @{
240 */
241 #define LL_RCC_SYSCLK_DIV_1 RCC_CFGR_HPRE_DIV1 /*!< SYSCLK not divided */
242 #define LL_RCC_SYSCLK_DIV_2 RCC_CFGR_HPRE_DIV2 /*!< SYSCLK divided by 2 */
243 #define LL_RCC_SYSCLK_DIV_4 RCC_CFGR_HPRE_DIV4 /*!< SYSCLK divided by 4 */
244 #define LL_RCC_SYSCLK_DIV_8 RCC_CFGR_HPRE_DIV8 /*!< SYSCLK divided by 8 */
245 #define LL_RCC_SYSCLK_DIV_16 RCC_CFGR_HPRE_DIV16 /*!< SYSCLK divided by 16 */
246 #define LL_RCC_SYSCLK_DIV_64 RCC_CFGR_HPRE_DIV64 /*!< SYSCLK divided by 64 */
247 #define LL_RCC_SYSCLK_DIV_128 RCC_CFGR_HPRE_DIV128 /*!< SYSCLK divided by 128 */
248 #define LL_RCC_SYSCLK_DIV_256 RCC_CFGR_HPRE_DIV256 /*!< SYSCLK divided by 256 */
249 #define LL_RCC_SYSCLK_DIV_512 RCC_CFGR_HPRE_DIV512 /*!< SYSCLK divided by 512 */
250 /**
251 * @}
252 */
253
254 /** @defgroup RCC_LL_EC_APB1_DIV APB low-speed prescaler (APB1)
255 * @{
256 */
257 #define LL_RCC_APB1_DIV_1 RCC_CFGR_PPRE1_DIV1 /*!< HCLK not divided */
258 #define LL_RCC_APB1_DIV_2 RCC_CFGR_PPRE1_DIV2 /*!< HCLK divided by 2 */
259 #define LL_RCC_APB1_DIV_4 RCC_CFGR_PPRE1_DIV4 /*!< HCLK divided by 4 */
260 #define LL_RCC_APB1_DIV_8 RCC_CFGR_PPRE1_DIV8 /*!< HCLK divided by 8 */
261 #define LL_RCC_APB1_DIV_16 RCC_CFGR_PPRE1_DIV16 /*!< HCLK divided by 16 */
262 /**
263 * @}
264 */
265
266 /** @defgroup RCC_LL_EC_APB2_DIV APB high-speed prescaler (APB2)
267 * @{
268 */
269 #define LL_RCC_APB2_DIV_1 RCC_CFGR_PPRE2_DIV1 /*!< HCLK not divided */
270 #define LL_RCC_APB2_DIV_2 RCC_CFGR_PPRE2_DIV2 /*!< HCLK divided by 2 */
271 #define LL_RCC_APB2_DIV_4 RCC_CFGR_PPRE2_DIV4 /*!< HCLK divided by 4 */
272 #define LL_RCC_APB2_DIV_8 RCC_CFGR_PPRE2_DIV8 /*!< HCLK divided by 8 */
273 #define LL_RCC_APB2_DIV_16 RCC_CFGR_PPRE2_DIV16 /*!< HCLK divided by 16 */
274 /**
275 * @}
276 */
277
278 /** @defgroup RCC_LL_EC_MCOxSOURCE MCO source selection
279 * @{
280 */
281 #define LL_RCC_MCO1SOURCE_HSI (uint32_t)(RCC_CFGR_MCO1|0x00000000U) /*!< HSI selection as MCO1 source */
282 #define LL_RCC_MCO1SOURCE_LSE (uint32_t)(RCC_CFGR_MCO1|(RCC_CFGR_MCO1_0 >> 16U)) /*!< LSE selection as MCO1 source */
283 #define LL_RCC_MCO1SOURCE_HSE (uint32_t)(RCC_CFGR_MCO1|(RCC_CFGR_MCO1_1 >> 16U)) /*!< HSE selection as MCO1 source */
284 #define LL_RCC_MCO1SOURCE_PLLCLK (uint32_t)(RCC_CFGR_MCO1|((RCC_CFGR_MCO1_1|RCC_CFGR_MCO1_0) >> 16U)) /*!< PLLCLK selection as MCO1 source */
285 #if defined(RCC_CFGR_MCO2)
286 #define LL_RCC_MCO2SOURCE_SYSCLK (uint32_t)(RCC_CFGR_MCO2|0x00000000U) /*!< SYSCLK selection as MCO2 source */
287 #define LL_RCC_MCO2SOURCE_PLLI2S (uint32_t)(RCC_CFGR_MCO2|(RCC_CFGR_MCO2_0 >> 16U)) /*!< PLLI2S selection as MCO2 source */
288 #define LL_RCC_MCO2SOURCE_HSE (uint32_t)(RCC_CFGR_MCO2|(RCC_CFGR_MCO2_1 >> 16U)) /*!< HSE selection as MCO2 source */
289 #define LL_RCC_MCO2SOURCE_PLLCLK (uint32_t)(RCC_CFGR_MCO2|((RCC_CFGR_MCO2_1|RCC_CFGR_MCO2_0) >> 16U)) /*!< PLLCLK selection as MCO2 source */
290 #endif /* RCC_CFGR_MCO2 */
291 /**
292 * @}
293 */
294
295 /** @defgroup RCC_LL_EC_MCOx_DIV MCO prescaler
296 * @{
297 */
298 #define LL_RCC_MCO1_DIV_1 (uint32_t)(RCC_CFGR_MCO1PRE|0x00000000U) /*!< MCO1 not divided */
299 #define LL_RCC_MCO1_DIV_2 (uint32_t)(RCC_CFGR_MCO1PRE|(RCC_CFGR_MCO1PRE_2 >> 16U)) /*!< MCO1 divided by 2 */
300 #define LL_RCC_MCO1_DIV_3 (uint32_t)(RCC_CFGR_MCO1PRE|((RCC_CFGR_MCO1PRE_2|RCC_CFGR_MCO1PRE_0) >> 16U)) /*!< MCO1 divided by 3 */
301 #define LL_RCC_MCO1_DIV_4 (uint32_t)(RCC_CFGR_MCO1PRE|((RCC_CFGR_MCO1PRE_2|RCC_CFGR_MCO1PRE_1) >> 16U)) /*!< MCO1 divided by 4 */
302 #define LL_RCC_MCO1_DIV_5 (uint32_t)(RCC_CFGR_MCO1PRE|(RCC_CFGR_MCO1PRE >> 16U)) /*!< MCO1 divided by 5 */
303 #if defined(RCC_CFGR_MCO2PRE)
304 #define LL_RCC_MCO2_DIV_1 (uint32_t)(RCC_CFGR_MCO2PRE|0x00000000U) /*!< MCO2 not divided */
305 #define LL_RCC_MCO2_DIV_2 (uint32_t)(RCC_CFGR_MCO2PRE|(RCC_CFGR_MCO2PRE_2 >> 16U)) /*!< MCO2 divided by 2 */
306 #define LL_RCC_MCO2_DIV_3 (uint32_t)(RCC_CFGR_MCO2PRE|((RCC_CFGR_MCO2PRE_2|RCC_CFGR_MCO2PRE_0) >> 16U)) /*!< MCO2 divided by 3 */
307 #define LL_RCC_MCO2_DIV_4 (uint32_t)(RCC_CFGR_MCO2PRE|((RCC_CFGR_MCO2PRE_2|RCC_CFGR_MCO2PRE_1) >> 16U)) /*!< MCO2 divided by 4 */
308 #define LL_RCC_MCO2_DIV_5 (uint32_t)(RCC_CFGR_MCO2PRE|(RCC_CFGR_MCO2PRE >> 16U)) /*!< MCO2 divided by 5 */
309 #endif /* RCC_CFGR_MCO2PRE */
310 /**
311 * @}
312 */
313
314 /** @defgroup RCC_LL_EC_RTC_HSEDIV HSE prescaler for RTC clock
315 * @{
316 */
317 #define LL_RCC_RTC_NOCLOCK 0x00000000U /*!< HSE not divided */
318 #define LL_RCC_RTC_HSE_DIV_2 RCC_CFGR_RTCPRE_1 /*!< HSE clock divided by 2 */
319 #define LL_RCC_RTC_HSE_DIV_3 (RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 3 */
320 #define LL_RCC_RTC_HSE_DIV_4 RCC_CFGR_RTCPRE_2 /*!< HSE clock divided by 4 */
321 #define LL_RCC_RTC_HSE_DIV_5 (RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 5 */
322 #define LL_RCC_RTC_HSE_DIV_6 (RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1) /*!< HSE clock divided by 6 */
323 #define LL_RCC_RTC_HSE_DIV_7 (RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 7 */
324 #define LL_RCC_RTC_HSE_DIV_8 RCC_CFGR_RTCPRE_3 /*!< HSE clock divided by 8 */
325 #define LL_RCC_RTC_HSE_DIV_9 (RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 9 */
326 #define LL_RCC_RTC_HSE_DIV_10 (RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_1) /*!< HSE clock divided by 10 */
327 #define LL_RCC_RTC_HSE_DIV_11 (RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 11 */
328 #define LL_RCC_RTC_HSE_DIV_12 (RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2) /*!< HSE clock divided by 12 */
329 #define LL_RCC_RTC_HSE_DIV_13 (RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 13 */
330 #define LL_RCC_RTC_HSE_DIV_14 (RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1) /*!< HSE clock divided by 14 */
331 #define LL_RCC_RTC_HSE_DIV_15 (RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 15 */
332 #define LL_RCC_RTC_HSE_DIV_16 RCC_CFGR_RTCPRE_4 /*!< HSE clock divided by 16 */
333 #define LL_RCC_RTC_HSE_DIV_17 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 17 */
334 #define LL_RCC_RTC_HSE_DIV_18 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_1) /*!< HSE clock divided by 18 */
335 #define LL_RCC_RTC_HSE_DIV_19 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 19 */
336 #define LL_RCC_RTC_HSE_DIV_20 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_2) /*!< HSE clock divided by 20 */
337 #define LL_RCC_RTC_HSE_DIV_21 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 21 */
338 #define LL_RCC_RTC_HSE_DIV_22 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1) /*!< HSE clock divided by 22 */
339 #define LL_RCC_RTC_HSE_DIV_23 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 23 */
340 #define LL_RCC_RTC_HSE_DIV_24 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3) /*!< HSE clock divided by 24 */
341 #define LL_RCC_RTC_HSE_DIV_25 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 25 */
342 #define LL_RCC_RTC_HSE_DIV_26 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_1) /*!< HSE clock divided by 26 */
343 #define LL_RCC_RTC_HSE_DIV_27 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 27 */
344 #define LL_RCC_RTC_HSE_DIV_28 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2) /*!< HSE clock divided by 28 */
345 #define LL_RCC_RTC_HSE_DIV_29 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 29 */
346 #define LL_RCC_RTC_HSE_DIV_30 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1) /*!< HSE clock divided by 30 */
347 #define LL_RCC_RTC_HSE_DIV_31 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 31 */
348 /**
349 * @}
350 */
351
352 #if defined(USE_FULL_LL_DRIVER)
353 /** @defgroup RCC_LL_EC_PERIPH_FREQUENCY Peripheral clock frequency
354 * @{
355 */
356 #define LL_RCC_PERIPH_FREQUENCY_NO 0x00000000U /*!< No clock enabled for the peripheral */
357 #define LL_RCC_PERIPH_FREQUENCY_NA 0xFFFFFFFFU /*!< Frequency cannot be provided as external clock */
358 /**
359 * @}
360 */
361 #endif /* USE_FULL_LL_DRIVER */
362
363 #if defined(FMPI2C1)
364 /** @defgroup RCC_LL_EC_FMPI2C1_CLKSOURCE Peripheral FMPI2C clock source selection
365 * @{
366 */
367 #define LL_RCC_FMPI2C1_CLKSOURCE_PCLK1 0x00000000U /*!< PCLK1 clock used as FMPI2C1 clock source */
368 #define LL_RCC_FMPI2C1_CLKSOURCE_SYSCLK RCC_DCKCFGR2_FMPI2C1SEL_0 /*!< SYSCLK clock used as FMPI2C1 clock source */
369 #define LL_RCC_FMPI2C1_CLKSOURCE_HSI RCC_DCKCFGR2_FMPI2C1SEL_1 /*!< HSI clock used as FMPI2C1 clock source */
370 /**
371 * @}
372 */
373 #endif /* FMPI2C1 */
374
375 #if defined(LPTIM1)
376 /** @defgroup RCC_LL_EC_LPTIM1_CLKSOURCE Peripheral LPTIM clock source selection
377 * @{
378 */
379 #define LL_RCC_LPTIM1_CLKSOURCE_PCLK1 0x00000000U /*!< PCLK1 clock used as LPTIM1 clock */
380 #define LL_RCC_LPTIM1_CLKSOURCE_HSI RCC_DCKCFGR2_LPTIM1SEL_0 /*!< LSI oscillator clock used as LPTIM1 clock */
381 #define LL_RCC_LPTIM1_CLKSOURCE_LSI RCC_DCKCFGR2_LPTIM1SEL_1 /*!< HSI oscillator clock used as LPTIM1 clock */
382 #define LL_RCC_LPTIM1_CLKSOURCE_LSE (uint32_t)(RCC_DCKCFGR2_LPTIM1SEL_1 | RCC_DCKCFGR2_LPTIM1SEL_0) /*!< LSE oscillator clock used as LPTIM1 clock */
383 /**
384 * @}
385 */
386 #endif /* LPTIM1 */
387
388 #if defined(SAI1)
389 /** @defgroup RCC_LL_EC_SAIx_CLKSOURCE Peripheral SAI clock source selection
390 * @{
391 */
392 #if defined(RCC_DCKCFGR_SAI1SRC)
393 #define LL_RCC_SAI1_CLKSOURCE_PLLSAI (uint32_t)(RCC_DCKCFGR_SAI1SRC | 0x00000000U) /*!< PLLSAI clock used as SAI1 clock source */
394 #define LL_RCC_SAI1_CLKSOURCE_PLLI2S (uint32_t)(RCC_DCKCFGR_SAI1SRC | (RCC_DCKCFGR_SAI1SRC_0 >> 16)) /*!< PLLI2S clock used as SAI1 clock source */
395 #define LL_RCC_SAI1_CLKSOURCE_PLL (uint32_t)(RCC_DCKCFGR_SAI1SRC | (RCC_DCKCFGR_SAI1SRC_1 >> 16)) /*!< PLL clock used as SAI1 clock source */
396 #define LL_RCC_SAI1_CLKSOURCE_PIN (uint32_t)(RCC_DCKCFGR_SAI1SRC | (RCC_DCKCFGR_SAI1SRC >> 16)) /*!< External pin clock used as SAI1 clock source */
397 #endif /* RCC_DCKCFGR_SAI1SRC */
398 #if defined(RCC_DCKCFGR_SAI2SRC)
399 #define LL_RCC_SAI2_CLKSOURCE_PLLSAI (uint32_t)(RCC_DCKCFGR_SAI2SRC | 0x00000000U) /*!< PLLSAI clock used as SAI2 clock source */
400 #define LL_RCC_SAI2_CLKSOURCE_PLLI2S (uint32_t)(RCC_DCKCFGR_SAI2SRC | (RCC_DCKCFGR_SAI2SRC_0 >> 16)) /*!< PLLI2S clock used as SAI2 clock source */
401 #define LL_RCC_SAI2_CLKSOURCE_PLL (uint32_t)(RCC_DCKCFGR_SAI2SRC | (RCC_DCKCFGR_SAI2SRC_1 >> 16)) /*!< PLL clock used as SAI2 clock source */
402 #define LL_RCC_SAI2_CLKSOURCE_PLLSRC (uint32_t)(RCC_DCKCFGR_SAI2SRC | (RCC_DCKCFGR_SAI2SRC >> 16)) /*!< PLL Main clock used as SAI2 clock source */
403 #endif /* RCC_DCKCFGR_SAI2SRC */
404 #if defined(RCC_DCKCFGR_SAI1ASRC)
405 #if defined(RCC_SAI1A_PLLSOURCE_SUPPORT)
406 #define LL_RCC_SAI1_A_CLKSOURCE_PLLI2S (uint32_t)(RCC_DCKCFGR_SAI1ASRC | 0x00000000U) /*!< PLLI2S clock used as SAI1 block A clock source */
407 #define LL_RCC_SAI1_A_CLKSOURCE_PIN (uint32_t)(RCC_DCKCFGR_SAI1ASRC | (RCC_DCKCFGR_SAI1ASRC_0 >> 16)) /*!< External pin used as SAI1 block A clock source */
408 #define LL_RCC_SAI1_A_CLKSOURCE_PLL (uint32_t)(RCC_DCKCFGR_SAI1ASRC | (RCC_DCKCFGR_SAI1ASRC_1 >> 16)) /*!< PLL clock used as SAI1 block A clock source */
409 #define LL_RCC_SAI1_A_CLKSOURCE_PLLSRC (uint32_t)(RCC_DCKCFGR_SAI1ASRC | (RCC_DCKCFGR_SAI1ASRC >> 16)) /*!< PLL Main clock used as SAI1 block A clock source */
410 #else
411 #define LL_RCC_SAI1_A_CLKSOURCE_PLLSAI (uint32_t)(RCC_DCKCFGR_SAI1ASRC | 0x00000000U) /*!< PLLSAI clock used as SAI1 block A clock source */
412 #define LL_RCC_SAI1_A_CLKSOURCE_PLLI2S (uint32_t)(RCC_DCKCFGR_SAI1ASRC | (RCC_DCKCFGR_SAI1ASRC_0 >> 16)) /*!< PLLI2S clock used as SAI1 block A clock source */
413 #define LL_RCC_SAI1_A_CLKSOURCE_PIN (uint32_t)(RCC_DCKCFGR_SAI1ASRC | (RCC_DCKCFGR_SAI1ASRC_1 >> 16)) /*!< External pin clock used as SAI1 block A clock source */
414 #endif /* RCC_SAI1A_PLLSOURCE_SUPPORT */
415 #endif /* RCC_DCKCFGR_SAI1ASRC */
416 #if defined(RCC_DCKCFGR_SAI1BSRC)
417 #if defined(RCC_SAI1B_PLLSOURCE_SUPPORT)
418 #define LL_RCC_SAI1_B_CLKSOURCE_PLLI2S (uint32_t)(RCC_DCKCFGR_SAI1BSRC | 0x00000000U) /*!< PLLI2S clock used as SAI1 block B clock source */
419 #define LL_RCC_SAI1_B_CLKSOURCE_PIN (uint32_t)(RCC_DCKCFGR_SAI1BSRC | (RCC_DCKCFGR_SAI1BSRC_0 >> 16)) /*!< External pin used as SAI1 block B clock source */
420 #define LL_RCC_SAI1_B_CLKSOURCE_PLL (uint32_t)(RCC_DCKCFGR_SAI1BSRC | (RCC_DCKCFGR_SAI1BSRC_1 >> 16)) /*!< PLL clock used as SAI1 block B clock source */
421 #define LL_RCC_SAI1_B_CLKSOURCE_PLLSRC (uint32_t)(RCC_DCKCFGR_SAI1BSRC | (RCC_DCKCFGR_SAI1BSRC >> 16)) /*!< PLL Main clock used as SAI1 block B clock source */
422 #else
423 #define LL_RCC_SAI1_B_CLKSOURCE_PLLSAI (uint32_t)(RCC_DCKCFGR_SAI1BSRC | 0x00000000U) /*!< PLLSAI clock used as SAI1 block B clock source */
424 #define LL_RCC_SAI1_B_CLKSOURCE_PLLI2S (uint32_t)(RCC_DCKCFGR_SAI1BSRC | (RCC_DCKCFGR_SAI1BSRC_0 >> 16)) /*!< PLLI2S clock used as SAI1 block B clock source */
425 #define LL_RCC_SAI1_B_CLKSOURCE_PIN (uint32_t)(RCC_DCKCFGR_SAI1BSRC | (RCC_DCKCFGR_SAI1BSRC_1 >> 16)) /*!< External pin clock used as SAI1 block B clock source */
426 #endif /* RCC_SAI1B_PLLSOURCE_SUPPORT */
427 #endif /* RCC_DCKCFGR_SAI1BSRC */
428 /**
429 * @}
430 */
431 #endif /* SAI1 */
432
433 #if defined(RCC_DCKCFGR_SDIOSEL) || defined(RCC_DCKCFGR2_SDIOSEL)
434 /** @defgroup RCC_LL_EC_SDIOx_CLKSOURCE Peripheral SDIO clock source selection
435 * @{
436 */
437 #define LL_RCC_SDIO_CLKSOURCE_PLL48CLK 0x00000000U /*!< PLL 48M domain clock used as SDIO clock */
438 #if defined(RCC_DCKCFGR_SDIOSEL)
439 #define LL_RCC_SDIO_CLKSOURCE_SYSCLK RCC_DCKCFGR_SDIOSEL /*!< System clock clock used as SDIO clock */
440 #else
441 #define LL_RCC_SDIO_CLKSOURCE_SYSCLK RCC_DCKCFGR2_SDIOSEL /*!< System clock clock used as SDIO clock */
442 #endif /* RCC_DCKCFGR_SDIOSEL */
443 /**
444 * @}
445 */
446 #endif /* RCC_DCKCFGR_SDIOSEL || RCC_DCKCFGR2_SDIOSEL */
447
448 #if defined(DSI)
449 /** @defgroup RCC_LL_EC_DSI_CLKSOURCE Peripheral DSI clock source selection
450 * @{
451 */
452 #define LL_RCC_DSI_CLKSOURCE_PHY 0x00000000U /*!< DSI-PHY clock used as DSI byte lane clock source */
453 #define LL_RCC_DSI_CLKSOURCE_PLL RCC_DCKCFGR_DSISEL /*!< PLL clock used as DSI byte lane clock source */
454 /**
455 * @}
456 */
457 #endif /* DSI */
458
459 #if defined(CEC)
460 /** @defgroup RCC_LL_EC_CEC_CLKSOURCE Peripheral CEC clock source selection
461 * @{
462 */
463 #define LL_RCC_CEC_CLKSOURCE_HSI_DIV488 0x00000000U /*!< HSI oscillator clock divided by 488 used as CEC clock */
464 #define LL_RCC_CEC_CLKSOURCE_LSE RCC_DCKCFGR2_CECSEL /*!< LSE oscillator clock used as CEC clock */
465 /**
466 * @}
467 */
468 #endif /* CEC */
469
470 /** @defgroup RCC_LL_EC_I2S1_CLKSOURCE Peripheral I2S clock source selection
471 * @{
472 */
473 #if defined(RCC_CFGR_I2SSRC)
474 #define LL_RCC_I2S1_CLKSOURCE_PLLI2S 0x00000000U /*!< I2S oscillator clock used as I2S1 clock */
475 #define LL_RCC_I2S1_CLKSOURCE_PIN RCC_CFGR_I2SSRC /*!< External pin clock used as I2S1 clock */
476 #endif /* RCC_CFGR_I2SSRC */
477 #if defined(RCC_DCKCFGR_I2SSRC)
478 #define LL_RCC_I2S1_CLKSOURCE_PLL (uint32_t)(RCC_DCKCFGR_I2SSRC | 0x00000000U) /*!< PLL clock used as I2S1 clock source */
479 #define LL_RCC_I2S1_CLKSOURCE_PIN (uint32_t)(RCC_DCKCFGR_I2SSRC | (RCC_DCKCFGR_I2SSRC_0 >> 16)) /*!< External pin used as I2S1 clock source */
480 #define LL_RCC_I2S1_CLKSOURCE_PLLSRC (uint32_t)(RCC_DCKCFGR_I2SSRC | (RCC_DCKCFGR_I2SSRC_1 >> 16)) /*!< PLL Main clock used as I2S1 clock source */
481 #endif /* RCC_DCKCFGR_I2SSRC */
482 #if defined(RCC_DCKCFGR_I2S1SRC)
483 #define LL_RCC_I2S1_CLKSOURCE_PLLI2S (uint32_t)(RCC_DCKCFGR_I2S1SRC | 0x00000000U) /*!< PLLI2S clock used as I2S1 clock source */
484 #define LL_RCC_I2S1_CLKSOURCE_PIN (uint32_t)(RCC_DCKCFGR_I2S1SRC | (RCC_DCKCFGR_I2S1SRC_0 >> 16)) /*!< External pin used as I2S1 clock source */
485 #define LL_RCC_I2S1_CLKSOURCE_PLL (uint32_t)(RCC_DCKCFGR_I2S1SRC | (RCC_DCKCFGR_I2S1SRC_1 >> 16)) /*!< PLL clock used as I2S1 clock source */
486 #define LL_RCC_I2S1_CLKSOURCE_PLLSRC (uint32_t)(RCC_DCKCFGR_I2S1SRC | (RCC_DCKCFGR_I2S1SRC >> 16)) /*!< PLL Main clock used as I2S1 clock source */
487 #endif /* RCC_DCKCFGR_I2S1SRC */
488 #if defined(RCC_DCKCFGR_I2S2SRC)
489 #define LL_RCC_I2S2_CLKSOURCE_PLLI2S (uint32_t)(RCC_DCKCFGR_I2S2SRC | 0x00000000U) /*!< PLLI2S clock used as I2S2 clock source */
490 #define LL_RCC_I2S2_CLKSOURCE_PIN (uint32_t)(RCC_DCKCFGR_I2S2SRC | (RCC_DCKCFGR_I2S2SRC_0 >> 16)) /*!< External pin used as I2S2 clock source */
491 #define LL_RCC_I2S2_CLKSOURCE_PLL (uint32_t)(RCC_DCKCFGR_I2S2SRC | (RCC_DCKCFGR_I2S2SRC_1 >> 16)) /*!< PLL clock used as I2S2 clock source */
492 #define LL_RCC_I2S2_CLKSOURCE_PLLSRC (uint32_t)(RCC_DCKCFGR_I2S2SRC | (RCC_DCKCFGR_I2S2SRC >> 16)) /*!< PLL Main clock used as I2S2 clock source */
493 #endif /* RCC_DCKCFGR_I2S2SRC */
494 /**
495 * @}
496 */
497
498 #if defined(RCC_DCKCFGR_CK48MSEL) || defined(RCC_DCKCFGR2_CK48MSEL)
499 /** @defgroup RCC_LL_EC_CK48M_CLKSOURCE Peripheral 48Mhz domain clock source selection
500 * @{
501 */
502 #if defined(RCC_DCKCFGR_CK48MSEL)
503 #define LL_RCC_CK48M_CLKSOURCE_PLL 0x00000000U /*!< PLL oscillator clock used as 48Mhz domain clock */
504 #define LL_RCC_CK48M_CLKSOURCE_PLLSAI RCC_DCKCFGR_CK48MSEL /*!< PLLSAI oscillator clock used as 48Mhz domain clock */
505 #endif /* RCC_DCKCFGR_CK48MSEL */
506 #if defined(RCC_DCKCFGR2_CK48MSEL)
507 #define LL_RCC_CK48M_CLKSOURCE_PLL 0x00000000U /*!< PLL oscillator clock used as 48Mhz domain clock */
508 #if defined(RCC_PLLSAI_SUPPORT)
509 #define LL_RCC_CK48M_CLKSOURCE_PLLSAI RCC_DCKCFGR2_CK48MSEL /*!< PLLSAI oscillator clock used as 48Mhz domain clock */
510 #endif /* RCC_PLLSAI_SUPPORT */
511 #if defined(RCC_PLLI2SCFGR_PLLI2SQ) && !defined(RCC_DCKCFGR_PLLI2SDIVQ)
512 #define LL_RCC_CK48M_CLKSOURCE_PLLI2S RCC_DCKCFGR2_CK48MSEL /*!< PLLI2S oscillator clock used as 48Mhz domain clock */
513 #endif /* RCC_PLLI2SCFGR_PLLI2SQ && !RCC_DCKCFGR_PLLI2SDIVQ */
514 #endif /* RCC_DCKCFGR2_CK48MSEL */
515 /**
516 * @}
517 */
518
519 #if defined(RNG)
520 /** @defgroup RCC_LL_EC_RNG_CLKSOURCE Peripheral RNG clock source selection
521 * @{
522 */
523 #define LL_RCC_RNG_CLKSOURCE_PLL LL_RCC_CK48M_CLKSOURCE_PLL /*!< PLL clock used as RNG clock source */
524 #if defined(RCC_PLLSAI_SUPPORT)
525 #define LL_RCC_RNG_CLKSOURCE_PLLSAI LL_RCC_CK48M_CLKSOURCE_PLLSAI /*!< PLLSAI clock used as RNG clock source */
526 #endif /* RCC_PLLSAI_SUPPORT */
527 #if defined(RCC_PLLI2SCFGR_PLLI2SQ) && !defined(RCC_DCKCFGR_PLLI2SDIVQ)
528 #define LL_RCC_RNG_CLKSOURCE_PLLI2S LL_RCC_CK48M_CLKSOURCE_PLLI2S /*!< PLLI2S clock used as RNG clock source */
529 #endif /* RCC_PLLI2SCFGR_PLLI2SQ && !RCC_DCKCFGR_PLLI2SDIVQ */
530 /**
531 * @}
532 */
533 #endif /* RNG */
534
535 #if defined(USB_OTG_FS) || defined(USB_OTG_HS)
536 /** @defgroup RCC_LL_EC_USB_CLKSOURCE Peripheral USB clock source selection
537 * @{
538 */
539 #define LL_RCC_USB_CLKSOURCE_PLL LL_RCC_CK48M_CLKSOURCE_PLL /*!< PLL clock used as USB clock source */
540 #if defined(RCC_PLLSAI_SUPPORT)
541 #define LL_RCC_USB_CLKSOURCE_PLLSAI LL_RCC_CK48M_CLKSOURCE_PLLSAI /*!< PLLSAI clock used as USB clock source */
542 #endif /* RCC_PLLSAI_SUPPORT */
543 #if defined(RCC_PLLI2SCFGR_PLLI2SQ) && !defined(RCC_DCKCFGR_PLLI2SDIVQ)
544 #define LL_RCC_USB_CLKSOURCE_PLLI2S LL_RCC_CK48M_CLKSOURCE_PLLI2S /*!< PLLI2S clock used as USB clock source */
545 #endif /* RCC_PLLI2SCFGR_PLLI2SQ && !RCC_DCKCFGR_PLLI2SDIVQ */
546 /**
547 * @}
548 */
549 #endif /* USB_OTG_FS || USB_OTG_HS */
550
551 #endif /* RCC_DCKCFGR_CK48MSEL || RCC_DCKCFGR2_CK48MSEL */
552
553 #if defined(DFSDM1_Channel0) || defined(DFSDM2_Channel0)
554 /** @defgroup RCC_LL_EC_DFSDM1_AUDIO_CLKSOURCE Peripheral DFSDM Audio clock source selection
555 * @{
556 */
557 #define LL_RCC_DFSDM1_AUDIO_CLKSOURCE_I2S1 (uint32_t)(RCC_DCKCFGR_CKDFSDM1ASEL | 0x00000000U) /*!< I2S1 clock used as DFSDM1 Audio clock source */
558 #define LL_RCC_DFSDM1_AUDIO_CLKSOURCE_I2S2 (uint32_t)(RCC_DCKCFGR_CKDFSDM1ASEL | (RCC_DCKCFGR_CKDFSDM1ASEL << 16)) /*!< I2S2 clock used as DFSDM1 Audio clock source */
559 #if defined(DFSDM2_Channel0)
560 #define LL_RCC_DFSDM2_AUDIO_CLKSOURCE_I2S1 (uint32_t)(RCC_DCKCFGR_CKDFSDM2ASEL | 0x00000000U) /*!< I2S1 clock used as DFSDM2 Audio clock source */
561 #define LL_RCC_DFSDM2_AUDIO_CLKSOURCE_I2S2 (uint32_t)(RCC_DCKCFGR_CKDFSDM2ASEL | (RCC_DCKCFGR_CKDFSDM2ASEL << 16)) /*!< I2S2 clock used as DFSDM2 Audio clock source */
562 #endif /* DFSDM2_Channel0 */
563 /**
564 * @}
565 */
566
567 /** @defgroup RCC_LL_EC_DFSDM1_CLKSOURCE Peripheral DFSDM clock source selection
568 * @{
569 */
570 #define LL_RCC_DFSDM1_CLKSOURCE_PCLK2 0x00000000U /*!< PCLK2 clock used as DFSDM1 clock */
571 #define LL_RCC_DFSDM1_CLKSOURCE_SYSCLK RCC_DCKCFGR_CKDFSDM1SEL /*!< System clock used as DFSDM1 clock */
572 #if defined(DFSDM2_Channel0)
573 #define LL_RCC_DFSDM2_CLKSOURCE_PCLK2 0x00000000U /*!< PCLK2 clock used as DFSDM2 clock */
574 #define LL_RCC_DFSDM2_CLKSOURCE_SYSCLK RCC_DCKCFGR_CKDFSDM1SEL /*!< System clock used as DFSDM2 clock */
575 #endif /* DFSDM2_Channel0 */
576 /**
577 * @}
578 */
579 #endif /* DFSDM1_Channel0 || DFSDM2_Channel0 */
580
581 #if defined(FMPI2C1)
582 /** @defgroup RCC_LL_EC_FMPI2C1 Peripheral FMPI2C get clock source
583 * @{
584 */
585 #define LL_RCC_FMPI2C1_CLKSOURCE RCC_DCKCFGR2_FMPI2C1SEL /*!< FMPI2C1 Clock source selection */
586 /**
587 * @}
588 */
589 #endif /* FMPI2C1 */
590
591 #if defined(SPDIFRX)
592 /** @defgroup RCC_LL_EC_SPDIFRX_CLKSOURCE Peripheral SPDIFRX clock source selection
593 * @{
594 */
595 #define LL_RCC_SPDIFRX1_CLKSOURCE_PLL 0x00000000U /*!< PLL clock used as SPDIFRX clock source */
596 #define LL_RCC_SPDIFRX1_CLKSOURCE_PLLI2S RCC_DCKCFGR2_SPDIFRXSEL /*!< PLLI2S clock used as SPDIFRX clock source */
597 /**
598 * @}
599 */
600 #endif /* SPDIFRX */
601
602 #if defined(LPTIM1)
603 /** @defgroup RCC_LL_EC_LPTIM1 Peripheral LPTIM get clock source
604 * @{
605 */
606 #define LL_RCC_LPTIM1_CLKSOURCE RCC_DCKCFGR2_LPTIM1SEL /*!< LPTIM1 Clock source selection */
607 /**
608 * @}
609 */
610 #endif /* LPTIM1 */
611
612 #if defined(SAI1)
613 /** @defgroup RCC_LL_EC_SAIx Peripheral SAI get clock source
614 * @{
615 */
616 #if defined(RCC_DCKCFGR_SAI1ASRC)
617 #define LL_RCC_SAI1_A_CLKSOURCE RCC_DCKCFGR_SAI1ASRC /*!< SAI1 block A Clock source selection */
618 #endif /* RCC_DCKCFGR_SAI1ASRC */
619 #if defined(RCC_DCKCFGR_SAI1BSRC)
620 #define LL_RCC_SAI1_B_CLKSOURCE RCC_DCKCFGR_SAI1BSRC /*!< SAI1 block B Clock source selection */
621 #endif /* RCC_DCKCFGR_SAI1BSRC */
622 #if defined(RCC_DCKCFGR_SAI1SRC)
623 #define LL_RCC_SAI1_CLKSOURCE RCC_DCKCFGR_SAI1SRC /*!< SAI1 Clock source selection */
624 #endif /* RCC_DCKCFGR_SAI1SRC */
625 #if defined(RCC_DCKCFGR_SAI2SRC)
626 #define LL_RCC_SAI2_CLKSOURCE RCC_DCKCFGR_SAI2SRC /*!< SAI2 Clock source selection */
627 #endif /* RCC_DCKCFGR_SAI2SRC */
628 /**
629 * @}
630 */
631 #endif /* SAI1 */
632
633 #if defined(SDIO)
634 /** @defgroup RCC_LL_EC_SDIOx Peripheral SDIO get clock source
635 * @{
636 */
637 #if defined(RCC_DCKCFGR_SDIOSEL)
638 #define LL_RCC_SDIO_CLKSOURCE RCC_DCKCFGR_SDIOSEL /*!< SDIO Clock source selection */
639 #elif defined(RCC_DCKCFGR2_SDIOSEL)
640 #define LL_RCC_SDIO_CLKSOURCE RCC_DCKCFGR2_SDIOSEL /*!< SDIO Clock source selection */
641 #else
642 #define LL_RCC_SDIO_CLKSOURCE RCC_PLLCFGR_PLLQ /*!< SDIO Clock source selection */
643 #endif
644 /**
645 * @}
646 */
647 #endif /* SDIO */
648
649 #if defined(RCC_DCKCFGR_CK48MSEL) || defined(RCC_DCKCFGR2_CK48MSEL)
650 /** @defgroup RCC_LL_EC_CK48M Peripheral CK48M get clock source
651 * @{
652 */
653 #if defined(RCC_DCKCFGR_CK48MSEL)
654 #define LL_RCC_CK48M_CLKSOURCE RCC_DCKCFGR_CK48MSEL /*!< CK48M Domain clock source selection */
655 #endif /* RCC_DCKCFGR_CK48MSEL */
656 #if defined(RCC_DCKCFGR2_CK48MSEL)
657 #define LL_RCC_CK48M_CLKSOURCE RCC_DCKCFGR2_CK48MSEL /*!< CK48M Domain clock source selection */
658 #endif /* RCC_DCKCFGR_CK48MSEL */
659 /**
660 * @}
661 */
662 #endif /* RCC_DCKCFGR_CK48MSEL || RCC_DCKCFGR2_CK48MSEL */
663
664 #if defined(RNG)
665 /** @defgroup RCC_LL_EC_RNG Peripheral RNG get clock source
666 * @{
667 */
668 #if defined(RCC_DCKCFGR_CK48MSEL) || defined(RCC_DCKCFGR2_CK48MSEL)
669 #define LL_RCC_RNG_CLKSOURCE LL_RCC_CK48M_CLKSOURCE /*!< RNG Clock source selection */
670 #else
671 #define LL_RCC_RNG_CLKSOURCE RCC_PLLCFGR_PLLQ /*!< RNG Clock source selection */
672 #endif /* RCC_DCKCFGR_CK48MSEL || RCC_DCKCFGR2_CK48MSEL */
673 /**
674 * @}
675 */
676 #endif /* RNG */
677
678 #if defined(USB_OTG_FS) || defined(USB_OTG_HS)
679 /** @defgroup RCC_LL_EC_USB Peripheral USB get clock source
680 * @{
681 */
682 #if defined(RCC_DCKCFGR_CK48MSEL) || defined(RCC_DCKCFGR2_CK48MSEL)
683 #define LL_RCC_USB_CLKSOURCE LL_RCC_CK48M_CLKSOURCE /*!< USB Clock source selection */
684 #else
685 #define LL_RCC_USB_CLKSOURCE RCC_PLLCFGR_PLLQ /*!< USB Clock source selection */
686 #endif /* RCC_DCKCFGR_CK48MSEL || RCC_DCKCFGR2_CK48MSEL */
687 /**
688 * @}
689 */
690 #endif /* USB_OTG_FS || USB_OTG_HS */
691
692 #if defined(CEC)
693 /** @defgroup RCC_LL_EC_CEC Peripheral CEC get clock source
694 * @{
695 */
696 #define LL_RCC_CEC_CLKSOURCE RCC_DCKCFGR2_CECSEL /*!< CEC Clock source selection */
697 /**
698 * @}
699 */
700 #endif /* CEC */
701
702 /** @defgroup RCC_LL_EC_I2S1 Peripheral I2S get clock source
703 * @{
704 */
705 #if defined(RCC_CFGR_I2SSRC)
706 #define LL_RCC_I2S1_CLKSOURCE RCC_CFGR_I2SSRC /*!< I2S1 Clock source selection */
707 #endif /* RCC_CFGR_I2SSRC */
708 #if defined(RCC_DCKCFGR_I2SSRC)
709 #define LL_RCC_I2S1_CLKSOURCE RCC_DCKCFGR_I2SSRC /*!< I2S1 Clock source selection */
710 #endif /* RCC_DCKCFGR_I2SSRC */
711 #if defined(RCC_DCKCFGR_I2S1SRC)
712 #define LL_RCC_I2S1_CLKSOURCE RCC_DCKCFGR_I2S1SRC /*!< I2S1 Clock source selection */
713 #endif /* RCC_DCKCFGR_I2S1SRC */
714 #if defined(RCC_DCKCFGR_I2S2SRC)
715 #define LL_RCC_I2S2_CLKSOURCE RCC_DCKCFGR_I2S2SRC /*!< I2S2 Clock source selection */
716 #endif /* RCC_DCKCFGR_I2S2SRC */
717 /**
718 * @}
719 */
720
721 #if defined(DFSDM1_Channel0) || defined(DFSDM2_Channel0)
722 /** @defgroup RCC_LL_EC_DFSDM_AUDIO Peripheral DFSDM Audio get clock source
723 * @{
724 */
725 #define LL_RCC_DFSDM1_AUDIO_CLKSOURCE RCC_DCKCFGR_CKDFSDM1ASEL /*!< DFSDM1 Audio Clock source selection */
726 #if defined(DFSDM2_Channel0)
727 #define LL_RCC_DFSDM2_AUDIO_CLKSOURCE RCC_DCKCFGR_CKDFSDM2ASEL /*!< DFSDM2 Audio Clock source selection */
728 #endif /* DFSDM2_Channel0 */
729 /**
730 * @}
731 */
732
733 /** @defgroup RCC_LL_EC_DFSDM Peripheral DFSDM get clock source
734 * @{
735 */
736 #define LL_RCC_DFSDM1_CLKSOURCE RCC_DCKCFGR_CKDFSDM1SEL /*!< DFSDM1 Clock source selection */
737 #if defined(DFSDM2_Channel0)
738 #define LL_RCC_DFSDM2_CLKSOURCE RCC_DCKCFGR_CKDFSDM1SEL /*!< DFSDM2 Clock source selection */
739 #endif /* DFSDM2_Channel0 */
740 /**
741 * @}
742 */
743 #endif /* DFSDM1_Channel0 || DFSDM2_Channel0 */
744
745 #if defined(SPDIFRX)
746 /** @defgroup RCC_LL_EC_SPDIFRX Peripheral SPDIFRX get clock source
747 * @{
748 */
749 #define LL_RCC_SPDIFRX1_CLKSOURCE RCC_DCKCFGR2_SPDIFRXSEL /*!< SPDIFRX Clock source selection */
750 /**
751 * @}
752 */
753 #endif /* SPDIFRX */
754
755 #if defined(DSI)
756 /** @defgroup RCC_LL_EC_DSI Peripheral DSI get clock source
757 * @{
758 */
759 #define LL_RCC_DSI_CLKSOURCE RCC_DCKCFGR_DSISEL /*!< DSI Clock source selection */
760 /**
761 * @}
762 */
763 #endif /* DSI */
764
765 #if defined(LTDC)
766 /** @defgroup RCC_LL_EC_LTDC Peripheral LTDC get clock source
767 * @{
768 */
769 #define LL_RCC_LTDC_CLKSOURCE RCC_DCKCFGR_PLLSAIDIVR /*!< LTDC Clock source selection */
770 /**
771 * @}
772 */
773 #endif /* LTDC */
774
775
776 /** @defgroup RCC_LL_EC_RTC_CLKSOURCE RTC clock source selection
777 * @{
778 */
779 #define LL_RCC_RTC_CLKSOURCE_NONE 0x00000000U /*!< No clock used as RTC clock */
780 #define LL_RCC_RTC_CLKSOURCE_LSE RCC_BDCR_RTCSEL_0 /*!< LSE oscillator clock used as RTC clock */
781 #define LL_RCC_RTC_CLKSOURCE_LSI RCC_BDCR_RTCSEL_1 /*!< LSI oscillator clock used as RTC clock */
782 #define LL_RCC_RTC_CLKSOURCE_HSE RCC_BDCR_RTCSEL /*!< HSE oscillator clock divided by HSE prescaler used as RTC clock */
783 /**
784 * @}
785 */
786
787 #if defined(RCC_DCKCFGR_TIMPRE)
788 /** @defgroup RCC_LL_EC_TIM_CLKPRESCALER Timers clocks prescalers selection
789 * @{
790 */
791 #define LL_RCC_TIM_PRESCALER_TWICE 0x00000000U /*!< Timers clock to twice PCLK */
792 #define LL_RCC_TIM_PRESCALER_FOUR_TIMES RCC_DCKCFGR_TIMPRE /*!< Timers clock to four time PCLK */
793 /**
794 * @}
795 */
796 #endif /* RCC_DCKCFGR_TIMPRE */
797
798 /** @defgroup RCC_LL_EC_PLLSOURCE PLL, PLLI2S and PLLSAI entry clock source
799 * @{
800 */
801 #define LL_RCC_PLLSOURCE_HSI RCC_PLLCFGR_PLLSRC_HSI /*!< HSI16 clock selected as PLL entry clock source */
802 #define LL_RCC_PLLSOURCE_HSE RCC_PLLCFGR_PLLSRC_HSE /*!< HSE clock selected as PLL entry clock source */
803 #if defined(RCC_PLLI2SCFGR_PLLI2SSRC)
804 #define LL_RCC_PLLI2SSOURCE_PIN (RCC_PLLI2SCFGR_PLLI2SSRC | 0x80U) /*!< I2S External pin input clock selected as PLLI2S entry clock source */
805 #endif /* RCC_PLLI2SCFGR_PLLI2SSRC */
806 /**
807 * @}
808 */
809
810 /** @defgroup RCC_LL_EC_PLLM_DIV PLL, PLLI2S and PLLSAI division factor
811 * @{
812 */
813 #define LL_RCC_PLLM_DIV_2 (RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 2 */
814 #define LL_RCC_PLLM_DIV_3 (RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 3 */
815 #define LL_RCC_PLLM_DIV_4 (RCC_PLLCFGR_PLLM_2) /*!< PLL, PLLI2S and PLLSAI division factor by 4 */
816 #define LL_RCC_PLLM_DIV_5 (RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 5 */
817 #define LL_RCC_PLLM_DIV_6 (RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 6 */
818 #define LL_RCC_PLLM_DIV_7 (RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 7 */
819 #define LL_RCC_PLLM_DIV_8 (RCC_PLLCFGR_PLLM_3) /*!< PLL, PLLI2S and PLLSAI division factor by 8 */
820 #define LL_RCC_PLLM_DIV_9 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 9 */
821 #define LL_RCC_PLLM_DIV_10 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 10 */
822 #define LL_RCC_PLLM_DIV_11 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 11 */
823 #define LL_RCC_PLLM_DIV_12 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2) /*!< PLL, PLLI2S and PLLSAI division factor by 12 */
824 #define LL_RCC_PLLM_DIV_13 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 13 */
825 #define LL_RCC_PLLM_DIV_14 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 14 */
826 #define LL_RCC_PLLM_DIV_15 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 15 */
827 #define LL_RCC_PLLM_DIV_16 (RCC_PLLCFGR_PLLM_4) /*!< PLL, PLLI2S and PLLSAI division factor by 16 */
828 #define LL_RCC_PLLM_DIV_17 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 17 */
829 #define LL_RCC_PLLM_DIV_18 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 18 */
830 #define LL_RCC_PLLM_DIV_19 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 19 */
831 #define LL_RCC_PLLM_DIV_20 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_2) /*!< PLL, PLLI2S and PLLSAI division factor by 20 */
832 #define LL_RCC_PLLM_DIV_21 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 21 */
833 #define LL_RCC_PLLM_DIV_22 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 22 */
834 #define LL_RCC_PLLM_DIV_23 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 23 */
835 #define LL_RCC_PLLM_DIV_24 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3) /*!< PLL, PLLI2S and PLLSAI division factor by 24 */
836 #define LL_RCC_PLLM_DIV_25 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 25 */
837 #define LL_RCC_PLLM_DIV_26 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 26 */
838 #define LL_RCC_PLLM_DIV_27 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 27 */
839 #define LL_RCC_PLLM_DIV_28 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2) /*!< PLL, PLLI2S and PLLSAI division factor by 28 */
840 #define LL_RCC_PLLM_DIV_29 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 29 */
841 #define LL_RCC_PLLM_DIV_30 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 30 */
842 #define LL_RCC_PLLM_DIV_31 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 31 */
843 #define LL_RCC_PLLM_DIV_32 (RCC_PLLCFGR_PLLM_5) /*!< PLL, PLLI2S and PLLSAI division factor by 32 */
844 #define LL_RCC_PLLM_DIV_33 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 33 */
845 #define LL_RCC_PLLM_DIV_34 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 34 */
846 #define LL_RCC_PLLM_DIV_35 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 35 */
847 #define LL_RCC_PLLM_DIV_36 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_2) /*!< PLL, PLLI2S and PLLSAI division factor by 36 */
848 #define LL_RCC_PLLM_DIV_37 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 37 */
849 #define LL_RCC_PLLM_DIV_38 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 38 */
850 #define LL_RCC_PLLM_DIV_39 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 39 */
851 #define LL_RCC_PLLM_DIV_40 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_3) /*!< PLL, PLLI2S and PLLSAI division factor by 40 */
852 #define LL_RCC_PLLM_DIV_41 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 41 */
853 #define LL_RCC_PLLM_DIV_42 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 42 */
854 #define LL_RCC_PLLM_DIV_43 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 43 */
855 #define LL_RCC_PLLM_DIV_44 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2) /*!< PLL, PLLI2S and PLLSAI division factor by 44 */
856 #define LL_RCC_PLLM_DIV_45 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 45 */
857 #define LL_RCC_PLLM_DIV_46 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 46 */
858 #define LL_RCC_PLLM_DIV_47 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 47 */
859 #define LL_RCC_PLLM_DIV_48 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4) /*!< PLL, PLLI2S and PLLSAI division factor by 48 */
860 #define LL_RCC_PLLM_DIV_49 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 49 */
861 #define LL_RCC_PLLM_DIV_50 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 50 */
862 #define LL_RCC_PLLM_DIV_51 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 51 */
863 #define LL_RCC_PLLM_DIV_52 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_2) /*!< PLL, PLLI2S and PLLSAI division factor by 52 */
864 #define LL_RCC_PLLM_DIV_53 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 53 */
865 #define LL_RCC_PLLM_DIV_54 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 54 */
866 #define LL_RCC_PLLM_DIV_55 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 55 */
867 #define LL_RCC_PLLM_DIV_56 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3) /*!< PLL, PLLI2S and PLLSAI division factor by 56 */
868 #define LL_RCC_PLLM_DIV_57 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 57 */
869 #define LL_RCC_PLLM_DIV_58 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 58 */
870 #define LL_RCC_PLLM_DIV_59 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 59 */
871 #define LL_RCC_PLLM_DIV_60 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2) /*!< PLL, PLLI2S and PLLSAI division factor by 60 */
872 #define LL_RCC_PLLM_DIV_61 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 61 */
873 #define LL_RCC_PLLM_DIV_62 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 62 */
874 #define LL_RCC_PLLM_DIV_63 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 63 */
875 /**
876 * @}
877 */
878
879 #if defined(RCC_PLLCFGR_PLLR)
880 /** @defgroup RCC_LL_EC_PLLR_DIV PLL division factor (PLLR)
881 * @{
882 */
883 #define LL_RCC_PLLR_DIV_2 (RCC_PLLCFGR_PLLR_1) /*!< Main PLL division factor for PLLCLK (system clock) by 2 */
884 #define LL_RCC_PLLR_DIV_3 (RCC_PLLCFGR_PLLR_1|RCC_PLLCFGR_PLLR_0) /*!< Main PLL division factor for PLLCLK (system clock) by 3 */
885 #define LL_RCC_PLLR_DIV_4 (RCC_PLLCFGR_PLLR_2) /*!< Main PLL division factor for PLLCLK (system clock) by 4 */
886 #define LL_RCC_PLLR_DIV_5 (RCC_PLLCFGR_PLLR_2|RCC_PLLCFGR_PLLR_0) /*!< Main PLL division factor for PLLCLK (system clock) by 5 */
887 #define LL_RCC_PLLR_DIV_6 (RCC_PLLCFGR_PLLR_2|RCC_PLLCFGR_PLLR_1) /*!< Main PLL division factor for PLLCLK (system clock) by 6 */
888 #define LL_RCC_PLLR_DIV_7 (RCC_PLLCFGR_PLLR) /*!< Main PLL division factor for PLLCLK (system clock) by 7 */
889 /**
890 * @}
891 */
892 #endif /* RCC_PLLCFGR_PLLR */
893
894 #if defined(RCC_DCKCFGR_PLLDIVR)
895 /** @defgroup RCC_LL_EC_PLLDIVR PLLDIVR division factor (PLLDIVR)
896 * @{
897 */
898 #define LL_RCC_PLLDIVR_DIV_1 (RCC_DCKCFGR_PLLDIVR_0) /*!< PLL division factor for PLLDIVR output by 1 */
899 #define LL_RCC_PLLDIVR_DIV_2 (RCC_DCKCFGR_PLLDIVR_1) /*!< PLL division factor for PLLDIVR output by 2 */
900 #define LL_RCC_PLLDIVR_DIV_3 (RCC_DCKCFGR_PLLDIVR_1 | RCC_DCKCFGR_PLLDIVR_0) /*!< PLL division factor for PLLDIVR output by 3 */
901 #define LL_RCC_PLLDIVR_DIV_4 (RCC_DCKCFGR_PLLDIVR_2) /*!< PLL division factor for PLLDIVR output by 4 */
902 #define LL_RCC_PLLDIVR_DIV_5 (RCC_DCKCFGR_PLLDIVR_2 | RCC_DCKCFGR_PLLDIVR_0) /*!< PLL division factor for PLLDIVR output by 5 */
903 #define LL_RCC_PLLDIVR_DIV_6 (RCC_DCKCFGR_PLLDIVR_2 | RCC_DCKCFGR_PLLDIVR_1) /*!< PLL division factor for PLLDIVR output by 6 */
904 #define LL_RCC_PLLDIVR_DIV_7 (RCC_DCKCFGR_PLLDIVR_2 | RCC_DCKCFGR_PLLDIVR_1 | RCC_DCKCFGR_PLLDIVR_0) /*!< PLL division factor for PLLDIVR output by 7 */
905 #define LL_RCC_PLLDIVR_DIV_8 (RCC_DCKCFGR_PLLDIVR_3) /*!< PLL division factor for PLLDIVR output by 8 */
906 #define LL_RCC_PLLDIVR_DIV_9 (RCC_DCKCFGR_PLLDIVR_3 | RCC_DCKCFGR_PLLDIVR_0) /*!< PLL division factor for PLLDIVR output by 9 */
907 #define LL_RCC_PLLDIVR_DIV_10 (RCC_DCKCFGR_PLLDIVR_3 | RCC_DCKCFGR_PLLDIVR_1) /*!< PLL division factor for PLLDIVR output by 10 */
908 #define LL_RCC_PLLDIVR_DIV_11 (RCC_DCKCFGR_PLLDIVR_3 | RCC_DCKCFGR_PLLDIVR_1 | RCC_DCKCFGR_PLLDIVR_0) /*!< PLL division factor for PLLDIVR output by 11 */
909 #define LL_RCC_PLLDIVR_DIV_12 (RCC_DCKCFGR_PLLDIVR_3 | RCC_DCKCFGR_PLLDIVR_2) /*!< PLL division factor for PLLDIVR output by 12 */
910 #define LL_RCC_PLLDIVR_DIV_13 (RCC_DCKCFGR_PLLDIVR_3 | RCC_DCKCFGR_PLLDIVR_2 | RCC_DCKCFGR_PLLDIVR_0) /*!< PLL division factor for PLLDIVR output by 13 */
911 #define LL_RCC_PLLDIVR_DIV_14 (RCC_DCKCFGR_PLLDIVR_3 | RCC_DCKCFGR_PLLDIVR_2 | RCC_DCKCFGR_PLLDIVR_1) /*!< PLL division factor for PLLDIVR output by 14 */
912 #define LL_RCC_PLLDIVR_DIV_15 (RCC_DCKCFGR_PLLDIVR_3 | RCC_DCKCFGR_PLLDIVR_2 | RCC_DCKCFGR_PLLDIVR_1 | RCC_DCKCFGR_PLLDIVR_0) /*!< PLL division factor for PLLDIVR output by 15 */
913 #define LL_RCC_PLLDIVR_DIV_16 (RCC_DCKCFGR_PLLDIVR_4) /*!< PLL division factor for PLLDIVR output by 16 */
914 #define LL_RCC_PLLDIVR_DIV_17 (RCC_DCKCFGR_PLLDIVR_4 | RCC_DCKCFGR_PLLDIVR_0) /*!< PLL division factor for PLLDIVR output by 17 */
915 #define LL_RCC_PLLDIVR_DIV_18 (RCC_DCKCFGR_PLLDIVR_4 | RCC_DCKCFGR_PLLDIVR_1) /*!< PLL division factor for PLLDIVR output by 18 */
916 #define LL_RCC_PLLDIVR_DIV_19 (RCC_DCKCFGR_PLLDIVR_4 | RCC_DCKCFGR_PLLDIVR_1 | RCC_DCKCFGR_PLLDIVR_0) /*!< PLL division factor for PLLDIVR output by 19 */
917 #define LL_RCC_PLLDIVR_DIV_20 (RCC_DCKCFGR_PLLDIVR_4 | RCC_DCKCFGR_PLLDIVR_2) /*!< PLL division factor for PLLDIVR output by 20 */
918 #define LL_RCC_PLLDIVR_DIV_21 (RCC_DCKCFGR_PLLDIVR_4 | RCC_DCKCFGR_PLLDIVR_2 | RCC_DCKCFGR_PLLDIVR_0) /*!< PLL division factor for PLLDIVR output by 21 */
919 #define LL_RCC_PLLDIVR_DIV_22 (RCC_DCKCFGR_PLLDIVR_4 | RCC_DCKCFGR_PLLDIVR_2 | RCC_DCKCFGR_PLLDIVR_1) /*!< PLL division factor for PLLDIVR output by 22 */
920 #define LL_RCC_PLLDIVR_DIV_23 (RCC_DCKCFGR_PLLDIVR_4 | RCC_DCKCFGR_PLLDIVR_2 | RCC_DCKCFGR_PLLDIVR_1 | RCC_DCKCFGR_PLLDIVR_0) /*!< PLL division factor for PLLDIVR output by 23 */
921 #define LL_RCC_PLLDIVR_DIV_24 (RCC_DCKCFGR_PLLDIVR_4 | RCC_DCKCFGR_PLLDIVR_3) /*!< PLL division factor for PLLDIVR output by 24 */
922 #define LL_RCC_PLLDIVR_DIV_25 (RCC_DCKCFGR_PLLDIVR_4 | RCC_DCKCFGR_PLLDIVR_3 | RCC_DCKCFGR_PLLDIVR_0) /*!< PLL division factor for PLLDIVR output by 25 */
923 #define LL_RCC_PLLDIVR_DIV_26 (RCC_DCKCFGR_PLLDIVR_4 | RCC_DCKCFGR_PLLDIVR_3 | RCC_DCKCFGR_PLLDIVR_1) /*!< PLL division factor for PLLDIVR output by 26 */
924 #define LL_RCC_PLLDIVR_DIV_27 (RCC_DCKCFGR_PLLDIVR_4 | RCC_DCKCFGR_PLLDIVR_3 | RCC_DCKCFGR_PLLDIVR_1 | RCC_DCKCFGR_PLLDIVR_0) /*!< PLL division factor for PLLDIVR output by 27 */
925 #define LL_RCC_PLLDIVR_DIV_28 (RCC_DCKCFGR_PLLDIVR_4 | RCC_DCKCFGR_PLLDIVR_3 | RCC_DCKCFGR_PLLDIVR_2) /*!< PLL division factor for PLLDIVR output by 28 */
926 #define LL_RCC_PLLDIVR_DIV_29 (RCC_DCKCFGR_PLLDIVR_4 | RCC_DCKCFGR_PLLDIVR_3 | RCC_DCKCFGR_PLLDIVR_2 | RCC_DCKCFGR_PLLDIVR_0) /*!< PLL division factor for PLLDIVR output by 29 */
927 #define LL_RCC_PLLDIVR_DIV_30 (RCC_DCKCFGR_PLLDIVR_4 | RCC_DCKCFGR_PLLDIVR_3 | RCC_DCKCFGR_PLLDIVR_2 | RCC_DCKCFGR_PLLDIVR_1) /*!< PLL division factor for PLLDIVR output by 30 */
928 #define LL_RCC_PLLDIVR_DIV_31 (RCC_DCKCFGR_PLLDIVR_4 | RCC_DCKCFGR_PLLDIVR_3 | RCC_DCKCFGR_PLLDIVR_2 | RCC_DCKCFGR_PLLDIVR_1 | RCC_DCKCFGR_PLLDIVR_0) /*!< PLL division factor for PLLDIVR output by 31 */
929 /**
930 * @}
931 */
932 #endif /* RCC_DCKCFGR_PLLDIVR */
933
934 /** @defgroup RCC_LL_EC_PLLP_DIV PLL division factor (PLLP)
935 * @{
936 */
937 #define LL_RCC_PLLP_DIV_2 0x00000000U /*!< Main PLL division factor for PLLP output by 2 */
938 #define LL_RCC_PLLP_DIV_4 RCC_PLLCFGR_PLLP_0 /*!< Main PLL division factor for PLLP output by 4 */
939 #define LL_RCC_PLLP_DIV_6 RCC_PLLCFGR_PLLP_1 /*!< Main PLL division factor for PLLP output by 6 */
940 #define LL_RCC_PLLP_DIV_8 (RCC_PLLCFGR_PLLP_1 | RCC_PLLCFGR_PLLP_0) /*!< Main PLL division factor for PLLP output by 8 */
941 /**
942 * @}
943 */
944
945 /** @defgroup RCC_LL_EC_PLLQ_DIV PLL division factor (PLLQ)
946 * @{
947 */
948 #define LL_RCC_PLLQ_DIV_2 RCC_PLLCFGR_PLLQ_1 /*!< Main PLL division factor for PLLQ output by 2 */
949 #define LL_RCC_PLLQ_DIV_3 (RCC_PLLCFGR_PLLQ_1|RCC_PLLCFGR_PLLQ_0) /*!< Main PLL division factor for PLLQ output by 3 */
950 #define LL_RCC_PLLQ_DIV_4 RCC_PLLCFGR_PLLQ_2 /*!< Main PLL division factor for PLLQ output by 4 */
951 #define LL_RCC_PLLQ_DIV_5 (RCC_PLLCFGR_PLLQ_2|RCC_PLLCFGR_PLLQ_0) /*!< Main PLL division factor for PLLQ output by 5 */
952 #define LL_RCC_PLLQ_DIV_6 (RCC_PLLCFGR_PLLQ_2|RCC_PLLCFGR_PLLQ_1) /*!< Main PLL division factor for PLLQ output by 6 */
953 #define LL_RCC_PLLQ_DIV_7 (RCC_PLLCFGR_PLLQ_2|RCC_PLLCFGR_PLLQ_1|RCC_PLLCFGR_PLLQ_0) /*!< Main PLL division factor for PLLQ output by 7 */
954 #define LL_RCC_PLLQ_DIV_8 RCC_PLLCFGR_PLLQ_3 /*!< Main PLL division factor for PLLQ output by 8 */
955 #define LL_RCC_PLLQ_DIV_9 (RCC_PLLCFGR_PLLQ_3|RCC_PLLCFGR_PLLQ_0) /*!< Main PLL division factor for PLLQ output by 9 */
956 #define LL_RCC_PLLQ_DIV_10 (RCC_PLLCFGR_PLLQ_3|RCC_PLLCFGR_PLLQ_1) /*!< Main PLL division factor for PLLQ output by 10 */
957 #define LL_RCC_PLLQ_DIV_11 (RCC_PLLCFGR_PLLQ_3|RCC_PLLCFGR_PLLQ_1|RCC_PLLCFGR_PLLQ_0) /*!< Main PLL division factor for PLLQ output by 11 */
958 #define LL_RCC_PLLQ_DIV_12 (RCC_PLLCFGR_PLLQ_3|RCC_PLLCFGR_PLLQ_2) /*!< Main PLL division factor for PLLQ output by 12 */
959 #define LL_RCC_PLLQ_DIV_13 (RCC_PLLCFGR_PLLQ_3|RCC_PLLCFGR_PLLQ_2|RCC_PLLCFGR_PLLQ_0) /*!< Main PLL division factor for PLLQ output by 13 */
960 #define LL_RCC_PLLQ_DIV_14 (RCC_PLLCFGR_PLLQ_3|RCC_PLLCFGR_PLLQ_2|RCC_PLLCFGR_PLLQ_1) /*!< Main PLL division factor for PLLQ output by 14 */
961 #define LL_RCC_PLLQ_DIV_15 (RCC_PLLCFGR_PLLQ_3|RCC_PLLCFGR_PLLQ_2|RCC_PLLCFGR_PLLQ_1|RCC_PLLCFGR_PLLQ_0) /*!< Main PLL division factor for PLLQ output by 15 */
962 /**
963 * @}
964 */
965
966 /** @defgroup RCC_LL_EC_PLL_SPRE_SEL PLL Spread Spectrum Selection
967 * @{
968 */
969 #define LL_RCC_SPREAD_SELECT_CENTER 0x00000000U /*!< PLL center spread spectrum selection */
970 #define LL_RCC_SPREAD_SELECT_DOWN RCC_SSCGR_SPREADSEL /*!< PLL down spread spectrum selection */
971 /**
972 * @}
973 */
974
975 #if defined(RCC_PLLI2S_SUPPORT)
976 /** @defgroup RCC_LL_EC_PLLI2SM PLLI2SM division factor (PLLI2SM)
977 * @{
978 */
979 #if defined(RCC_PLLI2SCFGR_PLLI2SM)
980 #define LL_RCC_PLLI2SM_DIV_2 (RCC_PLLI2SCFGR_PLLI2SM_1) /*!< PLLI2S division factor for PLLI2SM output by 2 */
981 #define LL_RCC_PLLI2SM_DIV_3 (RCC_PLLI2SCFGR_PLLI2SM_1 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 3 */
982 #define LL_RCC_PLLI2SM_DIV_4 (RCC_PLLI2SCFGR_PLLI2SM_2) /*!< PLLI2S division factor for PLLI2SM output by 4 */
983 #define LL_RCC_PLLI2SM_DIV_5 (RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 5 */
984 #define LL_RCC_PLLI2SM_DIV_6 (RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_1) /*!< PLLI2S division factor for PLLI2SM output by 6 */
985 #define LL_RCC_PLLI2SM_DIV_7 (RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_1 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 7 */
986 #define LL_RCC_PLLI2SM_DIV_8 (RCC_PLLI2SCFGR_PLLI2SM_3) /*!< PLLI2S division factor for PLLI2SM output by 8 */
987 #define LL_RCC_PLLI2SM_DIV_9 (RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 9 */
988 #define LL_RCC_PLLI2SM_DIV_10 (RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_1) /*!< PLLI2S division factor for PLLI2SM output by 10 */
989 #define LL_RCC_PLLI2SM_DIV_11 (RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_1 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 11 */
990 #define LL_RCC_PLLI2SM_DIV_12 (RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_2) /*!< PLLI2S division factor for PLLI2SM output by 12 */
991 #define LL_RCC_PLLI2SM_DIV_13 (RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 13 */
992 #define LL_RCC_PLLI2SM_DIV_14 (RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_1) /*!< PLLI2S division factor for PLLI2SM output by 14 */
993 #define LL_RCC_PLLI2SM_DIV_15 (RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_1 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 15 */
994 #define LL_RCC_PLLI2SM_DIV_16 (RCC_PLLI2SCFGR_PLLI2SM_4) /*!< PLLI2S division factor for PLLI2SM output by 16 */
995 #define LL_RCC_PLLI2SM_DIV_17 (RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 17 */
996 #define LL_RCC_PLLI2SM_DIV_18 (RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_1) /*!< PLLI2S division factor for PLLI2SM output by 18 */
997 #define LL_RCC_PLLI2SM_DIV_19 (RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_1 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 19 */
998 #define LL_RCC_PLLI2SM_DIV_20 (RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_2) /*!< PLLI2S division factor for PLLI2SM output by 20 */
999 #define LL_RCC_PLLI2SM_DIV_21 (RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 21 */
1000 #define LL_RCC_PLLI2SM_DIV_22 (RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_1) /*!< PLLI2S division factor for PLLI2SM output by 22 */
1001 #define LL_RCC_PLLI2SM_DIV_23 (RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_1 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 23 */
1002 #define LL_RCC_PLLI2SM_DIV_24 (RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_3) /*!< PLLI2S division factor for PLLI2SM output by 24 */
1003 #define LL_RCC_PLLI2SM_DIV_25 (RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 25 */
1004 #define LL_RCC_PLLI2SM_DIV_26 (RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_1) /*!< PLLI2S division factor for PLLI2SM output by 26 */
1005 #define LL_RCC_PLLI2SM_DIV_27 (RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_1 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 27 */
1006 #define LL_RCC_PLLI2SM_DIV_28 (RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_2) /*!< PLLI2S division factor for PLLI2SM output by 28 */
1007 #define LL_RCC_PLLI2SM_DIV_29 (RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 29 */
1008 #define LL_RCC_PLLI2SM_DIV_30 (RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_1) /*!< PLLI2S division factor for PLLI2SM output by 30 */
1009 #define LL_RCC_PLLI2SM_DIV_31 (RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_1 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 31 */
1010 #define LL_RCC_PLLI2SM_DIV_32 (RCC_PLLI2SCFGR_PLLI2SM_5) /*!< PLLI2S division factor for PLLI2SM output by 32 */
1011 #define LL_RCC_PLLI2SM_DIV_33 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 33 */
1012 #define LL_RCC_PLLI2SM_DIV_34 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_1) /*!< PLLI2S division factor for PLLI2SM output by 34 */
1013 #define LL_RCC_PLLI2SM_DIV_35 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_1 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 35 */
1014 #define LL_RCC_PLLI2SM_DIV_36 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_2) /*!< PLLI2S division factor for PLLI2SM output by 36 */
1015 #define LL_RCC_PLLI2SM_DIV_37 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 37 */
1016 #define LL_RCC_PLLI2SM_DIV_38 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_1) /*!< PLLI2S division factor for PLLI2SM output by 38 */
1017 #define LL_RCC_PLLI2SM_DIV_39 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_1 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 39 */
1018 #define LL_RCC_PLLI2SM_DIV_40 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_3) /*!< PLLI2S division factor for PLLI2SM output by 40 */
1019 #define LL_RCC_PLLI2SM_DIV_41 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 41 */
1020 #define LL_RCC_PLLI2SM_DIV_42 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_1) /*!< PLLI2S division factor for PLLI2SM output by 42 */
1021 #define LL_RCC_PLLI2SM_DIV_43 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_1 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 43 */
1022 #define LL_RCC_PLLI2SM_DIV_44 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_2) /*!< PLLI2S division factor for PLLI2SM output by 44 */
1023 #define LL_RCC_PLLI2SM_DIV_45 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 45 */
1024 #define LL_RCC_PLLI2SM_DIV_46 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_1) /*!< PLLI2S division factor for PLLI2SM output by 46 */
1025 #define LL_RCC_PLLI2SM_DIV_47 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_1 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 47 */
1026 #define LL_RCC_PLLI2SM_DIV_48 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_4) /*!< PLLI2S division factor for PLLI2SM output by 48 */
1027 #define LL_RCC_PLLI2SM_DIV_49 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 49 */
1028 #define LL_RCC_PLLI2SM_DIV_50 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_1) /*!< PLLI2S division factor for PLLI2SM output by 50 */
1029 #define LL_RCC_PLLI2SM_DIV_51 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_1 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 51 */
1030 #define LL_RCC_PLLI2SM_DIV_52 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_2) /*!< PLLI2S division factor for PLLI2SM output by 52 */
1031 #define LL_RCC_PLLI2SM_DIV_53 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 53 */
1032 #define LL_RCC_PLLI2SM_DIV_54 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_1) /*!< PLLI2S division factor for PLLI2SM output by 54 */
1033 #define LL_RCC_PLLI2SM_DIV_55 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_1 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 55 */
1034 #define LL_RCC_PLLI2SM_DIV_56 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_3) /*!< PLLI2S division factor for PLLI2SM output by 56 */
1035 #define LL_RCC_PLLI2SM_DIV_57 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 57 */
1036 #define LL_RCC_PLLI2SM_DIV_58 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_1) /*!< PLLI2S division factor for PLLI2SM output by 58 */
1037 #define LL_RCC_PLLI2SM_DIV_59 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_1 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 59 */
1038 #define LL_RCC_PLLI2SM_DIV_60 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_2) /*!< PLLI2S division factor for PLLI2SM output by 60 */
1039 #define LL_RCC_PLLI2SM_DIV_61 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 61 */
1040 #define LL_RCC_PLLI2SM_DIV_62 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_1) /*!< PLLI2S division factor for PLLI2SM output by 62 */
1041 #define LL_RCC_PLLI2SM_DIV_63 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_1 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 63 */
1042 #else
1043 #define LL_RCC_PLLI2SM_DIV_2 LL_RCC_PLLM_DIV_2 /*!< PLLI2S division factor for PLLI2SM output by 2 */
1044 #define LL_RCC_PLLI2SM_DIV_3 LL_RCC_PLLM_DIV_3 /*!< PLLI2S division factor for PLLI2SM output by 3 */
1045 #define LL_RCC_PLLI2SM_DIV_4 LL_RCC_PLLM_DIV_4 /*!< PLLI2S division factor for PLLI2SM output by 4 */
1046 #define LL_RCC_PLLI2SM_DIV_5 LL_RCC_PLLM_DIV_5 /*!< PLLI2S division factor for PLLI2SM output by 5 */
1047 #define LL_RCC_PLLI2SM_DIV_6 LL_RCC_PLLM_DIV_6 /*!< PLLI2S division factor for PLLI2SM output by 6 */
1048 #define LL_RCC_PLLI2SM_DIV_7 LL_RCC_PLLM_DIV_7 /*!< PLLI2S division factor for PLLI2SM output by 7 */
1049 #define LL_RCC_PLLI2SM_DIV_8 LL_RCC_PLLM_DIV_8 /*!< PLLI2S division factor for PLLI2SM output by 8 */
1050 #define LL_RCC_PLLI2SM_DIV_9 LL_RCC_PLLM_DIV_9 /*!< PLLI2S division factor for PLLI2SM output by 9 */
1051 #define LL_RCC_PLLI2SM_DIV_10 LL_RCC_PLLM_DIV_10 /*!< PLLI2S division factor for PLLI2SM output by 10 */
1052 #define LL_RCC_PLLI2SM_DIV_11 LL_RCC_PLLM_DIV_11 /*!< PLLI2S division factor for PLLI2SM output by 11 */
1053 #define LL_RCC_PLLI2SM_DIV_12 LL_RCC_PLLM_DIV_12 /*!< PLLI2S division factor for PLLI2SM output by 12 */
1054 #define LL_RCC_PLLI2SM_DIV_13 LL_RCC_PLLM_DIV_13 /*!< PLLI2S division factor for PLLI2SM output by 13 */
1055 #define LL_RCC_PLLI2SM_DIV_14 LL_RCC_PLLM_DIV_14 /*!< PLLI2S division factor for PLLI2SM output by 14 */
1056 #define LL_RCC_PLLI2SM_DIV_15 LL_RCC_PLLM_DIV_15 /*!< PLLI2S division factor for PLLI2SM output by 15 */
1057 #define LL_RCC_PLLI2SM_DIV_16 LL_RCC_PLLM_DIV_16 /*!< PLLI2S division factor for PLLI2SM output by 16 */
1058 #define LL_RCC_PLLI2SM_DIV_17 LL_RCC_PLLM_DIV_17 /*!< PLLI2S division factor for PLLI2SM output by 17 */
1059 #define LL_RCC_PLLI2SM_DIV_18 LL_RCC_PLLM_DIV_18 /*!< PLLI2S division factor for PLLI2SM output by 18 */
1060 #define LL_RCC_PLLI2SM_DIV_19 LL_RCC_PLLM_DIV_19 /*!< PLLI2S division factor for PLLI2SM output by 19 */
1061 #define LL_RCC_PLLI2SM_DIV_20 LL_RCC_PLLM_DIV_20 /*!< PLLI2S division factor for PLLI2SM output by 20 */
1062 #define LL_RCC_PLLI2SM_DIV_21 LL_RCC_PLLM_DIV_21 /*!< PLLI2S division factor for PLLI2SM output by 21 */
1063 #define LL_RCC_PLLI2SM_DIV_22 LL_RCC_PLLM_DIV_22 /*!< PLLI2S division factor for PLLI2SM output by 22 */
1064 #define LL_RCC_PLLI2SM_DIV_23 LL_RCC_PLLM_DIV_23 /*!< PLLI2S division factor for PLLI2SM output by 23 */
1065 #define LL_RCC_PLLI2SM_DIV_24 LL_RCC_PLLM_DIV_24 /*!< PLLI2S division factor for PLLI2SM output by 24 */
1066 #define LL_RCC_PLLI2SM_DIV_25 LL_RCC_PLLM_DIV_25 /*!< PLLI2S division factor for PLLI2SM output by 25 */
1067 #define LL_RCC_PLLI2SM_DIV_26 LL_RCC_PLLM_DIV_26 /*!< PLLI2S division factor for PLLI2SM output by 26 */
1068 #define LL_RCC_PLLI2SM_DIV_27 LL_RCC_PLLM_DIV_27 /*!< PLLI2S division factor for PLLI2SM output by 27 */
1069 #define LL_RCC_PLLI2SM_DIV_28 LL_RCC_PLLM_DIV_28 /*!< PLLI2S division factor for PLLI2SM output by 28 */
1070 #define LL_RCC_PLLI2SM_DIV_29 LL_RCC_PLLM_DIV_29 /*!< PLLI2S division factor for PLLI2SM output by 29 */
1071 #define LL_RCC_PLLI2SM_DIV_30 LL_RCC_PLLM_DIV_30 /*!< PLLI2S division factor for PLLI2SM output by 30 */
1072 #define LL_RCC_PLLI2SM_DIV_31 LL_RCC_PLLM_DIV_31 /*!< PLLI2S division factor for PLLI2SM output by 31 */
1073 #define LL_RCC_PLLI2SM_DIV_32 LL_RCC_PLLM_DIV_32 /*!< PLLI2S division factor for PLLI2SM output by 32 */
1074 #define LL_RCC_PLLI2SM_DIV_33 LL_RCC_PLLM_DIV_33 /*!< PLLI2S division factor for PLLI2SM output by 33 */
1075 #define LL_RCC_PLLI2SM_DIV_34 LL_RCC_PLLM_DIV_34 /*!< PLLI2S division factor for PLLI2SM output by 34 */
1076 #define LL_RCC_PLLI2SM_DIV_35 LL_RCC_PLLM_DIV_35 /*!< PLLI2S division factor for PLLI2SM output by 35 */
1077 #define LL_RCC_PLLI2SM_DIV_36 LL_RCC_PLLM_DIV_36 /*!< PLLI2S division factor for PLLI2SM output by 36 */
1078 #define LL_RCC_PLLI2SM_DIV_37 LL_RCC_PLLM_DIV_37 /*!< PLLI2S division factor for PLLI2SM output by 37 */
1079 #define LL_RCC_PLLI2SM_DIV_38 LL_RCC_PLLM_DIV_38 /*!< PLLI2S division factor for PLLI2SM output by 38 */
1080 #define LL_RCC_PLLI2SM_DIV_39 LL_RCC_PLLM_DIV_39 /*!< PLLI2S division factor for PLLI2SM output by 39 */
1081 #define LL_RCC_PLLI2SM_DIV_40 LL_RCC_PLLM_DIV_40 /*!< PLLI2S division factor for PLLI2SM output by 40 */
1082 #define LL_RCC_PLLI2SM_DIV_41 LL_RCC_PLLM_DIV_41 /*!< PLLI2S division factor for PLLI2SM output by 41 */
1083 #define LL_RCC_PLLI2SM_DIV_42 LL_RCC_PLLM_DIV_42 /*!< PLLI2S division factor for PLLI2SM output by 42 */
1084 #define LL_RCC_PLLI2SM_DIV_43 LL_RCC_PLLM_DIV_43 /*!< PLLI2S division factor for PLLI2SM output by 43 */
1085 #define LL_RCC_PLLI2SM_DIV_44 LL_RCC_PLLM_DIV_44 /*!< PLLI2S division factor for PLLI2SM output by 44 */
1086 #define LL_RCC_PLLI2SM_DIV_45 LL_RCC_PLLM_DIV_45 /*!< PLLI2S division factor for PLLI2SM output by 45 */
1087 #define LL_RCC_PLLI2SM_DIV_46 LL_RCC_PLLM_DIV_46 /*!< PLLI2S division factor for PLLI2SM output by 46 */
1088 #define LL_RCC_PLLI2SM_DIV_47 LL_RCC_PLLM_DIV_47 /*!< PLLI2S division factor for PLLI2SM output by 47 */
1089 #define LL_RCC_PLLI2SM_DIV_48 LL_RCC_PLLM_DIV_48 /*!< PLLI2S division factor for PLLI2SM output by 48 */
1090 #define LL_RCC_PLLI2SM_DIV_49 LL_RCC_PLLM_DIV_49 /*!< PLLI2S division factor for PLLI2SM output by 49 */
1091 #define LL_RCC_PLLI2SM_DIV_50 LL_RCC_PLLM_DIV_50 /*!< PLLI2S division factor for PLLI2SM output by 50 */
1092 #define LL_RCC_PLLI2SM_DIV_51 LL_RCC_PLLM_DIV_51 /*!< PLLI2S division factor for PLLI2SM output by 51 */
1093 #define LL_RCC_PLLI2SM_DIV_52 LL_RCC_PLLM_DIV_52 /*!< PLLI2S division factor for PLLI2SM output by 52 */
1094 #define LL_RCC_PLLI2SM_DIV_53 LL_RCC_PLLM_DIV_53 /*!< PLLI2S division factor for PLLI2SM output by 53 */
1095 #define LL_RCC_PLLI2SM_DIV_54 LL_RCC_PLLM_DIV_54 /*!< PLLI2S division factor for PLLI2SM output by 54 */
1096 #define LL_RCC_PLLI2SM_DIV_55 LL_RCC_PLLM_DIV_55 /*!< PLLI2S division factor for PLLI2SM output by 55 */
1097 #define LL_RCC_PLLI2SM_DIV_56 LL_RCC_PLLM_DIV_56 /*!< PLLI2S division factor for PLLI2SM output by 56 */
1098 #define LL_RCC_PLLI2SM_DIV_57 LL_RCC_PLLM_DIV_57 /*!< PLLI2S division factor for PLLI2SM output by 57 */
1099 #define LL_RCC_PLLI2SM_DIV_58 LL_RCC_PLLM_DIV_58 /*!< PLLI2S division factor for PLLI2SM output by 58 */
1100 #define LL_RCC_PLLI2SM_DIV_59 LL_RCC_PLLM_DIV_59 /*!< PLLI2S division factor for PLLI2SM output by 59 */
1101 #define LL_RCC_PLLI2SM_DIV_60 LL_RCC_PLLM_DIV_60 /*!< PLLI2S division factor for PLLI2SM output by 60 */
1102 #define LL_RCC_PLLI2SM_DIV_61 LL_RCC_PLLM_DIV_61 /*!< PLLI2S division factor for PLLI2SM output by 61 */
1103 #define LL_RCC_PLLI2SM_DIV_62 LL_RCC_PLLM_DIV_62 /*!< PLLI2S division factor for PLLI2SM output by 62 */
1104 #define LL_RCC_PLLI2SM_DIV_63 LL_RCC_PLLM_DIV_63 /*!< PLLI2S division factor for PLLI2SM output by 63 */
1105 #endif /* RCC_PLLI2SCFGR_PLLI2SM */
1106 /**
1107 * @}
1108 */
1109
1110 #if defined(RCC_PLLI2SCFGR_PLLI2SQ)
1111 /** @defgroup RCC_LL_EC_PLLI2SQ PLLI2SQ division factor (PLLI2SQ)
1112 * @{
1113 */
1114 #define LL_RCC_PLLI2SQ_DIV_2 RCC_PLLI2SCFGR_PLLI2SQ_1 /*!< PLLI2S division factor for PLLI2SQ output by 2 */
1115 #define LL_RCC_PLLI2SQ_DIV_3 (RCC_PLLI2SCFGR_PLLI2SQ_1 | RCC_PLLI2SCFGR_PLLI2SQ_0) /*!< PLLI2S division factor for PLLI2SQ output by 3 */
1116 #define LL_RCC_PLLI2SQ_DIV_4 RCC_PLLI2SCFGR_PLLI2SQ_2 /*!< PLLI2S division factor for PLLI2SQ output by 4 */
1117 #define LL_RCC_PLLI2SQ_DIV_5 (RCC_PLLI2SCFGR_PLLI2SQ_2 | RCC_PLLI2SCFGR_PLLI2SQ_0) /*!< PLLI2S division factor for PLLI2SQ output by 5 */
1118 #define LL_RCC_PLLI2SQ_DIV_6 (RCC_PLLI2SCFGR_PLLI2SQ_2 | RCC_PLLI2SCFGR_PLLI2SQ_1) /*!< PLLI2S division factor for PLLI2SQ output by 6 */
1119 #define LL_RCC_PLLI2SQ_DIV_7 (RCC_PLLI2SCFGR_PLLI2SQ_2 | RCC_PLLI2SCFGR_PLLI2SQ_1 | RCC_PLLI2SCFGR_PLLI2SQ_0) /*!< PLLI2S division factor for PLLI2SQ output by 7 */
1120 #define LL_RCC_PLLI2SQ_DIV_8 RCC_PLLI2SCFGR_PLLI2SQ_3 /*!< PLLI2S division factor for PLLI2SQ output by 8 */
1121 #define LL_RCC_PLLI2SQ_DIV_9 (RCC_PLLI2SCFGR_PLLI2SQ_3 | RCC_PLLI2SCFGR_PLLI2SQ_0) /*!< PLLI2S division factor for PLLI2SQ output by 9 */
1122 #define LL_RCC_PLLI2SQ_DIV_10 (RCC_PLLI2SCFGR_PLLI2SQ_3 | RCC_PLLI2SCFGR_PLLI2SQ_1) /*!< PLLI2S division factor for PLLI2SQ output by 10 */
1123 #define LL_RCC_PLLI2SQ_DIV_11 (RCC_PLLI2SCFGR_PLLI2SQ_3 | RCC_PLLI2SCFGR_PLLI2SQ_1 | RCC_PLLI2SCFGR_PLLI2SQ_0) /*!< PLLI2S division factor for PLLI2SQ output by 11 */
1124 #define LL_RCC_PLLI2SQ_DIV_12 (RCC_PLLI2SCFGR_PLLI2SQ_3 | RCC_PLLI2SCFGR_PLLI2SQ_2) /*!< PLLI2S division factor for PLLI2SQ output by 12 */
1125 #define LL_RCC_PLLI2SQ_DIV_13 (RCC_PLLI2SCFGR_PLLI2SQ_3 | RCC_PLLI2SCFGR_PLLI2SQ_2 | RCC_PLLI2SCFGR_PLLI2SQ_0) /*!< PLLI2S division factor for PLLI2SQ output by 13 */
1126 #define LL_RCC_PLLI2SQ_DIV_14 (RCC_PLLI2SCFGR_PLLI2SQ_3 | RCC_PLLI2SCFGR_PLLI2SQ_2 | RCC_PLLI2SCFGR_PLLI2SQ_1) /*!< PLLI2S division factor for PLLI2SQ output by 14 */
1127 #define LL_RCC_PLLI2SQ_DIV_15 (RCC_PLLI2SCFGR_PLLI2SQ_3 | RCC_PLLI2SCFGR_PLLI2SQ_2 | RCC_PLLI2SCFGR_PLLI2SQ_1 | RCC_PLLI2SCFGR_PLLI2SQ_0) /*!< PLLI2S division factor for PLLI2SQ output by 15 */
1128 /**
1129 * @}
1130 */
1131 #endif /* RCC_PLLI2SCFGR_PLLI2SQ */
1132
1133 #if defined(RCC_DCKCFGR_PLLI2SDIVQ)
1134 /** @defgroup RCC_LL_EC_PLLI2SDIVQ PLLI2SDIVQ division factor (PLLI2SDIVQ)
1135 * @{
1136 */
1137 #define LL_RCC_PLLI2SDIVQ_DIV_1 0x00000000U /*!< PLLI2S division factor for PLLI2SDIVQ output by 1 */
1138 #define LL_RCC_PLLI2SDIVQ_DIV_2 RCC_DCKCFGR_PLLI2SDIVQ_0 /*!< PLLI2S division factor for PLLI2SDIVQ output by 2 */
1139 #define LL_RCC_PLLI2SDIVQ_DIV_3 RCC_DCKCFGR_PLLI2SDIVQ_1 /*!< PLLI2S division factor for PLLI2SDIVQ output by 3 */
1140 #define LL_RCC_PLLI2SDIVQ_DIV_4 (RCC_DCKCFGR_PLLI2SDIVQ_1 | RCC_DCKCFGR_PLLI2SDIVQ_0) /*!< PLLI2S division factor for PLLI2SDIVQ output by 4 */
1141 #define LL_RCC_PLLI2SDIVQ_DIV_5 RCC_DCKCFGR_PLLI2SDIVQ_2 /*!< PLLI2S division factor for PLLI2SDIVQ output by 5 */
1142 #define LL_RCC_PLLI2SDIVQ_DIV_6 (RCC_DCKCFGR_PLLI2SDIVQ_2 | RCC_DCKCFGR_PLLI2SDIVQ_0) /*!< PLLI2S division factor for PLLI2SDIVQ output by 6 */
1143 #define LL_RCC_PLLI2SDIVQ_DIV_7 (RCC_DCKCFGR_PLLI2SDIVQ_2 | RCC_DCKCFGR_PLLI2SDIVQ_1) /*!< PLLI2S division factor for PLLI2SDIVQ output by 7 */
1144 #define LL_RCC_PLLI2SDIVQ_DIV_8 (RCC_DCKCFGR_PLLI2SDIVQ_2 | RCC_DCKCFGR_PLLI2SDIVQ_1 | RCC_DCKCFGR_PLLI2SDIVQ_0) /*!< PLLI2S division factor for PLLI2SDIVQ output by 8 */
1145 #define LL_RCC_PLLI2SDIVQ_DIV_9 RCC_DCKCFGR_PLLI2SDIVQ_3 /*!< PLLI2S division factor for PLLI2SDIVQ output by 9 */
1146 #define LL_RCC_PLLI2SDIVQ_DIV_10 (RCC_DCKCFGR_PLLI2SDIVQ_3 | RCC_DCKCFGR_PLLI2SDIVQ_0) /*!< PLLI2S division factor for PLLI2SDIVQ output by 10 */
1147 #define LL_RCC_PLLI2SDIVQ_DIV_11 (RCC_DCKCFGR_PLLI2SDIVQ_3 | RCC_DCKCFGR_PLLI2SDIVQ_1) /*!< PLLI2S division factor for PLLI2SDIVQ output by 11 */
1148 #define LL_RCC_PLLI2SDIVQ_DIV_12 (RCC_DCKCFGR_PLLI2SDIVQ_3 | RCC_DCKCFGR_PLLI2SDIVQ_1 | RCC_DCKCFGR_PLLI2SDIVQ_0) /*!< PLLI2S division factor for PLLI2SDIVQ output by 12 */
1149 #define LL_RCC_PLLI2SDIVQ_DIV_13 (RCC_DCKCFGR_PLLI2SDIVQ_3 | RCC_DCKCFGR_PLLI2SDIVQ_2) /*!< PLLI2S division factor for PLLI2SDIVQ output by 13 */
1150 #define LL_RCC_PLLI2SDIVQ_DIV_14 (RCC_DCKCFGR_PLLI2SDIVQ_3 | RCC_DCKCFGR_PLLI2SDIVQ_2 | RCC_DCKCFGR_PLLI2SDIVQ_0) /*!< PLLI2S division factor for PLLI2SDIVQ output by 14 */
1151 #define LL_RCC_PLLI2SDIVQ_DIV_15 (RCC_DCKCFGR_PLLI2SDIVQ_3 | RCC_DCKCFGR_PLLI2SDIVQ_2 | RCC_DCKCFGR_PLLI2SDIVQ_1) /*!< PLLI2S division factor for PLLI2SDIVQ output by 15 */
1152 #define LL_RCC_PLLI2SDIVQ_DIV_16 (RCC_DCKCFGR_PLLI2SDIVQ_3 | RCC_DCKCFGR_PLLI2SDIVQ_2 | RCC_DCKCFGR_PLLI2SDIVQ_1 | RCC_DCKCFGR_PLLI2SDIVQ_0) /*!< PLLI2S division factor for PLLI2SDIVQ output by 16 */
1153 #define LL_RCC_PLLI2SDIVQ_DIV_17 RCC_DCKCFGR_PLLI2SDIVQ_4 /*!< PLLI2S division factor for PLLI2SDIVQ output by 17 */
1154 #define LL_RCC_PLLI2SDIVQ_DIV_18 (RCC_DCKCFGR_PLLI2SDIVQ_4 | RCC_DCKCFGR_PLLI2SDIVQ_0) /*!< PLLI2S division factor for PLLI2SDIVQ output by 18 */
1155 #define LL_RCC_PLLI2SDIVQ_DIV_19 (RCC_DCKCFGR_PLLI2SDIVQ_4 | RCC_DCKCFGR_PLLI2SDIVQ_1) /*!< PLLI2S division factor for PLLI2SDIVQ output by 19 */
1156 #define LL_RCC_PLLI2SDIVQ_DIV_20 (RCC_DCKCFGR_PLLI2SDIVQ_4 | RCC_DCKCFGR_PLLI2SDIVQ_1 | RCC_DCKCFGR_PLLI2SDIVQ_0) /*!< PLLI2S division factor for PLLI2SDIVQ output by 20 */
1157 #define LL_RCC_PLLI2SDIVQ_DIV_21 (RCC_DCKCFGR_PLLI2SDIVQ_4 | RCC_DCKCFGR_PLLI2SDIVQ_2) /*!< PLLI2S division factor for PLLI2SDIVQ output by 21 */
1158 #define LL_RCC_PLLI2SDIVQ_DIV_22 (RCC_DCKCFGR_PLLI2SDIVQ_4 | RCC_DCKCFGR_PLLI2SDIVQ_2 | RCC_DCKCFGR_PLLI2SDIVQ_0) /*!< PLLI2S division factor for PLLI2SDIVQ output by 22 */
1159 #define LL_RCC_PLLI2SDIVQ_DIV_23 (RCC_DCKCFGR_PLLI2SDIVQ_4 | RCC_DCKCFGR_PLLI2SDIVQ_2 | RCC_DCKCFGR_PLLI2SDIVQ_1) /*!< PLLI2S division factor for PLLI2SDIVQ output by 23 */
1160 #define LL_RCC_PLLI2SDIVQ_DIV_24 (RCC_DCKCFGR_PLLI2SDIVQ_4 | RCC_DCKCFGR_PLLI2SDIVQ_2 | RCC_DCKCFGR_PLLI2SDIVQ_1 | RCC_DCKCFGR_PLLI2SDIVQ_0) /*!< PLLI2S division factor for PLLI2SDIVQ output by 24 */
1161 #define LL_RCC_PLLI2SDIVQ_DIV_25 (RCC_DCKCFGR_PLLI2SDIVQ_4 | RCC_DCKCFGR_PLLI2SDIVQ_3) /*!< PLLI2S division factor for PLLI2SDIVQ output by 25 */
1162 #define LL_RCC_PLLI2SDIVQ_DIV_26 (RCC_DCKCFGR_PLLI2SDIVQ_4 | RCC_DCKCFGR_PLLI2SDIVQ_3 | RCC_DCKCFGR_PLLI2SDIVQ_0) /*!< PLLI2S division factor for PLLI2SDIVQ output by 26 */
1163 #define LL_RCC_PLLI2SDIVQ_DIV_27 (RCC_DCKCFGR_PLLI2SDIVQ_4 | RCC_DCKCFGR_PLLI2SDIVQ_3 | RCC_DCKCFGR_PLLI2SDIVQ_1) /*!< PLLI2S division factor for PLLI2SDIVQ output by 27 */
1164 #define LL_RCC_PLLI2SDIVQ_DIV_28 (RCC_DCKCFGR_PLLI2SDIVQ_4 | RCC_DCKCFGR_PLLI2SDIVQ_3 | RCC_DCKCFGR_PLLI2SDIVQ_1 | RCC_DCKCFGR_PLLI2SDIVQ_0) /*!< PLLI2S division factor for PLLI2SDIVQ output by 28 */
1165 #define LL_RCC_PLLI2SDIVQ_DIV_29 (RCC_DCKCFGR_PLLI2SDIVQ_4 | RCC_DCKCFGR_PLLI2SDIVQ_3 | RCC_DCKCFGR_PLLI2SDIVQ_2) /*!< PLLI2S division factor for PLLI2SDIVQ output by 29 */
1166 #define LL_RCC_PLLI2SDIVQ_DIV_30 (RCC_DCKCFGR_PLLI2SDIVQ_4 | RCC_DCKCFGR_PLLI2SDIVQ_3 | RCC_DCKCFGR_PLLI2SDIVQ_2 | RCC_DCKCFGR_PLLI2SDIVQ_0) /*!< PLLI2S division factor for PLLI2SDIVQ output by 30 */
1167 #define LL_RCC_PLLI2SDIVQ_DIV_31 (RCC_DCKCFGR_PLLI2SDIVQ_4 | RCC_DCKCFGR_PLLI2SDIVQ_3 | RCC_DCKCFGR_PLLI2SDIVQ_2 | RCC_DCKCFGR_PLLI2SDIVQ_1) /*!< PLLI2S division factor for PLLI2SDIVQ output by 31 */
1168 #define LL_RCC_PLLI2SDIVQ_DIV_32 (RCC_DCKCFGR_PLLI2SDIVQ_4 | RCC_DCKCFGR_PLLI2SDIVQ_3 | RCC_DCKCFGR_PLLI2SDIVQ_2 | RCC_DCKCFGR_PLLI2SDIVQ_1 | RCC_DCKCFGR_PLLI2SDIVQ_0) /*!< PLLI2S division factor for PLLI2SDIVQ output by 32 */
1169 /**
1170 * @}
1171 */
1172 #endif /* RCC_DCKCFGR_PLLI2SDIVQ */
1173
1174 #if defined(RCC_DCKCFGR_PLLI2SDIVR)
1175 /** @defgroup RCC_LL_EC_PLLI2SDIVR PLLI2SDIVR division factor (PLLI2SDIVR)
1176 * @{
1177 */
1178 #define LL_RCC_PLLI2SDIVR_DIV_1 (RCC_DCKCFGR_PLLI2SDIVR_0) /*!< PLLI2S division factor for PLLI2SDIVR output by 1 */
1179 #define LL_RCC_PLLI2SDIVR_DIV_2 (RCC_DCKCFGR_PLLI2SDIVR_1) /*!< PLLI2S division factor for PLLI2SDIVR output by 2 */
1180 #define LL_RCC_PLLI2SDIVR_DIV_3 (RCC_DCKCFGR_PLLI2SDIVR_1 | RCC_DCKCFGR_PLLI2SDIVR_0) /*!< PLLI2S division factor for PLLI2SDIVR output by 3 */
1181 #define LL_RCC_PLLI2SDIVR_DIV_4 (RCC_DCKCFGR_PLLI2SDIVR_2) /*!< PLLI2S division factor for PLLI2SDIVR output by 4 */
1182 #define LL_RCC_PLLI2SDIVR_DIV_5 (RCC_DCKCFGR_PLLI2SDIVR_2 | RCC_DCKCFGR_PLLI2SDIVR_0) /*!< PLLI2S division factor for PLLI2SDIVR output by 5 */
1183 #define LL_RCC_PLLI2SDIVR_DIV_6 (RCC_DCKCFGR_PLLI2SDIVR_2 | RCC_DCKCFGR_PLLI2SDIVR_1) /*!< PLLI2S division factor for PLLI2SDIVR output by 6 */
1184 #define LL_RCC_PLLI2SDIVR_DIV_7 (RCC_DCKCFGR_PLLI2SDIVR_2 | RCC_DCKCFGR_PLLI2SDIVR_1 | RCC_DCKCFGR_PLLI2SDIVR_0) /*!< PLLI2S division factor for PLLI2SDIVR output by 7 */
1185 #define LL_RCC_PLLI2SDIVR_DIV_8 (RCC_DCKCFGR_PLLI2SDIVR_3) /*!< PLLI2S division factor for PLLI2SDIVR output by 8 */
1186 #define LL_RCC_PLLI2SDIVR_DIV_9 (RCC_DCKCFGR_PLLI2SDIVR_3 | RCC_DCKCFGR_PLLI2SDIVR_0) /*!< PLLI2S division factor for PLLI2SDIVR output by 9 */
1187 #define LL_RCC_PLLI2SDIVR_DIV_10 (RCC_DCKCFGR_PLLI2SDIVR_3 | RCC_DCKCFGR_PLLI2SDIVR_1) /*!< PLLI2S division factor for PLLI2SDIVR output by 10 */
1188 #define LL_RCC_PLLI2SDIVR_DIV_11 (RCC_DCKCFGR_PLLI2SDIVR_3 | RCC_DCKCFGR_PLLI2SDIVR_1 | RCC_DCKCFGR_PLLI2SDIVR_0) /*!< PLLI2S division factor for PLLI2SDIVR output by 11 */
1189 #define LL_RCC_PLLI2SDIVR_DIV_12 (RCC_DCKCFGR_PLLI2SDIVR_3 | RCC_DCKCFGR_PLLI2SDIVR_2) /*!< PLLI2S division factor for PLLI2SDIVR output by 12 */
1190 #define LL_RCC_PLLI2SDIVR_DIV_13 (RCC_DCKCFGR_PLLI2SDIVR_3 | RCC_DCKCFGR_PLLI2SDIVR_2 | RCC_DCKCFGR_PLLI2SDIVR_0) /*!< PLLI2S division factor for PLLI2SDIVR output by 13 */
1191 #define LL_RCC_PLLI2SDIVR_DIV_14 (RCC_DCKCFGR_PLLI2SDIVR_3 | RCC_DCKCFGR_PLLI2SDIVR_2 | RCC_DCKCFGR_PLLI2SDIVR_1) /*!< PLLI2S division factor for PLLI2SDIVR output by 14 */
1192 #define LL_RCC_PLLI2SDIVR_DIV_15 (RCC_DCKCFGR_PLLI2SDIVR_3 | RCC_DCKCFGR_PLLI2SDIVR_2 | RCC_DCKCFGR_PLLI2SDIVR_1 | RCC_DCKCFGR_PLLI2SDIVR_0) /*!< PLLI2S division factor for PLLI2SDIVR output by 15 */
1193 #define LL_RCC_PLLI2SDIVR_DIV_16 (RCC_DCKCFGR_PLLI2SDIVR_4) /*!< PLLI2S division factor for PLLI2SDIVR output by 16 */
1194 #define LL_RCC_PLLI2SDIVR_DIV_17 (RCC_DCKCFGR_PLLI2SDIVR_4 | RCC_DCKCFGR_PLLI2SDIVR_0) /*!< PLLI2S division factor for PLLI2SDIVR output by 17 */
1195 #define LL_RCC_PLLI2SDIVR_DIV_18 (RCC_DCKCFGR_PLLI2SDIVR_4 | RCC_DCKCFGR_PLLI2SDIVR_1) /*!< PLLI2S division factor for PLLI2SDIVR output by 18 */
1196 #define LL_RCC_PLLI2SDIVR_DIV_19 (RCC_DCKCFGR_PLLI2SDIVR_4 | RCC_DCKCFGR_PLLI2SDIVR_1 | RCC_DCKCFGR_PLLI2SDIVR_0) /*!< PLLI2S division factor for PLLI2SDIVR output by 19 */
1197 #define LL_RCC_PLLI2SDIVR_DIV_20 (RCC_DCKCFGR_PLLI2SDIVR_4 | RCC_DCKCFGR_PLLI2SDIVR_2) /*!< PLLI2S division factor for PLLI2SDIVR output by 20 */
1198 #define LL_RCC_PLLI2SDIVR_DIV_21 (RCC_DCKCFGR_PLLI2SDIVR_4 | RCC_DCKCFGR_PLLI2SDIVR_2 | RCC_DCKCFGR_PLLI2SDIVR_0) /*!< PLLI2S division factor for PLLI2SDIVR output by 21 */
1199 #define LL_RCC_PLLI2SDIVR_DIV_22 (RCC_DCKCFGR_PLLI2SDIVR_4 | RCC_DCKCFGR_PLLI2SDIVR_2 | RCC_DCKCFGR_PLLI2SDIVR_1) /*!< PLLI2S division factor for PLLI2SDIVR output by 22 */
1200 #define LL_RCC_PLLI2SDIVR_DIV_23 (RCC_DCKCFGR_PLLI2SDIVR_4 | RCC_DCKCFGR_PLLI2SDIVR_2 | RCC_DCKCFGR_PLLI2SDIVR_1 | RCC_DCKCFGR_PLLI2SDIVR_0) /*!< PLLI2S division factor for PLLI2SDIVR output by 23 */
1201 #define LL_RCC_PLLI2SDIVR_DIV_24 (RCC_DCKCFGR_PLLI2SDIVR_4 | RCC_DCKCFGR_PLLI2SDIVR_3) /*!< PLLI2S division factor for PLLI2SDIVR output by 24 */
1202 #define LL_RCC_PLLI2SDIVR_DIV_25 (RCC_DCKCFGR_PLLI2SDIVR_4 | RCC_DCKCFGR_PLLI2SDIVR_3 | RCC_DCKCFGR_PLLI2SDIVR_0) /*!< PLLI2S division factor for PLLI2SDIVR output by 25 */
1203 #define LL_RCC_PLLI2SDIVR_DIV_26 (RCC_DCKCFGR_PLLI2SDIVR_4 | RCC_DCKCFGR_PLLI2SDIVR_3 | RCC_DCKCFGR_PLLI2SDIVR_1) /*!< PLLI2S division factor for PLLI2SDIVR output by 26 */
1204 #define LL_RCC_PLLI2SDIVR_DIV_27 (RCC_DCKCFGR_PLLI2SDIVR_4 | RCC_DCKCFGR_PLLI2SDIVR_3 | RCC_DCKCFGR_PLLI2SDIVR_1 | RCC_DCKCFGR_PLLI2SDIVR_0) /*!< PLLI2S division factor for PLLI2SDIVR output by 27 */
1205 #define LL_RCC_PLLI2SDIVR_DIV_28 (RCC_DCKCFGR_PLLI2SDIVR_4 | RCC_DCKCFGR_PLLI2SDIVR_3 | RCC_DCKCFGR_PLLI2SDIVR_2) /*!< PLLI2S division factor for PLLI2SDIVR output by 28 */
1206 #define LL_RCC_PLLI2SDIVR_DIV_29 (RCC_DCKCFGR_PLLI2SDIVR_4 | RCC_DCKCFGR_PLLI2SDIVR_3 | RCC_DCKCFGR_PLLI2SDIVR_2 | RCC_DCKCFGR_PLLI2SDIVR_0) /*!< PLLI2S division factor for PLLI2SDIVR output by 29 */
1207 #define LL_RCC_PLLI2SDIVR_DIV_30 (RCC_DCKCFGR_PLLI2SDIVR_4 | RCC_DCKCFGR_PLLI2SDIVR_3 | RCC_DCKCFGR_PLLI2SDIVR_2 | RCC_DCKCFGR_PLLI2SDIVR_1) /*!< PLLI2S division factor for PLLI2SDIVR output by 30 */
1208 #define LL_RCC_PLLI2SDIVR_DIV_31 (RCC_DCKCFGR_PLLI2SDIVR_4 | RCC_DCKCFGR_PLLI2SDIVR_3 | RCC_DCKCFGR_PLLI2SDIVR_2 | RCC_DCKCFGR_PLLI2SDIVR_1 | RCC_DCKCFGR_PLLI2SDIVR_0) /*!< PLLI2S division factor for PLLI2SDIVR output by 31 */
1209 /**
1210 * @}
1211 */
1212 #endif /* RCC_DCKCFGR_PLLI2SDIVR */
1213
1214 /** @defgroup RCC_LL_EC_PLLI2SR PLLI2SR division factor (PLLI2SR)
1215 * @{
1216 */
1217 #define LL_RCC_PLLI2SR_DIV_2 RCC_PLLI2SCFGR_PLLI2SR_1 /*!< PLLI2S division factor for PLLI2SR output by 2 */
1218 #define LL_RCC_PLLI2SR_DIV_3 (RCC_PLLI2SCFGR_PLLI2SR_1 | RCC_PLLI2SCFGR_PLLI2SR_0) /*!< PLLI2S division factor for PLLI2SR output by 3 */
1219 #define LL_RCC_PLLI2SR_DIV_4 RCC_PLLI2SCFGR_PLLI2SR_2 /*!< PLLI2S division factor for PLLI2SR output by 4 */
1220 #define LL_RCC_PLLI2SR_DIV_5 (RCC_PLLI2SCFGR_PLLI2SR_2 | RCC_PLLI2SCFGR_PLLI2SR_0) /*!< PLLI2S division factor for PLLI2SR output by 5 */
1221 #define LL_RCC_PLLI2SR_DIV_6 (RCC_PLLI2SCFGR_PLLI2SR_2 | RCC_PLLI2SCFGR_PLLI2SR_1) /*!< PLLI2S division factor for PLLI2SR output by 6 */
1222 #define LL_RCC_PLLI2SR_DIV_7 (RCC_PLLI2SCFGR_PLLI2SR_2 | RCC_PLLI2SCFGR_PLLI2SR_1 | RCC_PLLI2SCFGR_PLLI2SR_0) /*!< PLLI2S division factor for PLLI2SR output by 7 */
1223 /**
1224 * @}
1225 */
1226
1227 #if defined(RCC_PLLI2SCFGR_PLLI2SP)
1228 /** @defgroup RCC_LL_EC_PLLI2SP PLLI2SP division factor (PLLI2SP)
1229 * @{
1230 */
1231 #define LL_RCC_PLLI2SP_DIV_2 0x00000000U /*!< PLLI2S division factor for PLLI2SP output by 2 */
1232 #define LL_RCC_PLLI2SP_DIV_4 RCC_PLLI2SCFGR_PLLI2SP_0 /*!< PLLI2S division factor for PLLI2SP output by 4 */
1233 #define LL_RCC_PLLI2SP_DIV_6 RCC_PLLI2SCFGR_PLLI2SP_1 /*!< PLLI2S division factor for PLLI2SP output by 6 */
1234 #define LL_RCC_PLLI2SP_DIV_8 (RCC_PLLI2SCFGR_PLLI2SP_1 | RCC_PLLI2SCFGR_PLLI2SP_0) /*!< PLLI2S division factor for PLLI2SP output by 8 */
1235 /**
1236 * @}
1237 */
1238 #endif /* RCC_PLLI2SCFGR_PLLI2SP */
1239 #endif /* RCC_PLLI2S_SUPPORT */
1240
1241 #if defined(RCC_PLLSAI_SUPPORT)
1242 /** @defgroup RCC_LL_EC_PLLSAIM PLLSAIM division factor (PLLSAIM or PLLM)
1243 * @{
1244 */
1245 #if defined(RCC_PLLSAICFGR_PLLSAIM)
1246 #define LL_RCC_PLLSAIM_DIV_2 (RCC_PLLSAICFGR_PLLSAIM_1) /*!< PLLSAI division factor for PLLSAIM output by 2 */
1247 #define LL_RCC_PLLSAIM_DIV_3 (RCC_PLLSAICFGR_PLLSAIM_1 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 3 */
1248 #define LL_RCC_PLLSAIM_DIV_4 (RCC_PLLSAICFGR_PLLSAIM_2) /*!< PLLSAI division factor for PLLSAIM output by 4 */
1249 #define LL_RCC_PLLSAIM_DIV_5 (RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 5 */
1250 #define LL_RCC_PLLSAIM_DIV_6 (RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_1) /*!< PLLSAI division factor for PLLSAIM output by 6 */
1251 #define LL_RCC_PLLSAIM_DIV_7 (RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_1 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 7 */
1252 #define LL_RCC_PLLSAIM_DIV_8 (RCC_PLLSAICFGR_PLLSAIM_3) /*!< PLLSAI division factor for PLLSAIM output by 8 */
1253 #define LL_RCC_PLLSAIM_DIV_9 (RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 9 */
1254 #define LL_RCC_PLLSAIM_DIV_10 (RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_1) /*!< PLLSAI division factor for PLLSAIM output by 10 */
1255 #define LL_RCC_PLLSAIM_DIV_11 (RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_1 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 11 */
1256 #define LL_RCC_PLLSAIM_DIV_12 (RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_2) /*!< PLLSAI division factor for PLLSAIM output by 12 */
1257 #define LL_RCC_PLLSAIM_DIV_13 (RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 13 */
1258 #define LL_RCC_PLLSAIM_DIV_14 (RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_1) /*!< PLLSAI division factor for PLLSAIM output by 14 */
1259 #define LL_RCC_PLLSAIM_DIV_15 (RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_1 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 15 */
1260 #define LL_RCC_PLLSAIM_DIV_16 (RCC_PLLSAICFGR_PLLSAIM_4) /*!< PLLSAI division factor for PLLSAIM output by 16 */
1261 #define LL_RCC_PLLSAIM_DIV_17 (RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 17 */
1262 #define LL_RCC_PLLSAIM_DIV_18 (RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_1) /*!< PLLSAI division factor for PLLSAIM output by 18 */
1263 #define LL_RCC_PLLSAIM_DIV_19 (RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_1 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 19 */
1264 #define LL_RCC_PLLSAIM_DIV_20 (RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_2) /*!< PLLSAI division factor for PLLSAIM output by 20 */
1265 #define LL_RCC_PLLSAIM_DIV_21 (RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 21 */
1266 #define LL_RCC_PLLSAIM_DIV_22 (RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_1) /*!< PLLSAI division factor for PLLSAIM output by 22 */
1267 #define LL_RCC_PLLSAIM_DIV_23 (RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_1 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 23 */
1268 #define LL_RCC_PLLSAIM_DIV_24 (RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_3) /*!< PLLSAI division factor for PLLSAIM output by 24 */
1269 #define LL_RCC_PLLSAIM_DIV_25 (RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 25 */
1270 #define LL_RCC_PLLSAIM_DIV_26 (RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_1) /*!< PLLSAI division factor for PLLSAIM output by 26 */
1271 #define LL_RCC_PLLSAIM_DIV_27 (RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_1 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 27 */
1272 #define LL_RCC_PLLSAIM_DIV_28 (RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_2) /*!< PLLSAI division factor for PLLSAIM output by 28 */
1273 #define LL_RCC_PLLSAIM_DIV_29 (RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 29 */
1274 #define LL_RCC_PLLSAIM_DIV_30 (RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_1) /*!< PLLSAI division factor for PLLSAIM output by 30 */
1275 #define LL_RCC_PLLSAIM_DIV_31 (RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_1 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 31 */
1276 #define LL_RCC_PLLSAIM_DIV_32 (RCC_PLLSAICFGR_PLLSAIM_5) /*!< PLLSAI division factor for PLLSAIM output by 32 */
1277 #define LL_RCC_PLLSAIM_DIV_33 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 33 */
1278 #define LL_RCC_PLLSAIM_DIV_34 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_1) /*!< PLLSAI division factor for PLLSAIM output by 34 */
1279 #define LL_RCC_PLLSAIM_DIV_35 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_1 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 35 */
1280 #define LL_RCC_PLLSAIM_DIV_36 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_2) /*!< PLLSAI division factor for PLLSAIM output by 36 */
1281 #define LL_RCC_PLLSAIM_DIV_37 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 37 */
1282 #define LL_RCC_PLLSAIM_DIV_38 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_1) /*!< PLLSAI division factor for PLLSAIM output by 38 */
1283 #define LL_RCC_PLLSAIM_DIV_39 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_1 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 39 */
1284 #define LL_RCC_PLLSAIM_DIV_40 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_3) /*!< PLLSAI division factor for PLLSAIM output by 40 */
1285 #define LL_RCC_PLLSAIM_DIV_41 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 41 */
1286 #define LL_RCC_PLLSAIM_DIV_42 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_1) /*!< PLLSAI division factor for PLLSAIM output by 42 */
1287 #define LL_RCC_PLLSAIM_DIV_43 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_1 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 43 */
1288 #define LL_RCC_PLLSAIM_DIV_44 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_2) /*!< PLLSAI division factor for PLLSAIM output by 44 */
1289 #define LL_RCC_PLLSAIM_DIV_45 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 45 */
1290 #define LL_RCC_PLLSAIM_DIV_46 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_1) /*!< PLLSAI division factor for PLLSAIM output by 46 */
1291 #define LL_RCC_PLLSAIM_DIV_47 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_1 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 47 */
1292 #define LL_RCC_PLLSAIM_DIV_48 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_4) /*!< PLLSAI division factor for PLLSAIM output by 48 */
1293 #define LL_RCC_PLLSAIM_DIV_49 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 49 */
1294 #define LL_RCC_PLLSAIM_DIV_50 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_1) /*!< PLLSAI division factor for PLLSAIM output by 50 */
1295 #define LL_RCC_PLLSAIM_DIV_51 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_1 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 51 */
1296 #define LL_RCC_PLLSAIM_DIV_52 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_2) /*!< PLLSAI division factor for PLLSAIM output by 52 */
1297 #define LL_RCC_PLLSAIM_DIV_53 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 53 */
1298 #define LL_RCC_PLLSAIM_DIV_54 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_1) /*!< PLLSAI division factor for PLLSAIM output by 54 */
1299 #define LL_RCC_PLLSAIM_DIV_55 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_1 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 55 */
1300 #define LL_RCC_PLLSAIM_DIV_56 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_3) /*!< PLLSAI division factor for PLLSAIM output by 56 */
1301 #define LL_RCC_PLLSAIM_DIV_57 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 57 */
1302 #define LL_RCC_PLLSAIM_DIV_58 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_1) /*!< PLLSAI division factor for PLLSAIM output by 58 */
1303 #define LL_RCC_PLLSAIM_DIV_59 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_1 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 59 */
1304 #define LL_RCC_PLLSAIM_DIV_60 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_2) /*!< PLLSAI division factor for PLLSAIM output by 60 */
1305 #define LL_RCC_PLLSAIM_DIV_61 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 61 */
1306 #define LL_RCC_PLLSAIM_DIV_62 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_1) /*!< PLLSAI division factor for PLLSAIM output by 62 */
1307 #define LL_RCC_PLLSAIM_DIV_63 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_1 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 63 */
1308 #else
1309 #define LL_RCC_PLLSAIM_DIV_2 LL_RCC_PLLM_DIV_2 /*!< PLLSAI division factor for PLLSAIM output by 2 */
1310 #define LL_RCC_PLLSAIM_DIV_3 LL_RCC_PLLM_DIV_3 /*!< PLLSAI division factor for PLLSAIM output by 3 */
1311 #define LL_RCC_PLLSAIM_DIV_4 LL_RCC_PLLM_DIV_4 /*!< PLLSAI division factor for PLLSAIM output by 4 */
1312 #define LL_RCC_PLLSAIM_DIV_5 LL_RCC_PLLM_DIV_5 /*!< PLLSAI division factor for PLLSAIM output by 5 */
1313 #define LL_RCC_PLLSAIM_DIV_6 LL_RCC_PLLM_DIV_6 /*!< PLLSAI division factor for PLLSAIM output by 6 */
1314 #define LL_RCC_PLLSAIM_DIV_7 LL_RCC_PLLM_DIV_7 /*!< PLLSAI division factor for PLLSAIM output by 7 */
1315 #define LL_RCC_PLLSAIM_DIV_8 LL_RCC_PLLM_DIV_8 /*!< PLLSAI division factor for PLLSAIM output by 8 */
1316 #define LL_RCC_PLLSAIM_DIV_9 LL_RCC_PLLM_DIV_9 /*!< PLLSAI division factor for PLLSAIM output by 9 */
1317 #define LL_RCC_PLLSAIM_DIV_10 LL_RCC_PLLM_DIV_10 /*!< PLLSAI division factor for PLLSAIM output by 10 */
1318 #define LL_RCC_PLLSAIM_DIV_11 LL_RCC_PLLM_DIV_11 /*!< PLLSAI division factor for PLLSAIM output by 11 */
1319 #define LL_RCC_PLLSAIM_DIV_12 LL_RCC_PLLM_DIV_12 /*!< PLLSAI division factor for PLLSAIM output by 12 */
1320 #define LL_RCC_PLLSAIM_DIV_13 LL_RCC_PLLM_DIV_13 /*!< PLLSAI division factor for PLLSAIM output by 13 */
1321 #define LL_RCC_PLLSAIM_DIV_14 LL_RCC_PLLM_DIV_14 /*!< PLLSAI division factor for PLLSAIM output by 14 */
1322 #define LL_RCC_PLLSAIM_DIV_15 LL_RCC_PLLM_DIV_15 /*!< PLLSAI division factor for PLLSAIM output by 15 */
1323 #define LL_RCC_PLLSAIM_DIV_16 LL_RCC_PLLM_DIV_16 /*!< PLLSAI division factor for PLLSAIM output by 16 */
1324 #define LL_RCC_PLLSAIM_DIV_17 LL_RCC_PLLM_DIV_17 /*!< PLLSAI division factor for PLLSAIM output by 17 */
1325 #define LL_RCC_PLLSAIM_DIV_18 LL_RCC_PLLM_DIV_18 /*!< PLLSAI division factor for PLLSAIM output by 18 */
1326 #define LL_RCC_PLLSAIM_DIV_19 LL_RCC_PLLM_DIV_19 /*!< PLLSAI division factor for PLLSAIM output by 19 */
1327 #define LL_RCC_PLLSAIM_DIV_20 LL_RCC_PLLM_DIV_20 /*!< PLLSAI division factor for PLLSAIM output by 20 */
1328 #define LL_RCC_PLLSAIM_DIV_21 LL_RCC_PLLM_DIV_21 /*!< PLLSAI division factor for PLLSAIM output by 21 */
1329 #define LL_RCC_PLLSAIM_DIV_22 LL_RCC_PLLM_DIV_22 /*!< PLLSAI division factor for PLLSAIM output by 22 */
1330 #define LL_RCC_PLLSAIM_DIV_23 LL_RCC_PLLM_DIV_23 /*!< PLLSAI division factor for PLLSAIM output by 23 */
1331 #define LL_RCC_PLLSAIM_DIV_24 LL_RCC_PLLM_DIV_24 /*!< PLLSAI division factor for PLLSAIM output by 24 */
1332 #define LL_RCC_PLLSAIM_DIV_25 LL_RCC_PLLM_DIV_25 /*!< PLLSAI division factor for PLLSAIM output by 25 */
1333 #define LL_RCC_PLLSAIM_DIV_26 LL_RCC_PLLM_DIV_26 /*!< PLLSAI division factor for PLLSAIM output by 26 */
1334 #define LL_RCC_PLLSAIM_DIV_27 LL_RCC_PLLM_DIV_27 /*!< PLLSAI division factor for PLLSAIM output by 27 */
1335 #define LL_RCC_PLLSAIM_DIV_28 LL_RCC_PLLM_DIV_28 /*!< PLLSAI division factor for PLLSAIM output by 28 */
1336 #define LL_RCC_PLLSAIM_DIV_29 LL_RCC_PLLM_DIV_29 /*!< PLLSAI division factor for PLLSAIM output by 29 */
1337 #define LL_RCC_PLLSAIM_DIV_30 LL_RCC_PLLM_DIV_30 /*!< PLLSAI division factor for PLLSAIM output by 30 */
1338 #define LL_RCC_PLLSAIM_DIV_31 LL_RCC_PLLM_DIV_31 /*!< PLLSAI division factor for PLLSAIM output by 31 */
1339 #define LL_RCC_PLLSAIM_DIV_32 LL_RCC_PLLM_DIV_32 /*!< PLLSAI division factor for PLLSAIM output by 32 */
1340 #define LL_RCC_PLLSAIM_DIV_33 LL_RCC_PLLM_DIV_33 /*!< PLLSAI division factor for PLLSAIM output by 33 */
1341 #define LL_RCC_PLLSAIM_DIV_34 LL_RCC_PLLM_DIV_34 /*!< PLLSAI division factor for PLLSAIM output by 34 */
1342 #define LL_RCC_PLLSAIM_DIV_35 LL_RCC_PLLM_DIV_35 /*!< PLLSAI division factor for PLLSAIM output by 35 */
1343 #define LL_RCC_PLLSAIM_DIV_36 LL_RCC_PLLM_DIV_36 /*!< PLLSAI division factor for PLLSAIM output by 36 */
1344 #define LL_RCC_PLLSAIM_DIV_37 LL_RCC_PLLM_DIV_37 /*!< PLLSAI division factor for PLLSAIM output by 37 */
1345 #define LL_RCC_PLLSAIM_DIV_38 LL_RCC_PLLM_DIV_38 /*!< PLLSAI division factor for PLLSAIM output by 38 */
1346 #define LL_RCC_PLLSAIM_DIV_39 LL_RCC_PLLM_DIV_39 /*!< PLLSAI division factor for PLLSAIM output by 39 */
1347 #define LL_RCC_PLLSAIM_DIV_40 LL_RCC_PLLM_DIV_40 /*!< PLLSAI division factor for PLLSAIM output by 40 */
1348 #define LL_RCC_PLLSAIM_DIV_41 LL_RCC_PLLM_DIV_41 /*!< PLLSAI division factor for PLLSAIM output by 41 */
1349 #define LL_RCC_PLLSAIM_DIV_42 LL_RCC_PLLM_DIV_42 /*!< PLLSAI division factor for PLLSAIM output by 42 */
1350 #define LL_RCC_PLLSAIM_DIV_43 LL_RCC_PLLM_DIV_43 /*!< PLLSAI division factor for PLLSAIM output by 43 */
1351 #define LL_RCC_PLLSAIM_DIV_44 LL_RCC_PLLM_DIV_44 /*!< PLLSAI division factor for PLLSAIM output by 44 */
1352 #define LL_RCC_PLLSAIM_DIV_45 LL_RCC_PLLM_DIV_45 /*!< PLLSAI division factor for PLLSAIM output by 45 */
1353 #define LL_RCC_PLLSAIM_DIV_46 LL_RCC_PLLM_DIV_46 /*!< PLLSAI division factor for PLLSAIM output by 46 */
1354 #define LL_RCC_PLLSAIM_DIV_47 LL_RCC_PLLM_DIV_47 /*!< PLLSAI division factor for PLLSAIM output by 47 */
1355 #define LL_RCC_PLLSAIM_DIV_48 LL_RCC_PLLM_DIV_48 /*!< PLLSAI division factor for PLLSAIM output by 48 */
1356 #define LL_RCC_PLLSAIM_DIV_49 LL_RCC_PLLM_DIV_49 /*!< PLLSAI division factor for PLLSAIM output by 49 */
1357 #define LL_RCC_PLLSAIM_DIV_50 LL_RCC_PLLM_DIV_50 /*!< PLLSAI division factor for PLLSAIM output by 50 */
1358 #define LL_RCC_PLLSAIM_DIV_51 LL_RCC_PLLM_DIV_51 /*!< PLLSAI division factor for PLLSAIM output by 51 */
1359 #define LL_RCC_PLLSAIM_DIV_52 LL_RCC_PLLM_DIV_52 /*!< PLLSAI division factor for PLLSAIM output by 52 */
1360 #define LL_RCC_PLLSAIM_DIV_53 LL_RCC_PLLM_DIV_53 /*!< PLLSAI division factor for PLLSAIM output by 53 */
1361 #define LL_RCC_PLLSAIM_DIV_54 LL_RCC_PLLM_DIV_54 /*!< PLLSAI division factor for PLLSAIM output by 54 */
1362 #define LL_RCC_PLLSAIM_DIV_55 LL_RCC_PLLM_DIV_55 /*!< PLLSAI division factor for PLLSAIM output by 55 */
1363 #define LL_RCC_PLLSAIM_DIV_56 LL_RCC_PLLM_DIV_56 /*!< PLLSAI division factor for PLLSAIM output by 56 */
1364 #define LL_RCC_PLLSAIM_DIV_57 LL_RCC_PLLM_DIV_57 /*!< PLLSAI division factor for PLLSAIM output by 57 */
1365 #define LL_RCC_PLLSAIM_DIV_58 LL_RCC_PLLM_DIV_58 /*!< PLLSAI division factor for PLLSAIM output by 58 */
1366 #define LL_RCC_PLLSAIM_DIV_59 LL_RCC_PLLM_DIV_59 /*!< PLLSAI division factor for PLLSAIM output by 59 */
1367 #define LL_RCC_PLLSAIM_DIV_60 LL_RCC_PLLM_DIV_60 /*!< PLLSAI division factor for PLLSAIM output by 60 */
1368 #define LL_RCC_PLLSAIM_DIV_61 LL_RCC_PLLM_DIV_61 /*!< PLLSAI division factor for PLLSAIM output by 61 */
1369 #define LL_RCC_PLLSAIM_DIV_62 LL_RCC_PLLM_DIV_62 /*!< PLLSAI division factor for PLLSAIM output by 62 */
1370 #define LL_RCC_PLLSAIM_DIV_63 LL_RCC_PLLM_DIV_63 /*!< PLLSAI division factor for PLLSAIM output by 63 */
1371 #endif /* RCC_PLLSAICFGR_PLLSAIM */
1372 /**
1373 * @}
1374 */
1375
1376 /** @defgroup RCC_LL_EC_PLLSAIQ PLLSAIQ division factor (PLLSAIQ)
1377 * @{
1378 */
1379 #define LL_RCC_PLLSAIQ_DIV_2 RCC_PLLSAICFGR_PLLSAIQ_1 /*!< PLLSAI division factor for PLLSAIQ output by 2 */
1380 #define LL_RCC_PLLSAIQ_DIV_3 (RCC_PLLSAICFGR_PLLSAIQ_1 | RCC_PLLSAICFGR_PLLSAIQ_0) /*!< PLLSAI division factor for PLLSAIQ output by 3 */
1381 #define LL_RCC_PLLSAIQ_DIV_4 RCC_PLLSAICFGR_PLLSAIQ_2 /*!< PLLSAI division factor for PLLSAIQ output by 4 */
1382 #define LL_RCC_PLLSAIQ_DIV_5 (RCC_PLLSAICFGR_PLLSAIQ_2 | RCC_PLLSAICFGR_PLLSAIQ_0) /*!< PLLSAI division factor for PLLSAIQ output by 5 */
1383 #define LL_RCC_PLLSAIQ_DIV_6 (RCC_PLLSAICFGR_PLLSAIQ_2 | RCC_PLLSAICFGR_PLLSAIQ_1) /*!< PLLSAI division factor for PLLSAIQ output by 6 */
1384 #define LL_RCC_PLLSAIQ_DIV_7 (RCC_PLLSAICFGR_PLLSAIQ_2 | RCC_PLLSAICFGR_PLLSAIQ_1 | RCC_PLLSAICFGR_PLLSAIQ_0) /*!< PLLSAI division factor for PLLSAIQ output by 7 */
1385 #define LL_RCC_PLLSAIQ_DIV_8 RCC_PLLSAICFGR_PLLSAIQ_3 /*!< PLLSAI division factor for PLLSAIQ output by 8 */
1386 #define LL_RCC_PLLSAIQ_DIV_9 (RCC_PLLSAICFGR_PLLSAIQ_3 | RCC_PLLSAICFGR_PLLSAIQ_0) /*!< PLLSAI division factor for PLLSAIQ output by 9 */
1387 #define LL_RCC_PLLSAIQ_DIV_10 (RCC_PLLSAICFGR_PLLSAIQ_3 | RCC_PLLSAICFGR_PLLSAIQ_1) /*!< PLLSAI division factor for PLLSAIQ output by 10 */
1388 #define LL_RCC_PLLSAIQ_DIV_11 (RCC_PLLSAICFGR_PLLSAIQ_3 | RCC_PLLSAICFGR_PLLSAIQ_1 | RCC_PLLSAICFGR_PLLSAIQ_0) /*!< PLLSAI division factor for PLLSAIQ output by 11 */
1389 #define LL_RCC_PLLSAIQ_DIV_12 (RCC_PLLSAICFGR_PLLSAIQ_3 | RCC_PLLSAICFGR_PLLSAIQ_2) /*!< PLLSAI division factor for PLLSAIQ output by 12 */
1390 #define LL_RCC_PLLSAIQ_DIV_13 (RCC_PLLSAICFGR_PLLSAIQ_3 | RCC_PLLSAICFGR_PLLSAIQ_2 | RCC_PLLSAICFGR_PLLSAIQ_0) /*!< PLLSAI division factor for PLLSAIQ output by 13 */
1391 #define LL_RCC_PLLSAIQ_DIV_14 (RCC_PLLSAICFGR_PLLSAIQ_3 | RCC_PLLSAICFGR_PLLSAIQ_2 | RCC_PLLSAICFGR_PLLSAIQ_1) /*!< PLLSAI division factor for PLLSAIQ output by 14 */
1392 #define LL_RCC_PLLSAIQ_DIV_15 (RCC_PLLSAICFGR_PLLSAIQ_3 | RCC_PLLSAICFGR_PLLSAIQ_2 | RCC_PLLSAICFGR_PLLSAIQ_1 | RCC_PLLSAICFGR_PLLSAIQ_0) /*!< PLLSAI division factor for PLLSAIQ output by 15 */
1393 /**
1394 * @}
1395 */
1396
1397 #if defined(RCC_DCKCFGR_PLLSAIDIVQ)
1398 /** @defgroup RCC_LL_EC_PLLSAIDIVQ PLLSAIDIVQ division factor (PLLSAIDIVQ)
1399 * @{
1400 */
1401 #define LL_RCC_PLLSAIDIVQ_DIV_1 0x00000000U /*!< PLLSAI division factor for PLLSAIDIVQ output by 1 */
1402 #define LL_RCC_PLLSAIDIVQ_DIV_2 RCC_DCKCFGR_PLLSAIDIVQ_0 /*!< PLLSAI division factor for PLLSAIDIVQ output by 2 */
1403 #define LL_RCC_PLLSAIDIVQ_DIV_3 RCC_DCKCFGR_PLLSAIDIVQ_1 /*!< PLLSAI division factor for PLLSAIDIVQ output by 3 */
1404 #define LL_RCC_PLLSAIDIVQ_DIV_4 (RCC_DCKCFGR_PLLSAIDIVQ_1 | RCC_DCKCFGR_PLLSAIDIVQ_0) /*!< PLLSAI division factor for PLLSAIDIVQ output by 4 */
1405 #define LL_RCC_PLLSAIDIVQ_DIV_5 RCC_DCKCFGR_PLLSAIDIVQ_2 /*!< PLLSAI division factor for PLLSAIDIVQ output by 5 */
1406 #define LL_RCC_PLLSAIDIVQ_DIV_6 (RCC_DCKCFGR_PLLSAIDIVQ_2 | RCC_DCKCFGR_PLLSAIDIVQ_0) /*!< PLLSAI division factor for PLLSAIDIVQ output by 6 */
1407 #define LL_RCC_PLLSAIDIVQ_DIV_7 (RCC_DCKCFGR_PLLSAIDIVQ_2 | RCC_DCKCFGR_PLLSAIDIVQ_1) /*!< PLLSAI division factor for PLLSAIDIVQ output by 7 */
1408 #define LL_RCC_PLLSAIDIVQ_DIV_8 (RCC_DCKCFGR_PLLSAIDIVQ_2 | RCC_DCKCFGR_PLLSAIDIVQ_1 | RCC_DCKCFGR_PLLSAIDIVQ_0) /*!< PLLSAI division factor for PLLSAIDIVQ output by 8 */
1409 #define LL_RCC_PLLSAIDIVQ_DIV_9 RCC_DCKCFGR_PLLSAIDIVQ_3 /*!< PLLSAI division factor for PLLSAIDIVQ output by 9 */
1410 #define LL_RCC_PLLSAIDIVQ_DIV_10 (RCC_DCKCFGR_PLLSAIDIVQ_3 | RCC_DCKCFGR_PLLSAIDIVQ_0) /*!< PLLSAI division factor for PLLSAIDIVQ output by 10 */
1411 #define LL_RCC_PLLSAIDIVQ_DIV_11 (RCC_DCKCFGR_PLLSAIDIVQ_3 | RCC_DCKCFGR_PLLSAIDIVQ_1) /*!< PLLSAI division factor for PLLSAIDIVQ output by 11 */
1412 #define LL_RCC_PLLSAIDIVQ_DIV_12 (RCC_DCKCFGR_PLLSAIDIVQ_3 | RCC_DCKCFGR_PLLSAIDIVQ_1 | RCC_DCKCFGR_PLLSAIDIVQ_0) /*!< PLLSAI division factor for PLLSAIDIVQ output by 12 */
1413 #define LL_RCC_PLLSAIDIVQ_DIV_13 (RCC_DCKCFGR_PLLSAIDIVQ_3 | RCC_DCKCFGR_PLLSAIDIVQ_2) /*!< PLLSAI division factor for PLLSAIDIVQ output by 13 */
1414 #define LL_RCC_PLLSAIDIVQ_DIV_14 (RCC_DCKCFGR_PLLSAIDIVQ_3 | RCC_DCKCFGR_PLLSAIDIVQ_2 | RCC_DCKCFGR_PLLSAIDIVQ_0) /*!< PLLSAI division factor for PLLSAIDIVQ output by 14 */
1415 #define LL_RCC_PLLSAIDIVQ_DIV_15 (RCC_DCKCFGR_PLLSAIDIVQ_3 | RCC_DCKCFGR_PLLSAIDIVQ_2 | RCC_DCKCFGR_PLLSAIDIVQ_1) /*!< PLLSAI division factor for PLLSAIDIVQ output by 15 */
1416 #define LL_RCC_PLLSAIDIVQ_DIV_16 (RCC_DCKCFGR_PLLSAIDIVQ_3 | RCC_DCKCFGR_PLLSAIDIVQ_2 | RCC_DCKCFGR_PLLSAIDIVQ_1 | RCC_DCKCFGR_PLLSAIDIVQ_0) /*!< PLLSAI division factor for PLLSAIDIVQ output by 16 */
1417 #define LL_RCC_PLLSAIDIVQ_DIV_17 RCC_DCKCFGR_PLLSAIDIVQ_4 /*!< PLLSAI division factor for PLLSAIDIVQ output by 17 */
1418 #define LL_RCC_PLLSAIDIVQ_DIV_18 (RCC_DCKCFGR_PLLSAIDIVQ_4 | RCC_DCKCFGR_PLLSAIDIVQ_0) /*!< PLLSAI division factor for PLLSAIDIVQ output by 18 */
1419 #define LL_RCC_PLLSAIDIVQ_DIV_19 (RCC_DCKCFGR_PLLSAIDIVQ_4 | RCC_DCKCFGR_PLLSAIDIVQ_1) /*!< PLLSAI division factor for PLLSAIDIVQ output by 19 */
1420 #define LL_RCC_PLLSAIDIVQ_DIV_20 (RCC_DCKCFGR_PLLSAIDIVQ_4 | RCC_DCKCFGR_PLLSAIDIVQ_1 | RCC_DCKCFGR_PLLSAIDIVQ_0) /*!< PLLSAI division factor for PLLSAIDIVQ output by 20 */
1421 #define LL_RCC_PLLSAIDIVQ_DIV_21 (RCC_DCKCFGR_PLLSAIDIVQ_4 | RCC_DCKCFGR_PLLSAIDIVQ_2) /*!< PLLSAI division factor for PLLSAIDIVQ output by 21 */
1422 #define LL_RCC_PLLSAIDIVQ_DIV_22 (RCC_DCKCFGR_PLLSAIDIVQ_4 | RCC_DCKCFGR_PLLSAIDIVQ_2 | RCC_DCKCFGR_PLLSAIDIVQ_0) /*!< PLLSAI division factor for PLLSAIDIVQ output by 22 */
1423 #define LL_RCC_PLLSAIDIVQ_DIV_23 (RCC_DCKCFGR_PLLSAIDIVQ_4 | RCC_DCKCFGR_PLLSAIDIVQ_2 | RCC_DCKCFGR_PLLSAIDIVQ_1) /*!< PLLSAI division factor for PLLSAIDIVQ output by 23 */
1424 #define LL_RCC_PLLSAIDIVQ_DIV_24 (RCC_DCKCFGR_PLLSAIDIVQ_4 | RCC_DCKCFGR_PLLSAIDIVQ_2 | RCC_DCKCFGR_PLLSAIDIVQ_1 | RCC_DCKCFGR_PLLSAIDIVQ_0) /*!< PLLSAI division factor for PLLSAIDIVQ output by 24 */
1425 #define LL_RCC_PLLSAIDIVQ_DIV_25 (RCC_DCKCFGR_PLLSAIDIVQ_4 | RCC_DCKCFGR_PLLSAIDIVQ_3) /*!< PLLSAI division factor for PLLSAIDIVQ output by 25 */
1426 #define LL_RCC_PLLSAIDIVQ_DIV_26 (RCC_DCKCFGR_PLLSAIDIVQ_4 | RCC_DCKCFGR_PLLSAIDIVQ_3 | RCC_DCKCFGR_PLLSAIDIVQ_0) /*!< PLLSAI division factor for PLLSAIDIVQ output by 26 */
1427 #define LL_RCC_PLLSAIDIVQ_DIV_27 (RCC_DCKCFGR_PLLSAIDIVQ_4 | RCC_DCKCFGR_PLLSAIDIVQ_3 | RCC_DCKCFGR_PLLSAIDIVQ_1) /*!< PLLSAI division factor for PLLSAIDIVQ output by 27 */
1428 #define LL_RCC_PLLSAIDIVQ_DIV_28 (RCC_DCKCFGR_PLLSAIDIVQ_4 | RCC_DCKCFGR_PLLSAIDIVQ_3 | RCC_DCKCFGR_PLLSAIDIVQ_1 | RCC_DCKCFGR_PLLSAIDIVQ_0) /*!< PLLSAI division factor for PLLSAIDIVQ output by 28 */
1429 #define LL_RCC_PLLSAIDIVQ_DIV_29 (RCC_DCKCFGR_PLLSAIDIVQ_4 | RCC_DCKCFGR_PLLSAIDIVQ_3 | RCC_DCKCFGR_PLLSAIDIVQ_2) /*!< PLLSAI division factor for PLLSAIDIVQ output by 29 */
1430 #define LL_RCC_PLLSAIDIVQ_DIV_30 (RCC_DCKCFGR_PLLSAIDIVQ_4 | RCC_DCKCFGR_PLLSAIDIVQ_3 | RCC_DCKCFGR_PLLSAIDIVQ_2 | RCC_DCKCFGR_PLLSAIDIVQ_0) /*!< PLLSAI division factor for PLLSAIDIVQ output by 30 */
1431 #define LL_RCC_PLLSAIDIVQ_DIV_31 (RCC_DCKCFGR_PLLSAIDIVQ_4 | RCC_DCKCFGR_PLLSAIDIVQ_3 | RCC_DCKCFGR_PLLSAIDIVQ_2 | RCC_DCKCFGR_PLLSAIDIVQ_1) /*!< PLLSAI division factor for PLLSAIDIVQ output by 31 */
1432 #define LL_RCC_PLLSAIDIVQ_DIV_32 (RCC_DCKCFGR_PLLSAIDIVQ_4 | RCC_DCKCFGR_PLLSAIDIVQ_3 | RCC_DCKCFGR_PLLSAIDIVQ_2 | RCC_DCKCFGR_PLLSAIDIVQ_1 | RCC_DCKCFGR_PLLSAIDIVQ_0) /*!< PLLSAI division factor for PLLSAIDIVQ output by 32 */
1433 /**
1434 * @}
1435 */
1436 #endif /* RCC_DCKCFGR_PLLSAIDIVQ */
1437
1438 #if defined(RCC_PLLSAICFGR_PLLSAIR)
1439 /** @defgroup RCC_LL_EC_PLLSAIR PLLSAIR division factor (PLLSAIR)
1440 * @{
1441 */
1442 #define LL_RCC_PLLSAIR_DIV_2 RCC_PLLSAICFGR_PLLSAIR_1 /*!< PLLSAI division factor for PLLSAIR output by 2 */
1443 #define LL_RCC_PLLSAIR_DIV_3 (RCC_PLLSAICFGR_PLLSAIR_1 | RCC_PLLSAICFGR_PLLSAIR_0) /*!< PLLSAI division factor for PLLSAIR output by 3 */
1444 #define LL_RCC_PLLSAIR_DIV_4 RCC_PLLSAICFGR_PLLSAIR_2 /*!< PLLSAI division factor for PLLSAIR output by 4 */
1445 #define LL_RCC_PLLSAIR_DIV_5 (RCC_PLLSAICFGR_PLLSAIR_2 | RCC_PLLSAICFGR_PLLSAIR_0) /*!< PLLSAI division factor for PLLSAIR output by 5 */
1446 #define LL_RCC_PLLSAIR_DIV_6 (RCC_PLLSAICFGR_PLLSAIR_2 | RCC_PLLSAICFGR_PLLSAIR_1) /*!< PLLSAI division factor for PLLSAIR output by 6 */
1447 #define LL_RCC_PLLSAIR_DIV_7 (RCC_PLLSAICFGR_PLLSAIR_2 | RCC_PLLSAICFGR_PLLSAIR_1 | RCC_PLLSAICFGR_PLLSAIR_0) /*!< PLLSAI division factor for PLLSAIR output by 7 */
1448 /**
1449 * @}
1450 */
1451 #endif /* RCC_PLLSAICFGR_PLLSAIR */
1452
1453 #if defined(RCC_DCKCFGR_PLLSAIDIVR)
1454 /** @defgroup RCC_LL_EC_PLLSAIDIVR PLLSAIDIVR division factor (PLLSAIDIVR)
1455 * @{
1456 */
1457 #define LL_RCC_PLLSAIDIVR_DIV_2 0x00000000U /*!< PLLSAI division factor for PLLSAIDIVR output by 2 */
1458 #define LL_RCC_PLLSAIDIVR_DIV_4 RCC_DCKCFGR_PLLSAIDIVR_0 /*!< PLLSAI division factor for PLLSAIDIVR output by 4 */
1459 #define LL_RCC_PLLSAIDIVR_DIV_8 RCC_DCKCFGR_PLLSAIDIVR_1 /*!< PLLSAI division factor for PLLSAIDIVR output by 8 */
1460 #define LL_RCC_PLLSAIDIVR_DIV_16 (RCC_DCKCFGR_PLLSAIDIVR_1 | RCC_DCKCFGR_PLLSAIDIVR_0) /*!< PLLSAI division factor for PLLSAIDIVR output by 16 */
1461 /**
1462 * @}
1463 */
1464 #endif /* RCC_DCKCFGR_PLLSAIDIVR */
1465
1466 #if defined(RCC_PLLSAICFGR_PLLSAIP)
1467 /** @defgroup RCC_LL_EC_PLLSAIP PLLSAIP division factor (PLLSAIP)
1468 * @{
1469 */
1470 #define LL_RCC_PLLSAIP_DIV_2 0x00000000U /*!< PLLSAI division factor for PLLSAIP output by 2 */
1471 #define LL_RCC_PLLSAIP_DIV_4 RCC_PLLSAICFGR_PLLSAIP_0 /*!< PLLSAI division factor for PLLSAIP output by 4 */
1472 #define LL_RCC_PLLSAIP_DIV_6 RCC_PLLSAICFGR_PLLSAIP_1 /*!< PLLSAI division factor for PLLSAIP output by 6 */
1473 #define LL_RCC_PLLSAIP_DIV_8 (RCC_PLLSAICFGR_PLLSAIP_1 | RCC_PLLSAICFGR_PLLSAIP_0) /*!< PLLSAI division factor for PLLSAIP output by 8 */
1474 /**
1475 * @}
1476 */
1477 #endif /* RCC_PLLSAICFGR_PLLSAIP */
1478 #endif /* RCC_PLLSAI_SUPPORT */
1479 /**
1480 * @}
1481 */
1482
1483 /* Exported macro ------------------------------------------------------------*/
1484 /** @defgroup RCC_LL_Exported_Macros RCC Exported Macros
1485 * @{
1486 */
1487
1488 /** @defgroup RCC_LL_EM_WRITE_READ Common Write and read registers Macros
1489 * @{
1490 */
1491
1492 /**
1493 * @brief Write a value in RCC register
1494 * @param __REG__ Register to be written
1495 * @param __VALUE__ Value to be written in the register
1496 * @retval None
1497 */
1498 #define LL_RCC_WriteReg(__REG__, __VALUE__) WRITE_REG(RCC->__REG__, (__VALUE__))
1499
1500 /**
1501 * @brief Read a value in RCC register
1502 * @param __REG__ Register to be read
1503 * @retval Register value
1504 */
1505 #define LL_RCC_ReadReg(__REG__) READ_REG(RCC->__REG__)
1506 /**
1507 * @}
1508 */
1509
1510 /** @defgroup RCC_LL_EM_CALC_FREQ Calculate frequencies
1511 * @{
1512 */
1513
1514 /**
1515 * @brief Helper macro to calculate the PLLCLK frequency on system domain
1516 * @note ex: @ref __LL_RCC_CALC_PLLCLK_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
1517 * @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetP ());
1518 * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
1519 * @param __PLLM__ This parameter can be one of the following values:
1520 * @arg @ref LL_RCC_PLLM_DIV_2
1521 * @arg @ref LL_RCC_PLLM_DIV_3
1522 * @arg @ref LL_RCC_PLLM_DIV_4
1523 * @arg @ref LL_RCC_PLLM_DIV_5
1524 * @arg @ref LL_RCC_PLLM_DIV_6
1525 * @arg @ref LL_RCC_PLLM_DIV_7
1526 * @arg @ref LL_RCC_PLLM_DIV_8
1527 * @arg @ref LL_RCC_PLLM_DIV_9
1528 * @arg @ref LL_RCC_PLLM_DIV_10
1529 * @arg @ref LL_RCC_PLLM_DIV_11
1530 * @arg @ref LL_RCC_PLLM_DIV_12
1531 * @arg @ref LL_RCC_PLLM_DIV_13
1532 * @arg @ref LL_RCC_PLLM_DIV_14
1533 * @arg @ref LL_RCC_PLLM_DIV_15
1534 * @arg @ref LL_RCC_PLLM_DIV_16
1535 * @arg @ref LL_RCC_PLLM_DIV_17
1536 * @arg @ref LL_RCC_PLLM_DIV_18
1537 * @arg @ref LL_RCC_PLLM_DIV_19
1538 * @arg @ref LL_RCC_PLLM_DIV_20
1539 * @arg @ref LL_RCC_PLLM_DIV_21
1540 * @arg @ref LL_RCC_PLLM_DIV_22
1541 * @arg @ref LL_RCC_PLLM_DIV_23
1542 * @arg @ref LL_RCC_PLLM_DIV_24
1543 * @arg @ref LL_RCC_PLLM_DIV_25
1544 * @arg @ref LL_RCC_PLLM_DIV_26
1545 * @arg @ref LL_RCC_PLLM_DIV_27
1546 * @arg @ref LL_RCC_PLLM_DIV_28
1547 * @arg @ref LL_RCC_PLLM_DIV_29
1548 * @arg @ref LL_RCC_PLLM_DIV_30
1549 * @arg @ref LL_RCC_PLLM_DIV_31
1550 * @arg @ref LL_RCC_PLLM_DIV_32
1551 * @arg @ref LL_RCC_PLLM_DIV_33
1552 * @arg @ref LL_RCC_PLLM_DIV_34
1553 * @arg @ref LL_RCC_PLLM_DIV_35
1554 * @arg @ref LL_RCC_PLLM_DIV_36
1555 * @arg @ref LL_RCC_PLLM_DIV_37
1556 * @arg @ref LL_RCC_PLLM_DIV_38
1557 * @arg @ref LL_RCC_PLLM_DIV_39
1558 * @arg @ref LL_RCC_PLLM_DIV_40
1559 * @arg @ref LL_RCC_PLLM_DIV_41
1560 * @arg @ref LL_RCC_PLLM_DIV_42
1561 * @arg @ref LL_RCC_PLLM_DIV_43
1562 * @arg @ref LL_RCC_PLLM_DIV_44
1563 * @arg @ref LL_RCC_PLLM_DIV_45
1564 * @arg @ref LL_RCC_PLLM_DIV_46
1565 * @arg @ref LL_RCC_PLLM_DIV_47
1566 * @arg @ref LL_RCC_PLLM_DIV_48
1567 * @arg @ref LL_RCC_PLLM_DIV_49
1568 * @arg @ref LL_RCC_PLLM_DIV_50
1569 * @arg @ref LL_RCC_PLLM_DIV_51
1570 * @arg @ref LL_RCC_PLLM_DIV_52
1571 * @arg @ref LL_RCC_PLLM_DIV_53
1572 * @arg @ref LL_RCC_PLLM_DIV_54
1573 * @arg @ref LL_RCC_PLLM_DIV_55
1574 * @arg @ref LL_RCC_PLLM_DIV_56
1575 * @arg @ref LL_RCC_PLLM_DIV_57
1576 * @arg @ref LL_RCC_PLLM_DIV_58
1577 * @arg @ref LL_RCC_PLLM_DIV_59
1578 * @arg @ref LL_RCC_PLLM_DIV_60
1579 * @arg @ref LL_RCC_PLLM_DIV_61
1580 * @arg @ref LL_RCC_PLLM_DIV_62
1581 * @arg @ref LL_RCC_PLLM_DIV_63
1582 * @param __PLLN__ Between 50/192(*) and 432
1583 *
1584 * (*) value not defined in all devices.
1585 * @param __PLLP__ This parameter can be one of the following values:
1586 * @arg @ref LL_RCC_PLLP_DIV_2
1587 * @arg @ref LL_RCC_PLLP_DIV_4
1588 * @arg @ref LL_RCC_PLLP_DIV_6
1589 * @arg @ref LL_RCC_PLLP_DIV_8
1590 * @retval PLL clock frequency (in Hz)
1591 */
1592 #define __LL_RCC_CALC_PLLCLK_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLP__) ((__INPUTFREQ__) / (__PLLM__) * (__PLLN__) / \
1593 ((((__PLLP__) >> RCC_PLLCFGR_PLLP_Pos ) + 1U) * 2U))
1594
1595 #if defined(RCC_PLLR_SYSCLK_SUPPORT)
1596 /**
1597 * @brief Helper macro to calculate the PLLRCLK frequency on system domain
1598 * @note ex: @ref __LL_RCC_CALC_PLLRCLK_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
1599 * @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetR ());
1600 * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
1601 * @param __PLLM__ This parameter can be one of the following values:
1602 * @arg @ref LL_RCC_PLLM_DIV_2
1603 * @arg @ref LL_RCC_PLLM_DIV_3
1604 * @arg @ref LL_RCC_PLLM_DIV_4
1605 * @arg @ref LL_RCC_PLLM_DIV_5
1606 * @arg @ref LL_RCC_PLLM_DIV_6
1607 * @arg @ref LL_RCC_PLLM_DIV_7
1608 * @arg @ref LL_RCC_PLLM_DIV_8
1609 * @arg @ref LL_RCC_PLLM_DIV_9
1610 * @arg @ref LL_RCC_PLLM_DIV_10
1611 * @arg @ref LL_RCC_PLLM_DIV_11
1612 * @arg @ref LL_RCC_PLLM_DIV_12
1613 * @arg @ref LL_RCC_PLLM_DIV_13
1614 * @arg @ref LL_RCC_PLLM_DIV_14
1615 * @arg @ref LL_RCC_PLLM_DIV_15
1616 * @arg @ref LL_RCC_PLLM_DIV_16
1617 * @arg @ref LL_RCC_PLLM_DIV_17
1618 * @arg @ref LL_RCC_PLLM_DIV_18
1619 * @arg @ref LL_RCC_PLLM_DIV_19
1620 * @arg @ref LL_RCC_PLLM_DIV_20
1621 * @arg @ref LL_RCC_PLLM_DIV_21
1622 * @arg @ref LL_RCC_PLLM_DIV_22
1623 * @arg @ref LL_RCC_PLLM_DIV_23
1624 * @arg @ref LL_RCC_PLLM_DIV_24
1625 * @arg @ref LL_RCC_PLLM_DIV_25
1626 * @arg @ref LL_RCC_PLLM_DIV_26
1627 * @arg @ref LL_RCC_PLLM_DIV_27
1628 * @arg @ref LL_RCC_PLLM_DIV_28
1629 * @arg @ref LL_RCC_PLLM_DIV_29
1630 * @arg @ref LL_RCC_PLLM_DIV_30
1631 * @arg @ref LL_RCC_PLLM_DIV_31
1632 * @arg @ref LL_RCC_PLLM_DIV_32
1633 * @arg @ref LL_RCC_PLLM_DIV_33
1634 * @arg @ref LL_RCC_PLLM_DIV_34
1635 * @arg @ref LL_RCC_PLLM_DIV_35
1636 * @arg @ref LL_RCC_PLLM_DIV_36
1637 * @arg @ref LL_RCC_PLLM_DIV_37
1638 * @arg @ref LL_RCC_PLLM_DIV_38
1639 * @arg @ref LL_RCC_PLLM_DIV_39
1640 * @arg @ref LL_RCC_PLLM_DIV_40
1641 * @arg @ref LL_RCC_PLLM_DIV_41
1642 * @arg @ref LL_RCC_PLLM_DIV_42
1643 * @arg @ref LL_RCC_PLLM_DIV_43
1644 * @arg @ref LL_RCC_PLLM_DIV_44
1645 * @arg @ref LL_RCC_PLLM_DIV_45
1646 * @arg @ref LL_RCC_PLLM_DIV_46
1647 * @arg @ref LL_RCC_PLLM_DIV_47
1648 * @arg @ref LL_RCC_PLLM_DIV_48
1649 * @arg @ref LL_RCC_PLLM_DIV_49
1650 * @arg @ref LL_RCC_PLLM_DIV_50
1651 * @arg @ref LL_RCC_PLLM_DIV_51
1652 * @arg @ref LL_RCC_PLLM_DIV_52
1653 * @arg @ref LL_RCC_PLLM_DIV_53
1654 * @arg @ref LL_RCC_PLLM_DIV_54
1655 * @arg @ref LL_RCC_PLLM_DIV_55
1656 * @arg @ref LL_RCC_PLLM_DIV_56
1657 * @arg @ref LL_RCC_PLLM_DIV_57
1658 * @arg @ref LL_RCC_PLLM_DIV_58
1659 * @arg @ref LL_RCC_PLLM_DIV_59
1660 * @arg @ref LL_RCC_PLLM_DIV_60
1661 * @arg @ref LL_RCC_PLLM_DIV_61
1662 * @arg @ref LL_RCC_PLLM_DIV_62
1663 * @arg @ref LL_RCC_PLLM_DIV_63
1664 * @param __PLLN__ Between 50 and 432
1665 * @param __PLLR__ This parameter can be one of the following values:
1666 * @arg @ref LL_RCC_PLLR_DIV_2
1667 * @arg @ref LL_RCC_PLLR_DIV_3
1668 * @arg @ref LL_RCC_PLLR_DIV_4
1669 * @arg @ref LL_RCC_PLLR_DIV_5
1670 * @arg @ref LL_RCC_PLLR_DIV_6
1671 * @arg @ref LL_RCC_PLLR_DIV_7
1672 * @retval PLL clock frequency (in Hz)
1673 */
1674 #define __LL_RCC_CALC_PLLRCLK_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLR__) ((__INPUTFREQ__) / (__PLLM__) * (__PLLN__) / \
1675 ((__PLLR__) >> RCC_PLLCFGR_PLLR_Pos ))
1676
1677 #endif /* RCC_PLLR_SYSCLK_SUPPORT */
1678
1679 /**
1680 * @brief Helper macro to calculate the PLLCLK frequency used on 48M domain
1681 * @note ex: @ref __LL_RCC_CALC_PLLCLK_48M_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
1682 * @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetQ ());
1683 * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
1684 * @param __PLLM__ This parameter can be one of the following values:
1685 * @arg @ref LL_RCC_PLLM_DIV_2
1686 * @arg @ref LL_RCC_PLLM_DIV_3
1687 * @arg @ref LL_RCC_PLLM_DIV_4
1688 * @arg @ref LL_RCC_PLLM_DIV_5
1689 * @arg @ref LL_RCC_PLLM_DIV_6
1690 * @arg @ref LL_RCC_PLLM_DIV_7
1691 * @arg @ref LL_RCC_PLLM_DIV_8
1692 * @arg @ref LL_RCC_PLLM_DIV_9
1693 * @arg @ref LL_RCC_PLLM_DIV_10
1694 * @arg @ref LL_RCC_PLLM_DIV_11
1695 * @arg @ref LL_RCC_PLLM_DIV_12
1696 * @arg @ref LL_RCC_PLLM_DIV_13
1697 * @arg @ref LL_RCC_PLLM_DIV_14
1698 * @arg @ref LL_RCC_PLLM_DIV_15
1699 * @arg @ref LL_RCC_PLLM_DIV_16
1700 * @arg @ref LL_RCC_PLLM_DIV_17
1701 * @arg @ref LL_RCC_PLLM_DIV_18
1702 * @arg @ref LL_RCC_PLLM_DIV_19
1703 * @arg @ref LL_RCC_PLLM_DIV_20
1704 * @arg @ref LL_RCC_PLLM_DIV_21
1705 * @arg @ref LL_RCC_PLLM_DIV_22
1706 * @arg @ref LL_RCC_PLLM_DIV_23
1707 * @arg @ref LL_RCC_PLLM_DIV_24
1708 * @arg @ref LL_RCC_PLLM_DIV_25
1709 * @arg @ref LL_RCC_PLLM_DIV_26
1710 * @arg @ref LL_RCC_PLLM_DIV_27
1711 * @arg @ref LL_RCC_PLLM_DIV_28
1712 * @arg @ref LL_RCC_PLLM_DIV_29
1713 * @arg @ref LL_RCC_PLLM_DIV_30
1714 * @arg @ref LL_RCC_PLLM_DIV_31
1715 * @arg @ref LL_RCC_PLLM_DIV_32
1716 * @arg @ref LL_RCC_PLLM_DIV_33
1717 * @arg @ref LL_RCC_PLLM_DIV_34
1718 * @arg @ref LL_RCC_PLLM_DIV_35
1719 * @arg @ref LL_RCC_PLLM_DIV_36
1720 * @arg @ref LL_RCC_PLLM_DIV_37
1721 * @arg @ref LL_RCC_PLLM_DIV_38
1722 * @arg @ref LL_RCC_PLLM_DIV_39
1723 * @arg @ref LL_RCC_PLLM_DIV_40
1724 * @arg @ref LL_RCC_PLLM_DIV_41
1725 * @arg @ref LL_RCC_PLLM_DIV_42
1726 * @arg @ref LL_RCC_PLLM_DIV_43
1727 * @arg @ref LL_RCC_PLLM_DIV_44
1728 * @arg @ref LL_RCC_PLLM_DIV_45
1729 * @arg @ref LL_RCC_PLLM_DIV_46
1730 * @arg @ref LL_RCC_PLLM_DIV_47
1731 * @arg @ref LL_RCC_PLLM_DIV_48
1732 * @arg @ref LL_RCC_PLLM_DIV_49
1733 * @arg @ref LL_RCC_PLLM_DIV_50
1734 * @arg @ref LL_RCC_PLLM_DIV_51
1735 * @arg @ref LL_RCC_PLLM_DIV_52
1736 * @arg @ref LL_RCC_PLLM_DIV_53
1737 * @arg @ref LL_RCC_PLLM_DIV_54
1738 * @arg @ref LL_RCC_PLLM_DIV_55
1739 * @arg @ref LL_RCC_PLLM_DIV_56
1740 * @arg @ref LL_RCC_PLLM_DIV_57
1741 * @arg @ref LL_RCC_PLLM_DIV_58
1742 * @arg @ref LL_RCC_PLLM_DIV_59
1743 * @arg @ref LL_RCC_PLLM_DIV_60
1744 * @arg @ref LL_RCC_PLLM_DIV_61
1745 * @arg @ref LL_RCC_PLLM_DIV_62
1746 * @arg @ref LL_RCC_PLLM_DIV_63
1747 * @param __PLLN__ Between 50/192(*) and 432
1748 *
1749 * (*) value not defined in all devices.
1750 * @param __PLLQ__ This parameter can be one of the following values:
1751 * @arg @ref LL_RCC_PLLQ_DIV_2
1752 * @arg @ref LL_RCC_PLLQ_DIV_3
1753 * @arg @ref LL_RCC_PLLQ_DIV_4
1754 * @arg @ref LL_RCC_PLLQ_DIV_5
1755 * @arg @ref LL_RCC_PLLQ_DIV_6
1756 * @arg @ref LL_RCC_PLLQ_DIV_7
1757 * @arg @ref LL_RCC_PLLQ_DIV_8
1758 * @arg @ref LL_RCC_PLLQ_DIV_9
1759 * @arg @ref LL_RCC_PLLQ_DIV_10
1760 * @arg @ref LL_RCC_PLLQ_DIV_11
1761 * @arg @ref LL_RCC_PLLQ_DIV_12
1762 * @arg @ref LL_RCC_PLLQ_DIV_13
1763 * @arg @ref LL_RCC_PLLQ_DIV_14
1764 * @arg @ref LL_RCC_PLLQ_DIV_15
1765 * @retval PLL clock frequency (in Hz)
1766 */
1767 #define __LL_RCC_CALC_PLLCLK_48M_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLQ__) ((__INPUTFREQ__) / (__PLLM__) * (__PLLN__) / \
1768 ((__PLLQ__) >> RCC_PLLCFGR_PLLQ_Pos ))
1769
1770 #if defined(DSI)
1771 /**
1772 * @brief Helper macro to calculate the PLLCLK frequency used on DSI
1773 * @note ex: @ref __LL_RCC_CALC_PLLCLK_DSI_FREQ (HSE_VALUE, @ref LL_RCC_PLL_GetDivider (),
1774 * @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetR ());
1775 * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
1776 * @param __PLLM__ This parameter can be one of the following values:
1777 * @arg @ref LL_RCC_PLLM_DIV_2
1778 * @arg @ref LL_RCC_PLLM_DIV_3
1779 * @arg @ref LL_RCC_PLLM_DIV_4
1780 * @arg @ref LL_RCC_PLLM_DIV_5
1781 * @arg @ref LL_RCC_PLLM_DIV_6
1782 * @arg @ref LL_RCC_PLLM_DIV_7
1783 * @arg @ref LL_RCC_PLLM_DIV_8
1784 * @arg @ref LL_RCC_PLLM_DIV_9
1785 * @arg @ref LL_RCC_PLLM_DIV_10
1786 * @arg @ref LL_RCC_PLLM_DIV_11
1787 * @arg @ref LL_RCC_PLLM_DIV_12
1788 * @arg @ref LL_RCC_PLLM_DIV_13
1789 * @arg @ref LL_RCC_PLLM_DIV_14
1790 * @arg @ref LL_RCC_PLLM_DIV_15
1791 * @arg @ref LL_RCC_PLLM_DIV_16
1792 * @arg @ref LL_RCC_PLLM_DIV_17
1793 * @arg @ref LL_RCC_PLLM_DIV_18
1794 * @arg @ref LL_RCC_PLLM_DIV_19
1795 * @arg @ref LL_RCC_PLLM_DIV_20
1796 * @arg @ref LL_RCC_PLLM_DIV_21
1797 * @arg @ref LL_RCC_PLLM_DIV_22
1798 * @arg @ref LL_RCC_PLLM_DIV_23
1799 * @arg @ref LL_RCC_PLLM_DIV_24
1800 * @arg @ref LL_RCC_PLLM_DIV_25
1801 * @arg @ref LL_RCC_PLLM_DIV_26
1802 * @arg @ref LL_RCC_PLLM_DIV_27
1803 * @arg @ref LL_RCC_PLLM_DIV_28
1804 * @arg @ref LL_RCC_PLLM_DIV_29
1805 * @arg @ref LL_RCC_PLLM_DIV_30
1806 * @arg @ref LL_RCC_PLLM_DIV_31
1807 * @arg @ref LL_RCC_PLLM_DIV_32
1808 * @arg @ref LL_RCC_PLLM_DIV_33
1809 * @arg @ref LL_RCC_PLLM_DIV_34
1810 * @arg @ref LL_RCC_PLLM_DIV_35
1811 * @arg @ref LL_RCC_PLLM_DIV_36
1812 * @arg @ref LL_RCC_PLLM_DIV_37
1813 * @arg @ref LL_RCC_PLLM_DIV_38
1814 * @arg @ref LL_RCC_PLLM_DIV_39
1815 * @arg @ref LL_RCC_PLLM_DIV_40
1816 * @arg @ref LL_RCC_PLLM_DIV_41
1817 * @arg @ref LL_RCC_PLLM_DIV_42
1818 * @arg @ref LL_RCC_PLLM_DIV_43
1819 * @arg @ref LL_RCC_PLLM_DIV_44
1820 * @arg @ref LL_RCC_PLLM_DIV_45
1821 * @arg @ref LL_RCC_PLLM_DIV_46
1822 * @arg @ref LL_RCC_PLLM_DIV_47
1823 * @arg @ref LL_RCC_PLLM_DIV_48
1824 * @arg @ref LL_RCC_PLLM_DIV_49
1825 * @arg @ref LL_RCC_PLLM_DIV_50
1826 * @arg @ref LL_RCC_PLLM_DIV_51
1827 * @arg @ref LL_RCC_PLLM_DIV_52
1828 * @arg @ref LL_RCC_PLLM_DIV_53
1829 * @arg @ref LL_RCC_PLLM_DIV_54
1830 * @arg @ref LL_RCC_PLLM_DIV_55
1831 * @arg @ref LL_RCC_PLLM_DIV_56
1832 * @arg @ref LL_RCC_PLLM_DIV_57
1833 * @arg @ref LL_RCC_PLLM_DIV_58
1834 * @arg @ref LL_RCC_PLLM_DIV_59
1835 * @arg @ref LL_RCC_PLLM_DIV_60
1836 * @arg @ref LL_RCC_PLLM_DIV_61
1837 * @arg @ref LL_RCC_PLLM_DIV_62
1838 * @arg @ref LL_RCC_PLLM_DIV_63
1839 * @param __PLLN__ Between 50 and 432
1840 * @param __PLLR__ This parameter can be one of the following values:
1841 * @arg @ref LL_RCC_PLLR_DIV_2
1842 * @arg @ref LL_RCC_PLLR_DIV_3
1843 * @arg @ref LL_RCC_PLLR_DIV_4
1844 * @arg @ref LL_RCC_PLLR_DIV_5
1845 * @arg @ref LL_RCC_PLLR_DIV_6
1846 * @arg @ref LL_RCC_PLLR_DIV_7
1847 * @retval PLL clock frequency (in Hz)
1848 */
1849 #define __LL_RCC_CALC_PLLCLK_DSI_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLR__) ((__INPUTFREQ__) / (__PLLM__) * (__PLLN__) / \
1850 ((__PLLR__) >> RCC_PLLCFGR_PLLR_Pos ))
1851 #endif /* DSI */
1852
1853 #if defined(RCC_PLLR_I2S_CLKSOURCE_SUPPORT)
1854 /**
1855 * @brief Helper macro to calculate the PLLCLK frequency used on I2S
1856 * @note ex: @ref __LL_RCC_CALC_PLLCLK_I2S_FREQ (HSE_VALUE, @ref LL_RCC_PLL_GetDivider (),
1857 * @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetR ());
1858 * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
1859 * @param __PLLM__ This parameter can be one of the following values:
1860 * @arg @ref LL_RCC_PLLM_DIV_2
1861 * @arg @ref LL_RCC_PLLM_DIV_3
1862 * @arg @ref LL_RCC_PLLM_DIV_4
1863 * @arg @ref LL_RCC_PLLM_DIV_5
1864 * @arg @ref LL_RCC_PLLM_DIV_6
1865 * @arg @ref LL_RCC_PLLM_DIV_7
1866 * @arg @ref LL_RCC_PLLM_DIV_8
1867 * @arg @ref LL_RCC_PLLM_DIV_9
1868 * @arg @ref LL_RCC_PLLM_DIV_10
1869 * @arg @ref LL_RCC_PLLM_DIV_11
1870 * @arg @ref LL_RCC_PLLM_DIV_12
1871 * @arg @ref LL_RCC_PLLM_DIV_13
1872 * @arg @ref LL_RCC_PLLM_DIV_14
1873 * @arg @ref LL_RCC_PLLM_DIV_15
1874 * @arg @ref LL_RCC_PLLM_DIV_16
1875 * @arg @ref LL_RCC_PLLM_DIV_17
1876 * @arg @ref LL_RCC_PLLM_DIV_18
1877 * @arg @ref LL_RCC_PLLM_DIV_19
1878 * @arg @ref LL_RCC_PLLM_DIV_20
1879 * @arg @ref LL_RCC_PLLM_DIV_21
1880 * @arg @ref LL_RCC_PLLM_DIV_22
1881 * @arg @ref LL_RCC_PLLM_DIV_23
1882 * @arg @ref LL_RCC_PLLM_DIV_24
1883 * @arg @ref LL_RCC_PLLM_DIV_25
1884 * @arg @ref LL_RCC_PLLM_DIV_26
1885 * @arg @ref LL_RCC_PLLM_DIV_27
1886 * @arg @ref LL_RCC_PLLM_DIV_28
1887 * @arg @ref LL_RCC_PLLM_DIV_29
1888 * @arg @ref LL_RCC_PLLM_DIV_30
1889 * @arg @ref LL_RCC_PLLM_DIV_31
1890 * @arg @ref LL_RCC_PLLM_DIV_32
1891 * @arg @ref LL_RCC_PLLM_DIV_33
1892 * @arg @ref LL_RCC_PLLM_DIV_34
1893 * @arg @ref LL_RCC_PLLM_DIV_35
1894 * @arg @ref LL_RCC_PLLM_DIV_36
1895 * @arg @ref LL_RCC_PLLM_DIV_37
1896 * @arg @ref LL_RCC_PLLM_DIV_38
1897 * @arg @ref LL_RCC_PLLM_DIV_39
1898 * @arg @ref LL_RCC_PLLM_DIV_40
1899 * @arg @ref LL_RCC_PLLM_DIV_41
1900 * @arg @ref LL_RCC_PLLM_DIV_42
1901 * @arg @ref LL_RCC_PLLM_DIV_43
1902 * @arg @ref LL_RCC_PLLM_DIV_44
1903 * @arg @ref LL_RCC_PLLM_DIV_45
1904 * @arg @ref LL_RCC_PLLM_DIV_46
1905 * @arg @ref LL_RCC_PLLM_DIV_47
1906 * @arg @ref LL_RCC_PLLM_DIV_48
1907 * @arg @ref LL_RCC_PLLM_DIV_49
1908 * @arg @ref LL_RCC_PLLM_DIV_50
1909 * @arg @ref LL_RCC_PLLM_DIV_51
1910 * @arg @ref LL_RCC_PLLM_DIV_52
1911 * @arg @ref LL_RCC_PLLM_DIV_53
1912 * @arg @ref LL_RCC_PLLM_DIV_54
1913 * @arg @ref LL_RCC_PLLM_DIV_55
1914 * @arg @ref LL_RCC_PLLM_DIV_56
1915 * @arg @ref LL_RCC_PLLM_DIV_57
1916 * @arg @ref LL_RCC_PLLM_DIV_58
1917 * @arg @ref LL_RCC_PLLM_DIV_59
1918 * @arg @ref LL_RCC_PLLM_DIV_60
1919 * @arg @ref LL_RCC_PLLM_DIV_61
1920 * @arg @ref LL_RCC_PLLM_DIV_62
1921 * @arg @ref LL_RCC_PLLM_DIV_63
1922 * @param __PLLN__ Between 50 and 432
1923 * @param __PLLR__ This parameter can be one of the following values:
1924 * @arg @ref LL_RCC_PLLR_DIV_2
1925 * @arg @ref LL_RCC_PLLR_DIV_3
1926 * @arg @ref LL_RCC_PLLR_DIV_4
1927 * @arg @ref LL_RCC_PLLR_DIV_5
1928 * @arg @ref LL_RCC_PLLR_DIV_6
1929 * @arg @ref LL_RCC_PLLR_DIV_7
1930 * @retval PLL clock frequency (in Hz)
1931 */
1932 #define __LL_RCC_CALC_PLLCLK_I2S_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLR__) ((__INPUTFREQ__) / (__PLLM__) * (__PLLN__) / \
1933 ((__PLLR__) >> RCC_PLLCFGR_PLLR_Pos ))
1934 #endif /* RCC_PLLR_I2S_CLKSOURCE_SUPPORT */
1935
1936 #if defined(SPDIFRX)
1937 /**
1938 * @brief Helper macro to calculate the PLLCLK frequency used on SPDIFRX
1939 * @note ex: @ref __LL_RCC_CALC_PLLCLK_SPDIFRX_FREQ (HSE_VALUE, @ref LL_RCC_PLL_GetDivider (),
1940 * @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetR ());
1941 * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
1942 * @param __PLLM__ This parameter can be one of the following values:
1943 * @arg @ref LL_RCC_PLLM_DIV_2
1944 * @arg @ref LL_RCC_PLLM_DIV_3
1945 * @arg @ref LL_RCC_PLLM_DIV_4
1946 * @arg @ref LL_RCC_PLLM_DIV_5
1947 * @arg @ref LL_RCC_PLLM_DIV_6
1948 * @arg @ref LL_RCC_PLLM_DIV_7
1949 * @arg @ref LL_RCC_PLLM_DIV_8
1950 * @arg @ref LL_RCC_PLLM_DIV_9
1951 * @arg @ref LL_RCC_PLLM_DIV_10
1952 * @arg @ref LL_RCC_PLLM_DIV_11
1953 * @arg @ref LL_RCC_PLLM_DIV_12
1954 * @arg @ref LL_RCC_PLLM_DIV_13
1955 * @arg @ref LL_RCC_PLLM_DIV_14
1956 * @arg @ref LL_RCC_PLLM_DIV_15
1957 * @arg @ref LL_RCC_PLLM_DIV_16
1958 * @arg @ref LL_RCC_PLLM_DIV_17
1959 * @arg @ref LL_RCC_PLLM_DIV_18
1960 * @arg @ref LL_RCC_PLLM_DIV_19
1961 * @arg @ref LL_RCC_PLLM_DIV_20
1962 * @arg @ref LL_RCC_PLLM_DIV_21
1963 * @arg @ref LL_RCC_PLLM_DIV_22
1964 * @arg @ref LL_RCC_PLLM_DIV_23
1965 * @arg @ref LL_RCC_PLLM_DIV_24
1966 * @arg @ref LL_RCC_PLLM_DIV_25
1967 * @arg @ref LL_RCC_PLLM_DIV_26
1968 * @arg @ref LL_RCC_PLLM_DIV_27
1969 * @arg @ref LL_RCC_PLLM_DIV_28
1970 * @arg @ref LL_RCC_PLLM_DIV_29
1971 * @arg @ref LL_RCC_PLLM_DIV_30
1972 * @arg @ref LL_RCC_PLLM_DIV_31
1973 * @arg @ref LL_RCC_PLLM_DIV_32
1974 * @arg @ref LL_RCC_PLLM_DIV_33
1975 * @arg @ref LL_RCC_PLLM_DIV_34
1976 * @arg @ref LL_RCC_PLLM_DIV_35
1977 * @arg @ref LL_RCC_PLLM_DIV_36
1978 * @arg @ref LL_RCC_PLLM_DIV_37
1979 * @arg @ref LL_RCC_PLLM_DIV_38
1980 * @arg @ref LL_RCC_PLLM_DIV_39
1981 * @arg @ref LL_RCC_PLLM_DIV_40
1982 * @arg @ref LL_RCC_PLLM_DIV_41
1983 * @arg @ref LL_RCC_PLLM_DIV_42
1984 * @arg @ref LL_RCC_PLLM_DIV_43
1985 * @arg @ref LL_RCC_PLLM_DIV_44
1986 * @arg @ref LL_RCC_PLLM_DIV_45
1987 * @arg @ref LL_RCC_PLLM_DIV_46
1988 * @arg @ref LL_RCC_PLLM_DIV_47
1989 * @arg @ref LL_RCC_PLLM_DIV_48
1990 * @arg @ref LL_RCC_PLLM_DIV_49
1991 * @arg @ref LL_RCC_PLLM_DIV_50
1992 * @arg @ref LL_RCC_PLLM_DIV_51
1993 * @arg @ref LL_RCC_PLLM_DIV_52
1994 * @arg @ref LL_RCC_PLLM_DIV_53
1995 * @arg @ref LL_RCC_PLLM_DIV_54
1996 * @arg @ref LL_RCC_PLLM_DIV_55
1997 * @arg @ref LL_RCC_PLLM_DIV_56
1998 * @arg @ref LL_RCC_PLLM_DIV_57
1999 * @arg @ref LL_RCC_PLLM_DIV_58
2000 * @arg @ref LL_RCC_PLLM_DIV_59
2001 * @arg @ref LL_RCC_PLLM_DIV_60
2002 * @arg @ref LL_RCC_PLLM_DIV_61
2003 * @arg @ref LL_RCC_PLLM_DIV_62
2004 * @arg @ref LL_RCC_PLLM_DIV_63
2005 * @param __PLLN__ Between 50 and 432
2006 * @param __PLLR__ This parameter can be one of the following values:
2007 * @arg @ref LL_RCC_PLLR_DIV_2
2008 * @arg @ref LL_RCC_PLLR_DIV_3
2009 * @arg @ref LL_RCC_PLLR_DIV_4
2010 * @arg @ref LL_RCC_PLLR_DIV_5
2011 * @arg @ref LL_RCC_PLLR_DIV_6
2012 * @arg @ref LL_RCC_PLLR_DIV_7
2013 * @retval PLL clock frequency (in Hz)
2014 */
2015 #define __LL_RCC_CALC_PLLCLK_SPDIFRX_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLR__) ((__INPUTFREQ__) / (__PLLM__) * (__PLLN__) / \
2016 ((__PLLR__) >> RCC_PLLCFGR_PLLR_Pos ))
2017 #endif /* SPDIFRX */
2018
2019 #if defined(RCC_PLLCFGR_PLLR)
2020 #if defined(SAI1)
2021 /**
2022 * @brief Helper macro to calculate the PLLCLK frequency used on SAI
2023 * @note ex: @ref __LL_RCC_CALC_PLLCLK_SAI_FREQ (HSE_VALUE, @ref LL_RCC_PLL_GetDivider (),
2024 * @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetR (), @ref LL_RCC_PLL_GetDIVR ());
2025 * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
2026 * @param __PLLM__ This parameter can be one of the following values:
2027 * @arg @ref LL_RCC_PLLM_DIV_2
2028 * @arg @ref LL_RCC_PLLM_DIV_3
2029 * @arg @ref LL_RCC_PLLM_DIV_4
2030 * @arg @ref LL_RCC_PLLM_DIV_5
2031 * @arg @ref LL_RCC_PLLM_DIV_6
2032 * @arg @ref LL_RCC_PLLM_DIV_7
2033 * @arg @ref LL_RCC_PLLM_DIV_8
2034 * @arg @ref LL_RCC_PLLM_DIV_9
2035 * @arg @ref LL_RCC_PLLM_DIV_10
2036 * @arg @ref LL_RCC_PLLM_DIV_11
2037 * @arg @ref LL_RCC_PLLM_DIV_12
2038 * @arg @ref LL_RCC_PLLM_DIV_13
2039 * @arg @ref LL_RCC_PLLM_DIV_14
2040 * @arg @ref LL_RCC_PLLM_DIV_15
2041 * @arg @ref LL_RCC_PLLM_DIV_16
2042 * @arg @ref LL_RCC_PLLM_DIV_17
2043 * @arg @ref LL_RCC_PLLM_DIV_18
2044 * @arg @ref LL_RCC_PLLM_DIV_19
2045 * @arg @ref LL_RCC_PLLM_DIV_20
2046 * @arg @ref LL_RCC_PLLM_DIV_21
2047 * @arg @ref LL_RCC_PLLM_DIV_22
2048 * @arg @ref LL_RCC_PLLM_DIV_23
2049 * @arg @ref LL_RCC_PLLM_DIV_24
2050 * @arg @ref LL_RCC_PLLM_DIV_25
2051 * @arg @ref LL_RCC_PLLM_DIV_26
2052 * @arg @ref LL_RCC_PLLM_DIV_27
2053 * @arg @ref LL_RCC_PLLM_DIV_28
2054 * @arg @ref LL_RCC_PLLM_DIV_29
2055 * @arg @ref LL_RCC_PLLM_DIV_30
2056 * @arg @ref LL_RCC_PLLM_DIV_31
2057 * @arg @ref LL_RCC_PLLM_DIV_32
2058 * @arg @ref LL_RCC_PLLM_DIV_33
2059 * @arg @ref LL_RCC_PLLM_DIV_34
2060 * @arg @ref LL_RCC_PLLM_DIV_35
2061 * @arg @ref LL_RCC_PLLM_DIV_36
2062 * @arg @ref LL_RCC_PLLM_DIV_37
2063 * @arg @ref LL_RCC_PLLM_DIV_38
2064 * @arg @ref LL_RCC_PLLM_DIV_39
2065 * @arg @ref LL_RCC_PLLM_DIV_40
2066 * @arg @ref LL_RCC_PLLM_DIV_41
2067 * @arg @ref LL_RCC_PLLM_DIV_42
2068 * @arg @ref LL_RCC_PLLM_DIV_43
2069 * @arg @ref LL_RCC_PLLM_DIV_44
2070 * @arg @ref LL_RCC_PLLM_DIV_45
2071 * @arg @ref LL_RCC_PLLM_DIV_46
2072 * @arg @ref LL_RCC_PLLM_DIV_47
2073 * @arg @ref LL_RCC_PLLM_DIV_48
2074 * @arg @ref LL_RCC_PLLM_DIV_49
2075 * @arg @ref LL_RCC_PLLM_DIV_50
2076 * @arg @ref LL_RCC_PLLM_DIV_51
2077 * @arg @ref LL_RCC_PLLM_DIV_52
2078 * @arg @ref LL_RCC_PLLM_DIV_53
2079 * @arg @ref LL_RCC_PLLM_DIV_54
2080 * @arg @ref LL_RCC_PLLM_DIV_55
2081 * @arg @ref LL_RCC_PLLM_DIV_56
2082 * @arg @ref LL_RCC_PLLM_DIV_57
2083 * @arg @ref LL_RCC_PLLM_DIV_58
2084 * @arg @ref LL_RCC_PLLM_DIV_59
2085 * @arg @ref LL_RCC_PLLM_DIV_60
2086 * @arg @ref LL_RCC_PLLM_DIV_61
2087 * @arg @ref LL_RCC_PLLM_DIV_62
2088 * @arg @ref LL_RCC_PLLM_DIV_63
2089 * @param __PLLN__ Between 50 and 432
2090 * @param __PLLR__ This parameter can be one of the following values:
2091 * @arg @ref LL_RCC_PLLR_DIV_2
2092 * @arg @ref LL_RCC_PLLR_DIV_3
2093 * @arg @ref LL_RCC_PLLR_DIV_4
2094 * @arg @ref LL_RCC_PLLR_DIV_5
2095 * @arg @ref LL_RCC_PLLR_DIV_6
2096 * @arg @ref LL_RCC_PLLR_DIV_7
2097 * @param __PLLDIVR__ This parameter can be one of the following values:
2098 * @arg @ref LL_RCC_PLLDIVR_DIV_1 (*)
2099 * @arg @ref LL_RCC_PLLDIVR_DIV_2 (*)
2100 * @arg @ref LL_RCC_PLLDIVR_DIV_3 (*)
2101 * @arg @ref LL_RCC_PLLDIVR_DIV_4 (*)
2102 * @arg @ref LL_RCC_PLLDIVR_DIV_5 (*)
2103 * @arg @ref LL_RCC_PLLDIVR_DIV_6 (*)
2104 * @arg @ref LL_RCC_PLLDIVR_DIV_7 (*)
2105 * @arg @ref LL_RCC_PLLDIVR_DIV_8 (*)
2106 * @arg @ref LL_RCC_PLLDIVR_DIV_9 (*)
2107 * @arg @ref LL_RCC_PLLDIVR_DIV_10 (*)
2108 * @arg @ref LL_RCC_PLLDIVR_DIV_11 (*)
2109 * @arg @ref LL_RCC_PLLDIVR_DIV_12 (*)
2110 * @arg @ref LL_RCC_PLLDIVR_DIV_13 (*)
2111 * @arg @ref LL_RCC_PLLDIVR_DIV_14 (*)
2112 * @arg @ref LL_RCC_PLLDIVR_DIV_15 (*)
2113 * @arg @ref LL_RCC_PLLDIVR_DIV_16 (*)
2114 * @arg @ref LL_RCC_PLLDIVR_DIV_17 (*)
2115 * @arg @ref LL_RCC_PLLDIVR_DIV_18 (*)
2116 * @arg @ref LL_RCC_PLLDIVR_DIV_19 (*)
2117 * @arg @ref LL_RCC_PLLDIVR_DIV_20 (*)
2118 * @arg @ref LL_RCC_PLLDIVR_DIV_21 (*)
2119 * @arg @ref LL_RCC_PLLDIVR_DIV_22 (*)
2120 * @arg @ref LL_RCC_PLLDIVR_DIV_23 (*)
2121 * @arg @ref LL_RCC_PLLDIVR_DIV_24 (*)
2122 * @arg @ref LL_RCC_PLLDIVR_DIV_25 (*)
2123 * @arg @ref LL_RCC_PLLDIVR_DIV_26 (*)
2124 * @arg @ref LL_RCC_PLLDIVR_DIV_27 (*)
2125 * @arg @ref LL_RCC_PLLDIVR_DIV_28 (*)
2126 * @arg @ref LL_RCC_PLLDIVR_DIV_29 (*)
2127 * @arg @ref LL_RCC_PLLDIVR_DIV_30 (*)
2128 * @arg @ref LL_RCC_PLLDIVR_DIV_31 (*)
2129 *
2130 * (*) value not defined in all devices.
2131 * @retval PLL clock frequency (in Hz)
2132 */
2133 #if defined(RCC_DCKCFGR_PLLDIVR)
2134 #define __LL_RCC_CALC_PLLCLK_SAI_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLR__, __PLLDIVR__) (((__INPUTFREQ__) / (__PLLM__) * (__PLLN__) / \
2135 ((__PLLR__) >> RCC_PLLCFGR_PLLR_Pos )) / ((__PLLDIVR__) >> RCC_DCKCFGR_PLLDIVR_Pos ))
2136 #else
2137 #define __LL_RCC_CALC_PLLCLK_SAI_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLR__) ((__INPUTFREQ__) / (__PLLM__) * (__PLLN__) / \
2138 ((__PLLR__) >> RCC_PLLCFGR_PLLR_Pos ))
2139 #endif /* RCC_DCKCFGR_PLLDIVR */
2140 #endif /* SAI1 */
2141 #endif /* RCC_PLLCFGR_PLLR */
2142
2143 #if defined(RCC_PLLSAI_SUPPORT)
2144 /**
2145 * @brief Helper macro to calculate the PLLSAI frequency used for SAI domain
2146 * @note ex: @ref __LL_RCC_CALC_PLLSAI_SAI_FREQ (HSE_VALUE,@ref LL_RCC_PLLSAI_GetDivider (),
2147 * @ref LL_RCC_PLLSAI_GetN (), @ref LL_RCC_PLLSAI_GetQ (), @ref LL_RCC_PLLSAI_GetDIVQ ());
2148 * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
2149 * @param __PLLM__ This parameter can be one of the following values:
2150 * @arg @ref LL_RCC_PLLSAIM_DIV_2
2151 * @arg @ref LL_RCC_PLLSAIM_DIV_3
2152 * @arg @ref LL_RCC_PLLSAIM_DIV_4
2153 * @arg @ref LL_RCC_PLLSAIM_DIV_5
2154 * @arg @ref LL_RCC_PLLSAIM_DIV_6
2155 * @arg @ref LL_RCC_PLLSAIM_DIV_7
2156 * @arg @ref LL_RCC_PLLSAIM_DIV_8
2157 * @arg @ref LL_RCC_PLLSAIM_DIV_9
2158 * @arg @ref LL_RCC_PLLSAIM_DIV_10
2159 * @arg @ref LL_RCC_PLLSAIM_DIV_11
2160 * @arg @ref LL_RCC_PLLSAIM_DIV_12
2161 * @arg @ref LL_RCC_PLLSAIM_DIV_13
2162 * @arg @ref LL_RCC_PLLSAIM_DIV_14
2163 * @arg @ref LL_RCC_PLLSAIM_DIV_15
2164 * @arg @ref LL_RCC_PLLSAIM_DIV_16
2165 * @arg @ref LL_RCC_PLLSAIM_DIV_17
2166 * @arg @ref LL_RCC_PLLSAIM_DIV_18
2167 * @arg @ref LL_RCC_PLLSAIM_DIV_19
2168 * @arg @ref LL_RCC_PLLSAIM_DIV_20
2169 * @arg @ref LL_RCC_PLLSAIM_DIV_21
2170 * @arg @ref LL_RCC_PLLSAIM_DIV_22
2171 * @arg @ref LL_RCC_PLLSAIM_DIV_23
2172 * @arg @ref LL_RCC_PLLSAIM_DIV_24
2173 * @arg @ref LL_RCC_PLLSAIM_DIV_25
2174 * @arg @ref LL_RCC_PLLSAIM_DIV_26
2175 * @arg @ref LL_RCC_PLLSAIM_DIV_27
2176 * @arg @ref LL_RCC_PLLSAIM_DIV_28
2177 * @arg @ref LL_RCC_PLLSAIM_DIV_29
2178 * @arg @ref LL_RCC_PLLSAIM_DIV_30
2179 * @arg @ref LL_RCC_PLLSAIM_DIV_31
2180 * @arg @ref LL_RCC_PLLSAIM_DIV_32
2181 * @arg @ref LL_RCC_PLLSAIM_DIV_33
2182 * @arg @ref LL_RCC_PLLSAIM_DIV_34
2183 * @arg @ref LL_RCC_PLLSAIM_DIV_35
2184 * @arg @ref LL_RCC_PLLSAIM_DIV_36
2185 * @arg @ref LL_RCC_PLLSAIM_DIV_37
2186 * @arg @ref LL_RCC_PLLSAIM_DIV_38
2187 * @arg @ref LL_RCC_PLLSAIM_DIV_39
2188 * @arg @ref LL_RCC_PLLSAIM_DIV_40
2189 * @arg @ref LL_RCC_PLLSAIM_DIV_41
2190 * @arg @ref LL_RCC_PLLSAIM_DIV_42
2191 * @arg @ref LL_RCC_PLLSAIM_DIV_43
2192 * @arg @ref LL_RCC_PLLSAIM_DIV_44
2193 * @arg @ref LL_RCC_PLLSAIM_DIV_45
2194 * @arg @ref LL_RCC_PLLSAIM_DIV_46
2195 * @arg @ref LL_RCC_PLLSAIM_DIV_47
2196 * @arg @ref LL_RCC_PLLSAIM_DIV_48
2197 * @arg @ref LL_RCC_PLLSAIM_DIV_49
2198 * @arg @ref LL_RCC_PLLSAIM_DIV_50
2199 * @arg @ref LL_RCC_PLLSAIM_DIV_51
2200 * @arg @ref LL_RCC_PLLSAIM_DIV_52
2201 * @arg @ref LL_RCC_PLLSAIM_DIV_53
2202 * @arg @ref LL_RCC_PLLSAIM_DIV_54
2203 * @arg @ref LL_RCC_PLLSAIM_DIV_55
2204 * @arg @ref LL_RCC_PLLSAIM_DIV_56
2205 * @arg @ref LL_RCC_PLLSAIM_DIV_57
2206 * @arg @ref LL_RCC_PLLSAIM_DIV_58
2207 * @arg @ref LL_RCC_PLLSAIM_DIV_59
2208 * @arg @ref LL_RCC_PLLSAIM_DIV_60
2209 * @arg @ref LL_RCC_PLLSAIM_DIV_61
2210 * @arg @ref LL_RCC_PLLSAIM_DIV_62
2211 * @arg @ref LL_RCC_PLLSAIM_DIV_63
2212 * @param __PLLSAIN__ Between 49/50(*) and 432
2213 *
2214 * (*) value not defined in all devices.
2215 * @param __PLLSAIQ__ This parameter can be one of the following values:
2216 * @arg @ref LL_RCC_PLLSAIQ_DIV_2
2217 * @arg @ref LL_RCC_PLLSAIQ_DIV_3
2218 * @arg @ref LL_RCC_PLLSAIQ_DIV_4
2219 * @arg @ref LL_RCC_PLLSAIQ_DIV_5
2220 * @arg @ref LL_RCC_PLLSAIQ_DIV_6
2221 * @arg @ref LL_RCC_PLLSAIQ_DIV_7
2222 * @arg @ref LL_RCC_PLLSAIQ_DIV_8
2223 * @arg @ref LL_RCC_PLLSAIQ_DIV_9
2224 * @arg @ref LL_RCC_PLLSAIQ_DIV_10
2225 * @arg @ref LL_RCC_PLLSAIQ_DIV_11
2226 * @arg @ref LL_RCC_PLLSAIQ_DIV_12
2227 * @arg @ref LL_RCC_PLLSAIQ_DIV_13
2228 * @arg @ref LL_RCC_PLLSAIQ_DIV_14
2229 * @arg @ref LL_RCC_PLLSAIQ_DIV_15
2230 * @param __PLLSAIDIVQ__ This parameter can be one of the following values:
2231 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_1
2232 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_2
2233 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_3
2234 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_4
2235 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_5
2236 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_6
2237 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_7
2238 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_8
2239 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_9
2240 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_10
2241 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_11
2242 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_12
2243 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_13
2244 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_14
2245 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_15
2246 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_16
2247 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_17
2248 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_18
2249 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_19
2250 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_20
2251 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_21
2252 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_22
2253 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_23
2254 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_24
2255 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_25
2256 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_26
2257 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_27
2258 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_28
2259 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_29
2260 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_30
2261 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_31
2262 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_32
2263 * @retval PLLSAI clock frequency (in Hz)
2264 */
2265 #define __LL_RCC_CALC_PLLSAI_SAI_FREQ(__INPUTFREQ__, __PLLM__, __PLLSAIN__, __PLLSAIQ__, __PLLSAIDIVQ__) (((__INPUTFREQ__) / (__PLLM__)) * (__PLLSAIN__) / \
2266 (((__PLLSAIQ__) >> RCC_PLLSAICFGR_PLLSAIQ_Pos) * (((__PLLSAIDIVQ__) >> RCC_DCKCFGR_PLLSAIDIVQ_Pos) + 1U)))
2267
2268 #if defined(RCC_PLLSAICFGR_PLLSAIP)
2269 /**
2270 * @brief Helper macro to calculate the PLLSAI frequency used on 48Mhz domain
2271 * @note ex: @ref __LL_RCC_CALC_PLLSAI_48M_FREQ (HSE_VALUE,@ref LL_RCC_PLLSAI_GetDivider (),
2272 * @ref LL_RCC_PLLSAI_GetN (), @ref LL_RCC_PLLSAI_GetP ());
2273 * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
2274 * @param __PLLM__ This parameter can be one of the following values:
2275 * @arg @ref LL_RCC_PLLSAIM_DIV_2
2276 * @arg @ref LL_RCC_PLLSAIM_DIV_3
2277 * @arg @ref LL_RCC_PLLSAIM_DIV_4
2278 * @arg @ref LL_RCC_PLLSAIM_DIV_5
2279 * @arg @ref LL_RCC_PLLSAIM_DIV_6
2280 * @arg @ref LL_RCC_PLLSAIM_DIV_7
2281 * @arg @ref LL_RCC_PLLSAIM_DIV_8
2282 * @arg @ref LL_RCC_PLLSAIM_DIV_9
2283 * @arg @ref LL_RCC_PLLSAIM_DIV_10
2284 * @arg @ref LL_RCC_PLLSAIM_DIV_11
2285 * @arg @ref LL_RCC_PLLSAIM_DIV_12
2286 * @arg @ref LL_RCC_PLLSAIM_DIV_13
2287 * @arg @ref LL_RCC_PLLSAIM_DIV_14
2288 * @arg @ref LL_RCC_PLLSAIM_DIV_15
2289 * @arg @ref LL_RCC_PLLSAIM_DIV_16
2290 * @arg @ref LL_RCC_PLLSAIM_DIV_17
2291 * @arg @ref LL_RCC_PLLSAIM_DIV_18
2292 * @arg @ref LL_RCC_PLLSAIM_DIV_19
2293 * @arg @ref LL_RCC_PLLSAIM_DIV_20
2294 * @arg @ref LL_RCC_PLLSAIM_DIV_21
2295 * @arg @ref LL_RCC_PLLSAIM_DIV_22
2296 * @arg @ref LL_RCC_PLLSAIM_DIV_23
2297 * @arg @ref LL_RCC_PLLSAIM_DIV_24
2298 * @arg @ref LL_RCC_PLLSAIM_DIV_25
2299 * @arg @ref LL_RCC_PLLSAIM_DIV_26
2300 * @arg @ref LL_RCC_PLLSAIM_DIV_27
2301 * @arg @ref LL_RCC_PLLSAIM_DIV_28
2302 * @arg @ref LL_RCC_PLLSAIM_DIV_29
2303 * @arg @ref LL_RCC_PLLSAIM_DIV_30
2304 * @arg @ref LL_RCC_PLLSAIM_DIV_31
2305 * @arg @ref LL_RCC_PLLSAIM_DIV_32
2306 * @arg @ref LL_RCC_PLLSAIM_DIV_33
2307 * @arg @ref LL_RCC_PLLSAIM_DIV_34
2308 * @arg @ref LL_RCC_PLLSAIM_DIV_35
2309 * @arg @ref LL_RCC_PLLSAIM_DIV_36
2310 * @arg @ref LL_RCC_PLLSAIM_DIV_37
2311 * @arg @ref LL_RCC_PLLSAIM_DIV_38
2312 * @arg @ref LL_RCC_PLLSAIM_DIV_39
2313 * @arg @ref LL_RCC_PLLSAIM_DIV_40
2314 * @arg @ref LL_RCC_PLLSAIM_DIV_41
2315 * @arg @ref LL_RCC_PLLSAIM_DIV_42
2316 * @arg @ref LL_RCC_PLLSAIM_DIV_43
2317 * @arg @ref LL_RCC_PLLSAIM_DIV_44
2318 * @arg @ref LL_RCC_PLLSAIM_DIV_45
2319 * @arg @ref LL_RCC_PLLSAIM_DIV_46
2320 * @arg @ref LL_RCC_PLLSAIM_DIV_47
2321 * @arg @ref LL_RCC_PLLSAIM_DIV_48
2322 * @arg @ref LL_RCC_PLLSAIM_DIV_49
2323 * @arg @ref LL_RCC_PLLSAIM_DIV_50
2324 * @arg @ref LL_RCC_PLLSAIM_DIV_51
2325 * @arg @ref LL_RCC_PLLSAIM_DIV_52
2326 * @arg @ref LL_RCC_PLLSAIM_DIV_53
2327 * @arg @ref LL_RCC_PLLSAIM_DIV_54
2328 * @arg @ref LL_RCC_PLLSAIM_DIV_55
2329 * @arg @ref LL_RCC_PLLSAIM_DIV_56
2330 * @arg @ref LL_RCC_PLLSAIM_DIV_57
2331 * @arg @ref LL_RCC_PLLSAIM_DIV_58
2332 * @arg @ref LL_RCC_PLLSAIM_DIV_59
2333 * @arg @ref LL_RCC_PLLSAIM_DIV_60
2334 * @arg @ref LL_RCC_PLLSAIM_DIV_61
2335 * @arg @ref LL_RCC_PLLSAIM_DIV_62
2336 * @arg @ref LL_RCC_PLLSAIM_DIV_63
2337 * @param __PLLSAIN__ Between 50 and 432
2338 * @param __PLLSAIP__ This parameter can be one of the following values:
2339 * @arg @ref LL_RCC_PLLSAIP_DIV_2
2340 * @arg @ref LL_RCC_PLLSAIP_DIV_4
2341 * @arg @ref LL_RCC_PLLSAIP_DIV_6
2342 * @arg @ref LL_RCC_PLLSAIP_DIV_8
2343 * @retval PLLSAI clock frequency (in Hz)
2344 */
2345 #define __LL_RCC_CALC_PLLSAI_48M_FREQ(__INPUTFREQ__, __PLLM__, __PLLSAIN__, __PLLSAIP__) (((__INPUTFREQ__) / (__PLLM__)) * (__PLLSAIN__) / \
2346 ((((__PLLSAIP__) >> RCC_PLLSAICFGR_PLLSAIP_Pos) + 1U) * 2U))
2347 #endif /* RCC_PLLSAICFGR_PLLSAIP */
2348
2349 #if defined(LTDC)
2350 /**
2351 * @brief Helper macro to calculate the PLLSAI frequency used for LTDC domain
2352 * @note ex: @ref __LL_RCC_CALC_PLLSAI_LTDC_FREQ (HSE_VALUE,@ref LL_RCC_PLLSAI_GetDivider (),
2353 * @ref LL_RCC_PLLSAI_GetN (), @ref LL_RCC_PLLSAI_GetR (), @ref LL_RCC_PLLSAI_GetDIVR ());
2354 * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
2355 * @param __PLLM__ This parameter can be one of the following values:
2356 * @arg @ref LL_RCC_PLLSAIM_DIV_2
2357 * @arg @ref LL_RCC_PLLSAIM_DIV_3
2358 * @arg @ref LL_RCC_PLLSAIM_DIV_4
2359 * @arg @ref LL_RCC_PLLSAIM_DIV_5
2360 * @arg @ref LL_RCC_PLLSAIM_DIV_6
2361 * @arg @ref LL_RCC_PLLSAIM_DIV_7
2362 * @arg @ref LL_RCC_PLLSAIM_DIV_8
2363 * @arg @ref LL_RCC_PLLSAIM_DIV_9
2364 * @arg @ref LL_RCC_PLLSAIM_DIV_10
2365 * @arg @ref LL_RCC_PLLSAIM_DIV_11
2366 * @arg @ref LL_RCC_PLLSAIM_DIV_12
2367 * @arg @ref LL_RCC_PLLSAIM_DIV_13
2368 * @arg @ref LL_RCC_PLLSAIM_DIV_14
2369 * @arg @ref LL_RCC_PLLSAIM_DIV_15
2370 * @arg @ref LL_RCC_PLLSAIM_DIV_16
2371 * @arg @ref LL_RCC_PLLSAIM_DIV_17
2372 * @arg @ref LL_RCC_PLLSAIM_DIV_18
2373 * @arg @ref LL_RCC_PLLSAIM_DIV_19
2374 * @arg @ref LL_RCC_PLLSAIM_DIV_20
2375 * @arg @ref LL_RCC_PLLSAIM_DIV_21
2376 * @arg @ref LL_RCC_PLLSAIM_DIV_22
2377 * @arg @ref LL_RCC_PLLSAIM_DIV_23
2378 * @arg @ref LL_RCC_PLLSAIM_DIV_24
2379 * @arg @ref LL_RCC_PLLSAIM_DIV_25
2380 * @arg @ref LL_RCC_PLLSAIM_DIV_26
2381 * @arg @ref LL_RCC_PLLSAIM_DIV_27
2382 * @arg @ref LL_RCC_PLLSAIM_DIV_28
2383 * @arg @ref LL_RCC_PLLSAIM_DIV_29
2384 * @arg @ref LL_RCC_PLLSAIM_DIV_30
2385 * @arg @ref LL_RCC_PLLSAIM_DIV_31
2386 * @arg @ref LL_RCC_PLLSAIM_DIV_32
2387 * @arg @ref LL_RCC_PLLSAIM_DIV_33
2388 * @arg @ref LL_RCC_PLLSAIM_DIV_34
2389 * @arg @ref LL_RCC_PLLSAIM_DIV_35
2390 * @arg @ref LL_RCC_PLLSAIM_DIV_36
2391 * @arg @ref LL_RCC_PLLSAIM_DIV_37
2392 * @arg @ref LL_RCC_PLLSAIM_DIV_38
2393 * @arg @ref LL_RCC_PLLSAIM_DIV_39
2394 * @arg @ref LL_RCC_PLLSAIM_DIV_40
2395 * @arg @ref LL_RCC_PLLSAIM_DIV_41
2396 * @arg @ref LL_RCC_PLLSAIM_DIV_42
2397 * @arg @ref LL_RCC_PLLSAIM_DIV_43
2398 * @arg @ref LL_RCC_PLLSAIM_DIV_44
2399 * @arg @ref LL_RCC_PLLSAIM_DIV_45
2400 * @arg @ref LL_RCC_PLLSAIM_DIV_46
2401 * @arg @ref LL_RCC_PLLSAIM_DIV_47
2402 * @arg @ref LL_RCC_PLLSAIM_DIV_48
2403 * @arg @ref LL_RCC_PLLSAIM_DIV_49
2404 * @arg @ref LL_RCC_PLLSAIM_DIV_50
2405 * @arg @ref LL_RCC_PLLSAIM_DIV_51
2406 * @arg @ref LL_RCC_PLLSAIM_DIV_52
2407 * @arg @ref LL_RCC_PLLSAIM_DIV_53
2408 * @arg @ref LL_RCC_PLLSAIM_DIV_54
2409 * @arg @ref LL_RCC_PLLSAIM_DIV_55
2410 * @arg @ref LL_RCC_PLLSAIM_DIV_56
2411 * @arg @ref LL_RCC_PLLSAIM_DIV_57
2412 * @arg @ref LL_RCC_PLLSAIM_DIV_58
2413 * @arg @ref LL_RCC_PLLSAIM_DIV_59
2414 * @arg @ref LL_RCC_PLLSAIM_DIV_60
2415 * @arg @ref LL_RCC_PLLSAIM_DIV_61
2416 * @arg @ref LL_RCC_PLLSAIM_DIV_62
2417 * @arg @ref LL_RCC_PLLSAIM_DIV_63
2418 * @param __PLLSAIN__ Between 49/50(*) and 432
2419 *
2420 * (*) value not defined in all devices.
2421 * @param __PLLSAIR__ This parameter can be one of the following values:
2422 * @arg @ref LL_RCC_PLLSAIR_DIV_2
2423 * @arg @ref LL_RCC_PLLSAIR_DIV_3
2424 * @arg @ref LL_RCC_PLLSAIR_DIV_4
2425 * @arg @ref LL_RCC_PLLSAIR_DIV_5
2426 * @arg @ref LL_RCC_PLLSAIR_DIV_6
2427 * @arg @ref LL_RCC_PLLSAIR_DIV_7
2428 * @param __PLLSAIDIVR__ This parameter can be one of the following values:
2429 * @arg @ref LL_RCC_PLLSAIDIVR_DIV_2
2430 * @arg @ref LL_RCC_PLLSAIDIVR_DIV_4
2431 * @arg @ref LL_RCC_PLLSAIDIVR_DIV_8
2432 * @arg @ref LL_RCC_PLLSAIDIVR_DIV_16
2433 * @retval PLLSAI clock frequency (in Hz)
2434 */
2435 #define __LL_RCC_CALC_PLLSAI_LTDC_FREQ(__INPUTFREQ__, __PLLM__, __PLLSAIN__, __PLLSAIR__, __PLLSAIDIVR__) (((__INPUTFREQ__) / (__PLLM__)) * (__PLLSAIN__) / \
2436 (((__PLLSAIR__) >> RCC_PLLSAICFGR_PLLSAIR_Pos) * (aRCC_PLLSAIDIVRPrescTable[(__PLLSAIDIVR__) >> RCC_DCKCFGR_PLLSAIDIVR_Pos])))
2437 #endif /* LTDC */
2438 #endif /* RCC_PLLSAI_SUPPORT */
2439
2440 #if defined(RCC_PLLI2S_SUPPORT)
2441 #if defined(RCC_DCKCFGR_PLLI2SDIVQ) || defined(RCC_DCKCFGR_PLLI2SDIVR)
2442 /**
2443 * @brief Helper macro to calculate the PLLI2S frequency used for SAI domain
2444 * @note ex: @ref __LL_RCC_CALC_PLLI2S_SAI_FREQ (HSE_VALUE,@ref LL_RCC_PLLI2S_GetDivider (),
2445 * @ref LL_RCC_PLLI2S_GetN (), @ref LL_RCC_PLLI2S_GetQ (), @ref LL_RCC_PLLI2S_GetDIVQ ());
2446 * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
2447 * @param __PLLM__ This parameter can be one of the following values:
2448 * @arg @ref LL_RCC_PLLI2SM_DIV_2
2449 * @arg @ref LL_RCC_PLLI2SM_DIV_3
2450 * @arg @ref LL_RCC_PLLI2SM_DIV_4
2451 * @arg @ref LL_RCC_PLLI2SM_DIV_5
2452 * @arg @ref LL_RCC_PLLI2SM_DIV_6
2453 * @arg @ref LL_RCC_PLLI2SM_DIV_7
2454 * @arg @ref LL_RCC_PLLI2SM_DIV_8
2455 * @arg @ref LL_RCC_PLLI2SM_DIV_9
2456 * @arg @ref LL_RCC_PLLI2SM_DIV_10
2457 * @arg @ref LL_RCC_PLLI2SM_DIV_11
2458 * @arg @ref LL_RCC_PLLI2SM_DIV_12
2459 * @arg @ref LL_RCC_PLLI2SM_DIV_13
2460 * @arg @ref LL_RCC_PLLI2SM_DIV_14
2461 * @arg @ref LL_RCC_PLLI2SM_DIV_15
2462 * @arg @ref LL_RCC_PLLI2SM_DIV_16
2463 * @arg @ref LL_RCC_PLLI2SM_DIV_17
2464 * @arg @ref LL_RCC_PLLI2SM_DIV_18
2465 * @arg @ref LL_RCC_PLLI2SM_DIV_19
2466 * @arg @ref LL_RCC_PLLI2SM_DIV_20
2467 * @arg @ref LL_RCC_PLLI2SM_DIV_21
2468 * @arg @ref LL_RCC_PLLI2SM_DIV_22
2469 * @arg @ref LL_RCC_PLLI2SM_DIV_23
2470 * @arg @ref LL_RCC_PLLI2SM_DIV_24
2471 * @arg @ref LL_RCC_PLLI2SM_DIV_25
2472 * @arg @ref LL_RCC_PLLI2SM_DIV_26
2473 * @arg @ref LL_RCC_PLLI2SM_DIV_27
2474 * @arg @ref LL_RCC_PLLI2SM_DIV_28
2475 * @arg @ref LL_RCC_PLLI2SM_DIV_29
2476 * @arg @ref LL_RCC_PLLI2SM_DIV_30
2477 * @arg @ref LL_RCC_PLLI2SM_DIV_31
2478 * @arg @ref LL_RCC_PLLI2SM_DIV_32
2479 * @arg @ref LL_RCC_PLLI2SM_DIV_33
2480 * @arg @ref LL_RCC_PLLI2SM_DIV_34
2481 * @arg @ref LL_RCC_PLLI2SM_DIV_35
2482 * @arg @ref LL_RCC_PLLI2SM_DIV_36
2483 * @arg @ref LL_RCC_PLLI2SM_DIV_37
2484 * @arg @ref LL_RCC_PLLI2SM_DIV_38
2485 * @arg @ref LL_RCC_PLLI2SM_DIV_39
2486 * @arg @ref LL_RCC_PLLI2SM_DIV_40
2487 * @arg @ref LL_RCC_PLLI2SM_DIV_41
2488 * @arg @ref LL_RCC_PLLI2SM_DIV_42
2489 * @arg @ref LL_RCC_PLLI2SM_DIV_43
2490 * @arg @ref LL_RCC_PLLI2SM_DIV_44
2491 * @arg @ref LL_RCC_PLLI2SM_DIV_45
2492 * @arg @ref LL_RCC_PLLI2SM_DIV_46
2493 * @arg @ref LL_RCC_PLLI2SM_DIV_47
2494 * @arg @ref LL_RCC_PLLI2SM_DIV_48
2495 * @arg @ref LL_RCC_PLLI2SM_DIV_49
2496 * @arg @ref LL_RCC_PLLI2SM_DIV_50
2497 * @arg @ref LL_RCC_PLLI2SM_DIV_51
2498 * @arg @ref LL_RCC_PLLI2SM_DIV_52
2499 * @arg @ref LL_RCC_PLLI2SM_DIV_53
2500 * @arg @ref LL_RCC_PLLI2SM_DIV_54
2501 * @arg @ref LL_RCC_PLLI2SM_DIV_55
2502 * @arg @ref LL_RCC_PLLI2SM_DIV_56
2503 * @arg @ref LL_RCC_PLLI2SM_DIV_57
2504 * @arg @ref LL_RCC_PLLI2SM_DIV_58
2505 * @arg @ref LL_RCC_PLLI2SM_DIV_59
2506 * @arg @ref LL_RCC_PLLI2SM_DIV_60
2507 * @arg @ref LL_RCC_PLLI2SM_DIV_61
2508 * @arg @ref LL_RCC_PLLI2SM_DIV_62
2509 * @arg @ref LL_RCC_PLLI2SM_DIV_63
2510 * @param __PLLI2SN__ Between 50/192(*) and 432
2511 *
2512 * (*) value not defined in all devices.
2513 * @param __PLLI2SQ_R__ This parameter can be one of the following values:
2514 * @arg @ref LL_RCC_PLLI2SQ_DIV_2 (*)
2515 * @arg @ref LL_RCC_PLLI2SQ_DIV_3 (*)
2516 * @arg @ref LL_RCC_PLLI2SQ_DIV_4 (*)
2517 * @arg @ref LL_RCC_PLLI2SQ_DIV_5 (*)
2518 * @arg @ref LL_RCC_PLLI2SQ_DIV_6 (*)
2519 * @arg @ref LL_RCC_PLLI2SQ_DIV_7 (*)
2520 * @arg @ref LL_RCC_PLLI2SQ_DIV_8 (*)
2521 * @arg @ref LL_RCC_PLLI2SQ_DIV_9 (*)
2522 * @arg @ref LL_RCC_PLLI2SQ_DIV_10 (*)
2523 * @arg @ref LL_RCC_PLLI2SQ_DIV_11 (*)
2524 * @arg @ref LL_RCC_PLLI2SQ_DIV_12 (*)
2525 * @arg @ref LL_RCC_PLLI2SQ_DIV_13 (*)
2526 * @arg @ref LL_RCC_PLLI2SQ_DIV_14 (*)
2527 * @arg @ref LL_RCC_PLLI2SQ_DIV_15 (*)
2528 * @arg @ref LL_RCC_PLLI2SR_DIV_2 (*)
2529 * @arg @ref LL_RCC_PLLI2SR_DIV_3 (*)
2530 * @arg @ref LL_RCC_PLLI2SR_DIV_4 (*)
2531 * @arg @ref LL_RCC_PLLI2SR_DIV_5 (*)
2532 * @arg @ref LL_RCC_PLLI2SR_DIV_6 (*)
2533 * @arg @ref LL_RCC_PLLI2SR_DIV_7 (*)
2534 *
2535 * (*) value not defined in all devices.
2536 * @param __PLLI2SDIVQ_R__ This parameter can be one of the following values:
2537 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_1 (*)
2538 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_2 (*)
2539 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_3 (*)
2540 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_4 (*)
2541 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_5 (*)
2542 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_6 (*)
2543 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_7 (*)
2544 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_8 (*)
2545 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_9 (*)
2546 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_10 (*)
2547 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_11 (*)
2548 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_12 (*)
2549 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_13 (*)
2550 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_14 (*)
2551 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_15 (*)
2552 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_16 (*)
2553 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_17 (*)
2554 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_18 (*)
2555 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_19 (*)
2556 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_20 (*)
2557 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_21 (*)
2558 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_22 (*)
2559 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_23 (*)
2560 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_24 (*)
2561 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_25 (*)
2562 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_26 (*)
2563 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_27 (*)
2564 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_28 (*)
2565 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_29 (*)
2566 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_30 (*)
2567 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_31 (*)
2568 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_32 (*)
2569 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_1 (*)
2570 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_2 (*)
2571 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_3 (*)
2572 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_4 (*)
2573 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_5 (*)
2574 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_6 (*)
2575 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_7 (*)
2576 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_8 (*)
2577 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_9 (*)
2578 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_10 (*)
2579 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_11 (*)
2580 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_12 (*)
2581 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_13 (*)
2582 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_14 (*)
2583 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_15 (*)
2584 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_16 (*)
2585 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_17 (*)
2586 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_18 (*)
2587 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_19 (*)
2588 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_20 (*)
2589 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_21 (*)
2590 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_22 (*)
2591 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_23 (*)
2592 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_24 (*)
2593 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_25 (*)
2594 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_26 (*)
2595 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_27 (*)
2596 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_28 (*)
2597 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_29 (*)
2598 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_30 (*)
2599 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_31 (*)
2600 *
2601 * (*) value not defined in all devices.
2602 * @retval PLLI2S clock frequency (in Hz)
2603 */
2604 #if defined(RCC_DCKCFGR_PLLI2SDIVQ)
2605 #define __LL_RCC_CALC_PLLI2S_SAI_FREQ(__INPUTFREQ__, __PLLM__, __PLLI2SN__, __PLLI2SQ_R__, __PLLI2SDIVQ_R__) (((__INPUTFREQ__) / (__PLLM__)) * (__PLLI2SN__) / \
2606 (((__PLLI2SQ_R__) >> RCC_PLLI2SCFGR_PLLI2SQ_Pos) * (((__PLLI2SDIVQ_R__) >> RCC_DCKCFGR_PLLI2SDIVQ_Pos) + 1U)))
2607 #else
2608 #define __LL_RCC_CALC_PLLI2S_SAI_FREQ(__INPUTFREQ__, __PLLM__, __PLLI2SN__, __PLLI2SQ_R__, __PLLI2SDIVQ_R__) (((__INPUTFREQ__) / (__PLLM__)) * (__PLLI2SN__) / \
2609 (((__PLLI2SQ_R__) >> RCC_PLLI2SCFGR_PLLI2SR_Pos) * ((__PLLI2SDIVQ_R__) >> RCC_DCKCFGR_PLLI2SDIVR_Pos)))
2610
2611 #endif /* RCC_DCKCFGR_PLLI2SDIVQ */
2612 #endif /* RCC_DCKCFGR_PLLI2SDIVQ || RCC_DCKCFGR_PLLI2SDIVR */
2613
2614 #if defined(SPDIFRX)
2615 /**
2616 * @brief Helper macro to calculate the PLLI2S frequency used on SPDIFRX domain
2617 * @note ex: @ref __LL_RCC_CALC_PLLI2S_SPDIFRX_FREQ (HSE_VALUE,@ref LL_RCC_PLLI2S_GetDivider (),
2618 * @ref LL_RCC_PLLI2S_GetN (), @ref LL_RCC_PLLI2S_GetP ());
2619 * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
2620 * @param __PLLM__ This parameter can be one of the following values:
2621 * @arg @ref LL_RCC_PLLI2SM_DIV_2
2622 * @arg @ref LL_RCC_PLLI2SM_DIV_3
2623 * @arg @ref LL_RCC_PLLI2SM_DIV_4
2624 * @arg @ref LL_RCC_PLLI2SM_DIV_5
2625 * @arg @ref LL_RCC_PLLI2SM_DIV_6
2626 * @arg @ref LL_RCC_PLLI2SM_DIV_7
2627 * @arg @ref LL_RCC_PLLI2SM_DIV_8
2628 * @arg @ref LL_RCC_PLLI2SM_DIV_9
2629 * @arg @ref LL_RCC_PLLI2SM_DIV_10
2630 * @arg @ref LL_RCC_PLLI2SM_DIV_11
2631 * @arg @ref LL_RCC_PLLI2SM_DIV_12
2632 * @arg @ref LL_RCC_PLLI2SM_DIV_13
2633 * @arg @ref LL_RCC_PLLI2SM_DIV_14
2634 * @arg @ref LL_RCC_PLLI2SM_DIV_15
2635 * @arg @ref LL_RCC_PLLI2SM_DIV_16
2636 * @arg @ref LL_RCC_PLLI2SM_DIV_17
2637 * @arg @ref LL_RCC_PLLI2SM_DIV_18
2638 * @arg @ref LL_RCC_PLLI2SM_DIV_19
2639 * @arg @ref LL_RCC_PLLI2SM_DIV_20
2640 * @arg @ref LL_RCC_PLLI2SM_DIV_21
2641 * @arg @ref LL_RCC_PLLI2SM_DIV_22
2642 * @arg @ref LL_RCC_PLLI2SM_DIV_23
2643 * @arg @ref LL_RCC_PLLI2SM_DIV_24
2644 * @arg @ref LL_RCC_PLLI2SM_DIV_25
2645 * @arg @ref LL_RCC_PLLI2SM_DIV_26
2646 * @arg @ref LL_RCC_PLLI2SM_DIV_27
2647 * @arg @ref LL_RCC_PLLI2SM_DIV_28
2648 * @arg @ref LL_RCC_PLLI2SM_DIV_29
2649 * @arg @ref LL_RCC_PLLI2SM_DIV_30
2650 * @arg @ref LL_RCC_PLLI2SM_DIV_31
2651 * @arg @ref LL_RCC_PLLI2SM_DIV_32
2652 * @arg @ref LL_RCC_PLLI2SM_DIV_33
2653 * @arg @ref LL_RCC_PLLI2SM_DIV_34
2654 * @arg @ref LL_RCC_PLLI2SM_DIV_35
2655 * @arg @ref LL_RCC_PLLI2SM_DIV_36
2656 * @arg @ref LL_RCC_PLLI2SM_DIV_37
2657 * @arg @ref LL_RCC_PLLI2SM_DIV_38
2658 * @arg @ref LL_RCC_PLLI2SM_DIV_39
2659 * @arg @ref LL_RCC_PLLI2SM_DIV_40
2660 * @arg @ref LL_RCC_PLLI2SM_DIV_41
2661 * @arg @ref LL_RCC_PLLI2SM_DIV_42
2662 * @arg @ref LL_RCC_PLLI2SM_DIV_43
2663 * @arg @ref LL_RCC_PLLI2SM_DIV_44
2664 * @arg @ref LL_RCC_PLLI2SM_DIV_45
2665 * @arg @ref LL_RCC_PLLI2SM_DIV_46
2666 * @arg @ref LL_RCC_PLLI2SM_DIV_47
2667 * @arg @ref LL_RCC_PLLI2SM_DIV_48
2668 * @arg @ref LL_RCC_PLLI2SM_DIV_49
2669 * @arg @ref LL_RCC_PLLI2SM_DIV_50
2670 * @arg @ref LL_RCC_PLLI2SM_DIV_51
2671 * @arg @ref LL_RCC_PLLI2SM_DIV_52
2672 * @arg @ref LL_RCC_PLLI2SM_DIV_53
2673 * @arg @ref LL_RCC_PLLI2SM_DIV_54
2674 * @arg @ref LL_RCC_PLLI2SM_DIV_55
2675 * @arg @ref LL_RCC_PLLI2SM_DIV_56
2676 * @arg @ref LL_RCC_PLLI2SM_DIV_57
2677 * @arg @ref LL_RCC_PLLI2SM_DIV_58
2678 * @arg @ref LL_RCC_PLLI2SM_DIV_59
2679 * @arg @ref LL_RCC_PLLI2SM_DIV_60
2680 * @arg @ref LL_RCC_PLLI2SM_DIV_61
2681 * @arg @ref LL_RCC_PLLI2SM_DIV_62
2682 * @arg @ref LL_RCC_PLLI2SM_DIV_63
2683 * @param __PLLI2SN__ Between 50 and 432
2684 * @param __PLLI2SP__ This parameter can be one of the following values:
2685 * @arg @ref LL_RCC_PLLI2SP_DIV_2
2686 * @arg @ref LL_RCC_PLLI2SP_DIV_4
2687 * @arg @ref LL_RCC_PLLI2SP_DIV_6
2688 * @arg @ref LL_RCC_PLLI2SP_DIV_8
2689 * @retval PLLI2S clock frequency (in Hz)
2690 */
2691 #define __LL_RCC_CALC_PLLI2S_SPDIFRX_FREQ(__INPUTFREQ__, __PLLM__, __PLLI2SN__, __PLLI2SP__) (((__INPUTFREQ__) / (__PLLM__)) * (__PLLI2SN__) / \
2692 ((((__PLLI2SP__) >> RCC_PLLI2SCFGR_PLLI2SP_Pos) + 1U) * 2U))
2693
2694 #endif /* SPDIFRX */
2695
2696 /**
2697 * @brief Helper macro to calculate the PLLI2S frequency used for I2S domain
2698 * @note ex: @ref __LL_RCC_CALC_PLLI2S_I2S_FREQ (HSE_VALUE,@ref LL_RCC_PLLI2S_GetDivider (),
2699 * @ref LL_RCC_PLLI2S_GetN (), @ref LL_RCC_PLLI2S_GetR ());
2700 * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
2701 * @param __PLLM__ This parameter can be one of the following values:
2702 * @arg @ref LL_RCC_PLLI2SM_DIV_2
2703 * @arg @ref LL_RCC_PLLI2SM_DIV_3
2704 * @arg @ref LL_RCC_PLLI2SM_DIV_4
2705 * @arg @ref LL_RCC_PLLI2SM_DIV_5
2706 * @arg @ref LL_RCC_PLLI2SM_DIV_6
2707 * @arg @ref LL_RCC_PLLI2SM_DIV_7
2708 * @arg @ref LL_RCC_PLLI2SM_DIV_8
2709 * @arg @ref LL_RCC_PLLI2SM_DIV_9
2710 * @arg @ref LL_RCC_PLLI2SM_DIV_10
2711 * @arg @ref LL_RCC_PLLI2SM_DIV_11
2712 * @arg @ref LL_RCC_PLLI2SM_DIV_12
2713 * @arg @ref LL_RCC_PLLI2SM_DIV_13
2714 * @arg @ref LL_RCC_PLLI2SM_DIV_14
2715 * @arg @ref LL_RCC_PLLI2SM_DIV_15
2716 * @arg @ref LL_RCC_PLLI2SM_DIV_16
2717 * @arg @ref LL_RCC_PLLI2SM_DIV_17
2718 * @arg @ref LL_RCC_PLLI2SM_DIV_18
2719 * @arg @ref LL_RCC_PLLI2SM_DIV_19
2720 * @arg @ref LL_RCC_PLLI2SM_DIV_20
2721 * @arg @ref LL_RCC_PLLI2SM_DIV_21
2722 * @arg @ref LL_RCC_PLLI2SM_DIV_22
2723 * @arg @ref LL_RCC_PLLI2SM_DIV_23
2724 * @arg @ref LL_RCC_PLLI2SM_DIV_24
2725 * @arg @ref LL_RCC_PLLI2SM_DIV_25
2726 * @arg @ref LL_RCC_PLLI2SM_DIV_26
2727 * @arg @ref LL_RCC_PLLI2SM_DIV_27
2728 * @arg @ref LL_RCC_PLLI2SM_DIV_28
2729 * @arg @ref LL_RCC_PLLI2SM_DIV_29
2730 * @arg @ref LL_RCC_PLLI2SM_DIV_30
2731 * @arg @ref LL_RCC_PLLI2SM_DIV_31
2732 * @arg @ref LL_RCC_PLLI2SM_DIV_32
2733 * @arg @ref LL_RCC_PLLI2SM_DIV_33
2734 * @arg @ref LL_RCC_PLLI2SM_DIV_34
2735 * @arg @ref LL_RCC_PLLI2SM_DIV_35
2736 * @arg @ref LL_RCC_PLLI2SM_DIV_36
2737 * @arg @ref LL_RCC_PLLI2SM_DIV_37
2738 * @arg @ref LL_RCC_PLLI2SM_DIV_38
2739 * @arg @ref LL_RCC_PLLI2SM_DIV_39
2740 * @arg @ref LL_RCC_PLLI2SM_DIV_40
2741 * @arg @ref LL_RCC_PLLI2SM_DIV_41
2742 * @arg @ref LL_RCC_PLLI2SM_DIV_42
2743 * @arg @ref LL_RCC_PLLI2SM_DIV_43
2744 * @arg @ref LL_RCC_PLLI2SM_DIV_44
2745 * @arg @ref LL_RCC_PLLI2SM_DIV_45
2746 * @arg @ref LL_RCC_PLLI2SM_DIV_46
2747 * @arg @ref LL_RCC_PLLI2SM_DIV_47
2748 * @arg @ref LL_RCC_PLLI2SM_DIV_48
2749 * @arg @ref LL_RCC_PLLI2SM_DIV_49
2750 * @arg @ref LL_RCC_PLLI2SM_DIV_50
2751 * @arg @ref LL_RCC_PLLI2SM_DIV_51
2752 * @arg @ref LL_RCC_PLLI2SM_DIV_52
2753 * @arg @ref LL_RCC_PLLI2SM_DIV_53
2754 * @arg @ref LL_RCC_PLLI2SM_DIV_54
2755 * @arg @ref LL_RCC_PLLI2SM_DIV_55
2756 * @arg @ref LL_RCC_PLLI2SM_DIV_56
2757 * @arg @ref LL_RCC_PLLI2SM_DIV_57
2758 * @arg @ref LL_RCC_PLLI2SM_DIV_58
2759 * @arg @ref LL_RCC_PLLI2SM_DIV_59
2760 * @arg @ref LL_RCC_PLLI2SM_DIV_60
2761 * @arg @ref LL_RCC_PLLI2SM_DIV_61
2762 * @arg @ref LL_RCC_PLLI2SM_DIV_62
2763 * @arg @ref LL_RCC_PLLI2SM_DIV_63
2764 * @param __PLLI2SN__ Between 50/192(*) and 432
2765 *
2766 * (*) value not defined in all devices.
2767 * @param __PLLI2SR__ This parameter can be one of the following values:
2768 * @arg @ref LL_RCC_PLLI2SR_DIV_2
2769 * @arg @ref LL_RCC_PLLI2SR_DIV_3
2770 * @arg @ref LL_RCC_PLLI2SR_DIV_4
2771 * @arg @ref LL_RCC_PLLI2SR_DIV_5
2772 * @arg @ref LL_RCC_PLLI2SR_DIV_6
2773 * @arg @ref LL_RCC_PLLI2SR_DIV_7
2774 * @retval PLLI2S clock frequency (in Hz)
2775 */
2776 #define __LL_RCC_CALC_PLLI2S_I2S_FREQ(__INPUTFREQ__, __PLLM__, __PLLI2SN__, __PLLI2SR__) (((__INPUTFREQ__) / (__PLLM__)) * (__PLLI2SN__) / \
2777 ((__PLLI2SR__) >> RCC_PLLI2SCFGR_PLLI2SR_Pos))
2778
2779 #if defined(RCC_PLLI2SCFGR_PLLI2SQ) && !defined(RCC_DCKCFGR_PLLI2SDIVQ)
2780 /**
2781 * @brief Helper macro to calculate the PLLI2S frequency used for 48Mhz domain
2782 * @note ex: @ref __LL_RCC_CALC_PLLI2S_48M_FREQ (HSE_VALUE,@ref LL_RCC_PLLI2S_GetDivider (),
2783 * @ref LL_RCC_PLLI2S_GetN (), @ref LL_RCC_PLLI2S_GetQ ());
2784 * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
2785 * @param __PLLM__ This parameter can be one of the following values:
2786 * @arg @ref LL_RCC_PLLI2SM_DIV_2
2787 * @arg @ref LL_RCC_PLLI2SM_DIV_3
2788 * @arg @ref LL_RCC_PLLI2SM_DIV_4
2789 * @arg @ref LL_RCC_PLLI2SM_DIV_5
2790 * @arg @ref LL_RCC_PLLI2SM_DIV_6
2791 * @arg @ref LL_RCC_PLLI2SM_DIV_7
2792 * @arg @ref LL_RCC_PLLI2SM_DIV_8
2793 * @arg @ref LL_RCC_PLLI2SM_DIV_9
2794 * @arg @ref LL_RCC_PLLI2SM_DIV_10
2795 * @arg @ref LL_RCC_PLLI2SM_DIV_11
2796 * @arg @ref LL_RCC_PLLI2SM_DIV_12
2797 * @arg @ref LL_RCC_PLLI2SM_DIV_13
2798 * @arg @ref LL_RCC_PLLI2SM_DIV_14
2799 * @arg @ref LL_RCC_PLLI2SM_DIV_15
2800 * @arg @ref LL_RCC_PLLI2SM_DIV_16
2801 * @arg @ref LL_RCC_PLLI2SM_DIV_17
2802 * @arg @ref LL_RCC_PLLI2SM_DIV_18
2803 * @arg @ref LL_RCC_PLLI2SM_DIV_19
2804 * @arg @ref LL_RCC_PLLI2SM_DIV_20
2805 * @arg @ref LL_RCC_PLLI2SM_DIV_21
2806 * @arg @ref LL_RCC_PLLI2SM_DIV_22
2807 * @arg @ref LL_RCC_PLLI2SM_DIV_23
2808 * @arg @ref LL_RCC_PLLI2SM_DIV_24
2809 * @arg @ref LL_RCC_PLLI2SM_DIV_25
2810 * @arg @ref LL_RCC_PLLI2SM_DIV_26
2811 * @arg @ref LL_RCC_PLLI2SM_DIV_27
2812 * @arg @ref LL_RCC_PLLI2SM_DIV_28
2813 * @arg @ref LL_RCC_PLLI2SM_DIV_29
2814 * @arg @ref LL_RCC_PLLI2SM_DIV_30
2815 * @arg @ref LL_RCC_PLLI2SM_DIV_31
2816 * @arg @ref LL_RCC_PLLI2SM_DIV_32
2817 * @arg @ref LL_RCC_PLLI2SM_DIV_33
2818 * @arg @ref LL_RCC_PLLI2SM_DIV_34
2819 * @arg @ref LL_RCC_PLLI2SM_DIV_35
2820 * @arg @ref LL_RCC_PLLI2SM_DIV_36
2821 * @arg @ref LL_RCC_PLLI2SM_DIV_37
2822 * @arg @ref LL_RCC_PLLI2SM_DIV_38
2823 * @arg @ref LL_RCC_PLLI2SM_DIV_39
2824 * @arg @ref LL_RCC_PLLI2SM_DIV_40
2825 * @arg @ref LL_RCC_PLLI2SM_DIV_41
2826 * @arg @ref LL_RCC_PLLI2SM_DIV_42
2827 * @arg @ref LL_RCC_PLLI2SM_DIV_43
2828 * @arg @ref LL_RCC_PLLI2SM_DIV_44
2829 * @arg @ref LL_RCC_PLLI2SM_DIV_45
2830 * @arg @ref LL_RCC_PLLI2SM_DIV_46
2831 * @arg @ref LL_RCC_PLLI2SM_DIV_47
2832 * @arg @ref LL_RCC_PLLI2SM_DIV_48
2833 * @arg @ref LL_RCC_PLLI2SM_DIV_49
2834 * @arg @ref LL_RCC_PLLI2SM_DIV_50
2835 * @arg @ref LL_RCC_PLLI2SM_DIV_51
2836 * @arg @ref LL_RCC_PLLI2SM_DIV_52
2837 * @arg @ref LL_RCC_PLLI2SM_DIV_53
2838 * @arg @ref LL_RCC_PLLI2SM_DIV_54
2839 * @arg @ref LL_RCC_PLLI2SM_DIV_55
2840 * @arg @ref LL_RCC_PLLI2SM_DIV_56
2841 * @arg @ref LL_RCC_PLLI2SM_DIV_57
2842 * @arg @ref LL_RCC_PLLI2SM_DIV_58
2843 * @arg @ref LL_RCC_PLLI2SM_DIV_59
2844 * @arg @ref LL_RCC_PLLI2SM_DIV_60
2845 * @arg @ref LL_RCC_PLLI2SM_DIV_61
2846 * @arg @ref LL_RCC_PLLI2SM_DIV_62
2847 * @arg @ref LL_RCC_PLLI2SM_DIV_63
2848 * @param __PLLI2SN__ Between 50 and 432
2849 * @param __PLLI2SQ__ This parameter can be one of the following values:
2850 * @arg @ref LL_RCC_PLLI2SQ_DIV_2
2851 * @arg @ref LL_RCC_PLLI2SQ_DIV_3
2852 * @arg @ref LL_RCC_PLLI2SQ_DIV_4
2853 * @arg @ref LL_RCC_PLLI2SQ_DIV_5
2854 * @arg @ref LL_RCC_PLLI2SQ_DIV_6
2855 * @arg @ref LL_RCC_PLLI2SQ_DIV_7
2856 * @arg @ref LL_RCC_PLLI2SQ_DIV_8
2857 * @arg @ref LL_RCC_PLLI2SQ_DIV_9
2858 * @arg @ref LL_RCC_PLLI2SQ_DIV_10
2859 * @arg @ref LL_RCC_PLLI2SQ_DIV_11
2860 * @arg @ref LL_RCC_PLLI2SQ_DIV_12
2861 * @arg @ref LL_RCC_PLLI2SQ_DIV_13
2862 * @arg @ref LL_RCC_PLLI2SQ_DIV_14
2863 * @arg @ref LL_RCC_PLLI2SQ_DIV_15
2864 * @retval PLLI2S clock frequency (in Hz)
2865 */
2866 #define __LL_RCC_CALC_PLLI2S_48M_FREQ(__INPUTFREQ__, __PLLM__, __PLLI2SN__, __PLLI2SQ__) (((__INPUTFREQ__) / (__PLLM__)) * (__PLLI2SN__) / \
2867 ((__PLLI2SQ__) >> RCC_PLLI2SCFGR_PLLI2SQ_Pos))
2868
2869 #endif /* RCC_PLLI2SCFGR_PLLI2SQ && !RCC_DCKCFGR_PLLI2SDIVQ */
2870 #endif /* RCC_PLLI2S_SUPPORT */
2871
2872 /**
2873 * @brief Helper macro to calculate the HCLK frequency
2874 * @param __SYSCLKFREQ__ SYSCLK frequency (based on HSE/HSI/PLLCLK)
2875 * @param __AHBPRESCALER__ This parameter can be one of the following values:
2876 * @arg @ref LL_RCC_SYSCLK_DIV_1
2877 * @arg @ref LL_RCC_SYSCLK_DIV_2
2878 * @arg @ref LL_RCC_SYSCLK_DIV_4
2879 * @arg @ref LL_RCC_SYSCLK_DIV_8
2880 * @arg @ref LL_RCC_SYSCLK_DIV_16
2881 * @arg @ref LL_RCC_SYSCLK_DIV_64
2882 * @arg @ref LL_RCC_SYSCLK_DIV_128
2883 * @arg @ref LL_RCC_SYSCLK_DIV_256
2884 * @arg @ref LL_RCC_SYSCLK_DIV_512
2885 * @retval HCLK clock frequency (in Hz)
2886 */
2887 #define __LL_RCC_CALC_HCLK_FREQ(__SYSCLKFREQ__, __AHBPRESCALER__) ((__SYSCLKFREQ__) >> AHBPrescTable[((__AHBPRESCALER__) & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos])
2888
2889 /**
2890 * @brief Helper macro to calculate the PCLK1 frequency (ABP1)
2891 * @param __HCLKFREQ__ HCLK frequency
2892 * @param __APB1PRESCALER__ This parameter can be one of the following values:
2893 * @arg @ref LL_RCC_APB1_DIV_1
2894 * @arg @ref LL_RCC_APB1_DIV_2
2895 * @arg @ref LL_RCC_APB1_DIV_4
2896 * @arg @ref LL_RCC_APB1_DIV_8
2897 * @arg @ref LL_RCC_APB1_DIV_16
2898 * @retval PCLK1 clock frequency (in Hz)
2899 */
2900 #define __LL_RCC_CALC_PCLK1_FREQ(__HCLKFREQ__, __APB1PRESCALER__) ((__HCLKFREQ__) >> APBPrescTable[(__APB1PRESCALER__) >> RCC_CFGR_PPRE1_Pos])
2901
2902 /**
2903 * @brief Helper macro to calculate the PCLK2 frequency (ABP2)
2904 * @param __HCLKFREQ__ HCLK frequency
2905 * @param __APB2PRESCALER__ This parameter can be one of the following values:
2906 * @arg @ref LL_RCC_APB2_DIV_1
2907 * @arg @ref LL_RCC_APB2_DIV_2
2908 * @arg @ref LL_RCC_APB2_DIV_4
2909 * @arg @ref LL_RCC_APB2_DIV_8
2910 * @arg @ref LL_RCC_APB2_DIV_16
2911 * @retval PCLK2 clock frequency (in Hz)
2912 */
2913 #define __LL_RCC_CALC_PCLK2_FREQ(__HCLKFREQ__, __APB2PRESCALER__) ((__HCLKFREQ__) >> APBPrescTable[(__APB2PRESCALER__) >> RCC_CFGR_PPRE2_Pos])
2914
2915 /**
2916 * @}
2917 */
2918
2919 /**
2920 * @}
2921 */
2922
2923 /* Exported functions --------------------------------------------------------*/
2924 /** @defgroup RCC_LL_Exported_Functions RCC Exported Functions
2925 * @{
2926 */
2927
2928 /** @defgroup RCC_LL_EF_HSE HSE
2929 * @{
2930 */
2931
2932 /**
2933 * @brief Enable the Clock Security System.
2934 * @rmtoll CR CSSON LL_RCC_HSE_EnableCSS
2935 * @retval None
2936 */
2937 __STATIC_INLINE void LL_RCC_HSE_EnableCSS(void)
2938 {
2939 SET_BIT(RCC->CR, RCC_CR_CSSON);
2940 }
2941
2942 /**
2943 * @brief Enable HSE external oscillator (HSE Bypass)
2944 * @rmtoll CR HSEBYP LL_RCC_HSE_EnableBypass
2945 * @retval None
2946 */
2947 __STATIC_INLINE void LL_RCC_HSE_EnableBypass(void)
2948 {
2949 SET_BIT(RCC->CR, RCC_CR_HSEBYP);
2950 }
2951
2952 /**
2953 * @brief Disable HSE external oscillator (HSE Bypass)
2954 * @rmtoll CR HSEBYP LL_RCC_HSE_DisableBypass
2955 * @retval None
2956 */
2957 __STATIC_INLINE void LL_RCC_HSE_DisableBypass(void)
2958 {
2959 CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);
2960 }
2961
2962 /**
2963 * @brief Enable HSE crystal oscillator (HSE ON)
2964 * @rmtoll CR HSEON LL_RCC_HSE_Enable
2965 * @retval None
2966 */
2967 __STATIC_INLINE void LL_RCC_HSE_Enable(void)
2968 {
2969 SET_BIT(RCC->CR, RCC_CR_HSEON);
2970 }
2971
2972 /**
2973 * @brief Disable HSE crystal oscillator (HSE ON)
2974 * @rmtoll CR HSEON LL_RCC_HSE_Disable
2975 * @retval None
2976 */
2977 __STATIC_INLINE void LL_RCC_HSE_Disable(void)
2978 {
2979 CLEAR_BIT(RCC->CR, RCC_CR_HSEON);
2980 }
2981
2982 /**
2983 * @brief Check if HSE oscillator Ready
2984 * @rmtoll CR HSERDY LL_RCC_HSE_IsReady
2985 * @retval State of bit (1 or 0).
2986 */
2987 __STATIC_INLINE uint32_t LL_RCC_HSE_IsReady(void)
2988 {
2989 return (READ_BIT(RCC->CR, RCC_CR_HSERDY) == (RCC_CR_HSERDY));
2990 }
2991
2992 /**
2993 * @}
2994 */
2995
2996 /** @defgroup RCC_LL_EF_HSI HSI
2997 * @{
2998 */
2999
3000 /**
3001 * @brief Enable HSI oscillator
3002 * @rmtoll CR HSION LL_RCC_HSI_Enable
3003 * @retval None
3004 */
3005 __STATIC_INLINE void LL_RCC_HSI_Enable(void)
3006 {
3007 SET_BIT(RCC->CR, RCC_CR_HSION);
3008 }
3009
3010 /**
3011 * @brief Disable HSI oscillator
3012 * @rmtoll CR HSION LL_RCC_HSI_Disable
3013 * @retval None
3014 */
3015 __STATIC_INLINE void LL_RCC_HSI_Disable(void)
3016 {
3017 CLEAR_BIT(RCC->CR, RCC_CR_HSION);
3018 }
3019
3020 /**
3021 * @brief Check if HSI clock is ready
3022 * @rmtoll CR HSIRDY LL_RCC_HSI_IsReady
3023 * @retval State of bit (1 or 0).
3024 */
3025 __STATIC_INLINE uint32_t LL_RCC_HSI_IsReady(void)
3026 {
3027 return (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == (RCC_CR_HSIRDY));
3028 }
3029
3030 /**
3031 * @brief Get HSI Calibration value
3032 * @note When HSITRIM is written, HSICAL is updated with the sum of
3033 * HSITRIM and the factory trim value
3034 * @rmtoll CR HSICAL LL_RCC_HSI_GetCalibration
3035 * @retval Between Min_Data = 0x00 and Max_Data = 0xFF
3036 */
3037 __STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibration(void)
3038 {
3039 return (uint32_t)(READ_BIT(RCC->CR, RCC_CR_HSICAL) >> RCC_CR_HSICAL_Pos);
3040 }
3041
3042 /**
3043 * @brief Set HSI Calibration trimming
3044 * @note user-programmable trimming value that is added to the HSICAL
3045 * @note Default value is 16, which, when added to the HSICAL value,
3046 * should trim the HSI to 16 MHz +/- 1 %
3047 * @rmtoll CR HSITRIM LL_RCC_HSI_SetCalibTrimming
3048 * @param Value Between Min_Data = 0 and Max_Data = 31
3049 * @retval None
3050 */
3051 __STATIC_INLINE void LL_RCC_HSI_SetCalibTrimming(uint32_t Value)
3052 {
3053 MODIFY_REG(RCC->CR, RCC_CR_HSITRIM, Value << RCC_CR_HSITRIM_Pos);
3054 }
3055
3056 /**
3057 * @brief Get HSI Calibration trimming
3058 * @rmtoll CR HSITRIM LL_RCC_HSI_GetCalibTrimming
3059 * @retval Between Min_Data = 0 and Max_Data = 31
3060 */
3061 __STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibTrimming(void)
3062 {
3063 return (uint32_t)(READ_BIT(RCC->CR, RCC_CR_HSITRIM) >> RCC_CR_HSITRIM_Pos);
3064 }
3065
3066 /**
3067 * @}
3068 */
3069
3070 /** @defgroup RCC_LL_EF_LSE LSE
3071 * @{
3072 */
3073
3074 /**
3075 * @brief Enable Low Speed External (LSE) crystal.
3076 * @rmtoll BDCR LSEON LL_RCC_LSE_Enable
3077 * @retval None
3078 */
3079 __STATIC_INLINE void LL_RCC_LSE_Enable(void)
3080 {
3081 SET_BIT(RCC->BDCR, RCC_BDCR_LSEON);
3082 }
3083
3084 /**
3085 * @brief Disable Low Speed External (LSE) crystal.
3086 * @rmtoll BDCR LSEON LL_RCC_LSE_Disable
3087 * @retval None
3088 */
3089 __STATIC_INLINE void LL_RCC_LSE_Disable(void)
3090 {
3091 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON);
3092 }
3093
3094 /**
3095 * @brief Enable external clock source (LSE bypass).
3096 * @rmtoll BDCR LSEBYP LL_RCC_LSE_EnableBypass
3097 * @retval None
3098 */
3099 __STATIC_INLINE void LL_RCC_LSE_EnableBypass(void)
3100 {
3101 SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);
3102 }
3103
3104 /**
3105 * @brief Disable external clock source (LSE bypass).
3106 * @rmtoll BDCR LSEBYP LL_RCC_LSE_DisableBypass
3107 * @retval None
3108 */
3109 __STATIC_INLINE void LL_RCC_LSE_DisableBypass(void)
3110 {
3111 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);
3112 }
3113
3114 /**
3115 * @brief Check if LSE oscillator Ready
3116 * @rmtoll BDCR LSERDY LL_RCC_LSE_IsReady
3117 * @retval State of bit (1 or 0).
3118 */
3119 __STATIC_INLINE uint32_t LL_RCC_LSE_IsReady(void)
3120 {
3121 return (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == (RCC_BDCR_LSERDY));
3122 }
3123
3124 #if defined(RCC_BDCR_LSEMOD)
3125 /**
3126 * @brief Enable LSE high drive mode.
3127 * @note LSE high drive mode can be enabled only when the LSE clock is disabled
3128 * @rmtoll BDCR LSEMOD LL_RCC_LSE_EnableHighDriveMode
3129 * @retval None
3130 */
3131 __STATIC_INLINE void LL_RCC_LSE_EnableHighDriveMode(void)
3132 {
3133 SET_BIT(RCC->BDCR, RCC_BDCR_LSEMOD);
3134 }
3135
3136 /**
3137 * @brief Disable LSE high drive mode.
3138 * @note LSE high drive mode can be disabled only when the LSE clock is disabled
3139 * @rmtoll BDCR LSEMOD LL_RCC_LSE_DisableHighDriveMode
3140 * @retval None
3141 */
3142 __STATIC_INLINE void LL_RCC_LSE_DisableHighDriveMode(void)
3143 {
3144 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEMOD);
3145 }
3146 #endif /* RCC_BDCR_LSEMOD */
3147
3148 /**
3149 * @}
3150 */
3151
3152 /** @defgroup RCC_LL_EF_LSI LSI
3153 * @{
3154 */
3155
3156 /**
3157 * @brief Enable LSI Oscillator
3158 * @rmtoll CSR LSION LL_RCC_LSI_Enable
3159 * @retval None
3160 */
3161 __STATIC_INLINE void LL_RCC_LSI_Enable(void)
3162 {
3163 SET_BIT(RCC->CSR, RCC_CSR_LSION);
3164 }
3165
3166 /**
3167 * @brief Disable LSI Oscillator
3168 * @rmtoll CSR LSION LL_RCC_LSI_Disable
3169 * @retval None
3170 */
3171 __STATIC_INLINE void LL_RCC_LSI_Disable(void)
3172 {
3173 CLEAR_BIT(RCC->CSR, RCC_CSR_LSION);
3174 }
3175
3176 /**
3177 * @brief Check if LSI is Ready
3178 * @rmtoll CSR LSIRDY LL_RCC_LSI_IsReady
3179 * @retval State of bit (1 or 0).
3180 */
3181 __STATIC_INLINE uint32_t LL_RCC_LSI_IsReady(void)
3182 {
3183 return (READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == (RCC_CSR_LSIRDY));
3184 }
3185
3186 /**
3187 * @}
3188 */
3189
3190 /** @defgroup RCC_LL_EF_System System
3191 * @{
3192 */
3193
3194 /**
3195 * @brief Configure the system clock source
3196 * @rmtoll CFGR SW LL_RCC_SetSysClkSource
3197 * @param Source This parameter can be one of the following values:
3198 * @arg @ref LL_RCC_SYS_CLKSOURCE_HSI
3199 * @arg @ref LL_RCC_SYS_CLKSOURCE_HSE
3200 * @arg @ref LL_RCC_SYS_CLKSOURCE_PLL
3201 * @arg @ref LL_RCC_SYS_CLKSOURCE_PLLR (*)
3202 *
3203 * (*) value not defined in all devices.
3204 * @retval None
3205 */
3206 __STATIC_INLINE void LL_RCC_SetSysClkSource(uint32_t Source)
3207 {
3208 MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, Source);
3209 }
3210
3211 /**
3212 * @brief Get the system clock source
3213 * @rmtoll CFGR SWS LL_RCC_GetSysClkSource
3214 * @retval Returned value can be one of the following values:
3215 * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSI
3216 * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSE
3217 * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_PLL
3218 * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_PLLR (*)
3219 *
3220 * (*) value not defined in all devices.
3221 */
3222 __STATIC_INLINE uint32_t LL_RCC_GetSysClkSource(void)
3223 {
3224 return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_SWS));
3225 }
3226
3227 /**
3228 * @brief Set AHB prescaler
3229 * @rmtoll CFGR HPRE LL_RCC_SetAHBPrescaler
3230 * @param Prescaler This parameter can be one of the following values:
3231 * @arg @ref LL_RCC_SYSCLK_DIV_1
3232 * @arg @ref LL_RCC_SYSCLK_DIV_2
3233 * @arg @ref LL_RCC_SYSCLK_DIV_4
3234 * @arg @ref LL_RCC_SYSCLK_DIV_8
3235 * @arg @ref LL_RCC_SYSCLK_DIV_16
3236 * @arg @ref LL_RCC_SYSCLK_DIV_64
3237 * @arg @ref LL_RCC_SYSCLK_DIV_128
3238 * @arg @ref LL_RCC_SYSCLK_DIV_256
3239 * @arg @ref LL_RCC_SYSCLK_DIV_512
3240 * @retval None
3241 */
3242 __STATIC_INLINE void LL_RCC_SetAHBPrescaler(uint32_t Prescaler)
3243 {
3244 MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, Prescaler);
3245 }
3246
3247 /**
3248 * @brief Set APB1 prescaler
3249 * @rmtoll CFGR PPRE1 LL_RCC_SetAPB1Prescaler
3250 * @param Prescaler This parameter can be one of the following values:
3251 * @arg @ref LL_RCC_APB1_DIV_1
3252 * @arg @ref LL_RCC_APB1_DIV_2
3253 * @arg @ref LL_RCC_APB1_DIV_4
3254 * @arg @ref LL_RCC_APB1_DIV_8
3255 * @arg @ref LL_RCC_APB1_DIV_16
3256 * @retval None
3257 */
3258 __STATIC_INLINE void LL_RCC_SetAPB1Prescaler(uint32_t Prescaler)
3259 {
3260 MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, Prescaler);
3261 }
3262
3263 /**
3264 * @brief Set APB2 prescaler
3265 * @rmtoll CFGR PPRE2 LL_RCC_SetAPB2Prescaler
3266 * @param Prescaler This parameter can be one of the following values:
3267 * @arg @ref LL_RCC_APB2_DIV_1
3268 * @arg @ref LL_RCC_APB2_DIV_2
3269 * @arg @ref LL_RCC_APB2_DIV_4
3270 * @arg @ref LL_RCC_APB2_DIV_8
3271 * @arg @ref LL_RCC_APB2_DIV_16
3272 * @retval None
3273 */
3274 __STATIC_INLINE void LL_RCC_SetAPB2Prescaler(uint32_t Prescaler)
3275 {
3276 MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, Prescaler);
3277 }
3278
3279 /**
3280 * @brief Get AHB prescaler
3281 * @rmtoll CFGR HPRE LL_RCC_GetAHBPrescaler
3282 * @retval Returned value can be one of the following values:
3283 * @arg @ref LL_RCC_SYSCLK_DIV_1
3284 * @arg @ref LL_RCC_SYSCLK_DIV_2
3285 * @arg @ref LL_RCC_SYSCLK_DIV_4
3286 * @arg @ref LL_RCC_SYSCLK_DIV_8
3287 * @arg @ref LL_RCC_SYSCLK_DIV_16
3288 * @arg @ref LL_RCC_SYSCLK_DIV_64
3289 * @arg @ref LL_RCC_SYSCLK_DIV_128
3290 * @arg @ref LL_RCC_SYSCLK_DIV_256
3291 * @arg @ref LL_RCC_SYSCLK_DIV_512
3292 */
3293 __STATIC_INLINE uint32_t LL_RCC_GetAHBPrescaler(void)
3294 {
3295 return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_HPRE));
3296 }
3297
3298 /**
3299 * @brief Get APB1 prescaler
3300 * @rmtoll CFGR PPRE1 LL_RCC_GetAPB1Prescaler
3301 * @retval Returned value can be one of the following values:
3302 * @arg @ref LL_RCC_APB1_DIV_1
3303 * @arg @ref LL_RCC_APB1_DIV_2
3304 * @arg @ref LL_RCC_APB1_DIV_4
3305 * @arg @ref LL_RCC_APB1_DIV_8
3306 * @arg @ref LL_RCC_APB1_DIV_16
3307 */
3308 __STATIC_INLINE uint32_t LL_RCC_GetAPB1Prescaler(void)
3309 {
3310 return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PPRE1));
3311 }
3312
3313 /**
3314 * @brief Get APB2 prescaler
3315 * @rmtoll CFGR PPRE2 LL_RCC_GetAPB2Prescaler
3316 * @retval Returned value can be one of the following values:
3317 * @arg @ref LL_RCC_APB2_DIV_1
3318 * @arg @ref LL_RCC_APB2_DIV_2
3319 * @arg @ref LL_RCC_APB2_DIV_4
3320 * @arg @ref LL_RCC_APB2_DIV_8
3321 * @arg @ref LL_RCC_APB2_DIV_16
3322 */
3323 __STATIC_INLINE uint32_t LL_RCC_GetAPB2Prescaler(void)
3324 {
3325 return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PPRE2));
3326 }
3327
3328 /**
3329 * @}
3330 */
3331
3332 /** @defgroup RCC_LL_EF_MCO MCO
3333 * @{
3334 */
3335
3336 #if defined(RCC_CFGR_MCO1EN)
3337 /**
3338 * @brief Enable MCO1 output
3339 * @rmtoll CFGR RCC_CFGR_MCO1EN LL_RCC_MCO1_Enable
3340 * @retval None
3341 */
3342 __STATIC_INLINE void LL_RCC_MCO1_Enable(void)
3343 {
3344 SET_BIT(RCC->CFGR, RCC_CFGR_MCO1EN);
3345 }
3346
3347 /**
3348 * @brief Disable MCO1 output
3349 * @rmtoll CFGR RCC_CFGR_MCO1EN LL_RCC_MCO1_Disable
3350 * @retval None
3351 */
3352 __STATIC_INLINE void LL_RCC_MCO1_Disable(void)
3353 {
3354 CLEAR_BIT(RCC->CFGR, RCC_CFGR_MCO1EN);
3355 }
3356 #endif /* RCC_CFGR_MCO1EN */
3357
3358 #if defined(RCC_CFGR_MCO2EN)
3359 /**
3360 * @brief Enable MCO2 output
3361 * @rmtoll CFGR RCC_CFGR_MCO2EN LL_RCC_MCO2_Enable
3362 * @retval None
3363 */
3364 __STATIC_INLINE void LL_RCC_MCO2_Enable(void)
3365 {
3366 SET_BIT(RCC->CFGR, RCC_CFGR_MCO2EN);
3367 }
3368
3369 /**
3370 * @brief Disable MCO2 output
3371 * @rmtoll CFGR RCC_CFGR_MCO2EN LL_RCC_MCO2_Disable
3372 * @retval None
3373 */
3374 __STATIC_INLINE void LL_RCC_MCO2_Disable(void)
3375 {
3376 CLEAR_BIT(RCC->CFGR, RCC_CFGR_MCO2EN);
3377 }
3378 #endif /* RCC_CFGR_MCO2EN */
3379
3380 /**
3381 * @brief Configure MCOx
3382 * @rmtoll CFGR MCO1 LL_RCC_ConfigMCO\n
3383 * CFGR MCO1PRE LL_RCC_ConfigMCO\n
3384 * CFGR MCO2 LL_RCC_ConfigMCO\n
3385 * CFGR MCO2PRE LL_RCC_ConfigMCO
3386 * @param MCOxSource This parameter can be one of the following values:
3387 * @arg @ref LL_RCC_MCO1SOURCE_HSI
3388 * @arg @ref LL_RCC_MCO1SOURCE_LSE
3389 * @arg @ref LL_RCC_MCO1SOURCE_HSE
3390 * @arg @ref LL_RCC_MCO1SOURCE_PLLCLK
3391 * @arg @ref LL_RCC_MCO2SOURCE_SYSCLK
3392 * @arg @ref LL_RCC_MCO2SOURCE_PLLI2S
3393 * @arg @ref LL_RCC_MCO2SOURCE_HSE
3394 * @arg @ref LL_RCC_MCO2SOURCE_PLLCLK
3395 * @param MCOxPrescaler This parameter can be one of the following values:
3396 * @arg @ref LL_RCC_MCO1_DIV_1
3397 * @arg @ref LL_RCC_MCO1_DIV_2
3398 * @arg @ref LL_RCC_MCO1_DIV_3
3399 * @arg @ref LL_RCC_MCO1_DIV_4
3400 * @arg @ref LL_RCC_MCO1_DIV_5
3401 * @arg @ref LL_RCC_MCO2_DIV_1
3402 * @arg @ref LL_RCC_MCO2_DIV_2
3403 * @arg @ref LL_RCC_MCO2_DIV_3
3404 * @arg @ref LL_RCC_MCO2_DIV_4
3405 * @arg @ref LL_RCC_MCO2_DIV_5
3406 * @retval None
3407 */
3408 __STATIC_INLINE void LL_RCC_ConfigMCO(uint32_t MCOxSource, uint32_t MCOxPrescaler)
3409 {
3410 MODIFY_REG(RCC->CFGR, (MCOxSource & 0xFFFF0000U) | (MCOxPrescaler & 0xFFFF0000U), (MCOxSource << 16U) | (MCOxPrescaler << 16U));
3411 }
3412
3413 /**
3414 * @}
3415 */
3416
3417 /** @defgroup RCC_LL_EF_Peripheral_Clock_Source Peripheral Clock Source
3418 * @{
3419 */
3420 #if defined(FMPI2C1)
3421 /**
3422 * @brief Configure FMPI2C clock source
3423 * @rmtoll DCKCFGR2 FMPI2C1SEL LL_RCC_SetFMPI2CClockSource
3424 * @param FMPI2CxSource This parameter can be one of the following values:
3425 * @arg @ref LL_RCC_FMPI2C1_CLKSOURCE_PCLK1
3426 * @arg @ref LL_RCC_FMPI2C1_CLKSOURCE_SYSCLK
3427 * @arg @ref LL_RCC_FMPI2C1_CLKSOURCE_HSI
3428 * @retval None
3429 */
3430 __STATIC_INLINE void LL_RCC_SetFMPI2CClockSource(uint32_t FMPI2CxSource)
3431 {
3432 MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_FMPI2C1SEL, FMPI2CxSource);
3433 }
3434 #endif /* FMPI2C1 */
3435
3436 #if defined(LPTIM1)
3437 /**
3438 * @brief Configure LPTIMx clock source
3439 * @rmtoll DCKCFGR2 LPTIM1SEL LL_RCC_SetLPTIMClockSource
3440 * @param LPTIMxSource This parameter can be one of the following values:
3441 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PCLK1
3442 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_HSI
3443 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSI
3444 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSE
3445 * @retval None
3446 */
3447 __STATIC_INLINE void LL_RCC_SetLPTIMClockSource(uint32_t LPTIMxSource)
3448 {
3449 MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_LPTIM1SEL, LPTIMxSource);
3450 }
3451 #endif /* LPTIM1 */
3452
3453 #if defined(SAI1)
3454 /**
3455 * @brief Configure SAIx clock source
3456 * @rmtoll DCKCFGR SAI1SRC LL_RCC_SetSAIClockSource\n
3457 * DCKCFGR SAI2SRC LL_RCC_SetSAIClockSource\n
3458 * DCKCFGR SAI1ASRC LL_RCC_SetSAIClockSource\n
3459 * DCKCFGR SAI1BSRC LL_RCC_SetSAIClockSource
3460 * @param SAIxSource This parameter can be one of the following values:
3461 * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLLSAI (*)
3462 * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLLI2S (*)
3463 * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL (*)
3464 * @arg @ref LL_RCC_SAI1_CLKSOURCE_PIN (*)
3465 * @arg @ref LL_RCC_SAI2_CLKSOURCE_PLLSAI (*)
3466 * @arg @ref LL_RCC_SAI2_CLKSOURCE_PLLI2S (*)
3467 * @arg @ref LL_RCC_SAI2_CLKSOURCE_PLL (*)
3468 * @arg @ref LL_RCC_SAI2_CLKSOURCE_PLLSRC (*)
3469 * @arg @ref LL_RCC_SAI1_A_CLKSOURCE_PLLSAI (*)
3470 * @arg @ref LL_RCC_SAI1_A_CLKSOURCE_PLLI2S (*)
3471 * @arg @ref LL_RCC_SAI1_A_CLKSOURCE_PIN (*)
3472 * @arg @ref LL_RCC_SAI1_A_CLKSOURCE_PLL (*)
3473 * @arg @ref LL_RCC_SAI1_A_CLKSOURCE_PLLSRC (*)
3474 * @arg @ref LL_RCC_SAI1_B_CLKSOURCE_PLLSAI (*)
3475 * @arg @ref LL_RCC_SAI1_B_CLKSOURCE_PLLI2S (*)
3476 * @arg @ref LL_RCC_SAI1_B_CLKSOURCE_PIN (*)
3477 * @arg @ref LL_RCC_SAI1_B_CLKSOURCE_PLL (*)
3478 * @arg @ref LL_RCC_SAI1_B_CLKSOURCE_PLLSRC (*)
3479 *
3480 * (*) value not defined in all devices.
3481 * @retval None
3482 */
3483 __STATIC_INLINE void LL_RCC_SetSAIClockSource(uint32_t SAIxSource)
3484 {
3485 MODIFY_REG(RCC->DCKCFGR, (SAIxSource & 0xFFFF0000U), (SAIxSource << 16U));
3486 }
3487 #endif /* SAI1 */
3488
3489 #if defined(RCC_DCKCFGR_SDIOSEL) || defined(RCC_DCKCFGR2_SDIOSEL)
3490 /**
3491 * @brief Configure SDIO clock source
3492 * @rmtoll DCKCFGR SDIOSEL LL_RCC_SetSDIOClockSource\n
3493 * DCKCFGR2 SDIOSEL LL_RCC_SetSDIOClockSource
3494 * @param SDIOxSource This parameter can be one of the following values:
3495 * @arg @ref LL_RCC_SDIO_CLKSOURCE_PLL48CLK
3496 * @arg @ref LL_RCC_SDIO_CLKSOURCE_SYSCLK
3497 * @retval None
3498 */
3499 __STATIC_INLINE void LL_RCC_SetSDIOClockSource(uint32_t SDIOxSource)
3500 {
3501 #if defined(RCC_DCKCFGR_SDIOSEL)
3502 MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_SDIOSEL, SDIOxSource);
3503 #else
3504 MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_SDIOSEL, SDIOxSource);
3505 #endif /* RCC_DCKCFGR_SDIOSEL */
3506 }
3507 #endif /* RCC_DCKCFGR_SDIOSEL || RCC_DCKCFGR2_SDIOSEL */
3508
3509 #if defined(RCC_DCKCFGR_CK48MSEL) || defined(RCC_DCKCFGR2_CK48MSEL)
3510 /**
3511 * @brief Configure 48Mhz domain clock source
3512 * @rmtoll DCKCFGR CK48MSEL LL_RCC_SetCK48MClockSource\n
3513 * DCKCFGR2 CK48MSEL LL_RCC_SetCK48MClockSource
3514 * @param CK48MxSource This parameter can be one of the following values:
3515 * @arg @ref LL_RCC_CK48M_CLKSOURCE_PLL
3516 * @arg @ref LL_RCC_CK48M_CLKSOURCE_PLLSAI (*)
3517 * @arg @ref LL_RCC_CK48M_CLKSOURCE_PLLI2S (*)
3518 *
3519 * (*) value not defined in all devices.
3520 * @retval None
3521 */
3522 __STATIC_INLINE void LL_RCC_SetCK48MClockSource(uint32_t CK48MxSource)
3523 {
3524 #if defined(RCC_DCKCFGR_CK48MSEL)
3525 MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_CK48MSEL, CK48MxSource);
3526 #else
3527 MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL, CK48MxSource);
3528 #endif /* RCC_DCKCFGR_CK48MSEL */
3529 }
3530
3531 #if defined(RNG)
3532 /**
3533 * @brief Configure RNG clock source
3534 * @rmtoll DCKCFGR CK48MSEL LL_RCC_SetRNGClockSource\n
3535 * DCKCFGR2 CK48MSEL LL_RCC_SetRNGClockSource
3536 * @param RNGxSource This parameter can be one of the following values:
3537 * @arg @ref LL_RCC_RNG_CLKSOURCE_PLL
3538 * @arg @ref LL_RCC_RNG_CLKSOURCE_PLLSAI (*)
3539 * @arg @ref LL_RCC_RNG_CLKSOURCE_PLLI2S (*)
3540 *
3541 * (*) value not defined in all devices.
3542 * @retval None
3543 */
3544 __STATIC_INLINE void LL_RCC_SetRNGClockSource(uint32_t RNGxSource)
3545 {
3546 #if defined(RCC_DCKCFGR_CK48MSEL)
3547 MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_CK48MSEL, RNGxSource);
3548 #else
3549 MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL, RNGxSource);
3550 #endif /* RCC_DCKCFGR_CK48MSEL */
3551 }
3552 #endif /* RNG */
3553
3554 #if defined(USB_OTG_FS) || defined(USB_OTG_HS)
3555 /**
3556 * @brief Configure USB clock source
3557 * @rmtoll DCKCFGR CK48MSEL LL_RCC_SetUSBClockSource\n
3558 * DCKCFGR2 CK48MSEL LL_RCC_SetUSBClockSource
3559 * @param USBxSource This parameter can be one of the following values:
3560 * @arg @ref LL_RCC_USB_CLKSOURCE_PLL
3561 * @arg @ref LL_RCC_USB_CLKSOURCE_PLLSAI (*)
3562 * @arg @ref LL_RCC_USB_CLKSOURCE_PLLI2S (*)
3563 *
3564 * (*) value not defined in all devices.
3565 * @retval None
3566 */
3567 __STATIC_INLINE void LL_RCC_SetUSBClockSource(uint32_t USBxSource)
3568 {
3569 #if defined(RCC_DCKCFGR_CK48MSEL)
3570 MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_CK48MSEL, USBxSource);
3571 #else
3572 MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL, USBxSource);
3573 #endif /* RCC_DCKCFGR_CK48MSEL */
3574 }
3575 #endif /* USB_OTG_FS || USB_OTG_HS */
3576 #endif /* RCC_DCKCFGR_CK48MSEL || RCC_DCKCFGR2_CK48MSEL */
3577
3578 #if defined(CEC)
3579 /**
3580 * @brief Configure CEC clock source
3581 * @rmtoll DCKCFGR2 CECSEL LL_RCC_SetCECClockSource
3582 * @param Source This parameter can be one of the following values:
3583 * @arg @ref LL_RCC_CEC_CLKSOURCE_HSI_DIV488
3584 * @arg @ref LL_RCC_CEC_CLKSOURCE_LSE
3585 * @retval None
3586 */
3587 __STATIC_INLINE void LL_RCC_SetCECClockSource(uint32_t Source)
3588 {
3589 MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CECSEL, Source);
3590 }
3591 #endif /* CEC */
3592
3593 /**
3594 * @brief Configure I2S clock source
3595 * @rmtoll CFGR I2SSRC LL_RCC_SetI2SClockSource\n
3596 * DCKCFGR I2SSRC LL_RCC_SetI2SClockSource\n
3597 * DCKCFGR I2S1SRC LL_RCC_SetI2SClockSource\n
3598 * DCKCFGR I2S2SRC LL_RCC_SetI2SClockSource
3599 * @param Source This parameter can be one of the following values:
3600 * @arg @ref LL_RCC_I2S1_CLKSOURCE_PLLI2S (*)
3601 * @arg @ref LL_RCC_I2S1_CLKSOURCE_PIN
3602 * @arg @ref LL_RCC_I2S1_CLKSOURCE_PLL (*)
3603 * @arg @ref LL_RCC_I2S1_CLKSOURCE_PLLSRC (*)
3604 * @arg @ref LL_RCC_I2S2_CLKSOURCE_PLLI2S (*)
3605 * @arg @ref LL_RCC_I2S2_CLKSOURCE_PIN (*)
3606 * @arg @ref LL_RCC_I2S2_CLKSOURCE_PLL (*)
3607 * @arg @ref LL_RCC_I2S2_CLKSOURCE_PLLSRC (*)
3608 *
3609 * (*) value not defined in all devices.
3610 * @retval None
3611 */
3612 __STATIC_INLINE void LL_RCC_SetI2SClockSource(uint32_t Source)
3613 {
3614 #if defined(RCC_CFGR_I2SSRC)
3615 MODIFY_REG(RCC->CFGR, RCC_CFGR_I2SSRC, Source);
3616 #else
3617 MODIFY_REG(RCC->DCKCFGR, (Source & 0xFFFF0000U), (Source << 16U));
3618 #endif /* RCC_CFGR_I2SSRC */
3619 }
3620
3621 #if defined(DSI)
3622 /**
3623 * @brief Configure DSI clock source
3624 * @rmtoll DCKCFGR DSISEL LL_RCC_SetDSIClockSource
3625 * @param Source This parameter can be one of the following values:
3626 * @arg @ref LL_RCC_DSI_CLKSOURCE_PHY
3627 * @arg @ref LL_RCC_DSI_CLKSOURCE_PLL
3628 * @retval None
3629 */
3630 __STATIC_INLINE void LL_RCC_SetDSIClockSource(uint32_t Source)
3631 {
3632 MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_DSISEL, Source);
3633 }
3634 #endif /* DSI */
3635
3636 #if defined(DFSDM1_Channel0)
3637 /**
3638 * @brief Configure DFSDM Audio clock source
3639 * @rmtoll DCKCFGR CKDFSDM1ASEL LL_RCC_SetDFSDMAudioClockSource\n
3640 * DCKCFGR CKDFSDM2ASEL LL_RCC_SetDFSDMAudioClockSource
3641 * @param Source This parameter can be one of the following values:
3642 * @arg @ref LL_RCC_DFSDM1_AUDIO_CLKSOURCE_I2S1
3643 * @arg @ref LL_RCC_DFSDM1_AUDIO_CLKSOURCE_I2S2
3644 * @arg @ref LL_RCC_DFSDM2_AUDIO_CLKSOURCE_I2S1 (*)
3645 * @arg @ref LL_RCC_DFSDM2_AUDIO_CLKSOURCE_I2S2 (*)
3646 *
3647 * (*) value not defined in all devices.
3648 * @retval None
3649 */
3650 __STATIC_INLINE void LL_RCC_SetDFSDMAudioClockSource(uint32_t Source)
3651 {
3652 MODIFY_REG(RCC->DCKCFGR, (Source & 0x0000FFFFU), (Source >> 16U));
3653 }
3654
3655 /**
3656 * @brief Configure DFSDM Kernel clock source
3657 * @rmtoll DCKCFGR CKDFSDM1SEL LL_RCC_SetDFSDMClockSource
3658 * @param Source This parameter can be one of the following values:
3659 * @arg @ref LL_RCC_DFSDM1_CLKSOURCE_PCLK2
3660 * @arg @ref LL_RCC_DFSDM1_CLKSOURCE_SYSCLK
3661 * @arg @ref LL_RCC_DFSDM2_CLKSOURCE_PCLK2 (*)
3662 * @arg @ref LL_RCC_DFSDM2_CLKSOURCE_SYSCLK (*)
3663 *
3664 * (*) value not defined in all devices.
3665 * @retval None
3666 */
3667 __STATIC_INLINE void LL_RCC_SetDFSDMClockSource(uint32_t Source)
3668 {
3669 MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_CKDFSDM1SEL, Source);
3670 }
3671 #endif /* DFSDM1_Channel0 */
3672
3673 #if defined(SPDIFRX)
3674 /**
3675 * @brief Configure SPDIFRX clock source
3676 * @rmtoll DCKCFGR2 SPDIFRXSEL LL_RCC_SetSPDIFRXClockSource
3677 * @param SPDIFRXxSource This parameter can be one of the following values:
3678 * @arg @ref LL_RCC_SPDIFRX1_CLKSOURCE_PLL
3679 * @arg @ref LL_RCC_SPDIFRX1_CLKSOURCE_PLLI2S
3680 *
3681 * (*) value not defined in all devices.
3682 * @retval None
3683 */
3684 __STATIC_INLINE void LL_RCC_SetSPDIFRXClockSource(uint32_t SPDIFRXxSource)
3685 {
3686 MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_SPDIFRXSEL, SPDIFRXxSource);
3687 }
3688 #endif /* SPDIFRX */
3689
3690 #if defined(FMPI2C1)
3691 /**
3692 * @brief Get FMPI2C clock source
3693 * @rmtoll DCKCFGR2 FMPI2C1SEL LL_RCC_GetFMPI2CClockSource
3694 * @param FMPI2Cx This parameter can be one of the following values:
3695 * @arg @ref LL_RCC_FMPI2C1_CLKSOURCE
3696 * @retval Returned value can be one of the following values:
3697 * @arg @ref LL_RCC_FMPI2C1_CLKSOURCE_PCLK1
3698 * @arg @ref LL_RCC_FMPI2C1_CLKSOURCE_SYSCLK
3699 * @arg @ref LL_RCC_FMPI2C1_CLKSOURCE_HSI
3700 */
3701 __STATIC_INLINE uint32_t LL_RCC_GetFMPI2CClockSource(uint32_t FMPI2Cx)
3702 {
3703 return (uint32_t)(READ_BIT(RCC->DCKCFGR2, FMPI2Cx));
3704 }
3705 #endif /* FMPI2C1 */
3706
3707 #if defined(LPTIM1)
3708 /**
3709 * @brief Get LPTIMx clock source
3710 * @rmtoll DCKCFGR2 LPTIM1SEL LL_RCC_GetLPTIMClockSource
3711 * @param LPTIMx This parameter can be one of the following values:
3712 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE
3713 * @retval Returned value can be one of the following values:
3714 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PCLK1
3715 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_HSI
3716 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSI
3717 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSE
3718 */
3719 __STATIC_INLINE uint32_t LL_RCC_GetLPTIMClockSource(uint32_t LPTIMx)
3720 {
3721 return (uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_LPTIM1SEL));
3722 }
3723 #endif /* LPTIM1 */
3724
3725 #if defined(SAI1)
3726 /**
3727 * @brief Get SAIx clock source
3728 * @rmtoll DCKCFGR SAI1SEL LL_RCC_GetSAIClockSource\n
3729 * DCKCFGR SAI2SEL LL_RCC_GetSAIClockSource\n
3730 * DCKCFGR SAI1ASRC LL_RCC_GetSAIClockSource\n
3731 * DCKCFGR SAI1BSRC LL_RCC_GetSAIClockSource
3732 * @param SAIx This parameter can be one of the following values:
3733 * @arg @ref LL_RCC_SAI1_CLKSOURCE (*)
3734 * @arg @ref LL_RCC_SAI2_CLKSOURCE (*)
3735 * @arg @ref LL_RCC_SAI1_A_CLKSOURCE (*)
3736 * @arg @ref LL_RCC_SAI1_B_CLKSOURCE (*)
3737 *
3738 * (*) value not defined in all devices.
3739 * @retval Returned value can be one of the following values:
3740 * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLLSAI (*)
3741 * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLLI2S (*)
3742 * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL (*)
3743 * @arg @ref LL_RCC_SAI1_CLKSOURCE_PIN (*)
3744 * @arg @ref LL_RCC_SAI2_CLKSOURCE_PLLSAI (*)
3745 * @arg @ref LL_RCC_SAI2_CLKSOURCE_PLLI2S (*)
3746 * @arg @ref LL_RCC_SAI2_CLKSOURCE_PLL (*)
3747 * @arg @ref LL_RCC_SAI2_CLKSOURCE_PLLSRC (*)
3748 * @arg @ref LL_RCC_SAI1_A_CLKSOURCE_PLLSAI (*)
3749 * @arg @ref LL_RCC_SAI1_A_CLKSOURCE_PLLI2S (*)
3750 * @arg @ref LL_RCC_SAI1_A_CLKSOURCE_PIN (*)
3751 * @arg @ref LL_RCC_SAI1_A_CLKSOURCE_PLL (*)
3752 * @arg @ref LL_RCC_SAI1_A_CLKSOURCE_PLLSRC (*)
3753 * @arg @ref LL_RCC_SAI1_B_CLKSOURCE_PLLSAI (*)
3754 * @arg @ref LL_RCC_SAI1_B_CLKSOURCE_PLLI2S (*)
3755 * @arg @ref LL_RCC_SAI1_B_CLKSOURCE_PIN (*)
3756 * @arg @ref LL_RCC_SAI1_B_CLKSOURCE_PLL (*)
3757 * @arg @ref LL_RCC_SAI1_B_CLKSOURCE_PLLSRC (*)
3758 *
3759 * (*) value not defined in all devices.
3760 */
3761 __STATIC_INLINE uint32_t LL_RCC_GetSAIClockSource(uint32_t SAIx)
3762 {
3763 return (uint32_t)(READ_BIT(RCC->DCKCFGR, SAIx) >> 16U | SAIx);
3764 }
3765 #endif /* SAI1 */
3766
3767 #if defined(RCC_DCKCFGR_SDIOSEL) || defined(RCC_DCKCFGR2_SDIOSEL)
3768 /**
3769 * @brief Get SDIOx clock source
3770 * @rmtoll DCKCFGR SDIOSEL LL_RCC_GetSDIOClockSource\n
3771 * DCKCFGR2 SDIOSEL LL_RCC_GetSDIOClockSource
3772 * @param SDIOx This parameter can be one of the following values:
3773 * @arg @ref LL_RCC_SDIO_CLKSOURCE
3774 * @retval Returned value can be one of the following values:
3775 * @arg @ref LL_RCC_SDIO_CLKSOURCE_PLL48CLK
3776 * @arg @ref LL_RCC_SDIO_CLKSOURCE_SYSCLK
3777 */
3778 __STATIC_INLINE uint32_t LL_RCC_GetSDIOClockSource(uint32_t SDIOx)
3779 {
3780 #if defined(RCC_DCKCFGR_SDIOSEL)
3781 return (uint32_t)(READ_BIT(RCC->DCKCFGR, SDIOx));
3782 #else
3783 return (uint32_t)(READ_BIT(RCC->DCKCFGR2, SDIOx));
3784 #endif /* RCC_DCKCFGR_SDIOSEL */
3785 }
3786 #endif /* RCC_DCKCFGR_SDIOSEL || RCC_DCKCFGR2_SDIOSEL */
3787
3788 #if defined(RCC_DCKCFGR_CK48MSEL) || defined(RCC_DCKCFGR2_CK48MSEL)
3789 /**
3790 * @brief Get 48Mhz domain clock source
3791 * @rmtoll DCKCFGR CK48MSEL LL_RCC_GetCK48MClockSource\n
3792 * DCKCFGR2 CK48MSEL LL_RCC_GetCK48MClockSource
3793 * @param CK48Mx This parameter can be one of the following values:
3794 * @arg @ref LL_RCC_CK48M_CLKSOURCE
3795 * @retval Returned value can be one of the following values:
3796 * @arg @ref LL_RCC_CK48M_CLKSOURCE_PLL
3797 * @arg @ref LL_RCC_CK48M_CLKSOURCE_PLLSAI (*)
3798 * @arg @ref LL_RCC_CK48M_CLKSOURCE_PLLI2S (*)
3799 *
3800 * (*) value not defined in all devices.
3801 */
3802 __STATIC_INLINE uint32_t LL_RCC_GetCK48MClockSource(uint32_t CK48Mx)
3803 {
3804 #if defined(RCC_DCKCFGR_CK48MSEL)
3805 return (uint32_t)(READ_BIT(RCC->DCKCFGR, CK48Mx));
3806 #else
3807 return (uint32_t)(READ_BIT(RCC->DCKCFGR2, CK48Mx));
3808 #endif /* RCC_DCKCFGR_CK48MSEL */
3809 }
3810
3811 #if defined(RNG)
3812 /**
3813 * @brief Get RNGx clock source
3814 * @rmtoll DCKCFGR CK48MSEL LL_RCC_GetRNGClockSource\n
3815 * DCKCFGR2 CK48MSEL LL_RCC_GetRNGClockSource
3816 * @param RNGx This parameter can be one of the following values:
3817 * @arg @ref LL_RCC_RNG_CLKSOURCE
3818 * @retval Returned value can be one of the following values:
3819 * @arg @ref LL_RCC_RNG_CLKSOURCE_PLL
3820 * @arg @ref LL_RCC_RNG_CLKSOURCE_PLLSAI (*)
3821 * @arg @ref LL_RCC_RNG_CLKSOURCE_PLLI2S (*)
3822 *
3823 * (*) value not defined in all devices.
3824 */
3825 __STATIC_INLINE uint32_t LL_RCC_GetRNGClockSource(uint32_t RNGx)
3826 {
3827 #if defined(RCC_DCKCFGR_CK48MSEL)
3828 return (uint32_t)(READ_BIT(RCC->DCKCFGR, RNGx));
3829 #else
3830 return (uint32_t)(READ_BIT(RCC->DCKCFGR2, RNGx));
3831 #endif /* RCC_DCKCFGR_CK48MSEL */
3832 }
3833 #endif /* RNG */
3834
3835 #if defined(USB_OTG_FS) || defined(USB_OTG_HS)
3836 /**
3837 * @brief Get USBx clock source
3838 * @rmtoll DCKCFGR CK48MSEL LL_RCC_GetUSBClockSource\n
3839 * DCKCFGR2 CK48MSEL LL_RCC_GetUSBClockSource
3840 * @param USBx This parameter can be one of the following values:
3841 * @arg @ref LL_RCC_USB_CLKSOURCE
3842 * @retval Returned value can be one of the following values:
3843 * @arg @ref LL_RCC_USB_CLKSOURCE_PLL
3844 * @arg @ref LL_RCC_USB_CLKSOURCE_PLLSAI (*)
3845 * @arg @ref LL_RCC_USB_CLKSOURCE_PLLI2S (*)
3846 *
3847 * (*) value not defined in all devices.
3848 */
3849 __STATIC_INLINE uint32_t LL_RCC_GetUSBClockSource(uint32_t USBx)
3850 {
3851 #if defined(RCC_DCKCFGR_CK48MSEL)
3852 return (uint32_t)(READ_BIT(RCC->DCKCFGR, USBx));
3853 #else
3854 return (uint32_t)(READ_BIT(RCC->DCKCFGR2, USBx));
3855 #endif /* RCC_DCKCFGR_CK48MSEL */
3856 }
3857 #endif /* USB_OTG_FS || USB_OTG_HS */
3858 #endif /* RCC_DCKCFGR_CK48MSEL || RCC_DCKCFGR2_CK48MSEL */
3859
3860 #if defined(CEC)
3861 /**
3862 * @brief Get CEC Clock Source
3863 * @rmtoll DCKCFGR2 CECSEL LL_RCC_GetCECClockSource
3864 * @param CECx This parameter can be one of the following values:
3865 * @arg @ref LL_RCC_CEC_CLKSOURCE
3866 * @retval Returned value can be one of the following values:
3867 * @arg @ref LL_RCC_CEC_CLKSOURCE_HSI_DIV488
3868 * @arg @ref LL_RCC_CEC_CLKSOURCE_LSE
3869 */
3870 __STATIC_INLINE uint32_t LL_RCC_GetCECClockSource(uint32_t CECx)
3871 {
3872 return (uint32_t)(READ_BIT(RCC->DCKCFGR2, CECx));
3873 }
3874 #endif /* CEC */
3875
3876 /**
3877 * @brief Get I2S Clock Source
3878 * @rmtoll CFGR I2SSRC LL_RCC_GetI2SClockSource\n
3879 * DCKCFGR I2SSRC LL_RCC_GetI2SClockSource\n
3880 * DCKCFGR I2S1SRC LL_RCC_GetI2SClockSource\n
3881 * DCKCFGR I2S2SRC LL_RCC_GetI2SClockSource
3882 * @param I2Sx This parameter can be one of the following values:
3883 * @arg @ref LL_RCC_I2S1_CLKSOURCE
3884 * @arg @ref LL_RCC_I2S2_CLKSOURCE (*)
3885 * @retval Returned value can be one of the following values:
3886 * @arg @ref LL_RCC_I2S1_CLKSOURCE_PLLI2S (*)
3887 * @arg @ref LL_RCC_I2S1_CLKSOURCE_PIN
3888 * @arg @ref LL_RCC_I2S1_CLKSOURCE_PLL (*)
3889 * @arg @ref LL_RCC_I2S1_CLKSOURCE_PLLSRC (*)
3890 * @arg @ref LL_RCC_I2S2_CLKSOURCE_PLLI2S (*)
3891 * @arg @ref LL_RCC_I2S2_CLKSOURCE_PIN (*)
3892 * @arg @ref LL_RCC_I2S2_CLKSOURCE_PLL (*)
3893 * @arg @ref LL_RCC_I2S2_CLKSOURCE_PLLSRC (*)
3894 *
3895 * (*) value not defined in all devices.
3896 */
3897 __STATIC_INLINE uint32_t LL_RCC_GetI2SClockSource(uint32_t I2Sx)
3898 {
3899 #if defined(RCC_CFGR_I2SSRC)
3900 return (uint32_t)(READ_BIT(RCC->CFGR, I2Sx));
3901 #else
3902 return (uint32_t)(READ_BIT(RCC->DCKCFGR, I2Sx) >> 16U | I2Sx);
3903 #endif /* RCC_CFGR_I2SSRC */
3904 }
3905
3906 #if defined(DFSDM1_Channel0)
3907 /**
3908 * @brief Get DFSDM Audio Clock Source
3909 * @rmtoll DCKCFGR CKDFSDM1ASEL LL_RCC_GetDFSDMAudioClockSource\n
3910 * DCKCFGR CKDFSDM2ASEL LL_RCC_GetDFSDMAudioClockSource
3911 * @param DFSDMx This parameter can be one of the following values:
3912 * @arg @ref LL_RCC_DFSDM1_AUDIO_CLKSOURCE
3913 * @arg @ref LL_RCC_DFSDM2_AUDIO_CLKSOURCE (*)
3914 * @retval Returned value can be one of the following values:
3915 * @arg @ref LL_RCC_DFSDM1_AUDIO_CLKSOURCE_I2S1
3916 * @arg @ref LL_RCC_DFSDM1_AUDIO_CLKSOURCE_I2S2
3917 * @arg @ref LL_RCC_DFSDM2_AUDIO_CLKSOURCE_I2S1 (*)
3918 * @arg @ref LL_RCC_DFSDM2_AUDIO_CLKSOURCE_I2S2 (*)
3919 *
3920 * (*) value not defined in all devices.
3921 */
3922 __STATIC_INLINE uint32_t LL_RCC_GetDFSDMAudioClockSource(uint32_t DFSDMx)
3923 {
3924 return (uint32_t)(READ_BIT(RCC->DCKCFGR, DFSDMx) << 16U | DFSDMx);
3925 }
3926
3927 /**
3928 * @brief Get DFSDM Audio Clock Source
3929 * @rmtoll DCKCFGR CKDFSDM1SEL LL_RCC_GetDFSDMClockSource
3930 * @param DFSDMx This parameter can be one of the following values:
3931 * @arg @ref LL_RCC_DFSDM1_CLKSOURCE
3932 * @arg @ref LL_RCC_DFSDM2_CLKSOURCE (*)
3933 * @retval Returned value can be one of the following values:
3934 * @arg @ref LL_RCC_DFSDM1_CLKSOURCE_PCLK2
3935 * @arg @ref LL_RCC_DFSDM1_CLKSOURCE_SYSCLK
3936 * @arg @ref LL_RCC_DFSDM2_CLKSOURCE_PCLK2 (*)
3937 * @arg @ref LL_RCC_DFSDM2_CLKSOURCE_SYSCLK (*)
3938 *
3939 * (*) value not defined in all devices.
3940 */
3941 __STATIC_INLINE uint32_t LL_RCC_GetDFSDMClockSource(uint32_t DFSDMx)
3942 {
3943 return (uint32_t)(READ_BIT(RCC->DCKCFGR, DFSDMx));
3944 }
3945 #endif /* DFSDM1_Channel0 */
3946
3947 #if defined(SPDIFRX)
3948 /**
3949 * @brief Get SPDIFRX clock source
3950 * @rmtoll DCKCFGR2 SPDIFRXSEL LL_RCC_GetSPDIFRXClockSource
3951 * @param SPDIFRXx This parameter can be one of the following values:
3952 * @arg @ref LL_RCC_SPDIFRX1_CLKSOURCE
3953 * @retval Returned value can be one of the following values:
3954 * @arg @ref LL_RCC_SPDIFRX1_CLKSOURCE_PLL
3955 * @arg @ref LL_RCC_SPDIFRX1_CLKSOURCE_PLLI2S
3956 *
3957 * (*) value not defined in all devices.
3958 */
3959 __STATIC_INLINE uint32_t LL_RCC_GetSPDIFRXClockSource(uint32_t SPDIFRXx)
3960 {
3961 return (uint32_t)(READ_BIT(RCC->DCKCFGR2, SPDIFRXx));
3962 }
3963 #endif /* SPDIFRX */
3964
3965 #if defined(DSI)
3966 /**
3967 * @brief Get DSI Clock Source
3968 * @rmtoll DCKCFGR DSISEL LL_RCC_GetDSIClockSource
3969 * @param DSIx This parameter can be one of the following values:
3970 * @arg @ref LL_RCC_DSI_CLKSOURCE
3971 * @retval Returned value can be one of the following values:
3972 * @arg @ref LL_RCC_DSI_CLKSOURCE_PHY
3973 * @arg @ref LL_RCC_DSI_CLKSOURCE_PLL
3974 */
3975 __STATIC_INLINE uint32_t LL_RCC_GetDSIClockSource(uint32_t DSIx)
3976 {
3977 return (uint32_t)(READ_BIT(RCC->DCKCFGR, DSIx));
3978 }
3979 #endif /* DSI */
3980
3981 /**
3982 * @}
3983 */
3984
3985 /** @defgroup RCC_LL_EF_RTC RTC
3986 * @{
3987 */
3988
3989 /**
3990 * @brief Set RTC Clock Source
3991 * @note Once the RTC clock source has been selected, it cannot be changed anymore unless
3992 * the Backup domain is reset, or unless a failure is detected on LSE (LSECSSD is
3993 * set). The BDRST bit can be used to reset them.
3994 * @rmtoll BDCR RTCSEL LL_RCC_SetRTCClockSource
3995 * @param Source This parameter can be one of the following values:
3996 * @arg @ref LL_RCC_RTC_CLKSOURCE_NONE
3997 * @arg @ref LL_RCC_RTC_CLKSOURCE_LSE
3998 * @arg @ref LL_RCC_RTC_CLKSOURCE_LSI
3999 * @arg @ref LL_RCC_RTC_CLKSOURCE_HSE
4000 * @retval None
4001 */
4002 __STATIC_INLINE void LL_RCC_SetRTCClockSource(uint32_t Source)
4003 {
4004 MODIFY_REG(RCC->BDCR, RCC_BDCR_RTCSEL, Source);
4005 }
4006
4007 /**
4008 * @brief Get RTC Clock Source
4009 * @rmtoll BDCR RTCSEL LL_RCC_GetRTCClockSource
4010 * @retval Returned value can be one of the following values:
4011 * @arg @ref LL_RCC_RTC_CLKSOURCE_NONE
4012 * @arg @ref LL_RCC_RTC_CLKSOURCE_LSE
4013 * @arg @ref LL_RCC_RTC_CLKSOURCE_LSI
4014 * @arg @ref LL_RCC_RTC_CLKSOURCE_HSE
4015 */
4016 __STATIC_INLINE uint32_t LL_RCC_GetRTCClockSource(void)
4017 {
4018 return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL));
4019 }
4020
4021 /**
4022 * @brief Enable RTC
4023 * @rmtoll BDCR RTCEN LL_RCC_EnableRTC
4024 * @retval None
4025 */
4026 __STATIC_INLINE void LL_RCC_EnableRTC(void)
4027 {
4028 SET_BIT(RCC->BDCR, RCC_BDCR_RTCEN);
4029 }
4030
4031 /**
4032 * @brief Disable RTC
4033 * @rmtoll BDCR RTCEN LL_RCC_DisableRTC
4034 * @retval None
4035 */
4036 __STATIC_INLINE void LL_RCC_DisableRTC(void)
4037 {
4038 CLEAR_BIT(RCC->BDCR, RCC_BDCR_RTCEN);
4039 }
4040
4041 /**
4042 * @brief Check if RTC has been enabled or not
4043 * @rmtoll BDCR RTCEN LL_RCC_IsEnabledRTC
4044 * @retval State of bit (1 or 0).
4045 */
4046 __STATIC_INLINE uint32_t LL_RCC_IsEnabledRTC(void)
4047 {
4048 return (READ_BIT(RCC->BDCR, RCC_BDCR_RTCEN) == (RCC_BDCR_RTCEN));
4049 }
4050
4051 /**
4052 * @brief Force the Backup domain reset
4053 * @rmtoll BDCR BDRST LL_RCC_ForceBackupDomainReset
4054 * @retval None
4055 */
4056 __STATIC_INLINE void LL_RCC_ForceBackupDomainReset(void)
4057 {
4058 SET_BIT(RCC->BDCR, RCC_BDCR_BDRST);
4059 }
4060
4061 /**
4062 * @brief Release the Backup domain reset
4063 * @rmtoll BDCR BDRST LL_RCC_ReleaseBackupDomainReset
4064 * @retval None
4065 */
4066 __STATIC_INLINE void LL_RCC_ReleaseBackupDomainReset(void)
4067 {
4068 CLEAR_BIT(RCC->BDCR, RCC_BDCR_BDRST);
4069 }
4070
4071 /**
4072 * @brief Set HSE Prescalers for RTC Clock
4073 * @rmtoll CFGR RTCPRE LL_RCC_SetRTC_HSEPrescaler
4074 * @param Prescaler This parameter can be one of the following values:
4075 * @arg @ref LL_RCC_RTC_NOCLOCK
4076 * @arg @ref LL_RCC_RTC_HSE_DIV_2
4077 * @arg @ref LL_RCC_RTC_HSE_DIV_3
4078 * @arg @ref LL_RCC_RTC_HSE_DIV_4
4079 * @arg @ref LL_RCC_RTC_HSE_DIV_5
4080 * @arg @ref LL_RCC_RTC_HSE_DIV_6
4081 * @arg @ref LL_RCC_RTC_HSE_DIV_7
4082 * @arg @ref LL_RCC_RTC_HSE_DIV_8
4083 * @arg @ref LL_RCC_RTC_HSE_DIV_9
4084 * @arg @ref LL_RCC_RTC_HSE_DIV_10
4085 * @arg @ref LL_RCC_RTC_HSE_DIV_11
4086 * @arg @ref LL_RCC_RTC_HSE_DIV_12
4087 * @arg @ref LL_RCC_RTC_HSE_DIV_13
4088 * @arg @ref LL_RCC_RTC_HSE_DIV_14
4089 * @arg @ref LL_RCC_RTC_HSE_DIV_15
4090 * @arg @ref LL_RCC_RTC_HSE_DIV_16
4091 * @arg @ref LL_RCC_RTC_HSE_DIV_17
4092 * @arg @ref LL_RCC_RTC_HSE_DIV_18
4093 * @arg @ref LL_RCC_RTC_HSE_DIV_19
4094 * @arg @ref LL_RCC_RTC_HSE_DIV_20
4095 * @arg @ref LL_RCC_RTC_HSE_DIV_21
4096 * @arg @ref LL_RCC_RTC_HSE_DIV_22
4097 * @arg @ref LL_RCC_RTC_HSE_DIV_23
4098 * @arg @ref LL_RCC_RTC_HSE_DIV_24
4099 * @arg @ref LL_RCC_RTC_HSE_DIV_25
4100 * @arg @ref LL_RCC_RTC_HSE_DIV_26
4101 * @arg @ref LL_RCC_RTC_HSE_DIV_27
4102 * @arg @ref LL_RCC_RTC_HSE_DIV_28
4103 * @arg @ref LL_RCC_RTC_HSE_DIV_29
4104 * @arg @ref LL_RCC_RTC_HSE_DIV_30
4105 * @arg @ref LL_RCC_RTC_HSE_DIV_31
4106 * @retval None
4107 */
4108 __STATIC_INLINE void LL_RCC_SetRTC_HSEPrescaler(uint32_t Prescaler)
4109 {
4110 MODIFY_REG(RCC->CFGR, RCC_CFGR_RTCPRE, Prescaler);
4111 }
4112
4113 /**
4114 * @brief Get HSE Prescalers for RTC Clock
4115 * @rmtoll CFGR RTCPRE LL_RCC_GetRTC_HSEPrescaler
4116 * @retval Returned value can be one of the following values:
4117 * @arg @ref LL_RCC_RTC_NOCLOCK
4118 * @arg @ref LL_RCC_RTC_HSE_DIV_2
4119 * @arg @ref LL_RCC_RTC_HSE_DIV_3
4120 * @arg @ref LL_RCC_RTC_HSE_DIV_4
4121 * @arg @ref LL_RCC_RTC_HSE_DIV_5
4122 * @arg @ref LL_RCC_RTC_HSE_DIV_6
4123 * @arg @ref LL_RCC_RTC_HSE_DIV_7
4124 * @arg @ref LL_RCC_RTC_HSE_DIV_8
4125 * @arg @ref LL_RCC_RTC_HSE_DIV_9
4126 * @arg @ref LL_RCC_RTC_HSE_DIV_10
4127 * @arg @ref LL_RCC_RTC_HSE_DIV_11
4128 * @arg @ref LL_RCC_RTC_HSE_DIV_12
4129 * @arg @ref LL_RCC_RTC_HSE_DIV_13
4130 * @arg @ref LL_RCC_RTC_HSE_DIV_14
4131 * @arg @ref LL_RCC_RTC_HSE_DIV_15
4132 * @arg @ref LL_RCC_RTC_HSE_DIV_16
4133 * @arg @ref LL_RCC_RTC_HSE_DIV_17
4134 * @arg @ref LL_RCC_RTC_HSE_DIV_18
4135 * @arg @ref LL_RCC_RTC_HSE_DIV_19
4136 * @arg @ref LL_RCC_RTC_HSE_DIV_20
4137 * @arg @ref LL_RCC_RTC_HSE_DIV_21
4138 * @arg @ref LL_RCC_RTC_HSE_DIV_22
4139 * @arg @ref LL_RCC_RTC_HSE_DIV_23
4140 * @arg @ref LL_RCC_RTC_HSE_DIV_24
4141 * @arg @ref LL_RCC_RTC_HSE_DIV_25
4142 * @arg @ref LL_RCC_RTC_HSE_DIV_26
4143 * @arg @ref LL_RCC_RTC_HSE_DIV_27
4144 * @arg @ref LL_RCC_RTC_HSE_DIV_28
4145 * @arg @ref LL_RCC_RTC_HSE_DIV_29
4146 * @arg @ref LL_RCC_RTC_HSE_DIV_30
4147 * @arg @ref LL_RCC_RTC_HSE_DIV_31
4148 */
4149 __STATIC_INLINE uint32_t LL_RCC_GetRTC_HSEPrescaler(void)
4150 {
4151 return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_RTCPRE));
4152 }
4153
4154 /**
4155 * @}
4156 */
4157
4158 #if defined(RCC_DCKCFGR_TIMPRE)
4159 /** @defgroup RCC_LL_EF_TIM_CLOCK_PRESCALER TIM
4160 * @{
4161 */
4162
4163 /**
4164 * @brief Set Timers Clock Prescalers
4165 * @rmtoll DCKCFGR TIMPRE LL_RCC_SetTIMPrescaler
4166 * @param Prescaler This parameter can be one of the following values:
4167 * @arg @ref LL_RCC_TIM_PRESCALER_TWICE
4168 * @arg @ref LL_RCC_TIM_PRESCALER_FOUR_TIMES
4169 * @retval None
4170 */
4171 __STATIC_INLINE void LL_RCC_SetTIMPrescaler(uint32_t Prescaler)
4172 {
4173 MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_TIMPRE, Prescaler);
4174 }
4175
4176 /**
4177 * @brief Get Timers Clock Prescalers
4178 * @rmtoll DCKCFGR TIMPRE LL_RCC_GetTIMPrescaler
4179 * @retval Returned value can be one of the following values:
4180 * @arg @ref LL_RCC_TIM_PRESCALER_TWICE
4181 * @arg @ref LL_RCC_TIM_PRESCALER_FOUR_TIMES
4182 */
4183 __STATIC_INLINE uint32_t LL_RCC_GetTIMPrescaler(void)
4184 {
4185 return (uint32_t)(READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_TIMPRE));
4186 }
4187
4188 /**
4189 * @}
4190 */
4191 #endif /* RCC_DCKCFGR_TIMPRE */
4192
4193 /** @defgroup RCC_LL_EF_PLL PLL
4194 * @{
4195 */
4196
4197 /**
4198 * @brief Enable PLL
4199 * @rmtoll CR PLLON LL_RCC_PLL_Enable
4200 * @retval None
4201 */
4202 __STATIC_INLINE void LL_RCC_PLL_Enable(void)
4203 {
4204 SET_BIT(RCC->CR, RCC_CR_PLLON);
4205 }
4206
4207 /**
4208 * @brief Disable PLL
4209 * @note Cannot be disabled if the PLL clock is used as the system clock
4210 * @rmtoll CR PLLON LL_RCC_PLL_Disable
4211 * @retval None
4212 */
4213 __STATIC_INLINE void LL_RCC_PLL_Disable(void)
4214 {
4215 CLEAR_BIT(RCC->CR, RCC_CR_PLLON);
4216 }
4217
4218 /**
4219 * @brief Check if PLL Ready
4220 * @rmtoll CR PLLRDY LL_RCC_PLL_IsReady
4221 * @retval State of bit (1 or 0).
4222 */
4223 __STATIC_INLINE uint32_t LL_RCC_PLL_IsReady(void)
4224 {
4225 return (READ_BIT(RCC->CR, RCC_CR_PLLRDY) == (RCC_CR_PLLRDY));
4226 }
4227
4228 /**
4229 * @brief Configure PLL used for SYSCLK Domain
4230 * @note PLL Source and PLLM Divider can be written only when PLL,
4231 * PLLI2S and PLLSAI(*) are disabled
4232 * @note PLLN/PLLP can be written only when PLL is disabled
4233 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_ConfigDomain_SYS\n
4234 * PLLCFGR PLLM LL_RCC_PLL_ConfigDomain_SYS\n
4235 * PLLCFGR PLLN LL_RCC_PLL_ConfigDomain_SYS\n
4236 * PLLCFGR PLLR LL_RCC_PLL_ConfigDomain_SYS\n
4237 * PLLCFGR PLLP LL_RCC_PLL_ConfigDomain_SYS
4238 * @param Source This parameter can be one of the following values:
4239 * @arg @ref LL_RCC_PLLSOURCE_HSI
4240 * @arg @ref LL_RCC_PLLSOURCE_HSE
4241 * @param PLLM This parameter can be one of the following values:
4242 * @arg @ref LL_RCC_PLLM_DIV_2
4243 * @arg @ref LL_RCC_PLLM_DIV_3
4244 * @arg @ref LL_RCC_PLLM_DIV_4
4245 * @arg @ref LL_RCC_PLLM_DIV_5
4246 * @arg @ref LL_RCC_PLLM_DIV_6
4247 * @arg @ref LL_RCC_PLLM_DIV_7
4248 * @arg @ref LL_RCC_PLLM_DIV_8
4249 * @arg @ref LL_RCC_PLLM_DIV_9
4250 * @arg @ref LL_RCC_PLLM_DIV_10
4251 * @arg @ref LL_RCC_PLLM_DIV_11
4252 * @arg @ref LL_RCC_PLLM_DIV_12
4253 * @arg @ref LL_RCC_PLLM_DIV_13
4254 * @arg @ref LL_RCC_PLLM_DIV_14
4255 * @arg @ref LL_RCC_PLLM_DIV_15
4256 * @arg @ref LL_RCC_PLLM_DIV_16
4257 * @arg @ref LL_RCC_PLLM_DIV_17
4258 * @arg @ref LL_RCC_PLLM_DIV_18
4259 * @arg @ref LL_RCC_PLLM_DIV_19
4260 * @arg @ref LL_RCC_PLLM_DIV_20
4261 * @arg @ref LL_RCC_PLLM_DIV_21
4262 * @arg @ref LL_RCC_PLLM_DIV_22
4263 * @arg @ref LL_RCC_PLLM_DIV_23
4264 * @arg @ref LL_RCC_PLLM_DIV_24
4265 * @arg @ref LL_RCC_PLLM_DIV_25
4266 * @arg @ref LL_RCC_PLLM_DIV_26
4267 * @arg @ref LL_RCC_PLLM_DIV_27
4268 * @arg @ref LL_RCC_PLLM_DIV_28
4269 * @arg @ref LL_RCC_PLLM_DIV_29
4270 * @arg @ref LL_RCC_PLLM_DIV_30
4271 * @arg @ref LL_RCC_PLLM_DIV_31
4272 * @arg @ref LL_RCC_PLLM_DIV_32
4273 * @arg @ref LL_RCC_PLLM_DIV_33
4274 * @arg @ref LL_RCC_PLLM_DIV_34
4275 * @arg @ref LL_RCC_PLLM_DIV_35
4276 * @arg @ref LL_RCC_PLLM_DIV_36
4277 * @arg @ref LL_RCC_PLLM_DIV_37
4278 * @arg @ref LL_RCC_PLLM_DIV_38
4279 * @arg @ref LL_RCC_PLLM_DIV_39
4280 * @arg @ref LL_RCC_PLLM_DIV_40
4281 * @arg @ref LL_RCC_PLLM_DIV_41
4282 * @arg @ref LL_RCC_PLLM_DIV_42
4283 * @arg @ref LL_RCC_PLLM_DIV_43
4284 * @arg @ref LL_RCC_PLLM_DIV_44
4285 * @arg @ref LL_RCC_PLLM_DIV_45
4286 * @arg @ref LL_RCC_PLLM_DIV_46
4287 * @arg @ref LL_RCC_PLLM_DIV_47
4288 * @arg @ref LL_RCC_PLLM_DIV_48
4289 * @arg @ref LL_RCC_PLLM_DIV_49
4290 * @arg @ref LL_RCC_PLLM_DIV_50
4291 * @arg @ref LL_RCC_PLLM_DIV_51
4292 * @arg @ref LL_RCC_PLLM_DIV_52
4293 * @arg @ref LL_RCC_PLLM_DIV_53
4294 * @arg @ref LL_RCC_PLLM_DIV_54
4295 * @arg @ref LL_RCC_PLLM_DIV_55
4296 * @arg @ref LL_RCC_PLLM_DIV_56
4297 * @arg @ref LL_RCC_PLLM_DIV_57
4298 * @arg @ref LL_RCC_PLLM_DIV_58
4299 * @arg @ref LL_RCC_PLLM_DIV_59
4300 * @arg @ref LL_RCC_PLLM_DIV_60
4301 * @arg @ref LL_RCC_PLLM_DIV_61
4302 * @arg @ref LL_RCC_PLLM_DIV_62
4303 * @arg @ref LL_RCC_PLLM_DIV_63
4304 * @param PLLN Between 50/192(*) and 432
4305 *
4306 * (*) value not defined in all devices.
4307 * @param PLLP_R This parameter can be one of the following values:
4308 * @arg @ref LL_RCC_PLLP_DIV_2
4309 * @arg @ref LL_RCC_PLLP_DIV_4
4310 * @arg @ref LL_RCC_PLLP_DIV_6
4311 * @arg @ref LL_RCC_PLLP_DIV_8
4312 * @arg @ref LL_RCC_PLLR_DIV_2 (*)
4313 * @arg @ref LL_RCC_PLLR_DIV_3 (*)
4314 * @arg @ref LL_RCC_PLLR_DIV_4 (*)
4315 * @arg @ref LL_RCC_PLLR_DIV_5 (*)
4316 * @arg @ref LL_RCC_PLLR_DIV_6 (*)
4317 * @arg @ref LL_RCC_PLLR_DIV_7 (*)
4318 *
4319 * (*) value not defined in all devices.
4320 * @retval None
4321 */
4322 __STATIC_INLINE void LL_RCC_PLL_ConfigDomain_SYS(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP_R)
4323 {
4324 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN,
4325 Source | PLLM | PLLN << RCC_PLLCFGR_PLLN_Pos);
4326 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLP, PLLP_R);
4327 #if defined(RCC_PLLR_SYSCLK_SUPPORT)
4328 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLR, PLLP_R);
4329 #endif /* RCC_PLLR_SYSCLK_SUPPORT */
4330 }
4331
4332 /**
4333 * @brief Configure PLL used for 48Mhz domain clock
4334 * @note PLL Source and PLLM Divider can be written only when PLL,
4335 * PLLI2S and PLLSAI(*) are disabled
4336 * @note PLLN/PLLQ can be written only when PLL is disabled
4337 * @note This can be selected for USB, RNG, SDIO
4338 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_ConfigDomain_48M\n
4339 * PLLCFGR PLLM LL_RCC_PLL_ConfigDomain_48M\n
4340 * PLLCFGR PLLN LL_RCC_PLL_ConfigDomain_48M\n
4341 * PLLCFGR PLLQ LL_RCC_PLL_ConfigDomain_48M
4342 * @param Source This parameter can be one of the following values:
4343 * @arg @ref LL_RCC_PLLSOURCE_HSI
4344 * @arg @ref LL_RCC_PLLSOURCE_HSE
4345 * @param PLLM This parameter can be one of the following values:
4346 * @arg @ref LL_RCC_PLLM_DIV_2
4347 * @arg @ref LL_RCC_PLLM_DIV_3
4348 * @arg @ref LL_RCC_PLLM_DIV_4
4349 * @arg @ref LL_RCC_PLLM_DIV_5
4350 * @arg @ref LL_RCC_PLLM_DIV_6
4351 * @arg @ref LL_RCC_PLLM_DIV_7
4352 * @arg @ref LL_RCC_PLLM_DIV_8
4353 * @arg @ref LL_RCC_PLLM_DIV_9
4354 * @arg @ref LL_RCC_PLLM_DIV_10
4355 * @arg @ref LL_RCC_PLLM_DIV_11
4356 * @arg @ref LL_RCC_PLLM_DIV_12
4357 * @arg @ref LL_RCC_PLLM_DIV_13
4358 * @arg @ref LL_RCC_PLLM_DIV_14
4359 * @arg @ref LL_RCC_PLLM_DIV_15
4360 * @arg @ref LL_RCC_PLLM_DIV_16
4361 * @arg @ref LL_RCC_PLLM_DIV_17
4362 * @arg @ref LL_RCC_PLLM_DIV_18
4363 * @arg @ref LL_RCC_PLLM_DIV_19
4364 * @arg @ref LL_RCC_PLLM_DIV_20
4365 * @arg @ref LL_RCC_PLLM_DIV_21
4366 * @arg @ref LL_RCC_PLLM_DIV_22
4367 * @arg @ref LL_RCC_PLLM_DIV_23
4368 * @arg @ref LL_RCC_PLLM_DIV_24
4369 * @arg @ref LL_RCC_PLLM_DIV_25
4370 * @arg @ref LL_RCC_PLLM_DIV_26
4371 * @arg @ref LL_RCC_PLLM_DIV_27
4372 * @arg @ref LL_RCC_PLLM_DIV_28
4373 * @arg @ref LL_RCC_PLLM_DIV_29
4374 * @arg @ref LL_RCC_PLLM_DIV_30
4375 * @arg @ref LL_RCC_PLLM_DIV_31
4376 * @arg @ref LL_RCC_PLLM_DIV_32
4377 * @arg @ref LL_RCC_PLLM_DIV_33
4378 * @arg @ref LL_RCC_PLLM_DIV_34
4379 * @arg @ref LL_RCC_PLLM_DIV_35
4380 * @arg @ref LL_RCC_PLLM_DIV_36
4381 * @arg @ref LL_RCC_PLLM_DIV_37
4382 * @arg @ref LL_RCC_PLLM_DIV_38
4383 * @arg @ref LL_RCC_PLLM_DIV_39
4384 * @arg @ref LL_RCC_PLLM_DIV_40
4385 * @arg @ref LL_RCC_PLLM_DIV_41
4386 * @arg @ref LL_RCC_PLLM_DIV_42
4387 * @arg @ref LL_RCC_PLLM_DIV_43
4388 * @arg @ref LL_RCC_PLLM_DIV_44
4389 * @arg @ref LL_RCC_PLLM_DIV_45
4390 * @arg @ref LL_RCC_PLLM_DIV_46
4391 * @arg @ref LL_RCC_PLLM_DIV_47
4392 * @arg @ref LL_RCC_PLLM_DIV_48
4393 * @arg @ref LL_RCC_PLLM_DIV_49
4394 * @arg @ref LL_RCC_PLLM_DIV_50
4395 * @arg @ref LL_RCC_PLLM_DIV_51
4396 * @arg @ref LL_RCC_PLLM_DIV_52
4397 * @arg @ref LL_RCC_PLLM_DIV_53
4398 * @arg @ref LL_RCC_PLLM_DIV_54
4399 * @arg @ref LL_RCC_PLLM_DIV_55
4400 * @arg @ref LL_RCC_PLLM_DIV_56
4401 * @arg @ref LL_RCC_PLLM_DIV_57
4402 * @arg @ref LL_RCC_PLLM_DIV_58
4403 * @arg @ref LL_RCC_PLLM_DIV_59
4404 * @arg @ref LL_RCC_PLLM_DIV_60
4405 * @arg @ref LL_RCC_PLLM_DIV_61
4406 * @arg @ref LL_RCC_PLLM_DIV_62
4407 * @arg @ref LL_RCC_PLLM_DIV_63
4408 * @param PLLN Between 50/192(*) and 432
4409 *
4410 * (*) value not defined in all devices.
4411 * @param PLLQ This parameter can be one of the following values:
4412 * @arg @ref LL_RCC_PLLQ_DIV_2
4413 * @arg @ref LL_RCC_PLLQ_DIV_3
4414 * @arg @ref LL_RCC_PLLQ_DIV_4
4415 * @arg @ref LL_RCC_PLLQ_DIV_5
4416 * @arg @ref LL_RCC_PLLQ_DIV_6
4417 * @arg @ref LL_RCC_PLLQ_DIV_7
4418 * @arg @ref LL_RCC_PLLQ_DIV_8
4419 * @arg @ref LL_RCC_PLLQ_DIV_9
4420 * @arg @ref LL_RCC_PLLQ_DIV_10
4421 * @arg @ref LL_RCC_PLLQ_DIV_11
4422 * @arg @ref LL_RCC_PLLQ_DIV_12
4423 * @arg @ref LL_RCC_PLLQ_DIV_13
4424 * @arg @ref LL_RCC_PLLQ_DIV_14
4425 * @arg @ref LL_RCC_PLLQ_DIV_15
4426 * @retval None
4427 */
4428 __STATIC_INLINE void LL_RCC_PLL_ConfigDomain_48M(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLQ)
4429 {
4430 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLQ,
4431 Source | PLLM | PLLN << RCC_PLLCFGR_PLLN_Pos | PLLQ);
4432 }
4433
4434 #if defined(DSI)
4435 /**
4436 * @brief Configure PLL used for DSI clock
4437 * @note PLL Source and PLLM Divider can be written only when PLL,
4438 * PLLI2S and PLLSAI are disabled
4439 * @note PLLN/PLLR can be written only when PLL is disabled
4440 * @note This can be selected for DSI
4441 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_ConfigDomain_DSI\n
4442 * PLLCFGR PLLM LL_RCC_PLL_ConfigDomain_DSI\n
4443 * PLLCFGR PLLN LL_RCC_PLL_ConfigDomain_DSI\n
4444 * PLLCFGR PLLR LL_RCC_PLL_ConfigDomain_DSI
4445 * @param Source This parameter can be one of the following values:
4446 * @arg @ref LL_RCC_PLLSOURCE_HSI
4447 * @arg @ref LL_RCC_PLLSOURCE_HSE
4448 * @param PLLM This parameter can be one of the following values:
4449 * @arg @ref LL_RCC_PLLM_DIV_2
4450 * @arg @ref LL_RCC_PLLM_DIV_3
4451 * @arg @ref LL_RCC_PLLM_DIV_4
4452 * @arg @ref LL_RCC_PLLM_DIV_5
4453 * @arg @ref LL_RCC_PLLM_DIV_6
4454 * @arg @ref LL_RCC_PLLM_DIV_7
4455 * @arg @ref LL_RCC_PLLM_DIV_8
4456 * @arg @ref LL_RCC_PLLM_DIV_9
4457 * @arg @ref LL_RCC_PLLM_DIV_10
4458 * @arg @ref LL_RCC_PLLM_DIV_11
4459 * @arg @ref LL_RCC_PLLM_DIV_12
4460 * @arg @ref LL_RCC_PLLM_DIV_13
4461 * @arg @ref LL_RCC_PLLM_DIV_14
4462 * @arg @ref LL_RCC_PLLM_DIV_15
4463 * @arg @ref LL_RCC_PLLM_DIV_16
4464 * @arg @ref LL_RCC_PLLM_DIV_17
4465 * @arg @ref LL_RCC_PLLM_DIV_18
4466 * @arg @ref LL_RCC_PLLM_DIV_19
4467 * @arg @ref LL_RCC_PLLM_DIV_20
4468 * @arg @ref LL_RCC_PLLM_DIV_21
4469 * @arg @ref LL_RCC_PLLM_DIV_22
4470 * @arg @ref LL_RCC_PLLM_DIV_23
4471 * @arg @ref LL_RCC_PLLM_DIV_24
4472 * @arg @ref LL_RCC_PLLM_DIV_25
4473 * @arg @ref LL_RCC_PLLM_DIV_26
4474 * @arg @ref LL_RCC_PLLM_DIV_27
4475 * @arg @ref LL_RCC_PLLM_DIV_28
4476 * @arg @ref LL_RCC_PLLM_DIV_29
4477 * @arg @ref LL_RCC_PLLM_DIV_30
4478 * @arg @ref LL_RCC_PLLM_DIV_31
4479 * @arg @ref LL_RCC_PLLM_DIV_32
4480 * @arg @ref LL_RCC_PLLM_DIV_33
4481 * @arg @ref LL_RCC_PLLM_DIV_34
4482 * @arg @ref LL_RCC_PLLM_DIV_35
4483 * @arg @ref LL_RCC_PLLM_DIV_36
4484 * @arg @ref LL_RCC_PLLM_DIV_37
4485 * @arg @ref LL_RCC_PLLM_DIV_38
4486 * @arg @ref LL_RCC_PLLM_DIV_39
4487 * @arg @ref LL_RCC_PLLM_DIV_40
4488 * @arg @ref LL_RCC_PLLM_DIV_41
4489 * @arg @ref LL_RCC_PLLM_DIV_42
4490 * @arg @ref LL_RCC_PLLM_DIV_43
4491 * @arg @ref LL_RCC_PLLM_DIV_44
4492 * @arg @ref LL_RCC_PLLM_DIV_45
4493 * @arg @ref LL_RCC_PLLM_DIV_46
4494 * @arg @ref LL_RCC_PLLM_DIV_47
4495 * @arg @ref LL_RCC_PLLM_DIV_48
4496 * @arg @ref LL_RCC_PLLM_DIV_49
4497 * @arg @ref LL_RCC_PLLM_DIV_50
4498 * @arg @ref LL_RCC_PLLM_DIV_51
4499 * @arg @ref LL_RCC_PLLM_DIV_52
4500 * @arg @ref LL_RCC_PLLM_DIV_53
4501 * @arg @ref LL_RCC_PLLM_DIV_54
4502 * @arg @ref LL_RCC_PLLM_DIV_55
4503 * @arg @ref LL_RCC_PLLM_DIV_56
4504 * @arg @ref LL_RCC_PLLM_DIV_57
4505 * @arg @ref LL_RCC_PLLM_DIV_58
4506 * @arg @ref LL_RCC_PLLM_DIV_59
4507 * @arg @ref LL_RCC_PLLM_DIV_60
4508 * @arg @ref LL_RCC_PLLM_DIV_61
4509 * @arg @ref LL_RCC_PLLM_DIV_62
4510 * @arg @ref LL_RCC_PLLM_DIV_63
4511 * @param PLLN Between 50 and 432
4512 * @param PLLR This parameter can be one of the following values:
4513 * @arg @ref LL_RCC_PLLR_DIV_2
4514 * @arg @ref LL_RCC_PLLR_DIV_3
4515 * @arg @ref LL_RCC_PLLR_DIV_4
4516 * @arg @ref LL_RCC_PLLR_DIV_5
4517 * @arg @ref LL_RCC_PLLR_DIV_6
4518 * @arg @ref LL_RCC_PLLR_DIV_7
4519 * @retval None
4520 */
4521 __STATIC_INLINE void LL_RCC_PLL_ConfigDomain_DSI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR)
4522 {
4523 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLR,
4524 Source | PLLM | PLLN << RCC_PLLCFGR_PLLN_Pos | PLLR);
4525 }
4526 #endif /* DSI */
4527
4528 #if defined(RCC_PLLR_I2S_CLKSOURCE_SUPPORT)
4529 /**
4530 * @brief Configure PLL used for I2S clock
4531 * @note PLL Source and PLLM Divider can be written only when PLL,
4532 * PLLI2S and PLLSAI are disabled
4533 * @note PLLN/PLLR can be written only when PLL is disabled
4534 * @note This can be selected for I2S
4535 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_ConfigDomain_I2S\n
4536 * PLLCFGR PLLM LL_RCC_PLL_ConfigDomain_I2S\n
4537 * PLLCFGR PLLN LL_RCC_PLL_ConfigDomain_I2S\n
4538 * PLLCFGR PLLR LL_RCC_PLL_ConfigDomain_I2S
4539 * @param Source This parameter can be one of the following values:
4540 * @arg @ref LL_RCC_PLLSOURCE_HSI
4541 * @arg @ref LL_RCC_PLLSOURCE_HSE
4542 * @param PLLM This parameter can be one of the following values:
4543 * @arg @ref LL_RCC_PLLM_DIV_2
4544 * @arg @ref LL_RCC_PLLM_DIV_3
4545 * @arg @ref LL_RCC_PLLM_DIV_4
4546 * @arg @ref LL_RCC_PLLM_DIV_5
4547 * @arg @ref LL_RCC_PLLM_DIV_6
4548 * @arg @ref LL_RCC_PLLM_DIV_7
4549 * @arg @ref LL_RCC_PLLM_DIV_8
4550 * @arg @ref LL_RCC_PLLM_DIV_9
4551 * @arg @ref LL_RCC_PLLM_DIV_10
4552 * @arg @ref LL_RCC_PLLM_DIV_11
4553 * @arg @ref LL_RCC_PLLM_DIV_12
4554 * @arg @ref LL_RCC_PLLM_DIV_13
4555 * @arg @ref LL_RCC_PLLM_DIV_14
4556 * @arg @ref LL_RCC_PLLM_DIV_15
4557 * @arg @ref LL_RCC_PLLM_DIV_16
4558 * @arg @ref LL_RCC_PLLM_DIV_17
4559 * @arg @ref LL_RCC_PLLM_DIV_18
4560 * @arg @ref LL_RCC_PLLM_DIV_19
4561 * @arg @ref LL_RCC_PLLM_DIV_20
4562 * @arg @ref LL_RCC_PLLM_DIV_21
4563 * @arg @ref LL_RCC_PLLM_DIV_22
4564 * @arg @ref LL_RCC_PLLM_DIV_23
4565 * @arg @ref LL_RCC_PLLM_DIV_24
4566 * @arg @ref LL_RCC_PLLM_DIV_25
4567 * @arg @ref LL_RCC_PLLM_DIV_26
4568 * @arg @ref LL_RCC_PLLM_DIV_27
4569 * @arg @ref LL_RCC_PLLM_DIV_28
4570 * @arg @ref LL_RCC_PLLM_DIV_29
4571 * @arg @ref LL_RCC_PLLM_DIV_30
4572 * @arg @ref LL_RCC_PLLM_DIV_31
4573 * @arg @ref LL_RCC_PLLM_DIV_32
4574 * @arg @ref LL_RCC_PLLM_DIV_33
4575 * @arg @ref LL_RCC_PLLM_DIV_34
4576 * @arg @ref LL_RCC_PLLM_DIV_35
4577 * @arg @ref LL_RCC_PLLM_DIV_36
4578 * @arg @ref LL_RCC_PLLM_DIV_37
4579 * @arg @ref LL_RCC_PLLM_DIV_38
4580 * @arg @ref LL_RCC_PLLM_DIV_39
4581 * @arg @ref LL_RCC_PLLM_DIV_40
4582 * @arg @ref LL_RCC_PLLM_DIV_41
4583 * @arg @ref LL_RCC_PLLM_DIV_42
4584 * @arg @ref LL_RCC_PLLM_DIV_43
4585 * @arg @ref LL_RCC_PLLM_DIV_44
4586 * @arg @ref LL_RCC_PLLM_DIV_45
4587 * @arg @ref LL_RCC_PLLM_DIV_46
4588 * @arg @ref LL_RCC_PLLM_DIV_47
4589 * @arg @ref LL_RCC_PLLM_DIV_48
4590 * @arg @ref LL_RCC_PLLM_DIV_49
4591 * @arg @ref LL_RCC_PLLM_DIV_50
4592 * @arg @ref LL_RCC_PLLM_DIV_51
4593 * @arg @ref LL_RCC_PLLM_DIV_52
4594 * @arg @ref LL_RCC_PLLM_DIV_53
4595 * @arg @ref LL_RCC_PLLM_DIV_54
4596 * @arg @ref LL_RCC_PLLM_DIV_55
4597 * @arg @ref LL_RCC_PLLM_DIV_56
4598 * @arg @ref LL_RCC_PLLM_DIV_57
4599 * @arg @ref LL_RCC_PLLM_DIV_58
4600 * @arg @ref LL_RCC_PLLM_DIV_59
4601 * @arg @ref LL_RCC_PLLM_DIV_60
4602 * @arg @ref LL_RCC_PLLM_DIV_61
4603 * @arg @ref LL_RCC_PLLM_DIV_62
4604 * @arg @ref LL_RCC_PLLM_DIV_63
4605 * @param PLLN Between 50 and 432
4606 * @param PLLR This parameter can be one of the following values:
4607 * @arg @ref LL_RCC_PLLR_DIV_2
4608 * @arg @ref LL_RCC_PLLR_DIV_3
4609 * @arg @ref LL_RCC_PLLR_DIV_4
4610 * @arg @ref LL_RCC_PLLR_DIV_5
4611 * @arg @ref LL_RCC_PLLR_DIV_6
4612 * @arg @ref LL_RCC_PLLR_DIV_7
4613 * @retval None
4614 */
4615 __STATIC_INLINE void LL_RCC_PLL_ConfigDomain_I2S(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR)
4616 {
4617 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLR,
4618 Source | PLLM | PLLN << RCC_PLLCFGR_PLLN_Pos | PLLR);
4619 }
4620 #endif /* RCC_PLLR_I2S_CLKSOURCE_SUPPORT */
4621
4622 #if defined(SPDIFRX)
4623 /**
4624 * @brief Configure PLL used for SPDIFRX clock
4625 * @note PLL Source and PLLM Divider can be written only when PLL,
4626 * PLLI2S and PLLSAI are disabled
4627 * @note PLLN/PLLR can be written only when PLL is disabled
4628 * @note This can be selected for SPDIFRX
4629 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_ConfigDomain_SPDIFRX\n
4630 * PLLCFGR PLLM LL_RCC_PLL_ConfigDomain_SPDIFRX\n
4631 * PLLCFGR PLLN LL_RCC_PLL_ConfigDomain_SPDIFRX\n
4632 * PLLCFGR PLLR LL_RCC_PLL_ConfigDomain_SPDIFRX
4633 * @param Source This parameter can be one of the following values:
4634 * @arg @ref LL_RCC_PLLSOURCE_HSI
4635 * @arg @ref LL_RCC_PLLSOURCE_HSE
4636 * @param PLLM This parameter can be one of the following values:
4637 * @arg @ref LL_RCC_PLLM_DIV_2
4638 * @arg @ref LL_RCC_PLLM_DIV_3
4639 * @arg @ref LL_RCC_PLLM_DIV_4
4640 * @arg @ref LL_RCC_PLLM_DIV_5
4641 * @arg @ref LL_RCC_PLLM_DIV_6
4642 * @arg @ref LL_RCC_PLLM_DIV_7
4643 * @arg @ref LL_RCC_PLLM_DIV_8
4644 * @arg @ref LL_RCC_PLLM_DIV_9
4645 * @arg @ref LL_RCC_PLLM_DIV_10
4646 * @arg @ref LL_RCC_PLLM_DIV_11
4647 * @arg @ref LL_RCC_PLLM_DIV_12
4648 * @arg @ref LL_RCC_PLLM_DIV_13
4649 * @arg @ref LL_RCC_PLLM_DIV_14
4650 * @arg @ref LL_RCC_PLLM_DIV_15
4651 * @arg @ref LL_RCC_PLLM_DIV_16
4652 * @arg @ref LL_RCC_PLLM_DIV_17
4653 * @arg @ref LL_RCC_PLLM_DIV_18
4654 * @arg @ref LL_RCC_PLLM_DIV_19
4655 * @arg @ref LL_RCC_PLLM_DIV_20
4656 * @arg @ref LL_RCC_PLLM_DIV_21
4657 * @arg @ref LL_RCC_PLLM_DIV_22
4658 * @arg @ref LL_RCC_PLLM_DIV_23
4659 * @arg @ref LL_RCC_PLLM_DIV_24
4660 * @arg @ref LL_RCC_PLLM_DIV_25
4661 * @arg @ref LL_RCC_PLLM_DIV_26
4662 * @arg @ref LL_RCC_PLLM_DIV_27
4663 * @arg @ref LL_RCC_PLLM_DIV_28
4664 * @arg @ref LL_RCC_PLLM_DIV_29
4665 * @arg @ref LL_RCC_PLLM_DIV_30
4666 * @arg @ref LL_RCC_PLLM_DIV_31
4667 * @arg @ref LL_RCC_PLLM_DIV_32
4668 * @arg @ref LL_RCC_PLLM_DIV_33
4669 * @arg @ref LL_RCC_PLLM_DIV_34
4670 * @arg @ref LL_RCC_PLLM_DIV_35
4671 * @arg @ref LL_RCC_PLLM_DIV_36
4672 * @arg @ref LL_RCC_PLLM_DIV_37
4673 * @arg @ref LL_RCC_PLLM_DIV_38
4674 * @arg @ref LL_RCC_PLLM_DIV_39
4675 * @arg @ref LL_RCC_PLLM_DIV_40
4676 * @arg @ref LL_RCC_PLLM_DIV_41
4677 * @arg @ref LL_RCC_PLLM_DIV_42
4678 * @arg @ref LL_RCC_PLLM_DIV_43
4679 * @arg @ref LL_RCC_PLLM_DIV_44
4680 * @arg @ref LL_RCC_PLLM_DIV_45
4681 * @arg @ref LL_RCC_PLLM_DIV_46
4682 * @arg @ref LL_RCC_PLLM_DIV_47
4683 * @arg @ref LL_RCC_PLLM_DIV_48
4684 * @arg @ref LL_RCC_PLLM_DIV_49
4685 * @arg @ref LL_RCC_PLLM_DIV_50
4686 * @arg @ref LL_RCC_PLLM_DIV_51
4687 * @arg @ref LL_RCC_PLLM_DIV_52
4688 * @arg @ref LL_RCC_PLLM_DIV_53
4689 * @arg @ref LL_RCC_PLLM_DIV_54
4690 * @arg @ref LL_RCC_PLLM_DIV_55
4691 * @arg @ref LL_RCC_PLLM_DIV_56
4692 * @arg @ref LL_RCC_PLLM_DIV_57
4693 * @arg @ref LL_RCC_PLLM_DIV_58
4694 * @arg @ref LL_RCC_PLLM_DIV_59
4695 * @arg @ref LL_RCC_PLLM_DIV_60
4696 * @arg @ref LL_RCC_PLLM_DIV_61
4697 * @arg @ref LL_RCC_PLLM_DIV_62
4698 * @arg @ref LL_RCC_PLLM_DIV_63
4699 * @param PLLN Between 50 and 432
4700 * @param PLLR This parameter can be one of the following values:
4701 * @arg @ref LL_RCC_PLLR_DIV_2
4702 * @arg @ref LL_RCC_PLLR_DIV_3
4703 * @arg @ref LL_RCC_PLLR_DIV_4
4704 * @arg @ref LL_RCC_PLLR_DIV_5
4705 * @arg @ref LL_RCC_PLLR_DIV_6
4706 * @arg @ref LL_RCC_PLLR_DIV_7
4707 * @retval None
4708 */
4709 __STATIC_INLINE void LL_RCC_PLL_ConfigDomain_SPDIFRX(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR)
4710 {
4711 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLR,
4712 Source | PLLM | PLLN << RCC_PLLCFGR_PLLN_Pos | PLLR);
4713 }
4714 #endif /* SPDIFRX */
4715
4716 #if defined(RCC_PLLCFGR_PLLR)
4717 #if defined(SAI1)
4718 /**
4719 * @brief Configure PLL used for SAI clock
4720 * @note PLL Source and PLLM Divider can be written only when PLL,
4721 * PLLI2S and PLLSAI are disabled
4722 * @note PLLN/PLLR can be written only when PLL is disabled
4723 * @note This can be selected for SAI
4724 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_ConfigDomain_SAI\n
4725 * PLLCFGR PLLM LL_RCC_PLL_ConfigDomain_SAI\n
4726 * PLLCFGR PLLN LL_RCC_PLL_ConfigDomain_SAI\n
4727 * PLLCFGR PLLR LL_RCC_PLL_ConfigDomain_SAI\n
4728 * DCKCFGR PLLDIVR LL_RCC_PLL_ConfigDomain_SAI
4729 * @param Source This parameter can be one of the following values:
4730 * @arg @ref LL_RCC_PLLSOURCE_HSI
4731 * @arg @ref LL_RCC_PLLSOURCE_HSE
4732 * @param PLLM This parameter can be one of the following values:
4733 * @arg @ref LL_RCC_PLLM_DIV_2
4734 * @arg @ref LL_RCC_PLLM_DIV_3
4735 * @arg @ref LL_RCC_PLLM_DIV_4
4736 * @arg @ref LL_RCC_PLLM_DIV_5
4737 * @arg @ref LL_RCC_PLLM_DIV_6
4738 * @arg @ref LL_RCC_PLLM_DIV_7
4739 * @arg @ref LL_RCC_PLLM_DIV_8
4740 * @arg @ref LL_RCC_PLLM_DIV_9
4741 * @arg @ref LL_RCC_PLLM_DIV_10
4742 * @arg @ref LL_RCC_PLLM_DIV_11
4743 * @arg @ref LL_RCC_PLLM_DIV_12
4744 * @arg @ref LL_RCC_PLLM_DIV_13
4745 * @arg @ref LL_RCC_PLLM_DIV_14
4746 * @arg @ref LL_RCC_PLLM_DIV_15
4747 * @arg @ref LL_RCC_PLLM_DIV_16
4748 * @arg @ref LL_RCC_PLLM_DIV_17
4749 * @arg @ref LL_RCC_PLLM_DIV_18
4750 * @arg @ref LL_RCC_PLLM_DIV_19
4751 * @arg @ref LL_RCC_PLLM_DIV_20
4752 * @arg @ref LL_RCC_PLLM_DIV_21
4753 * @arg @ref LL_RCC_PLLM_DIV_22
4754 * @arg @ref LL_RCC_PLLM_DIV_23
4755 * @arg @ref LL_RCC_PLLM_DIV_24
4756 * @arg @ref LL_RCC_PLLM_DIV_25
4757 * @arg @ref LL_RCC_PLLM_DIV_26
4758 * @arg @ref LL_RCC_PLLM_DIV_27
4759 * @arg @ref LL_RCC_PLLM_DIV_28
4760 * @arg @ref LL_RCC_PLLM_DIV_29
4761 * @arg @ref LL_RCC_PLLM_DIV_30
4762 * @arg @ref LL_RCC_PLLM_DIV_31
4763 * @arg @ref LL_RCC_PLLM_DIV_32
4764 * @arg @ref LL_RCC_PLLM_DIV_33
4765 * @arg @ref LL_RCC_PLLM_DIV_34
4766 * @arg @ref LL_RCC_PLLM_DIV_35
4767 * @arg @ref LL_RCC_PLLM_DIV_36
4768 * @arg @ref LL_RCC_PLLM_DIV_37
4769 * @arg @ref LL_RCC_PLLM_DIV_38
4770 * @arg @ref LL_RCC_PLLM_DIV_39
4771 * @arg @ref LL_RCC_PLLM_DIV_40
4772 * @arg @ref LL_RCC_PLLM_DIV_41
4773 * @arg @ref LL_RCC_PLLM_DIV_42
4774 * @arg @ref LL_RCC_PLLM_DIV_43
4775 * @arg @ref LL_RCC_PLLM_DIV_44
4776 * @arg @ref LL_RCC_PLLM_DIV_45
4777 * @arg @ref LL_RCC_PLLM_DIV_46
4778 * @arg @ref LL_RCC_PLLM_DIV_47
4779 * @arg @ref LL_RCC_PLLM_DIV_48
4780 * @arg @ref LL_RCC_PLLM_DIV_49
4781 * @arg @ref LL_RCC_PLLM_DIV_50
4782 * @arg @ref LL_RCC_PLLM_DIV_51
4783 * @arg @ref LL_RCC_PLLM_DIV_52
4784 * @arg @ref LL_RCC_PLLM_DIV_53
4785 * @arg @ref LL_RCC_PLLM_DIV_54
4786 * @arg @ref LL_RCC_PLLM_DIV_55
4787 * @arg @ref LL_RCC_PLLM_DIV_56
4788 * @arg @ref LL_RCC_PLLM_DIV_57
4789 * @arg @ref LL_RCC_PLLM_DIV_58
4790 * @arg @ref LL_RCC_PLLM_DIV_59
4791 * @arg @ref LL_RCC_PLLM_DIV_60
4792 * @arg @ref LL_RCC_PLLM_DIV_61
4793 * @arg @ref LL_RCC_PLLM_DIV_62
4794 * @arg @ref LL_RCC_PLLM_DIV_63
4795 * @param PLLN Between 50 and 432
4796 * @param PLLR This parameter can be one of the following values:
4797 * @arg @ref LL_RCC_PLLR_DIV_2
4798 * @arg @ref LL_RCC_PLLR_DIV_3
4799 * @arg @ref LL_RCC_PLLR_DIV_4
4800 * @arg @ref LL_RCC_PLLR_DIV_5
4801 * @arg @ref LL_RCC_PLLR_DIV_6
4802 * @arg @ref LL_RCC_PLLR_DIV_7
4803 * @param PLLDIVR This parameter can be one of the following values:
4804 * @arg @ref LL_RCC_PLLDIVR_DIV_1 (*)
4805 * @arg @ref LL_RCC_PLLDIVR_DIV_2 (*)
4806 * @arg @ref LL_RCC_PLLDIVR_DIV_3 (*)
4807 * @arg @ref LL_RCC_PLLDIVR_DIV_4 (*)
4808 * @arg @ref LL_RCC_PLLDIVR_DIV_5 (*)
4809 * @arg @ref LL_RCC_PLLDIVR_DIV_6 (*)
4810 * @arg @ref LL_RCC_PLLDIVR_DIV_7 (*)
4811 * @arg @ref LL_RCC_PLLDIVR_DIV_8 (*)
4812 * @arg @ref LL_RCC_PLLDIVR_DIV_9 (*)
4813 * @arg @ref LL_RCC_PLLDIVR_DIV_10 (*)
4814 * @arg @ref LL_RCC_PLLDIVR_DIV_11 (*)
4815 * @arg @ref LL_RCC_PLLDIVR_DIV_12 (*)
4816 * @arg @ref LL_RCC_PLLDIVR_DIV_13 (*)
4817 * @arg @ref LL_RCC_PLLDIVR_DIV_14 (*)
4818 * @arg @ref LL_RCC_PLLDIVR_DIV_15 (*)
4819 * @arg @ref LL_RCC_PLLDIVR_DIV_16 (*)
4820 * @arg @ref LL_RCC_PLLDIVR_DIV_17 (*)
4821 * @arg @ref LL_RCC_PLLDIVR_DIV_18 (*)
4822 * @arg @ref LL_RCC_PLLDIVR_DIV_19 (*)
4823 * @arg @ref LL_RCC_PLLDIVR_DIV_20 (*)
4824 * @arg @ref LL_RCC_PLLDIVR_DIV_21 (*)
4825 * @arg @ref LL_RCC_PLLDIVR_DIV_22 (*)
4826 * @arg @ref LL_RCC_PLLDIVR_DIV_23 (*)
4827 * @arg @ref LL_RCC_PLLDIVR_DIV_24 (*)
4828 * @arg @ref LL_RCC_PLLDIVR_DIV_25 (*)
4829 * @arg @ref LL_RCC_PLLDIVR_DIV_26 (*)
4830 * @arg @ref LL_RCC_PLLDIVR_DIV_27 (*)
4831 * @arg @ref LL_RCC_PLLDIVR_DIV_28 (*)
4832 * @arg @ref LL_RCC_PLLDIVR_DIV_29 (*)
4833 * @arg @ref LL_RCC_PLLDIVR_DIV_30 (*)
4834 * @arg @ref LL_RCC_PLLDIVR_DIV_31 (*)
4835 *
4836 * (*) value not defined in all devices.
4837 * @retval None
4838 */
4839 #if defined(RCC_DCKCFGR_PLLDIVR)
4840 __STATIC_INLINE void LL_RCC_PLL_ConfigDomain_SAI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR, uint32_t PLLDIVR)
4841 #else
4842 __STATIC_INLINE void LL_RCC_PLL_ConfigDomain_SAI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR)
4843 #endif /* RCC_DCKCFGR_PLLDIVR */
4844 {
4845 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLR,
4846 Source | PLLM | PLLN << RCC_PLLCFGR_PLLN_Pos | PLLR);
4847 #if defined(RCC_DCKCFGR_PLLDIVR)
4848 MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLDIVR, PLLDIVR);
4849 #endif /* RCC_DCKCFGR_PLLDIVR */
4850 }
4851 #endif /* SAI1 */
4852 #endif /* RCC_PLLCFGR_PLLR */
4853
4854 /**
4855 * @brief Configure PLL clock source
4856 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_SetMainSource
4857 * @param PLLSource This parameter can be one of the following values:
4858 * @arg @ref LL_RCC_PLLSOURCE_HSI
4859 * @arg @ref LL_RCC_PLLSOURCE_HSE
4860 * @retval None
4861 */
4862 __STATIC_INLINE void LL_RCC_PLL_SetMainSource(uint32_t PLLSource)
4863 {
4864 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, PLLSource);
4865 }
4866
4867 /**
4868 * @brief Get the oscillator used as PLL clock source.
4869 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_GetMainSource
4870 * @retval Returned value can be one of the following values:
4871 * @arg @ref LL_RCC_PLLSOURCE_HSI
4872 * @arg @ref LL_RCC_PLLSOURCE_HSE
4873 */
4874 __STATIC_INLINE uint32_t LL_RCC_PLL_GetMainSource(void)
4875 {
4876 return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC));
4877 }
4878
4879 /**
4880 * @brief Get Main PLL multiplication factor for VCO
4881 * @rmtoll PLLCFGR PLLN LL_RCC_PLL_GetN
4882 * @retval Between 50/192(*) and 432
4883 *
4884 * (*) value not defined in all devices.
4885 */
4886 __STATIC_INLINE uint32_t LL_RCC_PLL_GetN(void)
4887 {
4888 return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos);
4889 }
4890
4891 /**
4892 * @brief Get Main PLL division factor for PLLP
4893 * @rmtoll PLLCFGR PLLP LL_RCC_PLL_GetP
4894 * @retval Returned value can be one of the following values:
4895 * @arg @ref LL_RCC_PLLP_DIV_2
4896 * @arg @ref LL_RCC_PLLP_DIV_4
4897 * @arg @ref LL_RCC_PLLP_DIV_6
4898 * @arg @ref LL_RCC_PLLP_DIV_8
4899 */
4900 __STATIC_INLINE uint32_t LL_RCC_PLL_GetP(void)
4901 {
4902 return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLP));
4903 }
4904
4905 /**
4906 * @brief Get Main PLL division factor for PLLQ
4907 * @note used for PLL48MCLK selected for USB, RNG, SDIO (48 MHz clock)
4908 * @rmtoll PLLCFGR PLLQ LL_RCC_PLL_GetQ
4909 * @retval Returned value can be one of the following values:
4910 * @arg @ref LL_RCC_PLLQ_DIV_2
4911 * @arg @ref LL_RCC_PLLQ_DIV_3
4912 * @arg @ref LL_RCC_PLLQ_DIV_4
4913 * @arg @ref LL_RCC_PLLQ_DIV_5
4914 * @arg @ref LL_RCC_PLLQ_DIV_6
4915 * @arg @ref LL_RCC_PLLQ_DIV_7
4916 * @arg @ref LL_RCC_PLLQ_DIV_8
4917 * @arg @ref LL_RCC_PLLQ_DIV_9
4918 * @arg @ref LL_RCC_PLLQ_DIV_10
4919 * @arg @ref LL_RCC_PLLQ_DIV_11
4920 * @arg @ref LL_RCC_PLLQ_DIV_12
4921 * @arg @ref LL_RCC_PLLQ_DIV_13
4922 * @arg @ref LL_RCC_PLLQ_DIV_14
4923 * @arg @ref LL_RCC_PLLQ_DIV_15
4924 */
4925 __STATIC_INLINE uint32_t LL_RCC_PLL_GetQ(void)
4926 {
4927 return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQ));
4928 }
4929
4930 #if defined(RCC_PLLCFGR_PLLR)
4931 /**
4932 * @brief Get Main PLL division factor for PLLR
4933 * @note used for PLLCLK (system clock)
4934 * @rmtoll PLLCFGR PLLR LL_RCC_PLL_GetR
4935 * @retval Returned value can be one of the following values:
4936 * @arg @ref LL_RCC_PLLR_DIV_2
4937 * @arg @ref LL_RCC_PLLR_DIV_3
4938 * @arg @ref LL_RCC_PLLR_DIV_4
4939 * @arg @ref LL_RCC_PLLR_DIV_5
4940 * @arg @ref LL_RCC_PLLR_DIV_6
4941 * @arg @ref LL_RCC_PLLR_DIV_7
4942 */
4943 __STATIC_INLINE uint32_t LL_RCC_PLL_GetR(void)
4944 {
4945 return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLR));
4946 }
4947 #endif /* RCC_PLLCFGR_PLLR */
4948
4949 #if defined(RCC_DCKCFGR_PLLDIVR)
4950 /**
4951 * @brief Get Main PLL division factor for PLLDIVR
4952 * @note used for PLLSAICLK (SAI1 and SAI2 clock)
4953 * @rmtoll DCKCFGR PLLDIVR LL_RCC_PLL_GetDIVR
4954 * @retval Returned value can be one of the following values:
4955 * @arg @ref LL_RCC_PLLDIVR_DIV_1
4956 * @arg @ref LL_RCC_PLLDIVR_DIV_2
4957 * @arg @ref LL_RCC_PLLDIVR_DIV_3
4958 * @arg @ref LL_RCC_PLLDIVR_DIV_4
4959 * @arg @ref LL_RCC_PLLDIVR_DIV_5
4960 * @arg @ref LL_RCC_PLLDIVR_DIV_6
4961 * @arg @ref LL_RCC_PLLDIVR_DIV_7
4962 * @arg @ref LL_RCC_PLLDIVR_DIV_8
4963 * @arg @ref LL_RCC_PLLDIVR_DIV_9
4964 * @arg @ref LL_RCC_PLLDIVR_DIV_10
4965 * @arg @ref LL_RCC_PLLDIVR_DIV_11
4966 * @arg @ref LL_RCC_PLLDIVR_DIV_12
4967 * @arg @ref LL_RCC_PLLDIVR_DIV_13
4968 * @arg @ref LL_RCC_PLLDIVR_DIV_14
4969 * @arg @ref LL_RCC_PLLDIVR_DIV_15
4970 * @arg @ref LL_RCC_PLLDIVR_DIV_16
4971 * @arg @ref LL_RCC_PLLDIVR_DIV_17
4972 * @arg @ref LL_RCC_PLLDIVR_DIV_18
4973 * @arg @ref LL_RCC_PLLDIVR_DIV_19
4974 * @arg @ref LL_RCC_PLLDIVR_DIV_20
4975 * @arg @ref LL_RCC_PLLDIVR_DIV_21
4976 * @arg @ref LL_RCC_PLLDIVR_DIV_22
4977 * @arg @ref LL_RCC_PLLDIVR_DIV_23
4978 * @arg @ref LL_RCC_PLLDIVR_DIV_24
4979 * @arg @ref LL_RCC_PLLDIVR_DIV_25
4980 * @arg @ref LL_RCC_PLLDIVR_DIV_26
4981 * @arg @ref LL_RCC_PLLDIVR_DIV_27
4982 * @arg @ref LL_RCC_PLLDIVR_DIV_28
4983 * @arg @ref LL_RCC_PLLDIVR_DIV_29
4984 * @arg @ref LL_RCC_PLLDIVR_DIV_30
4985 * @arg @ref LL_RCC_PLLDIVR_DIV_31
4986 */
4987 __STATIC_INLINE uint32_t LL_RCC_PLL_GetDIVR(void)
4988 {
4989 return (uint32_t)(READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_PLLDIVR));
4990 }
4991 #endif /* RCC_DCKCFGR_PLLDIVR */
4992
4993 /**
4994 * @brief Get Division factor for the main PLL and other PLL
4995 * @rmtoll PLLCFGR PLLM LL_RCC_PLL_GetDivider
4996 * @retval Returned value can be one of the following values:
4997 * @arg @ref LL_RCC_PLLM_DIV_2
4998 * @arg @ref LL_RCC_PLLM_DIV_3
4999 * @arg @ref LL_RCC_PLLM_DIV_4
5000 * @arg @ref LL_RCC_PLLM_DIV_5
5001 * @arg @ref LL_RCC_PLLM_DIV_6
5002 * @arg @ref LL_RCC_PLLM_DIV_7
5003 * @arg @ref LL_RCC_PLLM_DIV_8
5004 * @arg @ref LL_RCC_PLLM_DIV_9
5005 * @arg @ref LL_RCC_PLLM_DIV_10
5006 * @arg @ref LL_RCC_PLLM_DIV_11
5007 * @arg @ref LL_RCC_PLLM_DIV_12
5008 * @arg @ref LL_RCC_PLLM_DIV_13
5009 * @arg @ref LL_RCC_PLLM_DIV_14
5010 * @arg @ref LL_RCC_PLLM_DIV_15
5011 * @arg @ref LL_RCC_PLLM_DIV_16
5012 * @arg @ref LL_RCC_PLLM_DIV_17
5013 * @arg @ref LL_RCC_PLLM_DIV_18
5014 * @arg @ref LL_RCC_PLLM_DIV_19
5015 * @arg @ref LL_RCC_PLLM_DIV_20
5016 * @arg @ref LL_RCC_PLLM_DIV_21
5017 * @arg @ref LL_RCC_PLLM_DIV_22
5018 * @arg @ref LL_RCC_PLLM_DIV_23
5019 * @arg @ref LL_RCC_PLLM_DIV_24
5020 * @arg @ref LL_RCC_PLLM_DIV_25
5021 * @arg @ref LL_RCC_PLLM_DIV_26
5022 * @arg @ref LL_RCC_PLLM_DIV_27
5023 * @arg @ref LL_RCC_PLLM_DIV_28
5024 * @arg @ref LL_RCC_PLLM_DIV_29
5025 * @arg @ref LL_RCC_PLLM_DIV_30
5026 * @arg @ref LL_RCC_PLLM_DIV_31
5027 * @arg @ref LL_RCC_PLLM_DIV_32
5028 * @arg @ref LL_RCC_PLLM_DIV_33
5029 * @arg @ref LL_RCC_PLLM_DIV_34
5030 * @arg @ref LL_RCC_PLLM_DIV_35
5031 * @arg @ref LL_RCC_PLLM_DIV_36
5032 * @arg @ref LL_RCC_PLLM_DIV_37
5033 * @arg @ref LL_RCC_PLLM_DIV_38
5034 * @arg @ref LL_RCC_PLLM_DIV_39
5035 * @arg @ref LL_RCC_PLLM_DIV_40
5036 * @arg @ref LL_RCC_PLLM_DIV_41
5037 * @arg @ref LL_RCC_PLLM_DIV_42
5038 * @arg @ref LL_RCC_PLLM_DIV_43
5039 * @arg @ref LL_RCC_PLLM_DIV_44
5040 * @arg @ref LL_RCC_PLLM_DIV_45
5041 * @arg @ref LL_RCC_PLLM_DIV_46
5042 * @arg @ref LL_RCC_PLLM_DIV_47
5043 * @arg @ref LL_RCC_PLLM_DIV_48
5044 * @arg @ref LL_RCC_PLLM_DIV_49
5045 * @arg @ref LL_RCC_PLLM_DIV_50
5046 * @arg @ref LL_RCC_PLLM_DIV_51
5047 * @arg @ref LL_RCC_PLLM_DIV_52
5048 * @arg @ref LL_RCC_PLLM_DIV_53
5049 * @arg @ref LL_RCC_PLLM_DIV_54
5050 * @arg @ref LL_RCC_PLLM_DIV_55
5051 * @arg @ref LL_RCC_PLLM_DIV_56
5052 * @arg @ref LL_RCC_PLLM_DIV_57
5053 * @arg @ref LL_RCC_PLLM_DIV_58
5054 * @arg @ref LL_RCC_PLLM_DIV_59
5055 * @arg @ref LL_RCC_PLLM_DIV_60
5056 * @arg @ref LL_RCC_PLLM_DIV_61
5057 * @arg @ref LL_RCC_PLLM_DIV_62
5058 * @arg @ref LL_RCC_PLLM_DIV_63
5059 */
5060 __STATIC_INLINE uint32_t LL_RCC_PLL_GetDivider(void)
5061 {
5062 return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM));
5063 }
5064
5065 /**
5066 * @brief Configure Spread Spectrum used for PLL
5067 * @note These bits must be written before enabling PLL
5068 * @rmtoll SSCGR MODPER LL_RCC_PLL_ConfigSpreadSpectrum\n
5069 * SSCGR INCSTEP LL_RCC_PLL_ConfigSpreadSpectrum\n
5070 * SSCGR SPREADSEL LL_RCC_PLL_ConfigSpreadSpectrum
5071 * @param Mod Between Min_Data=0 and Max_Data=8191
5072 * @param Inc Between Min_Data=0 and Max_Data=32767
5073 * @param Sel This parameter can be one of the following values:
5074 * @arg @ref LL_RCC_SPREAD_SELECT_CENTER
5075 * @arg @ref LL_RCC_SPREAD_SELECT_DOWN
5076 * @retval None
5077 */
5078 __STATIC_INLINE void LL_RCC_PLL_ConfigSpreadSpectrum(uint32_t Mod, uint32_t Inc, uint32_t Sel)
5079 {
5080 MODIFY_REG(RCC->SSCGR, RCC_SSCGR_MODPER | RCC_SSCGR_INCSTEP | RCC_SSCGR_SPREADSEL, Mod | (Inc << RCC_SSCGR_INCSTEP_Pos) | Sel);
5081 }
5082
5083 /**
5084 * @brief Get Spread Spectrum Modulation Period for PLL
5085 * @rmtoll SSCGR MODPER LL_RCC_PLL_GetPeriodModulation
5086 * @retval Between Min_Data=0 and Max_Data=8191
5087 */
5088 __STATIC_INLINE uint32_t LL_RCC_PLL_GetPeriodModulation(void)
5089 {
5090 return (uint32_t)(READ_BIT(RCC->SSCGR, RCC_SSCGR_MODPER));
5091 }
5092
5093 /**
5094 * @brief Get Spread Spectrum Incrementation Step for PLL
5095 * @note Must be written before enabling PLL
5096 * @rmtoll SSCGR INCSTEP LL_RCC_PLL_GetStepIncrementation
5097 * @retval Between Min_Data=0 and Max_Data=32767
5098 */
5099 __STATIC_INLINE uint32_t LL_RCC_PLL_GetStepIncrementation(void)
5100 {
5101 return (uint32_t)(READ_BIT(RCC->SSCGR, RCC_SSCGR_INCSTEP) >> RCC_SSCGR_INCSTEP_Pos);
5102 }
5103
5104 /**
5105 * @brief Get Spread Spectrum Selection for PLL
5106 * @note Must be written before enabling PLL
5107 * @rmtoll SSCGR SPREADSEL LL_RCC_PLL_GetSpreadSelection
5108 * @retval Returned value can be one of the following values:
5109 * @arg @ref LL_RCC_SPREAD_SELECT_CENTER
5110 * @arg @ref LL_RCC_SPREAD_SELECT_DOWN
5111 */
5112 __STATIC_INLINE uint32_t LL_RCC_PLL_GetSpreadSelection(void)
5113 {
5114 return (uint32_t)(READ_BIT(RCC->SSCGR, RCC_SSCGR_SPREADSEL));
5115 }
5116
5117 /**
5118 * @brief Enable Spread Spectrum for PLL.
5119 * @rmtoll SSCGR SSCGEN LL_RCC_PLL_SpreadSpectrum_Enable
5120 * @retval None
5121 */
5122 __STATIC_INLINE void LL_RCC_PLL_SpreadSpectrum_Enable(void)
5123 {
5124 SET_BIT(RCC->SSCGR, RCC_SSCGR_SSCGEN);
5125 }
5126
5127 /**
5128 * @brief Disable Spread Spectrum for PLL.
5129 * @rmtoll SSCGR SSCGEN LL_RCC_PLL_SpreadSpectrum_Disable
5130 * @retval None
5131 */
5132 __STATIC_INLINE void LL_RCC_PLL_SpreadSpectrum_Disable(void)
5133 {
5134 CLEAR_BIT(RCC->SSCGR, RCC_SSCGR_SSCGEN);
5135 }
5136
5137 /**
5138 * @}
5139 */
5140
5141 #if defined(RCC_PLLI2S_SUPPORT)
5142 /** @defgroup RCC_LL_EF_PLLI2S PLLI2S
5143 * @{
5144 */
5145
5146 /**
5147 * @brief Enable PLLI2S
5148 * @rmtoll CR PLLI2SON LL_RCC_PLLI2S_Enable
5149 * @retval None
5150 */
5151 __STATIC_INLINE void LL_RCC_PLLI2S_Enable(void)
5152 {
5153 SET_BIT(RCC->CR, RCC_CR_PLLI2SON);
5154 }
5155
5156 /**
5157 * @brief Disable PLLI2S
5158 * @rmtoll CR PLLI2SON LL_RCC_PLLI2S_Disable
5159 * @retval None
5160 */
5161 __STATIC_INLINE void LL_RCC_PLLI2S_Disable(void)
5162 {
5163 CLEAR_BIT(RCC->CR, RCC_CR_PLLI2SON);
5164 }
5165
5166 /**
5167 * @brief Check if PLLI2S Ready
5168 * @rmtoll CR PLLI2SRDY LL_RCC_PLLI2S_IsReady
5169 * @retval State of bit (1 or 0).
5170 */
5171 __STATIC_INLINE uint32_t LL_RCC_PLLI2S_IsReady(void)
5172 {
5173 return (READ_BIT(RCC->CR, RCC_CR_PLLI2SRDY) == (RCC_CR_PLLI2SRDY));
5174 }
5175
5176 #if (defined(RCC_DCKCFGR_PLLI2SDIVQ) || defined(RCC_DCKCFGR_PLLI2SDIVR))
5177 /**
5178 * @brief Configure PLLI2S used for SAI domain clock
5179 * @note PLL Source and PLLM Divider can be written only when PLL,
5180 * PLLI2S and PLLSAI(*) are disabled
5181 * @note PLLN/PLLQ/PLLR can be written only when PLLI2S is disabled
5182 * @note This can be selected for SAI
5183 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLLI2S_ConfigDomain_SAI\n
5184 * PLLI2SCFGR PLLI2SSRC LL_RCC_PLLI2S_ConfigDomain_SAI\n
5185 * PLLCFGR PLLM LL_RCC_PLLI2S_ConfigDomain_SAI\n
5186 * PLLI2SCFGR PLLI2SM LL_RCC_PLLI2S_ConfigDomain_SAI\n
5187 * PLLI2SCFGR PLLI2SN LL_RCC_PLLI2S_ConfigDomain_SAI\n
5188 * PLLI2SCFGR PLLI2SQ LL_RCC_PLLI2S_ConfigDomain_SAI\n
5189 * PLLI2SCFGR PLLI2SR LL_RCC_PLLI2S_ConfigDomain_SAI\n
5190 * DCKCFGR PLLI2SDIVQ LL_RCC_PLLI2S_ConfigDomain_SAI\n
5191 * DCKCFGR PLLI2SDIVR LL_RCC_PLLI2S_ConfigDomain_SAI
5192 * @param Source This parameter can be one of the following values:
5193 * @arg @ref LL_RCC_PLLSOURCE_HSI
5194 * @arg @ref LL_RCC_PLLSOURCE_HSE
5195 * @arg @ref LL_RCC_PLLI2SSOURCE_PIN (*)
5196 *
5197 * (*) value not defined in all devices.
5198 * @param PLLM This parameter can be one of the following values:
5199 * @arg @ref LL_RCC_PLLI2SM_DIV_2
5200 * @arg @ref LL_RCC_PLLI2SM_DIV_3
5201 * @arg @ref LL_RCC_PLLI2SM_DIV_4
5202 * @arg @ref LL_RCC_PLLI2SM_DIV_5
5203 * @arg @ref LL_RCC_PLLI2SM_DIV_6
5204 * @arg @ref LL_RCC_PLLI2SM_DIV_7
5205 * @arg @ref LL_RCC_PLLI2SM_DIV_8
5206 * @arg @ref LL_RCC_PLLI2SM_DIV_9
5207 * @arg @ref LL_RCC_PLLI2SM_DIV_10
5208 * @arg @ref LL_RCC_PLLI2SM_DIV_11
5209 * @arg @ref LL_RCC_PLLI2SM_DIV_12
5210 * @arg @ref LL_RCC_PLLI2SM_DIV_13
5211 * @arg @ref LL_RCC_PLLI2SM_DIV_14
5212 * @arg @ref LL_RCC_PLLI2SM_DIV_15
5213 * @arg @ref LL_RCC_PLLI2SM_DIV_16
5214 * @arg @ref LL_RCC_PLLI2SM_DIV_17
5215 * @arg @ref LL_RCC_PLLI2SM_DIV_18
5216 * @arg @ref LL_RCC_PLLI2SM_DIV_19
5217 * @arg @ref LL_RCC_PLLI2SM_DIV_20
5218 * @arg @ref LL_RCC_PLLI2SM_DIV_21
5219 * @arg @ref LL_RCC_PLLI2SM_DIV_22
5220 * @arg @ref LL_RCC_PLLI2SM_DIV_23
5221 * @arg @ref LL_RCC_PLLI2SM_DIV_24
5222 * @arg @ref LL_RCC_PLLI2SM_DIV_25
5223 * @arg @ref LL_RCC_PLLI2SM_DIV_26
5224 * @arg @ref LL_RCC_PLLI2SM_DIV_27
5225 * @arg @ref LL_RCC_PLLI2SM_DIV_28
5226 * @arg @ref LL_RCC_PLLI2SM_DIV_29
5227 * @arg @ref LL_RCC_PLLI2SM_DIV_30
5228 * @arg @ref LL_RCC_PLLI2SM_DIV_31
5229 * @arg @ref LL_RCC_PLLI2SM_DIV_32
5230 * @arg @ref LL_RCC_PLLI2SM_DIV_33
5231 * @arg @ref LL_RCC_PLLI2SM_DIV_34
5232 * @arg @ref LL_RCC_PLLI2SM_DIV_35
5233 * @arg @ref LL_RCC_PLLI2SM_DIV_36
5234 * @arg @ref LL_RCC_PLLI2SM_DIV_37
5235 * @arg @ref LL_RCC_PLLI2SM_DIV_38
5236 * @arg @ref LL_RCC_PLLI2SM_DIV_39
5237 * @arg @ref LL_RCC_PLLI2SM_DIV_40
5238 * @arg @ref LL_RCC_PLLI2SM_DIV_41
5239 * @arg @ref LL_RCC_PLLI2SM_DIV_42
5240 * @arg @ref LL_RCC_PLLI2SM_DIV_43
5241 * @arg @ref LL_RCC_PLLI2SM_DIV_44
5242 * @arg @ref LL_RCC_PLLI2SM_DIV_45
5243 * @arg @ref LL_RCC_PLLI2SM_DIV_46
5244 * @arg @ref LL_RCC_PLLI2SM_DIV_47
5245 * @arg @ref LL_RCC_PLLI2SM_DIV_48
5246 * @arg @ref LL_RCC_PLLI2SM_DIV_49
5247 * @arg @ref LL_RCC_PLLI2SM_DIV_50
5248 * @arg @ref LL_RCC_PLLI2SM_DIV_51
5249 * @arg @ref LL_RCC_PLLI2SM_DIV_52
5250 * @arg @ref LL_RCC_PLLI2SM_DIV_53
5251 * @arg @ref LL_RCC_PLLI2SM_DIV_54
5252 * @arg @ref LL_RCC_PLLI2SM_DIV_55
5253 * @arg @ref LL_RCC_PLLI2SM_DIV_56
5254 * @arg @ref LL_RCC_PLLI2SM_DIV_57
5255 * @arg @ref LL_RCC_PLLI2SM_DIV_58
5256 * @arg @ref LL_RCC_PLLI2SM_DIV_59
5257 * @arg @ref LL_RCC_PLLI2SM_DIV_60
5258 * @arg @ref LL_RCC_PLLI2SM_DIV_61
5259 * @arg @ref LL_RCC_PLLI2SM_DIV_62
5260 * @arg @ref LL_RCC_PLLI2SM_DIV_63
5261 * @param PLLN Between 50/192(*) and 432
5262 *
5263 * (*) value not defined in all devices.
5264 * @param PLLQ_R This parameter can be one of the following values:
5265 * @arg @ref LL_RCC_PLLI2SQ_DIV_2 (*)
5266 * @arg @ref LL_RCC_PLLI2SQ_DIV_3 (*)
5267 * @arg @ref LL_RCC_PLLI2SQ_DIV_4 (*)
5268 * @arg @ref LL_RCC_PLLI2SQ_DIV_5 (*)
5269 * @arg @ref LL_RCC_PLLI2SQ_DIV_6 (*)
5270 * @arg @ref LL_RCC_PLLI2SQ_DIV_7 (*)
5271 * @arg @ref LL_RCC_PLLI2SQ_DIV_8 (*)
5272 * @arg @ref LL_RCC_PLLI2SQ_DIV_9 (*)
5273 * @arg @ref LL_RCC_PLLI2SQ_DIV_10 (*)
5274 * @arg @ref LL_RCC_PLLI2SQ_DIV_11 (*)
5275 * @arg @ref LL_RCC_PLLI2SQ_DIV_12 (*)
5276 * @arg @ref LL_RCC_PLLI2SQ_DIV_13 (*)
5277 * @arg @ref LL_RCC_PLLI2SQ_DIV_14 (*)
5278 * @arg @ref LL_RCC_PLLI2SQ_DIV_15 (*)
5279 * @arg @ref LL_RCC_PLLI2SR_DIV_2 (*)
5280 * @arg @ref LL_RCC_PLLI2SR_DIV_3 (*)
5281 * @arg @ref LL_RCC_PLLI2SR_DIV_4 (*)
5282 * @arg @ref LL_RCC_PLLI2SR_DIV_5 (*)
5283 * @arg @ref LL_RCC_PLLI2SR_DIV_6 (*)
5284 * @arg @ref LL_RCC_PLLI2SR_DIV_7 (*)
5285 *
5286 * (*) value not defined in all devices.
5287 * @param PLLDIVQ_R This parameter can be one of the following values:
5288 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_1 (*)
5289 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_2 (*)
5290 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_3 (*)
5291 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_4 (*)
5292 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_5 (*)
5293 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_6 (*)
5294 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_7 (*)
5295 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_8 (*)
5296 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_9 (*)
5297 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_10 (*)
5298 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_11 (*)
5299 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_12 (*)
5300 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_13 (*)
5301 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_14 (*)
5302 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_15 (*)
5303 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_16 (*)
5304 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_17 (*)
5305 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_18 (*)
5306 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_19 (*)
5307 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_20 (*)
5308 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_21 (*)
5309 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_22 (*)
5310 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_23 (*)
5311 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_24 (*)
5312 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_25 (*)
5313 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_26 (*)
5314 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_27 (*)
5315 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_28 (*)
5316 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_29 (*)
5317 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_30 (*)
5318 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_31 (*)
5319 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_32 (*)
5320 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_1 (*)
5321 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_2 (*)
5322 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_3 (*)
5323 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_4 (*)
5324 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_5 (*)
5325 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_6 (*)
5326 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_7 (*)
5327 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_8 (*)
5328 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_9 (*)
5329 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_10 (*)
5330 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_11 (*)
5331 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_12 (*)
5332 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_13 (*)
5333 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_14 (*)
5334 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_15 (*)
5335 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_16 (*)
5336 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_17 (*)
5337 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_18 (*)
5338 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_19 (*)
5339 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_20 (*)
5340 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_21 (*)
5341 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_22 (*)
5342 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_23 (*)
5343 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_24 (*)
5344 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_25 (*)
5345 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_26 (*)
5346 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_27 (*)
5347 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_28 (*)
5348 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_29 (*)
5349 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_30 (*)
5350 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_31 (*)
5351 *
5352 * (*) value not defined in all devices.
5353 * @retval None
5354 */
5355 __STATIC_INLINE void LL_RCC_PLLI2S_ConfigDomain_SAI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLQ_R, uint32_t PLLDIVQ_R)
5356 {
5357 register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&RCC->PLLCFGR) + (Source & 0x80U)));
5358 MODIFY_REG(*pReg, RCC_PLLCFGR_PLLSRC, (Source & (~0x80U)));
5359 #if defined(RCC_PLLI2SCFGR_PLLI2SM)
5360 MODIFY_REG(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SM, PLLM);
5361 #else
5362 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLM, PLLM);
5363 #endif /* RCC_PLLI2SCFGR_PLLI2SM */
5364 MODIFY_REG(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SN, PLLN << RCC_PLLI2SCFGR_PLLI2SN_Pos);
5365 #if defined(RCC_DCKCFGR_PLLI2SDIVQ)
5366 MODIFY_REG(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SQ, PLLQ_R);
5367 MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLI2SDIVQ, PLLDIVQ_R);
5368 #else
5369 MODIFY_REG(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SR, PLLQ_R);
5370 MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLI2SDIVR, PLLDIVQ_R);
5371 #endif /* RCC_DCKCFGR_PLLI2SDIVQ */
5372 }
5373 #endif /* RCC_DCKCFGR_PLLI2SDIVQ && RCC_DCKCFGR_PLLI2SDIVR */
5374
5375 #if defined(RCC_PLLI2SCFGR_PLLI2SQ) && !defined(RCC_DCKCFGR_PLLI2SDIVQ)
5376 /**
5377 * @brief Configure PLLI2S used for 48Mhz domain clock
5378 * @note PLL Source and PLLM Divider can be written only when PLL,
5379 * PLLI2S and PLLSAI(*) are disabled
5380 * @note PLLN/PLLQ can be written only when PLLI2S is disabled
5381 * @note This can be selected for RNG, USB, SDIO
5382 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLLI2S_ConfigDomain_48M\n
5383 * PLLI2SCFGR PLLI2SSRC LL_RCC_PLLI2S_ConfigDomain_48M\n
5384 * PLLCFGR PLLM LL_RCC_PLLI2S_ConfigDomain_48M\n
5385 * PLLI2SCFGR PLLI2SM LL_RCC_PLLI2S_ConfigDomain_48M\n
5386 * PLLI2SCFGR PLLI2SN LL_RCC_PLLI2S_ConfigDomain_48M\n
5387 * PLLI2SCFGR PLLI2SQ LL_RCC_PLLI2S_ConfigDomain_48M
5388 * @param Source This parameter can be one of the following values:
5389 * @arg @ref LL_RCC_PLLSOURCE_HSI
5390 * @arg @ref LL_RCC_PLLSOURCE_HSE
5391 * @arg @ref LL_RCC_PLLI2SSOURCE_PIN (*)
5392 *
5393 * (*) value not defined in all devices.
5394 * @param PLLM This parameter can be one of the following values:
5395 * @arg @ref LL_RCC_PLLI2SM_DIV_2
5396 * @arg @ref LL_RCC_PLLI2SM_DIV_3
5397 * @arg @ref LL_RCC_PLLI2SM_DIV_4
5398 * @arg @ref LL_RCC_PLLI2SM_DIV_5
5399 * @arg @ref LL_RCC_PLLI2SM_DIV_6
5400 * @arg @ref LL_RCC_PLLI2SM_DIV_7
5401 * @arg @ref LL_RCC_PLLI2SM_DIV_8
5402 * @arg @ref LL_RCC_PLLI2SM_DIV_9
5403 * @arg @ref LL_RCC_PLLI2SM_DIV_10
5404 * @arg @ref LL_RCC_PLLI2SM_DIV_11
5405 * @arg @ref LL_RCC_PLLI2SM_DIV_12
5406 * @arg @ref LL_RCC_PLLI2SM_DIV_13
5407 * @arg @ref LL_RCC_PLLI2SM_DIV_14
5408 * @arg @ref LL_RCC_PLLI2SM_DIV_15
5409 * @arg @ref LL_RCC_PLLI2SM_DIV_16
5410 * @arg @ref LL_RCC_PLLI2SM_DIV_17
5411 * @arg @ref LL_RCC_PLLI2SM_DIV_18
5412 * @arg @ref LL_RCC_PLLI2SM_DIV_19
5413 * @arg @ref LL_RCC_PLLI2SM_DIV_20
5414 * @arg @ref LL_RCC_PLLI2SM_DIV_21
5415 * @arg @ref LL_RCC_PLLI2SM_DIV_22
5416 * @arg @ref LL_RCC_PLLI2SM_DIV_23
5417 * @arg @ref LL_RCC_PLLI2SM_DIV_24
5418 * @arg @ref LL_RCC_PLLI2SM_DIV_25
5419 * @arg @ref LL_RCC_PLLI2SM_DIV_26
5420 * @arg @ref LL_RCC_PLLI2SM_DIV_27
5421 * @arg @ref LL_RCC_PLLI2SM_DIV_28
5422 * @arg @ref LL_RCC_PLLI2SM_DIV_29
5423 * @arg @ref LL_RCC_PLLI2SM_DIV_30
5424 * @arg @ref LL_RCC_PLLI2SM_DIV_31
5425 * @arg @ref LL_RCC_PLLI2SM_DIV_32
5426 * @arg @ref LL_RCC_PLLI2SM_DIV_33
5427 * @arg @ref LL_RCC_PLLI2SM_DIV_34
5428 * @arg @ref LL_RCC_PLLI2SM_DIV_35
5429 * @arg @ref LL_RCC_PLLI2SM_DIV_36
5430 * @arg @ref LL_RCC_PLLI2SM_DIV_37
5431 * @arg @ref LL_RCC_PLLI2SM_DIV_38
5432 * @arg @ref LL_RCC_PLLI2SM_DIV_39
5433 * @arg @ref LL_RCC_PLLI2SM_DIV_40
5434 * @arg @ref LL_RCC_PLLI2SM_DIV_41
5435 * @arg @ref LL_RCC_PLLI2SM_DIV_42
5436 * @arg @ref LL_RCC_PLLI2SM_DIV_43
5437 * @arg @ref LL_RCC_PLLI2SM_DIV_44
5438 * @arg @ref LL_RCC_PLLI2SM_DIV_45
5439 * @arg @ref LL_RCC_PLLI2SM_DIV_46
5440 * @arg @ref LL_RCC_PLLI2SM_DIV_47
5441 * @arg @ref LL_RCC_PLLI2SM_DIV_48
5442 * @arg @ref LL_RCC_PLLI2SM_DIV_49
5443 * @arg @ref LL_RCC_PLLI2SM_DIV_50
5444 * @arg @ref LL_RCC_PLLI2SM_DIV_51
5445 * @arg @ref LL_RCC_PLLI2SM_DIV_52
5446 * @arg @ref LL_RCC_PLLI2SM_DIV_53
5447 * @arg @ref LL_RCC_PLLI2SM_DIV_54
5448 * @arg @ref LL_RCC_PLLI2SM_DIV_55
5449 * @arg @ref LL_RCC_PLLI2SM_DIV_56
5450 * @arg @ref LL_RCC_PLLI2SM_DIV_57
5451 * @arg @ref LL_RCC_PLLI2SM_DIV_58
5452 * @arg @ref LL_RCC_PLLI2SM_DIV_59
5453 * @arg @ref LL_RCC_PLLI2SM_DIV_60
5454 * @arg @ref LL_RCC_PLLI2SM_DIV_61
5455 * @arg @ref LL_RCC_PLLI2SM_DIV_62
5456 * @arg @ref LL_RCC_PLLI2SM_DIV_63
5457 * @param PLLN Between 50 and 432
5458 * @param PLLQ This parameter can be one of the following values:
5459 * @arg @ref LL_RCC_PLLI2SQ_DIV_2
5460 * @arg @ref LL_RCC_PLLI2SQ_DIV_3
5461 * @arg @ref LL_RCC_PLLI2SQ_DIV_4
5462 * @arg @ref LL_RCC_PLLI2SQ_DIV_5
5463 * @arg @ref LL_RCC_PLLI2SQ_DIV_6
5464 * @arg @ref LL_RCC_PLLI2SQ_DIV_7
5465 * @arg @ref LL_RCC_PLLI2SQ_DIV_8
5466 * @arg @ref LL_RCC_PLLI2SQ_DIV_9
5467 * @arg @ref LL_RCC_PLLI2SQ_DIV_10
5468 * @arg @ref LL_RCC_PLLI2SQ_DIV_11
5469 * @arg @ref LL_RCC_PLLI2SQ_DIV_12
5470 * @arg @ref LL_RCC_PLLI2SQ_DIV_13
5471 * @arg @ref LL_RCC_PLLI2SQ_DIV_14
5472 * @arg @ref LL_RCC_PLLI2SQ_DIV_15
5473 * @retval None
5474 */
5475 __STATIC_INLINE void LL_RCC_PLLI2S_ConfigDomain_48M(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLQ)
5476 {
5477 register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&RCC->PLLCFGR) + (Source & 0x80U)));
5478 MODIFY_REG(*pReg, RCC_PLLCFGR_PLLSRC, (Source & (~0x80U)));
5479 #if defined(RCC_PLLI2SCFGR_PLLI2SM)
5480 MODIFY_REG(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SM, PLLM);
5481 #else
5482 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLM, PLLM);
5483 #endif /* RCC_PLLI2SCFGR_PLLI2SM */
5484 MODIFY_REG(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SN | RCC_PLLI2SCFGR_PLLI2SQ, PLLN << RCC_PLLI2SCFGR_PLLI2SN_Pos | PLLQ);
5485 }
5486 #endif /* RCC_PLLI2SCFGR_PLLI2SQ && !RCC_DCKCFGR_PLLI2SDIVQ */
5487
5488 #if defined(SPDIFRX)
5489 /**
5490 * @brief Configure PLLI2S used for SPDIFRX domain clock
5491 * @note PLL Source and PLLM Divider can be written only when PLL,
5492 * PLLI2S and PLLSAI(*) are disabled
5493 * @note PLLN/PLLP can be written only when PLLI2S is disabled
5494 * @note This can be selected for SPDIFRX
5495 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLLI2S_ConfigDomain_SPDIFRX\n
5496 * PLLCFGR PLLM LL_RCC_PLLI2S_ConfigDomain_SPDIFRX\n
5497 * PLLI2SCFGR PLLI2SM LL_RCC_PLLI2S_ConfigDomain_SPDIFRX\n
5498 * PLLI2SCFGR PLLI2SN LL_RCC_PLLI2S_ConfigDomain_SPDIFRX\n
5499 * PLLI2SCFGR PLLI2SP LL_RCC_PLLI2S_ConfigDomain_SPDIFRX
5500 * @param Source This parameter can be one of the following values:
5501 * @arg @ref LL_RCC_PLLSOURCE_HSI
5502 * @arg @ref LL_RCC_PLLSOURCE_HSE
5503 * @param PLLM This parameter can be one of the following values:
5504 * @arg @ref LL_RCC_PLLI2SM_DIV_2
5505 * @arg @ref LL_RCC_PLLI2SM_DIV_3
5506 * @arg @ref LL_RCC_PLLI2SM_DIV_4
5507 * @arg @ref LL_RCC_PLLI2SM_DIV_5
5508 * @arg @ref LL_RCC_PLLI2SM_DIV_6
5509 * @arg @ref LL_RCC_PLLI2SM_DIV_7
5510 * @arg @ref LL_RCC_PLLI2SM_DIV_8
5511 * @arg @ref LL_RCC_PLLI2SM_DIV_9
5512 * @arg @ref LL_RCC_PLLI2SM_DIV_10
5513 * @arg @ref LL_RCC_PLLI2SM_DIV_11
5514 * @arg @ref LL_RCC_PLLI2SM_DIV_12
5515 * @arg @ref LL_RCC_PLLI2SM_DIV_13
5516 * @arg @ref LL_RCC_PLLI2SM_DIV_14
5517 * @arg @ref LL_RCC_PLLI2SM_DIV_15
5518 * @arg @ref LL_RCC_PLLI2SM_DIV_16
5519 * @arg @ref LL_RCC_PLLI2SM_DIV_17
5520 * @arg @ref LL_RCC_PLLI2SM_DIV_18
5521 * @arg @ref LL_RCC_PLLI2SM_DIV_19
5522 * @arg @ref LL_RCC_PLLI2SM_DIV_20
5523 * @arg @ref LL_RCC_PLLI2SM_DIV_21
5524 * @arg @ref LL_RCC_PLLI2SM_DIV_22
5525 * @arg @ref LL_RCC_PLLI2SM_DIV_23
5526 * @arg @ref LL_RCC_PLLI2SM_DIV_24
5527 * @arg @ref LL_RCC_PLLI2SM_DIV_25
5528 * @arg @ref LL_RCC_PLLI2SM_DIV_26
5529 * @arg @ref LL_RCC_PLLI2SM_DIV_27
5530 * @arg @ref LL_RCC_PLLI2SM_DIV_28
5531 * @arg @ref LL_RCC_PLLI2SM_DIV_29
5532 * @arg @ref LL_RCC_PLLI2SM_DIV_30
5533 * @arg @ref LL_RCC_PLLI2SM_DIV_31
5534 * @arg @ref LL_RCC_PLLI2SM_DIV_32
5535 * @arg @ref LL_RCC_PLLI2SM_DIV_33
5536 * @arg @ref LL_RCC_PLLI2SM_DIV_34
5537 * @arg @ref LL_RCC_PLLI2SM_DIV_35
5538 * @arg @ref LL_RCC_PLLI2SM_DIV_36
5539 * @arg @ref LL_RCC_PLLI2SM_DIV_37
5540 * @arg @ref LL_RCC_PLLI2SM_DIV_38
5541 * @arg @ref LL_RCC_PLLI2SM_DIV_39
5542 * @arg @ref LL_RCC_PLLI2SM_DIV_40
5543 * @arg @ref LL_RCC_PLLI2SM_DIV_41
5544 * @arg @ref LL_RCC_PLLI2SM_DIV_42
5545 * @arg @ref LL_RCC_PLLI2SM_DIV_43
5546 * @arg @ref LL_RCC_PLLI2SM_DIV_44
5547 * @arg @ref LL_RCC_PLLI2SM_DIV_45
5548 * @arg @ref LL_RCC_PLLI2SM_DIV_46
5549 * @arg @ref LL_RCC_PLLI2SM_DIV_47
5550 * @arg @ref LL_RCC_PLLI2SM_DIV_48
5551 * @arg @ref LL_RCC_PLLI2SM_DIV_49
5552 * @arg @ref LL_RCC_PLLI2SM_DIV_50
5553 * @arg @ref LL_RCC_PLLI2SM_DIV_51
5554 * @arg @ref LL_RCC_PLLI2SM_DIV_52
5555 * @arg @ref LL_RCC_PLLI2SM_DIV_53
5556 * @arg @ref LL_RCC_PLLI2SM_DIV_54
5557 * @arg @ref LL_RCC_PLLI2SM_DIV_55
5558 * @arg @ref LL_RCC_PLLI2SM_DIV_56
5559 * @arg @ref LL_RCC_PLLI2SM_DIV_57
5560 * @arg @ref LL_RCC_PLLI2SM_DIV_58
5561 * @arg @ref LL_RCC_PLLI2SM_DIV_59
5562 * @arg @ref LL_RCC_PLLI2SM_DIV_60
5563 * @arg @ref LL_RCC_PLLI2SM_DIV_61
5564 * @arg @ref LL_RCC_PLLI2SM_DIV_62
5565 * @arg @ref LL_RCC_PLLI2SM_DIV_63
5566 * @param PLLN Between 50 and 432
5567 * @param PLLP This parameter can be one of the following values:
5568 * @arg @ref LL_RCC_PLLI2SP_DIV_2
5569 * @arg @ref LL_RCC_PLLI2SP_DIV_4
5570 * @arg @ref LL_RCC_PLLI2SP_DIV_6
5571 * @arg @ref LL_RCC_PLLI2SP_DIV_8
5572 * @retval None
5573 */
5574 __STATIC_INLINE void LL_RCC_PLLI2S_ConfigDomain_SPDIFRX(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP)
5575 {
5576 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, Source);
5577 #if defined(RCC_PLLI2SCFGR_PLLI2SM)
5578 MODIFY_REG(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SM, PLLM);
5579 #else
5580 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLM, PLLM);
5581 #endif /* RCC_PLLI2SCFGR_PLLI2SM */
5582 MODIFY_REG(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SN | RCC_PLLI2SCFGR_PLLI2SP, PLLN << RCC_PLLI2SCFGR_PLLI2SN_Pos | PLLP);
5583 }
5584 #endif /* SPDIFRX */
5585
5586 /**
5587 * @brief Configure PLLI2S used for I2S1 domain clock
5588 * @note PLL Source and PLLM Divider can be written only when PLL,
5589 * PLLI2S and PLLSAI(*) are disabled
5590 * @note PLLN/PLLR can be written only when PLLI2S is disabled
5591 * @note This can be selected for I2S
5592 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLLI2S_ConfigDomain_I2S\n
5593 * PLLCFGR PLLM LL_RCC_PLLI2S_ConfigDomain_I2S\n
5594 * PLLI2SCFGR PLLI2SSRC LL_RCC_PLLI2S_ConfigDomain_I2S\n
5595 * PLLI2SCFGR PLLI2SM LL_RCC_PLLI2S_ConfigDomain_I2S\n
5596 * PLLI2SCFGR PLLI2SN LL_RCC_PLLI2S_ConfigDomain_I2S\n
5597 * PLLI2SCFGR PLLI2SR LL_RCC_PLLI2S_ConfigDomain_I2S
5598 * @param Source This parameter can be one of the following values:
5599 * @arg @ref LL_RCC_PLLSOURCE_HSI
5600 * @arg @ref LL_RCC_PLLSOURCE_HSE
5601 * @arg @ref LL_RCC_PLLI2SSOURCE_PIN (*)
5602 *
5603 * (*) value not defined in all devices.
5604 * @param PLLM This parameter can be one of the following values:
5605 * @arg @ref LL_RCC_PLLI2SM_DIV_2
5606 * @arg @ref LL_RCC_PLLI2SM_DIV_3
5607 * @arg @ref LL_RCC_PLLI2SM_DIV_4
5608 * @arg @ref LL_RCC_PLLI2SM_DIV_5
5609 * @arg @ref LL_RCC_PLLI2SM_DIV_6
5610 * @arg @ref LL_RCC_PLLI2SM_DIV_7
5611 * @arg @ref LL_RCC_PLLI2SM_DIV_8
5612 * @arg @ref LL_RCC_PLLI2SM_DIV_9
5613 * @arg @ref LL_RCC_PLLI2SM_DIV_10
5614 * @arg @ref LL_RCC_PLLI2SM_DIV_11
5615 * @arg @ref LL_RCC_PLLI2SM_DIV_12
5616 * @arg @ref LL_RCC_PLLI2SM_DIV_13
5617 * @arg @ref LL_RCC_PLLI2SM_DIV_14
5618 * @arg @ref LL_RCC_PLLI2SM_DIV_15
5619 * @arg @ref LL_RCC_PLLI2SM_DIV_16
5620 * @arg @ref LL_RCC_PLLI2SM_DIV_17
5621 * @arg @ref LL_RCC_PLLI2SM_DIV_18
5622 * @arg @ref LL_RCC_PLLI2SM_DIV_19
5623 * @arg @ref LL_RCC_PLLI2SM_DIV_20
5624 * @arg @ref LL_RCC_PLLI2SM_DIV_21
5625 * @arg @ref LL_RCC_PLLI2SM_DIV_22
5626 * @arg @ref LL_RCC_PLLI2SM_DIV_23
5627 * @arg @ref LL_RCC_PLLI2SM_DIV_24
5628 * @arg @ref LL_RCC_PLLI2SM_DIV_25
5629 * @arg @ref LL_RCC_PLLI2SM_DIV_26
5630 * @arg @ref LL_RCC_PLLI2SM_DIV_27
5631 * @arg @ref LL_RCC_PLLI2SM_DIV_28
5632 * @arg @ref LL_RCC_PLLI2SM_DIV_29
5633 * @arg @ref LL_RCC_PLLI2SM_DIV_30
5634 * @arg @ref LL_RCC_PLLI2SM_DIV_31
5635 * @arg @ref LL_RCC_PLLI2SM_DIV_32
5636 * @arg @ref LL_RCC_PLLI2SM_DIV_33
5637 * @arg @ref LL_RCC_PLLI2SM_DIV_34
5638 * @arg @ref LL_RCC_PLLI2SM_DIV_35
5639 * @arg @ref LL_RCC_PLLI2SM_DIV_36
5640 * @arg @ref LL_RCC_PLLI2SM_DIV_37
5641 * @arg @ref LL_RCC_PLLI2SM_DIV_38
5642 * @arg @ref LL_RCC_PLLI2SM_DIV_39
5643 * @arg @ref LL_RCC_PLLI2SM_DIV_40
5644 * @arg @ref LL_RCC_PLLI2SM_DIV_41
5645 * @arg @ref LL_RCC_PLLI2SM_DIV_42
5646 * @arg @ref LL_RCC_PLLI2SM_DIV_43
5647 * @arg @ref LL_RCC_PLLI2SM_DIV_44
5648 * @arg @ref LL_RCC_PLLI2SM_DIV_45
5649 * @arg @ref LL_RCC_PLLI2SM_DIV_46
5650 * @arg @ref LL_RCC_PLLI2SM_DIV_47
5651 * @arg @ref LL_RCC_PLLI2SM_DIV_48
5652 * @arg @ref LL_RCC_PLLI2SM_DIV_49
5653 * @arg @ref LL_RCC_PLLI2SM_DIV_50
5654 * @arg @ref LL_RCC_PLLI2SM_DIV_51
5655 * @arg @ref LL_RCC_PLLI2SM_DIV_52
5656 * @arg @ref LL_RCC_PLLI2SM_DIV_53
5657 * @arg @ref LL_RCC_PLLI2SM_DIV_54
5658 * @arg @ref LL_RCC_PLLI2SM_DIV_55
5659 * @arg @ref LL_RCC_PLLI2SM_DIV_56
5660 * @arg @ref LL_RCC_PLLI2SM_DIV_57
5661 * @arg @ref LL_RCC_PLLI2SM_DIV_58
5662 * @arg @ref LL_RCC_PLLI2SM_DIV_59
5663 * @arg @ref LL_RCC_PLLI2SM_DIV_60
5664 * @arg @ref LL_RCC_PLLI2SM_DIV_61
5665 * @arg @ref LL_RCC_PLLI2SM_DIV_62
5666 * @arg @ref LL_RCC_PLLI2SM_DIV_63
5667 * @param PLLN Between 50/192(*) and 432
5668 *
5669 * (*) value not defined in all devices.
5670 * @param PLLR This parameter can be one of the following values:
5671 * @arg @ref LL_RCC_PLLI2SR_DIV_2
5672 * @arg @ref LL_RCC_PLLI2SR_DIV_3
5673 * @arg @ref LL_RCC_PLLI2SR_DIV_4
5674 * @arg @ref LL_RCC_PLLI2SR_DIV_5
5675 * @arg @ref LL_RCC_PLLI2SR_DIV_6
5676 * @arg @ref LL_RCC_PLLI2SR_DIV_7
5677 * @retval None
5678 */
5679 __STATIC_INLINE void LL_RCC_PLLI2S_ConfigDomain_I2S(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR)
5680 {
5681 register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&RCC->PLLCFGR) + (Source & 0x80U)));
5682 MODIFY_REG(*pReg, RCC_PLLCFGR_PLLSRC, (Source & (~0x80U)));
5683 #if defined(RCC_PLLI2SCFGR_PLLI2SM)
5684 MODIFY_REG(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SM, PLLM);
5685 #else
5686 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLM, PLLM);
5687 #endif /* RCC_PLLI2SCFGR_PLLI2SM */
5688 MODIFY_REG(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SN | RCC_PLLI2SCFGR_PLLI2SR, PLLN << RCC_PLLI2SCFGR_PLLI2SN_Pos | PLLR);
5689 }
5690
5691 /**
5692 * @brief Get I2SPLL multiplication factor for VCO
5693 * @rmtoll PLLI2SCFGR PLLI2SN LL_RCC_PLLI2S_GetN
5694 * @retval Between 50/192(*) and 432
5695 *
5696 * (*) value not defined in all devices.
5697 */
5698 __STATIC_INLINE uint32_t LL_RCC_PLLI2S_GetN(void)
5699 {
5700 return (uint32_t)(READ_BIT(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SN) >> RCC_PLLI2SCFGR_PLLI2SN_Pos);
5701 }
5702
5703 #if defined(RCC_PLLI2SCFGR_PLLI2SQ)
5704 /**
5705 * @brief Get I2SPLL division factor for PLLI2SQ
5706 * @rmtoll PLLI2SCFGR PLLI2SQ LL_RCC_PLLI2S_GetQ
5707 * @retval Returned value can be one of the following values:
5708 * @arg @ref LL_RCC_PLLI2SQ_DIV_2
5709 * @arg @ref LL_RCC_PLLI2SQ_DIV_3
5710 * @arg @ref LL_RCC_PLLI2SQ_DIV_4
5711 * @arg @ref LL_RCC_PLLI2SQ_DIV_5
5712 * @arg @ref LL_RCC_PLLI2SQ_DIV_6
5713 * @arg @ref LL_RCC_PLLI2SQ_DIV_7
5714 * @arg @ref LL_RCC_PLLI2SQ_DIV_8
5715 * @arg @ref LL_RCC_PLLI2SQ_DIV_9
5716 * @arg @ref LL_RCC_PLLI2SQ_DIV_10
5717 * @arg @ref LL_RCC_PLLI2SQ_DIV_11
5718 * @arg @ref LL_RCC_PLLI2SQ_DIV_12
5719 * @arg @ref LL_RCC_PLLI2SQ_DIV_13
5720 * @arg @ref LL_RCC_PLLI2SQ_DIV_14
5721 * @arg @ref LL_RCC_PLLI2SQ_DIV_15
5722 */
5723 __STATIC_INLINE uint32_t LL_RCC_PLLI2S_GetQ(void)
5724 {
5725 return (uint32_t)(READ_BIT(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SQ));
5726 }
5727 #endif /* RCC_PLLI2SCFGR_PLLI2SQ */
5728
5729 /**
5730 * @brief Get I2SPLL division factor for PLLI2SR
5731 * @note used for PLLI2SCLK (I2S clock)
5732 * @rmtoll PLLI2SCFGR PLLI2SR LL_RCC_PLLI2S_GetR
5733 * @retval Returned value can be one of the following values:
5734 * @arg @ref LL_RCC_PLLI2SR_DIV_2
5735 * @arg @ref LL_RCC_PLLI2SR_DIV_3
5736 * @arg @ref LL_RCC_PLLI2SR_DIV_4
5737 * @arg @ref LL_RCC_PLLI2SR_DIV_5
5738 * @arg @ref LL_RCC_PLLI2SR_DIV_6
5739 * @arg @ref LL_RCC_PLLI2SR_DIV_7
5740 */
5741 __STATIC_INLINE uint32_t LL_RCC_PLLI2S_GetR(void)
5742 {
5743 return (uint32_t)(READ_BIT(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SR));
5744 }
5745
5746 #if defined(RCC_PLLI2SCFGR_PLLI2SP)
5747 /**
5748 * @brief Get I2SPLL division factor for PLLI2SP
5749 * @note used for PLLSPDIFRXCLK (SPDIFRX clock)
5750 * @rmtoll PLLI2SCFGR PLLI2SP LL_RCC_PLLI2S_GetP
5751 * @retval Returned value can be one of the following values:
5752 * @arg @ref LL_RCC_PLLI2SP_DIV_2
5753 * @arg @ref LL_RCC_PLLI2SP_DIV_4
5754 * @arg @ref LL_RCC_PLLI2SP_DIV_6
5755 * @arg @ref LL_RCC_PLLI2SP_DIV_8
5756 */
5757 __STATIC_INLINE uint32_t LL_RCC_PLLI2S_GetP(void)
5758 {
5759 return (uint32_t)(READ_BIT(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SP));
5760 }
5761 #endif /* RCC_PLLI2SCFGR_PLLI2SP */
5762
5763 #if defined(RCC_DCKCFGR_PLLI2SDIVQ)
5764 /**
5765 * @brief Get I2SPLL division factor for PLLI2SDIVQ
5766 * @note used PLLSAICLK selected (SAI clock)
5767 * @rmtoll DCKCFGR PLLI2SDIVQ LL_RCC_PLLI2S_GetDIVQ
5768 * @retval Returned value can be one of the following values:
5769 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_1
5770 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_2
5771 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_3
5772 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_4
5773 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_5
5774 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_6
5775 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_7
5776 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_8
5777 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_9
5778 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_10
5779 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_11
5780 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_12
5781 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_13
5782 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_14
5783 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_15
5784 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_16
5785 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_17
5786 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_18
5787 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_19
5788 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_20
5789 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_21
5790 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_22
5791 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_23
5792 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_24
5793 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_25
5794 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_26
5795 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_27
5796 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_28
5797 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_29
5798 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_30
5799 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_31
5800 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_32
5801 */
5802 __STATIC_INLINE uint32_t LL_RCC_PLLI2S_GetDIVQ(void)
5803 {
5804 return (uint32_t)(READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_PLLI2SDIVQ));
5805 }
5806 #endif /* RCC_DCKCFGR_PLLI2SDIVQ */
5807
5808 #if defined(RCC_DCKCFGR_PLLI2SDIVR)
5809 /**
5810 * @brief Get I2SPLL division factor for PLLI2SDIVR
5811 * @note used PLLSAICLK selected (SAI clock)
5812 * @rmtoll DCKCFGR PLLI2SDIVR LL_RCC_PLLI2S_GetDIVR
5813 * @retval Returned value can be one of the following values:
5814 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_1
5815 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_2
5816 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_3
5817 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_4
5818 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_5
5819 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_6
5820 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_7
5821 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_8
5822 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_9
5823 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_10
5824 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_11
5825 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_12
5826 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_13
5827 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_14
5828 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_15
5829 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_16
5830 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_17
5831 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_18
5832 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_19
5833 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_20
5834 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_21
5835 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_22
5836 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_23
5837 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_24
5838 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_25
5839 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_26
5840 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_27
5841 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_28
5842 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_29
5843 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_30
5844 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_31
5845 */
5846 __STATIC_INLINE uint32_t LL_RCC_PLLI2S_GetDIVR(void)
5847 {
5848 return (uint32_t)(READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_PLLI2SDIVR));
5849 }
5850 #endif /* RCC_DCKCFGR_PLLI2SDIVR */
5851
5852 /**
5853 * @brief Get division factor for PLLI2S input clock
5854 * @rmtoll PLLCFGR PLLM LL_RCC_PLLI2S_GetDivider\n
5855 * PLLI2SCFGR PLLI2SM LL_RCC_PLLI2S_GetDivider
5856 * @retval Returned value can be one of the following values:
5857 * @arg @ref LL_RCC_PLLI2SM_DIV_2
5858 * @arg @ref LL_RCC_PLLI2SM_DIV_3
5859 * @arg @ref LL_RCC_PLLI2SM_DIV_4
5860 * @arg @ref LL_RCC_PLLI2SM_DIV_5
5861 * @arg @ref LL_RCC_PLLI2SM_DIV_6
5862 * @arg @ref LL_RCC_PLLI2SM_DIV_7
5863 * @arg @ref LL_RCC_PLLI2SM_DIV_8
5864 * @arg @ref LL_RCC_PLLI2SM_DIV_9
5865 * @arg @ref LL_RCC_PLLI2SM_DIV_10
5866 * @arg @ref LL_RCC_PLLI2SM_DIV_11
5867 * @arg @ref LL_RCC_PLLI2SM_DIV_12
5868 * @arg @ref LL_RCC_PLLI2SM_DIV_13
5869 * @arg @ref LL_RCC_PLLI2SM_DIV_14
5870 * @arg @ref LL_RCC_PLLI2SM_DIV_15
5871 * @arg @ref LL_RCC_PLLI2SM_DIV_16
5872 * @arg @ref LL_RCC_PLLI2SM_DIV_17
5873 * @arg @ref LL_RCC_PLLI2SM_DIV_18
5874 * @arg @ref LL_RCC_PLLI2SM_DIV_19
5875 * @arg @ref LL_RCC_PLLI2SM_DIV_20
5876 * @arg @ref LL_RCC_PLLI2SM_DIV_21
5877 * @arg @ref LL_RCC_PLLI2SM_DIV_22
5878 * @arg @ref LL_RCC_PLLI2SM_DIV_23
5879 * @arg @ref LL_RCC_PLLI2SM_DIV_24
5880 * @arg @ref LL_RCC_PLLI2SM_DIV_25
5881 * @arg @ref LL_RCC_PLLI2SM_DIV_26
5882 * @arg @ref LL_RCC_PLLI2SM_DIV_27
5883 * @arg @ref LL_RCC_PLLI2SM_DIV_28
5884 * @arg @ref LL_RCC_PLLI2SM_DIV_29
5885 * @arg @ref LL_RCC_PLLI2SM_DIV_30
5886 * @arg @ref LL_RCC_PLLI2SM_DIV_31
5887 * @arg @ref LL_RCC_PLLI2SM_DIV_32
5888 * @arg @ref LL_RCC_PLLI2SM_DIV_33
5889 * @arg @ref LL_RCC_PLLI2SM_DIV_34
5890 * @arg @ref LL_RCC_PLLI2SM_DIV_35
5891 * @arg @ref LL_RCC_PLLI2SM_DIV_36
5892 * @arg @ref LL_RCC_PLLI2SM_DIV_37
5893 * @arg @ref LL_RCC_PLLI2SM_DIV_38
5894 * @arg @ref LL_RCC_PLLI2SM_DIV_39
5895 * @arg @ref LL_RCC_PLLI2SM_DIV_40
5896 * @arg @ref LL_RCC_PLLI2SM_DIV_41
5897 * @arg @ref LL_RCC_PLLI2SM_DIV_42
5898 * @arg @ref LL_RCC_PLLI2SM_DIV_43
5899 * @arg @ref LL_RCC_PLLI2SM_DIV_44
5900 * @arg @ref LL_RCC_PLLI2SM_DIV_45
5901 * @arg @ref LL_RCC_PLLI2SM_DIV_46
5902 * @arg @ref LL_RCC_PLLI2SM_DIV_47
5903 * @arg @ref LL_RCC_PLLI2SM_DIV_48
5904 * @arg @ref LL_RCC_PLLI2SM_DIV_49
5905 * @arg @ref LL_RCC_PLLI2SM_DIV_50
5906 * @arg @ref LL_RCC_PLLI2SM_DIV_51
5907 * @arg @ref LL_RCC_PLLI2SM_DIV_52
5908 * @arg @ref LL_RCC_PLLI2SM_DIV_53
5909 * @arg @ref LL_RCC_PLLI2SM_DIV_54
5910 * @arg @ref LL_RCC_PLLI2SM_DIV_55
5911 * @arg @ref LL_RCC_PLLI2SM_DIV_56
5912 * @arg @ref LL_RCC_PLLI2SM_DIV_57
5913 * @arg @ref LL_RCC_PLLI2SM_DIV_58
5914 * @arg @ref LL_RCC_PLLI2SM_DIV_59
5915 * @arg @ref LL_RCC_PLLI2SM_DIV_60
5916 * @arg @ref LL_RCC_PLLI2SM_DIV_61
5917 * @arg @ref LL_RCC_PLLI2SM_DIV_62
5918 * @arg @ref LL_RCC_PLLI2SM_DIV_63
5919 */
5920 __STATIC_INLINE uint32_t LL_RCC_PLLI2S_GetDivider(void)
5921 {
5922 #if defined(RCC_PLLI2SCFGR_PLLI2SM)
5923 return (uint32_t)(READ_BIT(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SM));
5924 #else
5925 return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM));
5926 #endif /* RCC_PLLI2SCFGR_PLLI2SM */
5927 }
5928
5929 /**
5930 * @brief Get the oscillator used as PLL clock source.
5931 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLLI2S_GetMainSource\n
5932 * PLLI2SCFGR PLLI2SSRC LL_RCC_PLLI2S_GetMainSource
5933 * @retval Returned value can be one of the following values:
5934 * @arg @ref LL_RCC_PLLSOURCE_HSI
5935 * @arg @ref LL_RCC_PLLSOURCE_HSE
5936 * @arg @ref LL_RCC_PLLI2SSOURCE_PIN (*)
5937 *
5938 * (*) value not defined in all devices.
5939 */
5940 __STATIC_INLINE uint32_t LL_RCC_PLLI2S_GetMainSource(void)
5941 {
5942 #if defined(RCC_PLLI2SCFGR_PLLI2SSRC)
5943 register uint32_t pllsrc = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC);
5944 register uint32_t plli2sssrc0 = READ_BIT(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SSRC);
5945 register uint32_t plli2sssrc1 = READ_BIT(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SSRC) >> 15U;
5946 return (uint32_t)(pllsrc | plli2sssrc0 | plli2sssrc1);
5947 #else
5948 return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC));
5949 #endif /* RCC_PLLI2SCFGR_PLLI2SSRC */
5950 }
5951
5952 /**
5953 * @}
5954 */
5955 #endif /* RCC_PLLI2S_SUPPORT */
5956
5957 #if defined(RCC_PLLSAI_SUPPORT)
5958 /** @defgroup RCC_LL_EF_PLLSAI PLLSAI
5959 * @{
5960 */
5961
5962 /**
5963 * @brief Enable PLLSAI
5964 * @rmtoll CR PLLSAION LL_RCC_PLLSAI_Enable
5965 * @retval None
5966 */
5967 __STATIC_INLINE void LL_RCC_PLLSAI_Enable(void)
5968 {
5969 SET_BIT(RCC->CR, RCC_CR_PLLSAION);
5970 }
5971
5972 /**
5973 * @brief Disable PLLSAI
5974 * @rmtoll CR PLLSAION LL_RCC_PLLSAI_Disable
5975 * @retval None
5976 */
5977 __STATIC_INLINE void LL_RCC_PLLSAI_Disable(void)
5978 {
5979 CLEAR_BIT(RCC->CR, RCC_CR_PLLSAION);
5980 }
5981
5982 /**
5983 * @brief Check if PLLSAI Ready
5984 * @rmtoll CR PLLSAIRDY LL_RCC_PLLSAI_IsReady
5985 * @retval State of bit (1 or 0).
5986 */
5987 __STATIC_INLINE uint32_t LL_RCC_PLLSAI_IsReady(void)
5988 {
5989 return (READ_BIT(RCC->CR, RCC_CR_PLLSAIRDY) == (RCC_CR_PLLSAIRDY));
5990 }
5991
5992 /**
5993 * @brief Configure PLLSAI used for SAI domain clock
5994 * @note PLL Source and PLLM Divider can be written only when PLL,
5995 * PLLI2S and PLLSAI(*) are disabled
5996 * @note PLLN/PLLQ can be written only when PLLSAI is disabled
5997 * @note This can be selected for SAI
5998 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLLSAI_ConfigDomain_SAI\n
5999 * PLLCFGR PLLM LL_RCC_PLLSAI_ConfigDomain_SAI\n
6000 * PLLSAICFGR PLLSAIM LL_RCC_PLLSAI_ConfigDomain_SAI\n
6001 * PLLSAICFGR PLLSAIN LL_RCC_PLLSAI_ConfigDomain_SAI\n
6002 * PLLSAICFGR PLLSAIQ LL_RCC_PLLSAI_ConfigDomain_SAI\n
6003 * DCKCFGR PLLSAIDIVQ LL_RCC_PLLSAI_ConfigDomain_SAI
6004 * @param Source This parameter can be one of the following values:
6005 * @arg @ref LL_RCC_PLLSOURCE_HSI
6006 * @arg @ref LL_RCC_PLLSOURCE_HSE
6007 * @param PLLM This parameter can be one of the following values:
6008 * @arg @ref LL_RCC_PLLSAIM_DIV_2
6009 * @arg @ref LL_RCC_PLLSAIM_DIV_3
6010 * @arg @ref LL_RCC_PLLSAIM_DIV_4
6011 * @arg @ref LL_RCC_PLLSAIM_DIV_5
6012 * @arg @ref LL_RCC_PLLSAIM_DIV_6
6013 * @arg @ref LL_RCC_PLLSAIM_DIV_7
6014 * @arg @ref LL_RCC_PLLSAIM_DIV_8
6015 * @arg @ref LL_RCC_PLLSAIM_DIV_9
6016 * @arg @ref LL_RCC_PLLSAIM_DIV_10
6017 * @arg @ref LL_RCC_PLLSAIM_DIV_11
6018 * @arg @ref LL_RCC_PLLSAIM_DIV_12
6019 * @arg @ref LL_RCC_PLLSAIM_DIV_13
6020 * @arg @ref LL_RCC_PLLSAIM_DIV_14
6021 * @arg @ref LL_RCC_PLLSAIM_DIV_15
6022 * @arg @ref LL_RCC_PLLSAIM_DIV_16
6023 * @arg @ref LL_RCC_PLLSAIM_DIV_17
6024 * @arg @ref LL_RCC_PLLSAIM_DIV_18
6025 * @arg @ref LL_RCC_PLLSAIM_DIV_19
6026 * @arg @ref LL_RCC_PLLSAIM_DIV_20
6027 * @arg @ref LL_RCC_PLLSAIM_DIV_21
6028 * @arg @ref LL_RCC_PLLSAIM_DIV_22
6029 * @arg @ref LL_RCC_PLLSAIM_DIV_23
6030 * @arg @ref LL_RCC_PLLSAIM_DIV_24
6031 * @arg @ref LL_RCC_PLLSAIM_DIV_25
6032 * @arg @ref LL_RCC_PLLSAIM_DIV_26
6033 * @arg @ref LL_RCC_PLLSAIM_DIV_27
6034 * @arg @ref LL_RCC_PLLSAIM_DIV_28
6035 * @arg @ref LL_RCC_PLLSAIM_DIV_29
6036 * @arg @ref LL_RCC_PLLSAIM_DIV_30
6037 * @arg @ref LL_RCC_PLLSAIM_DIV_31
6038 * @arg @ref LL_RCC_PLLSAIM_DIV_32
6039 * @arg @ref LL_RCC_PLLSAIM_DIV_33
6040 * @arg @ref LL_RCC_PLLSAIM_DIV_34
6041 * @arg @ref LL_RCC_PLLSAIM_DIV_35
6042 * @arg @ref LL_RCC_PLLSAIM_DIV_36
6043 * @arg @ref LL_RCC_PLLSAIM_DIV_37
6044 * @arg @ref LL_RCC_PLLSAIM_DIV_38
6045 * @arg @ref LL_RCC_PLLSAIM_DIV_39
6046 * @arg @ref LL_RCC_PLLSAIM_DIV_40
6047 * @arg @ref LL_RCC_PLLSAIM_DIV_41
6048 * @arg @ref LL_RCC_PLLSAIM_DIV_42
6049 * @arg @ref LL_RCC_PLLSAIM_DIV_43
6050 * @arg @ref LL_RCC_PLLSAIM_DIV_44
6051 * @arg @ref LL_RCC_PLLSAIM_DIV_45
6052 * @arg @ref LL_RCC_PLLSAIM_DIV_46
6053 * @arg @ref LL_RCC_PLLSAIM_DIV_47
6054 * @arg @ref LL_RCC_PLLSAIM_DIV_48
6055 * @arg @ref LL_RCC_PLLSAIM_DIV_49
6056 * @arg @ref LL_RCC_PLLSAIM_DIV_50
6057 * @arg @ref LL_RCC_PLLSAIM_DIV_51
6058 * @arg @ref LL_RCC_PLLSAIM_DIV_52
6059 * @arg @ref LL_RCC_PLLSAIM_DIV_53
6060 * @arg @ref LL_RCC_PLLSAIM_DIV_54
6061 * @arg @ref LL_RCC_PLLSAIM_DIV_55
6062 * @arg @ref LL_RCC_PLLSAIM_DIV_56
6063 * @arg @ref LL_RCC_PLLSAIM_DIV_57
6064 * @arg @ref LL_RCC_PLLSAIM_DIV_58
6065 * @arg @ref LL_RCC_PLLSAIM_DIV_59
6066 * @arg @ref LL_RCC_PLLSAIM_DIV_60
6067 * @arg @ref LL_RCC_PLLSAIM_DIV_61
6068 * @arg @ref LL_RCC_PLLSAIM_DIV_62
6069 * @arg @ref LL_RCC_PLLSAIM_DIV_63
6070 * @param PLLN Between 49/50(*) and 432
6071 *
6072 * (*) value not defined in all devices.
6073 * @param PLLQ This parameter can be one of the following values:
6074 * @arg @ref LL_RCC_PLLSAIQ_DIV_2
6075 * @arg @ref LL_RCC_PLLSAIQ_DIV_3
6076 * @arg @ref LL_RCC_PLLSAIQ_DIV_4
6077 * @arg @ref LL_RCC_PLLSAIQ_DIV_5
6078 * @arg @ref LL_RCC_PLLSAIQ_DIV_6
6079 * @arg @ref LL_RCC_PLLSAIQ_DIV_7
6080 * @arg @ref LL_RCC_PLLSAIQ_DIV_8
6081 * @arg @ref LL_RCC_PLLSAIQ_DIV_9
6082 * @arg @ref LL_RCC_PLLSAIQ_DIV_10
6083 * @arg @ref LL_RCC_PLLSAIQ_DIV_11
6084 * @arg @ref LL_RCC_PLLSAIQ_DIV_12
6085 * @arg @ref LL_RCC_PLLSAIQ_DIV_13
6086 * @arg @ref LL_RCC_PLLSAIQ_DIV_14
6087 * @arg @ref LL_RCC_PLLSAIQ_DIV_15
6088 * @param PLLDIVQ This parameter can be one of the following values:
6089 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_1
6090 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_2
6091 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_3
6092 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_4
6093 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_5
6094 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_6
6095 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_7
6096 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_8
6097 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_9
6098 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_10
6099 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_11
6100 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_12
6101 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_13
6102 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_14
6103 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_15
6104 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_16
6105 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_17
6106 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_18
6107 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_19
6108 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_20
6109 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_21
6110 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_22
6111 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_23
6112 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_24
6113 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_25
6114 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_26
6115 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_27
6116 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_28
6117 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_29
6118 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_30
6119 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_31
6120 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_32
6121 * @retval None
6122 */
6123 __STATIC_INLINE void LL_RCC_PLLSAI_ConfigDomain_SAI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLQ, uint32_t PLLDIVQ)
6124 {
6125 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, Source);
6126 #if defined(RCC_PLLSAICFGR_PLLSAIM)
6127 MODIFY_REG(RCC->PLLSAICFGR, RCC_PLLSAICFGR_PLLSAIM, PLLM);
6128 #else
6129 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLM, PLLM);
6130 #endif /* RCC_PLLSAICFGR_PLLSAIM */
6131 MODIFY_REG(RCC->PLLSAICFGR, RCC_PLLSAICFGR_PLLSAIN | RCC_PLLSAICFGR_PLLSAIQ, PLLN << RCC_PLLSAICFGR_PLLSAIN_Pos | PLLQ);
6132 MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLSAIDIVQ, PLLDIVQ);
6133 }
6134
6135 #if defined(RCC_PLLSAICFGR_PLLSAIP)
6136 /**
6137 * @brief Configure PLLSAI used for 48Mhz domain clock
6138 * @note PLL Source and PLLM Divider can be written only when PLL,
6139 * PLLI2S and PLLSAI(*) are disabled
6140 * @note PLLN/PLLP can be written only when PLLSAI is disabled
6141 * @note This can be selected for USB, RNG, SDIO
6142 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLLSAI_ConfigDomain_48M\n
6143 * PLLCFGR PLLM LL_RCC_PLLSAI_ConfigDomain_48M\n
6144 * PLLSAICFGR PLLSAIM LL_RCC_PLLSAI_ConfigDomain_48M\n
6145 * PLLSAICFGR PLLSAIN LL_RCC_PLLSAI_ConfigDomain_48M\n
6146 * PLLSAICFGR PLLSAIP LL_RCC_PLLSAI_ConfigDomain_48M
6147 * @param Source This parameter can be one of the following values:
6148 * @arg @ref LL_RCC_PLLSOURCE_HSI
6149 * @arg @ref LL_RCC_PLLSOURCE_HSE
6150 * @param PLLM This parameter can be one of the following values:
6151 * @arg @ref LL_RCC_PLLSAIM_DIV_2
6152 * @arg @ref LL_RCC_PLLSAIM_DIV_3
6153 * @arg @ref LL_RCC_PLLSAIM_DIV_4
6154 * @arg @ref LL_RCC_PLLSAIM_DIV_5
6155 * @arg @ref LL_RCC_PLLSAIM_DIV_6
6156 * @arg @ref LL_RCC_PLLSAIM_DIV_7
6157 * @arg @ref LL_RCC_PLLSAIM_DIV_8
6158 * @arg @ref LL_RCC_PLLSAIM_DIV_9
6159 * @arg @ref LL_RCC_PLLSAIM_DIV_10
6160 * @arg @ref LL_RCC_PLLSAIM_DIV_11
6161 * @arg @ref LL_RCC_PLLSAIM_DIV_12
6162 * @arg @ref LL_RCC_PLLSAIM_DIV_13
6163 * @arg @ref LL_RCC_PLLSAIM_DIV_14
6164 * @arg @ref LL_RCC_PLLSAIM_DIV_15
6165 * @arg @ref LL_RCC_PLLSAIM_DIV_16
6166 * @arg @ref LL_RCC_PLLSAIM_DIV_17
6167 * @arg @ref LL_RCC_PLLSAIM_DIV_18
6168 * @arg @ref LL_RCC_PLLSAIM_DIV_19
6169 * @arg @ref LL_RCC_PLLSAIM_DIV_20
6170 * @arg @ref LL_RCC_PLLSAIM_DIV_21
6171 * @arg @ref LL_RCC_PLLSAIM_DIV_22
6172 * @arg @ref LL_RCC_PLLSAIM_DIV_23
6173 * @arg @ref LL_RCC_PLLSAIM_DIV_24
6174 * @arg @ref LL_RCC_PLLSAIM_DIV_25
6175 * @arg @ref LL_RCC_PLLSAIM_DIV_26
6176 * @arg @ref LL_RCC_PLLSAIM_DIV_27
6177 * @arg @ref LL_RCC_PLLSAIM_DIV_28
6178 * @arg @ref LL_RCC_PLLSAIM_DIV_29
6179 * @arg @ref LL_RCC_PLLSAIM_DIV_30
6180 * @arg @ref LL_RCC_PLLSAIM_DIV_31
6181 * @arg @ref LL_RCC_PLLSAIM_DIV_32
6182 * @arg @ref LL_RCC_PLLSAIM_DIV_33
6183 * @arg @ref LL_RCC_PLLSAIM_DIV_34
6184 * @arg @ref LL_RCC_PLLSAIM_DIV_35
6185 * @arg @ref LL_RCC_PLLSAIM_DIV_36
6186 * @arg @ref LL_RCC_PLLSAIM_DIV_37
6187 * @arg @ref LL_RCC_PLLSAIM_DIV_38
6188 * @arg @ref LL_RCC_PLLSAIM_DIV_39
6189 * @arg @ref LL_RCC_PLLSAIM_DIV_40
6190 * @arg @ref LL_RCC_PLLSAIM_DIV_41
6191 * @arg @ref LL_RCC_PLLSAIM_DIV_42
6192 * @arg @ref LL_RCC_PLLSAIM_DIV_43
6193 * @arg @ref LL_RCC_PLLSAIM_DIV_44
6194 * @arg @ref LL_RCC_PLLSAIM_DIV_45
6195 * @arg @ref LL_RCC_PLLSAIM_DIV_46
6196 * @arg @ref LL_RCC_PLLSAIM_DIV_47
6197 * @arg @ref LL_RCC_PLLSAIM_DIV_48
6198 * @arg @ref LL_RCC_PLLSAIM_DIV_49
6199 * @arg @ref LL_RCC_PLLSAIM_DIV_50
6200 * @arg @ref LL_RCC_PLLSAIM_DIV_51
6201 * @arg @ref LL_RCC_PLLSAIM_DIV_52
6202 * @arg @ref LL_RCC_PLLSAIM_DIV_53
6203 * @arg @ref LL_RCC_PLLSAIM_DIV_54
6204 * @arg @ref LL_RCC_PLLSAIM_DIV_55
6205 * @arg @ref LL_RCC_PLLSAIM_DIV_56
6206 * @arg @ref LL_RCC_PLLSAIM_DIV_57
6207 * @arg @ref LL_RCC_PLLSAIM_DIV_58
6208 * @arg @ref LL_RCC_PLLSAIM_DIV_59
6209 * @arg @ref LL_RCC_PLLSAIM_DIV_60
6210 * @arg @ref LL_RCC_PLLSAIM_DIV_61
6211 * @arg @ref LL_RCC_PLLSAIM_DIV_62
6212 * @arg @ref LL_RCC_PLLSAIM_DIV_63
6213 * @param PLLN Between 50 and 432
6214 * @param PLLP This parameter can be one of the following values:
6215 * @arg @ref LL_RCC_PLLSAIP_DIV_2
6216 * @arg @ref LL_RCC_PLLSAIP_DIV_4
6217 * @arg @ref LL_RCC_PLLSAIP_DIV_6
6218 * @arg @ref LL_RCC_PLLSAIP_DIV_8
6219 * @retval None
6220 */
6221 __STATIC_INLINE void LL_RCC_PLLSAI_ConfigDomain_48M(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP)
6222 {
6223 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, Source);
6224 #if defined(RCC_PLLSAICFGR_PLLSAIM)
6225 MODIFY_REG(RCC->PLLSAICFGR, RCC_PLLSAICFGR_PLLSAIM, PLLM);
6226 #else
6227 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLM, PLLM);
6228 #endif /* RCC_PLLSAICFGR_PLLSAIM */
6229 MODIFY_REG(RCC->PLLSAICFGR, RCC_PLLSAICFGR_PLLSAIN | RCC_PLLSAICFGR_PLLSAIP, PLLN << RCC_PLLSAICFGR_PLLSAIN_Pos | PLLP);
6230 }
6231 #endif /* RCC_PLLSAICFGR_PLLSAIP */
6232
6233 #if defined(LTDC)
6234 /**
6235 * @brief Configure PLLSAI used for LTDC domain clock
6236 * @note PLL Source and PLLM Divider can be written only when PLL,
6237 * PLLI2S and PLLSAI(*) are disabled
6238 * @note PLLN/PLLR can be written only when PLLSAI is disabled
6239 * @note This can be selected for LTDC
6240 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLLSAI_ConfigDomain_LTDC\n
6241 * PLLCFGR PLLM LL_RCC_PLLSAI_ConfigDomain_LTDC\n
6242 * PLLSAICFGR PLLSAIN LL_RCC_PLLSAI_ConfigDomain_LTDC\n
6243 * PLLSAICFGR PLLSAIR LL_RCC_PLLSAI_ConfigDomain_LTDC\n
6244 * DCKCFGR PLLSAIDIVR LL_RCC_PLLSAI_ConfigDomain_LTDC
6245 * @param Source This parameter can be one of the following values:
6246 * @arg @ref LL_RCC_PLLSOURCE_HSI
6247 * @arg @ref LL_RCC_PLLSOURCE_HSE
6248 * @param PLLM This parameter can be one of the following values:
6249 * @arg @ref LL_RCC_PLLSAIM_DIV_2
6250 * @arg @ref LL_RCC_PLLSAIM_DIV_3
6251 * @arg @ref LL_RCC_PLLSAIM_DIV_4
6252 * @arg @ref LL_RCC_PLLSAIM_DIV_5
6253 * @arg @ref LL_RCC_PLLSAIM_DIV_6
6254 * @arg @ref LL_RCC_PLLSAIM_DIV_7
6255 * @arg @ref LL_RCC_PLLSAIM_DIV_8
6256 * @arg @ref LL_RCC_PLLSAIM_DIV_9
6257 * @arg @ref LL_RCC_PLLSAIM_DIV_10
6258 * @arg @ref LL_RCC_PLLSAIM_DIV_11
6259 * @arg @ref LL_RCC_PLLSAIM_DIV_12
6260 * @arg @ref LL_RCC_PLLSAIM_DIV_13
6261 * @arg @ref LL_RCC_PLLSAIM_DIV_14
6262 * @arg @ref LL_RCC_PLLSAIM_DIV_15
6263 * @arg @ref LL_RCC_PLLSAIM_DIV_16
6264 * @arg @ref LL_RCC_PLLSAIM_DIV_17
6265 * @arg @ref LL_RCC_PLLSAIM_DIV_18
6266 * @arg @ref LL_RCC_PLLSAIM_DIV_19
6267 * @arg @ref LL_RCC_PLLSAIM_DIV_20
6268 * @arg @ref LL_RCC_PLLSAIM_DIV_21
6269 * @arg @ref LL_RCC_PLLSAIM_DIV_22
6270 * @arg @ref LL_RCC_PLLSAIM_DIV_23
6271 * @arg @ref LL_RCC_PLLSAIM_DIV_24
6272 * @arg @ref LL_RCC_PLLSAIM_DIV_25
6273 * @arg @ref LL_RCC_PLLSAIM_DIV_26
6274 * @arg @ref LL_RCC_PLLSAIM_DIV_27
6275 * @arg @ref LL_RCC_PLLSAIM_DIV_28
6276 * @arg @ref LL_RCC_PLLSAIM_DIV_29
6277 * @arg @ref LL_RCC_PLLSAIM_DIV_30
6278 * @arg @ref LL_RCC_PLLSAIM_DIV_31
6279 * @arg @ref LL_RCC_PLLSAIM_DIV_32
6280 * @arg @ref LL_RCC_PLLSAIM_DIV_33
6281 * @arg @ref LL_RCC_PLLSAIM_DIV_34
6282 * @arg @ref LL_RCC_PLLSAIM_DIV_35
6283 * @arg @ref LL_RCC_PLLSAIM_DIV_36
6284 * @arg @ref LL_RCC_PLLSAIM_DIV_37
6285 * @arg @ref LL_RCC_PLLSAIM_DIV_38
6286 * @arg @ref LL_RCC_PLLSAIM_DIV_39
6287 * @arg @ref LL_RCC_PLLSAIM_DIV_40
6288 * @arg @ref LL_RCC_PLLSAIM_DIV_41
6289 * @arg @ref LL_RCC_PLLSAIM_DIV_42
6290 * @arg @ref LL_RCC_PLLSAIM_DIV_43
6291 * @arg @ref LL_RCC_PLLSAIM_DIV_44
6292 * @arg @ref LL_RCC_PLLSAIM_DIV_45
6293 * @arg @ref LL_RCC_PLLSAIM_DIV_46
6294 * @arg @ref LL_RCC_PLLSAIM_DIV_47
6295 * @arg @ref LL_RCC_PLLSAIM_DIV_48
6296 * @arg @ref LL_RCC_PLLSAIM_DIV_49
6297 * @arg @ref LL_RCC_PLLSAIM_DIV_50
6298 * @arg @ref LL_RCC_PLLSAIM_DIV_51
6299 * @arg @ref LL_RCC_PLLSAIM_DIV_52
6300 * @arg @ref LL_RCC_PLLSAIM_DIV_53
6301 * @arg @ref LL_RCC_PLLSAIM_DIV_54
6302 * @arg @ref LL_RCC_PLLSAIM_DIV_55
6303 * @arg @ref LL_RCC_PLLSAIM_DIV_56
6304 * @arg @ref LL_RCC_PLLSAIM_DIV_57
6305 * @arg @ref LL_RCC_PLLSAIM_DIV_58
6306 * @arg @ref LL_RCC_PLLSAIM_DIV_59
6307 * @arg @ref LL_RCC_PLLSAIM_DIV_60
6308 * @arg @ref LL_RCC_PLLSAIM_DIV_61
6309 * @arg @ref LL_RCC_PLLSAIM_DIV_62
6310 * @arg @ref LL_RCC_PLLSAIM_DIV_63
6311 * @param PLLN Between 49/50(*) and 432
6312 *
6313 * (*) value not defined in all devices.
6314 * @param PLLR This parameter can be one of the following values:
6315 * @arg @ref LL_RCC_PLLSAIR_DIV_2
6316 * @arg @ref LL_RCC_PLLSAIR_DIV_3
6317 * @arg @ref LL_RCC_PLLSAIR_DIV_4
6318 * @arg @ref LL_RCC_PLLSAIR_DIV_5
6319 * @arg @ref LL_RCC_PLLSAIR_DIV_6
6320 * @arg @ref LL_RCC_PLLSAIR_DIV_7
6321 * @param PLLDIVR This parameter can be one of the following values:
6322 * @arg @ref LL_RCC_PLLSAIDIVR_DIV_2
6323 * @arg @ref LL_RCC_PLLSAIDIVR_DIV_4
6324 * @arg @ref LL_RCC_PLLSAIDIVR_DIV_8
6325 * @arg @ref LL_RCC_PLLSAIDIVR_DIV_16
6326 * @retval None
6327 */
6328 __STATIC_INLINE void LL_RCC_PLLSAI_ConfigDomain_LTDC(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR, uint32_t PLLDIVR)
6329 {
6330 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM, Source | PLLM);
6331 MODIFY_REG(RCC->PLLSAICFGR, RCC_PLLSAICFGR_PLLSAIN | RCC_PLLSAICFGR_PLLSAIR, PLLN << RCC_PLLSAICFGR_PLLSAIN_Pos | PLLR);
6332 MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLSAIDIVR, PLLDIVR);
6333 }
6334 #endif /* LTDC */
6335
6336 /**
6337 * @brief Get division factor for PLLSAI input clock
6338 * @rmtoll PLLCFGR PLLM LL_RCC_PLLSAI_GetDivider\n
6339 * PLLSAICFGR PLLSAIM LL_RCC_PLLSAI_GetDivider
6340 * @retval Returned value can be one of the following values:
6341 * @arg @ref LL_RCC_PLLSAIM_DIV_2
6342 * @arg @ref LL_RCC_PLLSAIM_DIV_3
6343 * @arg @ref LL_RCC_PLLSAIM_DIV_4
6344 * @arg @ref LL_RCC_PLLSAIM_DIV_5
6345 * @arg @ref LL_RCC_PLLSAIM_DIV_6
6346 * @arg @ref LL_RCC_PLLSAIM_DIV_7
6347 * @arg @ref LL_RCC_PLLSAIM_DIV_8
6348 * @arg @ref LL_RCC_PLLSAIM_DIV_9
6349 * @arg @ref LL_RCC_PLLSAIM_DIV_10
6350 * @arg @ref LL_RCC_PLLSAIM_DIV_11
6351 * @arg @ref LL_RCC_PLLSAIM_DIV_12
6352 * @arg @ref LL_RCC_PLLSAIM_DIV_13
6353 * @arg @ref LL_RCC_PLLSAIM_DIV_14
6354 * @arg @ref LL_RCC_PLLSAIM_DIV_15
6355 * @arg @ref LL_RCC_PLLSAIM_DIV_16
6356 * @arg @ref LL_RCC_PLLSAIM_DIV_17
6357 * @arg @ref LL_RCC_PLLSAIM_DIV_18
6358 * @arg @ref LL_RCC_PLLSAIM_DIV_19
6359 * @arg @ref LL_RCC_PLLSAIM_DIV_20
6360 * @arg @ref LL_RCC_PLLSAIM_DIV_21
6361 * @arg @ref LL_RCC_PLLSAIM_DIV_22
6362 * @arg @ref LL_RCC_PLLSAIM_DIV_23
6363 * @arg @ref LL_RCC_PLLSAIM_DIV_24
6364 * @arg @ref LL_RCC_PLLSAIM_DIV_25
6365 * @arg @ref LL_RCC_PLLSAIM_DIV_26
6366 * @arg @ref LL_RCC_PLLSAIM_DIV_27
6367 * @arg @ref LL_RCC_PLLSAIM_DIV_28
6368 * @arg @ref LL_RCC_PLLSAIM_DIV_29
6369 * @arg @ref LL_RCC_PLLSAIM_DIV_30
6370 * @arg @ref LL_RCC_PLLSAIM_DIV_31
6371 * @arg @ref LL_RCC_PLLSAIM_DIV_32
6372 * @arg @ref LL_RCC_PLLSAIM_DIV_33
6373 * @arg @ref LL_RCC_PLLSAIM_DIV_34
6374 * @arg @ref LL_RCC_PLLSAIM_DIV_35
6375 * @arg @ref LL_RCC_PLLSAIM_DIV_36
6376 * @arg @ref LL_RCC_PLLSAIM_DIV_37
6377 * @arg @ref LL_RCC_PLLSAIM_DIV_38
6378 * @arg @ref LL_RCC_PLLSAIM_DIV_39
6379 * @arg @ref LL_RCC_PLLSAIM_DIV_40
6380 * @arg @ref LL_RCC_PLLSAIM_DIV_41
6381 * @arg @ref LL_RCC_PLLSAIM_DIV_42
6382 * @arg @ref LL_RCC_PLLSAIM_DIV_43
6383 * @arg @ref LL_RCC_PLLSAIM_DIV_44
6384 * @arg @ref LL_RCC_PLLSAIM_DIV_45
6385 * @arg @ref LL_RCC_PLLSAIM_DIV_46
6386 * @arg @ref LL_RCC_PLLSAIM_DIV_47
6387 * @arg @ref LL_RCC_PLLSAIM_DIV_48
6388 * @arg @ref LL_RCC_PLLSAIM_DIV_49
6389 * @arg @ref LL_RCC_PLLSAIM_DIV_50
6390 * @arg @ref LL_RCC_PLLSAIM_DIV_51
6391 * @arg @ref LL_RCC_PLLSAIM_DIV_52
6392 * @arg @ref LL_RCC_PLLSAIM_DIV_53
6393 * @arg @ref LL_RCC_PLLSAIM_DIV_54
6394 * @arg @ref LL_RCC_PLLSAIM_DIV_55
6395 * @arg @ref LL_RCC_PLLSAIM_DIV_56
6396 * @arg @ref LL_RCC_PLLSAIM_DIV_57
6397 * @arg @ref LL_RCC_PLLSAIM_DIV_58
6398 * @arg @ref LL_RCC_PLLSAIM_DIV_59
6399 * @arg @ref LL_RCC_PLLSAIM_DIV_60
6400 * @arg @ref LL_RCC_PLLSAIM_DIV_61
6401 * @arg @ref LL_RCC_PLLSAIM_DIV_62
6402 * @arg @ref LL_RCC_PLLSAIM_DIV_63
6403 */
6404 __STATIC_INLINE uint32_t LL_RCC_PLLSAI_GetDivider(void)
6405 {
6406 #if defined(RCC_PLLSAICFGR_PLLSAIM)
6407 return (uint32_t)(READ_BIT(RCC->PLLSAICFGR, RCC_PLLSAICFGR_PLLSAIM));
6408 #else
6409 return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM));
6410 #endif /* RCC_PLLSAICFGR_PLLSAIM */
6411 }
6412
6413 /**
6414 * @brief Get SAIPLL multiplication factor for VCO
6415 * @rmtoll PLLSAICFGR PLLSAIN LL_RCC_PLLSAI_GetN
6416 * @retval Between 49/50(*) and 432
6417 *
6418 * (*) value not defined in all devices.
6419 */
6420 __STATIC_INLINE uint32_t LL_RCC_PLLSAI_GetN(void)
6421 {
6422 return (uint32_t)(READ_BIT(RCC->PLLSAICFGR, RCC_PLLSAICFGR_PLLSAIN) >> RCC_PLLSAICFGR_PLLSAIN_Pos);
6423 }
6424
6425 /**
6426 * @brief Get SAIPLL division factor for PLLSAIQ
6427 * @rmtoll PLLSAICFGR PLLSAIQ LL_RCC_PLLSAI_GetQ
6428 * @retval Returned value can be one of the following values:
6429 * @arg @ref LL_RCC_PLLSAIQ_DIV_2
6430 * @arg @ref LL_RCC_PLLSAIQ_DIV_3
6431 * @arg @ref LL_RCC_PLLSAIQ_DIV_4
6432 * @arg @ref LL_RCC_PLLSAIQ_DIV_5
6433 * @arg @ref LL_RCC_PLLSAIQ_DIV_6
6434 * @arg @ref LL_RCC_PLLSAIQ_DIV_7
6435 * @arg @ref LL_RCC_PLLSAIQ_DIV_8
6436 * @arg @ref LL_RCC_PLLSAIQ_DIV_9
6437 * @arg @ref LL_RCC_PLLSAIQ_DIV_10
6438 * @arg @ref LL_RCC_PLLSAIQ_DIV_11
6439 * @arg @ref LL_RCC_PLLSAIQ_DIV_12
6440 * @arg @ref LL_RCC_PLLSAIQ_DIV_13
6441 * @arg @ref LL_RCC_PLLSAIQ_DIV_14
6442 * @arg @ref LL_RCC_PLLSAIQ_DIV_15
6443 */
6444 __STATIC_INLINE uint32_t LL_RCC_PLLSAI_GetQ(void)
6445 {
6446 return (uint32_t)(READ_BIT(RCC->PLLSAICFGR, RCC_PLLSAICFGR_PLLSAIQ));
6447 }
6448
6449 #if defined(RCC_PLLSAICFGR_PLLSAIR)
6450 /**
6451 * @brief Get SAIPLL division factor for PLLSAIR
6452 * @note used for PLLSAICLK (SAI clock)
6453 * @rmtoll PLLSAICFGR PLLSAIR LL_RCC_PLLSAI_GetR
6454 * @retval Returned value can be one of the following values:
6455 * @arg @ref LL_RCC_PLLSAIR_DIV_2
6456 * @arg @ref LL_RCC_PLLSAIR_DIV_3
6457 * @arg @ref LL_RCC_PLLSAIR_DIV_4
6458 * @arg @ref LL_RCC_PLLSAIR_DIV_5
6459 * @arg @ref LL_RCC_PLLSAIR_DIV_6
6460 * @arg @ref LL_RCC_PLLSAIR_DIV_7
6461 */
6462 __STATIC_INLINE uint32_t LL_RCC_PLLSAI_GetR(void)
6463 {
6464 return (uint32_t)(READ_BIT(RCC->PLLSAICFGR, RCC_PLLSAICFGR_PLLSAIR));
6465 }
6466 #endif /* RCC_PLLSAICFGR_PLLSAIR */
6467
6468 #if defined(RCC_PLLSAICFGR_PLLSAIP)
6469 /**
6470 * @brief Get SAIPLL division factor for PLLSAIP
6471 * @note used for PLL48MCLK (48M domain clock)
6472 * @rmtoll PLLSAICFGR PLLSAIP LL_RCC_PLLSAI_GetP
6473 * @retval Returned value can be one of the following values:
6474 * @arg @ref LL_RCC_PLLSAIP_DIV_2
6475 * @arg @ref LL_RCC_PLLSAIP_DIV_4
6476 * @arg @ref LL_RCC_PLLSAIP_DIV_6
6477 * @arg @ref LL_RCC_PLLSAIP_DIV_8
6478 */
6479 __STATIC_INLINE uint32_t LL_RCC_PLLSAI_GetP(void)
6480 {
6481 return (uint32_t)(READ_BIT(RCC->PLLSAICFGR, RCC_PLLSAICFGR_PLLSAIP));
6482 }
6483 #endif /* RCC_PLLSAICFGR_PLLSAIP */
6484
6485 /**
6486 * @brief Get SAIPLL division factor for PLLSAIDIVQ
6487 * @note used PLLSAICLK selected (SAI clock)
6488 * @rmtoll DCKCFGR PLLSAIDIVQ LL_RCC_PLLSAI_GetDIVQ
6489 * @retval Returned value can be one of the following values:
6490 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_1
6491 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_2
6492 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_3
6493 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_4
6494 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_5
6495 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_6
6496 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_7
6497 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_8
6498 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_9
6499 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_10
6500 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_11
6501 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_12
6502 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_13
6503 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_14
6504 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_15
6505 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_16
6506 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_17
6507 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_18
6508 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_19
6509 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_20
6510 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_21
6511 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_22
6512 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_23
6513 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_24
6514 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_25
6515 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_26
6516 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_27
6517 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_28
6518 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_29
6519 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_30
6520 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_31
6521 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_32
6522 */
6523 __STATIC_INLINE uint32_t LL_RCC_PLLSAI_GetDIVQ(void)
6524 {
6525 return (uint32_t)(READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_PLLSAIDIVQ));
6526 }
6527
6528 #if defined(RCC_DCKCFGR_PLLSAIDIVR)
6529 /**
6530 * @brief Get SAIPLL division factor for PLLSAIDIVR
6531 * @note used for LTDC domain clock
6532 * @rmtoll DCKCFGR PLLSAIDIVR LL_RCC_PLLSAI_GetDIVR
6533 * @retval Returned value can be one of the following values:
6534 * @arg @ref LL_RCC_PLLSAIDIVR_DIV_2
6535 * @arg @ref LL_RCC_PLLSAIDIVR_DIV_4
6536 * @arg @ref LL_RCC_PLLSAIDIVR_DIV_8
6537 * @arg @ref LL_RCC_PLLSAIDIVR_DIV_16
6538 */
6539 __STATIC_INLINE uint32_t LL_RCC_PLLSAI_GetDIVR(void)
6540 {
6541 return (uint32_t)(READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_PLLSAIDIVR));
6542 }
6543 #endif /* RCC_DCKCFGR_PLLSAIDIVR */
6544
6545 /**
6546 * @}
6547 */
6548 #endif /* RCC_PLLSAI_SUPPORT */
6549
6550 /** @defgroup RCC_LL_EF_FLAG_Management FLAG Management
6551 * @{
6552 */
6553
6554 /**
6555 * @brief Clear LSI ready interrupt flag
6556 * @rmtoll CIR LSIRDYC LL_RCC_ClearFlag_LSIRDY
6557 * @retval None
6558 */
6559 __STATIC_INLINE void LL_RCC_ClearFlag_LSIRDY(void)
6560 {
6561 SET_BIT(RCC->CIR, RCC_CIR_LSIRDYC);
6562 }
6563
6564 /**
6565 * @brief Clear LSE ready interrupt flag
6566 * @rmtoll CIR LSERDYC LL_RCC_ClearFlag_LSERDY
6567 * @retval None
6568 */
6569 __STATIC_INLINE void LL_RCC_ClearFlag_LSERDY(void)
6570 {
6571 SET_BIT(RCC->CIR, RCC_CIR_LSERDYC);
6572 }
6573
6574 /**
6575 * @brief Clear HSI ready interrupt flag
6576 * @rmtoll CIR HSIRDYC LL_RCC_ClearFlag_HSIRDY
6577 * @retval None
6578 */
6579 __STATIC_INLINE void LL_RCC_ClearFlag_HSIRDY(void)
6580 {
6581 SET_BIT(RCC->CIR, RCC_CIR_HSIRDYC);
6582 }
6583
6584 /**
6585 * @brief Clear HSE ready interrupt flag
6586 * @rmtoll CIR HSERDYC LL_RCC_ClearFlag_HSERDY
6587 * @retval None
6588 */
6589 __STATIC_INLINE void LL_RCC_ClearFlag_HSERDY(void)
6590 {
6591 SET_BIT(RCC->CIR, RCC_CIR_HSERDYC);
6592 }
6593
6594 /**
6595 * @brief Clear PLL ready interrupt flag
6596 * @rmtoll CIR PLLRDYC LL_RCC_ClearFlag_PLLRDY
6597 * @retval None
6598 */
6599 __STATIC_INLINE void LL_RCC_ClearFlag_PLLRDY(void)
6600 {
6601 SET_BIT(RCC->CIR, RCC_CIR_PLLRDYC);
6602 }
6603
6604 #if defined(RCC_PLLI2S_SUPPORT)
6605 /**
6606 * @brief Clear PLLI2S ready interrupt flag
6607 * @rmtoll CIR PLLI2SRDYC LL_RCC_ClearFlag_PLLI2SRDY
6608 * @retval None
6609 */
6610 __STATIC_INLINE void LL_RCC_ClearFlag_PLLI2SRDY(void)
6611 {
6612 SET_BIT(RCC->CIR, RCC_CIR_PLLI2SRDYC);
6613 }
6614
6615 #endif /* RCC_PLLI2S_SUPPORT */
6616
6617 #if defined(RCC_PLLSAI_SUPPORT)
6618 /**
6619 * @brief Clear PLLSAI ready interrupt flag
6620 * @rmtoll CIR PLLSAIRDYC LL_RCC_ClearFlag_PLLSAIRDY
6621 * @retval None
6622 */
6623 __STATIC_INLINE void LL_RCC_ClearFlag_PLLSAIRDY(void)
6624 {
6625 SET_BIT(RCC->CIR, RCC_CIR_PLLSAIRDYC);
6626 }
6627
6628 #endif /* RCC_PLLSAI_SUPPORT */
6629
6630 /**
6631 * @brief Clear Clock security system interrupt flag
6632 * @rmtoll CIR CSSC LL_RCC_ClearFlag_HSECSS
6633 * @retval None
6634 */
6635 __STATIC_INLINE void LL_RCC_ClearFlag_HSECSS(void)
6636 {
6637 SET_BIT(RCC->CIR, RCC_CIR_CSSC);
6638 }
6639
6640 /**
6641 * @brief Check if LSI ready interrupt occurred or not
6642 * @rmtoll CIR LSIRDYF LL_RCC_IsActiveFlag_LSIRDY
6643 * @retval State of bit (1 or 0).
6644 */
6645 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSIRDY(void)
6646 {
6647 return (READ_BIT(RCC->CIR, RCC_CIR_LSIRDYF) == (RCC_CIR_LSIRDYF));
6648 }
6649
6650 /**
6651 * @brief Check if LSE ready interrupt occurred or not
6652 * @rmtoll CIR LSERDYF LL_RCC_IsActiveFlag_LSERDY
6653 * @retval State of bit (1 or 0).
6654 */
6655 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSERDY(void)
6656 {
6657 return (READ_BIT(RCC->CIR, RCC_CIR_LSERDYF) == (RCC_CIR_LSERDYF));
6658 }
6659
6660 /**
6661 * @brief Check if HSI ready interrupt occurred or not
6662 * @rmtoll CIR HSIRDYF LL_RCC_IsActiveFlag_HSIRDY
6663 * @retval State of bit (1 or 0).
6664 */
6665 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSIRDY(void)
6666 {
6667 return (READ_BIT(RCC->CIR, RCC_CIR_HSIRDYF) == (RCC_CIR_HSIRDYF));
6668 }
6669
6670 /**
6671 * @brief Check if HSE ready interrupt occurred or not
6672 * @rmtoll CIR HSERDYF LL_RCC_IsActiveFlag_HSERDY
6673 * @retval State of bit (1 or 0).
6674 */
6675 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSERDY(void)
6676 {
6677 return (READ_BIT(RCC->CIR, RCC_CIR_HSERDYF) == (RCC_CIR_HSERDYF));
6678 }
6679
6680 /**
6681 * @brief Check if PLL ready interrupt occurred or not
6682 * @rmtoll CIR PLLRDYF LL_RCC_IsActiveFlag_PLLRDY
6683 * @retval State of bit (1 or 0).
6684 */
6685 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLLRDY(void)
6686 {
6687 return (READ_BIT(RCC->CIR, RCC_CIR_PLLRDYF) == (RCC_CIR_PLLRDYF));
6688 }
6689
6690 #if defined(RCC_PLLI2S_SUPPORT)
6691 /**
6692 * @brief Check if PLLI2S ready interrupt occurred or not
6693 * @rmtoll CIR PLLI2SRDYF LL_RCC_IsActiveFlag_PLLI2SRDY
6694 * @retval State of bit (1 or 0).
6695 */
6696 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLLI2SRDY(void)
6697 {
6698 return (READ_BIT(RCC->CIR, RCC_CIR_PLLI2SRDYF) == (RCC_CIR_PLLI2SRDYF));
6699 }
6700 #endif /* RCC_PLLI2S_SUPPORT */
6701
6702 #if defined(RCC_PLLSAI_SUPPORT)
6703 /**
6704 * @brief Check if PLLSAI ready interrupt occurred or not
6705 * @rmtoll CIR PLLSAIRDYF LL_RCC_IsActiveFlag_PLLSAIRDY
6706 * @retval State of bit (1 or 0).
6707 */
6708 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLLSAIRDY(void)
6709 {
6710 return (READ_BIT(RCC->CIR, RCC_CIR_PLLSAIRDYF) == (RCC_CIR_PLLSAIRDYF));
6711 }
6712 #endif /* RCC_PLLSAI_SUPPORT */
6713
6714 /**
6715 * @brief Check if Clock security system interrupt occurred or not
6716 * @rmtoll CIR CSSF LL_RCC_IsActiveFlag_HSECSS
6717 * @retval State of bit (1 or 0).
6718 */
6719 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSECSS(void)
6720 {
6721 return (READ_BIT(RCC->CIR, RCC_CIR_CSSF) == (RCC_CIR_CSSF));
6722 }
6723
6724 /**
6725 * @brief Check if RCC flag Independent Watchdog reset is set or not.
6726 * @rmtoll CSR IWDGRSTF LL_RCC_IsActiveFlag_IWDGRST
6727 * @retval State of bit (1 or 0).
6728 */
6729 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_IWDGRST(void)
6730 {
6731 return (READ_BIT(RCC->CSR, RCC_CSR_IWDGRSTF) == (RCC_CSR_IWDGRSTF));
6732 }
6733
6734 /**
6735 * @brief Check if RCC flag Low Power reset is set or not.
6736 * @rmtoll CSR LPWRRSTF LL_RCC_IsActiveFlag_LPWRRST
6737 * @retval State of bit (1 or 0).
6738 */
6739 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LPWRRST(void)
6740 {
6741 return (READ_BIT(RCC->CSR, RCC_CSR_LPWRRSTF) == (RCC_CSR_LPWRRSTF));
6742 }
6743
6744 /**
6745 * @brief Check if RCC flag Pin reset is set or not.
6746 * @rmtoll CSR PINRSTF LL_RCC_IsActiveFlag_PINRST
6747 * @retval State of bit (1 or 0).
6748 */
6749 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PINRST(void)
6750 {
6751 return (READ_BIT(RCC->CSR, RCC_CSR_PINRSTF) == (RCC_CSR_PINRSTF));
6752 }
6753
6754 /**
6755 * @brief Check if RCC flag POR/PDR reset is set or not.
6756 * @rmtoll CSR PORRSTF LL_RCC_IsActiveFlag_PORRST
6757 * @retval State of bit (1 or 0).
6758 */
6759 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PORRST(void)
6760 {
6761 return (READ_BIT(RCC->CSR, RCC_CSR_PORRSTF) == (RCC_CSR_PORRSTF));
6762 }
6763
6764 /**
6765 * @brief Check if RCC flag Software reset is set or not.
6766 * @rmtoll CSR SFTRSTF LL_RCC_IsActiveFlag_SFTRST
6767 * @retval State of bit (1 or 0).
6768 */
6769 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_SFTRST(void)
6770 {
6771 return (READ_BIT(RCC->CSR, RCC_CSR_SFTRSTF) == (RCC_CSR_SFTRSTF));
6772 }
6773
6774 /**
6775 * @brief Check if RCC flag Window Watchdog reset is set or not.
6776 * @rmtoll CSR WWDGRSTF LL_RCC_IsActiveFlag_WWDGRST
6777 * @retval State of bit (1 or 0).
6778 */
6779 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_WWDGRST(void)
6780 {
6781 return (READ_BIT(RCC->CSR, RCC_CSR_WWDGRSTF) == (RCC_CSR_WWDGRSTF));
6782 }
6783
6784 #if defined(RCC_CSR_BORRSTF)
6785 /**
6786 * @brief Check if RCC flag BOR reset is set or not.
6787 * @rmtoll CSR BORRSTF LL_RCC_IsActiveFlag_BORRST
6788 * @retval State of bit (1 or 0).
6789 */
6790 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_BORRST(void)
6791 {
6792 return (READ_BIT(RCC->CSR, RCC_CSR_BORRSTF) == (RCC_CSR_BORRSTF));
6793 }
6794 #endif /* RCC_CSR_BORRSTF */
6795
6796 /**
6797 * @brief Set RMVF bit to clear the reset flags.
6798 * @rmtoll CSR RMVF LL_RCC_ClearResetFlags
6799 * @retval None
6800 */
6801 __STATIC_INLINE void LL_RCC_ClearResetFlags(void)
6802 {
6803 SET_BIT(RCC->CSR, RCC_CSR_RMVF);
6804 }
6805
6806 /**
6807 * @}
6808 */
6809
6810 /** @defgroup RCC_LL_EF_IT_Management IT Management
6811 * @{
6812 */
6813
6814 /**
6815 * @brief Enable LSI ready interrupt
6816 * @rmtoll CIR LSIRDYIE LL_RCC_EnableIT_LSIRDY
6817 * @retval None
6818 */
6819 __STATIC_INLINE void LL_RCC_EnableIT_LSIRDY(void)
6820 {
6821 SET_BIT(RCC->CIR, RCC_CIR_LSIRDYIE);
6822 }
6823
6824 /**
6825 * @brief Enable LSE ready interrupt
6826 * @rmtoll CIR LSERDYIE LL_RCC_EnableIT_LSERDY
6827 * @retval None
6828 */
6829 __STATIC_INLINE void LL_RCC_EnableIT_LSERDY(void)
6830 {
6831 SET_BIT(RCC->CIR, RCC_CIR_LSERDYIE);
6832 }
6833
6834 /**
6835 * @brief Enable HSI ready interrupt
6836 * @rmtoll CIR HSIRDYIE LL_RCC_EnableIT_HSIRDY
6837 * @retval None
6838 */
6839 __STATIC_INLINE void LL_RCC_EnableIT_HSIRDY(void)
6840 {
6841 SET_BIT(RCC->CIR, RCC_CIR_HSIRDYIE);
6842 }
6843
6844 /**
6845 * @brief Enable HSE ready interrupt
6846 * @rmtoll CIR HSERDYIE LL_RCC_EnableIT_HSERDY
6847 * @retval None
6848 */
6849 __STATIC_INLINE void LL_RCC_EnableIT_HSERDY(void)
6850 {
6851 SET_BIT(RCC->CIR, RCC_CIR_HSERDYIE);
6852 }
6853
6854 /**
6855 * @brief Enable PLL ready interrupt
6856 * @rmtoll CIR PLLRDYIE LL_RCC_EnableIT_PLLRDY
6857 * @retval None
6858 */
6859 __STATIC_INLINE void LL_RCC_EnableIT_PLLRDY(void)
6860 {
6861 SET_BIT(RCC->CIR, RCC_CIR_PLLRDYIE);
6862 }
6863
6864 #if defined(RCC_PLLI2S_SUPPORT)
6865 /**
6866 * @brief Enable PLLI2S ready interrupt
6867 * @rmtoll CIR PLLI2SRDYIE LL_RCC_EnableIT_PLLI2SRDY
6868 * @retval None
6869 */
6870 __STATIC_INLINE void LL_RCC_EnableIT_PLLI2SRDY(void)
6871 {
6872 SET_BIT(RCC->CIR, RCC_CIR_PLLI2SRDYIE);
6873 }
6874 #endif /* RCC_PLLI2S_SUPPORT */
6875
6876 #if defined(RCC_PLLSAI_SUPPORT)
6877 /**
6878 * @brief Enable PLLSAI ready interrupt
6879 * @rmtoll CIR PLLSAIRDYIE LL_RCC_EnableIT_PLLSAIRDY
6880 * @retval None
6881 */
6882 __STATIC_INLINE void LL_RCC_EnableIT_PLLSAIRDY(void)
6883 {
6884 SET_BIT(RCC->CIR, RCC_CIR_PLLSAIRDYIE);
6885 }
6886 #endif /* RCC_PLLSAI_SUPPORT */
6887
6888 /**
6889 * @brief Disable LSI ready interrupt
6890 * @rmtoll CIR LSIRDYIE LL_RCC_DisableIT_LSIRDY
6891 * @retval None
6892 */
6893 __STATIC_INLINE void LL_RCC_DisableIT_LSIRDY(void)
6894 {
6895 CLEAR_BIT(RCC->CIR, RCC_CIR_LSIRDYIE);
6896 }
6897
6898 /**
6899 * @brief Disable LSE ready interrupt
6900 * @rmtoll CIR LSERDYIE LL_RCC_DisableIT_LSERDY
6901 * @retval None
6902 */
6903 __STATIC_INLINE void LL_RCC_DisableIT_LSERDY(void)
6904 {
6905 CLEAR_BIT(RCC->CIR, RCC_CIR_LSERDYIE);
6906 }
6907
6908 /**
6909 * @brief Disable HSI ready interrupt
6910 * @rmtoll CIR HSIRDYIE LL_RCC_DisableIT_HSIRDY
6911 * @retval None
6912 */
6913 __STATIC_INLINE void LL_RCC_DisableIT_HSIRDY(void)
6914 {
6915 CLEAR_BIT(RCC->CIR, RCC_CIR_HSIRDYIE);
6916 }
6917
6918 /**
6919 * @brief Disable HSE ready interrupt
6920 * @rmtoll CIR HSERDYIE LL_RCC_DisableIT_HSERDY
6921 * @retval None
6922 */
6923 __STATIC_INLINE void LL_RCC_DisableIT_HSERDY(void)
6924 {
6925 CLEAR_BIT(RCC->CIR, RCC_CIR_HSERDYIE);
6926 }
6927
6928 /**
6929 * @brief Disable PLL ready interrupt
6930 * @rmtoll CIR PLLRDYIE LL_RCC_DisableIT_PLLRDY
6931 * @retval None
6932 */
6933 __STATIC_INLINE void LL_RCC_DisableIT_PLLRDY(void)
6934 {
6935 CLEAR_BIT(RCC->CIR, RCC_CIR_PLLRDYIE);
6936 }
6937
6938 #if defined(RCC_PLLI2S_SUPPORT)
6939 /**
6940 * @brief Disable PLLI2S ready interrupt
6941 * @rmtoll CIR PLLI2SRDYIE LL_RCC_DisableIT_PLLI2SRDY
6942 * @retval None
6943 */
6944 __STATIC_INLINE void LL_RCC_DisableIT_PLLI2SRDY(void)
6945 {
6946 CLEAR_BIT(RCC->CIR, RCC_CIR_PLLI2SRDYIE);
6947 }
6948
6949 #endif /* RCC_PLLI2S_SUPPORT */
6950
6951 #if defined(RCC_PLLSAI_SUPPORT)
6952 /**
6953 * @brief Disable PLLSAI ready interrupt
6954 * @rmtoll CIR PLLSAIRDYIE LL_RCC_DisableIT_PLLSAIRDY
6955 * @retval None
6956 */
6957 __STATIC_INLINE void LL_RCC_DisableIT_PLLSAIRDY(void)
6958 {
6959 CLEAR_BIT(RCC->CIR, RCC_CIR_PLLSAIRDYIE);
6960 }
6961 #endif /* RCC_PLLSAI_SUPPORT */
6962
6963 /**
6964 * @brief Checks if LSI ready interrupt source is enabled or disabled.
6965 * @rmtoll CIR LSIRDYIE LL_RCC_IsEnabledIT_LSIRDY
6966 * @retval State of bit (1 or 0).
6967 */
6968 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSIRDY(void)
6969 {
6970 return (READ_BIT(RCC->CIR, RCC_CIR_LSIRDYIE) == (RCC_CIR_LSIRDYIE));
6971 }
6972
6973 /**
6974 * @brief Checks if LSE ready interrupt source is enabled or disabled.
6975 * @rmtoll CIR LSERDYIE LL_RCC_IsEnabledIT_LSERDY
6976 * @retval State of bit (1 or 0).
6977 */
6978 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSERDY(void)
6979 {
6980 return (READ_BIT(RCC->CIR, RCC_CIR_LSERDYIE) == (RCC_CIR_LSERDYIE));
6981 }
6982
6983 /**
6984 * @brief Checks if HSI ready interrupt source is enabled or disabled.
6985 * @rmtoll CIR HSIRDYIE LL_RCC_IsEnabledIT_HSIRDY
6986 * @retval State of bit (1 or 0).
6987 */
6988 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSIRDY(void)
6989 {
6990 return (READ_BIT(RCC->CIR, RCC_CIR_HSIRDYIE) == (RCC_CIR_HSIRDYIE));
6991 }
6992
6993 /**
6994 * @brief Checks if HSE ready interrupt source is enabled or disabled.
6995 * @rmtoll CIR HSERDYIE LL_RCC_IsEnabledIT_HSERDY
6996 * @retval State of bit (1 or 0).
6997 */
6998 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSERDY(void)
6999 {
7000 return (READ_BIT(RCC->CIR, RCC_CIR_HSERDYIE) == (RCC_CIR_HSERDYIE));
7001 }
7002
7003 /**
7004 * @brief Checks if PLL ready interrupt source is enabled or disabled.
7005 * @rmtoll CIR PLLRDYIE LL_RCC_IsEnabledIT_PLLRDY
7006 * @retval State of bit (1 or 0).
7007 */
7008 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLLRDY(void)
7009 {
7010 return (READ_BIT(RCC->CIR, RCC_CIR_PLLRDYIE) == (RCC_CIR_PLLRDYIE));
7011 }
7012
7013 #if defined(RCC_PLLI2S_SUPPORT)
7014 /**
7015 * @brief Checks if PLLI2S ready interrupt source is enabled or disabled.
7016 * @rmtoll CIR PLLI2SRDYIE LL_RCC_IsEnabledIT_PLLI2SRDY
7017 * @retval State of bit (1 or 0).
7018 */
7019 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLLI2SRDY(void)
7020 {
7021 return (READ_BIT(RCC->CIR, RCC_CIR_PLLI2SRDYIE) == (RCC_CIR_PLLI2SRDYIE));
7022 }
7023
7024 #endif /* RCC_PLLI2S_SUPPORT */
7025
7026 #if defined(RCC_PLLSAI_SUPPORT)
7027 /**
7028 * @brief Checks if PLLSAI ready interrupt source is enabled or disabled.
7029 * @rmtoll CIR PLLSAIRDYIE LL_RCC_IsEnabledIT_PLLSAIRDY
7030 * @retval State of bit (1 or 0).
7031 */
7032 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLLSAIRDY(void)
7033 {
7034 return (READ_BIT(RCC->CIR, RCC_CIR_PLLSAIRDYIE) == (RCC_CIR_PLLSAIRDYIE));
7035 }
7036 #endif /* RCC_PLLSAI_SUPPORT */
7037
7038 /**
7039 * @}
7040 */
7041
7042 #if defined(USE_FULL_LL_DRIVER)
7043 /** @defgroup RCC_LL_EF_Init De-initialization function
7044 * @{
7045 */
7046 ErrorStatus LL_RCC_DeInit(void);
7047 /**
7048 * @}
7049 */
7050
7051 /** @defgroup RCC_LL_EF_Get_Freq Get system and peripherals clocks frequency functions
7052 * @{
7053 */
7054 void LL_RCC_GetSystemClocksFreq(LL_RCC_ClocksTypeDef *RCC_Clocks);
7055 #if defined(FMPI2C1)
7056 uint32_t LL_RCC_GetFMPI2CClockFreq(uint32_t FMPI2CxSource);
7057 #endif /* FMPI2C1 */
7058 #if defined(LPTIM1)
7059 uint32_t LL_RCC_GetLPTIMClockFreq(uint32_t LPTIMxSource);
7060 #endif /* LPTIM1 */
7061 #if defined(SAI1)
7062 uint32_t LL_RCC_GetSAIClockFreq(uint32_t SAIxSource);
7063 #endif /* SAI1 */
7064 #if defined(SDIO)
7065 uint32_t LL_RCC_GetSDIOClockFreq(uint32_t SDIOxSource);
7066 #endif /* SDIO */
7067 #if defined(RNG)
7068 uint32_t LL_RCC_GetRNGClockFreq(uint32_t RNGxSource);
7069 #endif /* RNG */
7070 #if defined(USB_OTG_FS) || defined(USB_OTG_HS)
7071 uint32_t LL_RCC_GetUSBClockFreq(uint32_t USBxSource);
7072 #endif /* USB_OTG_FS || USB_OTG_HS */
7073 #if defined(DFSDM1_Channel0)
7074 uint32_t LL_RCC_GetDFSDMClockFreq(uint32_t DFSDMxSource);
7075 uint32_t LL_RCC_GetDFSDMAudioClockFreq(uint32_t DFSDMxSource);
7076 #endif /* DFSDM1_Channel0 */
7077 uint32_t LL_RCC_GetI2SClockFreq(uint32_t I2SxSource);
7078 #if defined(CEC)
7079 uint32_t LL_RCC_GetCECClockFreq(uint32_t CECxSource);
7080 #endif /* CEC */
7081 #if defined(LTDC)
7082 uint32_t LL_RCC_GetLTDCClockFreq(uint32_t LTDCxSource);
7083 #endif /* LTDC */
7084 #if defined(SPDIFRX)
7085 uint32_t LL_RCC_GetSPDIFRXClockFreq(uint32_t SPDIFRXxSource);
7086 #endif /* SPDIFRX */
7087 #if defined(DSI)
7088 uint32_t LL_RCC_GetDSIClockFreq(uint32_t DSIxSource);
7089 #endif /* DSI */
7090 /**
7091 * @}
7092 */
7093 #endif /* USE_FULL_LL_DRIVER */
7094
7095 /**
7096 * @}
7097 */
7098
7099 /**
7100 * @}
7101 */
7102
7103 #endif /* defined(RCC) */
7104
7105 /**
7106 * @}
7107 */
7108
7109 #ifdef __cplusplus
7110 }
7111 #endif
7112
7113 #endif /* __STM32F4xx_LL_RCC_H */
7114
7115 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/