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comparison Common/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_bus.h @ 160:e3ca52b8e7fa

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Merge with FlipDisplay
author heinrichsweikamp
date Thu, 07 Mar 2019 15:06:43 +0100
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80:cc2bb7bb8456 160:e3ca52b8e7fa
1 /**
2 ******************************************************************************
3 * @file stm32f4xx_ll_bus.h
4 * @author MCD Application Team
5 * @brief Header file of BUS LL module.
6
7 @verbatim
8 ##### RCC Limitations #####
9 ==============================================================================
10 [..]
11 A delay between an RCC peripheral clock enable and the effective peripheral
12 enabling should be taken into account in order to manage the peripheral read/write
13 from/to registers.
14 (+) This delay depends on the peripheral mapping.
15 (++) AHB & APB peripherals, 1 dummy read is necessary
16
17 [..]
18 Workarounds:
19 (#) For AHB & APB peripherals, a dummy read to the peripheral register has been
20 inserted in each LL_{BUS}_GRP{x}_EnableClock() function.
21
22 @endverbatim
23 ******************************************************************************
24 * @attention
25 *
26 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
27 *
28 * Redistribution and use in source and binary forms, with or without modification,
29 * are permitted provided that the following conditions are met:
30 * 1. Redistributions of source code must retain the above copyright notice,
31 * this list of conditions and the following disclaimer.
32 * 2. Redistributions in binary form must reproduce the above copyright notice,
33 * this list of conditions and the following disclaimer in the documentation
34 * and/or other materials provided with the distribution.
35 * 3. Neither the name of STMicroelectronics nor the names of its contributors
36 * may be used to endorse or promote products derived from this software
37 * without specific prior written permission.
38 *
39 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
40 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
41 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
42 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
43 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
44 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
45 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
46 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
47 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
48 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
49 *
50 ******************************************************************************
51 */
52
53 /* Define to prevent recursive inclusion -------------------------------------*/
54 #ifndef __STM32F4xx_LL_BUS_H
55 #define __STM32F4xx_LL_BUS_H
56
57 #ifdef __cplusplus
58 extern "C" {
59 #endif
60
61 /* Includes ------------------------------------------------------------------*/
62 #include "stm32f4xx.h"
63
64 /** @addtogroup STM32F4xx_LL_Driver
65 * @{
66 */
67
68 #if defined(RCC)
69
70 /** @defgroup BUS_LL BUS
71 * @{
72 */
73
74 /* Private types -------------------------------------------------------------*/
75 /* Private variables ---------------------------------------------------------*/
76 /* Private constants ---------------------------------------------------------*/
77 /* Private macros ------------------------------------------------------------*/
78 /* Exported types ------------------------------------------------------------*/
79 /* Exported constants --------------------------------------------------------*/
80 /** @defgroup BUS_LL_Exported_Constants BUS Exported Constants
81 * @{
82 */
83
84 /** @defgroup BUS_LL_EC_AHB1_GRP1_PERIPH AHB1 GRP1 PERIPH
85 * @{
86 */
87 #define LL_AHB1_GRP1_PERIPH_ALL 0xFFFFFFFFU
88 #define LL_AHB1_GRP1_PERIPH_GPIOA RCC_AHB1ENR_GPIOAEN
89 #define LL_AHB1_GRP1_PERIPH_GPIOB RCC_AHB1ENR_GPIOBEN
90 #define LL_AHB1_GRP1_PERIPH_GPIOC RCC_AHB1ENR_GPIOCEN
91 #if defined(GPIOD)
92 #define LL_AHB1_GRP1_PERIPH_GPIOD RCC_AHB1ENR_GPIODEN
93 #endif /* GPIOD */
94 #if defined(GPIOE)
95 #define LL_AHB1_GRP1_PERIPH_GPIOE RCC_AHB1ENR_GPIOEEN
96 #endif /* GPIOE */
97 #if defined(GPIOF)
98 #define LL_AHB1_GRP1_PERIPH_GPIOF RCC_AHB1ENR_GPIOFEN
99 #endif /* GPIOF */
100 #if defined(GPIOG)
101 #define LL_AHB1_GRP1_PERIPH_GPIOG RCC_AHB1ENR_GPIOGEN
102 #endif /* GPIOG */
103 #if defined(GPIOH)
104 #define LL_AHB1_GRP1_PERIPH_GPIOH RCC_AHB1ENR_GPIOHEN
105 #endif /* GPIOH */
106 #if defined(GPIOI)
107 #define LL_AHB1_GRP1_PERIPH_GPIOI RCC_AHB1ENR_GPIOIEN
108 #endif /* GPIOI */
109 #if defined(GPIOJ)
110 #define LL_AHB1_GRP1_PERIPH_GPIOJ RCC_AHB1ENR_GPIOJEN
111 #endif /* GPIOJ */
112 #if defined(GPIOK)
113 #define LL_AHB1_GRP1_PERIPH_GPIOK RCC_AHB1ENR_GPIOKEN
114 #endif /* GPIOK */
115 #define LL_AHB1_GRP1_PERIPH_CRC RCC_AHB1ENR_CRCEN
116 #if defined(RCC_AHB1ENR_BKPSRAMEN)
117 #define LL_AHB1_GRP1_PERIPH_BKPSRAM RCC_AHB1ENR_BKPSRAMEN
118 #endif /* RCC_AHB1ENR_BKPSRAMEN */
119 #if defined(RCC_AHB1ENR_CCMDATARAMEN)
120 #define LL_AHB1_GRP1_PERIPH_CCMDATARAM RCC_AHB1ENR_CCMDATARAMEN
121 #endif /* RCC_AHB1ENR_CCMDATARAMEN */
122 #define LL_AHB1_GRP1_PERIPH_DMA1 RCC_AHB1ENR_DMA1EN
123 #define LL_AHB1_GRP1_PERIPH_DMA2 RCC_AHB1ENR_DMA2EN
124 #if defined(RCC_AHB1ENR_RNGEN)
125 #define LL_AHB1_GRP1_PERIPH_RNG RCC_AHB1ENR_RNGEN
126 #endif /* RCC_AHB1ENR_RNGEN */
127 #if defined(DMA2D)
128 #define LL_AHB1_GRP1_PERIPH_DMA2D RCC_AHB1ENR_DMA2DEN
129 #endif /* DMA2D */
130 #if defined(ETH)
131 #define LL_AHB1_GRP1_PERIPH_ETHMAC RCC_AHB1ENR_ETHMACEN
132 #define LL_AHB1_GRP1_PERIPH_ETHMACTX RCC_AHB1ENR_ETHMACTXEN
133 #define LL_AHB1_GRP1_PERIPH_ETHMACRX RCC_AHB1ENR_ETHMACRXEN
134 #define LL_AHB1_GRP1_PERIPH_ETHMACPTP RCC_AHB1ENR_ETHMACPTPEN
135 #endif /* ETH */
136 #if defined(USB_OTG_HS)
137 #define LL_AHB1_GRP1_PERIPH_OTGHS RCC_AHB1ENR_OTGHSEN
138 #define LL_AHB1_GRP1_PERIPH_OTGHSULPI RCC_AHB1ENR_OTGHSULPIEN
139 #endif /* USB_OTG_HS */
140 #define LL_AHB1_GRP1_PERIPH_FLITF RCC_AHB1LPENR_FLITFLPEN
141 #define LL_AHB1_GRP1_PERIPH_SRAM1 RCC_AHB1LPENR_SRAM1LPEN
142 #if defined(RCC_AHB1LPENR_SRAM2LPEN)
143 #define LL_AHB1_GRP1_PERIPH_SRAM2 RCC_AHB1LPENR_SRAM2LPEN
144 #endif /* RCC_AHB1LPENR_SRAM2LPEN */
145 #if defined(RCC_AHB1LPENR_SRAM3LPEN)
146 #define LL_AHB1_GRP1_PERIPH_SRAM3 RCC_AHB1LPENR_SRAM3LPEN
147 #endif /* RCC_AHB1LPENR_SRAM3LPEN */
148 /**
149 * @}
150 */
151
152 #if defined(RCC_AHB2_SUPPORT)
153 /** @defgroup BUS_LL_EC_AHB2_GRP1_PERIPH AHB2 GRP1 PERIPH
154 * @{
155 */
156 #define LL_AHB2_GRP1_PERIPH_ALL 0xFFFFFFFFU
157 #if defined(DCMI)
158 #define LL_AHB2_GRP1_PERIPH_DCMI RCC_AHB2ENR_DCMIEN
159 #endif /* DCMI */
160 #if defined(CRYP)
161 #define LL_AHB2_GRP1_PERIPH_CRYP RCC_AHB2ENR_CRYPEN
162 #endif /* CRYP */
163 #if defined(AES)
164 #define LL_AHB2_GRP1_PERIPH_AES RCC_AHB2ENR_AESEN
165 #endif /* AES */
166 #if defined(HASH)
167 #define LL_AHB2_GRP1_PERIPH_HASH RCC_AHB2ENR_HASHEN
168 #endif /* HASH */
169 #if defined(RCC_AHB2ENR_RNGEN)
170 #define LL_AHB2_GRP1_PERIPH_RNG RCC_AHB2ENR_RNGEN
171 #endif /* RCC_AHB2ENR_RNGEN */
172 #if defined(USB_OTG_FS)
173 #define LL_AHB2_GRP1_PERIPH_OTGFS RCC_AHB2ENR_OTGFSEN
174 #endif /* USB_OTG_FS */
175 /**
176 * @}
177 */
178 #endif /* RCC_AHB2_SUPPORT */
179
180 #if defined(RCC_AHB3_SUPPORT)
181 /** @defgroup BUS_LL_EC_AHB3_GRP1_PERIPH AHB3 GRP1 PERIPH
182 * @{
183 */
184 #define LL_AHB3_GRP1_PERIPH_ALL 0xFFFFFFFFU
185 #if defined(FSMC_Bank1)
186 #define LL_AHB3_GRP1_PERIPH_FSMC RCC_AHB3ENR_FSMCEN
187 #endif /* FSMC_Bank1 */
188 #if defined(FMC_Bank1)
189 #define LL_AHB3_GRP1_PERIPH_FMC RCC_AHB3ENR_FMCEN
190 #endif /* FMC_Bank1 */
191 #if defined(QUADSPI)
192 #define LL_AHB3_GRP1_PERIPH_QSPI RCC_AHB3ENR_QSPIEN
193 #endif /* QUADSPI */
194 /**
195 * @}
196 */
197 #endif /* RCC_AHB3_SUPPORT */
198
199 /** @defgroup BUS_LL_EC_APB1_GRP1_PERIPH APB1 GRP1 PERIPH
200 * @{
201 */
202 #define LL_APB1_GRP1_PERIPH_ALL 0xFFFFFFFFU
203 #if defined(TIM2)
204 #define LL_APB1_GRP1_PERIPH_TIM2 RCC_APB1ENR_TIM2EN
205 #endif /* TIM2 */
206 #if defined(TIM3)
207 #define LL_APB1_GRP1_PERIPH_TIM3 RCC_APB1ENR_TIM3EN
208 #endif /* TIM3 */
209 #if defined(TIM4)
210 #define LL_APB1_GRP1_PERIPH_TIM4 RCC_APB1ENR_TIM4EN
211 #endif /* TIM4 */
212 #define LL_APB1_GRP1_PERIPH_TIM5 RCC_APB1ENR_TIM5EN
213 #if defined(TIM6)
214 #define LL_APB1_GRP1_PERIPH_TIM6 RCC_APB1ENR_TIM6EN
215 #endif /* TIM6 */
216 #if defined(TIM7)
217 #define LL_APB1_GRP1_PERIPH_TIM7 RCC_APB1ENR_TIM7EN
218 #endif /* TIM7 */
219 #if defined(TIM12)
220 #define LL_APB1_GRP1_PERIPH_TIM12 RCC_APB1ENR_TIM12EN
221 #endif /* TIM12 */
222 #if defined(TIM13)
223 #define LL_APB1_GRP1_PERIPH_TIM13 RCC_APB1ENR_TIM13EN
224 #endif /* TIM13 */
225 #if defined(TIM14)
226 #define LL_APB1_GRP1_PERIPH_TIM14 RCC_APB1ENR_TIM14EN
227 #endif /* TIM14 */
228 #if defined(LPTIM1)
229 #define LL_APB1_GRP1_PERIPH_LPTIM1 RCC_APB1ENR_LPTIM1EN
230 #endif /* LPTIM1 */
231 #if defined(RCC_APB1ENR_RTCAPBEN)
232 #define LL_APB1_GRP1_PERIPH_RTCAPB RCC_APB1ENR_RTCAPBEN
233 #endif /* RCC_APB1ENR_RTCAPBEN */
234 #define LL_APB1_GRP1_PERIPH_WWDG RCC_APB1ENR_WWDGEN
235 #if defined(SPI2)
236 #define LL_APB1_GRP1_PERIPH_SPI2 RCC_APB1ENR_SPI2EN
237 #endif /* SPI2 */
238 #if defined(SPI3)
239 #define LL_APB1_GRP1_PERIPH_SPI3 RCC_APB1ENR_SPI3EN
240 #endif /* SPI3 */
241 #if defined(SPDIFRX)
242 #define LL_APB1_GRP1_PERIPH_SPDIFRX RCC_APB1ENR_SPDIFRXEN
243 #endif /* SPDIFRX */
244 #define LL_APB1_GRP1_PERIPH_USART2 RCC_APB1ENR_USART2EN
245 #if defined(USART3)
246 #define LL_APB1_GRP1_PERIPH_USART3 RCC_APB1ENR_USART3EN
247 #endif /* USART3 */
248 #if defined(UART4)
249 #define LL_APB1_GRP1_PERIPH_UART4 RCC_APB1ENR_UART4EN
250 #endif /* UART4 */
251 #if defined(UART5)
252 #define LL_APB1_GRP1_PERIPH_UART5 RCC_APB1ENR_UART5EN
253 #endif /* UART5 */
254 #define LL_APB1_GRP1_PERIPH_I2C1 RCC_APB1ENR_I2C1EN
255 #define LL_APB1_GRP1_PERIPH_I2C2 RCC_APB1ENR_I2C2EN
256 #if defined(I2C3)
257 #define LL_APB1_GRP1_PERIPH_I2C3 RCC_APB1ENR_I2C3EN
258 #endif /* I2C3 */
259 #if defined(FMPI2C1)
260 #define LL_APB1_GRP1_PERIPH_FMPI2C1 RCC_APB1ENR_FMPI2C1EN
261 #endif /* FMPI2C1 */
262 #if defined(CAN1)
263 #define LL_APB1_GRP1_PERIPH_CAN1 RCC_APB1ENR_CAN1EN
264 #endif /* CAN1 */
265 #if defined(CAN2)
266 #define LL_APB1_GRP1_PERIPH_CAN2 RCC_APB1ENR_CAN2EN
267 #endif /* CAN2 */
268 #if defined(CAN3)
269 #define LL_APB1_GRP1_PERIPH_CAN3 RCC_APB1ENR_CAN3EN
270 #endif /* CAN3 */
271 #if defined(CEC)
272 #define LL_APB1_GRP1_PERIPH_CEC RCC_APB1ENR_CECEN
273 #endif /* CEC */
274 #define LL_APB1_GRP1_PERIPH_PWR RCC_APB1ENR_PWREN
275 #if defined(DAC1)
276 #define LL_APB1_GRP1_PERIPH_DAC1 RCC_APB1ENR_DACEN
277 #endif /* DAC1 */
278 #if defined(UART7)
279 #define LL_APB1_GRP1_PERIPH_UART7 RCC_APB1ENR_UART7EN
280 #endif /* UART7 */
281 #if defined(UART8)
282 #define LL_APB1_GRP1_PERIPH_UART8 RCC_APB1ENR_UART8EN
283 #endif /* UART8 */
284 /**
285 * @}
286 */
287
288 /** @defgroup BUS_LL_EC_APB2_GRP1_PERIPH APB2 GRP1 PERIPH
289 * @{
290 */
291 #define LL_APB2_GRP1_PERIPH_ALL 0xFFFFFFFFU
292 #define LL_APB2_GRP1_PERIPH_TIM1 RCC_APB2ENR_TIM1EN
293 #if defined(TIM8)
294 #define LL_APB2_GRP1_PERIPH_TIM8 RCC_APB2ENR_TIM8EN
295 #endif /* TIM8 */
296 #define LL_APB2_GRP1_PERIPH_USART1 RCC_APB2ENR_USART1EN
297 #if defined(USART6)
298 #define LL_APB2_GRP1_PERIPH_USART6 RCC_APB2ENR_USART6EN
299 #endif /* USART6 */
300 #if defined(UART9)
301 #define LL_APB2_GRP1_PERIPH_UART9 RCC_APB2ENR_UART9EN
302 #endif /* UART9 */
303 #if defined(UART10)
304 #define LL_APB2_GRP1_PERIPH_UART10 RCC_APB2ENR_UART10EN
305 #endif /* UART10 */
306 #define LL_APB2_GRP1_PERIPH_ADC1 RCC_APB2ENR_ADC1EN
307 #if defined(ADC2)
308 #define LL_APB2_GRP1_PERIPH_ADC2 RCC_APB2ENR_ADC2EN
309 #endif /* ADC2 */
310 #if defined(ADC3)
311 #define LL_APB2_GRP1_PERIPH_ADC3 RCC_APB2ENR_ADC3EN
312 #endif /* ADC3 */
313 #if defined(SDIO)
314 #define LL_APB2_GRP1_PERIPH_SDIO RCC_APB2ENR_SDIOEN
315 #endif /* SDIO */
316 #define LL_APB2_GRP1_PERIPH_SPI1 RCC_APB2ENR_SPI1EN
317 #if defined(SPI4)
318 #define LL_APB2_GRP1_PERIPH_SPI4 RCC_APB2ENR_SPI4EN
319 #endif /* SPI4 */
320 #define LL_APB2_GRP1_PERIPH_SYSCFG RCC_APB2ENR_SYSCFGEN
321 #if defined(RCC_APB2ENR_EXTITEN)
322 #define LL_APB2_GRP1_PERIPH_EXTI RCC_APB2ENR_EXTITEN
323 #endif /* RCC_APB2ENR_EXTITEN */
324 #define LL_APB2_GRP1_PERIPH_TIM9 RCC_APB2ENR_TIM9EN
325 #if defined(TIM10)
326 #define LL_APB2_GRP1_PERIPH_TIM10 RCC_APB2ENR_TIM10EN
327 #endif /* TIM10 */
328 #define LL_APB2_GRP1_PERIPH_TIM11 RCC_APB2ENR_TIM11EN
329 #if defined(SPI5)
330 #define LL_APB2_GRP1_PERIPH_SPI5 RCC_APB2ENR_SPI5EN
331 #endif /* SPI5 */
332 #if defined(SPI6)
333 #define LL_APB2_GRP1_PERIPH_SPI6 RCC_APB2ENR_SPI6EN
334 #endif /* SPI6 */
335 #if defined(SAI1)
336 #define LL_APB2_GRP1_PERIPH_SAI1 RCC_APB2ENR_SAI1EN
337 #endif /* SAI1 */
338 #if defined(SAI2)
339 #define LL_APB2_GRP1_PERIPH_SAI2 RCC_APB2ENR_SAI2EN
340 #endif /* SAI2 */
341 #if defined(LTDC)
342 #define LL_APB2_GRP1_PERIPH_LTDC RCC_APB2ENR_LTDCEN
343 #endif /* LTDC */
344 #if defined(DSI)
345 #define LL_APB2_GRP1_PERIPH_DSI RCC_APB2ENR_DSIEN
346 #endif /* DSI */
347 #if defined(DFSDM1_Channel0)
348 #define LL_APB2_GRP1_PERIPH_DFSDM1 RCC_APB2ENR_DFSDM1EN
349 #endif /* DFSDM1_Channel0 */
350 #if defined(DFSDM2_Channel0)
351 #define LL_APB2_GRP1_PERIPH_DFSDM2 RCC_APB2ENR_DFSDM2EN
352 #endif /* DFSDM2_Channel0 */
353 #define LL_APB2_GRP1_PERIPH_ADC RCC_APB2RSTR_ADCRST
354 /**
355 * @}
356 */
357
358 /**
359 * @}
360 */
361
362 /* Exported macro ------------------------------------------------------------*/
363 /* Exported functions --------------------------------------------------------*/
364 /** @defgroup BUS_LL_Exported_Functions BUS Exported Functions
365 * @{
366 */
367
368 /** @defgroup BUS_LL_EF_AHB1 AHB1
369 * @{
370 */
371
372 /**
373 * @brief Enable AHB1 peripherals clock.
374 * @rmtoll AHB1ENR GPIOAEN LL_AHB1_GRP1_EnableClock\n
375 * AHB1ENR GPIOBEN LL_AHB1_GRP1_EnableClock\n
376 * AHB1ENR GPIOCEN LL_AHB1_GRP1_EnableClock\n
377 * AHB1ENR GPIODEN LL_AHB1_GRP1_EnableClock\n
378 * AHB1ENR GPIOEEN LL_AHB1_GRP1_EnableClock\n
379 * AHB1ENR GPIOFEN LL_AHB1_GRP1_EnableClock\n
380 * AHB1ENR GPIOGEN LL_AHB1_GRP1_EnableClock\n
381 * AHB1ENR GPIOHEN LL_AHB1_GRP1_EnableClock\n
382 * AHB1ENR GPIOIEN LL_AHB1_GRP1_EnableClock\n
383 * AHB1ENR GPIOJEN LL_AHB1_GRP1_EnableClock\n
384 * AHB1ENR GPIOKEN LL_AHB1_GRP1_EnableClock\n
385 * AHB1ENR CRCEN LL_AHB1_GRP1_EnableClock\n
386 * AHB1ENR BKPSRAMEN LL_AHB1_GRP1_EnableClock\n
387 * AHB1ENR CCMDATARAMEN LL_AHB1_GRP1_EnableClock\n
388 * AHB1ENR DMA1EN LL_AHB1_GRP1_EnableClock\n
389 * AHB1ENR DMA2EN LL_AHB1_GRP1_EnableClock\n
390 * AHB1ENR RNGEN LL_AHB1_GRP1_EnableClock\n
391 * AHB1ENR DMA2DEN LL_AHB1_GRP1_EnableClock\n
392 * AHB1ENR ETHMACEN LL_AHB1_GRP1_EnableClock\n
393 * AHB1ENR ETHMACTXEN LL_AHB1_GRP1_EnableClock\n
394 * AHB1ENR ETHMACRXEN LL_AHB1_GRP1_EnableClock\n
395 * AHB1ENR ETHMACPTPEN LL_AHB1_GRP1_EnableClock\n
396 * AHB1ENR OTGHSEN LL_AHB1_GRP1_EnableClock\n
397 * AHB1ENR OTGHSULPIEN LL_AHB1_GRP1_EnableClock
398 * @param Periphs This parameter can be a combination of the following values:
399 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA
400 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB
401 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC
402 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD (*)
403 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*)
404 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF (*)
405 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG (*)
406 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH (*)
407 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOI (*)
408 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOJ (*)
409 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOK (*)
410 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
411 * @arg @ref LL_AHB1_GRP1_PERIPH_BKPSRAM (*)
412 * @arg @ref LL_AHB1_GRP1_PERIPH_CCMDATARAM (*)
413 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
414 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
415 * @arg @ref LL_AHB1_GRP1_PERIPH_RNG (*)
416 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*)
417 * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*)
418 * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACTX (*)
419 * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACRX (*)
420 * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACPTP (*)
421 * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHS (*)
422 * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHSULPI (*)
423 *
424 * (*) value not defined in all devices.
425 * @retval None
426 */
427 __STATIC_INLINE void LL_AHB1_GRP1_EnableClock(uint32_t Periphs)
428 {
429 __IO uint32_t tmpreg;
430 SET_BIT(RCC->AHB1ENR, Periphs);
431 /* Delay after an RCC peripheral clock enabling */
432 tmpreg = READ_BIT(RCC->AHB1ENR, Periphs);
433 (void)tmpreg;
434 }
435
436 /**
437 * @brief Check if AHB1 peripheral clock is enabled or not
438 * @rmtoll AHB1ENR GPIOAEN LL_AHB1_GRP1_IsEnabledClock\n
439 * AHB1ENR GPIOBEN LL_AHB1_GRP1_IsEnabledClock\n
440 * AHB1ENR GPIOCEN LL_AHB1_GRP1_IsEnabledClock\n
441 * AHB1ENR GPIODEN LL_AHB1_GRP1_IsEnabledClock\n
442 * AHB1ENR GPIOEEN LL_AHB1_GRP1_IsEnabledClock\n
443 * AHB1ENR GPIOFEN LL_AHB1_GRP1_IsEnabledClock\n
444 * AHB1ENR GPIOGEN LL_AHB1_GRP1_IsEnabledClock\n
445 * AHB1ENR GPIOHEN LL_AHB1_GRP1_IsEnabledClock\n
446 * AHB1ENR GPIOIEN LL_AHB1_GRP1_IsEnabledClock\n
447 * AHB1ENR GPIOJEN LL_AHB1_GRP1_IsEnabledClock\n
448 * AHB1ENR GPIOKEN LL_AHB1_GRP1_IsEnabledClock\n
449 * AHB1ENR CRCEN LL_AHB1_GRP1_IsEnabledClock\n
450 * AHB1ENR BKPSRAMEN LL_AHB1_GRP1_IsEnabledClock\n
451 * AHB1ENR CCMDATARAMEN LL_AHB1_GRP1_IsEnabledClock\n
452 * AHB1ENR DMA1EN LL_AHB1_GRP1_IsEnabledClock\n
453 * AHB1ENR DMA2EN LL_AHB1_GRP1_IsEnabledClock\n
454 * AHB1ENR RNGEN LL_AHB1_GRP1_IsEnabledClock\n
455 * AHB1ENR DMA2DEN LL_AHB1_GRP1_IsEnabledClock\n
456 * AHB1ENR ETHMACEN LL_AHB1_GRP1_IsEnabledClock\n
457 * AHB1ENR ETHMACTXEN LL_AHB1_GRP1_IsEnabledClock\n
458 * AHB1ENR ETHMACRXEN LL_AHB1_GRP1_IsEnabledClock\n
459 * AHB1ENR ETHMACPTPEN LL_AHB1_GRP1_IsEnabledClock\n
460 * AHB1ENR OTGHSEN LL_AHB1_GRP1_IsEnabledClock\n
461 * AHB1ENR OTGHSULPIEN LL_AHB1_GRP1_IsEnabledClock
462 * @param Periphs This parameter can be a combination of the following values:
463 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA
464 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB
465 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC
466 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD (*)
467 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*)
468 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF (*)
469 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG (*)
470 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH (*)
471 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOI (*)
472 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOJ (*)
473 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOK (*)
474 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
475 * @arg @ref LL_AHB1_GRP1_PERIPH_BKPSRAM (*)
476 * @arg @ref LL_AHB1_GRP1_PERIPH_CCMDATARAM (*)
477 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
478 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
479 * @arg @ref LL_AHB1_GRP1_PERIPH_RNG (*)
480 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*)
481 * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*)
482 * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACTX (*)
483 * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACRX (*)
484 * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACPTP (*)
485 * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHS (*)
486 * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHSULPI (*)
487 *
488 * (*) value not defined in all devices.
489 * @retval State of Periphs (1 or 0).
490 */
491 __STATIC_INLINE uint32_t LL_AHB1_GRP1_IsEnabledClock(uint32_t Periphs)
492 {
493 return (READ_BIT(RCC->AHB1ENR, Periphs) == Periphs);
494 }
495
496 /**
497 * @brief Disable AHB1 peripherals clock.
498 * @rmtoll AHB1ENR GPIOAEN LL_AHB1_GRP1_DisableClock\n
499 * AHB1ENR GPIOBEN LL_AHB1_GRP1_DisableClock\n
500 * AHB1ENR GPIOCEN LL_AHB1_GRP1_DisableClock\n
501 * AHB1ENR GPIODEN LL_AHB1_GRP1_DisableClock\n
502 * AHB1ENR GPIOEEN LL_AHB1_GRP1_DisableClock\n
503 * AHB1ENR GPIOFEN LL_AHB1_GRP1_DisableClock\n
504 * AHB1ENR GPIOGEN LL_AHB1_GRP1_DisableClock\n
505 * AHB1ENR GPIOHEN LL_AHB1_GRP1_DisableClock\n
506 * AHB1ENR GPIOIEN LL_AHB1_GRP1_DisableClock\n
507 * AHB1ENR GPIOJEN LL_AHB1_GRP1_DisableClock\n
508 * AHB1ENR GPIOKEN LL_AHB1_GRP1_DisableClock\n
509 * AHB1ENR CRCEN LL_AHB1_GRP1_DisableClock\n
510 * AHB1ENR BKPSRAMEN LL_AHB1_GRP1_DisableClock\n
511 * AHB1ENR CCMDATARAMEN LL_AHB1_GRP1_DisableClock\n
512 * AHB1ENR DMA1EN LL_AHB1_GRP1_DisableClock\n
513 * AHB1ENR DMA2EN LL_AHB1_GRP1_DisableClock\n
514 * AHB1ENR RNGEN LL_AHB1_GRP1_DisableClock\n
515 * AHB1ENR DMA2DEN LL_AHB1_GRP1_DisableClock\n
516 * AHB1ENR ETHMACEN LL_AHB1_GRP1_DisableClock\n
517 * AHB1ENR ETHMACTXEN LL_AHB1_GRP1_DisableClock\n
518 * AHB1ENR ETHMACRXEN LL_AHB1_GRP1_DisableClock\n
519 * AHB1ENR ETHMACPTPEN LL_AHB1_GRP1_DisableClock\n
520 * AHB1ENR OTGHSEN LL_AHB1_GRP1_DisableClock\n
521 * AHB1ENR OTGHSULPIEN LL_AHB1_GRP1_DisableClock
522 * @param Periphs This parameter can be a combination of the following values:
523 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA
524 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB
525 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC
526 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD (*)
527 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*)
528 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF (*)
529 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG (*)
530 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH (*)
531 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOI (*)
532 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOJ (*)
533 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOK (*)
534 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
535 * @arg @ref LL_AHB1_GRP1_PERIPH_BKPSRAM (*)
536 * @arg @ref LL_AHB1_GRP1_PERIPH_CCMDATARAM (*)
537 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
538 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
539 * @arg @ref LL_AHB1_GRP1_PERIPH_RNG (*)
540 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*)
541 * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*)
542 * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACTX (*)
543 * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACRX (*)
544 * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACPTP (*)
545 * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHS (*)
546 * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHSULPI (*)
547 *
548 * (*) value not defined in all devices.
549 * @retval None
550 */
551 __STATIC_INLINE void LL_AHB1_GRP1_DisableClock(uint32_t Periphs)
552 {
553 CLEAR_BIT(RCC->AHB1ENR, Periphs);
554 }
555
556 /**
557 * @brief Force AHB1 peripherals reset.
558 * @rmtoll AHB1RSTR GPIOARST LL_AHB1_GRP1_ForceReset\n
559 * AHB1RSTR GPIOBRST LL_AHB1_GRP1_ForceReset\n
560 * AHB1RSTR GPIOCRST LL_AHB1_GRP1_ForceReset\n
561 * AHB1RSTR GPIODRST LL_AHB1_GRP1_ForceReset\n
562 * AHB1RSTR GPIOERST LL_AHB1_GRP1_ForceReset\n
563 * AHB1RSTR GPIOFRST LL_AHB1_GRP1_ForceReset\n
564 * AHB1RSTR GPIOGRST LL_AHB1_GRP1_ForceReset\n
565 * AHB1RSTR GPIOHRST LL_AHB1_GRP1_ForceReset\n
566 * AHB1RSTR GPIOIRST LL_AHB1_GRP1_ForceReset\n
567 * AHB1RSTR GPIOJRST LL_AHB1_GRP1_ForceReset\n
568 * AHB1RSTR GPIOKRST LL_AHB1_GRP1_ForceReset\n
569 * AHB1RSTR CRCRST LL_AHB1_GRP1_ForceReset\n
570 * AHB1RSTR DMA1RST LL_AHB1_GRP1_ForceReset\n
571 * AHB1RSTR DMA2RST LL_AHB1_GRP1_ForceReset\n
572 * AHB1RSTR RNGRST LL_AHB1_GRP1_ForceReset\n
573 * AHB1RSTR DMA2DRST LL_AHB1_GRP1_ForceReset\n
574 * AHB1RSTR ETHMACRST LL_AHB1_GRP1_ForceReset\n
575 * AHB1RSTR OTGHSRST LL_AHB1_GRP1_ForceReset
576 * @param Periphs This parameter can be a combination of the following values:
577 * @arg @ref LL_AHB1_GRP1_PERIPH_ALL
578 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA
579 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB
580 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC
581 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD (*)
582 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*)
583 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF (*)
584 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG (*)
585 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH (*)
586 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOI (*)
587 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOJ (*)
588 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOK (*)
589 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
590 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
591 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
592 * @arg @ref LL_AHB1_GRP1_PERIPH_RNG (*)
593 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*)
594 * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*)
595 * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHS (*)
596 *
597 * (*) value not defined in all devices.
598 * @retval None
599 */
600 __STATIC_INLINE void LL_AHB1_GRP1_ForceReset(uint32_t Periphs)
601 {
602 SET_BIT(RCC->AHB1RSTR, Periphs);
603 }
604
605 /**
606 * @brief Release AHB1 peripherals reset.
607 * @rmtoll AHB1RSTR GPIOARST LL_AHB1_GRP1_ReleaseReset\n
608 * AHB1RSTR GPIOBRST LL_AHB1_GRP1_ReleaseReset\n
609 * AHB1RSTR GPIOCRST LL_AHB1_GRP1_ReleaseReset\n
610 * AHB1RSTR GPIODRST LL_AHB1_GRP1_ReleaseReset\n
611 * AHB1RSTR GPIOERST LL_AHB1_GRP1_ReleaseReset\n
612 * AHB1RSTR GPIOFRST LL_AHB1_GRP1_ReleaseReset\n
613 * AHB1RSTR GPIOGRST LL_AHB1_GRP1_ReleaseReset\n
614 * AHB1RSTR GPIOHRST LL_AHB1_GRP1_ReleaseReset\n
615 * AHB1RSTR GPIOIRST LL_AHB1_GRP1_ReleaseReset\n
616 * AHB1RSTR GPIOJRST LL_AHB1_GRP1_ReleaseReset\n
617 * AHB1RSTR GPIOKRST LL_AHB1_GRP1_ReleaseReset\n
618 * AHB1RSTR CRCRST LL_AHB1_GRP1_ReleaseReset\n
619 * AHB1RSTR DMA1RST LL_AHB1_GRP1_ReleaseReset\n
620 * AHB1RSTR DMA2RST LL_AHB1_GRP1_ReleaseReset\n
621 * AHB1RSTR RNGRST LL_AHB1_GRP1_ReleaseReset\n
622 * AHB1RSTR DMA2DRST LL_AHB1_GRP1_ReleaseReset\n
623 * AHB1RSTR ETHMACRST LL_AHB1_GRP1_ReleaseReset\n
624 * AHB1RSTR OTGHSRST LL_AHB1_GRP1_ReleaseReset
625 * @param Periphs This parameter can be a combination of the following values:
626 * @arg @ref LL_AHB1_GRP1_PERIPH_ALL
627 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA
628 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB
629 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC
630 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD (*)
631 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*)
632 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF (*)
633 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG (*)
634 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH (*)
635 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOI (*)
636 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOJ (*)
637 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOK (*)
638 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
639 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
640 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
641 * @arg @ref LL_AHB1_GRP1_PERIPH_RNG (*)
642 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*)
643 * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*)
644 * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHS (*)
645 *
646 * (*) value not defined in all devices.
647 * @retval None
648 */
649 __STATIC_INLINE void LL_AHB1_GRP1_ReleaseReset(uint32_t Periphs)
650 {
651 CLEAR_BIT(RCC->AHB1RSTR, Periphs);
652 }
653
654 /**
655 * @brief Enable AHB1 peripheral clocks in low-power mode
656 * @rmtoll AHB1LPENR GPIOALPEN LL_AHB1_GRP1_EnableClockLowPower\n
657 * AHB1LPENR GPIOBLPEN LL_AHB1_GRP1_EnableClockLowPower\n
658 * AHB1LPENR GPIOCLPEN LL_AHB1_GRP1_EnableClockLowPower\n
659 * AHB1LPENR GPIODLPEN LL_AHB1_GRP1_EnableClockLowPower\n
660 * AHB1LPENR GPIOELPEN LL_AHB1_GRP1_EnableClockLowPower\n
661 * AHB1LPENR GPIOFLPEN LL_AHB1_GRP1_EnableClockLowPower\n
662 * AHB1LPENR GPIOGLPEN LL_AHB1_GRP1_EnableClockLowPower\n
663 * AHB1LPENR GPIOHLPEN LL_AHB1_GRP1_EnableClockLowPower\n
664 * AHB1LPENR GPIOILPEN LL_AHB1_GRP1_EnableClockLowPower\n
665 * AHB1LPENR GPIOJLPEN LL_AHB1_GRP1_EnableClockLowPower\n
666 * AHB1LPENR GPIOKLPEN LL_AHB1_GRP1_EnableClockLowPower\n
667 * AHB1LPENR CRCLPEN LL_AHB1_GRP1_EnableClockLowPower\n
668 * AHB1LPENR BKPSRAMLPEN LL_AHB1_GRP1_EnableClockLowPower\n
669 * AHB1LPENR FLITFLPEN LL_AHB1_GRP1_EnableClockLowPower\n
670 * AHB1LPENR SRAM1LPEN LL_AHB1_GRP1_EnableClockLowPower\n
671 * AHB1LPENR SRAM2LPEN LL_AHB1_GRP1_EnableClockLowPower\n
672 * AHB1LPENR SRAM3LPEN LL_AHB1_GRP1_EnableClockLowPower\n
673 * AHB1LPENR BKPSRAMLPEN LL_AHB1_GRP1_EnableClockLowPower\n
674 * AHB1LPENR DMA1LPEN LL_AHB1_GRP1_EnableClockLowPower\n
675 * AHB1LPENR DMA2LPEN LL_AHB1_GRP1_EnableClockLowPower\n
676 * AHB1LPENR DMA2DLPEN LL_AHB1_GRP1_EnableClockLowPower\n
677 * AHB1LPENR RNGLPEN LL_AHB1_GRP1_EnableClockLowPower\n
678 * AHB1LPENR ETHMACLPEN LL_AHB1_GRP1_EnableClockLowPower\n
679 * AHB1LPENR ETHMACTXLPEN LL_AHB1_GRP1_EnableClockLowPower\n
680 * AHB1LPENR ETHMACRXLPEN LL_AHB1_GRP1_EnableClockLowPower\n
681 * AHB1LPENR ETHMACPTPLPEN LL_AHB1_GRP1_EnableClockLowPower\n
682 * AHB1LPENR OTGHSLPEN LL_AHB1_GRP1_EnableClockLowPower\n
683 * AHB1LPENR OTGHSULPILPEN LL_AHB1_GRP1_EnableClockLowPower
684 * @param Periphs This parameter can be a combination of the following values:
685 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA
686 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB
687 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC
688 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD (*)
689 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*)
690 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF (*)
691 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG (*)
692 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH (*)
693 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOI (*)
694 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOJ (*)
695 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOK (*)
696 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
697 * @arg @ref LL_AHB1_GRP1_PERIPH_BKPSRAM (*)
698 * @arg @ref LL_AHB1_GRP1_PERIPH_FLITF
699 * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM1
700 * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM2 (*)
701 * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM3 (*)
702 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
703 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
704 * @arg @ref LL_AHB1_GRP1_PERIPH_RNG (*)
705 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*)
706 * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*)
707 * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACTX (*)
708 * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACRX (*)
709 * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACPTP (*)
710 * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHS (*)
711 * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHSULPI (*)
712 *
713 * (*) value not defined in all devices.
714 * @retval None
715 */
716 __STATIC_INLINE void LL_AHB1_GRP1_EnableClockLowPower(uint32_t Periphs)
717 {
718 __IO uint32_t tmpreg;
719 SET_BIT(RCC->AHB1LPENR, Periphs);
720 /* Delay after an RCC peripheral clock enabling */
721 tmpreg = READ_BIT(RCC->AHB1LPENR, Periphs);
722 (void)tmpreg;
723 }
724
725 /**
726 * @brief Disable AHB1 peripheral clocks in low-power mode
727 * @rmtoll AHB1LPENR GPIOALPEN LL_AHB1_GRP1_DisableClockLowPower\n
728 * AHB1LPENR GPIOBLPEN LL_AHB1_GRP1_DisableClockLowPower\n
729 * AHB1LPENR GPIOCLPEN LL_AHB1_GRP1_DisableClockLowPower\n
730 * AHB1LPENR GPIODLPEN LL_AHB1_GRP1_DisableClockLowPower\n
731 * AHB1LPENR GPIOELPEN LL_AHB1_GRP1_DisableClockLowPower\n
732 * AHB1LPENR GPIOFLPEN LL_AHB1_GRP1_DisableClockLowPower\n
733 * AHB1LPENR GPIOGLPEN LL_AHB1_GRP1_DisableClockLowPower\n
734 * AHB1LPENR GPIOHLPEN LL_AHB1_GRP1_DisableClockLowPower\n
735 * AHB1LPENR GPIOILPEN LL_AHB1_GRP1_DisableClockLowPower\n
736 * AHB1LPENR GPIOJLPEN LL_AHB1_GRP1_DisableClockLowPower\n
737 * AHB1LPENR GPIOKLPEN LL_AHB1_GRP1_DisableClockLowPower\n
738 * AHB1LPENR CRCLPEN LL_AHB1_GRP1_DisableClockLowPower\n
739 * AHB1LPENR BKPSRAMLPEN LL_AHB1_GRP1_DisableClockLowPower\n
740 * AHB1LPENR FLITFLPEN LL_AHB1_GRP1_DisableClockLowPower\n
741 * AHB1LPENR SRAM1LPEN LL_AHB1_GRP1_DisableClockLowPower\n
742 * AHB1LPENR SRAM2LPEN LL_AHB1_GRP1_DisableClockLowPower\n
743 * AHB1LPENR SRAM3LPEN LL_AHB1_GRP1_DisableClockLowPower\n
744 * AHB1LPENR BKPSRAMLPEN LL_AHB1_GRP1_DisableClockLowPower\n
745 * AHB1LPENR DMA1LPEN LL_AHB1_GRP1_DisableClockLowPower\n
746 * AHB1LPENR DMA2LPEN LL_AHB1_GRP1_DisableClockLowPower\n
747 * AHB1LPENR DMA2DLPEN LL_AHB1_GRP1_DisableClockLowPower\n
748 * AHB1LPENR RNGLPEN LL_AHB1_GRP1_DisableClockLowPower\n
749 * AHB1LPENR ETHMACLPEN LL_AHB1_GRP1_DisableClockLowPower\n
750 * AHB1LPENR ETHMACTXLPEN LL_AHB1_GRP1_DisableClockLowPower\n
751 * AHB1LPENR ETHMACRXLPEN LL_AHB1_GRP1_DisableClockLowPower\n
752 * AHB1LPENR ETHMACPTPLPEN LL_AHB1_GRP1_DisableClockLowPower\n
753 * AHB1LPENR OTGHSLPEN LL_AHB1_GRP1_DisableClockLowPower\n
754 * AHB1LPENR OTGHSULPILPEN LL_AHB1_GRP1_DisableClockLowPower
755 * @param Periphs This parameter can be a combination of the following values:
756 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA
757 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB
758 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC
759 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD (*)
760 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*)
761 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF (*)
762 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG (*)
763 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH (*)
764 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOI (*)
765 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOJ (*)
766 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOK (*)
767 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
768 * @arg @ref LL_AHB1_GRP1_PERIPH_BKPSRAM (*)
769 * @arg @ref LL_AHB1_GRP1_PERIPH_FLITF
770 * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM1
771 * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM2 (*)
772 * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM3 (*)
773 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
774 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
775 * @arg @ref LL_AHB1_GRP1_PERIPH_RNG (*)
776 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*)
777 * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*)
778 * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACTX (*)
779 * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACRX (*)
780 * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACPTP (*)
781 * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHS (*)
782 * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHSULPI (*)
783 *
784 * (*) value not defined in all devices.
785 * @retval None
786 */
787 __STATIC_INLINE void LL_AHB1_GRP1_DisableClockLowPower(uint32_t Periphs)
788 {
789 CLEAR_BIT(RCC->AHB1LPENR, Periphs);
790 }
791
792 /**
793 * @}
794 */
795
796 #if defined(RCC_AHB2_SUPPORT)
797 /** @defgroup BUS_LL_EF_AHB2 AHB2
798 * @{
799 */
800
801 /**
802 * @brief Enable AHB2 peripherals clock.
803 * @rmtoll AHB2ENR DCMIEN LL_AHB2_GRP1_EnableClock\n
804 * AHB2ENR CRYPEN LL_AHB2_GRP1_EnableClock\n
805 * AHB2ENR AESEN LL_AHB2_GRP1_EnableClock\n
806 * AHB2ENR HASHEN LL_AHB2_GRP1_EnableClock\n
807 * AHB2ENR RNGEN LL_AHB2_GRP1_EnableClock\n
808 * AHB2ENR OTGFSEN LL_AHB2_GRP1_EnableClock
809 * @param Periphs This parameter can be a combination of the following values:
810 * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*)
811 * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)
812 * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*)
813 * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
814 * @arg @ref LL_AHB2_GRP1_PERIPH_RNG (*)
815 * @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS (*)
816 *
817 * (*) value not defined in all devices.
818 * @retval None
819 */
820 __STATIC_INLINE void LL_AHB2_GRP1_EnableClock(uint32_t Periphs)
821 {
822 __IO uint32_t tmpreg;
823 SET_BIT(RCC->AHB2ENR, Periphs);
824 /* Delay after an RCC peripheral clock enabling */
825 tmpreg = READ_BIT(RCC->AHB2ENR, Periphs);
826 (void)tmpreg;
827 }
828
829 /**
830 * @brief Check if AHB2 peripheral clock is enabled or not
831 * @rmtoll AHB2ENR DCMIEN LL_AHB2_GRP1_IsEnabledClock\n
832 * AHB2ENR CRYPEN LL_AHB2_GRP1_IsEnabledClock\n
833 * AHB2ENR AESEN LL_AHB2_GRP1_IsEnabledClock\n
834 * AHB2ENR HASHEN LL_AHB2_GRP1_IsEnabledClock\n
835 * AHB2ENR RNGEN LL_AHB2_GRP1_IsEnabledClock\n
836 * AHB2ENR OTGFSEN LL_AHB2_GRP1_IsEnabledClock
837 * @param Periphs This parameter can be a combination of the following values:
838 * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*)
839 * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)
840 * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*)
841 * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
842 * @arg @ref LL_AHB2_GRP1_PERIPH_RNG (*)
843 * @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS (*)
844 *
845 * (*) value not defined in all devices.
846 * @retval State of Periphs (1 or 0).
847 */
848 __STATIC_INLINE uint32_t LL_AHB2_GRP1_IsEnabledClock(uint32_t Periphs)
849 {
850 return (READ_BIT(RCC->AHB2ENR, Periphs) == Periphs);
851 }
852
853 /**
854 * @brief Disable AHB2 peripherals clock.
855 * @rmtoll AHB2ENR DCMIEN LL_AHB2_GRP1_DisableClock\n
856 * AHB2ENR CRYPEN LL_AHB2_GRP1_DisableClock\n
857 * AHB2ENR AESEN LL_AHB2_GRP1_DisableClock\n
858 * AHB2ENR HASHEN LL_AHB2_GRP1_DisableClock\n
859 * AHB2ENR RNGEN LL_AHB2_GRP1_DisableClock\n
860 * AHB2ENR OTGFSEN LL_AHB2_GRP1_DisableClock
861 * @param Periphs This parameter can be a combination of the following values:
862 * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*)
863 * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)
864 * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*)
865 * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
866 * @arg @ref LL_AHB2_GRP1_PERIPH_RNG (*)
867 * @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS (*)
868 *
869 * (*) value not defined in all devices.
870 * @retval None
871 */
872 __STATIC_INLINE void LL_AHB2_GRP1_DisableClock(uint32_t Periphs)
873 {
874 CLEAR_BIT(RCC->AHB2ENR, Periphs);
875 }
876
877 /**
878 * @brief Force AHB2 peripherals reset.
879 * @rmtoll AHB2RSTR DCMIRST LL_AHB2_GRP1_ForceReset\n
880 * AHB2RSTR CRYPRST LL_AHB2_GRP1_ForceReset\n
881 * AHB2RSTR AESRST LL_AHB2_GRP1_ForceReset\n
882 * AHB2RSTR HASHRST LL_AHB2_GRP1_ForceReset\n
883 * AHB2RSTR RNGRST LL_AHB2_GRP1_ForceReset\n
884 * AHB2RSTR OTGFSRST LL_AHB2_GRP1_ForceReset
885 * @param Periphs This parameter can be a combination of the following values:
886 * @arg @ref LL_AHB2_GRP1_PERIPH_ALL
887 * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*)
888 * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)
889 * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*)
890 * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
891 * @arg @ref LL_AHB2_GRP1_PERIPH_RNG (*)
892 * @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS (*)
893 *
894 * (*) value not defined in all devices.
895 * @retval None
896 */
897 __STATIC_INLINE void LL_AHB2_GRP1_ForceReset(uint32_t Periphs)
898 {
899 SET_BIT(RCC->AHB2RSTR, Periphs);
900 }
901
902 /**
903 * @brief Release AHB2 peripherals reset.
904 * @rmtoll AHB2RSTR DCMIRST LL_AHB2_GRP1_ReleaseReset\n
905 * AHB2RSTR CRYPRST LL_AHB2_GRP1_ReleaseReset\n
906 * AHB2RSTR AESRST LL_AHB2_GRP1_ReleaseReset\n
907 * AHB2RSTR HASHRST LL_AHB2_GRP1_ReleaseReset\n
908 * AHB2RSTR RNGRST LL_AHB2_GRP1_ReleaseReset\n
909 * AHB2RSTR OTGFSRST LL_AHB2_GRP1_ReleaseReset
910 * @param Periphs This parameter can be a combination of the following values:
911 * @arg @ref LL_AHB2_GRP1_PERIPH_ALL
912 * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*)
913 * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)
914 * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*)
915 * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
916 * @arg @ref LL_AHB2_GRP1_PERIPH_RNG (*)
917 * @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS (*)
918 *
919 * (*) value not defined in all devices.
920 * @retval None
921 */
922 __STATIC_INLINE void LL_AHB2_GRP1_ReleaseReset(uint32_t Periphs)
923 {
924 CLEAR_BIT(RCC->AHB2RSTR, Periphs);
925 }
926
927 /**
928 * @brief Enable AHB2 peripheral clocks in low-power mode
929 * @rmtoll AHB2LPENR DCMILPEN LL_AHB2_GRP1_EnableClockLowPower\n
930 * AHB2LPENR CRYPLPEN LL_AHB2_GRP1_EnableClockLowPower\n
931 * AHB2LPENR AESLPEN LL_AHB2_GRP1_EnableClockLowPower\n
932 * AHB2LPENR HASHLPEN LL_AHB2_GRP1_EnableClockLowPower\n
933 * AHB2LPENR RNGLPEN LL_AHB2_GRP1_EnableClockLowPower\n
934 * AHB2LPENR OTGFSLPEN LL_AHB2_GRP1_EnableClockLowPower
935 * @param Periphs This parameter can be a combination of the following values:
936 * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*)
937 * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)
938 * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*)
939 * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
940 * @arg @ref LL_AHB2_GRP1_PERIPH_RNG (*)
941 * @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS (*)
942 *
943 * (*) value not defined in all devices.
944 * @retval None
945 */
946 __STATIC_INLINE void LL_AHB2_GRP1_EnableClockLowPower(uint32_t Periphs)
947 {
948 __IO uint32_t tmpreg;
949 SET_BIT(RCC->AHB2LPENR, Periphs);
950 /* Delay after an RCC peripheral clock enabling */
951 tmpreg = READ_BIT(RCC->AHB2LPENR, Periphs);
952 (void)tmpreg;
953 }
954
955 /**
956 * @brief Disable AHB2 peripheral clocks in low-power mode
957 * @rmtoll AHB2LPENR DCMILPEN LL_AHB2_GRP1_DisableClockLowPower\n
958 * AHB2LPENR CRYPLPEN LL_AHB2_GRP1_DisableClockLowPower\n
959 * AHB2LPENR AESLPEN LL_AHB2_GRP1_DisableClockLowPower\n
960 * AHB2LPENR HASHLPEN LL_AHB2_GRP1_DisableClockLowPower\n
961 * AHB2LPENR RNGLPEN LL_AHB2_GRP1_DisableClockLowPower\n
962 * AHB2LPENR OTGFSLPEN LL_AHB2_GRP1_DisableClockLowPower
963 * @param Periphs This parameter can be a combination of the following values:
964 * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*)
965 * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)
966 * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*)
967 * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
968 * @arg @ref LL_AHB2_GRP1_PERIPH_RNG (*)
969 * @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS (*)
970 *
971 * (*) value not defined in all devices.
972 * @retval None
973 */
974 __STATIC_INLINE void LL_AHB2_GRP1_DisableClockLowPower(uint32_t Periphs)
975 {
976 CLEAR_BIT(RCC->AHB2LPENR, Periphs);
977 }
978
979 /**
980 * @}
981 */
982 #endif /* RCC_AHB2_SUPPORT */
983
984 #if defined(RCC_AHB3_SUPPORT)
985 /** @defgroup BUS_LL_EF_AHB3 AHB3
986 * @{
987 */
988
989 /**
990 * @brief Enable AHB3 peripherals clock.
991 * @rmtoll AHB3ENR FMCEN LL_AHB3_GRP1_EnableClock\n
992 * AHB3ENR FSMCEN LL_AHB3_GRP1_EnableClock\n
993 * AHB3ENR QSPIEN LL_AHB3_GRP1_EnableClock
994 * @param Periphs This parameter can be a combination of the following values:
995 * @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*)
996 * @arg @ref LL_AHB3_GRP1_PERIPH_FSMC (*)
997 * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*)
998 *
999 * (*) value not defined in all devices.
1000 * @retval None
1001 */
1002 __STATIC_INLINE void LL_AHB3_GRP1_EnableClock(uint32_t Periphs)
1003 {
1004 __IO uint32_t tmpreg;
1005 SET_BIT(RCC->AHB3ENR, Periphs);
1006 /* Delay after an RCC peripheral clock enabling */
1007 tmpreg = READ_BIT(RCC->AHB3ENR, Periphs);
1008 (void)tmpreg;
1009 }
1010
1011 /**
1012 * @brief Check if AHB3 peripheral clock is enabled or not
1013 * @rmtoll AHB3ENR FMCEN LL_AHB3_GRP1_IsEnabledClock\n
1014 * AHB3ENR FSMCEN LL_AHB3_GRP1_IsEnabledClock\n
1015 * AHB3ENR QSPIEN LL_AHB3_GRP1_IsEnabledClock
1016 * @param Periphs This parameter can be a combination of the following values:
1017 * @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*)
1018 * @arg @ref LL_AHB3_GRP1_PERIPH_FSMC (*)
1019 * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*)
1020 *
1021 * (*) value not defined in all devices.
1022 * @retval State of Periphs (1 or 0).
1023 */
1024 __STATIC_INLINE uint32_t LL_AHB3_GRP1_IsEnabledClock(uint32_t Periphs)
1025 {
1026 return (READ_BIT(RCC->AHB3ENR, Periphs) == Periphs);
1027 }
1028
1029 /**
1030 * @brief Disable AHB3 peripherals clock.
1031 * @rmtoll AHB3ENR FMCEN LL_AHB3_GRP1_DisableClock\n
1032 * AHB3ENR FSMCEN LL_AHB3_GRP1_DisableClock\n
1033 * AHB3ENR QSPIEN LL_AHB3_GRP1_DisableClock
1034 * @param Periphs This parameter can be a combination of the following values:
1035 * @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*)
1036 * @arg @ref LL_AHB3_GRP1_PERIPH_FSMC (*)
1037 * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*)
1038 *
1039 * (*) value not defined in all devices.
1040 * @retval None
1041 */
1042 __STATIC_INLINE void LL_AHB3_GRP1_DisableClock(uint32_t Periphs)
1043 {
1044 CLEAR_BIT(RCC->AHB3ENR, Periphs);
1045 }
1046
1047 /**
1048 * @brief Force AHB3 peripherals reset.
1049 * @rmtoll AHB3RSTR FMCRST LL_AHB3_GRP1_ForceReset\n
1050 * AHB3RSTR FSMCRST LL_AHB3_GRP1_ForceReset\n
1051 * AHB3RSTR QSPIRST LL_AHB3_GRP1_ForceReset
1052 * @param Periphs This parameter can be a combination of the following values:
1053 * @arg @ref LL_AHB3_GRP1_PERIPH_ALL
1054 * @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*)
1055 * @arg @ref LL_AHB3_GRP1_PERIPH_FSMC (*)
1056 * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*)
1057 *
1058 * (*) value not defined in all devices.
1059 * @retval None
1060 */
1061 __STATIC_INLINE void LL_AHB3_GRP1_ForceReset(uint32_t Periphs)
1062 {
1063 SET_BIT(RCC->AHB3RSTR, Periphs);
1064 }
1065
1066 /**
1067 * @brief Release AHB3 peripherals reset.
1068 * @rmtoll AHB3RSTR FMCRST LL_AHB3_GRP1_ReleaseReset\n
1069 * AHB3RSTR FSMCRST LL_AHB3_GRP1_ReleaseReset\n
1070 * AHB3RSTR QSPIRST LL_AHB3_GRP1_ReleaseReset
1071 * @param Periphs This parameter can be a combination of the following values:
1072 * @arg @ref LL_AHB2_GRP1_PERIPH_ALL
1073 * @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*)
1074 * @arg @ref LL_AHB3_GRP1_PERIPH_FSMC (*)
1075 * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*)
1076 *
1077 * (*) value not defined in all devices.
1078 * @retval None
1079 */
1080 __STATIC_INLINE void LL_AHB3_GRP1_ReleaseReset(uint32_t Periphs)
1081 {
1082 CLEAR_BIT(RCC->AHB3RSTR, Periphs);
1083 }
1084
1085 /**
1086 * @brief Enable AHB3 peripheral clocks in low-power mode
1087 * @rmtoll AHB3LPENR FMCLPEN LL_AHB3_GRP1_EnableClockLowPower\n
1088 * AHB3LPENR FSMCLPEN LL_AHB3_GRP1_EnableClockLowPower\n
1089 * AHB3LPENR QSPILPEN LL_AHB3_GRP1_EnableClockLowPower
1090 * @param Periphs This parameter can be a combination of the following values:
1091 * @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*)
1092 * @arg @ref LL_AHB3_GRP1_PERIPH_FSMC (*)
1093 * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*)
1094 *
1095 * (*) value not defined in all devices.
1096 * @retval None
1097 */
1098 __STATIC_INLINE void LL_AHB3_GRP1_EnableClockLowPower(uint32_t Periphs)
1099 {
1100 __IO uint32_t tmpreg;
1101 SET_BIT(RCC->AHB3LPENR, Periphs);
1102 /* Delay after an RCC peripheral clock enabling */
1103 tmpreg = READ_BIT(RCC->AHB3LPENR, Periphs);
1104 (void)tmpreg;
1105 }
1106
1107 /**
1108 * @brief Disable AHB3 peripheral clocks in low-power mode
1109 * @rmtoll AHB3LPENR FMCLPEN LL_AHB3_GRP1_DisableClockLowPower\n
1110 * AHB3LPENR FSMCLPEN LL_AHB3_GRP1_DisableClockLowPower\n
1111 * AHB3LPENR QSPILPEN LL_AHB3_GRP1_DisableClockLowPower
1112 * @param Periphs This parameter can be a combination of the following values:
1113 * @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*)
1114 * @arg @ref LL_AHB3_GRP1_PERIPH_FSMC (*)
1115 * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*)
1116 *
1117 * (*) value not defined in all devices.
1118 * @retval None
1119 */
1120 __STATIC_INLINE void LL_AHB3_GRP1_DisableClockLowPower(uint32_t Periphs)
1121 {
1122 CLEAR_BIT(RCC->AHB3LPENR, Periphs);
1123 }
1124
1125 /**
1126 * @}
1127 */
1128 #endif /* RCC_AHB3_SUPPORT */
1129
1130 /** @defgroup BUS_LL_EF_APB1 APB1
1131 * @{
1132 */
1133
1134 /**
1135 * @brief Enable APB1 peripherals clock.
1136 * @rmtoll APB1ENR TIM2EN LL_APB1_GRP1_EnableClock\n
1137 * APB1ENR TIM3EN LL_APB1_GRP1_EnableClock\n
1138 * APB1ENR TIM4EN LL_APB1_GRP1_EnableClock\n
1139 * APB1ENR TIM5EN LL_APB1_GRP1_EnableClock\n
1140 * APB1ENR TIM6EN LL_APB1_GRP1_EnableClock\n
1141 * APB1ENR TIM7EN LL_APB1_GRP1_EnableClock\n
1142 * APB1ENR TIM12EN LL_APB1_GRP1_EnableClock\n
1143 * APB1ENR TIM13EN LL_APB1_GRP1_EnableClock\n
1144 * APB1ENR TIM14EN LL_APB1_GRP1_EnableClock\n
1145 * APB1ENR LPTIM1EN LL_APB1_GRP1_EnableClock\n
1146 * APB1ENR WWDGEN LL_APB1_GRP1_EnableClock\n
1147 * APB1ENR SPI2EN LL_APB1_GRP1_EnableClock\n
1148 * APB1ENR SPI3EN LL_APB1_GRP1_EnableClock\n
1149 * APB1ENR SPDIFRXEN LL_APB1_GRP1_EnableClock\n
1150 * APB1ENR USART2EN LL_APB1_GRP1_EnableClock\n
1151 * APB1ENR USART3EN LL_APB1_GRP1_EnableClock\n
1152 * APB1ENR UART4EN LL_APB1_GRP1_EnableClock\n
1153 * APB1ENR UART5EN LL_APB1_GRP1_EnableClock\n
1154 * APB1ENR I2C1EN LL_APB1_GRP1_EnableClock\n
1155 * APB1ENR I2C2EN LL_APB1_GRP1_EnableClock\n
1156 * APB1ENR I2C3EN LL_APB1_GRP1_EnableClock\n
1157 * APB1ENR FMPI2C1EN LL_APB1_GRP1_EnableClock\n
1158 * APB1ENR CAN1EN LL_APB1_GRP1_EnableClock\n
1159 * APB1ENR CAN2EN LL_APB1_GRP1_EnableClock\n
1160 * APB1ENR CAN3EN LL_APB1_GRP1_EnableClock\n
1161 * APB1ENR CECEN LL_APB1_GRP1_EnableClock\n
1162 * APB1ENR PWREN LL_APB1_GRP1_EnableClock\n
1163 * APB1ENR DACEN LL_APB1_GRP1_EnableClock\n
1164 * APB1ENR UART7EN LL_APB1_GRP1_EnableClock\n
1165 * APB1ENR UART8EN LL_APB1_GRP1_EnableClock\n
1166 * APB1ENR RTCAPBEN LL_APB1_GRP1_EnableClock
1167 * @param Periphs This parameter can be a combination of the following values:
1168 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 (*)
1169 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*)
1170 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*)
1171 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5
1172 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*)
1173 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*)
1174 * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 (*)
1175 * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 (*)
1176 * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 (*)
1177 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 (*)
1178 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
1179 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
1180 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*)
1181 * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX (*)
1182 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
1183 * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*)
1184 * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
1185 * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
1186 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
1187 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2
1188 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*)
1189 * @arg @ref LL_APB1_GRP1_PERIPH_FMPI2C1 (*)
1190 * @arg @ref LL_APB1_GRP1_PERIPH_CAN1 (*)
1191 * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*)
1192 * @arg @ref LL_APB1_GRP1_PERIPH_CAN3 (*)
1193 * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*)
1194 * @arg @ref LL_APB1_GRP1_PERIPH_PWR
1195 * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*)
1196 * @arg @ref LL_APB1_GRP1_PERIPH_UART7 (*)
1197 * @arg @ref LL_APB1_GRP1_PERIPH_UART8 (*)
1198 * @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB (*)
1199 *
1200 * (*) value not defined in all devices.
1201 * @retval None
1202 */
1203 __STATIC_INLINE void LL_APB1_GRP1_EnableClock(uint32_t Periphs)
1204 {
1205 __IO uint32_t tmpreg;
1206 SET_BIT(RCC->APB1ENR, Periphs);
1207 /* Delay after an RCC peripheral clock enabling */
1208 tmpreg = READ_BIT(RCC->APB1ENR, Periphs);
1209 (void)tmpreg;
1210 }
1211
1212 /**
1213 * @brief Check if APB1 peripheral clock is enabled or not
1214 * @rmtoll APB1ENR TIM2EN LL_APB1_GRP1_IsEnabledClock\n
1215 * APB1ENR TIM3EN LL_APB1_GRP1_IsEnabledClock\n
1216 * APB1ENR TIM4EN LL_APB1_GRP1_IsEnabledClock\n
1217 * APB1ENR TIM5EN LL_APB1_GRP1_IsEnabledClock\n
1218 * APB1ENR TIM6EN LL_APB1_GRP1_IsEnabledClock\n
1219 * APB1ENR TIM7EN LL_APB1_GRP1_IsEnabledClock\n
1220 * APB1ENR TIM12EN LL_APB1_GRP1_IsEnabledClock\n
1221 * APB1ENR TIM13EN LL_APB1_GRP1_IsEnabledClock\n
1222 * APB1ENR TIM14EN LL_APB1_GRP1_IsEnabledClock\n
1223 * APB1ENR LPTIM1EN LL_APB1_GRP1_IsEnabledClock\n
1224 * APB1ENR WWDGEN LL_APB1_GRP1_IsEnabledClock\n
1225 * APB1ENR SPI2EN LL_APB1_GRP1_IsEnabledClock\n
1226 * APB1ENR SPI3EN LL_APB1_GRP1_IsEnabledClock\n
1227 * APB1ENR SPDIFRXEN LL_APB1_GRP1_IsEnabledClock\n
1228 * APB1ENR USART2EN LL_APB1_GRP1_IsEnabledClock\n
1229 * APB1ENR USART3EN LL_APB1_GRP1_IsEnabledClock\n
1230 * APB1ENR UART4EN LL_APB1_GRP1_IsEnabledClock\n
1231 * APB1ENR UART5EN LL_APB1_GRP1_IsEnabledClock\n
1232 * APB1ENR I2C1EN LL_APB1_GRP1_IsEnabledClock\n
1233 * APB1ENR I2C2EN LL_APB1_GRP1_IsEnabledClock\n
1234 * APB1ENR I2C3EN LL_APB1_GRP1_IsEnabledClock\n
1235 * APB1ENR FMPI2C1EN LL_APB1_GRP1_IsEnabledClock\n
1236 * APB1ENR CAN1EN LL_APB1_GRP1_IsEnabledClock\n
1237 * APB1ENR CAN2EN LL_APB1_GRP1_IsEnabledClock\n
1238 * APB1ENR CAN3EN LL_APB1_GRP1_IsEnabledClock\n
1239 * APB1ENR CECEN LL_APB1_GRP1_IsEnabledClock\n
1240 * APB1ENR PWREN LL_APB1_GRP1_IsEnabledClock\n
1241 * APB1ENR DACEN LL_APB1_GRP1_IsEnabledClock\n
1242 * APB1ENR UART7EN LL_APB1_GRP1_IsEnabledClock\n
1243 * APB1ENR UART8EN LL_APB1_GRP1_IsEnabledClock\n
1244 * APB1ENR RTCAPBEN LL_APB1_GRP1_IsEnabledClock
1245 * @param Periphs This parameter can be a combination of the following values:
1246 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 (*)
1247 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*)
1248 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*)
1249 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5
1250 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*)
1251 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*)
1252 * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 (*)
1253 * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 (*)
1254 * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 (*)
1255 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 (*)
1256 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
1257 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
1258 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*)
1259 * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX (*)
1260 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
1261 * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*)
1262 * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
1263 * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
1264 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
1265 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2
1266 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*)
1267 * @arg @ref LL_APB1_GRP1_PERIPH_FMPI2C1 (*)
1268 * @arg @ref LL_APB1_GRP1_PERIPH_CAN1 (*)
1269 * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*)
1270 * @arg @ref LL_APB1_GRP1_PERIPH_CAN3 (*)
1271 * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*)
1272 * @arg @ref LL_APB1_GRP1_PERIPH_PWR
1273 * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*)
1274 * @arg @ref LL_APB1_GRP1_PERIPH_UART7 (*)
1275 * @arg @ref LL_APB1_GRP1_PERIPH_UART8 (*)
1276 * @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB (*)
1277 *
1278 * (*) value not defined in all devices.
1279 * @retval State of Periphs (1 or 0).
1280 */
1281 __STATIC_INLINE uint32_t LL_APB1_GRP1_IsEnabledClock(uint32_t Periphs)
1282 {
1283 return (READ_BIT(RCC->APB1ENR, Periphs) == Periphs);
1284 }
1285
1286 /**
1287 * @brief Disable APB1 peripherals clock.
1288 * @rmtoll APB1ENR TIM2EN LL_APB1_GRP1_DisableClock\n
1289 * APB1ENR TIM3EN LL_APB1_GRP1_DisableClock\n
1290 * APB1ENR TIM4EN LL_APB1_GRP1_DisableClock\n
1291 * APB1ENR TIM5EN LL_APB1_GRP1_DisableClock\n
1292 * APB1ENR TIM6EN LL_APB1_GRP1_DisableClock\n
1293 * APB1ENR TIM7EN LL_APB1_GRP1_DisableClock\n
1294 * APB1ENR TIM12EN LL_APB1_GRP1_DisableClock\n
1295 * APB1ENR TIM13EN LL_APB1_GRP1_DisableClock\n
1296 * APB1ENR TIM14EN LL_APB1_GRP1_DisableClock\n
1297 * APB1ENR LPTIM1EN LL_APB1_GRP1_DisableClock\n
1298 * APB1ENR WWDGEN LL_APB1_GRP1_DisableClock\n
1299 * APB1ENR SPI2EN LL_APB1_GRP1_DisableClock\n
1300 * APB1ENR SPI3EN LL_APB1_GRP1_DisableClock\n
1301 * APB1ENR SPDIFRXEN LL_APB1_GRP1_DisableClock\n
1302 * APB1ENR USART2EN LL_APB1_GRP1_DisableClock\n
1303 * APB1ENR USART3EN LL_APB1_GRP1_DisableClock\n
1304 * APB1ENR UART4EN LL_APB1_GRP1_DisableClock\n
1305 * APB1ENR UART5EN LL_APB1_GRP1_DisableClock\n
1306 * APB1ENR I2C1EN LL_APB1_GRP1_DisableClock\n
1307 * APB1ENR I2C2EN LL_APB1_GRP1_DisableClock\n
1308 * APB1ENR I2C3EN LL_APB1_GRP1_DisableClock\n
1309 * APB1ENR FMPI2C1EN LL_APB1_GRP1_DisableClock\n
1310 * APB1ENR CAN1EN LL_APB1_GRP1_DisableClock\n
1311 * APB1ENR CAN2EN LL_APB1_GRP1_DisableClock\n
1312 * APB1ENR CAN3EN LL_APB1_GRP1_DisableClock\n
1313 * APB1ENR CECEN LL_APB1_GRP1_DisableClock\n
1314 * APB1ENR PWREN LL_APB1_GRP1_DisableClock\n
1315 * APB1ENR DACEN LL_APB1_GRP1_DisableClock\n
1316 * APB1ENR UART7EN LL_APB1_GRP1_DisableClock\n
1317 * APB1ENR UART8EN LL_APB1_GRP1_DisableClock\n
1318 * APB1ENR RTCAPBEN LL_APB1_GRP1_DisableClock
1319 * @param Periphs This parameter can be a combination of the following values:
1320 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 (*)
1321 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*)
1322 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*)
1323 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5
1324 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*)
1325 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*)
1326 * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 (*)
1327 * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 (*)
1328 * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 (*)
1329 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 (*)
1330 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
1331 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
1332 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*)
1333 * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX (*)
1334 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
1335 * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*)
1336 * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
1337 * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
1338 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
1339 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2
1340 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*)
1341 * @arg @ref LL_APB1_GRP1_PERIPH_FMPI2C1 (*)
1342 * @arg @ref LL_APB1_GRP1_PERIPH_CAN1 (*)
1343 * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*)
1344 * @arg @ref LL_APB1_GRP1_PERIPH_CAN3 (*)
1345 * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*)
1346 * @arg @ref LL_APB1_GRP1_PERIPH_PWR
1347 * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*)
1348 * @arg @ref LL_APB1_GRP1_PERIPH_UART7 (*)
1349 * @arg @ref LL_APB1_GRP1_PERIPH_UART8 (*)
1350 * @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB (*)
1351 *
1352 * (*) value not defined in all devices.
1353 * @retval None
1354 */
1355 __STATIC_INLINE void LL_APB1_GRP1_DisableClock(uint32_t Periphs)
1356 {
1357 CLEAR_BIT(RCC->APB1ENR, Periphs);
1358 }
1359
1360 /**
1361 * @brief Force APB1 peripherals reset.
1362 * @rmtoll APB1RSTR TIM2RST LL_APB1_GRP1_ForceReset\n
1363 * APB1RSTR TIM3RST LL_APB1_GRP1_ForceReset\n
1364 * APB1RSTR TIM4RST LL_APB1_GRP1_ForceReset\n
1365 * APB1RSTR TIM5RST LL_APB1_GRP1_ForceReset\n
1366 * APB1RSTR TIM6RST LL_APB1_GRP1_ForceReset\n
1367 * APB1RSTR TIM7RST LL_APB1_GRP1_ForceReset\n
1368 * APB1RSTR TIM12RST LL_APB1_GRP1_ForceReset\n
1369 * APB1RSTR TIM13RST LL_APB1_GRP1_ForceReset\n
1370 * APB1RSTR TIM14RST LL_APB1_GRP1_ForceReset\n
1371 * APB1RSTR LPTIM1RST LL_APB1_GRP1_ForceReset\n
1372 * APB1RSTR WWDGRST LL_APB1_GRP1_ForceReset\n
1373 * APB1RSTR SPI2RST LL_APB1_GRP1_ForceReset\n
1374 * APB1RSTR SPI3RST LL_APB1_GRP1_ForceReset\n
1375 * APB1RSTR SPDIFRXRST LL_APB1_GRP1_ForceReset\n
1376 * APB1RSTR USART2RST LL_APB1_GRP1_ForceReset\n
1377 * APB1RSTR USART3RST LL_APB1_GRP1_ForceReset\n
1378 * APB1RSTR UART4RST LL_APB1_GRP1_ForceReset\n
1379 * APB1RSTR UART5RST LL_APB1_GRP1_ForceReset\n
1380 * APB1RSTR I2C1RST LL_APB1_GRP1_ForceReset\n
1381 * APB1RSTR I2C2RST LL_APB1_GRP1_ForceReset\n
1382 * APB1RSTR I2C3RST LL_APB1_GRP1_ForceReset\n
1383 * APB1RSTR FMPI2C1RST LL_APB1_GRP1_ForceReset\n
1384 * APB1RSTR CAN1RST LL_APB1_GRP1_ForceReset\n
1385 * APB1RSTR CAN2RST LL_APB1_GRP1_ForceReset\n
1386 * APB1RSTR CAN3RST LL_APB1_GRP1_ForceReset\n
1387 * APB1RSTR CECRST LL_APB1_GRP1_ForceReset\n
1388 * APB1RSTR PWRRST LL_APB1_GRP1_ForceReset\n
1389 * APB1RSTR DACRST LL_APB1_GRP1_ForceReset\n
1390 * APB1RSTR UART7RST LL_APB1_GRP1_ForceReset\n
1391 * APB1RSTR UART8RST LL_APB1_GRP1_ForceReset
1392 * @param Periphs This parameter can be a combination of the following values:
1393 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 (*)
1394 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*)
1395 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*)
1396 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5
1397 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*)
1398 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*)
1399 * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 (*)
1400 * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 (*)
1401 * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 (*)
1402 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 (*)
1403 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
1404 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
1405 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*)
1406 * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX (*)
1407 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
1408 * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*)
1409 * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
1410 * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
1411 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
1412 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2
1413 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*)
1414 * @arg @ref LL_APB1_GRP1_PERIPH_FMPI2C1 (*)
1415 * @arg @ref LL_APB1_GRP1_PERIPH_CAN1 (*)
1416 * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*)
1417 * @arg @ref LL_APB1_GRP1_PERIPH_CAN3 (*)
1418 * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*)
1419 * @arg @ref LL_APB1_GRP1_PERIPH_PWR
1420 * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*)
1421 * @arg @ref LL_APB1_GRP1_PERIPH_UART7 (*)
1422 * @arg @ref LL_APB1_GRP1_PERIPH_UART8 (*)
1423 *
1424 * (*) value not defined in all devices.
1425 * @retval None
1426 */
1427 __STATIC_INLINE void LL_APB1_GRP1_ForceReset(uint32_t Periphs)
1428 {
1429 SET_BIT(RCC->APB1RSTR, Periphs);
1430 }
1431
1432 /**
1433 * @brief Release APB1 peripherals reset.
1434 * @rmtoll APB1RSTR TIM2RST LL_APB1_GRP1_ReleaseReset\n
1435 * APB1RSTR TIM3RST LL_APB1_GRP1_ReleaseReset\n
1436 * APB1RSTR TIM4RST LL_APB1_GRP1_ReleaseReset\n
1437 * APB1RSTR TIM5RST LL_APB1_GRP1_ReleaseReset\n
1438 * APB1RSTR TIM6RST LL_APB1_GRP1_ReleaseReset\n
1439 * APB1RSTR TIM7RST LL_APB1_GRP1_ReleaseReset\n
1440 * APB1RSTR TIM12RST LL_APB1_GRP1_ReleaseReset\n
1441 * APB1RSTR TIM13RST LL_APB1_GRP1_ReleaseReset\n
1442 * APB1RSTR TIM14RST LL_APB1_GRP1_ReleaseReset\n
1443 * APB1RSTR LPTIM1RST LL_APB1_GRP1_ReleaseReset\n
1444 * APB1RSTR WWDGRST LL_APB1_GRP1_ReleaseReset\n
1445 * APB1RSTR SPI2RST LL_APB1_GRP1_ReleaseReset\n
1446 * APB1RSTR SPI3RST LL_APB1_GRP1_ReleaseReset\n
1447 * APB1RSTR SPDIFRXRST LL_APB1_GRP1_ReleaseReset\n
1448 * APB1RSTR USART2RST LL_APB1_GRP1_ReleaseReset\n
1449 * APB1RSTR USART3RST LL_APB1_GRP1_ReleaseReset\n
1450 * APB1RSTR UART4RST LL_APB1_GRP1_ReleaseReset\n
1451 * APB1RSTR UART5RST LL_APB1_GRP1_ReleaseReset\n
1452 * APB1RSTR I2C1RST LL_APB1_GRP1_ReleaseReset\n
1453 * APB1RSTR I2C2RST LL_APB1_GRP1_ReleaseReset\n
1454 * APB1RSTR I2C3RST LL_APB1_GRP1_ReleaseReset\n
1455 * APB1RSTR FMPI2C1RST LL_APB1_GRP1_ReleaseReset\n
1456 * APB1RSTR CAN1RST LL_APB1_GRP1_ReleaseReset\n
1457 * APB1RSTR CAN2RST LL_APB1_GRP1_ReleaseReset\n
1458 * APB1RSTR CAN3RST LL_APB1_GRP1_ReleaseReset\n
1459 * APB1RSTR CECRST LL_APB1_GRP1_ReleaseReset\n
1460 * APB1RSTR PWRRST LL_APB1_GRP1_ReleaseReset\n
1461 * APB1RSTR DACRST LL_APB1_GRP1_ReleaseReset\n
1462 * APB1RSTR UART7RST LL_APB1_GRP1_ReleaseReset\n
1463 * APB1RSTR UART8RST LL_APB1_GRP1_ReleaseReset
1464 * @param Periphs This parameter can be a combination of the following values:
1465 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 (*)
1466 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*)
1467 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*)
1468 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5
1469 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*)
1470 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*)
1471 * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 (*)
1472 * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 (*)
1473 * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 (*)
1474 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 (*)
1475 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
1476 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
1477 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*)
1478 * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX (*)
1479 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
1480 * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*)
1481 * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
1482 * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
1483 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
1484 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2
1485 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*)
1486 * @arg @ref LL_APB1_GRP1_PERIPH_FMPI2C1 (*)
1487 * @arg @ref LL_APB1_GRP1_PERIPH_CAN1 (*)
1488 * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*)
1489 * @arg @ref LL_APB1_GRP1_PERIPH_CAN3 (*)
1490 * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*)
1491 * @arg @ref LL_APB1_GRP1_PERIPH_PWR
1492 * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*)
1493 * @arg @ref LL_APB1_GRP1_PERIPH_UART7 (*)
1494 * @arg @ref LL_APB1_GRP1_PERIPH_UART8 (*)
1495 *
1496 * (*) value not defined in all devices.
1497 * @retval None
1498 */
1499 __STATIC_INLINE void LL_APB1_GRP1_ReleaseReset(uint32_t Periphs)
1500 {
1501 CLEAR_BIT(RCC->APB1RSTR, Periphs);
1502 }
1503
1504 /**
1505 * @brief Enable APB1 peripheral clocks in low-power mode
1506 * @rmtoll APB1LPENR TIM2LPEN LL_APB1_GRP1_EnableClockLowPower\n
1507 * APB1LPENR TIM3LPEN LL_APB1_GRP1_EnableClockLowPower\n
1508 * APB1LPENR TIM4LPEN LL_APB1_GRP1_EnableClockLowPower\n
1509 * APB1LPENR TIM5LPEN LL_APB1_GRP1_EnableClockLowPower\n
1510 * APB1LPENR TIM6LPEN LL_APB1_GRP1_EnableClockLowPower\n
1511 * APB1LPENR TIM7LPEN LL_APB1_GRP1_EnableClockLowPower\n
1512 * APB1LPENR TIM12LPEN LL_APB1_GRP1_EnableClockLowPower\n
1513 * APB1LPENR TIM13LPEN LL_APB1_GRP1_EnableClockLowPower\n
1514 * APB1LPENR TIM14LPEN LL_APB1_GRP1_EnableClockLowPower\n
1515 * APB1LPENR LPTIM1LPEN LL_APB1_GRP1_EnableClockLowPower\n
1516 * APB1LPENR WWDGLPEN LL_APB1_GRP1_EnableClockLowPower\n
1517 * APB1LPENR SPI2LPEN LL_APB1_GRP1_EnableClockLowPower\n
1518 * APB1LPENR SPI3LPEN LL_APB1_GRP1_EnableClockLowPower\n
1519 * APB1LPENR SPDIFRXLPEN LL_APB1_GRP1_EnableClockLowPower\n
1520 * APB1LPENR USART2LPEN LL_APB1_GRP1_EnableClockLowPower\n
1521 * APB1LPENR USART3LPEN LL_APB1_GRP1_EnableClockLowPower\n
1522 * APB1LPENR UART4LPEN LL_APB1_GRP1_EnableClockLowPower\n
1523 * APB1LPENR UART5LPEN LL_APB1_GRP1_EnableClockLowPower\n
1524 * APB1LPENR I2C1LPEN LL_APB1_GRP1_EnableClockLowPower\n
1525 * APB1LPENR I2C2LPEN LL_APB1_GRP1_EnableClockLowPower\n
1526 * APB1LPENR I2C3LPEN LL_APB1_GRP1_EnableClockLowPower\n
1527 * APB1LPENR FMPI2C1LPEN LL_APB1_GRP1_EnableClockLowPower\n
1528 * APB1LPENR CAN1LPEN LL_APB1_GRP1_EnableClockLowPower\n
1529 * APB1LPENR CAN2LPEN LL_APB1_GRP1_EnableClockLowPower\n
1530 * APB1LPENR CAN3LPEN LL_APB1_GRP1_EnableClockLowPower\n
1531 * APB1LPENR CECLPEN LL_APB1_GRP1_EnableClockLowPower\n
1532 * APB1LPENR PWRLPEN LL_APB1_GRP1_EnableClockLowPower\n
1533 * APB1LPENR DACLPEN LL_APB1_GRP1_EnableClockLowPower\n
1534 * APB1LPENR UART7LPEN LL_APB1_GRP1_EnableClockLowPower\n
1535 * APB1LPENR UART8LPEN LL_APB1_GRP1_EnableClockLowPower\n
1536 * APB1LPENR RTCAPBLPEN LL_APB1_GRP1_EnableClockLowPower
1537 * @param Periphs This parameter can be a combination of the following values:
1538 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 (*)
1539 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*)
1540 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*)
1541 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5
1542 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*)
1543 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*)
1544 * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 (*)
1545 * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 (*)
1546 * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 (*)
1547 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 (*)
1548 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
1549 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
1550 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*)
1551 * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX (*)
1552 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
1553 * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*)
1554 * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
1555 * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
1556 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
1557 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2
1558 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*)
1559 * @arg @ref LL_APB1_GRP1_PERIPH_FMPI2C1 (*)
1560 * @arg @ref LL_APB1_GRP1_PERIPH_CAN1 (*)
1561 * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*)
1562 * @arg @ref LL_APB1_GRP1_PERIPH_CAN3 (*)
1563 * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*)
1564 * @arg @ref LL_APB1_GRP1_PERIPH_PWR
1565 * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*)
1566 * @arg @ref LL_APB1_GRP1_PERIPH_UART7 (*)
1567 * @arg @ref LL_APB1_GRP1_PERIPH_UART8 (*)
1568 * @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB (*)
1569 *
1570 * (*) value not defined in all devices.
1571 * @retval None
1572 */
1573 __STATIC_INLINE void LL_APB1_GRP1_EnableClockLowPower(uint32_t Periphs)
1574 {
1575 __IO uint32_t tmpreg;
1576 SET_BIT(RCC->APB1LPENR, Periphs);
1577 /* Delay after an RCC peripheral clock enabling */
1578 tmpreg = READ_BIT(RCC->APB1LPENR, Periphs);
1579 (void)tmpreg;
1580 }
1581
1582 /**
1583 * @brief Disable APB1 peripheral clocks in low-power mode
1584 * @rmtoll APB1LPENR TIM2LPEN LL_APB1_GRP1_DisableClockLowPower\n
1585 * APB1LPENR TIM3LPEN LL_APB1_GRP1_DisableClockLowPower\n
1586 * APB1LPENR TIM4LPEN LL_APB1_GRP1_DisableClockLowPower\n
1587 * APB1LPENR TIM5LPEN LL_APB1_GRP1_DisableClockLowPower\n
1588 * APB1LPENR TIM6LPEN LL_APB1_GRP1_DisableClockLowPower\n
1589 * APB1LPENR TIM7LPEN LL_APB1_GRP1_DisableClockLowPower\n
1590 * APB1LPENR TIM12LPEN LL_APB1_GRP1_DisableClockLowPower\n
1591 * APB1LPENR TIM13LPEN LL_APB1_GRP1_DisableClockLowPower\n
1592 * APB1LPENR TIM14LPEN LL_APB1_GRP1_DisableClockLowPower\n
1593 * APB1LPENR LPTIM1LPEN LL_APB1_GRP1_DisableClockLowPower\n
1594 * APB1LPENR WWDGLPEN LL_APB1_GRP1_DisableClockLowPower\n
1595 * APB1LPENR SPI2LPEN LL_APB1_GRP1_DisableClockLowPower\n
1596 * APB1LPENR SPI3LPEN LL_APB1_GRP1_DisableClockLowPower\n
1597 * APB1LPENR SPDIFRXLPEN LL_APB1_GRP1_DisableClockLowPower\n
1598 * APB1LPENR USART2LPEN LL_APB1_GRP1_DisableClockLowPower\n
1599 * APB1LPENR USART3LPEN LL_APB1_GRP1_DisableClockLowPower\n
1600 * APB1LPENR UART4LPEN LL_APB1_GRP1_DisableClockLowPower\n
1601 * APB1LPENR UART5LPEN LL_APB1_GRP1_DisableClockLowPower\n
1602 * APB1LPENR I2C1LPEN LL_APB1_GRP1_DisableClockLowPower\n
1603 * APB1LPENR I2C2LPEN LL_APB1_GRP1_DisableClockLowPower\n
1604 * APB1LPENR I2C3LPEN LL_APB1_GRP1_DisableClockLowPower\n
1605 * APB1LPENR FMPI2C1LPEN LL_APB1_GRP1_DisableClockLowPower\n
1606 * APB1LPENR CAN1LPEN LL_APB1_GRP1_DisableClockLowPower\n
1607 * APB1LPENR CAN2LPEN LL_APB1_GRP1_DisableClockLowPower\n
1608 * APB1LPENR CAN3LPEN LL_APB1_GRP1_DisableClockLowPower\n
1609 * APB1LPENR CECLPEN LL_APB1_GRP1_DisableClockLowPower\n
1610 * APB1LPENR PWRLPEN LL_APB1_GRP1_DisableClockLowPower\n
1611 * APB1LPENR DACLPEN LL_APB1_GRP1_DisableClockLowPower\n
1612 * APB1LPENR UART7LPEN LL_APB1_GRP1_DisableClockLowPower\n
1613 * APB1LPENR UART8LPEN LL_APB1_GRP1_DisableClockLowPower\n
1614 * APB1LPENR RTCAPBLPEN LL_APB1_GRP1_DisableClockLowPower
1615 * @param Periphs This parameter can be a combination of the following values:
1616 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 (*)
1617 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*)
1618 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*)
1619 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5
1620 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*)
1621 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*)
1622 * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 (*)
1623 * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 (*)
1624 * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 (*)
1625 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 (*)
1626 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
1627 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
1628 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*)
1629 * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX (*)
1630 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
1631 * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*)
1632 * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
1633 * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
1634 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
1635 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2
1636 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*)
1637 * @arg @ref LL_APB1_GRP1_PERIPH_FMPI2C1 (*)
1638 * @arg @ref LL_APB1_GRP1_PERIPH_CAN1 (*)
1639 * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*)
1640 * @arg @ref LL_APB1_GRP1_PERIPH_CAN3 (*)
1641 * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*)
1642 * @arg @ref LL_APB1_GRP1_PERIPH_PWR
1643 * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*)
1644 * @arg @ref LL_APB1_GRP1_PERIPH_UART7 (*)
1645 * @arg @ref LL_APB1_GRP1_PERIPH_UART8 (*)
1646 * @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB (*)
1647 *
1648 * (*) value not defined in all devices.
1649 * @retval None
1650 */
1651 __STATIC_INLINE void LL_APB1_GRP1_DisableClockLowPower(uint32_t Periphs)
1652 {
1653 CLEAR_BIT(RCC->APB1LPENR, Periphs);
1654 }
1655
1656 /**
1657 * @}
1658 */
1659
1660 /** @defgroup BUS_LL_EF_APB2 APB2
1661 * @{
1662 */
1663
1664 /**
1665 * @brief Enable APB2 peripherals clock.
1666 * @rmtoll APB2ENR TIM1EN LL_APB2_GRP1_EnableClock\n
1667 * APB2ENR TIM8EN LL_APB2_GRP1_EnableClock\n
1668 * APB2ENR USART1EN LL_APB2_GRP1_EnableClock\n
1669 * APB2ENR USART6EN LL_APB2_GRP1_EnableClock\n
1670 * APB2ENR UART9EN LL_APB2_GRP1_EnableClock\n
1671 * APB2ENR UART10EN LL_APB2_GRP1_EnableClock\n
1672 * APB2ENR ADC1EN LL_APB2_GRP1_EnableClock\n
1673 * APB2ENR ADC2EN LL_APB2_GRP1_EnableClock\n
1674 * APB2ENR ADC3EN LL_APB2_GRP1_EnableClock\n
1675 * APB2ENR SDIOEN LL_APB2_GRP1_EnableClock\n
1676 * APB2ENR SPI1EN LL_APB2_GRP1_EnableClock\n
1677 * APB2ENR SPI4EN LL_APB2_GRP1_EnableClock\n
1678 * APB2ENR SYSCFGEN LL_APB2_GRP1_EnableClock\n
1679 * APB2ENR EXTITEN LL_APB2_GRP1_EnableClock\n
1680 * APB2ENR TIM9EN LL_APB2_GRP1_EnableClock\n
1681 * APB2ENR TIM10EN LL_APB2_GRP1_EnableClock\n
1682 * APB2ENR TIM11EN LL_APB2_GRP1_EnableClock\n
1683 * APB2ENR SPI5EN LL_APB2_GRP1_EnableClock\n
1684 * APB2ENR SPI6EN LL_APB2_GRP1_EnableClock\n
1685 * APB2ENR SAI1EN LL_APB2_GRP1_EnableClock\n
1686 * APB2ENR SAI2EN LL_APB2_GRP1_EnableClock\n
1687 * APB2ENR LTDCEN LL_APB2_GRP1_EnableClock\n
1688 * APB2ENR DSIEN LL_APB2_GRP1_EnableClock\n
1689 * APB2ENR DFSDM1EN LL_APB2_GRP1_EnableClock\n
1690 * APB2ENR DFSDM2EN LL_APB2_GRP1_EnableClock
1691 * @param Periphs This parameter can be a combination of the following values:
1692 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
1693 * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*)
1694 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
1695 * @arg @ref LL_APB2_GRP1_PERIPH_USART6 (*)
1696 * @arg @ref LL_APB2_GRP1_PERIPH_UART9 (*)
1697 * @arg @ref LL_APB2_GRP1_PERIPH_UART10 (*)
1698 * @arg @ref LL_APB2_GRP1_PERIPH_ADC1
1699 * @arg @ref LL_APB2_GRP1_PERIPH_ADC2 (*)
1700 * @arg @ref LL_APB2_GRP1_PERIPH_ADC3 (*)
1701 * @arg @ref LL_APB2_GRP1_PERIPH_SDIO (*)
1702 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
1703 * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 (*)
1704 * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
1705 * @arg @ref LL_APB2_GRP1_PERIPH_EXTI (*)
1706 * @arg @ref LL_APB2_GRP1_PERIPH_TIM9
1707 * @arg @ref LL_APB2_GRP1_PERIPH_TIM10 (*)
1708 * @arg @ref LL_APB2_GRP1_PERIPH_TIM11
1709 * @arg @ref LL_APB2_GRP1_PERIPH_SPI5 (*)
1710 * @arg @ref LL_APB2_GRP1_PERIPH_SPI6 (*)
1711 * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 (*)
1712 * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*)
1713 * @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*)
1714 * @arg @ref LL_APB2_GRP1_PERIPH_DSI (*)
1715 * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*)
1716 * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM2 (*)
1717
1718 *
1719 * (*) value not defined in all devices.
1720 * @retval None
1721 */
1722 __STATIC_INLINE void LL_APB2_GRP1_EnableClock(uint32_t Periphs)
1723 {
1724 __IO uint32_t tmpreg;
1725 SET_BIT(RCC->APB2ENR, Periphs);
1726 /* Delay after an RCC peripheral clock enabling */
1727 tmpreg = READ_BIT(RCC->APB2ENR, Periphs);
1728 (void)tmpreg;
1729 }
1730
1731 /**
1732 * @brief Check if APB2 peripheral clock is enabled or not
1733 * @rmtoll APB2ENR TIM1EN LL_APB2_GRP1_IsEnabledClock\n
1734 * APB2ENR TIM8EN LL_APB2_GRP1_IsEnabledClock\n
1735 * APB2ENR USART1EN LL_APB2_GRP1_IsEnabledClock\n
1736 * APB2ENR USART6EN LL_APB2_GRP1_IsEnabledClock\n
1737 * APB2ENR UART9EN LL_APB2_GRP1_IsEnabledClock\n
1738 * APB2ENR UART10EN LL_APB2_GRP1_IsEnabledClock\n
1739 * APB2ENR ADC1EN LL_APB2_GRP1_IsEnabledClock\n
1740 * APB2ENR ADC2EN LL_APB2_GRP1_IsEnabledClock\n
1741 * APB2ENR ADC3EN LL_APB2_GRP1_IsEnabledClock\n
1742 * APB2ENR SDIOEN LL_APB2_GRP1_IsEnabledClock\n
1743 * APB2ENR SPI1EN LL_APB2_GRP1_IsEnabledClock\n
1744 * APB2ENR SPI4EN LL_APB2_GRP1_IsEnabledClock\n
1745 * APB2ENR SYSCFGEN LL_APB2_GRP1_IsEnabledClock\n
1746 * APB2ENR EXTITEN LL_APB2_GRP1_IsEnabledClock\n
1747 * APB2ENR TIM9EN LL_APB2_GRP1_IsEnabledClock\n
1748 * APB2ENR TIM10EN LL_APB2_GRP1_IsEnabledClock\n
1749 * APB2ENR TIM11EN LL_APB2_GRP1_IsEnabledClock\n
1750 * APB2ENR SPI5EN LL_APB2_GRP1_IsEnabledClock\n
1751 * APB2ENR SPI6EN LL_APB2_GRP1_IsEnabledClock\n
1752 * APB2ENR SAI1EN LL_APB2_GRP1_IsEnabledClock\n
1753 * APB2ENR SAI2EN LL_APB2_GRP1_IsEnabledClock\n
1754 * APB2ENR LTDCEN LL_APB2_GRP1_IsEnabledClock\n
1755 * APB2ENR DSIEN LL_APB2_GRP1_IsEnabledClock\n
1756 * APB2ENR DFSDM1EN LL_APB2_GRP1_IsEnabledClock\n
1757 * APB2ENR DFSDM2EN LL_APB2_GRP1_IsEnabledClock
1758 * @param Periphs This parameter can be a combination of the following values:
1759 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
1760 * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*)
1761 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
1762 * @arg @ref LL_APB2_GRP1_PERIPH_USART6 (*)
1763 * @arg @ref LL_APB2_GRP1_PERIPH_UART9 (*)
1764 * @arg @ref LL_APB2_GRP1_PERIPH_UART10 (*)
1765 * @arg @ref LL_APB2_GRP1_PERIPH_ADC1
1766 * @arg @ref LL_APB2_GRP1_PERIPH_ADC2 (*)
1767 * @arg @ref LL_APB2_GRP1_PERIPH_ADC3 (*)
1768 * @arg @ref LL_APB2_GRP1_PERIPH_SDIO (*)
1769 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
1770 * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 (*)
1771 * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
1772 * @arg @ref LL_APB2_GRP1_PERIPH_EXTI (*)
1773 * @arg @ref LL_APB2_GRP1_PERIPH_TIM9
1774 * @arg @ref LL_APB2_GRP1_PERIPH_TIM10 (*)
1775 * @arg @ref LL_APB2_GRP1_PERIPH_TIM11
1776 * @arg @ref LL_APB2_GRP1_PERIPH_SPI5 (*)
1777 * @arg @ref LL_APB2_GRP1_PERIPH_SPI6 (*)
1778 * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 (*)
1779 * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*)
1780 * @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*)
1781 * @arg @ref LL_APB2_GRP1_PERIPH_DSI (*)
1782 * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*)
1783 * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM2 (*)
1784 *
1785 * (*) value not defined in all devices.
1786 * @retval State of Periphs (1 or 0).
1787 */
1788 __STATIC_INLINE uint32_t LL_APB2_GRP1_IsEnabledClock(uint32_t Periphs)
1789 {
1790 return (READ_BIT(RCC->APB2ENR, Periphs) == Periphs);
1791 }
1792
1793 /**
1794 * @brief Disable APB2 peripherals clock.
1795 * @rmtoll APB2ENR TIM1EN LL_APB2_GRP1_DisableClock\n
1796 * APB2ENR TIM8EN LL_APB2_GRP1_DisableClock\n
1797 * APB2ENR USART1EN LL_APB2_GRP1_DisableClock\n
1798 * APB2ENR USART6EN LL_APB2_GRP1_DisableClock\n
1799 * APB2ENR UART9EN LL_APB2_GRP1_DisableClock\n
1800 * APB2ENR UART10EN LL_APB2_GRP1_DisableClock\n
1801 * APB2ENR ADC1EN LL_APB2_GRP1_DisableClock\n
1802 * APB2ENR ADC2EN LL_APB2_GRP1_DisableClock\n
1803 * APB2ENR ADC3EN LL_APB2_GRP1_DisableClock\n
1804 * APB2ENR SDIOEN LL_APB2_GRP1_DisableClock\n
1805 * APB2ENR SPI1EN LL_APB2_GRP1_DisableClock\n
1806 * APB2ENR SPI4EN LL_APB2_GRP1_DisableClock\n
1807 * APB2ENR SYSCFGEN LL_APB2_GRP1_DisableClock\n
1808 * APB2ENR EXTITEN LL_APB2_GRP1_DisableClock\n
1809 * APB2ENR TIM9EN LL_APB2_GRP1_DisableClock\n
1810 * APB2ENR TIM10EN LL_APB2_GRP1_DisableClock\n
1811 * APB2ENR TIM11EN LL_APB2_GRP1_DisableClock\n
1812 * APB2ENR SPI5EN LL_APB2_GRP1_DisableClock\n
1813 * APB2ENR SPI6EN LL_APB2_GRP1_DisableClock\n
1814 * APB2ENR SAI1EN LL_APB2_GRP1_DisableClock\n
1815 * APB2ENR SAI2EN LL_APB2_GRP1_DisableClock\n
1816 * APB2ENR LTDCEN LL_APB2_GRP1_DisableClock\n
1817 * APB2ENR DSIEN LL_APB2_GRP1_DisableClock\n
1818 * APB2ENR DFSDM1EN LL_APB2_GRP1_DisableClock\n
1819 * APB2ENR DFSDM2EN LL_APB2_GRP1_DisableClock
1820 * @param Periphs This parameter can be a combination of the following values:
1821 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
1822 * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*)
1823 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
1824 * @arg @ref LL_APB2_GRP1_PERIPH_USART6 (*)
1825 * @arg @ref LL_APB2_GRP1_PERIPH_UART9 (*)
1826 * @arg @ref LL_APB2_GRP1_PERIPH_UART10 (*)
1827 * @arg @ref LL_APB2_GRP1_PERIPH_ADC1
1828 * @arg @ref LL_APB2_GRP1_PERIPH_ADC2 (*)
1829 * @arg @ref LL_APB2_GRP1_PERIPH_ADC3 (*)
1830 * @arg @ref LL_APB2_GRP1_PERIPH_SDIO (*)
1831 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
1832 * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 (*)
1833 * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
1834 * @arg @ref LL_APB2_GRP1_PERIPH_EXTI (*)
1835 * @arg @ref LL_APB2_GRP1_PERIPH_TIM9
1836 * @arg @ref LL_APB2_GRP1_PERIPH_TIM10 (*)
1837 * @arg @ref LL_APB2_GRP1_PERIPH_TIM11
1838 * @arg @ref LL_APB2_GRP1_PERIPH_SPI5 (*)
1839 * @arg @ref LL_APB2_GRP1_PERIPH_SPI6 (*)
1840 * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 (*)
1841 * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*)
1842 * @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*)
1843 * @arg @ref LL_APB2_GRP1_PERIPH_DSI (*)
1844 * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*)
1845 * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM2 (*)
1846 *
1847 * (*) value not defined in all devices.
1848 * @retval None
1849 */
1850 __STATIC_INLINE void LL_APB2_GRP1_DisableClock(uint32_t Periphs)
1851 {
1852 CLEAR_BIT(RCC->APB2ENR, Periphs);
1853 }
1854
1855 /**
1856 * @brief Force APB2 peripherals reset.
1857 * @rmtoll APB2RSTR TIM1RST LL_APB2_GRP1_ForceReset\n
1858 * APB2RSTR TIM8RST LL_APB2_GRP1_ForceReset\n
1859 * APB2RSTR USART1RST LL_APB2_GRP1_ForceReset\n
1860 * APB2RSTR USART6RST LL_APB2_GRP1_ForceReset\n
1861 * APB2RSTR UART9RST LL_APB2_GRP1_ForceReset\n
1862 * APB2RSTR UART10RST LL_APB2_GRP1_ForceReset\n
1863 * APB2RSTR ADCRST LL_APB2_GRP1_ForceReset\n
1864 * APB2RSTR SDIORST LL_APB2_GRP1_ForceReset\n
1865 * APB2RSTR SPI1RST LL_APB2_GRP1_ForceReset\n
1866 * APB2RSTR SPI4RST LL_APB2_GRP1_ForceReset\n
1867 * APB2RSTR SYSCFGRST LL_APB2_GRP1_ForceReset\n
1868 * APB2RSTR TIM9RST LL_APB2_GRP1_ForceReset\n
1869 * APB2RSTR TIM10RST LL_APB2_GRP1_ForceReset\n
1870 * APB2RSTR TIM11RST LL_APB2_GRP1_ForceReset\n
1871 * APB2RSTR SPI5RST LL_APB2_GRP1_ForceReset\n
1872 * APB2RSTR SPI6RST LL_APB2_GRP1_ForceReset\n
1873 * APB2RSTR SAI1RST LL_APB2_GRP1_ForceReset\n
1874 * APB2RSTR SAI2RST LL_APB2_GRP1_ForceReset\n
1875 * APB2RSTR LTDCRST LL_APB2_GRP1_ForceReset\n
1876 * APB2RSTR DSIRST LL_APB2_GRP1_ForceReset\n
1877 * APB2RSTR DFSDM1RST LL_APB2_GRP1_ForceReset\n
1878 * APB2RSTR DFSDM2RST LL_APB2_GRP1_ForceReset
1879 * @param Periphs This parameter can be a combination of the following values:
1880 * @arg @ref LL_APB2_GRP1_PERIPH_ALL
1881 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
1882 * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*)
1883 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
1884 * @arg @ref LL_APB2_GRP1_PERIPH_USART6 (*)
1885 * @arg @ref LL_APB2_GRP1_PERIPH_UART9 (*)
1886 * @arg @ref LL_APB2_GRP1_PERIPH_UART10 (*)
1887 * @arg @ref LL_APB2_GRP1_PERIPH_ADC
1888 * @arg @ref LL_APB2_GRP1_PERIPH_SDIO (*)
1889 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
1890 * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 (*)
1891 * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
1892 * @arg @ref LL_APB2_GRP1_PERIPH_TIM9
1893 * @arg @ref LL_APB2_GRP1_PERIPH_TIM10 (*)
1894 * @arg @ref LL_APB2_GRP1_PERIPH_TIM11
1895 * @arg @ref LL_APB2_GRP1_PERIPH_SPI5 (*)
1896 * @arg @ref LL_APB2_GRP1_PERIPH_SPI6 (*)
1897 * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 (*)
1898 * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*)
1899 * @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*)
1900 * @arg @ref LL_APB2_GRP1_PERIPH_DSI (*)
1901 * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*)
1902 * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM2 (*)
1903 *
1904 * (*) value not defined in all devices.
1905 * @retval None
1906 */
1907 __STATIC_INLINE void LL_APB2_GRP1_ForceReset(uint32_t Periphs)
1908 {
1909 SET_BIT(RCC->APB2RSTR, Periphs);
1910 }
1911
1912 /**
1913 * @brief Release APB2 peripherals reset.
1914 * @rmtoll APB2RSTR TIM1RST LL_APB2_GRP1_ReleaseReset\n
1915 * APB2RSTR TIM8RST LL_APB2_GRP1_ReleaseReset\n
1916 * APB2RSTR USART1RST LL_APB2_GRP1_ReleaseReset\n
1917 * APB2RSTR USART6RST LL_APB2_GRP1_ReleaseReset\n
1918 * APB2RSTR UART9RST LL_APB2_GRP1_ReleaseReset\n
1919 * APB2RSTR UART10RST LL_APB2_GRP1_ReleaseReset\n
1920 * APB2RSTR ADCRST LL_APB2_GRP1_ReleaseReset\n
1921 * APB2RSTR SDIORST LL_APB2_GRP1_ReleaseReset\n
1922 * APB2RSTR SPI1RST LL_APB2_GRP1_ReleaseReset\n
1923 * APB2RSTR SPI4RST LL_APB2_GRP1_ReleaseReset\n
1924 * APB2RSTR SYSCFGRST LL_APB2_GRP1_ReleaseReset\n
1925 * APB2RSTR TIM9RST LL_APB2_GRP1_ReleaseReset\n
1926 * APB2RSTR TIM10RST LL_APB2_GRP1_ReleaseReset\n
1927 * APB2RSTR TIM11RST LL_APB2_GRP1_ReleaseReset\n
1928 * APB2RSTR SPI5RST LL_APB2_GRP1_ReleaseReset\n
1929 * APB2RSTR SPI6RST LL_APB2_GRP1_ReleaseReset\n
1930 * APB2RSTR SAI1RST LL_APB2_GRP1_ReleaseReset\n
1931 * APB2RSTR SAI2RST LL_APB2_GRP1_ReleaseReset\n
1932 * APB2RSTR LTDCRST LL_APB2_GRP1_ReleaseReset\n
1933 * APB2RSTR DSIRST LL_APB2_GRP1_ReleaseReset\n
1934 * APB2RSTR DFSDM1RST LL_APB2_GRP1_ReleaseReset\n
1935 * APB2RSTR DFSDM2RST LL_APB2_GRP1_ReleaseReset
1936 * @param Periphs This parameter can be a combination of the following values:
1937 * @arg @ref LL_APB2_GRP1_PERIPH_ALL
1938 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
1939 * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*)
1940 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
1941 * @arg @ref LL_APB2_GRP1_PERIPH_USART6 (*)
1942 * @arg @ref LL_APB2_GRP1_PERIPH_UART9 (*)
1943 * @arg @ref LL_APB2_GRP1_PERIPH_UART10 (*)
1944 * @arg @ref LL_APB2_GRP1_PERIPH_ADC
1945 * @arg @ref LL_APB2_GRP1_PERIPH_SDIO (*)
1946 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
1947 * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 (*)
1948 * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
1949 * @arg @ref LL_APB2_GRP1_PERIPH_EXTI (*)
1950 * @arg @ref LL_APB2_GRP1_PERIPH_TIM9
1951 * @arg @ref LL_APB2_GRP1_PERIPH_TIM10 (*)
1952 * @arg @ref LL_APB2_GRP1_PERIPH_TIM11
1953 * @arg @ref LL_APB2_GRP1_PERIPH_SPI5 (*)
1954 * @arg @ref LL_APB2_GRP1_PERIPH_SPI6 (*)
1955 * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 (*)
1956 * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*)
1957 * @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*)
1958 * @arg @ref LL_APB2_GRP1_PERIPH_DSI (*)
1959 * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*)
1960 * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM2 (*)
1961 *
1962 * (*) value not defined in all devices.
1963 * @retval None
1964 */
1965 __STATIC_INLINE void LL_APB2_GRP1_ReleaseReset(uint32_t Periphs)
1966 {
1967 CLEAR_BIT(RCC->APB2RSTR, Periphs);
1968 }
1969
1970 /**
1971 * @brief Enable APB2 peripheral clocks in low-power mode
1972 * @rmtoll APB2LPENR TIM1LPEN LL_APB2_GRP1_EnableClockLowPower\n
1973 * APB2LPENR TIM8LPEN LL_APB2_GRP1_EnableClockLowPower\n
1974 * APB2LPENR USART1LPEN LL_APB2_GRP1_EnableClockLowPower\n
1975 * APB2LPENR USART6LPEN LL_APB2_GRP1_EnableClockLowPower\n
1976 * APB2LPENR UART9LPEN LL_APB2_GRP1_EnableClockLowPower\n
1977 * APB2LPENR UART10LPEN LL_APB2_GRP1_EnableClockLowPower\n
1978 * APB2LPENR ADC1LPEN LL_APB2_GRP1_EnableClockLowPower\n
1979 * APB2LPENR ADC2LPEN LL_APB2_GRP1_EnableClockLowPower\n
1980 * APB2LPENR ADC3LPEN LL_APB2_GRP1_EnableClockLowPower\n
1981 * APB2LPENR SDIOLPEN LL_APB2_GRP1_EnableClockLowPower\n
1982 * APB2LPENR SPI1LPEN LL_APB2_GRP1_EnableClockLowPower\n
1983 * APB2LPENR SPI4LPEN LL_APB2_GRP1_EnableClockLowPower\n
1984 * APB2LPENR SYSCFGLPEN LL_APB2_GRP1_EnableClockLowPower\n
1985 * APB2LPENR EXTITLPEN LL_APB2_GRP1_EnableClockLowPower\n
1986 * APB2LPENR TIM9LPEN LL_APB2_GRP1_EnableClockLowPower\n
1987 * APB2LPENR TIM10LPEN LL_APB2_GRP1_EnableClockLowPower\n
1988 * APB2LPENR TIM11LPEN LL_APB2_GRP1_EnableClockLowPower\n
1989 * APB2LPENR SPI5LPEN LL_APB2_GRP1_EnableClockLowPower\n
1990 * APB2LPENR SPI6LPEN LL_APB2_GRP1_EnableClockLowPower\n
1991 * APB2LPENR SAI1LPEN LL_APB2_GRP1_EnableClockLowPower\n
1992 * APB2LPENR SAI2LPEN LL_APB2_GRP1_EnableClockLowPower\n
1993 * APB2LPENR LTDCLPEN LL_APB2_GRP1_EnableClockLowPower\n
1994 * APB2LPENR DSILPEN LL_APB2_GRP1_EnableClockLowPower\n
1995 * APB2LPENR DFSDM1LPEN LL_APB2_GRP1_EnableClockLowPower\n
1996 * APB2LPENR DSILPEN LL_APB2_GRP1_EnableClockLowPower\n
1997 * APB2LPENR DFSDM2LPEN LL_APB2_GRP1_EnableClockLowPower
1998 * @param Periphs This parameter can be a combination of the following values:
1999 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
2000 * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*)
2001 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
2002 * @arg @ref LL_APB2_GRP1_PERIPH_USART6 (*)
2003 * @arg @ref LL_APB2_GRP1_PERIPH_UART9 (*)
2004 * @arg @ref LL_APB2_GRP1_PERIPH_UART10 (*)
2005 * @arg @ref LL_APB2_GRP1_PERIPH_ADC1
2006 * @arg @ref LL_APB2_GRP1_PERIPH_ADC2 (*)
2007 * @arg @ref LL_APB2_GRP1_PERIPH_ADC3 (*)
2008 * @arg @ref LL_APB2_GRP1_PERIPH_SDIO (*)
2009 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
2010 * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 (*)
2011 * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
2012 * @arg @ref LL_APB2_GRP1_PERIPH_EXTI (*)
2013 * @arg @ref LL_APB2_GRP1_PERIPH_TIM9
2014 * @arg @ref LL_APB2_GRP1_PERIPH_TIM10 (*)
2015 * @arg @ref LL_APB2_GRP1_PERIPH_TIM11
2016 * @arg @ref LL_APB2_GRP1_PERIPH_SPI5 (*)
2017 * @arg @ref LL_APB2_GRP1_PERIPH_SPI6 (*)
2018 * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 (*)
2019 * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*)
2020 * @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*)
2021 * @arg @ref LL_APB2_GRP1_PERIPH_DSI (*)
2022 * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*)
2023 * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM2 (*)
2024 *
2025 * (*) value not defined in all devices.
2026 * @retval None
2027 */
2028 __STATIC_INLINE void LL_APB2_GRP1_EnableClockLowPower(uint32_t Periphs)
2029 {
2030 __IO uint32_t tmpreg;
2031 SET_BIT(RCC->APB2LPENR, Periphs);
2032 /* Delay after an RCC peripheral clock enabling */
2033 tmpreg = READ_BIT(RCC->APB2LPENR, Periphs);
2034 (void)tmpreg;
2035 }
2036
2037 /**
2038 * @brief Disable APB2 peripheral clocks in low-power mode
2039 * @rmtoll APB2LPENR TIM1LPEN LL_APB2_GRP1_DisableClockLowPower\n
2040 * APB2LPENR TIM8LPEN LL_APB2_GRP1_DisableClockLowPower\n
2041 * APB2LPENR USART1LPEN LL_APB2_GRP1_DisableClockLowPower\n
2042 * APB2LPENR USART6LPEN LL_APB2_GRP1_DisableClockLowPower\n
2043 * APB2LPENR UART9LPEN LL_APB2_GRP1_DisableClockLowPower\n
2044 * APB2LPENR UART10LPEN LL_APB2_GRP1_DisableClockLowPower\n
2045 * APB2LPENR ADC1LPEN LL_APB2_GRP1_DisableClockLowPower\n
2046 * APB2LPENR ADC2LPEN LL_APB2_GRP1_DisableClockLowPower\n
2047 * APB2LPENR ADC3LPEN LL_APB2_GRP1_DisableClockLowPower\n
2048 * APB2LPENR SDIOLPEN LL_APB2_GRP1_DisableClockLowPower\n
2049 * APB2LPENR SPI1LPEN LL_APB2_GRP1_DisableClockLowPower\n
2050 * APB2LPENR SPI4LPEN LL_APB2_GRP1_DisableClockLowPower\n
2051 * APB2LPENR SYSCFGLPEN LL_APB2_GRP1_DisableClockLowPower\n
2052 * APB2LPENR EXTITLPEN LL_APB2_GRP1_DisableClockLowPower\n
2053 * APB2LPENR TIM9LPEN LL_APB2_GRP1_DisableClockLowPower\n
2054 * APB2LPENR TIM10LPEN LL_APB2_GRP1_DisableClockLowPower\n
2055 * APB2LPENR TIM11LPEN LL_APB2_GRP1_DisableClockLowPower\n
2056 * APB2LPENR SPI5LPEN LL_APB2_GRP1_DisableClockLowPower\n
2057 * APB2LPENR SPI6LPEN LL_APB2_GRP1_DisableClockLowPower\n
2058 * APB2LPENR SAI1LPEN LL_APB2_GRP1_DisableClockLowPower\n
2059 * APB2LPENR SAI2LPEN LL_APB2_GRP1_DisableClockLowPower\n
2060 * APB2LPENR LTDCLPEN LL_APB2_GRP1_DisableClockLowPower\n
2061 * APB2LPENR DSILPEN LL_APB2_GRP1_DisableClockLowPower\n
2062 * APB2LPENR DFSDM1LPEN LL_APB2_GRP1_DisableClockLowPower\n
2063 * APB2LPENR DSILPEN LL_APB2_GRP1_DisableClockLowPower\n
2064 * APB2LPENR DFSDM2LPEN LL_APB2_GRP1_DisableClockLowPower
2065 * @param Periphs This parameter can be a combination of the following values:
2066 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
2067 * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*)
2068 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
2069 * @arg @ref LL_APB2_GRP1_PERIPH_USART6 (*)
2070 * @arg @ref LL_APB2_GRP1_PERIPH_UART9 (*)
2071 * @arg @ref LL_APB2_GRP1_PERIPH_UART10 (*)
2072 * @arg @ref LL_APB2_GRP1_PERIPH_ADC1
2073 * @arg @ref LL_APB2_GRP1_PERIPH_ADC2 (*)
2074 * @arg @ref LL_APB2_GRP1_PERIPH_ADC3 (*)
2075 * @arg @ref LL_APB2_GRP1_PERIPH_SDIO (*)
2076 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
2077 * @arg @ref LL_APB2_GRP1_PERIPH_SPI4 (*)
2078 * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
2079 * @arg @ref LL_APB2_GRP1_PERIPH_EXTI (*)
2080 * @arg @ref LL_APB2_GRP1_PERIPH_TIM9
2081 * @arg @ref LL_APB2_GRP1_PERIPH_TIM10 (*)
2082 * @arg @ref LL_APB2_GRP1_PERIPH_TIM11
2083 * @arg @ref LL_APB2_GRP1_PERIPH_SPI5 (*)
2084 * @arg @ref LL_APB2_GRP1_PERIPH_SPI6 (*)
2085 * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 (*)
2086 * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*)
2087 * @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*)
2088 * @arg @ref LL_APB2_GRP1_PERIPH_DSI (*)
2089 * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*)
2090 * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM2 (*)
2091 *
2092 * (*) value not defined in all devices.
2093 * @retval None
2094 */
2095 __STATIC_INLINE void LL_APB2_GRP1_DisableClockLowPower(uint32_t Periphs)
2096 {
2097 CLEAR_BIT(RCC->APB2LPENR, Periphs);
2098 }
2099
2100 /**
2101 * @}
2102 */
2103
2104 /**
2105 * @}
2106 */
2107
2108 /**
2109 * @}
2110 */
2111
2112 #endif /* defined(RCC) */
2113
2114 /**
2115 * @}
2116 */
2117
2118 #ifdef __cplusplus
2119 }
2120 #endif
2121
2122 #endif /* __STM32F4xx_LL_BUS_H */
2123
2124 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/