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comparison Common/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_nand.h @ 160:e3ca52b8e7fa
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author | heinrichsweikamp |
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date | Thu, 07 Mar 2019 15:06:43 +0100 |
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1 /** | |
2 ****************************************************************************** | |
3 * @file stm32f4xx_hal_nand.h | |
4 * @author MCD Application Team | |
5 * @brief Header file of NAND HAL module. | |
6 ****************************************************************************** | |
7 * @attention | |
8 * | |
9 * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2> | |
10 * | |
11 * Redistribution and use in source and binary forms, with or without modification, | |
12 * are permitted provided that the following conditions are met: | |
13 * 1. Redistributions of source code must retain the above copyright notice, | |
14 * this list of conditions and the following disclaimer. | |
15 * 2. Redistributions in binary form must reproduce the above copyright notice, | |
16 * this list of conditions and the following disclaimer in the documentation | |
17 * and/or other materials provided with the distribution. | |
18 * 3. Neither the name of STMicroelectronics nor the names of its contributors | |
19 * may be used to endorse or promote products derived from this software | |
20 * without specific prior written permission. | |
21 * | |
22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" | |
23 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE | |
24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE | |
25 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE | |
26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL | |
27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR | |
28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER | |
29 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, | |
30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE | |
31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | |
32 * | |
33 ****************************************************************************** | |
34 */ | |
35 | |
36 /* Define to prevent recursive inclusion -------------------------------------*/ | |
37 #ifndef __STM32F4xx_HAL_NAND_H | |
38 #define __STM32F4xx_HAL_NAND_H | |
39 | |
40 #ifdef __cplusplus | |
41 extern "C" { | |
42 #endif | |
43 | |
44 /* Includes ------------------------------------------------------------------*/ | |
45 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) | |
46 #include "stm32f4xx_ll_fsmc.h" | |
47 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */ | |
48 | |
49 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\ | |
50 defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) | |
51 #include "stm32f4xx_ll_fmc.h" | |
52 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx ||\ | |
53 STM32F479xx */ | |
54 | |
55 /** @addtogroup STM32F4xx_HAL_Driver | |
56 * @{ | |
57 */ | |
58 | |
59 /** @addtogroup NAND | |
60 * @{ | |
61 */ | |
62 | |
63 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \ | |
64 defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \ | |
65 defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) | |
66 | |
67 /* Exported typedef ----------------------------------------------------------*/ | |
68 /* Exported types ------------------------------------------------------------*/ | |
69 /** @defgroup NAND_Exported_Types NAND Exported Types | |
70 * @{ | |
71 */ | |
72 | |
73 /** | |
74 * @brief HAL NAND State structures definition | |
75 */ | |
76 typedef enum | |
77 { | |
78 HAL_NAND_STATE_RESET = 0x00U, /*!< NAND not yet initialized or disabled */ | |
79 HAL_NAND_STATE_READY = 0x01U, /*!< NAND initialized and ready for use */ | |
80 HAL_NAND_STATE_BUSY = 0x02U, /*!< NAND internal process is ongoing */ | |
81 HAL_NAND_STATE_ERROR = 0x03U /*!< NAND error state */ | |
82 }HAL_NAND_StateTypeDef; | |
83 | |
84 /** | |
85 * @brief NAND Memory electronic signature Structure definition | |
86 */ | |
87 typedef struct | |
88 { | |
89 /*<! NAND memory electronic signature maker and device IDs */ | |
90 | |
91 uint8_t Maker_Id; | |
92 | |
93 uint8_t Device_Id; | |
94 | |
95 uint8_t Third_Id; | |
96 | |
97 uint8_t Fourth_Id; | |
98 }NAND_IDTypeDef; | |
99 | |
100 /** | |
101 * @brief NAND Memory address Structure definition | |
102 */ | |
103 typedef struct | |
104 { | |
105 uint16_t Page; /*!< NAND memory Page address */ | |
106 | |
107 uint16_t Plane; /*!< NAND memory Plane address */ | |
108 | |
109 uint16_t Block; /*!< NAND memory Block address */ | |
110 | |
111 }NAND_AddressTypeDef; | |
112 | |
113 /** | |
114 * @brief NAND Memory info Structure definition | |
115 */ | |
116 typedef struct | |
117 { | |
118 uint32_t PageSize; /*!< NAND memory page (without spare area) size measured in bytes | |
119 for 8 bits adressing or words for 16 bits addressing */ | |
120 | |
121 uint32_t SpareAreaSize; /*!< NAND memory spare area size measured in bytes | |
122 for 8 bits adressing or words for 16 bits addressing */ | |
123 | |
124 uint32_t BlockSize; /*!< NAND memory block size measured in number of pages */ | |
125 | |
126 uint32_t BlockNbr; /*!< NAND memory number of total blocks */ | |
127 | |
128 uint32_t PlaneNbr; /*!< NAND memory number of planes */ | |
129 | |
130 uint32_t PlaneSize; /*!< NAND memory plane size measured in number of blocks */ | |
131 | |
132 FunctionalState ExtraCommandEnable; /*!< NAND extra command needed for Page reading mode. This | |
133 parameter is mandatory for some NAND parts after the read | |
134 command (NAND_CMD_AREA_TRUE1) and before DATA reading sequence. | |
135 Example: Toshiba THTH58BYG3S0HBAI6. | |
136 This parameter could be ENABLE or DISABLE | |
137 Please check the Read Mode sequnece in the NAND device datasheet */ | |
138 }NAND_DeviceConfigTypeDef; | |
139 | |
140 /** | |
141 * @brief NAND handle Structure definition | |
142 */ | |
143 typedef struct | |
144 { | |
145 FMC_NAND_TypeDef *Instance; /*!< Register base address */ | |
146 | |
147 FMC_NAND_InitTypeDef Init; /*!< NAND device control configuration parameters */ | |
148 | |
149 HAL_LockTypeDef Lock; /*!< NAND locking object */ | |
150 | |
151 __IO HAL_NAND_StateTypeDef State; /*!< NAND device access state */ | |
152 | |
153 NAND_DeviceConfigTypeDef Config; /*!< NAND phusical characteristic information structure */ | |
154 | |
155 }NAND_HandleTypeDef; | |
156 /** | |
157 * @} | |
158 */ | |
159 | |
160 /* Exported constants --------------------------------------------------------*/ | |
161 /* Exported macros ------------------------------------------------------------*/ | |
162 /** @defgroup NAND_Exported_Macros NAND Exported Macros | |
163 * @{ | |
164 */ | |
165 | |
166 /** @brief Reset NAND handle state | |
167 * @param __HANDLE__ specifies the NAND handle. | |
168 * @retval None | |
169 */ | |
170 #define __HAL_NAND_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_NAND_STATE_RESET) | |
171 | |
172 /** | |
173 * @} | |
174 */ | |
175 | |
176 /* Exported functions --------------------------------------------------------*/ | |
177 /** @addtogroup NAND_Exported_Functions NAND Exported Functions | |
178 * @{ | |
179 */ | |
180 | |
181 /** @addtogroup NAND_Exported_Functions_Group1 Initialization and de-initialization functions | |
182 * @{ | |
183 */ | |
184 | |
185 /* Initialization/de-initialization functions ********************************/ | |
186 /* Initialization/de-initialization functions ********************************/ | |
187 HAL_StatusTypeDef HAL_NAND_Init(NAND_HandleTypeDef *hnand, FMC_NAND_PCC_TimingTypeDef *ComSpace_Timing, FMC_NAND_PCC_TimingTypeDef *AttSpace_Timing); | |
188 HAL_StatusTypeDef HAL_NAND_DeInit(NAND_HandleTypeDef *hnand); | |
189 | |
190 HAL_StatusTypeDef HAL_NAND_ConfigDevice(NAND_HandleTypeDef *hnand, NAND_DeviceConfigTypeDef *pDeviceConfig); | |
191 | |
192 HAL_StatusTypeDef HAL_NAND_Read_ID(NAND_HandleTypeDef *hnand, NAND_IDTypeDef *pNAND_ID); | |
193 | |
194 void HAL_NAND_MspInit(NAND_HandleTypeDef *hnand); | |
195 void HAL_NAND_MspDeInit(NAND_HandleTypeDef *hnand); | |
196 void HAL_NAND_IRQHandler(NAND_HandleTypeDef *hnand); | |
197 void HAL_NAND_ITCallback(NAND_HandleTypeDef *hnand); | |
198 | |
199 /** | |
200 * @} | |
201 */ | |
202 | |
203 /** @addtogroup NAND_Exported_Functions_Group2 Input and Output functions | |
204 * @{ | |
205 */ | |
206 | |
207 /* IO operation functions ****************************************************/ | |
208 HAL_StatusTypeDef HAL_NAND_Reset(NAND_HandleTypeDef *hnand); | |
209 | |
210 HAL_StatusTypeDef HAL_NAND_Read_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToRead); | |
211 HAL_StatusTypeDef HAL_NAND_Write_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToWrite); | |
212 HAL_StatusTypeDef HAL_NAND_Read_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaToRead); | |
213 HAL_StatusTypeDef HAL_NAND_Write_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaTowrite); | |
214 | |
215 HAL_StatusTypeDef HAL_NAND_Read_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumPageToRead); | |
216 HAL_StatusTypeDef HAL_NAND_Write_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumPageToWrite); | |
217 HAL_StatusTypeDef HAL_NAND_Read_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumSpareAreaToRead); | |
218 HAL_StatusTypeDef HAL_NAND_Write_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumSpareAreaTowrite); | |
219 | |
220 HAL_StatusTypeDef HAL_NAND_Erase_Block(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress); | |
221 | |
222 uint32_t HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand); | |
223 uint32_t HAL_NAND_Address_Inc(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress); | |
224 | |
225 /** | |
226 * @} | |
227 */ | |
228 | |
229 /** @addtogroup NAND_Exported_Functions_Group3 Peripheral Control functions | |
230 * @{ | |
231 */ | |
232 | |
233 /* NAND Control functions ****************************************************/ | |
234 HAL_StatusTypeDef HAL_NAND_ECC_Enable(NAND_HandleTypeDef *hnand); | |
235 HAL_StatusTypeDef HAL_NAND_ECC_Disable(NAND_HandleTypeDef *hnand); | |
236 HAL_StatusTypeDef HAL_NAND_GetECC(NAND_HandleTypeDef *hnand, uint32_t *ECCval, uint32_t Timeout); | |
237 | |
238 /** | |
239 * @} | |
240 */ | |
241 | |
242 /** @addtogroup NAND_Exported_Functions_Group4 Peripheral State functions | |
243 * @{ | |
244 */ | |
245 /* NAND State functions *******************************************************/ | |
246 HAL_NAND_StateTypeDef HAL_NAND_GetState(NAND_HandleTypeDef *hnand); | |
247 /** | |
248 * @} | |
249 */ | |
250 | |
251 /** | |
252 * @} | |
253 */ | |
254 | |
255 /* Private types -------------------------------------------------------------*/ | |
256 /* Private variables ---------------------------------------------------------*/ | |
257 /* Private constants ---------------------------------------------------------*/ | |
258 /** @defgroup NAND_Private_Constants NAND Private Constants | |
259 * @{ | |
260 */ | |
261 #define NAND_DEVICE1 0x70000000U | |
262 #define NAND_DEVICE2 0x80000000U | |
263 #define NAND_WRITE_TIMEOUT 0x01000000U | |
264 | |
265 #define CMD_AREA ((uint32_t)(1U<<16U)) /* A16 = CLE high */ | |
266 #define ADDR_AREA ((uint32_t)(1U<<17U)) /* A17 = ALE high */ | |
267 | |
268 #define NAND_CMD_AREA_A ((uint8_t)0x00) | |
269 #define NAND_CMD_AREA_B ((uint8_t)0x01) | |
270 #define NAND_CMD_AREA_C ((uint8_t)0x50) | |
271 #define NAND_CMD_AREA_TRUE1 ((uint8_t)0x30) | |
272 | |
273 #define NAND_CMD_WRITE0 ((uint8_t)0x80) | |
274 #define NAND_CMD_WRITE_TRUE1 ((uint8_t)0x10) | |
275 #define NAND_CMD_ERASE0 ((uint8_t)0x60) | |
276 #define NAND_CMD_ERASE1 ((uint8_t)0xD0) | |
277 #define NAND_CMD_READID ((uint8_t)0x90) | |
278 #define NAND_CMD_STATUS ((uint8_t)0x70) | |
279 #define NAND_CMD_LOCK_STATUS ((uint8_t)0x7A) | |
280 #define NAND_CMD_RESET ((uint8_t)0xFF) | |
281 | |
282 /* NAND memory status */ | |
283 #define NAND_VALID_ADDRESS 0x00000100U | |
284 #define NAND_INVALID_ADDRESS 0x00000200U | |
285 #define NAND_TIMEOUT_ERROR 0x00000400U | |
286 #define NAND_BUSY 0x00000000U | |
287 #define NAND_ERROR 0x00000001U | |
288 #define NAND_READY 0x00000040U | |
289 /** | |
290 * @} | |
291 */ | |
292 | |
293 /* Private macros ------------------------------------------------------------*/ | |
294 /** @defgroup NAND_Private_Macros NAND Private Macros | |
295 * @{ | |
296 */ | |
297 | |
298 /** | |
299 * @brief NAND memory address computation. | |
300 * @param __ADDRESS__ NAND memory address. | |
301 * @param __HANDLE__ NAND handle. | |
302 * @retval NAND Raw address value | |
303 */ | |
304 #define ARRAY_ADDRESS(__ADDRESS__ , __HANDLE__) ((__ADDRESS__)->Page + \ | |
305 (((__ADDRESS__)->Block + (((__ADDRESS__)->Plane) * ((__HANDLE__)->Config.PlaneSize)))* ((__HANDLE__)->Config.BlockSize))) | |
306 | |
307 /** | |
308 * @brief NAND memory Column address computation. | |
309 * @param __HANDLE__ NAND handle. | |
310 * @retval NAND Raw address value | |
311 */ | |
312 #define COLUMN_ADDRESS( __HANDLE__) ((__HANDLE__)->Config.PageSize) | |
313 | |
314 /** | |
315 * @brief NAND memory address cycling. | |
316 * @param __ADDRESS__ NAND memory address. | |
317 * @retval NAND address cycling value. | |
318 */ | |
319 #define ADDR_1ST_CYCLE(__ADDRESS__) (uint8_t)(__ADDRESS__) /* 1st addressing cycle */ | |
320 #define ADDR_2ND_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) >> 8) /* 2nd addressing cycle */ | |
321 #define ADDR_3RD_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) >> 16) /* 3rd addressing cycle */ | |
322 #define ADDR_4TH_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) >> 24) /* 4th addressing cycle */ | |
323 | |
324 /** | |
325 * @brief NAND memory Columns cycling. | |
326 * @param __ADDRESS__ NAND memory address. | |
327 * @retval NAND Column address cycling value. | |
328 */ | |
329 #define COLUMN_1ST_CYCLE(__ADDRESS__) (uint8_t)(__ADDRESS__) /* 1st Column addressing cycle */ | |
330 #define COLUMN_2ND_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) >> 8) /* 2nd Column addressing cycle */ | |
331 | |
332 /** | |
333 * @} | |
334 */ | |
335 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx ||\ | |
336 STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx ||\ | |
337 STM32F446xx || STM32F469xx || STM32F479xx */ | |
338 | |
339 /** | |
340 * @} | |
341 */ | |
342 /** | |
343 * @} | |
344 */ | |
345 | |
346 /** | |
347 * @} | |
348 */ | |
349 | |
350 #ifdef __cplusplus | |
351 } | |
352 #endif | |
353 | |
354 #endif /* __STM32F4xx_HAL_NAND_H */ | |
355 | |
356 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |