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comparison Common/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_fmpi2c.h @ 160:e3ca52b8e7fa

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Merge with FlipDisplay
author heinrichsweikamp
date Thu, 07 Mar 2019 15:06:43 +0100
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80:cc2bb7bb8456 160:e3ca52b8e7fa
1 /**
2 ******************************************************************************
3 * @file stm32f4xx_hal_fmpi2c.h
4 * @author MCD Application Team
5 * @brief Header file of FMPI2C HAL module.
6 ******************************************************************************
7 * @attention
8 *
9 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
10 *
11 * Redistribution and use in source and binary forms, with or without modification,
12 * are permitted provided that the following conditions are met:
13 * 1. Redistributions of source code must retain the above copyright notice,
14 * this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright notice,
16 * this list of conditions and the following disclaimer in the documentation
17 * and/or other materials provided with the distribution.
18 * 3. Neither the name of STMicroelectronics nor the names of its contributors
19 * may be used to endorse or promote products derived from this software
20 * without specific prior written permission.
21 *
22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
23 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
25 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
29 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32 *
33 ******************************************************************************
34 */
35
36 /* Define to prevent recursive inclusion -------------------------------------*/
37 #ifndef __STM32F4xx_HAL_FMPI2C_H
38 #define __STM32F4xx_HAL_FMPI2C_H
39
40 #ifdef __cplusplus
41 extern "C" {
42 #endif
43
44 #if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F446xx) || defined(STM32F412Zx) ||\
45 defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)
46
47 /* Includes ------------------------------------------------------------------*/
48 #include "stm32f4xx_hal_def.h"
49
50 /** @addtogroup STM32F4xx_HAL_Driver
51 * @{
52 */
53
54 /** @addtogroup FMPI2C
55 * @{
56 */
57
58 /* Exported types ------------------------------------------------------------*/
59 /** @defgroup FMPI2C_Exported_Types FMPI2C Exported Types
60 * @{
61 */
62
63 /** @defgroup FMPI2C_Configuration_Structure_definition FMPI2C Configuration Structure definition
64 * @brief FMPI2C Configuration Structure definition
65 * @{
66 */
67 typedef struct
68 {
69 uint32_t Timing; /*!< Specifies the FMPI2C_TIMINGR_register value.
70 This parameter calculated by referring to FMPI2C initialization
71 section in Reference manual */
72
73 uint32_t OwnAddress1; /*!< Specifies the first device own address.
74 This parameter can be a 7-bit or 10-bit address. */
75
76 uint32_t AddressingMode; /*!< Specifies if 7-bit or 10-bit addressing mode is selected.
77 This parameter can be a value of @ref FMPI2C_ADDRESSING_MODE */
78
79 uint32_t DualAddressMode; /*!< Specifies if dual addressing mode is selected.
80 This parameter can be a value of @ref FMPI2C_DUAL_ADDRESSING_MODE */
81
82 uint32_t OwnAddress2; /*!< Specifies the second device own address if dual addressing mode is selected
83 This parameter can be a 7-bit address. */
84
85 uint32_t OwnAddress2Masks; /*!< Specifies the acknowledge mask address second device own address if dual addressing mode is selected
86 This parameter can be a value of @ref FMPI2C_OWN_ADDRESS2_MASKS */
87
88 uint32_t GeneralCallMode; /*!< Specifies if general call mode is selected.
89 This parameter can be a value of @ref FMPI2C_GENERAL_CALL_ADDRESSING_MODE */
90
91 uint32_t NoStretchMode; /*!< Specifies if nostretch mode is selected.
92 This parameter can be a value of @ref FMPI2C_NOSTRETCH_MODE */
93
94 } FMPI2C_InitTypeDef;
95
96 /**
97 * @}
98 */
99
100 /** @defgroup HAL_state_structure_definition HAL state structure definition
101 * @brief HAL State structure definition
102 * @note HAL FMPI2C State value coding follow below described bitmap :\n
103 * b7-b6 Error information\n
104 * 00 : No Error\n
105 * 01 : Abort (Abort user request on going)\n
106 * 10 : Timeout\n
107 * 11 : Error\n
108 * b5 IP initilisation status\n
109 * 0 : Reset (IP not initialized)\n
110 * 1 : Init done (IP initialized and ready to use. HAL FMPI2C Init function called)\n
111 * b4 (not used)\n
112 * x : Should be set to 0\n
113 * b3\n
114 * 0 : Ready or Busy (No Listen mode ongoing)\n
115 * 1 : Listen (IP in Address Listen Mode)\n
116 * b2 Intrinsic process state\n
117 * 0 : Ready\n
118 * 1 : Busy (IP busy with some configuration or internal operations)\n
119 * b1 Rx state\n
120 * 0 : Ready (no Rx operation ongoing)\n
121 * 1 : Busy (Rx operation ongoing)\n
122 * b0 Tx state\n
123 * 0 : Ready (no Tx operation ongoing)\n
124 * 1 : Busy (Tx operation ongoing)
125 * @{
126 */
127 typedef enum
128 {
129 HAL_FMPI2C_STATE_RESET = 0x00U, /*!< Peripheral is not yet Initialized */
130 HAL_FMPI2C_STATE_READY = 0x20U, /*!< Peripheral Initialized and ready for use */
131 HAL_FMPI2C_STATE_BUSY = 0x24U, /*!< An internal process is ongoing */
132 HAL_FMPI2C_STATE_BUSY_TX = 0x21U, /*!< Data Transmission process is ongoing */
133 HAL_FMPI2C_STATE_BUSY_RX = 0x22U, /*!< Data Reception process is ongoing */
134 HAL_FMPI2C_STATE_LISTEN = 0x28U, /*!< Address Listen Mode is ongoing */
135 HAL_FMPI2C_STATE_BUSY_TX_LISTEN = 0x29U, /*!< Address Listen Mode and Data Transmission
136 process is ongoing */
137 HAL_FMPI2C_STATE_BUSY_RX_LISTEN = 0x2AU, /*!< Address Listen Mode and Data Reception
138 process is ongoing */
139 HAL_FMPI2C_STATE_ABORT = 0x60U, /*!< Abort user request ongoing */
140 HAL_FMPI2C_STATE_TIMEOUT = 0xA0U, /*!< Timeout state */
141 HAL_FMPI2C_STATE_ERROR = 0xE0U /*!< Error */
142
143 } HAL_FMPI2C_StateTypeDef;
144
145 /**
146 * @}
147 */
148
149 /** @defgroup HAL_mode_structure_definition HAL mode structure definition
150 * @brief HAL Mode structure definition
151 * @note HAL FMPI2C Mode value coding follow below described bitmap :\n
152 * b7 (not used)\n
153 * x : Should be set to 0\n
154 * b6\n
155 * 0 : None\n
156 * 1 : Memory (HAL FMPI2C communication is in Memory Mode)\n
157 * b5\n
158 * 0 : None\n
159 * 1 : Slave (HAL FMPI2C communication is in Slave Mode)\n
160 * b4\n
161 * 0 : None\n
162 * 1 : Master (HAL FMPI2C communication is in Master Mode)\n
163 * b3-b2-b1-b0 (not used)\n
164 * xxxx : Should be set to 0000
165 * @{
166 */
167 typedef enum
168 {
169 HAL_FMPI2C_MODE_NONE = 0x00U, /*!< No FMPI2C communication on going */
170 HAL_FMPI2C_MODE_MASTER = 0x10U, /*!< FMPI2C communication is in Master Mode */
171 HAL_FMPI2C_MODE_SLAVE = 0x20U, /*!< FMPI2C communication is in Slave Mode */
172 HAL_FMPI2C_MODE_MEM = 0x40U /*!< FMPI2C communication is in Memory Mode */
173
174 } HAL_FMPI2C_ModeTypeDef;
175
176 /**
177 * @}
178 */
179
180 /** @defgroup FMPI2C_Error_Code_definition FMPI2C Error Code definition
181 * @brief FMPI2C Error Code definition
182 * @{
183 */
184 #define HAL_FMPI2C_ERROR_NONE (0x00000000U) /*!< No error */
185 #define HAL_FMPI2C_ERROR_BERR (0x00000001U) /*!< BERR error */
186 #define HAL_FMPI2C_ERROR_ARLO (0x00000002U) /*!< ARLO error */
187 #define HAL_FMPI2C_ERROR_AF (0x00000004U) /*!< ACKF error */
188 #define HAL_FMPI2C_ERROR_OVR (0x00000008U) /*!< OVR error */
189 #define HAL_FMPI2C_ERROR_DMA (0x00000010U) /*!< DMA transfer error */
190 #define HAL_FMPI2C_ERROR_TIMEOUT (0x00000020U) /*!< Timeout error */
191 #define HAL_FMPI2C_ERROR_SIZE (0x00000040U) /*!< Size Management error */
192 /**
193 * @}
194 */
195
196 /** @defgroup FMPI2C_handle_Structure_definition FMPI2C handle Structure definition
197 * @brief FMPI2C handle Structure definition
198 * @{
199 */
200 typedef struct __FMPI2C_HandleTypeDef
201 {
202 FMPI2C_TypeDef *Instance; /*!< FMPI2C registers base address */
203
204 FMPI2C_InitTypeDef Init; /*!< FMPI2C communication parameters */
205
206 uint8_t *pBuffPtr; /*!< Pointer to FMPI2C transfer buffer */
207
208 uint16_t XferSize; /*!< FMPI2C transfer size */
209
210 __IO uint16_t XferCount; /*!< FMPI2C transfer counter */
211
212 __IO uint32_t XferOptions; /*!< FMPI2C sequantial transfer options, this parameter can
213 be a value of @ref FMPI2C_XFEROPTIONS */
214
215 __IO uint32_t PreviousState; /*!< FMPI2C communication Previous state */
216
217 HAL_StatusTypeDef(*XferISR)(struct __FMPI2C_HandleTypeDef *hfmpi2c, uint32_t ITFlags, uint32_t ITSources); /*!< FMPI2C transfer IRQ handler function pointer */
218
219 DMA_HandleTypeDef *hdmatx; /*!< FMPI2C Tx DMA handle parameters */
220
221 DMA_HandleTypeDef *hdmarx; /*!< FMPI2C Rx DMA handle parameters */
222
223 HAL_LockTypeDef Lock; /*!< FMPI2C locking object */
224
225 __IO HAL_FMPI2C_StateTypeDef State; /*!< FMPI2C communication state */
226
227 __IO HAL_FMPI2C_ModeTypeDef Mode; /*!< FMPI2C communication mode */
228
229 __IO uint32_t ErrorCode; /*!< FMPI2C Error code */
230
231 __IO uint32_t AddrEventCount; /*!< FMPI2C Address Event counter */
232 } FMPI2C_HandleTypeDef;
233 /**
234 * @}
235 */
236
237 /**
238 * @}
239 */
240 /* Exported constants --------------------------------------------------------*/
241
242 /** @defgroup FMPI2C_Exported_Constants FMPI2C Exported Constants
243 * @{
244 */
245
246 /** @defgroup FMPI2C_XFEROPTIONS FMPI2C Sequential Transfer Options
247 * @{
248 */
249 #define FMPI2C_FIRST_FRAME ((uint32_t)FMPI2C_SOFTEND_MODE)
250 #define FMPI2C_FIRST_AND_NEXT_FRAME ((uint32_t)(FMPI2C_RELOAD_MODE | FMPI2C_SOFTEND_MODE))
251 #define FMPI2C_NEXT_FRAME ((uint32_t)(FMPI2C_RELOAD_MODE | FMPI2C_SOFTEND_MODE))
252 #define FMPI2C_FIRST_AND_LAST_FRAME ((uint32_t)FMPI2C_AUTOEND_MODE)
253 #define FMPI2C_LAST_FRAME ((uint32_t)FMPI2C_AUTOEND_MODE)
254 #define FMPI2C_LAST_FRAME_NO_STOP ((uint32_t)FMPI2C_SOFTEND_MODE)
255 /**
256 * @}
257 */
258
259 /** @defgroup FMPI2C_ADDRESSING_MODE FMPI2C Addressing Mode
260 * @{
261 */
262 #define FMPI2C_ADDRESSINGMODE_7BIT (0x00000001U)
263 #define FMPI2C_ADDRESSINGMODE_10BIT (0x00000002U)
264 /**
265 * @}
266 */
267
268 /** @defgroup FMPI2C_DUAL_ADDRESSING_MODE FMPI2C Dual Addressing Mode
269 * @{
270 */
271 #define FMPI2C_DUALADDRESS_DISABLE (0x00000000U)
272 #define FMPI2C_DUALADDRESS_ENABLE FMPI2C_OAR2_OA2EN
273 /**
274 * @}
275 */
276
277 /** @defgroup FMPI2C_OWN_ADDRESS2_MASKS FMPI2C Own Address2 Masks
278 * @{
279 */
280 #define FMPI2C_OA2_NOMASK ((uint8_t)0x00)
281 #define FMPI2C_OA2_MASK01 ((uint8_t)0x01)
282 #define FMPI2C_OA2_MASK02 ((uint8_t)0x02)
283 #define FMPI2C_OA2_MASK03 ((uint8_t)0x03)
284 #define FMPI2C_OA2_MASK04 ((uint8_t)0x04)
285 #define FMPI2C_OA2_MASK05 ((uint8_t)0x05)
286 #define FMPI2C_OA2_MASK06 ((uint8_t)0x06)
287 #define FMPI2C_OA2_MASK07 ((uint8_t)0x07)
288 /**
289 * @}
290 */
291
292 /** @defgroup FMPI2C_GENERAL_CALL_ADDRESSING_MODE FMPI2C General Call Addressing Mode
293 * @{
294 */
295 #define FMPI2C_GENERALCALL_DISABLE (0x00000000U)
296 #define FMPI2C_GENERALCALL_ENABLE FMPI2C_CR1_GCEN
297 /**
298 * @}
299 */
300
301 /** @defgroup FMPI2C_NOSTRETCH_MODE FMPI2C No-Stretch Mode
302 * @{
303 */
304 #define FMPI2C_NOSTRETCH_DISABLE (0x00000000U)
305 #define FMPI2C_NOSTRETCH_ENABLE FMPI2C_CR1_NOSTRETCH
306 /**
307 * @}
308 */
309
310 /** @defgroup FMPI2C_MEMORY_ADDRESS_SIZE FMPI2C Memory Address Size
311 * @{
312 */
313 #define FMPI2C_MEMADD_SIZE_8BIT (0x00000001U)
314 #define FMPI2C_MEMADD_SIZE_16BIT (0x00000002U)
315 /**
316 * @}
317 */
318
319 /** @defgroup FMPI2C_XFERDIRECTION FMPI2C Transfer Direction Master Point of View
320 * @{
321 */
322 #define FMPI2C_DIRECTION_TRANSMIT (0x00000000U)
323 #define FMPI2C_DIRECTION_RECEIVE (0x00000001U)
324 /**
325 * @}
326 */
327
328 /** @defgroup FMPI2C_RELOAD_END_MODE FMPI2C Reload End Mode
329 * @{
330 */
331 #define FMPI2C_RELOAD_MODE FMPI2C_CR2_RELOAD
332 #define FMPI2C_AUTOEND_MODE FMPI2C_CR2_AUTOEND
333 #define FMPI2C_SOFTEND_MODE (0x00000000U)
334 /**
335 * @}
336 */
337
338 /** @defgroup FMPI2C_START_STOP_MODE FMPI2C Start or Stop Mode
339 * @{
340 */
341 #define FMPI2C_NO_STARTSTOP (0x00000000U)
342 #define FMPI2C_GENERATE_STOP (uint32_t)(0x80000000U | FMPI2C_CR2_STOP)
343 #define FMPI2C_GENERATE_START_READ (uint32_t)(0x80000000U | FMPI2C_CR2_START | FMPI2C_CR2_RD_WRN)
344 #define FMPI2C_GENERATE_START_WRITE (uint32_t)(0x80000000U | FMPI2C_CR2_START)
345 /**
346 * @}
347 */
348
349 /** @defgroup FMPI2C_Interrupt_configuration_definition FMPI2C Interrupt configuration definition
350 * @brief FMPI2C Interrupt definition
351 * Elements values convention: 0xXXXXXXXX
352 * - XXXXXXXX : Interrupt control mask
353 * @{
354 */
355 #define FMPI2C_IT_ERRI FMPI2C_CR1_ERRIE
356 #define FMPI2C_IT_TCI FMPI2C_CR1_TCIE
357 #define FMPI2C_IT_STOPI FMPI2C_CR1_STOPIE
358 #define FMPI2C_IT_NACKI FMPI2C_CR1_NACKIE
359 #define FMPI2C_IT_ADDRI FMPI2C_CR1_ADDRIE
360 #define FMPI2C_IT_RXI FMPI2C_CR1_RXIE
361 #define FMPI2C_IT_TXI FMPI2C_CR1_TXIE
362 /**
363 * @}
364 */
365
366 /** @defgroup FMPI2C_Flag_definition FMPI2C Flag definition
367 * @{
368 */
369 #define FMPI2C_FLAG_TXE FMPI2C_ISR_TXE
370 #define FMPI2C_FLAG_TXIS FMPI2C_ISR_TXIS
371 #define FMPI2C_FLAG_RXNE FMPI2C_ISR_RXNE
372 #define FMPI2C_FLAG_ADDR FMPI2C_ISR_ADDR
373 #define FMPI2C_FLAG_AF FMPI2C_ISR_NACKF
374 #define FMPI2C_FLAG_STOPF FMPI2C_ISR_STOPF
375 #define FMPI2C_FLAG_TC FMPI2C_ISR_TC
376 #define FMPI2C_FLAG_TCR FMPI2C_ISR_TCR
377 #define FMPI2C_FLAG_BERR FMPI2C_ISR_BERR
378 #define FMPI2C_FLAG_ARLO FMPI2C_ISR_ARLO
379 #define FMPI2C_FLAG_OVR FMPI2C_ISR_OVR
380 #define FMPI2C_FLAG_PECERR FMPI2C_ISR_PECERR
381 #define FMPI2C_FLAG_TIMEOUT FMPI2C_ISR_TIMEOUT
382 #define FMPI2C_FLAG_ALERT FMPI2C_ISR_ALERT
383 #define FMPI2C_FLAG_BUSY FMPI2C_ISR_BUSY
384 #define FMPI2C_FLAG_DIR FMPI2C_ISR_DIR
385 /**
386 * @}
387 */
388
389 /**
390 * @}
391 */
392
393 /* Exported macros -----------------------------------------------------------*/
394
395 /** @defgroup FMPI2C_Exported_Macros FMPI2C Exported Macros
396 * @{
397 */
398
399 /** @brief Reset FMPI2C handle state.
400 * @param __HANDLE__ specifies the FMPI2C Handle.
401 * @retval None
402 */
403 #define __HAL_FMPI2C_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_FMPI2C_STATE_RESET)
404
405 /** @brief Enable the specified FMPI2C interrupt.
406 * @param __HANDLE__ specifies the FMPI2C Handle.
407 * @param __INTERRUPT__ specifies the interrupt source to enable.
408 * This parameter can be one of the following values:
409 * @arg @ref FMPI2C_IT_ERRI Errors interrupt enable
410 * @arg @ref FMPI2C_IT_TCI Transfer complete interrupt enable
411 * @arg @ref FMPI2C_IT_STOPI STOP detection interrupt enable
412 * @arg @ref FMPI2C_IT_NACKI NACK received interrupt enable
413 * @arg @ref FMPI2C_IT_ADDRI Address match interrupt enable
414 * @arg @ref FMPI2C_IT_RXI RX interrupt enable
415 * @arg @ref FMPI2C_IT_TXI TX interrupt enable
416 *
417 * @retval None
418 */
419 #define __HAL_FMPI2C_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 |= (__INTERRUPT__))
420
421 /** @brief Disable the specified FMPI2C interrupt.
422 * @param __HANDLE__ specifies the FMPI2C Handle.
423 * @param __INTERRUPT__ specifies the interrupt source to disable.
424 * This parameter can be one of the following values:
425 * @arg @ref FMPI2C_IT_ERRI Errors interrupt enable
426 * @arg @ref FMPI2C_IT_TCI Transfer complete interrupt enable
427 * @arg @ref FMPI2C_IT_STOPI STOP detection interrupt enable
428 * @arg @ref FMPI2C_IT_NACKI NACK received interrupt enable
429 * @arg @ref FMPI2C_IT_ADDRI Address match interrupt enable
430 * @arg @ref FMPI2C_IT_RXI RX interrupt enable
431 * @arg @ref FMPI2C_IT_TXI TX interrupt enable
432 *
433 * @retval None
434 */
435 #define __HAL_FMPI2C_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 &= (~(__INTERRUPT__)))
436
437 /** @brief Check whether the specified FMPI2C interrupt source is enabled or not.
438 * @param __HANDLE__ specifies the FMPI2C Handle.
439 * @param __INTERRUPT__ specifies the FMPI2C interrupt source to check.
440 * This parameter can be one of the following values:
441 * @arg @ref FMPI2C_IT_ERRI Errors interrupt enable
442 * @arg @ref FMPI2C_IT_TCI Transfer complete interrupt enable
443 * @arg @ref FMPI2C_IT_STOPI STOP detection interrupt enable
444 * @arg @ref FMPI2C_IT_NACKI NACK received interrupt enable
445 * @arg @ref FMPI2C_IT_ADDRI Address match interrupt enable
446 * @arg @ref FMPI2C_IT_RXI RX interrupt enable
447 * @arg @ref FMPI2C_IT_TXI TX interrupt enable
448 *
449 * @retval The new state of __INTERRUPT__ (SET or RESET).
450 */
451 #define __HAL_FMPI2C_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
452
453 /** @brief Check whether the specified FMPI2C flag is set or not.
454 * @param __HANDLE__ specifies the FMPI2C Handle.
455 * @param __FLAG__ specifies the flag to check.
456 * This parameter can be one of the following values:
457 * @arg @ref FMPI2C_FLAG_TXE Transmit data register empty
458 * @arg @ref FMPI2C_FLAG_TXIS Transmit interrupt status
459 * @arg @ref FMPI2C_FLAG_RXNE Receive data register not empty
460 * @arg @ref FMPI2C_FLAG_ADDR Address matched (slave mode)
461 * @arg @ref FMPI2C_FLAG_AF Acknowledge failure received flag
462 * @arg @ref FMPI2C_FLAG_STOPF STOP detection flag
463 * @arg @ref FMPI2C_FLAG_TC Transfer complete (master mode)
464 * @arg @ref FMPI2C_FLAG_TCR Transfer complete reload
465 * @arg @ref FMPI2C_FLAG_BERR Bus error
466 * @arg @ref FMPI2C_FLAG_ARLO Arbitration lost
467 * @arg @ref FMPI2C_FLAG_OVR Overrun/Underrun
468 * @arg @ref FMPI2C_FLAG_PECERR PEC error in reception
469 * @arg @ref FMPI2C_FLAG_TIMEOUT Timeout or Tlow detection flag
470 * @arg @ref FMPI2C_FLAG_ALERT SMBus alert
471 * @arg @ref FMPI2C_FLAG_BUSY Bus busy
472 * @arg @ref FMPI2C_FLAG_DIR Transfer direction (slave mode)
473 *
474 * @retval The new state of __FLAG__ (SET or RESET).
475 */
476 #define __HAL_FMPI2C_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) == (__FLAG__)) ? SET : RESET)
477
478 /** @brief Clear the FMPI2C pending flags which are cleared by writing 1 in a specific bit.
479 * @param __HANDLE__ specifies the FMPI2C Handle.
480 * @param __FLAG__ specifies the flag to clear.
481 * This parameter can be any combination of the following values:
482 * @arg @ref FMPI2C_FLAG_TXE Transmit data register empty
483 * @arg @ref FMPI2C_FLAG_ADDR Address matched (slave mode)
484 * @arg @ref FMPI2C_FLAG_AF Acknowledge failure received flag
485 * @arg @ref FMPI2C_FLAG_STOPF STOP detection flag
486 * @arg @ref FMPI2C_FLAG_BERR Bus error
487 * @arg @ref FMPI2C_FLAG_ARLO Arbitration lost
488 * @arg @ref FMPI2C_FLAG_OVR Overrun/Underrun
489 * @arg @ref FMPI2C_FLAG_PECERR PEC error in reception
490 * @arg @ref FMPI2C_FLAG_TIMEOUT Timeout or Tlow detection flag
491 * @arg @ref FMPI2C_FLAG_ALERT SMBus alert
492 *
493 * @retval None
494 */
495 #define __HAL_FMPI2C_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__FLAG__) == FMPI2C_FLAG_TXE) ? ((__HANDLE__)->Instance->ISR |= (__FLAG__)) \
496 : ((__HANDLE__)->Instance->ICR = (__FLAG__)))
497
498 /** @brief Enable the specified FMPI2C peripheral.
499 * @param __HANDLE__ specifies the FMPI2C Handle.
500 * @retval None
501 */
502 #define __HAL_FMPI2C_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR1, FMPI2C_CR1_PE))
503
504 /** @brief Disable the specified FMPI2C peripheral.
505 * @param __HANDLE__ specifies the FMPI2C Handle.
506 * @retval None
507 */
508 #define __HAL_FMPI2C_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CR1, FMPI2C_CR1_PE))
509
510 /** @brief Generate a Non-Acknowledge FMPI2C peripheral in Slave mode.
511 * @param __HANDLE__ specifies the FMPI2C Handle.
512 * @retval None
513 */
514 #define __HAL_FMPI2C_GENERATE_NACK(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR2, FMPI2C_CR2_NACK))
515 /**
516 * @}
517 */
518
519 /* Include FMPI2C HAL Extended module */
520 #include "stm32f4xx_hal_fmpi2c_ex.h"
521
522 /* Exported functions --------------------------------------------------------*/
523 /** @addtogroup FMPI2C_Exported_Functions
524 * @{
525 */
526
527 /** @addtogroup FMPI2C_Exported_Functions_Group1 Initialization and de-initialization functions
528 * @{
529 */
530 /* Initialization and de-initialization functions******************************/
531 HAL_StatusTypeDef HAL_FMPI2C_Init(FMPI2C_HandleTypeDef *hfmpi2c);
532 HAL_StatusTypeDef HAL_FMPI2C_DeInit(FMPI2C_HandleTypeDef *hfmpi2c);
533 void HAL_FMPI2C_MspInit(FMPI2C_HandleTypeDef *hfmpi2c);
534 void HAL_FMPI2C_MspDeInit(FMPI2C_HandleTypeDef *hfmpi2c);
535 /**
536 * @}
537 */
538
539 /** @addtogroup FMPI2C_Exported_Functions_Group2 Input and Output operation functions
540 * @{
541 */
542 /* IO operation functions ****************************************************/
543 /******* Blocking mode: Polling */
544 HAL_StatusTypeDef HAL_FMPI2C_Master_Transmit(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout);
545 HAL_StatusTypeDef HAL_FMPI2C_Master_Receive(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout);
546 HAL_StatusTypeDef HAL_FMPI2C_Slave_Transmit(FMPI2C_HandleTypeDef *hfmpi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout);
547 HAL_StatusTypeDef HAL_FMPI2C_Slave_Receive(FMPI2C_HandleTypeDef *hfmpi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout);
548 HAL_StatusTypeDef HAL_FMPI2C_Mem_Write(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout);
549 HAL_StatusTypeDef HAL_FMPI2C_Mem_Read(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout);
550 HAL_StatusTypeDef HAL_FMPI2C_IsDeviceReady(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout);
551
552 /******* Non-Blocking mode: Interrupt */
553 HAL_StatusTypeDef HAL_FMPI2C_Master_Transmit_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);
554 HAL_StatusTypeDef HAL_FMPI2C_Master_Receive_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);
555 HAL_StatusTypeDef HAL_FMPI2C_Slave_Transmit_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint8_t *pData, uint16_t Size);
556 HAL_StatusTypeDef HAL_FMPI2C_Slave_Receive_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint8_t *pData, uint16_t Size);
557 HAL_StatusTypeDef HAL_FMPI2C_Mem_Write_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
558 HAL_StatusTypeDef HAL_FMPI2C_Mem_Read_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
559
560 HAL_StatusTypeDef HAL_FMPI2C_Master_Sequential_Transmit_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
561 HAL_StatusTypeDef HAL_FMPI2C_Master_Sequential_Receive_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
562 HAL_StatusTypeDef HAL_FMPI2C_Slave_Sequential_Transmit_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
563 HAL_StatusTypeDef HAL_FMPI2C_Slave_Sequential_Receive_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
564 HAL_StatusTypeDef HAL_FMPI2C_EnableListen_IT(FMPI2C_HandleTypeDef *hfmpi2c);
565 HAL_StatusTypeDef HAL_FMPI2C_DisableListen_IT(FMPI2C_HandleTypeDef *hfmpi2c);
566 HAL_StatusTypeDef HAL_FMPI2C_Master_Abort_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress);
567
568 /******* Non-Blocking mode: DMA */
569 HAL_StatusTypeDef HAL_FMPI2C_Master_Transmit_DMA(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);
570 HAL_StatusTypeDef HAL_FMPI2C_Master_Receive_DMA(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);
571 HAL_StatusTypeDef HAL_FMPI2C_Slave_Transmit_DMA(FMPI2C_HandleTypeDef *hfmpi2c, uint8_t *pData, uint16_t Size);
572 HAL_StatusTypeDef HAL_FMPI2C_Slave_Receive_DMA(FMPI2C_HandleTypeDef *hfmpi2c, uint8_t *pData, uint16_t Size);
573 HAL_StatusTypeDef HAL_FMPI2C_Mem_Write_DMA(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
574 HAL_StatusTypeDef HAL_FMPI2C_Mem_Read_DMA(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
575 /**
576 * @}
577 */
578
579 /** @addtogroup FMPI2C_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks
580 * @{
581 */
582 /******* FMPI2C IRQHandler and Callbacks used in non blocking modes (Interrupt and DMA) */
583 void HAL_FMPI2C_EV_IRQHandler(FMPI2C_HandleTypeDef *hfmpi2c);
584 void HAL_FMPI2C_ER_IRQHandler(FMPI2C_HandleTypeDef *hfmpi2c);
585 void HAL_FMPI2C_MasterTxCpltCallback(FMPI2C_HandleTypeDef *hfmpi2c);
586 void HAL_FMPI2C_MasterRxCpltCallback(FMPI2C_HandleTypeDef *hfmpi2c);
587 void HAL_FMPI2C_SlaveTxCpltCallback(FMPI2C_HandleTypeDef *hfmpi2c);
588 void HAL_FMPI2C_SlaveRxCpltCallback(FMPI2C_HandleTypeDef *hfmpi2c);
589 void HAL_FMPI2C_AddrCallback(FMPI2C_HandleTypeDef *hfmpi2c, uint8_t TransferDirection, uint16_t AddrMatchCode);
590 void HAL_FMPI2C_ListenCpltCallback(FMPI2C_HandleTypeDef *hfmpi2c);
591 void HAL_FMPI2C_MemTxCpltCallback(FMPI2C_HandleTypeDef *hfmpi2c);
592 void HAL_FMPI2C_MemRxCpltCallback(FMPI2C_HandleTypeDef *hfmpi2c);
593 void HAL_FMPI2C_ErrorCallback(FMPI2C_HandleTypeDef *hfmpi2c);
594 void HAL_FMPI2C_AbortCpltCallback(FMPI2C_HandleTypeDef *hfmpi2c);
595 /**
596 * @}
597 */
598
599 /** @addtogroup FMPI2C_Exported_Functions_Group3 Peripheral State, Mode and Error functions
600 * @{
601 */
602 /* Peripheral State, Mode and Error functions *********************************/
603 HAL_FMPI2C_StateTypeDef HAL_FMPI2C_GetState(FMPI2C_HandleTypeDef *hfmpi2c);
604 HAL_FMPI2C_ModeTypeDef HAL_FMPI2C_GetMode(FMPI2C_HandleTypeDef *hfmpi2c);
605 uint32_t HAL_FMPI2C_GetError(FMPI2C_HandleTypeDef *hfmpi2c);
606
607 /**
608 * @}
609 */
610
611 /**
612 * @}
613 */
614
615 /* Private constants ---------------------------------------------------------*/
616 /** @defgroup FMPI2C_Private_Constants FMPI2C Private Constants
617 * @{
618 */
619
620 /**
621 * @}
622 */
623
624 /* Private macros ------------------------------------------------------------*/
625 /** @defgroup FMPI2C_Private_Macro FMPI2C Private Macros
626 * @{
627 */
628
629 #define IS_FMPI2C_ADDRESSING_MODE(MODE) (((MODE) == FMPI2C_ADDRESSINGMODE_7BIT) || \
630 ((MODE) == FMPI2C_ADDRESSINGMODE_10BIT))
631
632 #define IS_FMPI2C_DUAL_ADDRESS(ADDRESS) (((ADDRESS) == FMPI2C_DUALADDRESS_DISABLE) || \
633 ((ADDRESS) == FMPI2C_DUALADDRESS_ENABLE))
634
635 #define IS_FMPI2C_OWN_ADDRESS2_MASK(MASK) (((MASK) == FMPI2C_OA2_NOMASK) || \
636 ((MASK) == FMPI2C_OA2_MASK01) || \
637 ((MASK) == FMPI2C_OA2_MASK02) || \
638 ((MASK) == FMPI2C_OA2_MASK03) || \
639 ((MASK) == FMPI2C_OA2_MASK04) || \
640 ((MASK) == FMPI2C_OA2_MASK05) || \
641 ((MASK) == FMPI2C_OA2_MASK06) || \
642 ((MASK) == FMPI2C_OA2_MASK07))
643
644 #define IS_FMPI2C_GENERAL_CALL(CALL) (((CALL) == FMPI2C_GENERALCALL_DISABLE) || \
645 ((CALL) == FMPI2C_GENERALCALL_ENABLE))
646
647 #define IS_FMPI2C_NO_STRETCH(STRETCH) (((STRETCH) == FMPI2C_NOSTRETCH_DISABLE) || \
648 ((STRETCH) == FMPI2C_NOSTRETCH_ENABLE))
649
650 #define IS_FMPI2C_MEMADD_SIZE(SIZE) (((SIZE) == FMPI2C_MEMADD_SIZE_8BIT) || \
651 ((SIZE) == FMPI2C_MEMADD_SIZE_16BIT))
652
653 #define IS_TRANSFER_MODE(MODE) (((MODE) == FMPI2C_RELOAD_MODE) || \
654 ((MODE) == FMPI2C_AUTOEND_MODE) || \
655 ((MODE) == FMPI2C_SOFTEND_MODE))
656
657 #define IS_TRANSFER_REQUEST(REQUEST) (((REQUEST) == FMPI2C_GENERATE_STOP) || \
658 ((REQUEST) == FMPI2C_GENERATE_START_READ) || \
659 ((REQUEST) == FMPI2C_GENERATE_START_WRITE) || \
660 ((REQUEST) == FMPI2C_NO_STARTSTOP))
661
662 #define IS_FMPI2C_TRANSFER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == FMPI2C_FIRST_FRAME) || \
663 ((REQUEST) == FMPI2C_FIRST_AND_NEXT_FRAME) || \
664 ((REQUEST) == FMPI2C_NEXT_FRAME) || \
665 ((REQUEST) == FMPI2C_FIRST_AND_LAST_FRAME) || \
666 ((REQUEST) == FMPI2C_LAST_FRAME) || \
667 ((REQUEST) == FMPI2C_LAST_FRAME_NO_STOP))
668
669 #define FMPI2C_RESET_CR2(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= (uint32_t)~((uint32_t)(FMPI2C_CR2_SADD | FMPI2C_CR2_HEAD10R | FMPI2C_CR2_NBYTES | FMPI2C_CR2_RELOAD | FMPI2C_CR2_RD_WRN)))
670
671 #define FMPI2C_GET_ADDR_MATCH(__HANDLE__) (((__HANDLE__)->Instance->ISR & FMPI2C_ISR_ADDCODE) >> 16)
672 #define FMPI2C_GET_DIR(__HANDLE__) (((__HANDLE__)->Instance->ISR & FMPI2C_ISR_DIR) >> 16)
673 #define FMPI2C_GET_STOP_MODE(__HANDLE__) ((__HANDLE__)->Instance->CR2 & FMPI2C_CR2_AUTOEND)
674 #define FMPI2C_GET_OWN_ADDRESS1(__HANDLE__) ((__HANDLE__)->Instance->OAR1 & FMPI2C_OAR1_OA1)
675 #define FMPI2C_GET_OWN_ADDRESS2(__HANDLE__) ((__HANDLE__)->Instance->OAR2 & FMPI2C_OAR2_OA2)
676
677 #define IS_FMPI2C_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= 0x000003FFU)
678 #define IS_FMPI2C_OWN_ADDRESS2(ADDRESS2) ((ADDRESS2) <= (uint16_t)0x00FF)
679
680 #define FMPI2C_MEM_ADD_MSB(__ADDRESS__) ((uint8_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0xFF00))) >> 8U)))
681 #define FMPI2C_MEM_ADD_LSB(__ADDRESS__) ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FF))))
682
683 #define FMPI2C_GENERATE_START(__ADDMODE__,__ADDRESS__) (((__ADDMODE__) == FMPI2C_ADDRESSINGMODE_7BIT) ? (uint32_t)((((uint32_t)(__ADDRESS__) & (FMPI2C_CR2_SADD)) | (FMPI2C_CR2_START) | (FMPI2C_CR2_AUTOEND)) & (~FMPI2C_CR2_RD_WRN)) : \
684 (uint32_t)((((uint32_t)(__ADDRESS__) & (FMPI2C_CR2_SADD)) | (FMPI2C_CR2_ADD10) | (FMPI2C_CR2_START)) & (~FMPI2C_CR2_RD_WRN)))
685 /**
686 * @}
687 */
688
689 /* Private Functions ---------------------------------------------------------*/
690 /** @defgroup FMPI2C_Private_Functions FMPI2C Private Functions
691 * @{
692 */
693 /* Private functions are defined in stm32f4xx_hal_fmpi2c.c file */
694 /**
695 * @}
696 */
697
698 /**
699 * @}
700 */
701
702 /**
703 * @}
704 */
705 #endif /* STM32F410xx || STM32F446xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */
706 #ifdef __cplusplus
707 }
708 #endif
709
710
711 #endif /* __STM32F4xx_HAL_FMPI2C_H */
712
713 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/