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comparison Common/Drivers/STM32F4xx/Source/Templates/gcc/startup_stm32f413xx.s @ 160:e3ca52b8e7fa

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author heinrichsweikamp
date Thu, 07 Mar 2019 15:06:43 +0100
parents c78bcbd5deda
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80:cc2bb7bb8456 160:e3ca52b8e7fa
1 /**
2 ******************************************************************************
3 * @file startup_stm32f413xx.s
4 * @author MCD Application Team
5 * @brief STM32F413xx Devices vector table for GCC based toolchains.
6 * This module performs:
7 * - Set the initial SP
8 * - Set the initial PC == Reset_Handler,
9 * - Set the vector table entries with the exceptions ISR address
10 * - Branches to main in the C library (which eventually
11 * calls main()).
12 * After Reset the Cortex-M4 processor is in Thread mode,
13 * priority is Privileged, and the Stack is set to Main.
14 ******************************************************************************
15 * @attention
16 *
17 * <h2><center>&copy; COPYRIGHT 2017 STMicroelectronics</center></h2>
18 *
19 * Redistribution and use in source and binary forms, with or without modification,
20 * are permitted provided that the following conditions are met:
21 * 1. Redistributions of source code must retain the above copyright notice,
22 * this list of conditions and the following disclaimer.
23 * 2. Redistributions in binary form must reproduce the above copyright notice,
24 * this list of conditions and the following disclaimer in the documentation
25 * and/or other materials provided with the distribution.
26 * 3. Neither the name of STMicroelectronics nor the names of its contributors
27 * may be used to endorse or promote products derived from this software
28 * without specific prior written permission.
29 *
30 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
31 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
32 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
33 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
34 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
35 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
36 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
37 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
38 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 *
41 ******************************************************************************
42 */
43
44 .syntax unified
45 .cpu cortex-m4
46 .fpu softvfp
47 .thumb
48
49 .global g_pfnVectors
50 .global Default_Handler
51
52 /* start address for the initialization values of the .data section.
53 defined in linker script */
54 .word _sidata
55 /* start address for the .data section. defined in linker script */
56 .word _sdata
57 /* end address for the .data section. defined in linker script */
58 .word _edata
59 /* start address for the .bss section. defined in linker script */
60 .word _sbss
61 /* end address for the .bss section. defined in linker script */
62 .word _ebss
63 /* stack used for SystemInit_ExtMemCtl; always internal RAM used */
64
65 /**
66 * @brief This is the code that gets called when the processor first
67 * starts execution following a reset event. Only the absolutely
68 * necessary set is performed, after which the application
69 * supplied main() routine is called.
70 * @param None
71 * @retval : None
72 */
73
74 .section .text.Reset_Handler
75 .weak Reset_Handler
76 .type Reset_Handler, %function
77 Reset_Handler:
78 ldr sp, =_estack /* set stack pointer */
79
80 /* Copy the data segment initializers from flash to SRAM */
81 movs r1, #0
82 b LoopCopyDataInit
83
84 CopyDataInit:
85 ldr r3, =_sidata
86 ldr r3, [r3, r1]
87 str r3, [r0, r1]
88 adds r1, r1, #4
89
90 LoopCopyDataInit:
91 ldr r0, =_sdata
92 ldr r3, =_edata
93 adds r2, r0, r1
94 cmp r2, r3
95 bcc CopyDataInit
96 ldr r2, =_sbss
97 b LoopFillZerobss
98 /* Zero fill the bss segment. */
99 FillZerobss:
100 movs r3, #0
101 str r3, [r2], #4
102
103 LoopFillZerobss:
104 ldr r3, = _ebss
105 cmp r2, r3
106 bcc FillZerobss
107
108 /* Call the clock system intitialization function.*/
109 bl SystemInit
110 /* Call static constructors */
111 bl __libc_init_array
112 /* Call the application's entry point.*/
113 bl main
114 bx lr
115 .size Reset_Handler, .-Reset_Handler
116
117 /**
118 * @brief This is the code that gets called when the processor receives an
119 * unexpected interrupt. This simply enters an infinite loop, preserving
120 * the system state for examination by a debugger.
121 * @param None
122 * @retval None
123 */
124 .section .text.Default_Handler,"ax",%progbits
125 Default_Handler:
126 Infinite_Loop:
127 b Infinite_Loop
128 .size Default_Handler, .-Default_Handler
129 /******************************************************************************
130 *
131 * The minimal vector table for a Cortex M3. Note that the proper constructs
132 * must be placed on this to ensure that it ends up at physical address
133 * 0x0000.0000.
134 *
135 *******************************************************************************/
136 .section .isr_vector,"a",%progbits
137 .type g_pfnVectors, %object
138 .size g_pfnVectors, .-g_pfnVectors
139
140 g_pfnVectors:
141 .word _estack
142 .word Reset_Handler
143 .word NMI_Handler
144 .word HardFault_Handler
145 .word MemManage_Handler
146 .word BusFault_Handler
147 .word UsageFault_Handler
148 .word 0
149 .word 0
150 .word 0
151 .word 0
152 .word SVC_Handler
153 .word DebugMon_Handler
154 .word 0
155 .word PendSV_Handler
156 .word SysTick_Handler
157
158 /* External Interrupts */
159 .word WWDG_IRQHandler /* Window WatchDog */
160 .word PVD_IRQHandler /* PVD through EXTI Line detection */
161 .word TAMP_STAMP_IRQHandler /* Tamper and TimeStamps through the EXTI line */
162 .word RTC_WKUP_IRQHandler /* RTC Wakeup through the EXTI line */
163 .word FLASH_IRQHandler /* FLASH */
164 .word RCC_IRQHandler /* RCC */
165 .word EXTI0_IRQHandler /* EXTI Line0 */
166 .word EXTI1_IRQHandler /* EXTI Line1 */
167 .word EXTI2_IRQHandler /* EXTI Line2 */
168 .word EXTI3_IRQHandler /* EXTI Line3 */
169 .word EXTI4_IRQHandler /* EXTI Line4 */
170 .word DMA1_Stream0_IRQHandler /* DMA1 Stream 0 */
171 .word DMA1_Stream1_IRQHandler /* DMA1 Stream 1 */
172 .word DMA1_Stream2_IRQHandler /* DMA1 Stream 2 */
173 .word DMA1_Stream3_IRQHandler /* DMA1 Stream 3 */
174 .word DMA1_Stream4_IRQHandler /* DMA1 Stream 4 */
175 .word DMA1_Stream5_IRQHandler /* DMA1 Stream 5 */
176 .word DMA1_Stream6_IRQHandler /* DMA1 Stream 6 */
177 .word ADC_IRQHandler /* ADC1, ADC2 and ADC3s */
178 .word CAN1_TX_IRQHandler /* CAN1 TX */
179 .word CAN1_RX0_IRQHandler /* CAN1 RX0 */
180 .word CAN1_RX1_IRQHandler /* CAN1 RX1 */
181 .word CAN1_SCE_IRQHandler /* CAN1 SCE */
182 .word EXTI9_5_IRQHandler /* External Line[9:5]s */
183 .word TIM1_BRK_TIM9_IRQHandler /* TIM1 Break and TIM9 */
184 .word TIM1_UP_TIM10_IRQHandler /* TIM1 Update and TIM10 */
185 .word TIM1_TRG_COM_TIM11_IRQHandler /* TIM1 Trigger and Commutation and TIM11 */
186 .word TIM1_CC_IRQHandler /* TIM1 Capture Compare */
187 .word TIM2_IRQHandler /* TIM2 */
188 .word TIM3_IRQHandler /* TIM3 */
189 .word TIM4_IRQHandler /* TIM4 */
190 .word I2C1_EV_IRQHandler /* I2C1 Event */
191 .word I2C1_ER_IRQHandler /* I2C1 Error */
192 .word I2C2_EV_IRQHandler /* I2C2 Event */
193 .word I2C2_ER_IRQHandler /* I2C2 Error */
194 .word SPI1_IRQHandler /* SPI1 */
195 .word SPI2_IRQHandler /* SPI2 */
196 .word USART1_IRQHandler /* USART1 */
197 .word USART2_IRQHandler /* USART2 */
198 .word USART3_IRQHandler /* USART3 */
199 .word EXTI15_10_IRQHandler /* External Line[15:10]s */
200 .word RTC_Alarm_IRQHandler /* RTC Alarm (A and B) through EXTI Line */
201 .word OTG_FS_WKUP_IRQHandler /* USB OTG FS Wakeup through EXTI line */
202 .word TIM8_BRK_TIM12_IRQHandler /* TIM8 Break and TIM12 */
203 .word TIM8_UP_TIM13_IRQHandler /* TIM8 Update and TIM13 */
204 .word TIM8_TRG_COM_TIM14_IRQHandler /* TIM8 Trigger and Commutation and TIM14 */
205 .word TIM8_CC_IRQHandler /* TIM8 Capture Compare */
206 .word DMA1_Stream7_IRQHandler /* DMA1 Stream7 */
207 .word FSMC_IRQHandler /* FSMC */
208 .word SDIO_IRQHandler /* SDIO */
209 .word TIM5_IRQHandler /* TIM5 */
210 .word SPI3_IRQHandler /* SPI3 */
211 .word UART4_IRQHandler /* UART4 */
212 .word UART5_IRQHandler /* UART5 */
213 .word TIM6_DAC_IRQHandler /* TIM6, DAC1 and DAC2 */
214 .word TIM7_IRQHandler /* TIM7 */
215 .word DMA2_Stream0_IRQHandler /* DMA2 Stream 0 */
216 .word DMA2_Stream1_IRQHandler /* DMA2 Stream 1 */
217 .word DMA2_Stream2_IRQHandler /* DMA2 Stream 2 */
218 .word DMA2_Stream3_IRQHandler /* DMA2 Stream 3 */
219 .word DMA2_Stream4_IRQHandler /* DMA2 Stream 4 */
220 .word DFSDM1_FLT0_IRQHandler /* DFSDM1 Filter0 */
221 .word DFSDM1_FLT1_IRQHandler /* DFSDM1 Filter1 */
222 .word CAN2_TX_IRQHandler /* CAN2 TX */
223 .word CAN2_RX0_IRQHandler /* CAN2 RX0 */
224 .word CAN2_RX1_IRQHandler /* CAN2 RX1 */
225 .word CAN2_SCE_IRQHandler /* CAN2 SCE */
226 .word OTG_FS_IRQHandler /* USB OTG FS */
227 .word DMA2_Stream5_IRQHandler /* DMA2 Stream 5 */
228 .word DMA2_Stream6_IRQHandler /* DMA2 Stream 6 */
229 .word DMA2_Stream7_IRQHandler /* DMA2 Stream 7 */
230 .word USART6_IRQHandler /* USART6 */
231 .word I2C3_EV_IRQHandler /* I2C3 event */
232 .word I2C3_ER_IRQHandler /* I2C3 error */
233 .word CAN3_TX_IRQHandler /* CAN3 TX */
234 .word CAN3_RX0_IRQHandler /* CAN3 RX0 */
235 .word CAN3_RX1_IRQHandler /* CAN3 RX1 */
236 .word CAN3_SCE_IRQHandler /* CAN3 SCE */
237 .word 0 /* Reserved */
238 .word 0 /* Reserved */
239 .word RNG_IRQHandler /* RNG */
240 .word FPU_IRQHandler /* FPU */
241 .word UART7_IRQHandler /* UART7 */
242 .word UART8_IRQHandler /* UART8 */
243 .word SPI4_IRQHandler /* SPI4 */
244 .word SPI5_IRQHandler /* SPI5 */
245 .word 0 /* Reserved */
246 .word SAI1_IRQHandler /* SAI1 */
247 .word UART9_IRQHandler /* UART9 */
248 .word UART10_IRQHandler /* UART10 */
249 .word 0 /* Reserved */
250 .word 0 /* Reserved */
251 .word QUADSPI_IRQHandler /* QuadSPI */
252 .word 0 /* Reserved */
253 .word 0 /* Reserved */
254 .word FMPI2C1_EV_IRQHandler /* FMPI2C1 Event */
255 .word FMPI2C1_ER_IRQHandler /* FMPI2C1 Error */
256 .word LPTIM1_IRQHandler /* LPTIM1 */
257 .word DFSDM2_FLT0_IRQHandler /* DFSDM2 Filter0 */
258 .word DFSDM2_FLT1_IRQHandler /* DFSDM2 Filter1 */
259 .word DFSDM2_FLT2_IRQHandler /* DFSDM2 Filter2 */
260 .word DFSDM2_FLT3_IRQHandler /* DFSDM2 Filter3 */
261
262 /*******************************************************************************
263 *
264 * Provide weak aliases for each Exception handler to the Default_Handler.
265 * As they are weak aliases, any function with the same name will override
266 * this definition.
267 *
268 *******************************************************************************/
269 .weak NMI_Handler
270 .thumb_set NMI_Handler,Default_Handler
271
272 .weak HardFault_Handler
273 .thumb_set HardFault_Handler,Default_Handler
274
275 .weak MemManage_Handler
276 .thumb_set MemManage_Handler,Default_Handler
277
278 .weak BusFault_Handler
279 .thumb_set BusFault_Handler,Default_Handler
280
281 .weak UsageFault_Handler
282 .thumb_set UsageFault_Handler,Default_Handler
283
284 .weak SVC_Handler
285 .thumb_set SVC_Handler,Default_Handler
286
287 .weak DebugMon_Handler
288 .thumb_set DebugMon_Handler,Default_Handler
289
290 .weak PendSV_Handler
291 .thumb_set PendSV_Handler,Default_Handler
292
293 .weak SysTick_Handler
294 .thumb_set SysTick_Handler,Default_Handler
295
296 .weak WWDG_IRQHandler
297 .thumb_set WWDG_IRQHandler,Default_Handler
298
299 .weak PVD_IRQHandler
300 .thumb_set PVD_IRQHandler,Default_Handler
301
302 .weak TAMP_STAMP_IRQHandler
303 .thumb_set TAMP_STAMP_IRQHandler,Default_Handler
304
305 .weak RTC_WKUP_IRQHandler
306 .thumb_set RTC_WKUP_IRQHandler,Default_Handler
307
308 .weak FLASH_IRQHandler
309 .thumb_set FLASH_IRQHandler,Default_Handler
310
311 .weak RCC_IRQHandler
312 .thumb_set RCC_IRQHandler,Default_Handler
313
314 .weak EXTI0_IRQHandler
315 .thumb_set EXTI0_IRQHandler,Default_Handler
316
317 .weak EXTI1_IRQHandler
318 .thumb_set EXTI1_IRQHandler,Default_Handler
319
320 .weak EXTI2_IRQHandler
321 .thumb_set EXTI2_IRQHandler,Default_Handler
322
323 .weak EXTI3_IRQHandler
324 .thumb_set EXTI3_IRQHandler,Default_Handler
325
326 .weak EXTI4_IRQHandler
327 .thumb_set EXTI4_IRQHandler,Default_Handler
328
329 .weak DMA1_Stream0_IRQHandler
330 .thumb_set DMA1_Stream0_IRQHandler,Default_Handler
331
332 .weak DMA1_Stream1_IRQHandler
333 .thumb_set DMA1_Stream1_IRQHandler,Default_Handler
334
335 .weak DMA1_Stream2_IRQHandler
336 .thumb_set DMA1_Stream2_IRQHandler,Default_Handler
337
338 .weak DMA1_Stream3_IRQHandler
339 .thumb_set DMA1_Stream3_IRQHandler,Default_Handler
340
341 .weak DMA1_Stream4_IRQHandler
342 .thumb_set DMA1_Stream4_IRQHandler,Default_Handler
343
344 .weak DMA1_Stream5_IRQHandler
345 .thumb_set DMA1_Stream5_IRQHandler,Default_Handler
346
347 .weak DMA1_Stream6_IRQHandler
348 .thumb_set DMA1_Stream6_IRQHandler,Default_Handler
349
350 .weak ADC_IRQHandler
351 .thumb_set ADC_IRQHandler,Default_Handler
352
353 .weak CAN1_TX_IRQHandler
354 .thumb_set CAN1_TX_IRQHandler,Default_Handler
355
356 .weak CAN1_RX0_IRQHandler
357 .thumb_set CAN1_RX0_IRQHandler,Default_Handler
358
359 .weak CAN1_RX1_IRQHandler
360 .thumb_set CAN1_RX1_IRQHandler,Default_Handler
361
362 .weak CAN1_SCE_IRQHandler
363 .thumb_set CAN1_SCE_IRQHandler,Default_Handler
364
365 .weak EXTI9_5_IRQHandler
366 .thumb_set EXTI9_5_IRQHandler,Default_Handler
367
368 .weak TIM1_BRK_TIM9_IRQHandler
369 .thumb_set TIM1_BRK_TIM9_IRQHandler,Default_Handler
370
371 .weak TIM1_UP_TIM10_IRQHandler
372 .thumb_set TIM1_UP_TIM10_IRQHandler,Default_Handler
373
374 .weak TIM1_TRG_COM_TIM11_IRQHandler
375 .thumb_set TIM1_TRG_COM_TIM11_IRQHandler,Default_Handler
376
377 .weak TIM1_CC_IRQHandler
378 .thumb_set TIM1_CC_IRQHandler,Default_Handler
379
380 .weak TIM2_IRQHandler
381 .thumb_set TIM2_IRQHandler,Default_Handler
382
383 .weak TIM3_IRQHandler
384 .thumb_set TIM3_IRQHandler,Default_Handler
385
386 .weak TIM4_IRQHandler
387 .thumb_set TIM4_IRQHandler,Default_Handler
388
389 .weak I2C1_EV_IRQHandler
390 .thumb_set I2C1_EV_IRQHandler,Default_Handler
391
392 .weak I2C1_ER_IRQHandler
393 .thumb_set I2C1_ER_IRQHandler,Default_Handler
394
395 .weak I2C2_EV_IRQHandler
396 .thumb_set I2C2_EV_IRQHandler,Default_Handler
397
398 .weak I2C2_ER_IRQHandler
399 .thumb_set I2C2_ER_IRQHandler,Default_Handler
400
401 .weak SPI1_IRQHandler
402 .thumb_set SPI1_IRQHandler,Default_Handler
403
404 .weak SPI2_IRQHandler
405 .thumb_set SPI2_IRQHandler,Default_Handler
406
407 .weak USART1_IRQHandler
408 .thumb_set USART1_IRQHandler,Default_Handler
409
410 .weak USART2_IRQHandler
411 .thumb_set USART2_IRQHandler,Default_Handler
412
413 .weak USART3_IRQHandler
414 .thumb_set USART3_IRQHandler,Default_Handler
415
416 .weak EXTI15_10_IRQHandler
417 .thumb_set EXTI15_10_IRQHandler,Default_Handler
418
419 .weak RTC_Alarm_IRQHandler
420 .thumb_set RTC_Alarm_IRQHandler,Default_Handler
421
422 .weak OTG_FS_WKUP_IRQHandler
423 .thumb_set OTG_FS_WKUP_IRQHandler,Default_Handler
424
425 .weak TIM8_BRK_TIM12_IRQHandler
426 .thumb_set TIM8_BRK_TIM12_IRQHandler,Default_Handler
427
428 .weak TIM8_UP_TIM13_IRQHandler
429 .thumb_set TIM8_UP_TIM13_IRQHandler,Default_Handler
430
431 .weak TIM8_TRG_COM_TIM14_IRQHandler
432 .thumb_set TIM8_TRG_COM_TIM14_IRQHandler,Default_Handler
433
434 .weak TIM8_CC_IRQHandler
435 .thumb_set TIM8_CC_IRQHandler,Default_Handler
436
437 .weak DMA1_Stream7_IRQHandler
438 .thumb_set DMA1_Stream7_IRQHandler,Default_Handler
439
440 .weak FSMC_IRQHandler
441 .thumb_set FSMC_IRQHandler,Default_Handler
442
443 .weak SDIO_IRQHandler
444 .thumb_set SDIO_IRQHandler,Default_Handler
445
446 .weak TIM5_IRQHandler
447 .thumb_set TIM5_IRQHandler,Default_Handler
448
449 .weak SPI3_IRQHandler
450 .thumb_set SPI3_IRQHandler,Default_Handler
451
452 .weak UART4_IRQHandler
453 .thumb_set UART4_IRQHandler,Default_Handler
454
455 .weak UART5_IRQHandler
456 .thumb_set UART5_IRQHandler,Default_Handler
457
458 .weak TIM6_DAC_IRQHandler
459 .thumb_set TIM6_DAC_IRQHandler,Default_Handler
460
461 .weak TIM7_IRQHandler
462 .thumb_set TIM7_IRQHandler,Default_Handler
463
464 .weak DMA2_Stream0_IRQHandler
465 .thumb_set DMA2_Stream0_IRQHandler,Default_Handler
466
467 .weak DMA2_Stream1_IRQHandler
468 .thumb_set DMA2_Stream1_IRQHandler,Default_Handler
469
470 .weak DMA2_Stream2_IRQHandler
471 .thumb_set DMA2_Stream2_IRQHandler,Default_Handler
472
473 .weak DMA2_Stream3_IRQHandler
474 .thumb_set DMA2_Stream3_IRQHandler,Default_Handler
475
476 .weak DMA2_Stream4_IRQHandler
477 .thumb_set DMA2_Stream4_IRQHandler,Default_Handler
478
479 .weak DFSDM1_FLT0_IRQHandler
480 .thumb_set DFSDM1_FLT0_IRQHandler,Default_Handler
481
482 .weak DFSDM1_FLT1_IRQHandler
483 .thumb_set DFSDM1_FLT1_IRQHandler,Default_Handler
484
485 .weak CAN2_TX_IRQHandler
486 .thumb_set CAN2_TX_IRQHandler,Default_Handler
487
488 .weak CAN2_RX0_IRQHandler
489 .thumb_set CAN2_RX0_IRQHandler,Default_Handler
490
491 .weak CAN2_RX1_IRQHandler
492 .thumb_set CAN2_RX1_IRQHandler,Default_Handler
493
494 .weak CAN2_SCE_IRQHandler
495 .thumb_set CAN2_SCE_IRQHandler,Default_Handler
496
497 .weak OTG_FS_IRQHandler
498 .thumb_set OTG_FS_IRQHandler,Default_Handler
499
500 .weak DMA2_Stream5_IRQHandler
501 .thumb_set DMA2_Stream5_IRQHandler,Default_Handler
502
503 .weak DMA2_Stream6_IRQHandler
504 .thumb_set DMA2_Stream6_IRQHandler,Default_Handler
505
506 .weak DMA2_Stream7_IRQHandler
507 .thumb_set DMA2_Stream7_IRQHandler,Default_Handler
508
509 .weak USART6_IRQHandler
510 .thumb_set USART6_IRQHandler,Default_Handler
511
512 .weak I2C3_EV_IRQHandler
513 .thumb_set I2C3_EV_IRQHandler,Default_Handler
514
515 .weak I2C3_ER_IRQHandler
516 .thumb_set I2C3_ER_IRQHandler,Default_Handler
517
518 .weak CAN3_TX_IRQHandler
519 .thumb_set CAN3_TX_IRQHandler,Default_Handler
520
521 .weak CAN3_RX0_IRQHandler
522 .thumb_set CAN3_RX0_IRQHandler,Default_Handler
523
524 .weak CAN3_RX1_IRQHandler
525 .thumb_set CAN3_RX1_IRQHandler,Default_Handler
526
527 .weak CAN3_SCE_IRQHandler
528 .thumb_set CAN3_SCE_IRQHandler,Default_Handler
529
530 .weak RNG_IRQHandler
531 .thumb_set RNG_IRQHandler,Default_Handler
532
533 .weak FPU_IRQHandler
534 .thumb_set FPU_IRQHandler,Default_Handler
535
536 .weak UART7_IRQHandler
537 .thumb_set UART7_IRQHandler,Default_Handler
538
539 .weak UART8_IRQHandler
540 .thumb_set UART8_IRQHandler,Default_Handler
541
542 .weak SPI4_IRQHandler
543 .thumb_set SPI4_IRQHandler,Default_Handler
544
545 .weak SPI5_IRQHandler
546 .thumb_set SPI5_IRQHandler,Default_Handler
547
548 .weak SAI1_IRQHandler
549 .thumb_set SAI1_IRQHandler,Default_Handler
550
551 .weak UART9_IRQHandler
552 .thumb_set UART9_IRQHandler,Default_Handler
553
554 .weak UART10_IRQHandler
555 .thumb_set UART10_IRQHandler,Default_Handler
556
557 .weak QUADSPI_IRQHandler
558 .thumb_set QUADSPI_IRQHandler,Default_Handler
559
560 .weak FMPI2C1_EV_IRQHandler
561 .thumb_set FMPI2C1_EV_IRQHandler,Default_Handler
562
563 .weak FMPI2C1_ER_IRQHandler
564 .thumb_set FMPI2C1_ER_IRQHandler,Default_Handler
565
566 .weak LPTIM1_IRQHandler
567 .thumb_set LPTIM1_IRQHandler,Default_Handler
568
569 .weak DFSDM2_FLT0_IRQHandler
570 .thumb_set DFSDM2_FLT0_IRQHandler,Default_Handler
571
572 .weak DFSDM2_FLT1_IRQHandler
573 .thumb_set DFSDM2_FLT1_IRQHandler,Default_Handler
574
575 .weak DFSDM2_FLT2_IRQHandler
576 .thumb_set DFSDM2_FLT2_IRQHandler,Default_Handler
577
578 .weak DFSDM2_FLT3_IRQHandler
579 .thumb_set DFSDM2_FLT3_IRQHandler,Default_Handler
580 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/