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comparison Common/Drivers/STM32F4xx/Source/Templates/gcc/startup_stm32f411xe.s @ 160:e3ca52b8e7fa

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author heinrichsweikamp
date Thu, 07 Mar 2019 15:06:43 +0100
parents c78bcbd5deda
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80:cc2bb7bb8456 160:e3ca52b8e7fa
1 /**
2 ******************************************************************************
3 * @file startup_stm32f411xe.s
4 * @author MCD Application Team
5 * @brief STM32F411xExx Devices vector table for GCC based toolchains.
6 * This module performs:
7 * - Set the initial SP
8 * - Set the initial PC == Reset_Handler,
9 * - Set the vector table entries with the exceptions ISR address
10 * - Branches to main in the C library (which eventually
11 * calls main()).
12 * After Reset the Cortex-M4 processor is in Thread mode,
13 * priority is Privileged, and the Stack is set to Main.
14 ******************************************************************************
15 * @attention
16 *
17 * <h2><center>&copy; COPYRIGHT 2017 STMicroelectronics</center></h2>
18 *
19 * Redistribution and use in source and binary forms, with or without modification,
20 * are permitted provided that the following conditions are met:
21 * 1. Redistributions of source code must retain the above copyright notice,
22 * this list of conditions and the following disclaimer.
23 * 2. Redistributions in binary form must reproduce the above copyright notice,
24 * this list of conditions and the following disclaimer in the documentation
25 * and/or other materials provided with the distribution.
26 * 3. Neither the name of STMicroelectronics nor the names of its contributors
27 * may be used to endorse or promote products derived from this software
28 * without specific prior written permission.
29 *
30 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
31 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
32 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
33 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
34 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
35 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
36 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
37 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
38 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 *
41 ******************************************************************************
42 */
43
44 .syntax unified
45 .cpu cortex-m4
46 .fpu softvfp
47 .thumb
48
49 .global g_pfnVectors
50 .global Default_Handler
51
52 /* start address for the initialization values of the .data section.
53 defined in linker script */
54 .word _sidata
55 /* start address for the .data section. defined in linker script */
56 .word _sdata
57 /* end address for the .data section. defined in linker script */
58 .word _edata
59 /* start address for the .bss section. defined in linker script */
60 .word _sbss
61 /* end address for the .bss section. defined in linker script */
62 .word _ebss
63 /* stack used for SystemInit_ExtMemCtl; always internal RAM used */
64
65 /**
66 * @brief This is the code that gets called when the processor first
67 * starts execution following a reset event. Only the absolutely
68 * necessary set is performed, after which the application
69 * supplied main() routine is called.
70 * @param None
71 * @retval : None
72 */
73
74 .section .text.Reset_Handler
75 .weak Reset_Handler
76 .type Reset_Handler, %function
77 Reset_Handler:
78 ldr sp, =_estack /* set stack pointer */
79
80 /* Copy the data segment initializers from flash to SRAM */
81 movs r1, #0
82 b LoopCopyDataInit
83
84 CopyDataInit:
85 ldr r3, =_sidata
86 ldr r3, [r3, r1]
87 str r3, [r0, r1]
88 adds r1, r1, #4
89
90 LoopCopyDataInit:
91 ldr r0, =_sdata
92 ldr r3, =_edata
93 adds r2, r0, r1
94 cmp r2, r3
95 bcc CopyDataInit
96 ldr r2, =_sbss
97 b LoopFillZerobss
98 /* Zero fill the bss segment. */
99 FillZerobss:
100 movs r3, #0
101 str r3, [r2], #4
102
103 LoopFillZerobss:
104 ldr r3, = _ebss
105 cmp r2, r3
106 bcc FillZerobss
107
108 /* Call the clock system intitialization function.*/
109 bl SystemInit
110 /* Call static constructors */
111 bl __libc_init_array
112 /* Call the application's entry point.*/
113 bl main
114 bx lr
115 .size Reset_Handler, .-Reset_Handler
116
117 /**
118 * @brief This is the code that gets called when the processor receives an
119 * unexpected interrupt. This simply enters an infinite loop, preserving
120 * the system state for examination by a debugger.
121 * @param None
122 * @retval None
123 */
124 .section .text.Default_Handler,"ax",%progbits
125 Default_Handler:
126 Infinite_Loop:
127 b Infinite_Loop
128 .size Default_Handler, .-Default_Handler
129 /******************************************************************************
130 *
131 * The minimal vector table for a Cortex M3. Note that the proper constructs
132 * must be placed on this to ensure that it ends up at physical address
133 * 0x0000.0000.
134 *
135 *******************************************************************************/
136 .section .isr_vector,"a",%progbits
137 .type g_pfnVectors, %object
138 .size g_pfnVectors, .-g_pfnVectors
139
140 g_pfnVectors:
141 .word _estack
142 .word Reset_Handler
143 .word NMI_Handler
144 .word HardFault_Handler
145 .word MemManage_Handler
146 .word BusFault_Handler
147 .word UsageFault_Handler
148 .word 0
149 .word 0
150 .word 0
151 .word 0
152 .word SVC_Handler
153 .word DebugMon_Handler
154 .word 0
155 .word PendSV_Handler
156 .word SysTick_Handler
157
158 /* External Interrupts */
159 .word WWDG_IRQHandler /* Window WatchDog */
160 .word PVD_IRQHandler /* PVD through EXTI Line detection */
161 .word TAMP_STAMP_IRQHandler /* Tamper and TimeStamps through the EXTI line */
162 .word RTC_WKUP_IRQHandler /* RTC Wakeup through the EXTI line */
163 .word FLASH_IRQHandler /* FLASH */
164 .word RCC_IRQHandler /* RCC */
165 .word EXTI0_IRQHandler /* EXTI Line0 */
166 .word EXTI1_IRQHandler /* EXTI Line1 */
167 .word EXTI2_IRQHandler /* EXTI Line2 */
168 .word EXTI3_IRQHandler /* EXTI Line3 */
169 .word EXTI4_IRQHandler /* EXTI Line4 */
170 .word DMA1_Stream0_IRQHandler /* DMA1 Stream 0 */
171 .word DMA1_Stream1_IRQHandler /* DMA1 Stream 1 */
172 .word DMA1_Stream2_IRQHandler /* DMA1 Stream 2 */
173 .word DMA1_Stream3_IRQHandler /* DMA1 Stream 3 */
174 .word DMA1_Stream4_IRQHandler /* DMA1 Stream 4 */
175 .word DMA1_Stream5_IRQHandler /* DMA1 Stream 5 */
176 .word DMA1_Stream6_IRQHandler /* DMA1 Stream 6 */
177 .word ADC_IRQHandler /* ADC1, ADC2 and ADC3s */
178 .word 0 /* Reserved */
179 .word 0 /* Reserved */
180 .word 0 /* Reserved */
181 .word 0 /* Reserved */
182 .word EXTI9_5_IRQHandler /* External Line[9:5]s */
183 .word TIM1_BRK_TIM9_IRQHandler /* TIM1 Break and TIM9 */
184 .word TIM1_UP_TIM10_IRQHandler /* TIM1 Update and TIM10 */
185 .word TIM1_TRG_COM_TIM11_IRQHandler /* TIM1 Trigger and Commutation and TIM11 */
186 .word TIM1_CC_IRQHandler /* TIM1 Capture Compare */
187 .word TIM2_IRQHandler /* TIM2 */
188 .word TIM3_IRQHandler /* TIM3 */
189 .word TIM4_IRQHandler /* TIM4 */
190 .word I2C1_EV_IRQHandler /* I2C1 Event */
191 .word I2C1_ER_IRQHandler /* I2C1 Error */
192 .word I2C2_EV_IRQHandler /* I2C2 Event */
193 .word I2C2_ER_IRQHandler /* I2C2 Error */
194 .word SPI1_IRQHandler /* SPI1 */
195 .word SPI2_IRQHandler /* SPI2 */
196 .word USART1_IRQHandler /* USART1 */
197 .word USART2_IRQHandler /* USART2 */
198 .word 0 /* Reserved */
199 .word EXTI15_10_IRQHandler /* External Line[15:10]s */
200 .word RTC_Alarm_IRQHandler /* RTC Alarm (A and B) through EXTI Line */
201 .word OTG_FS_WKUP_IRQHandler /* USB OTG FS Wakeup through EXTI line */
202 .word 0 /* Reserved */
203 .word 0 /* Reserved */
204 .word 0 /* Reserved */
205 .word 0 /* Reserved */
206 .word DMA1_Stream7_IRQHandler /* DMA1 Stream7 */
207 .word 0 /* Reserved */
208 .word SDIO_IRQHandler /* SDIO */
209 .word TIM5_IRQHandler /* TIM5 */
210 .word SPI3_IRQHandler /* SPI3 */
211 .word 0 /* Reserved */
212 .word 0 /* Reserved */
213 .word 0 /* Reserved */
214 .word 0 /* Reserved */
215 .word DMA2_Stream0_IRQHandler /* DMA2 Stream 0 */
216 .word DMA2_Stream1_IRQHandler /* DMA2 Stream 1 */
217 .word DMA2_Stream2_IRQHandler /* DMA2 Stream 2 */
218 .word DMA2_Stream3_IRQHandler /* DMA2 Stream 3 */
219 .word DMA2_Stream4_IRQHandler /* DMA2 Stream 4 */
220 .word 0 /* Reserved */
221 .word 0 /* Reserved */
222 .word 0 /* Reserved */
223 .word 0 /* Reserved */
224 .word 0 /* Reserved */
225 .word 0 /* Reserved */
226 .word OTG_FS_IRQHandler /* USB OTG FS */
227 .word DMA2_Stream5_IRQHandler /* DMA2 Stream 5 */
228 .word DMA2_Stream6_IRQHandler /* DMA2 Stream 6 */
229 .word DMA2_Stream7_IRQHandler /* DMA2 Stream 7 */
230 .word USART6_IRQHandler /* USART6 */
231 .word I2C3_EV_IRQHandler /* I2C3 event */
232 .word I2C3_ER_IRQHandler /* I2C3 error */
233 .word 0 /* Reserved */
234 .word 0 /* Reserved */
235 .word 0 /* Reserved */
236 .word 0 /* Reserved */
237 .word 0 /* Reserved */
238 .word 0 /* Reserved */
239 .word 0 /* Reserved */
240 .word FPU_IRQHandler /* FPU */
241 .word 0 /* Reserved */
242 .word 0 /* Reserved */
243 .word SPI4_IRQHandler /* SPI4 */
244 .word SPI5_IRQHandler /* SPI5 */
245
246 /*******************************************************************************
247 *
248 * Provide weak aliases for each Exception handler to the Default_Handler.
249 * As they are weak aliases, any function with the same name will override
250 * this definition.
251 *
252 *******************************************************************************/
253 .weak NMI_Handler
254 .thumb_set NMI_Handler,Default_Handler
255
256 .weak HardFault_Handler
257 .thumb_set HardFault_Handler,Default_Handler
258
259 .weak MemManage_Handler
260 .thumb_set MemManage_Handler,Default_Handler
261
262 .weak BusFault_Handler
263 .thumb_set BusFault_Handler,Default_Handler
264
265 .weak UsageFault_Handler
266 .thumb_set UsageFault_Handler,Default_Handler
267
268 .weak SVC_Handler
269 .thumb_set SVC_Handler,Default_Handler
270
271 .weak DebugMon_Handler
272 .thumb_set DebugMon_Handler,Default_Handler
273
274 .weak PendSV_Handler
275 .thumb_set PendSV_Handler,Default_Handler
276
277 .weak SysTick_Handler
278 .thumb_set SysTick_Handler,Default_Handler
279
280 .weak WWDG_IRQHandler
281 .thumb_set WWDG_IRQHandler,Default_Handler
282
283 .weak PVD_IRQHandler
284 .thumb_set PVD_IRQHandler,Default_Handler
285
286 .weak TAMP_STAMP_IRQHandler
287 .thumb_set TAMP_STAMP_IRQHandler,Default_Handler
288
289 .weak RTC_WKUP_IRQHandler
290 .thumb_set RTC_WKUP_IRQHandler,Default_Handler
291
292 .weak FLASH_IRQHandler
293 .thumb_set FLASH_IRQHandler,Default_Handler
294
295 .weak RCC_IRQHandler
296 .thumb_set RCC_IRQHandler,Default_Handler
297
298 .weak EXTI0_IRQHandler
299 .thumb_set EXTI0_IRQHandler,Default_Handler
300
301 .weak EXTI1_IRQHandler
302 .thumb_set EXTI1_IRQHandler,Default_Handler
303
304 .weak EXTI2_IRQHandler
305 .thumb_set EXTI2_IRQHandler,Default_Handler
306
307 .weak EXTI3_IRQHandler
308 .thumb_set EXTI3_IRQHandler,Default_Handler
309
310 .weak EXTI4_IRQHandler
311 .thumb_set EXTI4_IRQHandler,Default_Handler
312
313 .weak DMA1_Stream0_IRQHandler
314 .thumb_set DMA1_Stream0_IRQHandler,Default_Handler
315
316 .weak DMA1_Stream1_IRQHandler
317 .thumb_set DMA1_Stream1_IRQHandler,Default_Handler
318
319 .weak DMA1_Stream2_IRQHandler
320 .thumb_set DMA1_Stream2_IRQHandler,Default_Handler
321
322 .weak DMA1_Stream3_IRQHandler
323 .thumb_set DMA1_Stream3_IRQHandler,Default_Handler
324
325 .weak DMA1_Stream4_IRQHandler
326 .thumb_set DMA1_Stream4_IRQHandler,Default_Handler
327
328 .weak DMA1_Stream5_IRQHandler
329 .thumb_set DMA1_Stream5_IRQHandler,Default_Handler
330
331 .weak DMA1_Stream6_IRQHandler
332 .thumb_set DMA1_Stream6_IRQHandler,Default_Handler
333
334 .weak ADC_IRQHandler
335 .thumb_set ADC_IRQHandler,Default_Handler
336
337 .weak EXTI9_5_IRQHandler
338 .thumb_set EXTI9_5_IRQHandler,Default_Handler
339
340 .weak TIM1_BRK_TIM9_IRQHandler
341 .thumb_set TIM1_BRK_TIM9_IRQHandler,Default_Handler
342
343 .weak TIM1_UP_TIM10_IRQHandler
344 .thumb_set TIM1_UP_TIM10_IRQHandler,Default_Handler
345
346 .weak TIM1_TRG_COM_TIM11_IRQHandler
347 .thumb_set TIM1_TRG_COM_TIM11_IRQHandler,Default_Handler
348
349 .weak TIM1_CC_IRQHandler
350 .thumb_set TIM1_CC_IRQHandler,Default_Handler
351
352 .weak TIM2_IRQHandler
353 .thumb_set TIM2_IRQHandler,Default_Handler
354
355 .weak TIM3_IRQHandler
356 .thumb_set TIM3_IRQHandler,Default_Handler
357
358 .weak TIM4_IRQHandler
359 .thumb_set TIM4_IRQHandler,Default_Handler
360
361 .weak I2C1_EV_IRQHandler
362 .thumb_set I2C1_EV_IRQHandler,Default_Handler
363
364 .weak I2C1_ER_IRQHandler
365 .thumb_set I2C1_ER_IRQHandler,Default_Handler
366
367 .weak I2C2_EV_IRQHandler
368 .thumb_set I2C2_EV_IRQHandler,Default_Handler
369
370 .weak I2C2_ER_IRQHandler
371 .thumb_set I2C2_ER_IRQHandler,Default_Handler
372
373 .weak SPI1_IRQHandler
374 .thumb_set SPI1_IRQHandler,Default_Handler
375
376 .weak SPI2_IRQHandler
377 .thumb_set SPI2_IRQHandler,Default_Handler
378
379 .weak USART1_IRQHandler
380 .thumb_set USART1_IRQHandler,Default_Handler
381
382 .weak USART2_IRQHandler
383 .thumb_set USART2_IRQHandler,Default_Handler
384
385 .weak EXTI15_10_IRQHandler
386 .thumb_set EXTI15_10_IRQHandler,Default_Handler
387
388 .weak RTC_Alarm_IRQHandler
389 .thumb_set RTC_Alarm_IRQHandler,Default_Handler
390
391 .weak OTG_FS_WKUP_IRQHandler
392 .thumb_set OTG_FS_WKUP_IRQHandler,Default_Handler
393
394 .weak DMA1_Stream7_IRQHandler
395 .thumb_set DMA1_Stream7_IRQHandler,Default_Handler
396
397 .weak SDIO_IRQHandler
398 .thumb_set SDIO_IRQHandler,Default_Handler
399
400 .weak TIM5_IRQHandler
401 .thumb_set TIM5_IRQHandler,Default_Handler
402
403 .weak SPI3_IRQHandler
404 .thumb_set SPI3_IRQHandler,Default_Handler
405
406 .weak DMA2_Stream0_IRQHandler
407 .thumb_set DMA2_Stream0_IRQHandler,Default_Handler
408
409 .weak DMA2_Stream1_IRQHandler
410 .thumb_set DMA2_Stream1_IRQHandler,Default_Handler
411
412 .weak DMA2_Stream2_IRQHandler
413 .thumb_set DMA2_Stream2_IRQHandler,Default_Handler
414
415 .weak DMA2_Stream3_IRQHandler
416 .thumb_set DMA2_Stream3_IRQHandler,Default_Handler
417
418 .weak DMA2_Stream4_IRQHandler
419 .thumb_set DMA2_Stream4_IRQHandler,Default_Handler
420
421 .weak OTG_FS_IRQHandler
422 .thumb_set OTG_FS_IRQHandler,Default_Handler
423
424 .weak DMA2_Stream5_IRQHandler
425 .thumb_set DMA2_Stream5_IRQHandler,Default_Handler
426
427 .weak DMA2_Stream6_IRQHandler
428 .thumb_set DMA2_Stream6_IRQHandler,Default_Handler
429
430 .weak DMA2_Stream7_IRQHandler
431 .thumb_set DMA2_Stream7_IRQHandler,Default_Handler
432
433 .weak USART6_IRQHandler
434 .thumb_set USART6_IRQHandler,Default_Handler
435
436 .weak I2C3_EV_IRQHandler
437 .thumb_set I2C3_EV_IRQHandler,Default_Handler
438
439 .weak I2C3_ER_IRQHandler
440 .thumb_set I2C3_ER_IRQHandler,Default_Handler
441
442 .weak FPU_IRQHandler
443 .thumb_set FPU_IRQHandler,Default_Handler
444
445 .weak SPI4_IRQHandler
446 .thumb_set SPI4_IRQHandler,Default_Handler
447
448 .weak SPI5_IRQHandler
449 .thumb_set SPI5_IRQHandler,Default_Handler
450
451 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
452