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comparison Common/Drivers/STM32F4xx/Source/Templates/arm/startup_stm32f410cx.s @ 160:e3ca52b8e7fa

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author heinrichsweikamp
date Thu, 07 Mar 2019 15:06:43 +0100
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1 ;******************** (C) COPYRIGHT 2017 STMicroelectronics ********************
2 ;* File Name : startup_stm32f410cx.s
3 ;* Author : MCD Application Team
4 ;* Description : STM32F410Cx devices vector table for MDK-ARM toolchain.
5 ;* This module performs:
6 ;* - Set the initial SP
7 ;* - Set the initial PC == Reset_Handler
8 ;* - Set the vector table entries with the exceptions ISR address
9 ;* - Branches to __main in the C library (which eventually
10 ;* calls main()).
11 ;* After Reset the CortexM4 processor is in Thread mode,
12 ;* priority is Privileged, and the Stack is set to Main.
13 ;* <<< Use Configuration Wizard in Context Menu >>>
14 ;*******************************************************************************
15 ;
16 ;* Redistribution and use in source and binary forms, with or without modification,
17 ;* are permitted provided that the following conditions are met:
18 ;* 1. Redistributions of source code must retain the above copyright notice,
19 ;* this list of conditions and the following disclaimer.
20 ;* 2. Redistributions in binary form must reproduce the above copyright notice,
21 ;* this list of conditions and the following disclaimer in the documentation
22 ;* and/or other materials provided with the distribution.
23 ;* 3. Neither the name of STMicroelectronics nor the names of its contributors
24 ;* may be used to endorse or promote products derived from this software
25 ;* without specific prior written permission.
26 ;*
27 ;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
28 ;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
29 ;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
30 ;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
31 ;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
32 ;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
33 ;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
34 ;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
35 ;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
36 ;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
37 ;
38 ;*******************************************************************************
39
40 ; Amount of memory (in bytes) allocated for Stack
41 ; Tailor this value to your application needs
42 ; <h> Stack Configuration
43 ; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
44 ; </h>
45
46 Stack_Size EQU 0x00000400
47
48 AREA STACK, NOINIT, READWRITE, ALIGN=3
49 Stack_Mem SPACE Stack_Size
50 __initial_sp
51
52
53 ; <h> Heap Configuration
54 ; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
55 ; </h>
56
57 Heap_Size EQU 0x00000200
58
59 AREA HEAP, NOINIT, READWRITE, ALIGN=3
60 __heap_base
61 Heap_Mem SPACE Heap_Size
62 __heap_limit
63
64 PRESERVE8
65 THUMB
66
67
68 ; Vector Table Mapped to Address 0 at Reset
69 AREA RESET, DATA, READONLY
70 EXPORT __Vectors
71 EXPORT __Vectors_End
72 EXPORT __Vectors_Size
73
74 __Vectors DCD __initial_sp ; Top of Stack
75 DCD Reset_Handler ; Reset Handler
76 DCD NMI_Handler ; NMI Handler
77 DCD HardFault_Handler ; Hard Fault Handler
78 DCD MemManage_Handler ; MPU Fault Handler
79 DCD BusFault_Handler ; Bus Fault Handler
80 DCD UsageFault_Handler ; Usage Fault Handler
81 DCD 0 ; Reserved
82 DCD 0 ; Reserved
83 DCD 0 ; Reserved
84 DCD 0 ; Reserved
85 DCD SVC_Handler ; SVCall Handler
86 DCD DebugMon_Handler ; Debug Monitor Handler
87 DCD 0 ; Reserved
88 DCD PendSV_Handler ; PendSV Handler
89 DCD SysTick_Handler ; SysTick Handler
90
91 ; External Interrupts
92 DCD WWDG_IRQHandler ; Window WatchDog
93 DCD PVD_IRQHandler ; PVD through EXTI Line detection
94 DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line
95 DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line
96 DCD FLASH_IRQHandler ; FLASH
97 DCD RCC_IRQHandler ; RCC
98 DCD EXTI0_IRQHandler ; EXTI Line0
99 DCD EXTI1_IRQHandler ; EXTI Line1
100 DCD EXTI2_IRQHandler ; EXTI Line2
101 DCD EXTI3_IRQHandler ; EXTI Line3
102 DCD EXTI4_IRQHandler ; EXTI Line4
103 DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0
104 DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1
105 DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2
106 DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3
107 DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4
108 DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5
109 DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6
110 DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s
111 DCD 0 ; Reserved
112 DCD 0 ; Reserved
113 DCD 0 ; Reserved
114 DCD 0 ; Reserved
115 DCD EXTI9_5_IRQHandler ; External Line[9:5]s
116 DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9
117 DCD TIM1_UP_IRQHandler ; TIM1 Update
118 DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11
119 DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
120 DCD 0 ; Reserved
121 DCD 0 ; Reserved
122 DCD 0 ; Reserved
123 DCD I2C1_EV_IRQHandler ; I2C1 Event
124 DCD I2C1_ER_IRQHandler ; I2C1 Error
125 DCD I2C2_EV_IRQHandler ; I2C2 Event
126 DCD I2C2_ER_IRQHandler ; I2C2 Error
127 DCD SPI1_IRQHandler ; SPI1
128 DCD SPI2_IRQHandler ; SPI2
129 DCD USART1_IRQHandler ; USART1
130 DCD USART2_IRQHandler ; USART2
131 DCD 0 ; Reserved
132 DCD EXTI15_10_IRQHandler ; External Line[15:10]s
133 DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line
134 DCD 0 ; Reserved
135 DCD 0 ; Reserved
136 DCD 0 ; Reserved
137 DCD 0 ; Reserved
138 DCD 0 ; Reserved
139 DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7
140 DCD 0 ; Reserved
141 DCD 0 ; Reserved
142 DCD TIM5_IRQHandler ; TIM5
143 DCD 0 ; Reserved
144 DCD 0 ; Reserved
145 DCD 0 ; Reserved
146 DCD TIM6_DAC_IRQHandler ; TIM6 and DAC
147 DCD 0 ; Reserved
148 DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0
149 DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1
150 DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2
151 DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3
152 DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4
153 DCD 0 ; Reserved
154 DCD 0 ; Reserved
155 DCD 0 ; Reserved
156 DCD 0 ; Reserved
157 DCD 0 ; Reserved
158 DCD 0 ; Reserved
159 DCD 0 ; Reserved
160 DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5
161 DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6
162 DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7
163 DCD USART6_IRQHandler ; USART6
164 DCD 0 ; Reserved
165 DCD 0 ; Reserved
166 DCD 0 ; Reserved
167 DCD 0 ; Reserved
168 DCD 0 ; Reserved
169 DCD 0 ; Reserved
170 DCD 0 ; Reserved
171 DCD 0 ; Reserved
172 DCD RNG_IRQHandler ; RNG
173 DCD FPU_IRQHandler ; FPU
174 DCD 0 ; Reserved
175 DCD 0 ; Reserved
176 DCD 0 ; Reserved
177 DCD SPI5_IRQHandler ; SPI5
178 DCD 0 ; Reserved
179 DCD 0 ; Reserved
180 DCD 0 ; Reserved
181 DCD 0 ; Reserved
182 DCD 0 ; Reserved
183 DCD 0 ; Reserved
184 DCD 0 ; Reserved
185 DCD 0 ; Reserved
186 DCD 0 ; Reserved
187 DCD FMPI2C1_EV_IRQHandler ; FMPI2C1 Event
188 DCD FMPI2C1_ER_IRQHandler ; FMPI2C1 Error
189 DCD LPTIM1_IRQHandler ; LP TIM1
190
191 __Vectors_End
192
193 __Vectors_Size EQU __Vectors_End - __Vectors
194
195 AREA |.text|, CODE, READONLY
196
197 ; Reset handler
198 Reset_Handler PROC
199 EXPORT Reset_Handler [WEAK]
200 IMPORT SystemInit
201 IMPORT __main
202
203 LDR R0, =SystemInit
204 BLX R0
205 LDR R0, =__main
206 BX R0
207 ENDP
208
209 ; Dummy Exception Handlers (infinite loops which can be modified)
210
211 NMI_Handler PROC
212 EXPORT NMI_Handler [WEAK]
213 B .
214 ENDP
215 HardFault_Handler\
216 PROC
217 EXPORT HardFault_Handler [WEAK]
218 B .
219 ENDP
220 MemManage_Handler\
221 PROC
222 EXPORT MemManage_Handler [WEAK]
223 B .
224 ENDP
225 BusFault_Handler\
226 PROC
227 EXPORT BusFault_Handler [WEAK]
228 B .
229 ENDP
230 UsageFault_Handler\
231 PROC
232 EXPORT UsageFault_Handler [WEAK]
233 B .
234 ENDP
235 SVC_Handler PROC
236 EXPORT SVC_Handler [WEAK]
237 B .
238 ENDP
239 DebugMon_Handler\
240 PROC
241 EXPORT DebugMon_Handler [WEAK]
242 B .
243 ENDP
244 PendSV_Handler PROC
245 EXPORT PendSV_Handler [WEAK]
246 B .
247 ENDP
248 SysTick_Handler PROC
249 EXPORT SysTick_Handler [WEAK]
250 B .
251 ENDP
252
253 Default_Handler PROC
254
255 EXPORT WWDG_IRQHandler [WEAK]
256 EXPORT PVD_IRQHandler [WEAK]
257 EXPORT TAMP_STAMP_IRQHandler [WEAK]
258 EXPORT RTC_WKUP_IRQHandler [WEAK]
259 EXPORT FLASH_IRQHandler [WEAK]
260 EXPORT RCC_IRQHandler [WEAK]
261 EXPORT EXTI0_IRQHandler [WEAK]
262 EXPORT EXTI1_IRQHandler [WEAK]
263 EXPORT EXTI2_IRQHandler [WEAK]
264 EXPORT EXTI3_IRQHandler [WEAK]
265 EXPORT EXTI4_IRQHandler [WEAK]
266 EXPORT DMA1_Stream0_IRQHandler [WEAK]
267 EXPORT DMA1_Stream1_IRQHandler [WEAK]
268 EXPORT DMA1_Stream2_IRQHandler [WEAK]
269 EXPORT DMA1_Stream3_IRQHandler [WEAK]
270 EXPORT DMA1_Stream4_IRQHandler [WEAK]
271 EXPORT DMA1_Stream5_IRQHandler [WEAK]
272 EXPORT DMA1_Stream6_IRQHandler [WEAK]
273 EXPORT ADC_IRQHandler [WEAK]
274 EXPORT EXTI9_5_IRQHandler [WEAK]
275 EXPORT TIM1_BRK_TIM9_IRQHandler [WEAK]
276 EXPORT TIM1_UP_IRQHandler [WEAK]
277 EXPORT TIM1_TRG_COM_TIM11_IRQHandler [WEAK]
278 EXPORT TIM1_CC_IRQHandler [WEAK]
279 EXPORT I2C1_EV_IRQHandler [WEAK]
280 EXPORT I2C1_ER_IRQHandler [WEAK]
281 EXPORT I2C2_EV_IRQHandler [WEAK]
282 EXPORT I2C2_ER_IRQHandler [WEAK]
283 EXPORT SPI1_IRQHandler [WEAK]
284 EXPORT SPI2_IRQHandler [WEAK]
285 EXPORT USART1_IRQHandler [WEAK]
286 EXPORT USART2_IRQHandler [WEAK]
287 EXPORT EXTI15_10_IRQHandler [WEAK]
288 EXPORT RTC_Alarm_IRQHandler [WEAK]
289 EXPORT DMA1_Stream7_IRQHandler [WEAK]
290 EXPORT TIM5_IRQHandler [WEAK]
291 EXPORT TIM6_DAC_IRQHandler [WEAK]
292 EXPORT DMA2_Stream0_IRQHandler [WEAK]
293 EXPORT DMA2_Stream1_IRQHandler [WEAK]
294 EXPORT DMA2_Stream2_IRQHandler [WEAK]
295 EXPORT DMA2_Stream3_IRQHandler [WEAK]
296 EXPORT DMA2_Stream4_IRQHandler [WEAK]
297 EXPORT DMA2_Stream4_IRQHandler [WEAK]
298 EXPORT DMA2_Stream5_IRQHandler [WEAK]
299 EXPORT DMA2_Stream6_IRQHandler [WEAK]
300 EXPORT DMA2_Stream7_IRQHandler [WEAK]
301 EXPORT USART6_IRQHandler [WEAK]
302 EXPORT RNG_IRQHandler [WEAK]
303 EXPORT FPU_IRQHandler [WEAK]
304 EXPORT SPI5_IRQHandler [WEAK]
305 EXPORT FMPI2C1_EV_IRQHandler [WEAK]
306 EXPORT FMPI2C1_ER_IRQHandler [WEAK]
307 EXPORT LPTIM1_IRQHandler [WEAK]
308
309 WWDG_IRQHandler
310 PVD_IRQHandler
311 TAMP_STAMP_IRQHandler
312 RTC_WKUP_IRQHandler
313 FLASH_IRQHandler
314 RCC_IRQHandler
315 EXTI0_IRQHandler
316 EXTI1_IRQHandler
317 EXTI2_IRQHandler
318 EXTI3_IRQHandler
319 EXTI4_IRQHandler
320 DMA1_Stream0_IRQHandler
321 DMA1_Stream1_IRQHandler
322 DMA1_Stream2_IRQHandler
323 DMA1_Stream3_IRQHandler
324 DMA1_Stream4_IRQHandler
325 DMA1_Stream5_IRQHandler
326 DMA1_Stream6_IRQHandler
327 ADC_IRQHandler
328 EXTI9_5_IRQHandler
329 TIM1_BRK_TIM9_IRQHandler
330 TIM1_UP_IRQHandler
331 TIM1_TRG_COM_TIM11_IRQHandler
332 TIM1_CC_IRQHandler
333 I2C1_EV_IRQHandler
334 I2C1_ER_IRQHandler
335 I2C2_EV_IRQHandler
336 I2C2_ER_IRQHandler
337 SPI1_IRQHandler
338 SPI2_IRQHandler
339 USART1_IRQHandler
340 USART2_IRQHandler
341 EXTI15_10_IRQHandler
342 RTC_Alarm_IRQHandler
343 DMA1_Stream7_IRQHandler
344 TIM5_IRQHandler
345 TIM6_DAC_IRQHandler
346 DMA2_Stream0_IRQHandler
347 DMA2_Stream1_IRQHandler
348 DMA2_Stream2_IRQHandler
349 DMA2_Stream3_IRQHandler
350 DMA2_Stream4_IRQHandler
351 DMA2_Stream5_IRQHandler
352 DMA2_Stream6_IRQHandler
353 DMA2_Stream7_IRQHandler
354 USART6_IRQHandler
355 RNG_IRQHandler
356 FPU_IRQHandler
357 SPI5_IRQHandler
358 FMPI2C1_EV_IRQHandler
359 FMPI2C1_ER_IRQHandler
360 LPTIM1_IRQHandler
361
362 B .
363
364 ENDP
365
366 ALIGN
367
368 ;*******************************************************************************
369 ; User Stack and Heap initialization
370 ;*******************************************************************************
371 IF :DEF:__MICROLIB
372
373 EXPORT __initial_sp
374 EXPORT __heap_base
375 EXPORT __heap_limit
376
377 ELSE
378
379 IMPORT __use_two_region_memory
380 EXPORT __user_initial_stackheap
381
382 __user_initial_stackheap
383
384 LDR R0, = Heap_Mem
385 LDR R1, =(Stack_Mem + Stack_Size)
386 LDR R2, = (Heap_Mem + Heap_Size)
387 LDR R3, = Stack_Mem
388 BX LR
389
390 ALIGN
391
392 ENDIF
393
394 END
395
396 ;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****