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comparison Common/Drivers/STM32F4xx/Include/stm32f469xx.h @ 160:e3ca52b8e7fa

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Merge with FlipDisplay
author heinrichsweikamp
date Thu, 07 Mar 2019 15:06:43 +0100
parents c78bcbd5deda
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80:cc2bb7bb8456 160:e3ca52b8e7fa
1 /**
2 ******************************************************************************
3 * @file stm32f469xx.h
4 * @author MCD Application Team
5 * @brief CMSIS STM32F469xx Device Peripheral Access Layer Header File.
6 *
7 * This file contains:
8 * - Data structures and the address mapping for all peripherals
9 * - peripherals registers declarations and bits definition
10 * - Macros to access peripheral’s registers hardware
11 *
12 ******************************************************************************
13 * @attention
14 *
15 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
16 *
17 * Redistribution and use in source and binary forms, with or without modification,
18 * are permitted provided that the following conditions are met:
19 * 1. Redistributions of source code must retain the above copyright notice,
20 * this list of conditions and the following disclaimer.
21 * 2. Redistributions in binary form must reproduce the above copyright notice,
22 * this list of conditions and the following disclaimer in the documentation
23 * and/or other materials provided with the distribution.
24 * 3. Neither the name of STMicroelectronics nor the names of its contributors
25 * may be used to endorse or promote products derived from this software
26 * without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
29 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
30 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
31 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
32 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
34 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
35 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
36 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
37 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
38 *
39 ******************************************************************************
40 */
41
42 /** @addtogroup CMSIS_Device
43 * @{
44 */
45
46 /** @addtogroup stm32f469xx
47 * @{
48 */
49
50 #ifndef __STM32F469xx_H
51 #define __STM32F469xx_H
52
53 #ifdef __cplusplus
54 extern "C" {
55 #endif /* __cplusplus */
56
57 /** @addtogroup Configuration_section_for_CMSIS
58 * @{
59 */
60
61 /**
62 * @brief Configuration of the Cortex-M4 Processor and Core Peripherals
63 */
64 #define __CM4_REV 0x0001U /*!< Core revision r0p1 */
65 #define __MPU_PRESENT 1U /*!< STM32F4XX provides an MPU */
66 #define __NVIC_PRIO_BITS 4U /*!< STM32F4XX uses 4 Bits for the Priority Levels */
67 #define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */
68 #define __FPU_PRESENT 1U /*!< FPU present */
69
70 /**
71 * @}
72 */
73
74 /** @addtogroup Peripheral_interrupt_number_definition
75 * @{
76 */
77
78 /**
79 * @brief STM32F4XX Interrupt Number Definition, according to the selected device
80 * in @ref Library_configuration_section
81 */
82 typedef enum
83 {
84 /****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/
85 NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
86 MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */
87 BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */
88 UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */
89 SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */
90 DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */
91 PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */
92 SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */
93 /****** STM32 specific Interrupt Numbers **********************************************************************/
94 WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
95 PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */
96 TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */
97 RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line */
98 FLASH_IRQn = 4, /*!< FLASH global Interrupt */
99 RCC_IRQn = 5, /*!< RCC global Interrupt */
100 EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */
101 EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */
102 EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */
103 EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */
104 EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */
105 DMA1_Stream0_IRQn = 11, /*!< DMA1 Stream 0 global Interrupt */
106 DMA1_Stream1_IRQn = 12, /*!< DMA1 Stream 1 global Interrupt */
107 DMA1_Stream2_IRQn = 13, /*!< DMA1 Stream 2 global Interrupt */
108 DMA1_Stream3_IRQn = 14, /*!< DMA1 Stream 3 global Interrupt */
109 DMA1_Stream4_IRQn = 15, /*!< DMA1 Stream 4 global Interrupt */
110 DMA1_Stream5_IRQn = 16, /*!< DMA1 Stream 5 global Interrupt */
111 DMA1_Stream6_IRQn = 17, /*!< DMA1 Stream 6 global Interrupt */
112 ADC_IRQn = 18, /*!< ADC1, ADC2 and ADC3 global Interrupts */
113 CAN1_TX_IRQn = 19, /*!< CAN1 TX Interrupt */
114 CAN1_RX0_IRQn = 20, /*!< CAN1 RX0 Interrupt */
115 CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */
116 CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */
117 EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
118 TIM1_BRK_TIM9_IRQn = 24, /*!< TIM1 Break interrupt and TIM9 global interrupt */
119 TIM1_UP_TIM10_IRQn = 25, /*!< TIM1 Update Interrupt and TIM10 global interrupt */
120 TIM1_TRG_COM_TIM11_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */
121 TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
122 TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
123 TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
124 TIM4_IRQn = 30, /*!< TIM4 global Interrupt */
125 I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
126 I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
127 I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
128 I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
129 SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
130 SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
131 USART1_IRQn = 37, /*!< USART1 global Interrupt */
132 USART2_IRQn = 38, /*!< USART2 global Interrupt */
133 USART3_IRQn = 39, /*!< USART3 global Interrupt */
134 EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
135 RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */
136 OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS Wakeup through EXTI line interrupt */
137 TIM8_BRK_TIM12_IRQn = 43, /*!< TIM8 Break Interrupt and TIM12 global interrupt */
138 TIM8_UP_TIM13_IRQn = 44, /*!< TIM8 Update Interrupt and TIM13 global interrupt */
139 TIM8_TRG_COM_TIM14_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */
140 TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare global interrupt */
141 DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */
142 FMC_IRQn = 48, /*!< FMC global Interrupt */
143 SDIO_IRQn = 49, /*!< SDIO global Interrupt */
144 TIM5_IRQn = 50, /*!< TIM5 global Interrupt */
145 SPI3_IRQn = 51, /*!< SPI3 global Interrupt */
146 UART4_IRQn = 52, /*!< UART4 global Interrupt */
147 UART5_IRQn = 53, /*!< UART5 global Interrupt */
148 TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC1&2 underrun error interrupts */
149 TIM7_IRQn = 55, /*!< TIM7 global interrupt */
150 DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */
151 DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */
152 DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */
153 DMA2_Stream3_IRQn = 59, /*!< DMA2 Stream 3 global Interrupt */
154 DMA2_Stream4_IRQn = 60, /*!< DMA2 Stream 4 global Interrupt */
155 ETH_IRQn = 61, /*!< Ethernet global Interrupt */
156 ETH_WKUP_IRQn = 62, /*!< Ethernet Wakeup through EXTI line Interrupt */
157 CAN2_TX_IRQn = 63, /*!< CAN2 TX Interrupt */
158 CAN2_RX0_IRQn = 64, /*!< CAN2 RX0 Interrupt */
159 CAN2_RX1_IRQn = 65, /*!< CAN2 RX1 Interrupt */
160 CAN2_SCE_IRQn = 66, /*!< CAN2 SCE Interrupt */
161 OTG_FS_IRQn = 67, /*!< USB OTG FS global Interrupt */
162 DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */
163 DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */
164 DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */
165 USART6_IRQn = 71, /*!< USART6 global interrupt */
166 I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */
167 I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */
168 OTG_HS_EP1_OUT_IRQn = 74, /*!< USB OTG HS End Point 1 Out global interrupt */
169 OTG_HS_EP1_IN_IRQn = 75, /*!< USB OTG HS End Point 1 In global interrupt */
170 OTG_HS_WKUP_IRQn = 76, /*!< USB OTG HS Wakeup through EXTI interrupt */
171 OTG_HS_IRQn = 77, /*!< USB OTG HS global interrupt */
172 DCMI_IRQn = 78, /*!< DCMI global interrupt */
173 HASH_RNG_IRQn = 80, /*!< Hash and Rng global interrupt */
174 FPU_IRQn = 81, /*!< FPU global interrupt */
175 UART7_IRQn = 82, /*!< UART7 global interrupt */
176 UART8_IRQn = 83, /*!< UART8 global interrupt */
177 SPI4_IRQn = 84, /*!< SPI4 global Interrupt */
178 SPI5_IRQn = 85, /*!< SPI5 global Interrupt */
179 SPI6_IRQn = 86, /*!< SPI6 global Interrupt */
180 SAI1_IRQn = 87, /*!< SAI1 global Interrupt */
181 LTDC_IRQn = 88, /*!< LTDC global Interrupt */
182 LTDC_ER_IRQn = 89, /*!< LTDC Error global Interrupt */
183 DMA2D_IRQn = 90, /*!< DMA2D global Interrupt */
184 QUADSPI_IRQn = 91, /*!< QUADSPI global Interrupt */
185 DSI_IRQn = 92 /*!< DSI global Interrupt */
186 } IRQn_Type;
187
188 /**
189 * @}
190 */
191
192 #include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
193 #include "system_stm32f4xx.h"
194 #include <stdint.h>
195
196 /** @addtogroup Peripheral_registers_structures
197 * @{
198 */
199
200 /**
201 * @brief Analog to Digital Converter
202 */
203
204 typedef struct
205 {
206 __IO uint32_t SR; /*!< ADC status register, Address offset: 0x00 */
207 __IO uint32_t CR1; /*!< ADC control register 1, Address offset: 0x04 */
208 __IO uint32_t CR2; /*!< ADC control register 2, Address offset: 0x08 */
209 __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x0C */
210 __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x10 */
211 __IO uint32_t JOFR1; /*!< ADC injected channel data offset register 1, Address offset: 0x14 */
212 __IO uint32_t JOFR2; /*!< ADC injected channel data offset register 2, Address offset: 0x18 */
213 __IO uint32_t JOFR3; /*!< ADC injected channel data offset register 3, Address offset: 0x1C */
214 __IO uint32_t JOFR4; /*!< ADC injected channel data offset register 4, Address offset: 0x20 */
215 __IO uint32_t HTR; /*!< ADC watchdog higher threshold register, Address offset: 0x24 */
216 __IO uint32_t LTR; /*!< ADC watchdog lower threshold register, Address offset: 0x28 */
217 __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x2C */
218 __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x30 */
219 __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x34 */
220 __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x38*/
221 __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x3C */
222 __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x40 */
223 __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x44 */
224 __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x48 */
225 __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x4C */
226 } ADC_TypeDef;
227
228 typedef struct
229 {
230 __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1 base address + 0x300 */
231 __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1 base address + 0x304 */
232 __IO uint32_t CDR; /*!< ADC common regular data register for dual
233 AND triple modes, Address offset: ADC1 base address + 0x308 */
234 } ADC_Common_TypeDef;
235
236
237 /**
238 * @brief Controller Area Network TxMailBox
239 */
240
241 typedef struct
242 {
243 __IO uint32_t TIR; /*!< CAN TX mailbox identifier register */
244 __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */
245 __IO uint32_t TDLR; /*!< CAN mailbox data low register */
246 __IO uint32_t TDHR; /*!< CAN mailbox data high register */
247 } CAN_TxMailBox_TypeDef;
248
249 /**
250 * @brief Controller Area Network FIFOMailBox
251 */
252
253 typedef struct
254 {
255 __IO uint32_t RIR; /*!< CAN receive FIFO mailbox identifier register */
256 __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */
257 __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */
258 __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */
259 } CAN_FIFOMailBox_TypeDef;
260
261 /**
262 * @brief Controller Area Network FilterRegister
263 */
264
265 typedef struct
266 {
267 __IO uint32_t FR1; /*!< CAN Filter bank register 1 */
268 __IO uint32_t FR2; /*!< CAN Filter bank register 1 */
269 } CAN_FilterRegister_TypeDef;
270
271 /**
272 * @brief Controller Area Network
273 */
274
275 typedef struct
276 {
277 __IO uint32_t MCR; /*!< CAN master control register, Address offset: 0x00 */
278 __IO uint32_t MSR; /*!< CAN master status register, Address offset: 0x04 */
279 __IO uint32_t TSR; /*!< CAN transmit status register, Address offset: 0x08 */
280 __IO uint32_t RF0R; /*!< CAN receive FIFO 0 register, Address offset: 0x0C */
281 __IO uint32_t RF1R; /*!< CAN receive FIFO 1 register, Address offset: 0x10 */
282 __IO uint32_t IER; /*!< CAN interrupt enable register, Address offset: 0x14 */
283 __IO uint32_t ESR; /*!< CAN error status register, Address offset: 0x18 */
284 __IO uint32_t BTR; /*!< CAN bit timing register, Address offset: 0x1C */
285 uint32_t RESERVED0[88]; /*!< Reserved, 0x020 - 0x17F */
286 CAN_TxMailBox_TypeDef sTxMailBox[3]; /*!< CAN Tx MailBox, Address offset: 0x180 - 0x1AC */
287 CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; /*!< CAN FIFO MailBox, Address offset: 0x1B0 - 0x1CC */
288 uint32_t RESERVED1[12]; /*!< Reserved, 0x1D0 - 0x1FF */
289 __IO uint32_t FMR; /*!< CAN filter master register, Address offset: 0x200 */
290 __IO uint32_t FM1R; /*!< CAN filter mode register, Address offset: 0x204 */
291 uint32_t RESERVED2; /*!< Reserved, 0x208 */
292 __IO uint32_t FS1R; /*!< CAN filter scale register, Address offset: 0x20C */
293 uint32_t RESERVED3; /*!< Reserved, 0x210 */
294 __IO uint32_t FFA1R; /*!< CAN filter FIFO assignment register, Address offset: 0x214 */
295 uint32_t RESERVED4; /*!< Reserved, 0x218 */
296 __IO uint32_t FA1R; /*!< CAN filter activation register, Address offset: 0x21C */
297 uint32_t RESERVED5[8]; /*!< Reserved, 0x220-0x23F */
298 CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register, Address offset: 0x240-0x31C */
299 } CAN_TypeDef;
300
301 /**
302 * @brief CRC calculation unit
303 */
304
305 typedef struct
306 {
307 __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
308 __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
309 uint8_t RESERVED0; /*!< Reserved, 0x05 */
310 uint16_t RESERVED1; /*!< Reserved, 0x06 */
311 __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
312 } CRC_TypeDef;
313
314 /**
315 * @brief Digital to Analog Converter
316 */
317
318 typedef struct
319 {
320 __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */
321 __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */
322 __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
323 __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */
324 __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */
325 __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
326 __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */
327 __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */
328 __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */
329 __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */
330 __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */
331 __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */
332 __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */
333 __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */
334 } DAC_TypeDef;
335
336 /**
337 * @brief Debug MCU
338 */
339
340 typedef struct
341 {
342 __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
343 __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
344 __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */
345 __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */
346 }DBGMCU_TypeDef;
347
348 /**
349 * @brief DCMI
350 */
351
352 typedef struct
353 {
354 __IO uint32_t CR; /*!< DCMI control register 1, Address offset: 0x00 */
355 __IO uint32_t SR; /*!< DCMI status register, Address offset: 0x04 */
356 __IO uint32_t RISR; /*!< DCMI raw interrupt status register, Address offset: 0x08 */
357 __IO uint32_t IER; /*!< DCMI interrupt enable register, Address offset: 0x0C */
358 __IO uint32_t MISR; /*!< DCMI masked interrupt status register, Address offset: 0x10 */
359 __IO uint32_t ICR; /*!< DCMI interrupt clear register, Address offset: 0x14 */
360 __IO uint32_t ESCR; /*!< DCMI embedded synchronization code register, Address offset: 0x18 */
361 __IO uint32_t ESUR; /*!< DCMI embedded synchronization unmask register, Address offset: 0x1C */
362 __IO uint32_t CWSTRTR; /*!< DCMI crop window start, Address offset: 0x20 */
363 __IO uint32_t CWSIZER; /*!< DCMI crop window size, Address offset: 0x24 */
364 __IO uint32_t DR; /*!< DCMI data register, Address offset: 0x28 */
365 } DCMI_TypeDef;
366
367 /**
368 * @brief DMA Controller
369 */
370
371 typedef struct
372 {
373 __IO uint32_t CR; /*!< DMA stream x configuration register */
374 __IO uint32_t NDTR; /*!< DMA stream x number of data register */
375 __IO uint32_t PAR; /*!< DMA stream x peripheral address register */
376 __IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */
377 __IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */
378 __IO uint32_t FCR; /*!< DMA stream x FIFO control register */
379 } DMA_Stream_TypeDef;
380
381 typedef struct
382 {
383 __IO uint32_t LISR; /*!< DMA low interrupt status register, Address offset: 0x00 */
384 __IO uint32_t HISR; /*!< DMA high interrupt status register, Address offset: 0x04 */
385 __IO uint32_t LIFCR; /*!< DMA low interrupt flag clear register, Address offset: 0x08 */
386 __IO uint32_t HIFCR; /*!< DMA high interrupt flag clear register, Address offset: 0x0C */
387 } DMA_TypeDef;
388
389 /**
390 * @brief DMA2D Controller
391 */
392
393 typedef struct
394 {
395 __IO uint32_t CR; /*!< DMA2D Control Register, Address offset: 0x00 */
396 __IO uint32_t ISR; /*!< DMA2D Interrupt Status Register, Address offset: 0x04 */
397 __IO uint32_t IFCR; /*!< DMA2D Interrupt Flag Clear Register, Address offset: 0x08 */
398 __IO uint32_t FGMAR; /*!< DMA2D Foreground Memory Address Register, Address offset: 0x0C */
399 __IO uint32_t FGOR; /*!< DMA2D Foreground Offset Register, Address offset: 0x10 */
400 __IO uint32_t BGMAR; /*!< DMA2D Background Memory Address Register, Address offset: 0x14 */
401 __IO uint32_t BGOR; /*!< DMA2D Background Offset Register, Address offset: 0x18 */
402 __IO uint32_t FGPFCCR; /*!< DMA2D Foreground PFC Control Register, Address offset: 0x1C */
403 __IO uint32_t FGCOLR; /*!< DMA2D Foreground Color Register, Address offset: 0x20 */
404 __IO uint32_t BGPFCCR; /*!< DMA2D Background PFC Control Register, Address offset: 0x24 */
405 __IO uint32_t BGCOLR; /*!< DMA2D Background Color Register, Address offset: 0x28 */
406 __IO uint32_t FGCMAR; /*!< DMA2D Foreground CLUT Memory Address Register, Address offset: 0x2C */
407 __IO uint32_t BGCMAR; /*!< DMA2D Background CLUT Memory Address Register, Address offset: 0x30 */
408 __IO uint32_t OPFCCR; /*!< DMA2D Output PFC Control Register, Address offset: 0x34 */
409 __IO uint32_t OCOLR; /*!< DMA2D Output Color Register, Address offset: 0x38 */
410 __IO uint32_t OMAR; /*!< DMA2D Output Memory Address Register, Address offset: 0x3C */
411 __IO uint32_t OOR; /*!< DMA2D Output Offset Register, Address offset: 0x40 */
412 __IO uint32_t NLR; /*!< DMA2D Number of Line Register, Address offset: 0x44 */
413 __IO uint32_t LWR; /*!< DMA2D Line Watermark Register, Address offset: 0x48 */
414 __IO uint32_t AMTCR; /*!< DMA2D AHB Master Timer Configuration Register, Address offset: 0x4C */
415 uint32_t RESERVED[236]; /*!< Reserved, 0x50-0x3FF */
416 __IO uint32_t FGCLUT[256]; /*!< DMA2D Foreground CLUT, Address offset:400-7FF */
417 __IO uint32_t BGCLUT[256]; /*!< DMA2D Background CLUT, Address offset:800-BFF */
418 } DMA2D_TypeDef;
419
420 /**
421 * @brief DSI Controller
422 */
423
424 typedef struct
425 {
426 __IO uint32_t VR; /*!< DSI Host Version Register, Address offset: 0x00 */
427 __IO uint32_t CR; /*!< DSI Host Control Register, Address offset: 0x04 */
428 __IO uint32_t CCR; /*!< DSI HOST Clock Control Register, Address offset: 0x08 */
429 __IO uint32_t LVCIDR; /*!< DSI Host LTDC VCID Register, Address offset: 0x0C */
430 __IO uint32_t LCOLCR; /*!< DSI Host LTDC Color Coding Register, Address offset: 0x10 */
431 __IO uint32_t LPCR; /*!< DSI Host LTDC Polarity Configuration Register, Address offset: 0x14 */
432 __IO uint32_t LPMCR; /*!< DSI Host Low-Power Mode Configuration Register, Address offset: 0x18 */
433 uint32_t RESERVED0[4]; /*!< Reserved, 0x1C - 0x2B */
434 __IO uint32_t PCR; /*!< DSI Host Protocol Configuration Register, Address offset: 0x2C */
435 __IO uint32_t GVCIDR; /*!< DSI Host Generic VCID Register, Address offset: 0x30 */
436 __IO uint32_t MCR; /*!< DSI Host Mode Configuration Register, Address offset: 0x34 */
437 __IO uint32_t VMCR; /*!< DSI Host Video Mode Configuration Register, Address offset: 0x38 */
438 __IO uint32_t VPCR; /*!< DSI Host Video Packet Configuration Register, Address offset: 0x3C */
439 __IO uint32_t VCCR; /*!< DSI Host Video Chunks Configuration Register, Address offset: 0x40 */
440 __IO uint32_t VNPCR; /*!< DSI Host Video Null Packet Configuration Register, Address offset: 0x44 */
441 __IO uint32_t VHSACR; /*!< DSI Host Video HSA Configuration Register, Address offset: 0x48 */
442 __IO uint32_t VHBPCR; /*!< DSI Host Video HBP Configuration Register, Address offset: 0x4C */
443 __IO uint32_t VLCR; /*!< DSI Host Video Line Configuration Register, Address offset: 0x50 */
444 __IO uint32_t VVSACR; /*!< DSI Host Video VSA Configuration Register, Address offset: 0x54 */
445 __IO uint32_t VVBPCR; /*!< DSI Host Video VBP Configuration Register, Address offset: 0x58 */
446 __IO uint32_t VVFPCR; /*!< DSI Host Video VFP Configuration Register, Address offset: 0x5C */
447 __IO uint32_t VVACR; /*!< DSI Host Video VA Configuration Register, Address offset: 0x60 */
448 __IO uint32_t LCCR; /*!< DSI Host LTDC Command Configuration Register, Address offset: 0x64 */
449 __IO uint32_t CMCR; /*!< DSI Host Command Mode Configuration Register, Address offset: 0x68 */
450 __IO uint32_t GHCR; /*!< DSI Host Generic Header Configuration Register, Address offset: 0x6C */
451 __IO uint32_t GPDR; /*!< DSI Host Generic Payload Data Register, Address offset: 0x70 */
452 __IO uint32_t GPSR; /*!< DSI Host Generic Packet Status Register, Address offset: 0x74 */
453 __IO uint32_t TCCR[6]; /*!< DSI Host Timeout Counter Configuration Register, Address offset: 0x78-0x8F */
454 __IO uint32_t TDCR; /*!< DSI Host 3D Configuration Register, Address offset: 0x90 */
455 __IO uint32_t CLCR; /*!< DSI Host Clock Lane Configuration Register, Address offset: 0x94 */
456 __IO uint32_t CLTCR; /*!< DSI Host Clock Lane Timer Configuration Register, Address offset: 0x98 */
457 __IO uint32_t DLTCR; /*!< DSI Host Data Lane Timer Configuration Register, Address offset: 0x9C */
458 __IO uint32_t PCTLR; /*!< DSI Host PHY Control Register, Address offset: 0xA0 */
459 __IO uint32_t PCONFR; /*!< DSI Host PHY Configuration Register, Address offset: 0xA4 */
460 __IO uint32_t PUCR; /*!< DSI Host PHY ULPS Control Register, Address offset: 0xA8 */
461 __IO uint32_t PTTCR; /*!< DSI Host PHY TX Triggers Configuration Register, Address offset: 0xAC */
462 __IO uint32_t PSR; /*!< DSI Host PHY Status Register, Address offset: 0xB0 */
463 uint32_t RESERVED1[2]; /*!< Reserved, 0xB4 - 0xBB */
464 __IO uint32_t ISR[2]; /*!< DSI Host Interrupt & Status Register, Address offset: 0xBC-0xC3 */
465 __IO uint32_t IER[2]; /*!< DSI Host Interrupt Enable Register, Address offset: 0xC4-0xCB */
466 uint32_t RESERVED2[3]; /*!< Reserved, 0xD0 - 0xD7 */
467 __IO uint32_t FIR[2]; /*!< DSI Host Force Interrupt Register, Address offset: 0xD8-0xDF */
468 uint32_t RESERVED3[8]; /*!< Reserved, 0xE0 - 0xFF */
469 __IO uint32_t VSCR; /*!< DSI Host Video Shadow Control Register, Address offset: 0x100 */
470 uint32_t RESERVED4[2]; /*!< Reserved, 0x104 - 0x10B */
471 __IO uint32_t LCVCIDR; /*!< DSI Host LTDC Current VCID Register, Address offset: 0x10C */
472 __IO uint32_t LCCCR; /*!< DSI Host LTDC Current Color Coding Register, Address offset: 0x110 */
473 uint32_t RESERVED5; /*!< Reserved, 0x114 */
474 __IO uint32_t LPMCCR; /*!< DSI Host Low-power Mode Current Configuration Register, Address offset: 0x118 */
475 uint32_t RESERVED6[7]; /*!< Reserved, 0x11C - 0x137 */
476 __IO uint32_t VMCCR; /*!< DSI Host Video Mode Current Configuration Register, Address offset: 0x138 */
477 __IO uint32_t VPCCR; /*!< DSI Host Video Packet Current Configuration Register, Address offset: 0x13C */
478 __IO uint32_t VCCCR; /*!< DSI Host Video Chuncks Current Configuration Register, Address offset: 0x140 */
479 __IO uint32_t VNPCCR; /*!< DSI Host Video Null Packet Current Configuration Register, Address offset: 0x144 */
480 __IO uint32_t VHSACCR; /*!< DSI Host Video HSA Current Configuration Register, Address offset: 0x148 */
481 __IO uint32_t VHBPCCR; /*!< DSI Host Video HBP Current Configuration Register, Address offset: 0x14C */
482 __IO uint32_t VLCCR; /*!< DSI Host Video Line Current Configuration Register, Address offset: 0x150 */
483 __IO uint32_t VVSACCR; /*!< DSI Host Video VSA Current Configuration Register, Address offset: 0x154 */
484 __IO uint32_t VVBPCCR; /*!< DSI Host Video VBP Current Configuration Register, Address offset: 0x158 */
485 __IO uint32_t VVFPCCR; /*!< DSI Host Video VFP Current Configuration Register, Address offset: 0x15C */
486 __IO uint32_t VVACCR; /*!< DSI Host Video VA Current Configuration Register, Address offset: 0x160 */
487 uint32_t RESERVED7[11]; /*!< Reserved, 0x164 - 0x18F */
488 __IO uint32_t TDCCR; /*!< DSI Host 3D Current Configuration Register, Address offset: 0x190 */
489 uint32_t RESERVED8[155]; /*!< Reserved, 0x194 - 0x3FF */
490 __IO uint32_t WCFGR; /*!< DSI Wrapper Configuration Register, Address offset: 0x400 */
491 __IO uint32_t WCR; /*!< DSI Wrapper Control Register, Address offset: 0x404 */
492 __IO uint32_t WIER; /*!< DSI Wrapper Interrupt Enable Register, Address offset: 0x408 */
493 __IO uint32_t WISR; /*!< DSI Wrapper Interrupt and Status Register, Address offset: 0x40C */
494 __IO uint32_t WIFCR; /*!< DSI Wrapper Interrupt Flag Clear Register, Address offset: 0x410 */
495 uint32_t RESERVED9; /*!< Reserved, 0x414 */
496 __IO uint32_t WPCR[5]; /*!< DSI Wrapper PHY Configuration Register, Address offset: 0x418-0x42B */
497 uint32_t RESERVED10; /*!< Reserved, 0x42C */
498 __IO uint32_t WRPCR; /*!< DSI Wrapper Regulator and PLL Control Register, Address offset: 0x430 */
499 } DSI_TypeDef;
500
501 /**
502 * @brief Ethernet MAC
503 */
504
505 typedef struct
506 {
507 __IO uint32_t MACCR;
508 __IO uint32_t MACFFR;
509 __IO uint32_t MACHTHR;
510 __IO uint32_t MACHTLR;
511 __IO uint32_t MACMIIAR;
512 __IO uint32_t MACMIIDR;
513 __IO uint32_t MACFCR;
514 __IO uint32_t MACVLANTR; /* 8 */
515 uint32_t RESERVED0[2];
516 __IO uint32_t MACRWUFFR; /* 11 */
517 __IO uint32_t MACPMTCSR;
518 uint32_t RESERVED1;
519 __IO uint32_t MACDBGR;
520 __IO uint32_t MACSR; /* 15 */
521 __IO uint32_t MACIMR;
522 __IO uint32_t MACA0HR;
523 __IO uint32_t MACA0LR;
524 __IO uint32_t MACA1HR;
525 __IO uint32_t MACA1LR;
526 __IO uint32_t MACA2HR;
527 __IO uint32_t MACA2LR;
528 __IO uint32_t MACA3HR;
529 __IO uint32_t MACA3LR; /* 24 */
530 uint32_t RESERVED2[40];
531 __IO uint32_t MMCCR; /* 65 */
532 __IO uint32_t MMCRIR;
533 __IO uint32_t MMCTIR;
534 __IO uint32_t MMCRIMR;
535 __IO uint32_t MMCTIMR; /* 69 */
536 uint32_t RESERVED3[14];
537 __IO uint32_t MMCTGFSCCR; /* 84 */
538 __IO uint32_t MMCTGFMSCCR;
539 uint32_t RESERVED4[5];
540 __IO uint32_t MMCTGFCR;
541 uint32_t RESERVED5[10];
542 __IO uint32_t MMCRFCECR;
543 __IO uint32_t MMCRFAECR;
544 uint32_t RESERVED6[10];
545 __IO uint32_t MMCRGUFCR;
546 uint32_t RESERVED7[334];
547 __IO uint32_t PTPTSCR;
548 __IO uint32_t PTPSSIR;
549 __IO uint32_t PTPTSHR;
550 __IO uint32_t PTPTSLR;
551 __IO uint32_t PTPTSHUR;
552 __IO uint32_t PTPTSLUR;
553 __IO uint32_t PTPTSAR;
554 __IO uint32_t PTPTTHR;
555 __IO uint32_t PTPTTLR;
556 __IO uint32_t RESERVED8;
557 __IO uint32_t PTPTSSR;
558 uint32_t RESERVED9[565];
559 __IO uint32_t DMABMR;
560 __IO uint32_t DMATPDR;
561 __IO uint32_t DMARPDR;
562 __IO uint32_t DMARDLAR;
563 __IO uint32_t DMATDLAR;
564 __IO uint32_t DMASR;
565 __IO uint32_t DMAOMR;
566 __IO uint32_t DMAIER;
567 __IO uint32_t DMAMFBOCR;
568 __IO uint32_t DMARSWTR;
569 uint32_t RESERVED10[8];
570 __IO uint32_t DMACHTDR;
571 __IO uint32_t DMACHRDR;
572 __IO uint32_t DMACHTBAR;
573 __IO uint32_t DMACHRBAR;
574 } ETH_TypeDef;
575
576 /**
577 * @brief External Interrupt/Event Controller
578 */
579
580 typedef struct
581 {
582 __IO uint32_t IMR; /*!< EXTI Interrupt mask register, Address offset: 0x00 */
583 __IO uint32_t EMR; /*!< EXTI Event mask register, Address offset: 0x04 */
584 __IO uint32_t RTSR; /*!< EXTI Rising trigger selection register, Address offset: 0x08 */
585 __IO uint32_t FTSR; /*!< EXTI Falling trigger selection register, Address offset: 0x0C */
586 __IO uint32_t SWIER; /*!< EXTI Software interrupt event register, Address offset: 0x10 */
587 __IO uint32_t PR; /*!< EXTI Pending register, Address offset: 0x14 */
588 } EXTI_TypeDef;
589
590 /**
591 * @brief FLASH Registers
592 */
593
594 typedef struct
595 {
596 __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */
597 __IO uint32_t KEYR; /*!< FLASH key register, Address offset: 0x04 */
598 __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x08 */
599 __IO uint32_t SR; /*!< FLASH status register, Address offset: 0x0C */
600 __IO uint32_t CR; /*!< FLASH control register, Address offset: 0x10 */
601 __IO uint32_t OPTCR; /*!< FLASH option control register , Address offset: 0x14 */
602 __IO uint32_t OPTCR1; /*!< FLASH option control register 1, Address offset: 0x18 */
603 } FLASH_TypeDef;
604
605 /**
606 * @brief Flexible Memory Controller
607 */
608
609 typedef struct
610 {
611 __IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */
612 } FMC_Bank1_TypeDef;
613
614 /**
615 * @brief Flexible Memory Controller Bank1E
616 */
617
618 typedef struct
619 {
620 __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */
621 } FMC_Bank1E_TypeDef;
622
623 /**
624 * @brief Flexible Memory Controller Bank3
625 */
626
627 typedef struct
628 {
629 __IO uint32_t PCR; /*!< NAND Flash control register, Address offset: 0x80 */
630 __IO uint32_t SR; /*!< NAND Flash FIFO status and interrupt register, Address offset: 0x84 */
631 __IO uint32_t PMEM; /*!< NAND Flash Common memory space timing register, Address offset: 0x88 */
632 __IO uint32_t PATT; /*!< NAND Flash Attribute memory space timing register, Address offset: 0x8C */
633 uint32_t RESERVED; /*!< Reserved, 0x90 */
634 __IO uint32_t ECCR; /*!< NAND Flash ECC result registers, Address offset: 0x94 */
635 } FMC_Bank3_TypeDef;
636
637 /**
638 * @brief Flexible Memory Controller Bank5_6
639 */
640
641 typedef struct
642 {
643 __IO uint32_t SDCR[2]; /*!< SDRAM Control registers , Address offset: 0x140-0x144 */
644 __IO uint32_t SDTR[2]; /*!< SDRAM Timing registers , Address offset: 0x148-0x14C */
645 __IO uint32_t SDCMR; /*!< SDRAM Command Mode register, Address offset: 0x150 */
646 __IO uint32_t SDRTR; /*!< SDRAM Refresh Timer register, Address offset: 0x154 */
647 __IO uint32_t SDSR; /*!< SDRAM Status register, Address offset: 0x158 */
648 } FMC_Bank5_6_TypeDef;
649
650 /**
651 * @brief General Purpose I/O
652 */
653
654 typedef struct
655 {
656 __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */
657 __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */
658 __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */
659 __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
660 __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
661 __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
662 __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */
663 __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
664 __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */
665 } GPIO_TypeDef;
666
667 /**
668 * @brief System configuration controller
669 */
670
671 typedef struct
672 {
673 __IO uint32_t MEMRMP; /*!< SYSCFG memory remap register, Address offset: 0x00 */
674 __IO uint32_t PMC; /*!< SYSCFG peripheral mode configuration register, Address offset: 0x04 */
675 __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */
676 uint32_t RESERVED[2]; /*!< Reserved, 0x18-0x1C */
677 __IO uint32_t CMPCR; /*!< SYSCFG Compensation cell control register, Address offset: 0x20 */
678 } SYSCFG_TypeDef;
679
680 /**
681 * @brief Inter-integrated Circuit Interface
682 */
683
684 typedef struct
685 {
686 __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */
687 __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */
688 __IO uint32_t OAR1; /*!< I2C Own address register 1, Address offset: 0x08 */
689 __IO uint32_t OAR2; /*!< I2C Own address register 2, Address offset: 0x0C */
690 __IO uint32_t DR; /*!< I2C Data register, Address offset: 0x10 */
691 __IO uint32_t SR1; /*!< I2C Status register 1, Address offset: 0x14 */
692 __IO uint32_t SR2; /*!< I2C Status register 2, Address offset: 0x18 */
693 __IO uint32_t CCR; /*!< I2C Clock control register, Address offset: 0x1C */
694 __IO uint32_t TRISE; /*!< I2C TRISE register, Address offset: 0x20 */
695 __IO uint32_t FLTR; /*!< I2C FLTR register, Address offset: 0x24 */
696 } I2C_TypeDef;
697
698 /**
699 * @brief Independent WATCHDOG
700 */
701
702 typedef struct
703 {
704 __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */
705 __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */
706 __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */
707 __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */
708 } IWDG_TypeDef;
709
710 /**
711 * @brief LCD-TFT Display Controller
712 */
713
714 typedef struct
715 {
716 uint32_t RESERVED0[2]; /*!< Reserved, 0x00-0x04 */
717 __IO uint32_t SSCR; /*!< LTDC Synchronization Size Configuration Register, Address offset: 0x08 */
718 __IO uint32_t BPCR; /*!< LTDC Back Porch Configuration Register, Address offset: 0x0C */
719 __IO uint32_t AWCR; /*!< LTDC Active Width Configuration Register, Address offset: 0x10 */
720 __IO uint32_t TWCR; /*!< LTDC Total Width Configuration Register, Address offset: 0x14 */
721 __IO uint32_t GCR; /*!< LTDC Global Control Register, Address offset: 0x18 */
722 uint32_t RESERVED1[2]; /*!< Reserved, 0x1C-0x20 */
723 __IO uint32_t SRCR; /*!< LTDC Shadow Reload Configuration Register, Address offset: 0x24 */
724 uint32_t RESERVED2[1]; /*!< Reserved, 0x28 */
725 __IO uint32_t BCCR; /*!< LTDC Background Color Configuration Register, Address offset: 0x2C */
726 uint32_t RESERVED3[1]; /*!< Reserved, 0x30 */
727 __IO uint32_t IER; /*!< LTDC Interrupt Enable Register, Address offset: 0x34 */
728 __IO uint32_t ISR; /*!< LTDC Interrupt Status Register, Address offset: 0x38 */
729 __IO uint32_t ICR; /*!< LTDC Interrupt Clear Register, Address offset: 0x3C */
730 __IO uint32_t LIPCR; /*!< LTDC Line Interrupt Position Configuration Register, Address offset: 0x40 */
731 __IO uint32_t CPSR; /*!< LTDC Current Position Status Register, Address offset: 0x44 */
732 __IO uint32_t CDSR; /*!< LTDC Current Display Status Register, Address offset: 0x48 */
733 } LTDC_TypeDef;
734
735 /**
736 * @brief LCD-TFT Display layer x Controller
737 */
738
739 typedef struct
740 {
741 __IO uint32_t CR; /*!< LTDC Layerx Control Register Address offset: 0x84 */
742 __IO uint32_t WHPCR; /*!< LTDC Layerx Window Horizontal Position Configuration Register Address offset: 0x88 */
743 __IO uint32_t WVPCR; /*!< LTDC Layerx Window Vertical Position Configuration Register Address offset: 0x8C */
744 __IO uint32_t CKCR; /*!< LTDC Layerx Color Keying Configuration Register Address offset: 0x90 */
745 __IO uint32_t PFCR; /*!< LTDC Layerx Pixel Format Configuration Register Address offset: 0x94 */
746 __IO uint32_t CACR; /*!< LTDC Layerx Constant Alpha Configuration Register Address offset: 0x98 */
747 __IO uint32_t DCCR; /*!< LTDC Layerx Default Color Configuration Register Address offset: 0x9C */
748 __IO uint32_t BFCR; /*!< LTDC Layerx Blending Factors Configuration Register Address offset: 0xA0 */
749 uint32_t RESERVED0[2]; /*!< Reserved */
750 __IO uint32_t CFBAR; /*!< LTDC Layerx Color Frame Buffer Address Register Address offset: 0xAC */
751 __IO uint32_t CFBLR; /*!< LTDC Layerx Color Frame Buffer Length Register Address offset: 0xB0 */
752 __IO uint32_t CFBLNR; /*!< LTDC Layerx ColorFrame Buffer Line Number Register Address offset: 0xB4 */
753 uint32_t RESERVED1[3]; /*!< Reserved */
754 __IO uint32_t CLUTWR; /*!< LTDC Layerx CLUT Write Register Address offset: 0x144*/
755 } LTDC_Layer_TypeDef;
756
757 /**
758 * @brief Power Control
759 */
760
761 typedef struct
762 {
763 __IO uint32_t CR; /*!< PWR power control register, Address offset: 0x00 */
764 __IO uint32_t CSR; /*!< PWR power control/status register, Address offset: 0x04 */
765 } PWR_TypeDef;
766
767 /**
768 * @brief Reset and Clock Control
769 */
770
771 typedef struct
772 {
773 __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */
774 __IO uint32_t PLLCFGR; /*!< RCC PLL configuration register, Address offset: 0x04 */
775 __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x08 */
776 __IO uint32_t CIR; /*!< RCC clock interrupt register, Address offset: 0x0C */
777 __IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x10 */
778 __IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x14 */
779 __IO uint32_t AHB3RSTR; /*!< RCC AHB3 peripheral reset register, Address offset: 0x18 */
780 uint32_t RESERVED0; /*!< Reserved, 0x1C */
781 __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x20 */
782 __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x24 */
783 uint32_t RESERVED1[2]; /*!< Reserved, 0x28-0x2C */
784 __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clock register, Address offset: 0x30 */
785 __IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clock register, Address offset: 0x34 */
786 __IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clock register, Address offset: 0x38 */
787 uint32_t RESERVED2; /*!< Reserved, 0x3C */
788 __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral clock enable register, Address offset: 0x40 */
789 __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock enable register, Address offset: 0x44 */
790 uint32_t RESERVED3[2]; /*!< Reserved, 0x48-0x4C */
791 __IO uint32_t AHB1LPENR; /*!< RCC AHB1 peripheral clock enable in low power mode register, Address offset: 0x50 */
792 __IO uint32_t AHB2LPENR; /*!< RCC AHB2 peripheral clock enable in low power mode register, Address offset: 0x54 */
793 __IO uint32_t AHB3LPENR; /*!< RCC AHB3 peripheral clock enable in low power mode register, Address offset: 0x58 */
794 uint32_t RESERVED4; /*!< Reserved, 0x5C */
795 __IO uint32_t APB1LPENR; /*!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x60 */
796 __IO uint32_t APB2LPENR; /*!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x64 */
797 uint32_t RESERVED5[2]; /*!< Reserved, 0x68-0x6C */
798 __IO uint32_t BDCR; /*!< RCC Backup domain control register, Address offset: 0x70 */
799 __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x74 */
800 uint32_t RESERVED6[2]; /*!< Reserved, 0x78-0x7C */
801 __IO uint32_t SSCGR; /*!< RCC spread spectrum clock generation register, Address offset: 0x80 */
802 __IO uint32_t PLLI2SCFGR; /*!< RCC PLLI2S configuration register, Address offset: 0x84 */
803 __IO uint32_t PLLSAICFGR; /*!< RCC PLLSAI configuration register, Address offset: 0x88 */
804 __IO uint32_t DCKCFGR; /*!< RCC Dedicated Clocks configuration register, Address offset: 0x8C */
805 } RCC_TypeDef;
806
807 /**
808 * @brief Real-Time Clock
809 */
810
811 typedef struct
812 {
813 __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */
814 __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */
815 __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */
816 __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */
817 __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */
818 __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */
819 __IO uint32_t CALIBR; /*!< RTC calibration register, Address offset: 0x18 */
820 __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */
821 __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */
822 __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */
823 __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */
824 __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */
825 __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */
826 __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */
827 __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */
828 __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */
829 __IO uint32_t TAFCR; /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */
830 __IO uint32_t ALRMASSR;/*!< RTC alarm A sub second register, Address offset: 0x44 */
831 __IO uint32_t ALRMBSSR;/*!< RTC alarm B sub second register, Address offset: 0x48 */
832 uint32_t RESERVED7; /*!< Reserved, 0x4C */
833 __IO uint32_t BKP0R; /*!< RTC backup register 1, Address offset: 0x50 */
834 __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */
835 __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */
836 __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */
837 __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */
838 __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */
839 __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */
840 __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */
841 __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */
842 __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */
843 __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */
844 __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */
845 __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */
846 __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */
847 __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */
848 __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */
849 __IO uint32_t BKP16R; /*!< RTC backup register 16, Address offset: 0x90 */
850 __IO uint32_t BKP17R; /*!< RTC backup register 17, Address offset: 0x94 */
851 __IO uint32_t BKP18R; /*!< RTC backup register 18, Address offset: 0x98 */
852 __IO uint32_t BKP19R; /*!< RTC backup register 19, Address offset: 0x9C */
853 } RTC_TypeDef;
854
855 /**
856 * @brief Serial Audio Interface
857 */
858
859 typedef struct
860 {
861 __IO uint32_t GCR; /*!< SAI global configuration register, Address offset: 0x00 */
862 } SAI_TypeDef;
863
864 typedef struct
865 {
866 __IO uint32_t CR1; /*!< SAI block x configuration register 1, Address offset: 0x04 */
867 __IO uint32_t CR2; /*!< SAI block x configuration register 2, Address offset: 0x08 */
868 __IO uint32_t FRCR; /*!< SAI block x frame configuration register, Address offset: 0x0C */
869 __IO uint32_t SLOTR; /*!< SAI block x slot register, Address offset: 0x10 */
870 __IO uint32_t IMR; /*!< SAI block x interrupt mask register, Address offset: 0x14 */
871 __IO uint32_t SR; /*!< SAI block x status register, Address offset: 0x18 */
872 __IO uint32_t CLRFR; /*!< SAI block x clear flag register, Address offset: 0x1C */
873 __IO uint32_t DR; /*!< SAI block x data register, Address offset: 0x20 */
874 } SAI_Block_TypeDef;
875
876 /**
877 * @brief SD host Interface
878 */
879
880 typedef struct
881 {
882 __IO uint32_t POWER; /*!< SDIO power control register, Address offset: 0x00 */
883 __IO uint32_t CLKCR; /*!< SDI clock control register, Address offset: 0x04 */
884 __IO uint32_t ARG; /*!< SDIO argument register, Address offset: 0x08 */
885 __IO uint32_t CMD; /*!< SDIO command register, Address offset: 0x0C */
886 __IO const uint32_t RESPCMD; /*!< SDIO command response register, Address offset: 0x10 */
887 __IO const uint32_t RESP1; /*!< SDIO response 1 register, Address offset: 0x14 */
888 __IO const uint32_t RESP2; /*!< SDIO response 2 register, Address offset: 0x18 */
889 __IO const uint32_t RESP3; /*!< SDIO response 3 register, Address offset: 0x1C */
890 __IO const uint32_t RESP4; /*!< SDIO response 4 register, Address offset: 0x20 */
891 __IO uint32_t DTIMER; /*!< SDIO data timer register, Address offset: 0x24 */
892 __IO uint32_t DLEN; /*!< SDIO data length register, Address offset: 0x28 */
893 __IO uint32_t DCTRL; /*!< SDIO data control register, Address offset: 0x2C */
894 __IO const uint32_t DCOUNT; /*!< SDIO data counter register, Address offset: 0x30 */
895 __IO const uint32_t STA; /*!< SDIO status register, Address offset: 0x34 */
896 __IO uint32_t ICR; /*!< SDIO interrupt clear register, Address offset: 0x38 */
897 __IO uint32_t MASK; /*!< SDIO mask register, Address offset: 0x3C */
898 uint32_t RESERVED0[2]; /*!< Reserved, 0x40-0x44 */
899 __IO const uint32_t FIFOCNT; /*!< SDIO FIFO counter register, Address offset: 0x48 */
900 uint32_t RESERVED1[13]; /*!< Reserved, 0x4C-0x7C */
901 __IO uint32_t FIFO; /*!< SDIO data FIFO register, Address offset: 0x80 */
902 } SDIO_TypeDef;
903
904 /**
905 * @brief Serial Peripheral Interface
906 */
907
908 typedef struct
909 {
910 __IO uint32_t CR1; /*!< SPI control register 1 (not used in I2S mode), Address offset: 0x00 */
911 __IO uint32_t CR2; /*!< SPI control register 2, Address offset: 0x04 */
912 __IO uint32_t SR; /*!< SPI status register, Address offset: 0x08 */
913 __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */
914 __IO uint32_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
915 __IO uint32_t RXCRCR; /*!< SPI RX CRC register (not used in I2S mode), Address offset: 0x14 */
916 __IO uint32_t TXCRCR; /*!< SPI TX CRC register (not used in I2S mode), Address offset: 0x18 */
917 __IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */
918 __IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */
919 } SPI_TypeDef;
920
921 /**
922 * @brief QUAD Serial Peripheral Interface
923 */
924
925 typedef struct
926 {
927 __IO uint32_t CR; /*!< QUADSPI Control register, Address offset: 0x00 */
928 __IO uint32_t DCR; /*!< QUADSPI Device Configuration register, Address offset: 0x04 */
929 __IO uint32_t SR; /*!< QUADSPI Status register, Address offset: 0x08 */
930 __IO uint32_t FCR; /*!< QUADSPI Flag Clear register, Address offset: 0x0C */
931 __IO uint32_t DLR; /*!< QUADSPI Data Length register, Address offset: 0x10 */
932 __IO uint32_t CCR; /*!< QUADSPI Communication Configuration register, Address offset: 0x14 */
933 __IO uint32_t AR; /*!< QUADSPI Address register, Address offset: 0x18 */
934 __IO uint32_t ABR; /*!< QUADSPI Alternate Bytes register, Address offset: 0x1C */
935 __IO uint32_t DR; /*!< QUADSPI Data register, Address offset: 0x20 */
936 __IO uint32_t PSMKR; /*!< QUADSPI Polling Status Mask register, Address offset: 0x24 */
937 __IO uint32_t PSMAR; /*!< QUADSPI Polling Status Match register, Address offset: 0x28 */
938 __IO uint32_t PIR; /*!< QUADSPI Polling Interval register, Address offset: 0x2C */
939 __IO uint32_t LPTR; /*!< QUADSPI Low Power Timeout register, Address offset: 0x30 */
940 } QUADSPI_TypeDef;
941
942 /**
943 * @brief TIM
944 */
945
946 typedef struct
947 {
948 __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
949 __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
950 __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */
951 __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
952 __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */
953 __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
954 __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
955 __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
956 __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
957 __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
958 __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */
959 __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
960 __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */
961 __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
962 __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
963 __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
964 __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
965 __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */
966 __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
967 __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */
968 __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */
969 } TIM_TypeDef;
970
971 /**
972 * @brief Universal Synchronous Asynchronous Receiver Transmitter
973 */
974
975 typedef struct
976 {
977 __IO uint32_t SR; /*!< USART Status register, Address offset: 0x00 */
978 __IO uint32_t DR; /*!< USART Data register, Address offset: 0x04 */
979 __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x08 */
980 __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x0C */
981 __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x10 */
982 __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x14 */
983 __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x18 */
984 } USART_TypeDef;
985
986 /**
987 * @brief Window WATCHDOG
988 */
989
990 typedef struct
991 {
992 __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
993 __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
994 __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
995 } WWDG_TypeDef;
996
997 /**
998 * @brief RNG
999 */
1000
1001 typedef struct
1002 {
1003 __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */
1004 __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */
1005 __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */
1006 } RNG_TypeDef;
1007
1008 /**
1009 * @brief USB_OTG_Core_Registers
1010 */
1011 typedef struct
1012 {
1013 __IO uint32_t GOTGCTL; /*!< USB_OTG Control and Status Register 000h */
1014 __IO uint32_t GOTGINT; /*!< USB_OTG Interrupt Register 004h */
1015 __IO uint32_t GAHBCFG; /*!< Core AHB Configuration Register 008h */
1016 __IO uint32_t GUSBCFG; /*!< Core USB Configuration Register 00Ch */
1017 __IO uint32_t GRSTCTL; /*!< Core Reset Register 010h */
1018 __IO uint32_t GINTSTS; /*!< Core Interrupt Register 014h */
1019 __IO uint32_t GINTMSK; /*!< Core Interrupt Mask Register 018h */
1020 __IO uint32_t GRXSTSR; /*!< Receive Sts Q Read Register 01Ch */
1021 __IO uint32_t GRXSTSP; /*!< Receive Sts Q Read & POP Register 020h */
1022 __IO uint32_t GRXFSIZ; /*!< Receive FIFO Size Register 024h */
1023 __IO uint32_t DIEPTXF0_HNPTXFSIZ; /*!< EP0 / Non Periodic Tx FIFO Size Register 028h */
1024 __IO uint32_t HNPTXSTS; /*!< Non Periodic Tx FIFO/Queue Sts reg 02Ch */
1025 uint32_t Reserved30[2]; /*!< Reserved 030h */
1026 __IO uint32_t GCCFG; /*!< General Purpose IO Register 038h */
1027 __IO uint32_t CID; /*!< User ID Register 03Ch */
1028 uint32_t Reserved5[3]; /*!< Reserved 040h-048h */
1029 __IO uint32_t GHWCFG3; /*!< User HW config3 04Ch */
1030 uint32_t Reserved6; /*!< Reserved 050h */
1031 __IO uint32_t GLPMCFG; /*!< LPM Register 054h */
1032 uint32_t Reserved; /*!< Reserved 058h */
1033 __IO uint32_t GDFIFOCFG; /*!< DFIFO Software Config Register 05Ch */
1034 uint32_t Reserved43[40]; /*!< Reserved 058h-0FFh */
1035 __IO uint32_t HPTXFSIZ; /*!< Host Periodic Tx FIFO Size Reg 100h */
1036 __IO uint32_t DIEPTXF[0x0F]; /*!< dev Periodic Transmit FIFO */
1037 } USB_OTG_GlobalTypeDef;
1038
1039 /**
1040 * @brief USB_OTG_device_Registers
1041 */
1042 typedef struct
1043 {
1044 __IO uint32_t DCFG; /*!< dev Configuration Register 800h */
1045 __IO uint32_t DCTL; /*!< dev Control Register 804h */
1046 __IO uint32_t DSTS; /*!< dev Status Register (RO) 808h */
1047 uint32_t Reserved0C; /*!< Reserved 80Ch */
1048 __IO uint32_t DIEPMSK; /*!< dev IN Endpoint Mask 810h */
1049 __IO uint32_t DOEPMSK; /*!< dev OUT Endpoint Mask 814h */
1050 __IO uint32_t DAINT; /*!< dev All Endpoints Itr Reg 818h */
1051 __IO uint32_t DAINTMSK; /*!< dev All Endpoints Itr Mask 81Ch */
1052 uint32_t Reserved20; /*!< Reserved 820h */
1053 uint32_t Reserved9; /*!< Reserved 824h */
1054 __IO uint32_t DVBUSDIS; /*!< dev VBUS discharge Register 828h */
1055 __IO uint32_t DVBUSPULSE; /*!< dev VBUS Pulse Register 82Ch */
1056 __IO uint32_t DTHRCTL; /*!< dev threshold 830h */
1057 __IO uint32_t DIEPEMPMSK; /*!< dev empty msk 834h */
1058 __IO uint32_t DEACHINT; /*!< dedicated EP interrupt 838h */
1059 __IO uint32_t DEACHMSK; /*!< dedicated EP msk 83Ch */
1060 uint32_t Reserved40; /*!< dedicated EP mask 840h */
1061 __IO uint32_t DINEP1MSK; /*!< dedicated EP mask 844h */
1062 uint32_t Reserved44[15]; /*!< Reserved 844-87Ch */
1063 __IO uint32_t DOUTEP1MSK; /*!< dedicated EP msk 884h */
1064 } USB_OTG_DeviceTypeDef;
1065
1066 /**
1067 * @brief USB_OTG_IN_Endpoint-Specific_Register
1068 */
1069 typedef struct
1070 {
1071 __IO uint32_t DIEPCTL; /*!< dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h */
1072 uint32_t Reserved04; /*!< Reserved 900h + (ep_num * 20h) + 04h */
1073 __IO uint32_t DIEPINT; /*!< dev IN Endpoint Itr Reg 900h + (ep_num * 20h) + 08h */
1074 uint32_t Reserved0C; /*!< Reserved 900h + (ep_num * 20h) + 0Ch */
1075 __IO uint32_t DIEPTSIZ; /*!< IN Endpoint Txfer Size 900h + (ep_num * 20h) + 10h */
1076 __IO uint32_t DIEPDMA; /*!< IN Endpoint DMA Address Reg 900h + (ep_num * 20h) + 14h */
1077 __IO uint32_t DTXFSTS; /*!< IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h */
1078 uint32_t Reserved18; /*!< Reserved 900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch */
1079 } USB_OTG_INEndpointTypeDef;
1080
1081 /**
1082 * @brief USB_OTG_OUT_Endpoint-Specific_Registers
1083 */
1084 typedef struct
1085 {
1086 __IO uint32_t DOEPCTL; /*!< dev OUT Endpoint Control Reg B00h + (ep_num * 20h) + 00h */
1087 uint32_t Reserved04; /*!< Reserved B00h + (ep_num * 20h) + 04h */
1088 __IO uint32_t DOEPINT; /*!< dev OUT Endpoint Itr Reg B00h + (ep_num * 20h) + 08h */
1089 uint32_t Reserved0C; /*!< Reserved B00h + (ep_num * 20h) + 0Ch */
1090 __IO uint32_t DOEPTSIZ; /*!< dev OUT Endpoint Txfer Size B00h + (ep_num * 20h) + 10h */
1091 __IO uint32_t DOEPDMA; /*!< dev OUT Endpoint DMA Address B00h + (ep_num * 20h) + 14h */
1092 uint32_t Reserved18[2]; /*!< Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch */
1093 } USB_OTG_OUTEndpointTypeDef;
1094
1095 /**
1096 * @brief USB_OTG_Host_Mode_Register_Structures
1097 */
1098 typedef struct
1099 {
1100 __IO uint32_t HCFG; /*!< Host Configuration Register 400h */
1101 __IO uint32_t HFIR; /*!< Host Frame Interval Register 404h */
1102 __IO uint32_t HFNUM; /*!< Host Frame Nbr/Frame Remaining 408h */
1103 uint32_t Reserved40C; /*!< Reserved 40Ch */
1104 __IO uint32_t HPTXSTS; /*!< Host Periodic Tx FIFO/ Queue Status 410h */
1105 __IO uint32_t HAINT; /*!< Host All Channels Interrupt Register 414h */
1106 __IO uint32_t HAINTMSK; /*!< Host All Channels Interrupt Mask 418h */
1107 } USB_OTG_HostTypeDef;
1108
1109 /**
1110 * @brief USB_OTG_Host_Channel_Specific_Registers
1111 */
1112 typedef struct
1113 {
1114 __IO uint32_t HCCHAR; /*!< Host Channel Characteristics Register 500h */
1115 __IO uint32_t HCSPLT; /*!< Host Channel Split Control Register 504h */
1116 __IO uint32_t HCINT; /*!< Host Channel Interrupt Register 508h */
1117 __IO uint32_t HCINTMSK; /*!< Host Channel Interrupt Mask Register 50Ch */
1118 __IO uint32_t HCTSIZ; /*!< Host Channel Transfer Size Register 510h */
1119 __IO uint32_t HCDMA; /*!< Host Channel DMA Address Register 514h */
1120 uint32_t Reserved[2]; /*!< Reserved */
1121 } USB_OTG_HostChannelTypeDef;
1122
1123 /**
1124 * @}
1125 */
1126
1127 /** @addtogroup Peripheral_memory_map
1128 * @{
1129 */
1130 #define FLASH_BASE 0x08000000U /*!< FLASH(up to 1 MB) base address in the alias region */
1131 #define CCMDATARAM_BASE 0x10000000U /*!< CCM(core coupled memory) data RAM(64 KB) base address in the alias region */
1132 #define SRAM1_BASE 0x20000000U /*!< SRAM1(160 KB) base address in the alias region */
1133 #define SRAM2_BASE 0x20028000U /*!< SRAM2(32 KB) base address in the alias region */
1134 #define SRAM3_BASE 0x20030000U /*!< SRAM3(128 KB) base address in the alias region */
1135 #define PERIPH_BASE 0x40000000U /*!< Peripheral base address in the alias region */
1136 #define BKPSRAM_BASE 0x40024000U /*!< Backup SRAM(4 KB) base address in the alias region */
1137 #define FMC_R_BASE 0xA0000000U /*!< FMC registers base address */
1138 #define QSPI_R_BASE 0xA0001000U /*!< QuadSPI registers base address */
1139 #define SRAM1_BB_BASE 0x22000000U /*!< SRAM1(112 KB) base address in the bit-band region */
1140 #define SRAM2_BB_BASE 0x22500000U /*!< SRAM2(16 KB) base address in the bit-band region */
1141 #define SRAM3_BB_BASE 0x22600000U /*!< SRAM3(64 KB) base address in the bit-band region */
1142 #define PERIPH_BB_BASE 0x42000000U /*!< Peripheral base address in the bit-band region */
1143 #define BKPSRAM_BB_BASE 0x42480000U /*!< Backup SRAM(4 KB) base address in the bit-band region */
1144 #define FLASH_END 0x081FFFFFU /*!< FLASH end address */
1145 #define FLASH_OTP_BASE 0x1FFF7800U /*!< Base address of : (up to 528 Bytes) embedded FLASH OTP Area */
1146 #define FLASH_OTP_END 0x1FFF7A0FU /*!< End address of : (up to 528 Bytes) embedded FLASH OTP Area */
1147 #define CCMDATARAM_END 0x1000FFFFU /*!< CCM data RAM end address */
1148
1149 /* Legacy defines */
1150 #define SRAM_BASE SRAM1_BASE
1151 #define SRAM_BB_BASE SRAM1_BB_BASE
1152
1153 /*!< Peripheral memory map */
1154 #define APB1PERIPH_BASE PERIPH_BASE
1155 #define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000U)
1156 #define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000U)
1157 #define AHB2PERIPH_BASE (PERIPH_BASE + 0x10000000U)
1158
1159 /*!< APB1 peripherals */
1160 #define TIM2_BASE (APB1PERIPH_BASE + 0x0000U)
1161 #define TIM3_BASE (APB1PERIPH_BASE + 0x0400U)
1162 #define TIM4_BASE (APB1PERIPH_BASE + 0x0800U)
1163 #define TIM5_BASE (APB1PERIPH_BASE + 0x0C00U)
1164 #define TIM6_BASE (APB1PERIPH_BASE + 0x1000U)
1165 #define TIM7_BASE (APB1PERIPH_BASE + 0x1400U)
1166 #define TIM12_BASE (APB1PERIPH_BASE + 0x1800U)
1167 #define TIM13_BASE (APB1PERIPH_BASE + 0x1C00U)
1168 #define TIM14_BASE (APB1PERIPH_BASE + 0x2000U)
1169 #define RTC_BASE (APB1PERIPH_BASE + 0x2800U)
1170 #define WWDG_BASE (APB1PERIPH_BASE + 0x2C00U)
1171 #define IWDG_BASE (APB1PERIPH_BASE + 0x3000U)
1172 #define I2S2ext_BASE (APB1PERIPH_BASE + 0x3400U)
1173 #define SPI2_BASE (APB1PERIPH_BASE + 0x3800U)
1174 #define SPI3_BASE (APB1PERIPH_BASE + 0x3C00U)
1175 #define I2S3ext_BASE (APB1PERIPH_BASE + 0x4000U)
1176 #define USART2_BASE (APB1PERIPH_BASE + 0x4400U)
1177 #define USART3_BASE (APB1PERIPH_BASE + 0x4800U)
1178 #define UART4_BASE (APB1PERIPH_BASE + 0x4C00U)
1179 #define UART5_BASE (APB1PERIPH_BASE + 0x5000U)
1180 #define I2C1_BASE (APB1PERIPH_BASE + 0x5400U)
1181 #define I2C2_BASE (APB1PERIPH_BASE + 0x5800U)
1182 #define I2C3_BASE (APB1PERIPH_BASE + 0x5C00U)
1183 #define CAN1_BASE (APB1PERIPH_BASE + 0x6400U)
1184 #define CAN2_BASE (APB1PERIPH_BASE + 0x6800U)
1185 #define PWR_BASE (APB1PERIPH_BASE + 0x7000U)
1186 #define DAC_BASE (APB1PERIPH_BASE + 0x7400U)
1187 #define UART7_BASE (APB1PERIPH_BASE + 0x7800U)
1188 #define UART8_BASE (APB1PERIPH_BASE + 0x7C00U)
1189
1190 /*!< APB2 peripherals */
1191 #define TIM1_BASE (APB2PERIPH_BASE + 0x0000U)
1192 #define TIM8_BASE (APB2PERIPH_BASE + 0x0400U)
1193 #define USART1_BASE (APB2PERIPH_BASE + 0x1000U)
1194 #define USART6_BASE (APB2PERIPH_BASE + 0x1400U)
1195 #define ADC1_BASE (APB2PERIPH_BASE + 0x2000U)
1196 #define ADC2_BASE (APB2PERIPH_BASE + 0x2100U)
1197 #define ADC3_BASE (APB2PERIPH_BASE + 0x2200U)
1198 #define ADC123_COMMON_BASE (APB2PERIPH_BASE + 0x2300U)
1199 /* Legacy define */
1200 #define ADC_BASE ADC123_COMMON_BASE
1201 #define SDIO_BASE (APB2PERIPH_BASE + 0x2C00U)
1202 #define SPI1_BASE (APB2PERIPH_BASE + 0x3000U)
1203 #define SPI4_BASE (APB2PERIPH_BASE + 0x3400U)
1204 #define SYSCFG_BASE (APB2PERIPH_BASE + 0x3800U)
1205 #define EXTI_BASE (APB2PERIPH_BASE + 0x3C00U)
1206 #define TIM9_BASE (APB2PERIPH_BASE + 0x4000U)
1207 #define TIM10_BASE (APB2PERIPH_BASE + 0x4400U)
1208 #define TIM11_BASE (APB2PERIPH_BASE + 0x4800U)
1209 #define SPI5_BASE (APB2PERIPH_BASE + 0x5000U)
1210 #define SPI6_BASE (APB2PERIPH_BASE + 0x5400U)
1211 #define SAI1_BASE (APB2PERIPH_BASE + 0x5800U)
1212 #define SAI1_Block_A_BASE (SAI1_BASE + 0x004U)
1213 #define SAI1_Block_B_BASE (SAI1_BASE + 0x024U)
1214 #define LTDC_BASE (APB2PERIPH_BASE + 0x6800U)
1215 #define LTDC_Layer1_BASE (LTDC_BASE + 0x84U)
1216 #define LTDC_Layer2_BASE (LTDC_BASE + 0x104U)
1217 #define DSI_BASE (APB2PERIPH_BASE + 0x6C00U)
1218
1219 /*!< AHB1 peripherals */
1220 #define GPIOA_BASE (AHB1PERIPH_BASE + 0x0000U)
1221 #define GPIOB_BASE (AHB1PERIPH_BASE + 0x0400U)
1222 #define GPIOC_BASE (AHB1PERIPH_BASE + 0x0800U)
1223 #define GPIOD_BASE (AHB1PERIPH_BASE + 0x0C00U)
1224 #define GPIOE_BASE (AHB1PERIPH_BASE + 0x1000U)
1225 #define GPIOF_BASE (AHB1PERIPH_BASE + 0x1400U)
1226 #define GPIOG_BASE (AHB1PERIPH_BASE + 0x1800U)
1227 #define GPIOH_BASE (AHB1PERIPH_BASE + 0x1C00U)
1228 #define GPIOI_BASE (AHB1PERIPH_BASE + 0x2000U)
1229 #define GPIOJ_BASE (AHB1PERIPH_BASE + 0x2400U)
1230 #define GPIOK_BASE (AHB1PERIPH_BASE + 0x2800U)
1231 #define CRC_BASE (AHB1PERIPH_BASE + 0x3000U)
1232 #define RCC_BASE (AHB1PERIPH_BASE + 0x3800U)
1233 #define FLASH_R_BASE (AHB1PERIPH_BASE + 0x3C00U)
1234 #define DMA1_BASE (AHB1PERIPH_BASE + 0x6000U)
1235 #define DMA1_Stream0_BASE (DMA1_BASE + 0x010U)
1236 #define DMA1_Stream1_BASE (DMA1_BASE + 0x028U)
1237 #define DMA1_Stream2_BASE (DMA1_BASE + 0x040U)
1238 #define DMA1_Stream3_BASE (DMA1_BASE + 0x058U)
1239 #define DMA1_Stream4_BASE (DMA1_BASE + 0x070U)
1240 #define DMA1_Stream5_BASE (DMA1_BASE + 0x088U)
1241 #define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0U)
1242 #define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8U)
1243 #define DMA2_BASE (AHB1PERIPH_BASE + 0x6400U)
1244 #define DMA2_Stream0_BASE (DMA2_BASE + 0x010U)
1245 #define DMA2_Stream1_BASE (DMA2_BASE + 0x028U)
1246 #define DMA2_Stream2_BASE (DMA2_BASE + 0x040U)
1247 #define DMA2_Stream3_BASE (DMA2_BASE + 0x058U)
1248 #define DMA2_Stream4_BASE (DMA2_BASE + 0x070U)
1249 #define DMA2_Stream5_BASE (DMA2_BASE + 0x088U)
1250 #define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0U)
1251 #define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8U)
1252 #define ETH_BASE (AHB1PERIPH_BASE + 0x8000U)
1253 #define ETH_MAC_BASE (ETH_BASE)
1254 #define ETH_MMC_BASE (ETH_BASE + 0x0100U)
1255 #define ETH_PTP_BASE (ETH_BASE + 0x0700U)
1256 #define ETH_DMA_BASE (ETH_BASE + 0x1000U)
1257 #define DMA2D_BASE (AHB1PERIPH_BASE + 0xB000U)
1258
1259 /*!< AHB2 peripherals */
1260 #define DCMI_BASE (AHB2PERIPH_BASE + 0x50000U)
1261 #define RNG_BASE (AHB2PERIPH_BASE + 0x60800U)
1262
1263 /*!< FMC Bankx registers base address */
1264 #define FMC_Bank1_R_BASE (FMC_R_BASE + 0x0000U)
1265 #define FMC_Bank1E_R_BASE (FMC_R_BASE + 0x0104U)
1266 #define FMC_Bank3_R_BASE (FMC_R_BASE + 0x0080U)
1267 #define FMC_Bank5_6_R_BASE (FMC_R_BASE + 0x0140U)
1268
1269
1270 /*!< Debug MCU registers base address */
1271 #define DBGMCU_BASE 0xE0042000U
1272 /*!< USB registers base address */
1273 #define USB_OTG_HS_PERIPH_BASE 0x40040000U
1274 #define USB_OTG_FS_PERIPH_BASE 0x50000000U
1275
1276 #define USB_OTG_GLOBAL_BASE 0x000U
1277 #define USB_OTG_DEVICE_BASE 0x800U
1278 #define USB_OTG_IN_ENDPOINT_BASE 0x900U
1279 #define USB_OTG_OUT_ENDPOINT_BASE 0xB00U
1280 #define USB_OTG_EP_REG_SIZE 0x20U
1281 #define USB_OTG_HOST_BASE 0x400U
1282 #define USB_OTG_HOST_PORT_BASE 0x440U
1283 #define USB_OTG_HOST_CHANNEL_BASE 0x500U
1284 #define USB_OTG_HOST_CHANNEL_SIZE 0x20U
1285 #define USB_OTG_PCGCCTL_BASE 0xE00U
1286 #define USB_OTG_FIFO_BASE 0x1000U
1287 #define USB_OTG_FIFO_SIZE 0x1000U
1288
1289 #define UID_BASE 0x1FFF7A10U /*!< Unique device ID register base address */
1290 #define FLASHSIZE_BASE 0x1FFF7A22U /*!< FLASH Size register base address */
1291 #define PACKAGE_BASE 0x1FFF7BF0U /*!< Package size register base address */
1292 /**
1293 * @}
1294 */
1295
1296 /** @addtogroup Peripheral_declaration
1297 * @{
1298 */
1299 #define TIM2 ((TIM_TypeDef *) TIM2_BASE)
1300 #define TIM3 ((TIM_TypeDef *) TIM3_BASE)
1301 #define TIM4 ((TIM_TypeDef *) TIM4_BASE)
1302 #define TIM5 ((TIM_TypeDef *) TIM5_BASE)
1303 #define TIM6 ((TIM_TypeDef *) TIM6_BASE)
1304 #define TIM7 ((TIM_TypeDef *) TIM7_BASE)
1305 #define TIM12 ((TIM_TypeDef *) TIM12_BASE)
1306 #define TIM13 ((TIM_TypeDef *) TIM13_BASE)
1307 #define TIM14 ((TIM_TypeDef *) TIM14_BASE)
1308 #define RTC ((RTC_TypeDef *) RTC_BASE)
1309 #define WWDG ((WWDG_TypeDef *) WWDG_BASE)
1310 #define IWDG ((IWDG_TypeDef *) IWDG_BASE)
1311 #define I2S2ext ((SPI_TypeDef *) I2S2ext_BASE)
1312 #define SPI2 ((SPI_TypeDef *) SPI2_BASE)
1313 #define SPI3 ((SPI_TypeDef *) SPI3_BASE)
1314 #define I2S3ext ((SPI_TypeDef *) I2S3ext_BASE)
1315 #define USART2 ((USART_TypeDef *) USART2_BASE)
1316 #define USART3 ((USART_TypeDef *) USART3_BASE)
1317 #define UART4 ((USART_TypeDef *) UART4_BASE)
1318 #define UART5 ((USART_TypeDef *) UART5_BASE)
1319 #define I2C1 ((I2C_TypeDef *) I2C1_BASE)
1320 #define I2C2 ((I2C_TypeDef *) I2C2_BASE)
1321 #define I2C3 ((I2C_TypeDef *) I2C3_BASE)
1322 #define CAN1 ((CAN_TypeDef *) CAN1_BASE)
1323 #define CAN2 ((CAN_TypeDef *) CAN2_BASE)
1324 #define PWR ((PWR_TypeDef *) PWR_BASE)
1325 #define DAC1 ((DAC_TypeDef *) DAC_BASE)
1326 #define DAC ((DAC_TypeDef *) DAC_BASE) /* Kept for legacy purpose */
1327 #define UART7 ((USART_TypeDef *) UART7_BASE)
1328 #define UART8 ((USART_TypeDef *) UART8_BASE)
1329 #define TIM1 ((TIM_TypeDef *) TIM1_BASE)
1330 #define TIM8 ((TIM_TypeDef *) TIM8_BASE)
1331 #define USART1 ((USART_TypeDef *) USART1_BASE)
1332 #define USART6 ((USART_TypeDef *) USART6_BASE)
1333 #define ADC1 ((ADC_TypeDef *) ADC1_BASE)
1334 #define ADC2 ((ADC_TypeDef *) ADC2_BASE)
1335 #define ADC3 ((ADC_TypeDef *) ADC3_BASE)
1336 #define ADC123_COMMON ((ADC_Common_TypeDef *) ADC123_COMMON_BASE)
1337 /* Legacy define */
1338 #define ADC ADC123_COMMON
1339 #define SDIO ((SDIO_TypeDef *) SDIO_BASE)
1340 #define SPI1 ((SPI_TypeDef *) SPI1_BASE)
1341 #define SPI4 ((SPI_TypeDef *) SPI4_BASE)
1342 #define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
1343 #define EXTI ((EXTI_TypeDef *) EXTI_BASE)
1344 #define TIM9 ((TIM_TypeDef *) TIM9_BASE)
1345 #define TIM10 ((TIM_TypeDef *) TIM10_BASE)
1346 #define TIM11 ((TIM_TypeDef *) TIM11_BASE)
1347 #define SPI5 ((SPI_TypeDef *) SPI5_BASE)
1348 #define SPI6 ((SPI_TypeDef *) SPI6_BASE)
1349 #define SAI1 ((SAI_TypeDef *) SAI1_BASE)
1350 #define SAI1_Block_A ((SAI_Block_TypeDef *)SAI1_Block_A_BASE)
1351 #define SAI1_Block_B ((SAI_Block_TypeDef *)SAI1_Block_B_BASE)
1352 #define LTDC ((LTDC_TypeDef *)LTDC_BASE)
1353 #define LTDC_Layer1 ((LTDC_Layer_TypeDef *)LTDC_Layer1_BASE)
1354 #define LTDC_Layer2 ((LTDC_Layer_TypeDef *)LTDC_Layer2_BASE)
1355 #define DSI ((DSI_TypeDef *)DSI_BASE)
1356 #define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
1357 #define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
1358 #define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
1359 #define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
1360 #define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
1361 #define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
1362 #define GPIOG ((GPIO_TypeDef *) GPIOG_BASE)
1363 #define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)
1364 #define GPIOI ((GPIO_TypeDef *) GPIOI_BASE)
1365 #define GPIOJ ((GPIO_TypeDef *) GPIOJ_BASE)
1366 #define GPIOK ((GPIO_TypeDef *) GPIOK_BASE)
1367 #define CRC ((CRC_TypeDef *) CRC_BASE)
1368 #define RCC ((RCC_TypeDef *) RCC_BASE)
1369 #define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
1370 #define DMA1 ((DMA_TypeDef *) DMA1_BASE)
1371 #define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)
1372 #define DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)
1373 #define DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)
1374 #define DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)
1375 #define DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)
1376 #define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)
1377 #define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)
1378 #define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)
1379 #define DMA2 ((DMA_TypeDef *) DMA2_BASE)
1380 #define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)
1381 #define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)
1382 #define DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)
1383 #define DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)
1384 #define DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)
1385 #define DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)
1386 #define DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)
1387 #define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)
1388 #define ETH ((ETH_TypeDef *) ETH_BASE)
1389 #define DMA2D ((DMA2D_TypeDef *)DMA2D_BASE)
1390 #define DCMI ((DCMI_TypeDef *) DCMI_BASE)
1391 #define RNG ((RNG_TypeDef *) RNG_BASE)
1392 #define FMC_Bank1 ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE)
1393 #define FMC_Bank1E ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE)
1394 #define FMC_Bank3 ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE)
1395 #define FMC_Bank5_6 ((FMC_Bank5_6_TypeDef *) FMC_Bank5_6_R_BASE)
1396 #define QUADSPI ((QUADSPI_TypeDef *) QSPI_R_BASE)
1397 #define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
1398 #define USB_OTG_FS ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_PERIPH_BASE)
1399 #define USB_OTG_HS ((USB_OTG_GlobalTypeDef *) USB_OTG_HS_PERIPH_BASE)
1400
1401 /**
1402 * @}
1403 */
1404
1405 /** @addtogroup Exported_constants
1406 * @{
1407 */
1408
1409 /** @addtogroup Peripheral_Registers_Bits_Definition
1410 * @{
1411 */
1412
1413 /******************************************************************************/
1414 /* Peripheral Registers_Bits_Definition */
1415 /******************************************************************************/
1416
1417 /******************************************************************************/
1418 /* */
1419 /* Analog to Digital Converter */
1420 /* */
1421 /******************************************************************************/
1422 /*
1423 * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
1424 */
1425 #define ADC_MULTIMODE_SUPPORT /*!<ADC Multimode feature available on specific devices */
1426
1427 /******************** Bit definition for ADC_SR register ********************/
1428 #define ADC_SR_AWD_Pos (0U)
1429 #define ADC_SR_AWD_Msk (0x1U << ADC_SR_AWD_Pos) /*!< 0x00000001 */
1430 #define ADC_SR_AWD ADC_SR_AWD_Msk /*!<Analog watchdog flag */
1431 #define ADC_SR_EOC_Pos (1U)
1432 #define ADC_SR_EOC_Msk (0x1U << ADC_SR_EOC_Pos) /*!< 0x00000002 */
1433 #define ADC_SR_EOC ADC_SR_EOC_Msk /*!<End of conversion */
1434 #define ADC_SR_JEOC_Pos (2U)
1435 #define ADC_SR_JEOC_Msk (0x1U << ADC_SR_JEOC_Pos) /*!< 0x00000004 */
1436 #define ADC_SR_JEOC ADC_SR_JEOC_Msk /*!<Injected channel end of conversion */
1437 #define ADC_SR_JSTRT_Pos (3U)
1438 #define ADC_SR_JSTRT_Msk (0x1U << ADC_SR_JSTRT_Pos) /*!< 0x00000008 */
1439 #define ADC_SR_JSTRT ADC_SR_JSTRT_Msk /*!<Injected channel Start flag */
1440 #define ADC_SR_STRT_Pos (4U)
1441 #define ADC_SR_STRT_Msk (0x1U << ADC_SR_STRT_Pos) /*!< 0x00000010 */
1442 #define ADC_SR_STRT ADC_SR_STRT_Msk /*!<Regular channel Start flag */
1443 #define ADC_SR_OVR_Pos (5U)
1444 #define ADC_SR_OVR_Msk (0x1U << ADC_SR_OVR_Pos) /*!< 0x00000020 */
1445 #define ADC_SR_OVR ADC_SR_OVR_Msk /*!<Overrun flag */
1446
1447 /******************* Bit definition for ADC_CR1 register ********************/
1448 #define ADC_CR1_AWDCH_Pos (0U)
1449 #define ADC_CR1_AWDCH_Msk (0x1FU << ADC_CR1_AWDCH_Pos) /*!< 0x0000001F */
1450 #define ADC_CR1_AWDCH ADC_CR1_AWDCH_Msk /*!<AWDCH[4:0] bits (Analog watchdog channel select bits) */
1451 #define ADC_CR1_AWDCH_0 (0x01U << ADC_CR1_AWDCH_Pos) /*!< 0x00000001 */
1452 #define ADC_CR1_AWDCH_1 (0x02U << ADC_CR1_AWDCH_Pos) /*!< 0x00000002 */
1453 #define ADC_CR1_AWDCH_2 (0x04U << ADC_CR1_AWDCH_Pos) /*!< 0x00000004 */
1454 #define ADC_CR1_AWDCH_3 (0x08U << ADC_CR1_AWDCH_Pos) /*!< 0x00000008 */
1455 #define ADC_CR1_AWDCH_4 (0x10U << ADC_CR1_AWDCH_Pos) /*!< 0x00000010 */
1456 #define ADC_CR1_EOCIE_Pos (5U)
1457 #define ADC_CR1_EOCIE_Msk (0x1U << ADC_CR1_EOCIE_Pos) /*!< 0x00000020 */
1458 #define ADC_CR1_EOCIE ADC_CR1_EOCIE_Msk /*!<Interrupt enable for EOC */
1459 #define ADC_CR1_AWDIE_Pos (6U)
1460 #define ADC_CR1_AWDIE_Msk (0x1U << ADC_CR1_AWDIE_Pos) /*!< 0x00000040 */
1461 #define ADC_CR1_AWDIE ADC_CR1_AWDIE_Msk /*!<AAnalog Watchdog interrupt enable */
1462 #define ADC_CR1_JEOCIE_Pos (7U)
1463 #define ADC_CR1_JEOCIE_Msk (0x1U << ADC_CR1_JEOCIE_Pos) /*!< 0x00000080 */
1464 #define ADC_CR1_JEOCIE ADC_CR1_JEOCIE_Msk /*!<Interrupt enable for injected channels */
1465 #define ADC_CR1_SCAN_Pos (8U)
1466 #define ADC_CR1_SCAN_Msk (0x1U << ADC_CR1_SCAN_Pos) /*!< 0x00000100 */
1467 #define ADC_CR1_SCAN ADC_CR1_SCAN_Msk /*!<Scan mode */
1468 #define ADC_CR1_AWDSGL_Pos (9U)
1469 #define ADC_CR1_AWDSGL_Msk (0x1U << ADC_CR1_AWDSGL_Pos) /*!< 0x00000200 */
1470 #define ADC_CR1_AWDSGL ADC_CR1_AWDSGL_Msk /*!<Enable the watchdog on a single channel in scan mode */
1471 #define ADC_CR1_JAUTO_Pos (10U)
1472 #define ADC_CR1_JAUTO_Msk (0x1U << ADC_CR1_JAUTO_Pos) /*!< 0x00000400 */
1473 #define ADC_CR1_JAUTO ADC_CR1_JAUTO_Msk /*!<Automatic injected group conversion */
1474 #define ADC_CR1_DISCEN_Pos (11U)
1475 #define ADC_CR1_DISCEN_Msk (0x1U << ADC_CR1_DISCEN_Pos) /*!< 0x00000800 */
1476 #define ADC_CR1_DISCEN ADC_CR1_DISCEN_Msk /*!<Discontinuous mode on regular channels */
1477 #define ADC_CR1_JDISCEN_Pos (12U)
1478 #define ADC_CR1_JDISCEN_Msk (0x1U << ADC_CR1_JDISCEN_Pos) /*!< 0x00001000 */
1479 #define ADC_CR1_JDISCEN ADC_CR1_JDISCEN_Msk /*!<Discontinuous mode on injected channels */
1480 #define ADC_CR1_DISCNUM_Pos (13U)
1481 #define ADC_CR1_DISCNUM_Msk (0x7U << ADC_CR1_DISCNUM_Pos) /*!< 0x0000E000 */
1482 #define ADC_CR1_DISCNUM ADC_CR1_DISCNUM_Msk /*!<DISCNUM[2:0] bits (Discontinuous mode channel count) */
1483 #define ADC_CR1_DISCNUM_0 (0x1U << ADC_CR1_DISCNUM_Pos) /*!< 0x00002000 */
1484 #define ADC_CR1_DISCNUM_1 (0x2U << ADC_CR1_DISCNUM_Pos) /*!< 0x00004000 */
1485 #define ADC_CR1_DISCNUM_2 (0x4U << ADC_CR1_DISCNUM_Pos) /*!< 0x00008000 */
1486 #define ADC_CR1_JAWDEN_Pos (22U)
1487 #define ADC_CR1_JAWDEN_Msk (0x1U << ADC_CR1_JAWDEN_Pos) /*!< 0x00400000 */
1488 #define ADC_CR1_JAWDEN ADC_CR1_JAWDEN_Msk /*!<Analog watchdog enable on injected channels */
1489 #define ADC_CR1_AWDEN_Pos (23U)
1490 #define ADC_CR1_AWDEN_Msk (0x1U << ADC_CR1_AWDEN_Pos) /*!< 0x00800000 */
1491 #define ADC_CR1_AWDEN ADC_CR1_AWDEN_Msk /*!<Analog watchdog enable on regular channels */
1492 #define ADC_CR1_RES_Pos (24U)
1493 #define ADC_CR1_RES_Msk (0x3U << ADC_CR1_RES_Pos) /*!< 0x03000000 */
1494 #define ADC_CR1_RES ADC_CR1_RES_Msk /*!<RES[2:0] bits (Resolution) */
1495 #define ADC_CR1_RES_0 (0x1U << ADC_CR1_RES_Pos) /*!< 0x01000000 */
1496 #define ADC_CR1_RES_1 (0x2U << ADC_CR1_RES_Pos) /*!< 0x02000000 */
1497 #define ADC_CR1_OVRIE_Pos (26U)
1498 #define ADC_CR1_OVRIE_Msk (0x1U << ADC_CR1_OVRIE_Pos) /*!< 0x04000000 */
1499 #define ADC_CR1_OVRIE ADC_CR1_OVRIE_Msk /*!<overrun interrupt enable */
1500
1501 /******************* Bit definition for ADC_CR2 register ********************/
1502 #define ADC_CR2_ADON_Pos (0U)
1503 #define ADC_CR2_ADON_Msk (0x1U << ADC_CR2_ADON_Pos) /*!< 0x00000001 */
1504 #define ADC_CR2_ADON ADC_CR2_ADON_Msk /*!<A/D Converter ON / OFF */
1505 #define ADC_CR2_CONT_Pos (1U)
1506 #define ADC_CR2_CONT_Msk (0x1U << ADC_CR2_CONT_Pos) /*!< 0x00000002 */
1507 #define ADC_CR2_CONT ADC_CR2_CONT_Msk /*!<Continuous Conversion */
1508 #define ADC_CR2_DMA_Pos (8U)
1509 #define ADC_CR2_DMA_Msk (0x1U << ADC_CR2_DMA_Pos) /*!< 0x00000100 */
1510 #define ADC_CR2_DMA ADC_CR2_DMA_Msk /*!<Direct Memory access mode */
1511 #define ADC_CR2_DDS_Pos (9U)
1512 #define ADC_CR2_DDS_Msk (0x1U << ADC_CR2_DDS_Pos) /*!< 0x00000200 */
1513 #define ADC_CR2_DDS ADC_CR2_DDS_Msk /*!<DMA disable selection (Single ADC) */
1514 #define ADC_CR2_EOCS_Pos (10U)
1515 #define ADC_CR2_EOCS_Msk (0x1U << ADC_CR2_EOCS_Pos) /*!< 0x00000400 */
1516 #define ADC_CR2_EOCS ADC_CR2_EOCS_Msk /*!<End of conversion selection */
1517 #define ADC_CR2_ALIGN_Pos (11U)
1518 #define ADC_CR2_ALIGN_Msk (0x1U << ADC_CR2_ALIGN_Pos) /*!< 0x00000800 */
1519 #define ADC_CR2_ALIGN ADC_CR2_ALIGN_Msk /*!<Data Alignment */
1520 #define ADC_CR2_JEXTSEL_Pos (16U)
1521 #define ADC_CR2_JEXTSEL_Msk (0xFU << ADC_CR2_JEXTSEL_Pos) /*!< 0x000F0000 */
1522 #define ADC_CR2_JEXTSEL ADC_CR2_JEXTSEL_Msk /*!<JEXTSEL[3:0] bits (External event select for injected group) */
1523 #define ADC_CR2_JEXTSEL_0 (0x1U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00010000 */
1524 #define ADC_CR2_JEXTSEL_1 (0x2U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00020000 */
1525 #define ADC_CR2_JEXTSEL_2 (0x4U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00040000 */
1526 #define ADC_CR2_JEXTSEL_3 (0x8U << ADC_CR2_JEXTSEL_Pos) /*!< 0x00080000 */
1527 #define ADC_CR2_JEXTEN_Pos (20U)
1528 #define ADC_CR2_JEXTEN_Msk (0x3U << ADC_CR2_JEXTEN_Pos) /*!< 0x00300000 */
1529 #define ADC_CR2_JEXTEN ADC_CR2_JEXTEN_Msk /*!<JEXTEN[1:0] bits (External Trigger Conversion mode for injected channelsp) */
1530 #define ADC_CR2_JEXTEN_0 (0x1U << ADC_CR2_JEXTEN_Pos) /*!< 0x00100000 */
1531 #define ADC_CR2_JEXTEN_1 (0x2U << ADC_CR2_JEXTEN_Pos) /*!< 0x00200000 */
1532 #define ADC_CR2_JSWSTART_Pos (22U)
1533 #define ADC_CR2_JSWSTART_Msk (0x1U << ADC_CR2_JSWSTART_Pos) /*!< 0x00400000 */
1534 #define ADC_CR2_JSWSTART ADC_CR2_JSWSTART_Msk /*!<Start Conversion of injected channels */
1535 #define ADC_CR2_EXTSEL_Pos (24U)
1536 #define ADC_CR2_EXTSEL_Msk (0xFU << ADC_CR2_EXTSEL_Pos) /*!< 0x0F000000 */
1537 #define ADC_CR2_EXTSEL ADC_CR2_EXTSEL_Msk /*!<EXTSEL[3:0] bits (External Event Select for regular group) */
1538 #define ADC_CR2_EXTSEL_0 (0x1U << ADC_CR2_EXTSEL_Pos) /*!< 0x01000000 */
1539 #define ADC_CR2_EXTSEL_1 (0x2U << ADC_CR2_EXTSEL_Pos) /*!< 0x02000000 */
1540 #define ADC_CR2_EXTSEL_2 (0x4U << ADC_CR2_EXTSEL_Pos) /*!< 0x04000000 */
1541 #define ADC_CR2_EXTSEL_3 (0x8U << ADC_CR2_EXTSEL_Pos) /*!< 0x08000000 */
1542 #define ADC_CR2_EXTEN_Pos (28U)
1543 #define ADC_CR2_EXTEN_Msk (0x3U << ADC_CR2_EXTEN_Pos) /*!< 0x30000000 */
1544 #define ADC_CR2_EXTEN ADC_CR2_EXTEN_Msk /*!<EXTEN[1:0] bits (External Trigger Conversion mode for regular channelsp) */
1545 #define ADC_CR2_EXTEN_0 (0x1U << ADC_CR2_EXTEN_Pos) /*!< 0x10000000 */
1546 #define ADC_CR2_EXTEN_1 (0x2U << ADC_CR2_EXTEN_Pos) /*!< 0x20000000 */
1547 #define ADC_CR2_SWSTART_Pos (30U)
1548 #define ADC_CR2_SWSTART_Msk (0x1U << ADC_CR2_SWSTART_Pos) /*!< 0x40000000 */
1549 #define ADC_CR2_SWSTART ADC_CR2_SWSTART_Msk /*!<Start Conversion of regular channels */
1550
1551 /****************** Bit definition for ADC_SMPR1 register *******************/
1552 #define ADC_SMPR1_SMP10_Pos (0U)
1553 #define ADC_SMPR1_SMP10_Msk (0x7U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000007 */
1554 #define ADC_SMPR1_SMP10 ADC_SMPR1_SMP10_Msk /*!<SMP10[2:0] bits (Channel 10 Sample time selection) */
1555 #define ADC_SMPR1_SMP10_0 (0x1U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000001 */
1556 #define ADC_SMPR1_SMP10_1 (0x2U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000002 */
1557 #define ADC_SMPR1_SMP10_2 (0x4U << ADC_SMPR1_SMP10_Pos) /*!< 0x00000004 */
1558 #define ADC_SMPR1_SMP11_Pos (3U)
1559 #define ADC_SMPR1_SMP11_Msk (0x7U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000038 */
1560 #define ADC_SMPR1_SMP11 ADC_SMPR1_SMP11_Msk /*!<SMP11[2:0] bits (Channel 11 Sample time selection) */
1561 #define ADC_SMPR1_SMP11_0 (0x1U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000008 */
1562 #define ADC_SMPR1_SMP11_1 (0x2U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000010 */
1563 #define ADC_SMPR1_SMP11_2 (0x4U << ADC_SMPR1_SMP11_Pos) /*!< 0x00000020 */
1564 #define ADC_SMPR1_SMP12_Pos (6U)
1565 #define ADC_SMPR1_SMP12_Msk (0x7U << ADC_SMPR1_SMP12_Pos) /*!< 0x000001C0 */
1566 #define ADC_SMPR1_SMP12 ADC_SMPR1_SMP12_Msk /*!<SMP12[2:0] bits (Channel 12 Sample time selection) */
1567 #define ADC_SMPR1_SMP12_0 (0x1U << ADC_SMPR1_SMP12_Pos) /*!< 0x00000040 */
1568 #define ADC_SMPR1_SMP12_1 (0x2U << ADC_SMPR1_SMP12_Pos) /*!< 0x00000080 */
1569 #define ADC_SMPR1_SMP12_2 (0x4U << ADC_SMPR1_SMP12_Pos) /*!< 0x00000100 */
1570 #define ADC_SMPR1_SMP13_Pos (9U)
1571 #define ADC_SMPR1_SMP13_Msk (0x7U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000E00 */
1572 #define ADC_SMPR1_SMP13 ADC_SMPR1_SMP13_Msk /*!<SMP13[2:0] bits (Channel 13 Sample time selection) */
1573 #define ADC_SMPR1_SMP13_0 (0x1U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000200 */
1574 #define ADC_SMPR1_SMP13_1 (0x2U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000400 */
1575 #define ADC_SMPR1_SMP13_2 (0x4U << ADC_SMPR1_SMP13_Pos) /*!< 0x00000800 */
1576 #define ADC_SMPR1_SMP14_Pos (12U)
1577 #define ADC_SMPR1_SMP14_Msk (0x7U << ADC_SMPR1_SMP14_Pos) /*!< 0x00007000 */
1578 #define ADC_SMPR1_SMP14 ADC_SMPR1_SMP14_Msk /*!<SMP14[2:0] bits (Channel 14 Sample time selection) */
1579 #define ADC_SMPR1_SMP14_0 (0x1U << ADC_SMPR1_SMP14_Pos) /*!< 0x00001000 */
1580 #define ADC_SMPR1_SMP14_1 (0x2U << ADC_SMPR1_SMP14_Pos) /*!< 0x00002000 */
1581 #define ADC_SMPR1_SMP14_2 (0x4U << ADC_SMPR1_SMP14_Pos) /*!< 0x00004000 */
1582 #define ADC_SMPR1_SMP15_Pos (15U)
1583 #define ADC_SMPR1_SMP15_Msk (0x7U << ADC_SMPR1_SMP15_Pos) /*!< 0x00038000 */
1584 #define ADC_SMPR1_SMP15 ADC_SMPR1_SMP15_Msk /*!<SMP15[2:0] bits (Channel 15 Sample time selection) */
1585 #define ADC_SMPR1_SMP15_0 (0x1U << ADC_SMPR1_SMP15_Pos) /*!< 0x00008000 */
1586 #define ADC_SMPR1_SMP15_1 (0x2U << ADC_SMPR1_SMP15_Pos) /*!< 0x00010000 */
1587 #define ADC_SMPR1_SMP15_2 (0x4U << ADC_SMPR1_SMP15_Pos) /*!< 0x00020000 */
1588 #define ADC_SMPR1_SMP16_Pos (18U)
1589 #define ADC_SMPR1_SMP16_Msk (0x7U << ADC_SMPR1_SMP16_Pos) /*!< 0x001C0000 */
1590 #define ADC_SMPR1_SMP16 ADC_SMPR1_SMP16_Msk /*!<SMP16[2:0] bits (Channel 16 Sample time selection) */
1591 #define ADC_SMPR1_SMP16_0 (0x1U << ADC_SMPR1_SMP16_Pos) /*!< 0x00040000 */
1592 #define ADC_SMPR1_SMP16_1 (0x2U << ADC_SMPR1_SMP16_Pos) /*!< 0x00080000 */
1593 #define ADC_SMPR1_SMP16_2 (0x4U << ADC_SMPR1_SMP16_Pos) /*!< 0x00100000 */
1594 #define ADC_SMPR1_SMP17_Pos (21U)
1595 #define ADC_SMPR1_SMP17_Msk (0x7U << ADC_SMPR1_SMP17_Pos) /*!< 0x00E00000 */
1596 #define ADC_SMPR1_SMP17 ADC_SMPR1_SMP17_Msk /*!<SMP17[2:0] bits (Channel 17 Sample time selection) */
1597 #define ADC_SMPR1_SMP17_0 (0x1U << ADC_SMPR1_SMP17_Pos) /*!< 0x00200000 */
1598 #define ADC_SMPR1_SMP17_1 (0x2U << ADC_SMPR1_SMP17_Pos) /*!< 0x00400000 */
1599 #define ADC_SMPR1_SMP17_2 (0x4U << ADC_SMPR1_SMP17_Pos) /*!< 0x00800000 */
1600 #define ADC_SMPR1_SMP18_Pos (24U)
1601 #define ADC_SMPR1_SMP18_Msk (0x7U << ADC_SMPR1_SMP18_Pos) /*!< 0x07000000 */
1602 #define ADC_SMPR1_SMP18 ADC_SMPR1_SMP18_Msk /*!<SMP18[2:0] bits (Channel 18 Sample time selection) */
1603 #define ADC_SMPR1_SMP18_0 (0x1U << ADC_SMPR1_SMP18_Pos) /*!< 0x01000000 */
1604 #define ADC_SMPR1_SMP18_1 (0x2U << ADC_SMPR1_SMP18_Pos) /*!< 0x02000000 */
1605 #define ADC_SMPR1_SMP18_2 (0x4U << ADC_SMPR1_SMP18_Pos) /*!< 0x04000000 */
1606
1607 /****************** Bit definition for ADC_SMPR2 register *******************/
1608 #define ADC_SMPR2_SMP0_Pos (0U)
1609 #define ADC_SMPR2_SMP0_Msk (0x7U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000007 */
1610 #define ADC_SMPR2_SMP0 ADC_SMPR2_SMP0_Msk /*!<SMP0[2:0] bits (Channel 0 Sample time selection) */
1611 #define ADC_SMPR2_SMP0_0 (0x1U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000001 */
1612 #define ADC_SMPR2_SMP0_1 (0x2U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000002 */
1613 #define ADC_SMPR2_SMP0_2 (0x4U << ADC_SMPR2_SMP0_Pos) /*!< 0x00000004 */
1614 #define ADC_SMPR2_SMP1_Pos (3U)
1615 #define ADC_SMPR2_SMP1_Msk (0x7U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000038 */
1616 #define ADC_SMPR2_SMP1 ADC_SMPR2_SMP1_Msk /*!<SMP1[2:0] bits (Channel 1 Sample time selection) */
1617 #define ADC_SMPR2_SMP1_0 (0x1U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000008 */
1618 #define ADC_SMPR2_SMP1_1 (0x2U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000010 */
1619 #define ADC_SMPR2_SMP1_2 (0x4U << ADC_SMPR2_SMP1_Pos) /*!< 0x00000020 */
1620 #define ADC_SMPR2_SMP2_Pos (6U)
1621 #define ADC_SMPR2_SMP2_Msk (0x7U << ADC_SMPR2_SMP2_Pos) /*!< 0x000001C0 */
1622 #define ADC_SMPR2_SMP2 ADC_SMPR2_SMP2_Msk /*!<SMP2[2:0] bits (Channel 2 Sample time selection) */
1623 #define ADC_SMPR2_SMP2_0 (0x1U << ADC_SMPR2_SMP2_Pos) /*!< 0x00000040 */
1624 #define ADC_SMPR2_SMP2_1 (0x2U << ADC_SMPR2_SMP2_Pos) /*!< 0x00000080 */
1625 #define ADC_SMPR2_SMP2_2 (0x4U << ADC_SMPR2_SMP2_Pos) /*!< 0x00000100 */
1626 #define ADC_SMPR2_SMP3_Pos (9U)
1627 #define ADC_SMPR2_SMP3_Msk (0x7U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000E00 */
1628 #define ADC_SMPR2_SMP3 ADC_SMPR2_SMP3_Msk /*!<SMP3[2:0] bits (Channel 3 Sample time selection) */
1629 #define ADC_SMPR2_SMP3_0 (0x1U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000200 */
1630 #define ADC_SMPR2_SMP3_1 (0x2U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000400 */
1631 #define ADC_SMPR2_SMP3_2 (0x4U << ADC_SMPR2_SMP3_Pos) /*!< 0x00000800 */
1632 #define ADC_SMPR2_SMP4_Pos (12U)
1633 #define ADC_SMPR2_SMP4_Msk (0x7U << ADC_SMPR2_SMP4_Pos) /*!< 0x00007000 */
1634 #define ADC_SMPR2_SMP4 ADC_SMPR2_SMP4_Msk /*!<SMP4[2:0] bits (Channel 4 Sample time selection) */
1635 #define ADC_SMPR2_SMP4_0 (0x1U << ADC_SMPR2_SMP4_Pos) /*!< 0x00001000 */
1636 #define ADC_SMPR2_SMP4_1 (0x2U << ADC_SMPR2_SMP4_Pos) /*!< 0x00002000 */
1637 #define ADC_SMPR2_SMP4_2 (0x4U << ADC_SMPR2_SMP4_Pos) /*!< 0x00004000 */
1638 #define ADC_SMPR2_SMP5_Pos (15U)
1639 #define ADC_SMPR2_SMP5_Msk (0x7U << ADC_SMPR2_SMP5_Pos) /*!< 0x00038000 */
1640 #define ADC_SMPR2_SMP5 ADC_SMPR2_SMP5_Msk /*!<SMP5[2:0] bits (Channel 5 Sample time selection) */
1641 #define ADC_SMPR2_SMP5_0 (0x1U << ADC_SMPR2_SMP5_Pos) /*!< 0x00008000 */
1642 #define ADC_SMPR2_SMP5_1 (0x2U << ADC_SMPR2_SMP5_Pos) /*!< 0x00010000 */
1643 #define ADC_SMPR2_SMP5_2 (0x4U << ADC_SMPR2_SMP5_Pos) /*!< 0x00020000 */
1644 #define ADC_SMPR2_SMP6_Pos (18U)
1645 #define ADC_SMPR2_SMP6_Msk (0x7U << ADC_SMPR2_SMP6_Pos) /*!< 0x001C0000 */
1646 #define ADC_SMPR2_SMP6 ADC_SMPR2_SMP6_Msk /*!<SMP6[2:0] bits (Channel 6 Sample time selection) */
1647 #define ADC_SMPR2_SMP6_0 (0x1U << ADC_SMPR2_SMP6_Pos) /*!< 0x00040000 */
1648 #define ADC_SMPR2_SMP6_1 (0x2U << ADC_SMPR2_SMP6_Pos) /*!< 0x00080000 */
1649 #define ADC_SMPR2_SMP6_2 (0x4U << ADC_SMPR2_SMP6_Pos) /*!< 0x00100000 */
1650 #define ADC_SMPR2_SMP7_Pos (21U)
1651 #define ADC_SMPR2_SMP7_Msk (0x7U << ADC_SMPR2_SMP7_Pos) /*!< 0x00E00000 */
1652 #define ADC_SMPR2_SMP7 ADC_SMPR2_SMP7_Msk /*!<SMP7[2:0] bits (Channel 7 Sample time selection) */
1653 #define ADC_SMPR2_SMP7_0 (0x1U << ADC_SMPR2_SMP7_Pos) /*!< 0x00200000 */
1654 #define ADC_SMPR2_SMP7_1 (0x2U << ADC_SMPR2_SMP7_Pos) /*!< 0x00400000 */
1655 #define ADC_SMPR2_SMP7_2 (0x4U << ADC_SMPR2_SMP7_Pos) /*!< 0x00800000 */
1656 #define ADC_SMPR2_SMP8_Pos (24U)
1657 #define ADC_SMPR2_SMP8_Msk (0x7U << ADC_SMPR2_SMP8_Pos) /*!< 0x07000000 */
1658 #define ADC_SMPR2_SMP8 ADC_SMPR2_SMP8_Msk /*!<SMP8[2:0] bits (Channel 8 Sample time selection) */
1659 #define ADC_SMPR2_SMP8_0 (0x1U << ADC_SMPR2_SMP8_Pos) /*!< 0x01000000 */
1660 #define ADC_SMPR2_SMP8_1 (0x2U << ADC_SMPR2_SMP8_Pos) /*!< 0x02000000 */
1661 #define ADC_SMPR2_SMP8_2 (0x4U << ADC_SMPR2_SMP8_Pos) /*!< 0x04000000 */
1662 #define ADC_SMPR2_SMP9_Pos (27U)
1663 #define ADC_SMPR2_SMP9_Msk (0x7U << ADC_SMPR2_SMP9_Pos) /*!< 0x38000000 */
1664 #define ADC_SMPR2_SMP9 ADC_SMPR2_SMP9_Msk /*!<SMP9[2:0] bits (Channel 9 Sample time selection) */
1665 #define ADC_SMPR2_SMP9_0 (0x1U << ADC_SMPR2_SMP9_Pos) /*!< 0x08000000 */
1666 #define ADC_SMPR2_SMP9_1 (0x2U << ADC_SMPR2_SMP9_Pos) /*!< 0x10000000 */
1667 #define ADC_SMPR2_SMP9_2 (0x4U << ADC_SMPR2_SMP9_Pos) /*!< 0x20000000 */
1668
1669 /****************** Bit definition for ADC_JOFR1 register *******************/
1670 #define ADC_JOFR1_JOFFSET1_Pos (0U)
1671 #define ADC_JOFR1_JOFFSET1_Msk (0xFFFU << ADC_JOFR1_JOFFSET1_Pos) /*!< 0x00000FFF */
1672 #define ADC_JOFR1_JOFFSET1 ADC_JOFR1_JOFFSET1_Msk /*!<Data offset for injected channel 1 */
1673
1674 /****************** Bit definition for ADC_JOFR2 register *******************/
1675 #define ADC_JOFR2_JOFFSET2_Pos (0U)
1676 #define ADC_JOFR2_JOFFSET2_Msk (0xFFFU << ADC_JOFR2_JOFFSET2_Pos) /*!< 0x00000FFF */
1677 #define ADC_JOFR2_JOFFSET2 ADC_JOFR2_JOFFSET2_Msk /*!<Data offset for injected channel 2 */
1678
1679 /****************** Bit definition for ADC_JOFR3 register *******************/
1680 #define ADC_JOFR3_JOFFSET3_Pos (0U)
1681 #define ADC_JOFR3_JOFFSET3_Msk (0xFFFU << ADC_JOFR3_JOFFSET3_Pos) /*!< 0x00000FFF */
1682 #define ADC_JOFR3_JOFFSET3 ADC_JOFR3_JOFFSET3_Msk /*!<Data offset for injected channel 3 */
1683
1684 /****************** Bit definition for ADC_JOFR4 register *******************/
1685 #define ADC_JOFR4_JOFFSET4_Pos (0U)
1686 #define ADC_JOFR4_JOFFSET4_Msk (0xFFFU << ADC_JOFR4_JOFFSET4_Pos) /*!< 0x00000FFF */
1687 #define ADC_JOFR4_JOFFSET4 ADC_JOFR4_JOFFSET4_Msk /*!<Data offset for injected channel 4 */
1688
1689 /******************* Bit definition for ADC_HTR register ********************/
1690 #define ADC_HTR_HT_Pos (0U)
1691 #define ADC_HTR_HT_Msk (0xFFFU << ADC_HTR_HT_Pos) /*!< 0x00000FFF */
1692 #define ADC_HTR_HT ADC_HTR_HT_Msk /*!<Analog watchdog high threshold */
1693
1694 /******************* Bit definition for ADC_LTR register ********************/
1695 #define ADC_LTR_LT_Pos (0U)
1696 #define ADC_LTR_LT_Msk (0xFFFU << ADC_LTR_LT_Pos) /*!< 0x00000FFF */
1697 #define ADC_LTR_LT ADC_LTR_LT_Msk /*!<Analog watchdog low threshold */
1698
1699 /******************* Bit definition for ADC_SQR1 register *******************/
1700 #define ADC_SQR1_SQ13_Pos (0U)
1701 #define ADC_SQR1_SQ13_Msk (0x1FU << ADC_SQR1_SQ13_Pos) /*!< 0x0000001F */
1702 #define ADC_SQR1_SQ13 ADC_SQR1_SQ13_Msk /*!<SQ13[4:0] bits (13th conversion in regular sequence) */
1703 #define ADC_SQR1_SQ13_0 (0x01U << ADC_SQR1_SQ13_Pos) /*!< 0x00000001 */
1704 #define ADC_SQR1_SQ13_1 (0x02U << ADC_SQR1_SQ13_Pos) /*!< 0x00000002 */
1705 #define ADC_SQR1_SQ13_2 (0x04U << ADC_SQR1_SQ13_Pos) /*!< 0x00000004 */
1706 #define ADC_SQR1_SQ13_3 (0x08U << ADC_SQR1_SQ13_Pos) /*!< 0x00000008 */
1707 #define ADC_SQR1_SQ13_4 (0x10U << ADC_SQR1_SQ13_Pos) /*!< 0x00000010 */
1708 #define ADC_SQR1_SQ14_Pos (5U)
1709 #define ADC_SQR1_SQ14_Msk (0x1FU << ADC_SQR1_SQ14_Pos) /*!< 0x000003E0 */
1710 #define ADC_SQR1_SQ14 ADC_SQR1_SQ14_Msk /*!<SQ14[4:0] bits (14th conversion in regular sequence) */
1711 #define ADC_SQR1_SQ14_0 (0x01U << ADC_SQR1_SQ14_Pos) /*!< 0x00000020 */
1712 #define ADC_SQR1_SQ14_1 (0x02U << ADC_SQR1_SQ14_Pos) /*!< 0x00000040 */
1713 #define ADC_SQR1_SQ14_2 (0x04U << ADC_SQR1_SQ14_Pos) /*!< 0x00000080 */
1714 #define ADC_SQR1_SQ14_3 (0x08U << ADC_SQR1_SQ14_Pos) /*!< 0x00000100 */
1715 #define ADC_SQR1_SQ14_4 (0x10U << ADC_SQR1_SQ14_Pos) /*!< 0x00000200 */
1716 #define ADC_SQR1_SQ15_Pos (10U)
1717 #define ADC_SQR1_SQ15_Msk (0x1FU << ADC_SQR1_SQ15_Pos) /*!< 0x00007C00 */
1718 #define ADC_SQR1_SQ15 ADC_SQR1_SQ15_Msk /*!<SQ15[4:0] bits (15th conversion in regular sequence) */
1719 #define ADC_SQR1_SQ15_0 (0x01U << ADC_SQR1_SQ15_Pos) /*!< 0x00000400 */
1720 #define ADC_SQR1_SQ15_1 (0x02U << ADC_SQR1_SQ15_Pos) /*!< 0x00000800 */
1721 #define ADC_SQR1_SQ15_2 (0x04U << ADC_SQR1_SQ15_Pos) /*!< 0x00001000 */
1722 #define ADC_SQR1_SQ15_3 (0x08U << ADC_SQR1_SQ15_Pos) /*!< 0x00002000 */
1723 #define ADC_SQR1_SQ15_4 (0x10U << ADC_SQR1_SQ15_Pos) /*!< 0x00004000 */
1724 #define ADC_SQR1_SQ16_Pos (15U)
1725 #define ADC_SQR1_SQ16_Msk (0x1FU << ADC_SQR1_SQ16_Pos) /*!< 0x000F8000 */
1726 #define ADC_SQR1_SQ16 ADC_SQR1_SQ16_Msk /*!<SQ16[4:0] bits (16th conversion in regular sequence) */
1727 #define ADC_SQR1_SQ16_0 (0x01U << ADC_SQR1_SQ16_Pos) /*!< 0x00008000 */
1728 #define ADC_SQR1_SQ16_1 (0x02U << ADC_SQR1_SQ16_Pos) /*!< 0x00010000 */
1729 #define ADC_SQR1_SQ16_2 (0x04U << ADC_SQR1_SQ16_Pos) /*!< 0x00020000 */
1730 #define ADC_SQR1_SQ16_3 (0x08U << ADC_SQR1_SQ16_Pos) /*!< 0x00040000 */
1731 #define ADC_SQR1_SQ16_4 (0x10U << ADC_SQR1_SQ16_Pos) /*!< 0x00080000 */
1732 #define ADC_SQR1_L_Pos (20U)
1733 #define ADC_SQR1_L_Msk (0xFU << ADC_SQR1_L_Pos) /*!< 0x00F00000 */
1734 #define ADC_SQR1_L ADC_SQR1_L_Msk /*!<L[3:0] bits (Regular channel sequence length) */
1735 #define ADC_SQR1_L_0 (0x1U << ADC_SQR1_L_Pos) /*!< 0x00100000 */
1736 #define ADC_SQR1_L_1 (0x2U << ADC_SQR1_L_Pos) /*!< 0x00200000 */
1737 #define ADC_SQR1_L_2 (0x4U << ADC_SQR1_L_Pos) /*!< 0x00400000 */
1738 #define ADC_SQR1_L_3 (0x8U << ADC_SQR1_L_Pos) /*!< 0x00800000 */
1739
1740 /******************* Bit definition for ADC_SQR2 register *******************/
1741 #define ADC_SQR2_SQ7_Pos (0U)
1742 #define ADC_SQR2_SQ7_Msk (0x1FU << ADC_SQR2_SQ7_Pos) /*!< 0x0000001F */
1743 #define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk /*!<SQ7[4:0] bits (7th conversion in regular sequence) */
1744 #define ADC_SQR2_SQ7_0 (0x01U << ADC_SQR2_SQ7_Pos) /*!< 0x00000001 */
1745 #define ADC_SQR2_SQ7_1 (0x02U << ADC_SQR2_SQ7_Pos) /*!< 0x00000002 */
1746 #define ADC_SQR2_SQ7_2 (0x04U << ADC_SQR2_SQ7_Pos) /*!< 0x00000004 */
1747 #define ADC_SQR2_SQ7_3 (0x08U << ADC_SQR2_SQ7_Pos) /*!< 0x00000008 */
1748 #define ADC_SQR2_SQ7_4 (0x10U << ADC_SQR2_SQ7_Pos) /*!< 0x00000010 */
1749 #define ADC_SQR2_SQ8_Pos (5U)
1750 #define ADC_SQR2_SQ8_Msk (0x1FU << ADC_SQR2_SQ8_Pos) /*!< 0x000003E0 */
1751 #define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk /*!<SQ8[4:0] bits (8th conversion in regular sequence) */
1752 #define ADC_SQR2_SQ8_0 (0x01U << ADC_SQR2_SQ8_Pos) /*!< 0x00000020 */
1753 #define ADC_SQR2_SQ8_1 (0x02U << ADC_SQR2_SQ8_Pos) /*!< 0x00000040 */
1754 #define ADC_SQR2_SQ8_2 (0x04U << ADC_SQR2_SQ8_Pos) /*!< 0x00000080 */
1755 #define ADC_SQR2_SQ8_3 (0x08U << ADC_SQR2_SQ8_Pos) /*!< 0x00000100 */
1756 #define ADC_SQR2_SQ8_4 (0x10U << ADC_SQR2_SQ8_Pos) /*!< 0x00000200 */
1757 #define ADC_SQR2_SQ9_Pos (10U)
1758 #define ADC_SQR2_SQ9_Msk (0x1FU << ADC_SQR2_SQ9_Pos) /*!< 0x00007C00 */
1759 #define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk /*!<SQ9[4:0] bits (9th conversion in regular sequence) */
1760 #define ADC_SQR2_SQ9_0 (0x01U << ADC_SQR2_SQ9_Pos) /*!< 0x00000400 */
1761 #define ADC_SQR2_SQ9_1 (0x02U << ADC_SQR2_SQ9_Pos) /*!< 0x00000800 */
1762 #define ADC_SQR2_SQ9_2 (0x04U << ADC_SQR2_SQ9_Pos) /*!< 0x00001000 */
1763 #define ADC_SQR2_SQ9_3 (0x08U << ADC_SQR2_SQ9_Pos) /*!< 0x00002000 */
1764 #define ADC_SQR2_SQ9_4 (0x10U << ADC_SQR2_SQ9_Pos) /*!< 0x00004000 */
1765 #define ADC_SQR2_SQ10_Pos (15U)
1766 #define ADC_SQR2_SQ10_Msk (0x1FU << ADC_SQR2_SQ10_Pos) /*!< 0x000F8000 */
1767 #define ADC_SQR2_SQ10 ADC_SQR2_SQ10_Msk /*!<SQ10[4:0] bits (10th conversion in regular sequence) */
1768 #define ADC_SQR2_SQ10_0 (0x01U << ADC_SQR2_SQ10_Pos) /*!< 0x00008000 */
1769 #define ADC_SQR2_SQ10_1 (0x02U << ADC_SQR2_SQ10_Pos) /*!< 0x00010000 */
1770 #define ADC_SQR2_SQ10_2 (0x04U << ADC_SQR2_SQ10_Pos) /*!< 0x00020000 */
1771 #define ADC_SQR2_SQ10_3 (0x08U << ADC_SQR2_SQ10_Pos) /*!< 0x00040000 */
1772 #define ADC_SQR2_SQ10_4 (0x10U << ADC_SQR2_SQ10_Pos) /*!< 0x00080000 */
1773 #define ADC_SQR2_SQ11_Pos (20U)
1774 #define ADC_SQR2_SQ11_Msk (0x1FU << ADC_SQR2_SQ11_Pos) /*!< 0x01F00000 */
1775 #define ADC_SQR2_SQ11 ADC_SQR2_SQ11_Msk /*!<SQ11[4:0] bits (11th conversion in regular sequence) */
1776 #define ADC_SQR2_SQ11_0 (0x01U << ADC_SQR2_SQ11_Pos) /*!< 0x00100000 */
1777 #define ADC_SQR2_SQ11_1 (0x02U << ADC_SQR2_SQ11_Pos) /*!< 0x00200000 */
1778 #define ADC_SQR2_SQ11_2 (0x04U << ADC_SQR2_SQ11_Pos) /*!< 0x00400000 */
1779 #define ADC_SQR2_SQ11_3 (0x08U << ADC_SQR2_SQ11_Pos) /*!< 0x00800000 */
1780 #define ADC_SQR2_SQ11_4 (0x10U << ADC_SQR2_SQ11_Pos) /*!< 0x01000000 */
1781 #define ADC_SQR2_SQ12_Pos (25U)
1782 #define ADC_SQR2_SQ12_Msk (0x1FU << ADC_SQR2_SQ12_Pos) /*!< 0x3E000000 */
1783 #define ADC_SQR2_SQ12 ADC_SQR2_SQ12_Msk /*!<SQ12[4:0] bits (12th conversion in regular sequence) */
1784 #define ADC_SQR2_SQ12_0 (0x01U << ADC_SQR2_SQ12_Pos) /*!< 0x02000000 */
1785 #define ADC_SQR2_SQ12_1 (0x02U << ADC_SQR2_SQ12_Pos) /*!< 0x04000000 */
1786 #define ADC_SQR2_SQ12_2 (0x04U << ADC_SQR2_SQ12_Pos) /*!< 0x08000000 */
1787 #define ADC_SQR2_SQ12_3 (0x08U << ADC_SQR2_SQ12_Pos) /*!< 0x10000000 */
1788 #define ADC_SQR2_SQ12_4 (0x10U << ADC_SQR2_SQ12_Pos) /*!< 0x20000000 */
1789
1790 /******************* Bit definition for ADC_SQR3 register *******************/
1791 #define ADC_SQR3_SQ1_Pos (0U)
1792 #define ADC_SQR3_SQ1_Msk (0x1FU << ADC_SQR3_SQ1_Pos) /*!< 0x0000001F */
1793 #define ADC_SQR3_SQ1 ADC_SQR3_SQ1_Msk /*!<SQ1[4:0] bits (1st conversion in regular sequence) */
1794 #define ADC_SQR3_SQ1_0 (0x01U << ADC_SQR3_SQ1_Pos) /*!< 0x00000001 */
1795 #define ADC_SQR3_SQ1_1 (0x02U << ADC_SQR3_SQ1_Pos) /*!< 0x00000002 */
1796 #define ADC_SQR3_SQ1_2 (0x04U << ADC_SQR3_SQ1_Pos) /*!< 0x00000004 */
1797 #define ADC_SQR3_SQ1_3 (0x08U << ADC_SQR3_SQ1_Pos) /*!< 0x00000008 */
1798 #define ADC_SQR3_SQ1_4 (0x10U << ADC_SQR3_SQ1_Pos) /*!< 0x00000010 */
1799 #define ADC_SQR3_SQ2_Pos (5U)
1800 #define ADC_SQR3_SQ2_Msk (0x1FU << ADC_SQR3_SQ2_Pos) /*!< 0x000003E0 */
1801 #define ADC_SQR3_SQ2 ADC_SQR3_SQ2_Msk /*!<SQ2[4:0] bits (2nd conversion in regular sequence) */
1802 #define ADC_SQR3_SQ2_0 (0x01U << ADC_SQR3_SQ2_Pos) /*!< 0x00000020 */
1803 #define ADC_SQR3_SQ2_1 (0x02U << ADC_SQR3_SQ2_Pos) /*!< 0x00000040 */
1804 #define ADC_SQR3_SQ2_2 (0x04U << ADC_SQR3_SQ2_Pos) /*!< 0x00000080 */
1805 #define ADC_SQR3_SQ2_3 (0x08U << ADC_SQR3_SQ2_Pos) /*!< 0x00000100 */
1806 #define ADC_SQR3_SQ2_4 (0x10U << ADC_SQR3_SQ2_Pos) /*!< 0x00000200 */
1807 #define ADC_SQR3_SQ3_Pos (10U)
1808 #define ADC_SQR3_SQ3_Msk (0x1FU << ADC_SQR3_SQ3_Pos) /*!< 0x00007C00 */
1809 #define ADC_SQR3_SQ3 ADC_SQR3_SQ3_Msk /*!<SQ3[4:0] bits (3rd conversion in regular sequence) */
1810 #define ADC_SQR3_SQ3_0 (0x01U << ADC_SQR3_SQ3_Pos) /*!< 0x00000400 */
1811 #define ADC_SQR3_SQ3_1 (0x02U << ADC_SQR3_SQ3_Pos) /*!< 0x00000800 */
1812 #define ADC_SQR3_SQ3_2 (0x04U << ADC_SQR3_SQ3_Pos) /*!< 0x00001000 */
1813 #define ADC_SQR3_SQ3_3 (0x08U << ADC_SQR3_SQ3_Pos) /*!< 0x00002000 */
1814 #define ADC_SQR3_SQ3_4 (0x10U << ADC_SQR3_SQ3_Pos) /*!< 0x00004000 */
1815 #define ADC_SQR3_SQ4_Pos (15U)
1816 #define ADC_SQR3_SQ4_Msk (0x1FU << ADC_SQR3_SQ4_Pos) /*!< 0x000F8000 */
1817 #define ADC_SQR3_SQ4 ADC_SQR3_SQ4_Msk /*!<SQ4[4:0] bits (4th conversion in regular sequence) */
1818 #define ADC_SQR3_SQ4_0 (0x01U << ADC_SQR3_SQ4_Pos) /*!< 0x00008000 */
1819 #define ADC_SQR3_SQ4_1 (0x02U << ADC_SQR3_SQ4_Pos) /*!< 0x00010000 */
1820 #define ADC_SQR3_SQ4_2 (0x04U << ADC_SQR3_SQ4_Pos) /*!< 0x00020000 */
1821 #define ADC_SQR3_SQ4_3 (0x08U << ADC_SQR3_SQ4_Pos) /*!< 0x00040000 */
1822 #define ADC_SQR3_SQ4_4 (0x10U << ADC_SQR3_SQ4_Pos) /*!< 0x00080000 */
1823 #define ADC_SQR3_SQ5_Pos (20U)
1824 #define ADC_SQR3_SQ5_Msk (0x1FU << ADC_SQR3_SQ5_Pos) /*!< 0x01F00000 */
1825 #define ADC_SQR3_SQ5 ADC_SQR3_SQ5_Msk /*!<SQ5[4:0] bits (5th conversion in regular sequence) */
1826 #define ADC_SQR3_SQ5_0 (0x01U << ADC_SQR3_SQ5_Pos) /*!< 0x00100000 */
1827 #define ADC_SQR3_SQ5_1 (0x02U << ADC_SQR3_SQ5_Pos) /*!< 0x00200000 */
1828 #define ADC_SQR3_SQ5_2 (0x04U << ADC_SQR3_SQ5_Pos) /*!< 0x00400000 */
1829 #define ADC_SQR3_SQ5_3 (0x08U << ADC_SQR3_SQ5_Pos) /*!< 0x00800000 */
1830 #define ADC_SQR3_SQ5_4 (0x10U << ADC_SQR3_SQ5_Pos) /*!< 0x01000000 */
1831 #define ADC_SQR3_SQ6_Pos (25U)
1832 #define ADC_SQR3_SQ6_Msk (0x1FU << ADC_SQR3_SQ6_Pos) /*!< 0x3E000000 */
1833 #define ADC_SQR3_SQ6 ADC_SQR3_SQ6_Msk /*!<SQ6[4:0] bits (6th conversion in regular sequence) */
1834 #define ADC_SQR3_SQ6_0 (0x01U << ADC_SQR3_SQ6_Pos) /*!< 0x02000000 */
1835 #define ADC_SQR3_SQ6_1 (0x02U << ADC_SQR3_SQ6_Pos) /*!< 0x04000000 */
1836 #define ADC_SQR3_SQ6_2 (0x04U << ADC_SQR3_SQ6_Pos) /*!< 0x08000000 */
1837 #define ADC_SQR3_SQ6_3 (0x08U << ADC_SQR3_SQ6_Pos) /*!< 0x10000000 */
1838 #define ADC_SQR3_SQ6_4 (0x10U << ADC_SQR3_SQ6_Pos) /*!< 0x20000000 */
1839
1840 /******************* Bit definition for ADC_JSQR register *******************/
1841 #define ADC_JSQR_JSQ1_Pos (0U)
1842 #define ADC_JSQR_JSQ1_Msk (0x1FU << ADC_JSQR_JSQ1_Pos) /*!< 0x0000001F */
1843 #define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk /*!<JSQ1[4:0] bits (1st conversion in injected sequence) */
1844 #define ADC_JSQR_JSQ1_0 (0x01U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000001 */
1845 #define ADC_JSQR_JSQ1_1 (0x02U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000002 */
1846 #define ADC_JSQR_JSQ1_2 (0x04U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000004 */
1847 #define ADC_JSQR_JSQ1_3 (0x08U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000008 */
1848 #define ADC_JSQR_JSQ1_4 (0x10U << ADC_JSQR_JSQ1_Pos) /*!< 0x00000010 */
1849 #define ADC_JSQR_JSQ2_Pos (5U)
1850 #define ADC_JSQR_JSQ2_Msk (0x1FU << ADC_JSQR_JSQ2_Pos) /*!< 0x000003E0 */
1851 #define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk /*!<JSQ2[4:0] bits (2nd conversion in injected sequence) */
1852 #define ADC_JSQR_JSQ2_0 (0x01U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000020 */
1853 #define ADC_JSQR_JSQ2_1 (0x02U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000040 */
1854 #define ADC_JSQR_JSQ2_2 (0x04U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000080 */
1855 #define ADC_JSQR_JSQ2_3 (0x08U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000100 */
1856 #define ADC_JSQR_JSQ2_4 (0x10U << ADC_JSQR_JSQ2_Pos) /*!< 0x00000200 */
1857 #define ADC_JSQR_JSQ3_Pos (10U)
1858 #define ADC_JSQR_JSQ3_Msk (0x1FU << ADC_JSQR_JSQ3_Pos) /*!< 0x00007C00 */
1859 #define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk /*!<JSQ3[4:0] bits (3rd conversion in injected sequence) */
1860 #define ADC_JSQR_JSQ3_0 (0x01U << ADC_JSQR_JSQ3_Pos) /*!< 0x00000400 */
1861 #define ADC_JSQR_JSQ3_1 (0x02U << ADC_JSQR_JSQ3_Pos) /*!< 0x00000800 */
1862 #define ADC_JSQR_JSQ3_2 (0x04U << ADC_JSQR_JSQ3_Pos) /*!< 0x00001000 */
1863 #define ADC_JSQR_JSQ3_3 (0x08U << ADC_JSQR_JSQ3_Pos) /*!< 0x00002000 */
1864 #define ADC_JSQR_JSQ3_4 (0x10U << ADC_JSQR_JSQ3_Pos) /*!< 0x00004000 */
1865 #define ADC_JSQR_JSQ4_Pos (15U)
1866 #define ADC_JSQR_JSQ4_Msk (0x1FU << ADC_JSQR_JSQ4_Pos) /*!< 0x000F8000 */
1867 #define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk /*!<JSQ4[4:0] bits (4th conversion in injected sequence) */
1868 #define ADC_JSQR_JSQ4_0 (0x01U << ADC_JSQR_JSQ4_Pos) /*!< 0x00008000 */
1869 #define ADC_JSQR_JSQ4_1 (0x02U << ADC_JSQR_JSQ4_Pos) /*!< 0x00010000 */
1870 #define ADC_JSQR_JSQ4_2 (0x04U << ADC_JSQR_JSQ4_Pos) /*!< 0x00020000 */
1871 #define ADC_JSQR_JSQ4_3 (0x08U << ADC_JSQR_JSQ4_Pos) /*!< 0x00040000 */
1872 #define ADC_JSQR_JSQ4_4 (0x10U << ADC_JSQR_JSQ4_Pos) /*!< 0x00080000 */
1873 #define ADC_JSQR_JL_Pos (20U)
1874 #define ADC_JSQR_JL_Msk (0x3U << ADC_JSQR_JL_Pos) /*!< 0x00300000 */
1875 #define ADC_JSQR_JL ADC_JSQR_JL_Msk /*!<JL[1:0] bits (Injected Sequence length) */
1876 #define ADC_JSQR_JL_0 (0x1U << ADC_JSQR_JL_Pos) /*!< 0x00100000 */
1877 #define ADC_JSQR_JL_1 (0x2U << ADC_JSQR_JL_Pos) /*!< 0x00200000 */
1878
1879 /******************* Bit definition for ADC_JDR1 register *******************/
1880 #define ADC_JDR1_JDATA_Pos (0U)
1881 #define ADC_JDR1_JDATA_Msk (0xFFFFU << ADC_JDR1_JDATA_Pos) /*!< 0x0000FFFF */
1882 #define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /*!<Injected data */
1883
1884 /******************* Bit definition for ADC_JDR2 register *******************/
1885 #define ADC_JDR2_JDATA_Pos (0U)
1886 #define ADC_JDR2_JDATA_Msk (0xFFFFU << ADC_JDR2_JDATA_Pos) /*!< 0x0000FFFF */
1887 #define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /*!<Injected data */
1888
1889 /******************* Bit definition for ADC_JDR3 register *******************/
1890 #define ADC_JDR3_JDATA_Pos (0U)
1891 #define ADC_JDR3_JDATA_Msk (0xFFFFU << ADC_JDR3_JDATA_Pos) /*!< 0x0000FFFF */
1892 #define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /*!<Injected data */
1893
1894 /******************* Bit definition for ADC_JDR4 register *******************/
1895 #define ADC_JDR4_JDATA_Pos (0U)
1896 #define ADC_JDR4_JDATA_Msk (0xFFFFU << ADC_JDR4_JDATA_Pos) /*!< 0x0000FFFF */
1897 #define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /*!<Injected data */
1898
1899 /******************** Bit definition for ADC_DR register ********************/
1900 #define ADC_DR_DATA_Pos (0U)
1901 #define ADC_DR_DATA_Msk (0xFFFFU << ADC_DR_DATA_Pos) /*!< 0x0000FFFF */
1902 #define ADC_DR_DATA ADC_DR_DATA_Msk /*!<Regular data */
1903 #define ADC_DR_ADC2DATA_Pos (16U)
1904 #define ADC_DR_ADC2DATA_Msk (0xFFFFU << ADC_DR_ADC2DATA_Pos) /*!< 0xFFFF0000 */
1905 #define ADC_DR_ADC2DATA ADC_DR_ADC2DATA_Msk /*!<ADC2 data */
1906
1907 /******************* Bit definition for ADC_CSR register ********************/
1908 #define ADC_CSR_AWD1_Pos (0U)
1909 #define ADC_CSR_AWD1_Msk (0x1U << ADC_CSR_AWD1_Pos) /*!< 0x00000001 */
1910 #define ADC_CSR_AWD1 ADC_CSR_AWD1_Msk /*!<ADC1 Analog watchdog flag */
1911 #define ADC_CSR_EOC1_Pos (1U)
1912 #define ADC_CSR_EOC1_Msk (0x1U << ADC_CSR_EOC1_Pos) /*!< 0x00000002 */
1913 #define ADC_CSR_EOC1 ADC_CSR_EOC1_Msk /*!<ADC1 End of conversion */
1914 #define ADC_CSR_JEOC1_Pos (2U)
1915 #define ADC_CSR_JEOC1_Msk (0x1U << ADC_CSR_JEOC1_Pos) /*!< 0x00000004 */
1916 #define ADC_CSR_JEOC1 ADC_CSR_JEOC1_Msk /*!<ADC1 Injected channel end of conversion */
1917 #define ADC_CSR_JSTRT1_Pos (3U)
1918 #define ADC_CSR_JSTRT1_Msk (0x1U << ADC_CSR_JSTRT1_Pos) /*!< 0x00000008 */
1919 #define ADC_CSR_JSTRT1 ADC_CSR_JSTRT1_Msk /*!<ADC1 Injected channel Start flag */
1920 #define ADC_CSR_STRT1_Pos (4U)
1921 #define ADC_CSR_STRT1_Msk (0x1U << ADC_CSR_STRT1_Pos) /*!< 0x00000010 */
1922 #define ADC_CSR_STRT1 ADC_CSR_STRT1_Msk /*!<ADC1 Regular channel Start flag */
1923 #define ADC_CSR_OVR1_Pos (5U)
1924 #define ADC_CSR_OVR1_Msk (0x1U << ADC_CSR_OVR1_Pos) /*!< 0x00000020 */
1925 #define ADC_CSR_OVR1 ADC_CSR_OVR1_Msk /*!<ADC1 DMA overrun flag */
1926 #define ADC_CSR_AWD2_Pos (8U)
1927 #define ADC_CSR_AWD2_Msk (0x1U << ADC_CSR_AWD2_Pos) /*!< 0x00000100 */
1928 #define ADC_CSR_AWD2 ADC_CSR_AWD2_Msk /*!<ADC2 Analog watchdog flag */
1929 #define ADC_CSR_EOC2_Pos (9U)
1930 #define ADC_CSR_EOC2_Msk (0x1U << ADC_CSR_EOC2_Pos) /*!< 0x00000200 */
1931 #define ADC_CSR_EOC2 ADC_CSR_EOC2_Msk /*!<ADC2 End of conversion */
1932 #define ADC_CSR_JEOC2_Pos (10U)
1933 #define ADC_CSR_JEOC2_Msk (0x1U << ADC_CSR_JEOC2_Pos) /*!< 0x00000400 */
1934 #define ADC_CSR_JEOC2 ADC_CSR_JEOC2_Msk /*!<ADC2 Injected channel end of conversion */
1935 #define ADC_CSR_JSTRT2_Pos (11U)
1936 #define ADC_CSR_JSTRT2_Msk (0x1U << ADC_CSR_JSTRT2_Pos) /*!< 0x00000800 */
1937 #define ADC_CSR_JSTRT2 ADC_CSR_JSTRT2_Msk /*!<ADC2 Injected channel Start flag */
1938 #define ADC_CSR_STRT2_Pos (12U)
1939 #define ADC_CSR_STRT2_Msk (0x1U << ADC_CSR_STRT2_Pos) /*!< 0x00001000 */
1940 #define ADC_CSR_STRT2 ADC_CSR_STRT2_Msk /*!<ADC2 Regular channel Start flag */
1941 #define ADC_CSR_OVR2_Pos (13U)
1942 #define ADC_CSR_OVR2_Msk (0x1U << ADC_CSR_OVR2_Pos) /*!< 0x00002000 */
1943 #define ADC_CSR_OVR2 ADC_CSR_OVR2_Msk /*!<ADC2 DMA overrun flag */
1944 #define ADC_CSR_AWD3_Pos (16U)
1945 #define ADC_CSR_AWD3_Msk (0x1U << ADC_CSR_AWD3_Pos) /*!< 0x00010000 */
1946 #define ADC_CSR_AWD3 ADC_CSR_AWD3_Msk /*!<ADC3 Analog watchdog flag */
1947 #define ADC_CSR_EOC3_Pos (17U)
1948 #define ADC_CSR_EOC3_Msk (0x1U << ADC_CSR_EOC3_Pos) /*!< 0x00020000 */
1949 #define ADC_CSR_EOC3 ADC_CSR_EOC3_Msk /*!<ADC3 End of conversion */
1950 #define ADC_CSR_JEOC3_Pos (18U)
1951 #define ADC_CSR_JEOC3_Msk (0x1U << ADC_CSR_JEOC3_Pos) /*!< 0x00040000 */
1952 #define ADC_CSR_JEOC3 ADC_CSR_JEOC3_Msk /*!<ADC3 Injected channel end of conversion */
1953 #define ADC_CSR_JSTRT3_Pos (19U)
1954 #define ADC_CSR_JSTRT3_Msk (0x1U << ADC_CSR_JSTRT3_Pos) /*!< 0x00080000 */
1955 #define ADC_CSR_JSTRT3 ADC_CSR_JSTRT3_Msk /*!<ADC3 Injected channel Start flag */
1956 #define ADC_CSR_STRT3_Pos (20U)
1957 #define ADC_CSR_STRT3_Msk (0x1U << ADC_CSR_STRT3_Pos) /*!< 0x00100000 */
1958 #define ADC_CSR_STRT3 ADC_CSR_STRT3_Msk /*!<ADC3 Regular channel Start flag */
1959 #define ADC_CSR_OVR3_Pos (21U)
1960 #define ADC_CSR_OVR3_Msk (0x1U << ADC_CSR_OVR3_Pos) /*!< 0x00200000 */
1961 #define ADC_CSR_OVR3 ADC_CSR_OVR3_Msk /*!<ADC3 DMA overrun flag */
1962
1963 /* Legacy defines */
1964 #define ADC_CSR_DOVR1 ADC_CSR_OVR1
1965 #define ADC_CSR_DOVR2 ADC_CSR_OVR2
1966 #define ADC_CSR_DOVR3 ADC_CSR_OVR3
1967
1968 /******************* Bit definition for ADC_CCR register ********************/
1969 #define ADC_CCR_MULTI_Pos (0U)
1970 #define ADC_CCR_MULTI_Msk (0x1FU << ADC_CCR_MULTI_Pos) /*!< 0x0000001F */
1971 #define ADC_CCR_MULTI ADC_CCR_MULTI_Msk /*!<MULTI[4:0] bits (Multi-ADC mode selection) */
1972 #define ADC_CCR_MULTI_0 (0x01U << ADC_CCR_MULTI_Pos) /*!< 0x00000001 */
1973 #define ADC_CCR_MULTI_1 (0x02U << ADC_CCR_MULTI_Pos) /*!< 0x00000002 */
1974 #define ADC_CCR_MULTI_2 (0x04U << ADC_CCR_MULTI_Pos) /*!< 0x00000004 */
1975 #define ADC_CCR_MULTI_3 (0x08U << ADC_CCR_MULTI_Pos) /*!< 0x00000008 */
1976 #define ADC_CCR_MULTI_4 (0x10U << ADC_CCR_MULTI_Pos) /*!< 0x00000010 */
1977 #define ADC_CCR_DELAY_Pos (8U)
1978 #define ADC_CCR_DELAY_Msk (0xFU << ADC_CCR_DELAY_Pos) /*!< 0x00000F00 */
1979 #define ADC_CCR_DELAY ADC_CCR_DELAY_Msk /*!<DELAY[3:0] bits (Delay between 2 sampling phases) */
1980 #define ADC_CCR_DELAY_0 (0x1U << ADC_CCR_DELAY_Pos) /*!< 0x00000100 */
1981 #define ADC_CCR_DELAY_1 (0x2U << ADC_CCR_DELAY_Pos) /*!< 0x00000200 */
1982 #define ADC_CCR_DELAY_2 (0x4U << ADC_CCR_DELAY_Pos) /*!< 0x00000400 */
1983 #define ADC_CCR_DELAY_3 (0x8U << ADC_CCR_DELAY_Pos) /*!< 0x00000800 */
1984 #define ADC_CCR_DDS_Pos (13U)
1985 #define ADC_CCR_DDS_Msk (0x1U << ADC_CCR_DDS_Pos) /*!< 0x00002000 */
1986 #define ADC_CCR_DDS ADC_CCR_DDS_Msk /*!<DMA disable selection (Multi-ADC mode) */
1987 #define ADC_CCR_DMA_Pos (14U)
1988 #define ADC_CCR_DMA_Msk (0x3U << ADC_CCR_DMA_Pos) /*!< 0x0000C000 */
1989 #define ADC_CCR_DMA ADC_CCR_DMA_Msk /*!<DMA[1:0] bits (Direct Memory Access mode for multimode) */
1990 #define ADC_CCR_DMA_0 (0x1U << ADC_CCR_DMA_Pos) /*!< 0x00004000 */
1991 #define ADC_CCR_DMA_1 (0x2U << ADC_CCR_DMA_Pos) /*!< 0x00008000 */
1992 #define ADC_CCR_ADCPRE_Pos (16U)
1993 #define ADC_CCR_ADCPRE_Msk (0x3U << ADC_CCR_ADCPRE_Pos) /*!< 0x00030000 */
1994 #define ADC_CCR_ADCPRE ADC_CCR_ADCPRE_Msk /*!<ADCPRE[1:0] bits (ADC prescaler) */
1995 #define ADC_CCR_ADCPRE_0 (0x1U << ADC_CCR_ADCPRE_Pos) /*!< 0x00010000 */
1996 #define ADC_CCR_ADCPRE_1 (0x2U << ADC_CCR_ADCPRE_Pos) /*!< 0x00020000 */
1997 #define ADC_CCR_VBATE_Pos (22U)
1998 #define ADC_CCR_VBATE_Msk (0x1U << ADC_CCR_VBATE_Pos) /*!< 0x00400000 */
1999 #define ADC_CCR_VBATE ADC_CCR_VBATE_Msk /*!<VBAT Enable */
2000 #define ADC_CCR_TSVREFE_Pos (23U)
2001 #define ADC_CCR_TSVREFE_Msk (0x1U << ADC_CCR_TSVREFE_Pos) /*!< 0x00800000 */
2002 #define ADC_CCR_TSVREFE ADC_CCR_TSVREFE_Msk /*!<Temperature Sensor and VREFINT Enable */
2003
2004 /******************* Bit definition for ADC_CDR register ********************/
2005 #define ADC_CDR_DATA1_Pos (0U)
2006 #define ADC_CDR_DATA1_Msk (0xFFFFU << ADC_CDR_DATA1_Pos) /*!< 0x0000FFFF */
2007 #define ADC_CDR_DATA1 ADC_CDR_DATA1_Msk /*!<1st data of a pair of regular conversions */
2008 #define ADC_CDR_DATA2_Pos (16U)
2009 #define ADC_CDR_DATA2_Msk (0xFFFFU << ADC_CDR_DATA2_Pos) /*!< 0xFFFF0000 */
2010 #define ADC_CDR_DATA2 ADC_CDR_DATA2_Msk /*!<2nd data of a pair of regular conversions */
2011
2012 /* Legacy defines */
2013 #define ADC_CDR_RDATA_MST ADC_CDR_DATA1
2014 #define ADC_CDR_RDATA_SLV ADC_CDR_DATA2
2015
2016 /******************************************************************************/
2017 /* */
2018 /* Controller Area Network */
2019 /* */
2020 /******************************************************************************/
2021 /*!<CAN control and status registers */
2022 /******************* Bit definition for CAN_MCR register ********************/
2023 #define CAN_MCR_INRQ_Pos (0U)
2024 #define CAN_MCR_INRQ_Msk (0x1U << CAN_MCR_INRQ_Pos) /*!< 0x00000001 */
2025 #define CAN_MCR_INRQ CAN_MCR_INRQ_Msk /*!<Initialization Request */
2026 #define CAN_MCR_SLEEP_Pos (1U)
2027 #define CAN_MCR_SLEEP_Msk (0x1U << CAN_MCR_SLEEP_Pos) /*!< 0x00000002 */
2028 #define CAN_MCR_SLEEP CAN_MCR_SLEEP_Msk /*!<Sleep Mode Request */
2029 #define CAN_MCR_TXFP_Pos (2U)
2030 #define CAN_MCR_TXFP_Msk (0x1U << CAN_MCR_TXFP_Pos) /*!< 0x00000004 */
2031 #define CAN_MCR_TXFP CAN_MCR_TXFP_Msk /*!<Transmit FIFO Priority */
2032 #define CAN_MCR_RFLM_Pos (3U)
2033 #define CAN_MCR_RFLM_Msk (0x1U << CAN_MCR_RFLM_Pos) /*!< 0x00000008 */
2034 #define CAN_MCR_RFLM CAN_MCR_RFLM_Msk /*!<Receive FIFO Locked Mode */
2035 #define CAN_MCR_NART_Pos (4U)
2036 #define CAN_MCR_NART_Msk (0x1U << CAN_MCR_NART_Pos) /*!< 0x00000010 */
2037 #define CAN_MCR_NART CAN_MCR_NART_Msk /*!<No Automatic Retransmission */
2038 #define CAN_MCR_AWUM_Pos (5U)
2039 #define CAN_MCR_AWUM_Msk (0x1U << CAN_MCR_AWUM_Pos) /*!< 0x00000020 */
2040 #define CAN_MCR_AWUM CAN_MCR_AWUM_Msk /*!<Automatic Wakeup Mode */
2041 #define CAN_MCR_ABOM_Pos (6U)
2042 #define CAN_MCR_ABOM_Msk (0x1U << CAN_MCR_ABOM_Pos) /*!< 0x00000040 */
2043 #define CAN_MCR_ABOM CAN_MCR_ABOM_Msk /*!<Automatic Bus-Off Management */
2044 #define CAN_MCR_TTCM_Pos (7U)
2045 #define CAN_MCR_TTCM_Msk (0x1U << CAN_MCR_TTCM_Pos) /*!< 0x00000080 */
2046 #define CAN_MCR_TTCM CAN_MCR_TTCM_Msk /*!<Time Triggered Communication Mode */
2047 #define CAN_MCR_RESET_Pos (15U)
2048 #define CAN_MCR_RESET_Msk (0x1U << CAN_MCR_RESET_Pos) /*!< 0x00008000 */
2049 #define CAN_MCR_RESET CAN_MCR_RESET_Msk /*!<bxCAN software master reset */
2050 #define CAN_MCR_DBF_Pos (16U)
2051 #define CAN_MCR_DBF_Msk (0x1U << CAN_MCR_DBF_Pos) /*!< 0x00010000 */
2052 #define CAN_MCR_DBF CAN_MCR_DBF_Msk /*!<bxCAN Debug freeze */
2053 /******************* Bit definition for CAN_MSR register ********************/
2054 #define CAN_MSR_INAK_Pos (0U)
2055 #define CAN_MSR_INAK_Msk (0x1U << CAN_MSR_INAK_Pos) /*!< 0x00000001 */
2056 #define CAN_MSR_INAK CAN_MSR_INAK_Msk /*!<Initialization Acknowledge */
2057 #define CAN_MSR_SLAK_Pos (1U)
2058 #define CAN_MSR_SLAK_Msk (0x1U << CAN_MSR_SLAK_Pos) /*!< 0x00000002 */
2059 #define CAN_MSR_SLAK CAN_MSR_SLAK_Msk /*!<Sleep Acknowledge */
2060 #define CAN_MSR_ERRI_Pos (2U)
2061 #define CAN_MSR_ERRI_Msk (0x1U << CAN_MSR_ERRI_Pos) /*!< 0x00000004 */
2062 #define CAN_MSR_ERRI CAN_MSR_ERRI_Msk /*!<Error Interrupt */
2063 #define CAN_MSR_WKUI_Pos (3U)
2064 #define CAN_MSR_WKUI_Msk (0x1U << CAN_MSR_WKUI_Pos) /*!< 0x00000008 */
2065 #define CAN_MSR_WKUI CAN_MSR_WKUI_Msk /*!<Wakeup Interrupt */
2066 #define CAN_MSR_SLAKI_Pos (4U)
2067 #define CAN_MSR_SLAKI_Msk (0x1U << CAN_MSR_SLAKI_Pos) /*!< 0x00000010 */
2068 #define CAN_MSR_SLAKI CAN_MSR_SLAKI_Msk /*!<Sleep Acknowledge Interrupt */
2069 #define CAN_MSR_TXM_Pos (8U)
2070 #define CAN_MSR_TXM_Msk (0x1U << CAN_MSR_TXM_Pos) /*!< 0x00000100 */
2071 #define CAN_MSR_TXM CAN_MSR_TXM_Msk /*!<Transmit Mode */
2072 #define CAN_MSR_RXM_Pos (9U)
2073 #define CAN_MSR_RXM_Msk (0x1U << CAN_MSR_RXM_Pos) /*!< 0x00000200 */
2074 #define CAN_MSR_RXM CAN_MSR_RXM_Msk /*!<Receive Mode */
2075 #define CAN_MSR_SAMP_Pos (10U)
2076 #define CAN_MSR_SAMP_Msk (0x1U << CAN_MSR_SAMP_Pos) /*!< 0x00000400 */
2077 #define CAN_MSR_SAMP CAN_MSR_SAMP_Msk /*!<Last Sample Point */
2078 #define CAN_MSR_RX_Pos (11U)
2079 #define CAN_MSR_RX_Msk (0x1U << CAN_MSR_RX_Pos) /*!< 0x00000800 */
2080 #define CAN_MSR_RX CAN_MSR_RX_Msk /*!<CAN Rx Signal */
2081
2082 /******************* Bit definition for CAN_TSR register ********************/
2083 #define CAN_TSR_RQCP0_Pos (0U)
2084 #define CAN_TSR_RQCP0_Msk (0x1U << CAN_TSR_RQCP0_Pos) /*!< 0x00000001 */
2085 #define CAN_TSR_RQCP0 CAN_TSR_RQCP0_Msk /*!<Request Completed Mailbox0 */
2086 #define CAN_TSR_TXOK0_Pos (1U)
2087 #define CAN_TSR_TXOK0_Msk (0x1U << CAN_TSR_TXOK0_Pos) /*!< 0x00000002 */
2088 #define CAN_TSR_TXOK0 CAN_TSR_TXOK0_Msk /*!<Transmission OK of Mailbox0 */
2089 #define CAN_TSR_ALST0_Pos (2U)
2090 #define CAN_TSR_ALST0_Msk (0x1U << CAN_TSR_ALST0_Pos) /*!< 0x00000004 */
2091 #define CAN_TSR_ALST0 CAN_TSR_ALST0_Msk /*!<Arbitration Lost for Mailbox0 */
2092 #define CAN_TSR_TERR0_Pos (3U)
2093 #define CAN_TSR_TERR0_Msk (0x1U << CAN_TSR_TERR0_Pos) /*!< 0x00000008 */
2094 #define CAN_TSR_TERR0 CAN_TSR_TERR0_Msk /*!<Transmission Error of Mailbox0 */
2095 #define CAN_TSR_ABRQ0_Pos (7U)
2096 #define CAN_TSR_ABRQ0_Msk (0x1U << CAN_TSR_ABRQ0_Pos) /*!< 0x00000080 */
2097 #define CAN_TSR_ABRQ0 CAN_TSR_ABRQ0_Msk /*!<Abort Request for Mailbox0 */
2098 #define CAN_TSR_RQCP1_Pos (8U)
2099 #define CAN_TSR_RQCP1_Msk (0x1U << CAN_TSR_RQCP1_Pos) /*!< 0x00000100 */
2100 #define CAN_TSR_RQCP1 CAN_TSR_RQCP1_Msk /*!<Request Completed Mailbox1 */
2101 #define CAN_TSR_TXOK1_Pos (9U)
2102 #define CAN_TSR_TXOK1_Msk (0x1U << CAN_TSR_TXOK1_Pos) /*!< 0x00000200 */
2103 #define CAN_TSR_TXOK1 CAN_TSR_TXOK1_Msk /*!<Transmission OK of Mailbox1 */
2104 #define CAN_TSR_ALST1_Pos (10U)
2105 #define CAN_TSR_ALST1_Msk (0x1U << CAN_TSR_ALST1_Pos) /*!< 0x00000400 */
2106 #define CAN_TSR_ALST1 CAN_TSR_ALST1_Msk /*!<Arbitration Lost for Mailbox1 */
2107 #define CAN_TSR_TERR1_Pos (11U)
2108 #define CAN_TSR_TERR1_Msk (0x1U << CAN_TSR_TERR1_Pos) /*!< 0x00000800 */
2109 #define CAN_TSR_TERR1 CAN_TSR_TERR1_Msk /*!<Transmission Error of Mailbox1 */
2110 #define CAN_TSR_ABRQ1_Pos (15U)
2111 #define CAN_TSR_ABRQ1_Msk (0x1U << CAN_TSR_ABRQ1_Pos) /*!< 0x00008000 */
2112 #define CAN_TSR_ABRQ1 CAN_TSR_ABRQ1_Msk /*!<Abort Request for Mailbox 1 */
2113 #define CAN_TSR_RQCP2_Pos (16U)
2114 #define CAN_TSR_RQCP2_Msk (0x1U << CAN_TSR_RQCP2_Pos) /*!< 0x00010000 */
2115 #define CAN_TSR_RQCP2 CAN_TSR_RQCP2_Msk /*!<Request Completed Mailbox2 */
2116 #define CAN_TSR_TXOK2_Pos (17U)
2117 #define CAN_TSR_TXOK2_Msk (0x1U << CAN_TSR_TXOK2_Pos) /*!< 0x00020000 */
2118 #define CAN_TSR_TXOK2 CAN_TSR_TXOK2_Msk /*!<Transmission OK of Mailbox 2 */
2119 #define CAN_TSR_ALST2_Pos (18U)
2120 #define CAN_TSR_ALST2_Msk (0x1U << CAN_TSR_ALST2_Pos) /*!< 0x00040000 */
2121 #define CAN_TSR_ALST2 CAN_TSR_ALST2_Msk /*!<Arbitration Lost for mailbox 2 */
2122 #define CAN_TSR_TERR2_Pos (19U)
2123 #define CAN_TSR_TERR2_Msk (0x1U << CAN_TSR_TERR2_Pos) /*!< 0x00080000 */
2124 #define CAN_TSR_TERR2 CAN_TSR_TERR2_Msk /*!<Transmission Error of Mailbox 2 */
2125 #define CAN_TSR_ABRQ2_Pos (23U)
2126 #define CAN_TSR_ABRQ2_Msk (0x1U << CAN_TSR_ABRQ2_Pos) /*!< 0x00800000 */
2127 #define CAN_TSR_ABRQ2 CAN_TSR_ABRQ2_Msk /*!<Abort Request for Mailbox 2 */
2128 #define CAN_TSR_CODE_Pos (24U)
2129 #define CAN_TSR_CODE_Msk (0x3U << CAN_TSR_CODE_Pos) /*!< 0x03000000 */
2130 #define CAN_TSR_CODE CAN_TSR_CODE_Msk /*!<Mailbox Code */
2131
2132 #define CAN_TSR_TME_Pos (26U)
2133 #define CAN_TSR_TME_Msk (0x7U << CAN_TSR_TME_Pos) /*!< 0x1C000000 */
2134 #define CAN_TSR_TME CAN_TSR_TME_Msk /*!<TME[2:0] bits */
2135 #define CAN_TSR_TME0_Pos (26U)
2136 #define CAN_TSR_TME0_Msk (0x1U << CAN_TSR_TME0_Pos) /*!< 0x04000000 */
2137 #define CAN_TSR_TME0 CAN_TSR_TME0_Msk /*!<Transmit Mailbox 0 Empty */
2138 #define CAN_TSR_TME1_Pos (27U)
2139 #define CAN_TSR_TME1_Msk (0x1U << CAN_TSR_TME1_Pos) /*!< 0x08000000 */
2140 #define CAN_TSR_TME1 CAN_TSR_TME1_Msk /*!<Transmit Mailbox 1 Empty */
2141 #define CAN_TSR_TME2_Pos (28U)
2142 #define CAN_TSR_TME2_Msk (0x1U << CAN_TSR_TME2_Pos) /*!< 0x10000000 */
2143 #define CAN_TSR_TME2 CAN_TSR_TME2_Msk /*!<Transmit Mailbox 2 Empty */
2144
2145 #define CAN_TSR_LOW_Pos (29U)
2146 #define CAN_TSR_LOW_Msk (0x7U << CAN_TSR_LOW_Pos) /*!< 0xE0000000 */
2147 #define CAN_TSR_LOW CAN_TSR_LOW_Msk /*!<LOW[2:0] bits */
2148 #define CAN_TSR_LOW0_Pos (29U)
2149 #define CAN_TSR_LOW0_Msk (0x1U << CAN_TSR_LOW0_Pos) /*!< 0x20000000 */
2150 #define CAN_TSR_LOW0 CAN_TSR_LOW0_Msk /*!<Lowest Priority Flag for Mailbox 0 */
2151 #define CAN_TSR_LOW1_Pos (30U)
2152 #define CAN_TSR_LOW1_Msk (0x1U << CAN_TSR_LOW1_Pos) /*!< 0x40000000 */
2153 #define CAN_TSR_LOW1 CAN_TSR_LOW1_Msk /*!<Lowest Priority Flag for Mailbox 1 */
2154 #define CAN_TSR_LOW2_Pos (31U)
2155 #define CAN_TSR_LOW2_Msk (0x1U << CAN_TSR_LOW2_Pos) /*!< 0x80000000 */
2156 #define CAN_TSR_LOW2 CAN_TSR_LOW2_Msk /*!<Lowest Priority Flag for Mailbox 2 */
2157
2158 /******************* Bit definition for CAN_RF0R register *******************/
2159 #define CAN_RF0R_FMP0_Pos (0U)
2160 #define CAN_RF0R_FMP0_Msk (0x3U << CAN_RF0R_FMP0_Pos) /*!< 0x00000003 */
2161 #define CAN_RF0R_FMP0 CAN_RF0R_FMP0_Msk /*!<FIFO 0 Message Pending */
2162 #define CAN_RF0R_FULL0_Pos (3U)
2163 #define CAN_RF0R_FULL0_Msk (0x1U << CAN_RF0R_FULL0_Pos) /*!< 0x00000008 */
2164 #define CAN_RF0R_FULL0 CAN_RF0R_FULL0_Msk /*!<FIFO 0 Full */
2165 #define CAN_RF0R_FOVR0_Pos (4U)
2166 #define CAN_RF0R_FOVR0_Msk (0x1U << CAN_RF0R_FOVR0_Pos) /*!< 0x00000010 */
2167 #define CAN_RF0R_FOVR0 CAN_RF0R_FOVR0_Msk /*!<FIFO 0 Overrun */
2168 #define CAN_RF0R_RFOM0_Pos (5U)
2169 #define CAN_RF0R_RFOM0_Msk (0x1U << CAN_RF0R_RFOM0_Pos) /*!< 0x00000020 */
2170 #define CAN_RF0R_RFOM0 CAN_RF0R_RFOM0_Msk /*!<Release FIFO 0 Output Mailbox */
2171
2172 /******************* Bit definition for CAN_RF1R register *******************/
2173 #define CAN_RF1R_FMP1_Pos (0U)
2174 #define CAN_RF1R_FMP1_Msk (0x3U << CAN_RF1R_FMP1_Pos) /*!< 0x00000003 */
2175 #define CAN_RF1R_FMP1 CAN_RF1R_FMP1_Msk /*!<FIFO 1 Message Pending */
2176 #define CAN_RF1R_FULL1_Pos (3U)
2177 #define CAN_RF1R_FULL1_Msk (0x1U << CAN_RF1R_FULL1_Pos) /*!< 0x00000008 */
2178 #define CAN_RF1R_FULL1 CAN_RF1R_FULL1_Msk /*!<FIFO 1 Full */
2179 #define CAN_RF1R_FOVR1_Pos (4U)
2180 #define CAN_RF1R_FOVR1_Msk (0x1U << CAN_RF1R_FOVR1_Pos) /*!< 0x00000010 */
2181 #define CAN_RF1R_FOVR1 CAN_RF1R_FOVR1_Msk /*!<FIFO 1 Overrun */
2182 #define CAN_RF1R_RFOM1_Pos (5U)
2183 #define CAN_RF1R_RFOM1_Msk (0x1U << CAN_RF1R_RFOM1_Pos) /*!< 0x00000020 */
2184 #define CAN_RF1R_RFOM1 CAN_RF1R_RFOM1_Msk /*!<Release FIFO 1 Output Mailbox */
2185
2186 /******************** Bit definition for CAN_IER register *******************/
2187 #define CAN_IER_TMEIE_Pos (0U)
2188 #define CAN_IER_TMEIE_Msk (0x1U << CAN_IER_TMEIE_Pos) /*!< 0x00000001 */
2189 #define CAN_IER_TMEIE CAN_IER_TMEIE_Msk /*!<Transmit Mailbox Empty Interrupt Enable */
2190 #define CAN_IER_FMPIE0_Pos (1U)
2191 #define CAN_IER_FMPIE0_Msk (0x1U << CAN_IER_FMPIE0_Pos) /*!< 0x00000002 */
2192 #define CAN_IER_FMPIE0 CAN_IER_FMPIE0_Msk /*!<FIFO Message Pending Interrupt Enable */
2193 #define CAN_IER_FFIE0_Pos (2U)
2194 #define CAN_IER_FFIE0_Msk (0x1U << CAN_IER_FFIE0_Pos) /*!< 0x00000004 */
2195 #define CAN_IER_FFIE0 CAN_IER_FFIE0_Msk /*!<FIFO Full Interrupt Enable */
2196 #define CAN_IER_FOVIE0_Pos (3U)
2197 #define CAN_IER_FOVIE0_Msk (0x1U << CAN_IER_FOVIE0_Pos) /*!< 0x00000008 */
2198 #define CAN_IER_FOVIE0 CAN_IER_FOVIE0_Msk /*!<FIFO Overrun Interrupt Enable */
2199 #define CAN_IER_FMPIE1_Pos (4U)
2200 #define CAN_IER_FMPIE1_Msk (0x1U << CAN_IER_FMPIE1_Pos) /*!< 0x00000010 */
2201 #define CAN_IER_FMPIE1 CAN_IER_FMPIE1_Msk /*!<FIFO Message Pending Interrupt Enable */
2202 #define CAN_IER_FFIE1_Pos (5U)
2203 #define CAN_IER_FFIE1_Msk (0x1U << CAN_IER_FFIE1_Pos) /*!< 0x00000020 */
2204 #define CAN_IER_FFIE1 CAN_IER_FFIE1_Msk /*!<FIFO Full Interrupt Enable */
2205 #define CAN_IER_FOVIE1_Pos (6U)
2206 #define CAN_IER_FOVIE1_Msk (0x1U << CAN_IER_FOVIE1_Pos) /*!< 0x00000040 */
2207 #define CAN_IER_FOVIE1 CAN_IER_FOVIE1_Msk /*!<FIFO Overrun Interrupt Enable */
2208 #define CAN_IER_EWGIE_Pos (8U)
2209 #define CAN_IER_EWGIE_Msk (0x1U << CAN_IER_EWGIE_Pos) /*!< 0x00000100 */
2210 #define CAN_IER_EWGIE CAN_IER_EWGIE_Msk /*!<Error Warning Interrupt Enable */
2211 #define CAN_IER_EPVIE_Pos (9U)
2212 #define CAN_IER_EPVIE_Msk (0x1U << CAN_IER_EPVIE_Pos) /*!< 0x00000200 */
2213 #define CAN_IER_EPVIE CAN_IER_EPVIE_Msk /*!<Error Passive Interrupt Enable */
2214 #define CAN_IER_BOFIE_Pos (10U)
2215 #define CAN_IER_BOFIE_Msk (0x1U << CAN_IER_BOFIE_Pos) /*!< 0x00000400 */
2216 #define CAN_IER_BOFIE CAN_IER_BOFIE_Msk /*!<Bus-Off Interrupt Enable */
2217 #define CAN_IER_LECIE_Pos (11U)
2218 #define CAN_IER_LECIE_Msk (0x1U << CAN_IER_LECIE_Pos) /*!< 0x00000800 */
2219 #define CAN_IER_LECIE CAN_IER_LECIE_Msk /*!<Last Error Code Interrupt Enable */
2220 #define CAN_IER_ERRIE_Pos (15U)
2221 #define CAN_IER_ERRIE_Msk (0x1U << CAN_IER_ERRIE_Pos) /*!< 0x00008000 */
2222 #define CAN_IER_ERRIE CAN_IER_ERRIE_Msk /*!<Error Interrupt Enable */
2223 #define CAN_IER_WKUIE_Pos (16U)
2224 #define CAN_IER_WKUIE_Msk (0x1U << CAN_IER_WKUIE_Pos) /*!< 0x00010000 */
2225 #define CAN_IER_WKUIE CAN_IER_WKUIE_Msk /*!<Wakeup Interrupt Enable */
2226 #define CAN_IER_SLKIE_Pos (17U)
2227 #define CAN_IER_SLKIE_Msk (0x1U << CAN_IER_SLKIE_Pos) /*!< 0x00020000 */
2228 #define CAN_IER_SLKIE CAN_IER_SLKIE_Msk /*!<Sleep Interrupt Enable */
2229 #define CAN_IER_EWGIE_Pos (8U)
2230
2231 /******************** Bit definition for CAN_ESR register *******************/
2232 #define CAN_ESR_EWGF_Pos (0U)
2233 #define CAN_ESR_EWGF_Msk (0x1U << CAN_ESR_EWGF_Pos) /*!< 0x00000001 */
2234 #define CAN_ESR_EWGF CAN_ESR_EWGF_Msk /*!<Error Warning Flag */
2235 #define CAN_ESR_EPVF_Pos (1U)
2236 #define CAN_ESR_EPVF_Msk (0x1U << CAN_ESR_EPVF_Pos) /*!< 0x00000002 */
2237 #define CAN_ESR_EPVF CAN_ESR_EPVF_Msk /*!<Error Passive Flag */
2238 #define CAN_ESR_BOFF_Pos (2U)
2239 #define CAN_ESR_BOFF_Msk (0x1U << CAN_ESR_BOFF_Pos) /*!< 0x00000004 */
2240 #define CAN_ESR_BOFF CAN_ESR_BOFF_Msk /*!<Bus-Off Flag */
2241
2242 #define CAN_ESR_LEC_Pos (4U)
2243 #define CAN_ESR_LEC_Msk (0x7U << CAN_ESR_LEC_Pos) /*!< 0x00000070 */
2244 #define CAN_ESR_LEC CAN_ESR_LEC_Msk /*!<LEC[2:0] bits (Last Error Code) */
2245 #define CAN_ESR_LEC_0 (0x1U << CAN_ESR_LEC_Pos) /*!< 0x00000010 */
2246 #define CAN_ESR_LEC_1 (0x2U << CAN_ESR_LEC_Pos) /*!< 0x00000020 */
2247 #define CAN_ESR_LEC_2 (0x4U << CAN_ESR_LEC_Pos) /*!< 0x00000040 */
2248
2249 #define CAN_ESR_TEC_Pos (16U)
2250 #define CAN_ESR_TEC_Msk (0xFFU << CAN_ESR_TEC_Pos) /*!< 0x00FF0000 */
2251 #define CAN_ESR_TEC CAN_ESR_TEC_Msk /*!<Least significant byte of the 9-bit Transmit Error Counter */
2252 #define CAN_ESR_REC_Pos (24U)
2253 #define CAN_ESR_REC_Msk (0xFFU << CAN_ESR_REC_Pos) /*!< 0xFF000000 */
2254 #define CAN_ESR_REC CAN_ESR_REC_Msk /*!<Receive Error Counter */
2255
2256 /******************* Bit definition for CAN_BTR register ********************/
2257 #define CAN_BTR_BRP_Pos (0U)
2258 #define CAN_BTR_BRP_Msk (0x3FFU << CAN_BTR_BRP_Pos) /*!< 0x000003FF */
2259 #define CAN_BTR_BRP CAN_BTR_BRP_Msk /*!<Baud Rate Prescaler */
2260 #define CAN_BTR_TS1_Pos (16U)
2261 #define CAN_BTR_TS1_Msk (0xFU << CAN_BTR_TS1_Pos) /*!< 0x000F0000 */
2262 #define CAN_BTR_TS1 CAN_BTR_TS1_Msk /*!<Time Segment 1 */
2263 #define CAN_BTR_TS1_0 (0x1U << CAN_BTR_TS1_Pos) /*!< 0x00010000 */
2264 #define CAN_BTR_TS1_1 (0x2U << CAN_BTR_TS1_Pos) /*!< 0x00020000 */
2265 #define CAN_BTR_TS1_2 (0x4U << CAN_BTR_TS1_Pos) /*!< 0x00040000 */
2266 #define CAN_BTR_TS1_3 (0x8U << CAN_BTR_TS1_Pos) /*!< 0x00080000 */
2267 #define CAN_BTR_TS2_Pos (20U)
2268 #define CAN_BTR_TS2_Msk (0x7U << CAN_BTR_TS2_Pos) /*!< 0x00700000 */
2269 #define CAN_BTR_TS2 CAN_BTR_TS2_Msk /*!<Time Segment 2 */
2270 #define CAN_BTR_TS2_0 (0x1U << CAN_BTR_TS2_Pos) /*!< 0x00100000 */
2271 #define CAN_BTR_TS2_1 (0x2U << CAN_BTR_TS2_Pos) /*!< 0x00200000 */
2272 #define CAN_BTR_TS2_2 (0x4U << CAN_BTR_TS2_Pos) /*!< 0x00400000 */
2273 #define CAN_BTR_SJW_Pos (24U)
2274 #define CAN_BTR_SJW_Msk (0x3U << CAN_BTR_SJW_Pos) /*!< 0x03000000 */
2275 #define CAN_BTR_SJW CAN_BTR_SJW_Msk /*!<Resynchronization Jump Width */
2276 #define CAN_BTR_SJW_0 (0x1U << CAN_BTR_SJW_Pos) /*!< 0x01000000 */
2277 #define CAN_BTR_SJW_1 (0x2U << CAN_BTR_SJW_Pos) /*!< 0x02000000 */
2278 #define CAN_BTR_LBKM_Pos (30U)
2279 #define CAN_BTR_LBKM_Msk (0x1U << CAN_BTR_LBKM_Pos) /*!< 0x40000000 */
2280 #define CAN_BTR_LBKM CAN_BTR_LBKM_Msk /*!<Loop Back Mode (Debug) */
2281 #define CAN_BTR_SILM_Pos (31U)
2282 #define CAN_BTR_SILM_Msk (0x1U << CAN_BTR_SILM_Pos) /*!< 0x80000000 */
2283 #define CAN_BTR_SILM CAN_BTR_SILM_Msk /*!<Silent Mode */
2284
2285
2286 /*!<Mailbox registers */
2287 /****************** Bit definition for CAN_TI0R register ********************/
2288 #define CAN_TI0R_TXRQ_Pos (0U)
2289 #define CAN_TI0R_TXRQ_Msk (0x1U << CAN_TI0R_TXRQ_Pos) /*!< 0x00000001 */
2290 #define CAN_TI0R_TXRQ CAN_TI0R_TXRQ_Msk /*!<Transmit Mailbox Request */
2291 #define CAN_TI0R_RTR_Pos (1U)
2292 #define CAN_TI0R_RTR_Msk (0x1U << CAN_TI0R_RTR_Pos) /*!< 0x00000002 */
2293 #define CAN_TI0R_RTR CAN_TI0R_RTR_Msk /*!<Remote Transmission Request */
2294 #define CAN_TI0R_IDE_Pos (2U)
2295 #define CAN_TI0R_IDE_Msk (0x1U << CAN_TI0R_IDE_Pos) /*!< 0x00000004 */
2296 #define CAN_TI0R_IDE CAN_TI0R_IDE_Msk /*!<Identifier Extension */
2297 #define CAN_TI0R_EXID_Pos (3U)
2298 #define CAN_TI0R_EXID_Msk (0x3FFFFU << CAN_TI0R_EXID_Pos) /*!< 0x001FFFF8 */
2299 #define CAN_TI0R_EXID CAN_TI0R_EXID_Msk /*!<Extended Identifier */
2300 #define CAN_TI0R_STID_Pos (21U)
2301 #define CAN_TI0R_STID_Msk (0x7FFU << CAN_TI0R_STID_Pos) /*!< 0xFFE00000 */
2302 #define CAN_TI0R_STID CAN_TI0R_STID_Msk /*!<Standard Identifier or Extended Identifier */
2303
2304 /****************** Bit definition for CAN_TDT0R register *******************/
2305 #define CAN_TDT0R_DLC_Pos (0U)
2306 #define CAN_TDT0R_DLC_Msk (0xFU << CAN_TDT0R_DLC_Pos) /*!< 0x0000000F */
2307 #define CAN_TDT0R_DLC CAN_TDT0R_DLC_Msk /*!<Data Length Code */
2308 #define CAN_TDT0R_TGT_Pos (8U)
2309 #define CAN_TDT0R_TGT_Msk (0x1U << CAN_TDT0R_TGT_Pos) /*!< 0x00000100 */
2310 #define CAN_TDT0R_TGT CAN_TDT0R_TGT_Msk /*!<Transmit Global Time */
2311 #define CAN_TDT0R_TIME_Pos (16U)
2312 #define CAN_TDT0R_TIME_Msk (0xFFFFU << CAN_TDT0R_TIME_Pos) /*!< 0xFFFF0000 */
2313 #define CAN_TDT0R_TIME CAN_TDT0R_TIME_Msk /*!<Message Time Stamp */
2314
2315 /****************** Bit definition for CAN_TDL0R register *******************/
2316 #define CAN_TDL0R_DATA0_Pos (0U)
2317 #define CAN_TDL0R_DATA0_Msk (0xFFU << CAN_TDL0R_DATA0_Pos) /*!< 0x000000FF */
2318 #define CAN_TDL0R_DATA0 CAN_TDL0R_DATA0_Msk /*!<Data byte 0 */
2319 #define CAN_TDL0R_DATA1_Pos (8U)
2320 #define CAN_TDL0R_DATA1_Msk (0xFFU << CAN_TDL0R_DATA1_Pos) /*!< 0x0000FF00 */
2321 #define CAN_TDL0R_DATA1 CAN_TDL0R_DATA1_Msk /*!<Data byte 1 */
2322 #define CAN_TDL0R_DATA2_Pos (16U)
2323 #define CAN_TDL0R_DATA2_Msk (0xFFU << CAN_TDL0R_DATA2_Pos) /*!< 0x00FF0000 */
2324 #define CAN_TDL0R_DATA2 CAN_TDL0R_DATA2_Msk /*!<Data byte 2 */
2325 #define CAN_TDL0R_DATA3_Pos (24U)
2326 #define CAN_TDL0R_DATA3_Msk (0xFFU << CAN_TDL0R_DATA3_Pos) /*!< 0xFF000000 */
2327 #define CAN_TDL0R_DATA3 CAN_TDL0R_DATA3_Msk /*!<Data byte 3 */
2328
2329 /****************** Bit definition for CAN_TDH0R register *******************/
2330 #define CAN_TDH0R_DATA4_Pos (0U)
2331 #define CAN_TDH0R_DATA4_Msk (0xFFU << CAN_TDH0R_DATA4_Pos) /*!< 0x000000FF */
2332 #define CAN_TDH0R_DATA4 CAN_TDH0R_DATA4_Msk /*!<Data byte 4 */
2333 #define CAN_TDH0R_DATA5_Pos (8U)
2334 #define CAN_TDH0R_DATA5_Msk (0xFFU << CAN_TDH0R_DATA5_Pos) /*!< 0x0000FF00 */
2335 #define CAN_TDH0R_DATA5 CAN_TDH0R_DATA5_Msk /*!<Data byte 5 */
2336 #define CAN_TDH0R_DATA6_Pos (16U)
2337 #define CAN_TDH0R_DATA6_Msk (0xFFU << CAN_TDH0R_DATA6_Pos) /*!< 0x00FF0000 */
2338 #define CAN_TDH0R_DATA6 CAN_TDH0R_DATA6_Msk /*!<Data byte 6 */
2339 #define CAN_TDH0R_DATA7_Pos (24U)
2340 #define CAN_TDH0R_DATA7_Msk (0xFFU << CAN_TDH0R_DATA7_Pos) /*!< 0xFF000000 */
2341 #define CAN_TDH0R_DATA7 CAN_TDH0R_DATA7_Msk /*!<Data byte 7 */
2342
2343 /******************* Bit definition for CAN_TI1R register *******************/
2344 #define CAN_TI1R_TXRQ_Pos (0U)
2345 #define CAN_TI1R_TXRQ_Msk (0x1U << CAN_TI1R_TXRQ_Pos) /*!< 0x00000001 */
2346 #define CAN_TI1R_TXRQ CAN_TI1R_TXRQ_Msk /*!<Transmit Mailbox Request */
2347 #define CAN_TI1R_RTR_Pos (1U)
2348 #define CAN_TI1R_RTR_Msk (0x1U << CAN_TI1R_RTR_Pos) /*!< 0x00000002 */
2349 #define CAN_TI1R_RTR CAN_TI1R_RTR_Msk /*!<Remote Transmission Request */
2350 #define CAN_TI1R_IDE_Pos (2U)
2351 #define CAN_TI1R_IDE_Msk (0x1U << CAN_TI1R_IDE_Pos) /*!< 0x00000004 */
2352 #define CAN_TI1R_IDE CAN_TI1R_IDE_Msk /*!<Identifier Extension */
2353 #define CAN_TI1R_EXID_Pos (3U)
2354 #define CAN_TI1R_EXID_Msk (0x3FFFFU << CAN_TI1R_EXID_Pos) /*!< 0x001FFFF8 */
2355 #define CAN_TI1R_EXID CAN_TI1R_EXID_Msk /*!<Extended Identifier */
2356 #define CAN_TI1R_STID_Pos (21U)
2357 #define CAN_TI1R_STID_Msk (0x7FFU << CAN_TI1R_STID_Pos) /*!< 0xFFE00000 */
2358 #define CAN_TI1R_STID CAN_TI1R_STID_Msk /*!<Standard Identifier or Extended Identifier */
2359
2360 /******************* Bit definition for CAN_TDT1R register ******************/
2361 #define CAN_TDT1R_DLC_Pos (0U)
2362 #define CAN_TDT1R_DLC_Msk (0xFU << CAN_TDT1R_DLC_Pos) /*!< 0x0000000F */
2363 #define CAN_TDT1R_DLC CAN_TDT1R_DLC_Msk /*!<Data Length Code */
2364 #define CAN_TDT1R_TGT_Pos (8U)
2365 #define CAN_TDT1R_TGT_Msk (0x1U << CAN_TDT1R_TGT_Pos) /*!< 0x00000100 */
2366 #define CAN_TDT1R_TGT CAN_TDT1R_TGT_Msk /*!<Transmit Global Time */
2367 #define CAN_TDT1R_TIME_Pos (16U)
2368 #define CAN_TDT1R_TIME_Msk (0xFFFFU << CAN_TDT1R_TIME_Pos) /*!< 0xFFFF0000 */
2369 #define CAN_TDT1R_TIME CAN_TDT1R_TIME_Msk /*!<Message Time Stamp */
2370
2371 /******************* Bit definition for CAN_TDL1R register ******************/
2372 #define CAN_TDL1R_DATA0_Pos (0U)
2373 #define CAN_TDL1R_DATA0_Msk (0xFFU << CAN_TDL1R_DATA0_Pos) /*!< 0x000000FF */
2374 #define CAN_TDL1R_DATA0 CAN_TDL1R_DATA0_Msk /*!<Data byte 0 */
2375 #define CAN_TDL1R_DATA1_Pos (8U)
2376 #define CAN_TDL1R_DATA1_Msk (0xFFU << CAN_TDL1R_DATA1_Pos) /*!< 0x0000FF00 */
2377 #define CAN_TDL1R_DATA1 CAN_TDL1R_DATA1_Msk /*!<Data byte 1 */
2378 #define CAN_TDL1R_DATA2_Pos (16U)
2379 #define CAN_TDL1R_DATA2_Msk (0xFFU << CAN_TDL1R_DATA2_Pos) /*!< 0x00FF0000 */
2380 #define CAN_TDL1R_DATA2 CAN_TDL1R_DATA2_Msk /*!<Data byte 2 */
2381 #define CAN_TDL1R_DATA3_Pos (24U)
2382 #define CAN_TDL1R_DATA3_Msk (0xFFU << CAN_TDL1R_DATA3_Pos) /*!< 0xFF000000 */
2383 #define CAN_TDL1R_DATA3 CAN_TDL1R_DATA3_Msk /*!<Data byte 3 */
2384
2385 /******************* Bit definition for CAN_TDH1R register ******************/
2386 #define CAN_TDH1R_DATA4_Pos (0U)
2387 #define CAN_TDH1R_DATA4_Msk (0xFFU << CAN_TDH1R_DATA4_Pos) /*!< 0x000000FF */
2388 #define CAN_TDH1R_DATA4 CAN_TDH1R_DATA4_Msk /*!<Data byte 4 */
2389 #define CAN_TDH1R_DATA5_Pos (8U)
2390 #define CAN_TDH1R_DATA5_Msk (0xFFU << CAN_TDH1R_DATA5_Pos) /*!< 0x0000FF00 */
2391 #define CAN_TDH1R_DATA5 CAN_TDH1R_DATA5_Msk /*!<Data byte 5 */
2392 #define CAN_TDH1R_DATA6_Pos (16U)
2393 #define CAN_TDH1R_DATA6_Msk (0xFFU << CAN_TDH1R_DATA6_Pos) /*!< 0x00FF0000 */
2394 #define CAN_TDH1R_DATA6 CAN_TDH1R_DATA6_Msk /*!<Data byte 6 */
2395 #define CAN_TDH1R_DATA7_Pos (24U)
2396 #define CAN_TDH1R_DATA7_Msk (0xFFU << CAN_TDH1R_DATA7_Pos) /*!< 0xFF000000 */
2397 #define CAN_TDH1R_DATA7 CAN_TDH1R_DATA7_Msk /*!<Data byte 7 */
2398
2399 /******************* Bit definition for CAN_TI2R register *******************/
2400 #define CAN_TI2R_TXRQ_Pos (0U)
2401 #define CAN_TI2R_TXRQ_Msk (0x1U << CAN_TI2R_TXRQ_Pos) /*!< 0x00000001 */
2402 #define CAN_TI2R_TXRQ CAN_TI2R_TXRQ_Msk /*!<Transmit Mailbox Request */
2403 #define CAN_TI2R_RTR_Pos (1U)
2404 #define CAN_TI2R_RTR_Msk (0x1U << CAN_TI2R_RTR_Pos) /*!< 0x00000002 */
2405 #define CAN_TI2R_RTR CAN_TI2R_RTR_Msk /*!<Remote Transmission Request */
2406 #define CAN_TI2R_IDE_Pos (2U)
2407 #define CAN_TI2R_IDE_Msk (0x1U << CAN_TI2R_IDE_Pos) /*!< 0x00000004 */
2408 #define CAN_TI2R_IDE CAN_TI2R_IDE_Msk /*!<Identifier Extension */
2409 #define CAN_TI2R_EXID_Pos (3U)
2410 #define CAN_TI2R_EXID_Msk (0x3FFFFU << CAN_TI2R_EXID_Pos) /*!< 0x001FFFF8 */
2411 #define CAN_TI2R_EXID CAN_TI2R_EXID_Msk /*!<Extended identifier */
2412 #define CAN_TI2R_STID_Pos (21U)
2413 #define CAN_TI2R_STID_Msk (0x7FFU << CAN_TI2R_STID_Pos) /*!< 0xFFE00000 */
2414 #define CAN_TI2R_STID CAN_TI2R_STID_Msk /*!<Standard Identifier or Extended Identifier */
2415
2416 /******************* Bit definition for CAN_TDT2R register ******************/
2417 #define CAN_TDT2R_DLC_Pos (0U)
2418 #define CAN_TDT2R_DLC_Msk (0xFU << CAN_TDT2R_DLC_Pos) /*!< 0x0000000F */
2419 #define CAN_TDT2R_DLC CAN_TDT2R_DLC_Msk /*!<Data Length Code */
2420 #define CAN_TDT2R_TGT_Pos (8U)
2421 #define CAN_TDT2R_TGT_Msk (0x1U << CAN_TDT2R_TGT_Pos) /*!< 0x00000100 */
2422 #define CAN_TDT2R_TGT CAN_TDT2R_TGT_Msk /*!<Transmit Global Time */
2423 #define CAN_TDT2R_TIME_Pos (16U)
2424 #define CAN_TDT2R_TIME_Msk (0xFFFFU << CAN_TDT2R_TIME_Pos) /*!< 0xFFFF0000 */
2425 #define CAN_TDT2R_TIME CAN_TDT2R_TIME_Msk /*!<Message Time Stamp */
2426
2427 /******************* Bit definition for CAN_TDL2R register ******************/
2428 #define CAN_TDL2R_DATA0_Pos (0U)
2429 #define CAN_TDL2R_DATA0_Msk (0xFFU << CAN_TDL2R_DATA0_Pos) /*!< 0x000000FF */
2430 #define CAN_TDL2R_DATA0 CAN_TDL2R_DATA0_Msk /*!<Data byte 0 */
2431 #define CAN_TDL2R_DATA1_Pos (8U)
2432 #define CAN_TDL2R_DATA1_Msk (0xFFU << CAN_TDL2R_DATA1_Pos) /*!< 0x0000FF00 */
2433 #define CAN_TDL2R_DATA1 CAN_TDL2R_DATA1_Msk /*!<Data byte 1 */
2434 #define CAN_TDL2R_DATA2_Pos (16U)
2435 #define CAN_TDL2R_DATA2_Msk (0xFFU << CAN_TDL2R_DATA2_Pos) /*!< 0x00FF0000 */
2436 #define CAN_TDL2R_DATA2 CAN_TDL2R_DATA2_Msk /*!<Data byte 2 */
2437 #define CAN_TDL2R_DATA3_Pos (24U)
2438 #define CAN_TDL2R_DATA3_Msk (0xFFU << CAN_TDL2R_DATA3_Pos) /*!< 0xFF000000 */
2439 #define CAN_TDL2R_DATA3 CAN_TDL2R_DATA3_Msk /*!<Data byte 3 */
2440
2441 /******************* Bit definition for CAN_TDH2R register ******************/
2442 #define CAN_TDH2R_DATA4_Pos (0U)
2443 #define CAN_TDH2R_DATA4_Msk (0xFFU << CAN_TDH2R_DATA4_Pos) /*!< 0x000000FF */
2444 #define CAN_TDH2R_DATA4 CAN_TDH2R_DATA4_Msk /*!<Data byte 4 */
2445 #define CAN_TDH2R_DATA5_Pos (8U)
2446 #define CAN_TDH2R_DATA5_Msk (0xFFU << CAN_TDH2R_DATA5_Pos) /*!< 0x0000FF00 */
2447 #define CAN_TDH2R_DATA5 CAN_TDH2R_DATA5_Msk /*!<Data byte 5 */
2448 #define CAN_TDH2R_DATA6_Pos (16U)
2449 #define CAN_TDH2R_DATA6_Msk (0xFFU << CAN_TDH2R_DATA6_Pos) /*!< 0x00FF0000 */
2450 #define CAN_TDH2R_DATA6 CAN_TDH2R_DATA6_Msk /*!<Data byte 6 */
2451 #define CAN_TDH2R_DATA7_Pos (24U)
2452 #define CAN_TDH2R_DATA7_Msk (0xFFU << CAN_TDH2R_DATA7_Pos) /*!< 0xFF000000 */
2453 #define CAN_TDH2R_DATA7 CAN_TDH2R_DATA7_Msk /*!<Data byte 7 */
2454
2455 /******************* Bit definition for CAN_RI0R register *******************/
2456 #define CAN_RI0R_RTR_Pos (1U)
2457 #define CAN_RI0R_RTR_Msk (0x1U << CAN_RI0R_RTR_Pos) /*!< 0x00000002 */
2458 #define CAN_RI0R_RTR CAN_RI0R_RTR_Msk /*!<Remote Transmission Request */
2459 #define CAN_RI0R_IDE_Pos (2U)
2460 #define CAN_RI0R_IDE_Msk (0x1U << CAN_RI0R_IDE_Pos) /*!< 0x00000004 */
2461 #define CAN_RI0R_IDE CAN_RI0R_IDE_Msk /*!<Identifier Extension */
2462 #define CAN_RI0R_EXID_Pos (3U)
2463 #define CAN_RI0R_EXID_Msk (0x3FFFFU << CAN_RI0R_EXID_Pos) /*!< 0x001FFFF8 */
2464 #define CAN_RI0R_EXID CAN_RI0R_EXID_Msk /*!<Extended Identifier */
2465 #define CAN_RI0R_STID_Pos (21U)
2466 #define CAN_RI0R_STID_Msk (0x7FFU << CAN_RI0R_STID_Pos) /*!< 0xFFE00000 */
2467 #define CAN_RI0R_STID CAN_RI0R_STID_Msk /*!<Standard Identifier or Extended Identifier */
2468
2469 /******************* Bit definition for CAN_RDT0R register ******************/
2470 #define CAN_RDT0R_DLC_Pos (0U)
2471 #define CAN_RDT0R_DLC_Msk (0xFU << CAN_RDT0R_DLC_Pos) /*!< 0x0000000F */
2472 #define CAN_RDT0R_DLC CAN_RDT0R_DLC_Msk /*!<Data Length Code */
2473 #define CAN_RDT0R_FMI_Pos (8U)
2474 #define CAN_RDT0R_FMI_Msk (0xFFU << CAN_RDT0R_FMI_Pos) /*!< 0x0000FF00 */
2475 #define CAN_RDT0R_FMI CAN_RDT0R_FMI_Msk /*!<Filter Match Index */
2476 #define CAN_RDT0R_TIME_Pos (16U)
2477 #define CAN_RDT0R_TIME_Msk (0xFFFFU << CAN_RDT0R_TIME_Pos) /*!< 0xFFFF0000 */
2478 #define CAN_RDT0R_TIME CAN_RDT0R_TIME_Msk /*!<Message Time Stamp */
2479
2480 /******************* Bit definition for CAN_RDL0R register ******************/
2481 #define CAN_RDL0R_DATA0_Pos (0U)
2482 #define CAN_RDL0R_DATA0_Msk (0xFFU << CAN_RDL0R_DATA0_Pos) /*!< 0x000000FF */
2483 #define CAN_RDL0R_DATA0 CAN_RDL0R_DATA0_Msk /*!<Data byte 0 */
2484 #define CAN_RDL0R_DATA1_Pos (8U)
2485 #define CAN_RDL0R_DATA1_Msk (0xFFU << CAN_RDL0R_DATA1_Pos) /*!< 0x0000FF00 */
2486 #define CAN_RDL0R_DATA1 CAN_RDL0R_DATA1_Msk /*!<Data byte 1 */
2487 #define CAN_RDL0R_DATA2_Pos (16U)
2488 #define CAN_RDL0R_DATA2_Msk (0xFFU << CAN_RDL0R_DATA2_Pos) /*!< 0x00FF0000 */
2489 #define CAN_RDL0R_DATA2 CAN_RDL0R_DATA2_Msk /*!<Data byte 2 */
2490 #define CAN_RDL0R_DATA3_Pos (24U)
2491 #define CAN_RDL0R_DATA3_Msk (0xFFU << CAN_RDL0R_DATA3_Pos) /*!< 0xFF000000 */
2492 #define CAN_RDL0R_DATA3 CAN_RDL0R_DATA3_Msk /*!<Data byte 3 */
2493
2494 /******************* Bit definition for CAN_RDH0R register ******************/
2495 #define CAN_RDH0R_DATA4_Pos (0U)
2496 #define CAN_RDH0R_DATA4_Msk (0xFFU << CAN_RDH0R_DATA4_Pos) /*!< 0x000000FF */
2497 #define CAN_RDH0R_DATA4 CAN_RDH0R_DATA4_Msk /*!<Data byte 4 */
2498 #define CAN_RDH0R_DATA5_Pos (8U)
2499 #define CAN_RDH0R_DATA5_Msk (0xFFU << CAN_RDH0R_DATA5_Pos) /*!< 0x0000FF00 */
2500 #define CAN_RDH0R_DATA5 CAN_RDH0R_DATA5_Msk /*!<Data byte 5 */
2501 #define CAN_RDH0R_DATA6_Pos (16U)
2502 #define CAN_RDH0R_DATA6_Msk (0xFFU << CAN_RDH0R_DATA6_Pos) /*!< 0x00FF0000 */
2503 #define CAN_RDH0R_DATA6 CAN_RDH0R_DATA6_Msk /*!<Data byte 6 */
2504 #define CAN_RDH0R_DATA7_Pos (24U)
2505 #define CAN_RDH0R_DATA7_Msk (0xFFU << CAN_RDH0R_DATA7_Pos) /*!< 0xFF000000 */
2506 #define CAN_RDH0R_DATA7 CAN_RDH0R_DATA7_Msk /*!<Data byte 7 */
2507
2508 /******************* Bit definition for CAN_RI1R register *******************/
2509 #define CAN_RI1R_RTR_Pos (1U)
2510 #define CAN_RI1R_RTR_Msk (0x1U << CAN_RI1R_RTR_Pos) /*!< 0x00000002 */
2511 #define CAN_RI1R_RTR CAN_RI1R_RTR_Msk /*!<Remote Transmission Request */
2512 #define CAN_RI1R_IDE_Pos (2U)
2513 #define CAN_RI1R_IDE_Msk (0x1U << CAN_RI1R_IDE_Pos) /*!< 0x00000004 */
2514 #define CAN_RI1R_IDE CAN_RI1R_IDE_Msk /*!<Identifier Extension */
2515 #define CAN_RI1R_EXID_Pos (3U)
2516 #define CAN_RI1R_EXID_Msk (0x3FFFFU << CAN_RI1R_EXID_Pos) /*!< 0x001FFFF8 */
2517 #define CAN_RI1R_EXID CAN_RI1R_EXID_Msk /*!<Extended identifier */
2518 #define CAN_RI1R_STID_Pos (21U)
2519 #define CAN_RI1R_STID_Msk (0x7FFU << CAN_RI1R_STID_Pos) /*!< 0xFFE00000 */
2520 #define CAN_RI1R_STID CAN_RI1R_STID_Msk /*!<Standard Identifier or Extended Identifier */
2521
2522 /******************* Bit definition for CAN_RDT1R register ******************/
2523 #define CAN_RDT1R_DLC_Pos (0U)
2524 #define CAN_RDT1R_DLC_Msk (0xFU << CAN_RDT1R_DLC_Pos) /*!< 0x0000000F */
2525 #define CAN_RDT1R_DLC CAN_RDT1R_DLC_Msk /*!<Data Length Code */
2526 #define CAN_RDT1R_FMI_Pos (8U)
2527 #define CAN_RDT1R_FMI_Msk (0xFFU << CAN_RDT1R_FMI_Pos) /*!< 0x0000FF00 */
2528 #define CAN_RDT1R_FMI CAN_RDT1R_FMI_Msk /*!<Filter Match Index */
2529 #define CAN_RDT1R_TIME_Pos (16U)
2530 #define CAN_RDT1R_TIME_Msk (0xFFFFU << CAN_RDT1R_TIME_Pos) /*!< 0xFFFF0000 */
2531 #define CAN_RDT1R_TIME CAN_RDT1R_TIME_Msk /*!<Message Time Stamp */
2532
2533 /******************* Bit definition for CAN_RDL1R register ******************/
2534 #define CAN_RDL1R_DATA0_Pos (0U)
2535 #define CAN_RDL1R_DATA0_Msk (0xFFU << CAN_RDL1R_DATA0_Pos) /*!< 0x000000FF */
2536 #define CAN_RDL1R_DATA0 CAN_RDL1R_DATA0_Msk /*!<Data byte 0 */
2537 #define CAN_RDL1R_DATA1_Pos (8U)
2538 #define CAN_RDL1R_DATA1_Msk (0xFFU << CAN_RDL1R_DATA1_Pos) /*!< 0x0000FF00 */
2539 #define CAN_RDL1R_DATA1 CAN_RDL1R_DATA1_Msk /*!<Data byte 1 */
2540 #define CAN_RDL1R_DATA2_Pos (16U)
2541 #define CAN_RDL1R_DATA2_Msk (0xFFU << CAN_RDL1R_DATA2_Pos) /*!< 0x00FF0000 */
2542 #define CAN_RDL1R_DATA2 CAN_RDL1R_DATA2_Msk /*!<Data byte 2 */
2543 #define CAN_RDL1R_DATA3_Pos (24U)
2544 #define CAN_RDL1R_DATA3_Msk (0xFFU << CAN_RDL1R_DATA3_Pos) /*!< 0xFF000000 */
2545 #define CAN_RDL1R_DATA3 CAN_RDL1R_DATA3_Msk /*!<Data byte 3 */
2546
2547 /******************* Bit definition for CAN_RDH1R register ******************/
2548 #define CAN_RDH1R_DATA4_Pos (0U)
2549 #define CAN_RDH1R_DATA4_Msk (0xFFU << CAN_RDH1R_DATA4_Pos) /*!< 0x000000FF */
2550 #define CAN_RDH1R_DATA4 CAN_RDH1R_DATA4_Msk /*!<Data byte 4 */
2551 #define CAN_RDH1R_DATA5_Pos (8U)
2552 #define CAN_RDH1R_DATA5_Msk (0xFFU << CAN_RDH1R_DATA5_Pos) /*!< 0x0000FF00 */
2553 #define CAN_RDH1R_DATA5 CAN_RDH1R_DATA5_Msk /*!<Data byte 5 */
2554 #define CAN_RDH1R_DATA6_Pos (16U)
2555 #define CAN_RDH1R_DATA6_Msk (0xFFU << CAN_RDH1R_DATA6_Pos) /*!< 0x00FF0000 */
2556 #define CAN_RDH1R_DATA6 CAN_RDH1R_DATA6_Msk /*!<Data byte 6 */
2557 #define CAN_RDH1R_DATA7_Pos (24U)
2558 #define CAN_RDH1R_DATA7_Msk (0xFFU << CAN_RDH1R_DATA7_Pos) /*!< 0xFF000000 */
2559 #define CAN_RDH1R_DATA7 CAN_RDH1R_DATA7_Msk /*!<Data byte 7 */
2560
2561 /*!<CAN filter registers */
2562 /******************* Bit definition for CAN_FMR register ********************/
2563 #define CAN_FMR_FINIT_Pos (0U)
2564 #define CAN_FMR_FINIT_Msk (0x1U << CAN_FMR_FINIT_Pos) /*!< 0x00000001 */
2565 #define CAN_FMR_FINIT CAN_FMR_FINIT_Msk /*!<Filter Init Mode */
2566 #define CAN_FMR_CAN2SB_Pos (8U)
2567 #define CAN_FMR_CAN2SB_Msk (0x3FU << CAN_FMR_CAN2SB_Pos) /*!< 0x00003F00 */
2568 #define CAN_FMR_CAN2SB CAN_FMR_CAN2SB_Msk /*!<CAN2 start bank */
2569
2570 /******************* Bit definition for CAN_FM1R register *******************/
2571 #define CAN_FM1R_FBM_Pos (0U)
2572 #define CAN_FM1R_FBM_Msk (0xFFFFFFFU << CAN_FM1R_FBM_Pos) /*!< 0x0FFFFFFF */
2573 #define CAN_FM1R_FBM CAN_FM1R_FBM_Msk /*!<Filter Mode */
2574 #define CAN_FM1R_FBM0_Pos (0U)
2575 #define CAN_FM1R_FBM0_Msk (0x1U << CAN_FM1R_FBM0_Pos) /*!< 0x00000001 */
2576 #define CAN_FM1R_FBM0 CAN_FM1R_FBM0_Msk /*!<Filter Init Mode bit 0 */
2577 #define CAN_FM1R_FBM1_Pos (1U)
2578 #define CAN_FM1R_FBM1_Msk (0x1U << CAN_FM1R_FBM1_Pos) /*!< 0x00000002 */
2579 #define CAN_FM1R_FBM1 CAN_FM1R_FBM1_Msk /*!<Filter Init Mode bit 1 */
2580 #define CAN_FM1R_FBM2_Pos (2U)
2581 #define CAN_FM1R_FBM2_Msk (0x1U << CAN_FM1R_FBM2_Pos) /*!< 0x00000004 */
2582 #define CAN_FM1R_FBM2 CAN_FM1R_FBM2_Msk /*!<Filter Init Mode bit 2 */
2583 #define CAN_FM1R_FBM3_Pos (3U)
2584 #define CAN_FM1R_FBM3_Msk (0x1U << CAN_FM1R_FBM3_Pos) /*!< 0x00000008 */
2585 #define CAN_FM1R_FBM3 CAN_FM1R_FBM3_Msk /*!<Filter Init Mode bit 3 */
2586 #define CAN_FM1R_FBM4_Pos (4U)
2587 #define CAN_FM1R_FBM4_Msk (0x1U << CAN_FM1R_FBM4_Pos) /*!< 0x00000010 */
2588 #define CAN_FM1R_FBM4 CAN_FM1R_FBM4_Msk /*!<Filter Init Mode bit 4 */
2589 #define CAN_FM1R_FBM5_Pos (5U)
2590 #define CAN_FM1R_FBM5_Msk (0x1U << CAN_FM1R_FBM5_Pos) /*!< 0x00000020 */
2591 #define CAN_FM1R_FBM5 CAN_FM1R_FBM5_Msk /*!<Filter Init Mode bit 5 */
2592 #define CAN_FM1R_FBM6_Pos (6U)
2593 #define CAN_FM1R_FBM6_Msk (0x1U << CAN_FM1R_FBM6_Pos) /*!< 0x00000040 */
2594 #define CAN_FM1R_FBM6 CAN_FM1R_FBM6_Msk /*!<Filter Init Mode bit 6 */
2595 #define CAN_FM1R_FBM7_Pos (7U)
2596 #define CAN_FM1R_FBM7_Msk (0x1U << CAN_FM1R_FBM7_Pos) /*!< 0x00000080 */
2597 #define CAN_FM1R_FBM7 CAN_FM1R_FBM7_Msk /*!<Filter Init Mode bit 7 */
2598 #define CAN_FM1R_FBM8_Pos (8U)
2599 #define CAN_FM1R_FBM8_Msk (0x1U << CAN_FM1R_FBM8_Pos) /*!< 0x00000100 */
2600 #define CAN_FM1R_FBM8 CAN_FM1R_FBM8_Msk /*!<Filter Init Mode bit 8 */
2601 #define CAN_FM1R_FBM9_Pos (9U)
2602 #define CAN_FM1R_FBM9_Msk (0x1U << CAN_FM1R_FBM9_Pos) /*!< 0x00000200 */
2603 #define CAN_FM1R_FBM9 CAN_FM1R_FBM9_Msk /*!<Filter Init Mode bit 9 */
2604 #define CAN_FM1R_FBM10_Pos (10U)
2605 #define CAN_FM1R_FBM10_Msk (0x1U << CAN_FM1R_FBM10_Pos) /*!< 0x00000400 */
2606 #define CAN_FM1R_FBM10 CAN_FM1R_FBM10_Msk /*!<Filter Init Mode bit 10 */
2607 #define CAN_FM1R_FBM11_Pos (11U)
2608 #define CAN_FM1R_FBM11_Msk (0x1U << CAN_FM1R_FBM11_Pos) /*!< 0x00000800 */
2609 #define CAN_FM1R_FBM11 CAN_FM1R_FBM11_Msk /*!<Filter Init Mode bit 11 */
2610 #define CAN_FM1R_FBM12_Pos (12U)
2611 #define CAN_FM1R_FBM12_Msk (0x1U << CAN_FM1R_FBM12_Pos) /*!< 0x00001000 */
2612 #define CAN_FM1R_FBM12 CAN_FM1R_FBM12_Msk /*!<Filter Init Mode bit 12 */
2613 #define CAN_FM1R_FBM13_Pos (13U)
2614 #define CAN_FM1R_FBM13_Msk (0x1U << CAN_FM1R_FBM13_Pos) /*!< 0x00002000 */
2615 #define CAN_FM1R_FBM13 CAN_FM1R_FBM13_Msk /*!<Filter Init Mode bit 13 */
2616 #define CAN_FM1R_FBM14_Pos (14U)
2617 #define CAN_FM1R_FBM14_Msk (0x1U << CAN_FM1R_FBM14_Pos) /*!< 0x00004000 */
2618 #define CAN_FM1R_FBM14 CAN_FM1R_FBM14_Msk /*!<Filter Init Mode bit 14 */
2619 #define CAN_FM1R_FBM15_Pos (15U)
2620 #define CAN_FM1R_FBM15_Msk (0x1U << CAN_FM1R_FBM15_Pos) /*!< 0x00008000 */
2621 #define CAN_FM1R_FBM15 CAN_FM1R_FBM15_Msk /*!<Filter Init Mode bit 15 */
2622 #define CAN_FM1R_FBM16_Pos (16U)
2623 #define CAN_FM1R_FBM16_Msk (0x1U << CAN_FM1R_FBM16_Pos) /*!< 0x00010000 */
2624 #define CAN_FM1R_FBM16 CAN_FM1R_FBM16_Msk /*!<Filter Init Mode bit 16 */
2625 #define CAN_FM1R_FBM17_Pos (17U)
2626 #define CAN_FM1R_FBM17_Msk (0x1U << CAN_FM1R_FBM17_Pos) /*!< 0x00020000 */
2627 #define CAN_FM1R_FBM17 CAN_FM1R_FBM17_Msk /*!<Filter Init Mode bit 17 */
2628 #define CAN_FM1R_FBM18_Pos (18U)
2629 #define CAN_FM1R_FBM18_Msk (0x1U << CAN_FM1R_FBM18_Pos) /*!< 0x00040000 */
2630 #define CAN_FM1R_FBM18 CAN_FM1R_FBM18_Msk /*!<Filter Init Mode bit 18 */
2631 #define CAN_FM1R_FBM19_Pos (19U)
2632 #define CAN_FM1R_FBM19_Msk (0x1U << CAN_FM1R_FBM19_Pos) /*!< 0x00080000 */
2633 #define CAN_FM1R_FBM19 CAN_FM1R_FBM19_Msk /*!<Filter Init Mode bit 19 */
2634 #define CAN_FM1R_FBM20_Pos (20U)
2635 #define CAN_FM1R_FBM20_Msk (0x1U << CAN_FM1R_FBM20_Pos) /*!< 0x00100000 */
2636 #define CAN_FM1R_FBM20 CAN_FM1R_FBM20_Msk /*!<Filter Init Mode bit 20 */
2637 #define CAN_FM1R_FBM21_Pos (21U)
2638 #define CAN_FM1R_FBM21_Msk (0x1U << CAN_FM1R_FBM21_Pos) /*!< 0x00200000 */
2639 #define CAN_FM1R_FBM21 CAN_FM1R_FBM21_Msk /*!<Filter Init Mode bit 21 */
2640 #define CAN_FM1R_FBM22_Pos (22U)
2641 #define CAN_FM1R_FBM22_Msk (0x1U << CAN_FM1R_FBM22_Pos) /*!< 0x00400000 */
2642 #define CAN_FM1R_FBM22 CAN_FM1R_FBM22_Msk /*!<Filter Init Mode bit 22 */
2643 #define CAN_FM1R_FBM23_Pos (23U)
2644 #define CAN_FM1R_FBM23_Msk (0x1U << CAN_FM1R_FBM23_Pos) /*!< 0x00800000 */
2645 #define CAN_FM1R_FBM23 CAN_FM1R_FBM23_Msk /*!<Filter Init Mode bit 23 */
2646 #define CAN_FM1R_FBM24_Pos (24U)
2647 #define CAN_FM1R_FBM24_Msk (0x1U << CAN_FM1R_FBM24_Pos) /*!< 0x01000000 */
2648 #define CAN_FM1R_FBM24 CAN_FM1R_FBM24_Msk /*!<Filter Init Mode bit 24 */
2649 #define CAN_FM1R_FBM25_Pos (25U)
2650 #define CAN_FM1R_FBM25_Msk (0x1U << CAN_FM1R_FBM25_Pos) /*!< 0x02000000 */
2651 #define CAN_FM1R_FBM25 CAN_FM1R_FBM25_Msk /*!<Filter Init Mode bit 25 */
2652 #define CAN_FM1R_FBM26_Pos (26U)
2653 #define CAN_FM1R_FBM26_Msk (0x1U << CAN_FM1R_FBM26_Pos) /*!< 0x04000000 */
2654 #define CAN_FM1R_FBM26 CAN_FM1R_FBM26_Msk /*!<Filter Init Mode bit 26 */
2655 #define CAN_FM1R_FBM27_Pos (27U)
2656 #define CAN_FM1R_FBM27_Msk (0x1U << CAN_FM1R_FBM27_Pos) /*!< 0x08000000 */
2657 #define CAN_FM1R_FBM27 CAN_FM1R_FBM27_Msk /*!<Filter Init Mode bit 27 */
2658
2659 /******************* Bit definition for CAN_FS1R register *******************/
2660 #define CAN_FS1R_FSC_Pos (0U)
2661 #define CAN_FS1R_FSC_Msk (0xFFFFFFFU << CAN_FS1R_FSC_Pos) /*!< 0x0FFFFFFF */
2662 #define CAN_FS1R_FSC CAN_FS1R_FSC_Msk /*!<Filter Scale Configuration */
2663 #define CAN_FS1R_FSC0_Pos (0U)
2664 #define CAN_FS1R_FSC0_Msk (0x1U << CAN_FS1R_FSC0_Pos) /*!< 0x00000001 */
2665 #define CAN_FS1R_FSC0 CAN_FS1R_FSC0_Msk /*!<Filter Scale Configuration bit 0 */
2666 #define CAN_FS1R_FSC1_Pos (1U)
2667 #define CAN_FS1R_FSC1_Msk (0x1U << CAN_FS1R_FSC1_Pos) /*!< 0x00000002 */
2668 #define CAN_FS1R_FSC1 CAN_FS1R_FSC1_Msk /*!<Filter Scale Configuration bit 1 */
2669 #define CAN_FS1R_FSC2_Pos (2U)
2670 #define CAN_FS1R_FSC2_Msk (0x1U << CAN_FS1R_FSC2_Pos) /*!< 0x00000004 */
2671 #define CAN_FS1R_FSC2 CAN_FS1R_FSC2_Msk /*!<Filter Scale Configuration bit 2 */
2672 #define CAN_FS1R_FSC3_Pos (3U)
2673 #define CAN_FS1R_FSC3_Msk (0x1U << CAN_FS1R_FSC3_Pos) /*!< 0x00000008 */
2674 #define CAN_FS1R_FSC3 CAN_FS1R_FSC3_Msk /*!<Filter Scale Configuration bit 3 */
2675 #define CAN_FS1R_FSC4_Pos (4U)
2676 #define CAN_FS1R_FSC4_Msk (0x1U << CAN_FS1R_FSC4_Pos) /*!< 0x00000010 */
2677 #define CAN_FS1R_FSC4 CAN_FS1R_FSC4_Msk /*!<Filter Scale Configuration bit 4 */
2678 #define CAN_FS1R_FSC5_Pos (5U)
2679 #define CAN_FS1R_FSC5_Msk (0x1U << CAN_FS1R_FSC5_Pos) /*!< 0x00000020 */
2680 #define CAN_FS1R_FSC5 CAN_FS1R_FSC5_Msk /*!<Filter Scale Configuration bit 5 */
2681 #define CAN_FS1R_FSC6_Pos (6U)
2682 #define CAN_FS1R_FSC6_Msk (0x1U << CAN_FS1R_FSC6_Pos) /*!< 0x00000040 */
2683 #define CAN_FS1R_FSC6 CAN_FS1R_FSC6_Msk /*!<Filter Scale Configuration bit 6 */
2684 #define CAN_FS1R_FSC7_Pos (7U)
2685 #define CAN_FS1R_FSC7_Msk (0x1U << CAN_FS1R_FSC7_Pos) /*!< 0x00000080 */
2686 #define CAN_FS1R_FSC7 CAN_FS1R_FSC7_Msk /*!<Filter Scale Configuration bit 7 */
2687 #define CAN_FS1R_FSC8_Pos (8U)
2688 #define CAN_FS1R_FSC8_Msk (0x1U << CAN_FS1R_FSC8_Pos) /*!< 0x00000100 */
2689 #define CAN_FS1R_FSC8 CAN_FS1R_FSC8_Msk /*!<Filter Scale Configuration bit 8 */
2690 #define CAN_FS1R_FSC9_Pos (9U)
2691 #define CAN_FS1R_FSC9_Msk (0x1U << CAN_FS1R_FSC9_Pos) /*!< 0x00000200 */
2692 #define CAN_FS1R_FSC9 CAN_FS1R_FSC9_Msk /*!<Filter Scale Configuration bit 9 */
2693 #define CAN_FS1R_FSC10_Pos (10U)
2694 #define CAN_FS1R_FSC10_Msk (0x1U << CAN_FS1R_FSC10_Pos) /*!< 0x00000400 */
2695 #define CAN_FS1R_FSC10 CAN_FS1R_FSC10_Msk /*!<Filter Scale Configuration bit 10 */
2696 #define CAN_FS1R_FSC11_Pos (11U)
2697 #define CAN_FS1R_FSC11_Msk (0x1U << CAN_FS1R_FSC11_Pos) /*!< 0x00000800 */
2698 #define CAN_FS1R_FSC11 CAN_FS1R_FSC11_Msk /*!<Filter Scale Configuration bit 11 */
2699 #define CAN_FS1R_FSC12_Pos (12U)
2700 #define CAN_FS1R_FSC12_Msk (0x1U << CAN_FS1R_FSC12_Pos) /*!< 0x00001000 */
2701 #define CAN_FS1R_FSC12 CAN_FS1R_FSC12_Msk /*!<Filter Scale Configuration bit 12 */
2702 #define CAN_FS1R_FSC13_Pos (13U)
2703 #define CAN_FS1R_FSC13_Msk (0x1U << CAN_FS1R_FSC13_Pos) /*!< 0x00002000 */
2704 #define CAN_FS1R_FSC13 CAN_FS1R_FSC13_Msk /*!<Filter Scale Configuration bit 13 */
2705 #define CAN_FS1R_FSC14_Pos (14U)
2706 #define CAN_FS1R_FSC14_Msk (0x1U << CAN_FS1R_FSC14_Pos) /*!< 0x00004000 */
2707 #define CAN_FS1R_FSC14 CAN_FS1R_FSC14_Msk /*!<Filter Scale Configuration bit 14 */
2708 #define CAN_FS1R_FSC15_Pos (15U)
2709 #define CAN_FS1R_FSC15_Msk (0x1U << CAN_FS1R_FSC15_Pos) /*!< 0x00008000 */
2710 #define CAN_FS1R_FSC15 CAN_FS1R_FSC15_Msk /*!<Filter Scale Configuration bit 15 */
2711 #define CAN_FS1R_FSC16_Pos (16U)
2712 #define CAN_FS1R_FSC16_Msk (0x1U << CAN_FS1R_FSC16_Pos) /*!< 0x00010000 */
2713 #define CAN_FS1R_FSC16 CAN_FS1R_FSC16_Msk /*!<Filter Scale Configuration bit 16 */
2714 #define CAN_FS1R_FSC17_Pos (17U)
2715 #define CAN_FS1R_FSC17_Msk (0x1U << CAN_FS1R_FSC17_Pos) /*!< 0x00020000 */
2716 #define CAN_FS1R_FSC17 CAN_FS1R_FSC17_Msk /*!<Filter Scale Configuration bit 17 */
2717 #define CAN_FS1R_FSC18_Pos (18U)
2718 #define CAN_FS1R_FSC18_Msk (0x1U << CAN_FS1R_FSC18_Pos) /*!< 0x00040000 */
2719 #define CAN_FS1R_FSC18 CAN_FS1R_FSC18_Msk /*!<Filter Scale Configuration bit 18 */
2720 #define CAN_FS1R_FSC19_Pos (19U)
2721 #define CAN_FS1R_FSC19_Msk (0x1U << CAN_FS1R_FSC19_Pos) /*!< 0x00080000 */
2722 #define CAN_FS1R_FSC19 CAN_FS1R_FSC19_Msk /*!<Filter Scale Configuration bit 19 */
2723 #define CAN_FS1R_FSC20_Pos (20U)
2724 #define CAN_FS1R_FSC20_Msk (0x1U << CAN_FS1R_FSC20_Pos) /*!< 0x00100000 */
2725 #define CAN_FS1R_FSC20 CAN_FS1R_FSC20_Msk /*!<Filter Scale Configuration bit 20 */
2726 #define CAN_FS1R_FSC21_Pos (21U)
2727 #define CAN_FS1R_FSC21_Msk (0x1U << CAN_FS1R_FSC21_Pos) /*!< 0x00200000 */
2728 #define CAN_FS1R_FSC21 CAN_FS1R_FSC21_Msk /*!<Filter Scale Configuration bit 21 */
2729 #define CAN_FS1R_FSC22_Pos (22U)
2730 #define CAN_FS1R_FSC22_Msk (0x1U << CAN_FS1R_FSC22_Pos) /*!< 0x00400000 */
2731 #define CAN_FS1R_FSC22 CAN_FS1R_FSC22_Msk /*!<Filter Scale Configuration bit 22 */
2732 #define CAN_FS1R_FSC23_Pos (23U)
2733 #define CAN_FS1R_FSC23_Msk (0x1U << CAN_FS1R_FSC23_Pos) /*!< 0x00800000 */
2734 #define CAN_FS1R_FSC23 CAN_FS1R_FSC23_Msk /*!<Filter Scale Configuration bit 23 */
2735 #define CAN_FS1R_FSC24_Pos (24U)
2736 #define CAN_FS1R_FSC24_Msk (0x1U << CAN_FS1R_FSC24_Pos) /*!< 0x01000000 */
2737 #define CAN_FS1R_FSC24 CAN_FS1R_FSC24_Msk /*!<Filter Scale Configuration bit 24 */
2738 #define CAN_FS1R_FSC25_Pos (25U)
2739 #define CAN_FS1R_FSC25_Msk (0x1U << CAN_FS1R_FSC25_Pos) /*!< 0x02000000 */
2740 #define CAN_FS1R_FSC25 CAN_FS1R_FSC25_Msk /*!<Filter Scale Configuration bit 25 */
2741 #define CAN_FS1R_FSC26_Pos (26U)
2742 #define CAN_FS1R_FSC26_Msk (0x1U << CAN_FS1R_FSC26_Pos) /*!< 0x04000000 */
2743 #define CAN_FS1R_FSC26 CAN_FS1R_FSC26_Msk /*!<Filter Scale Configuration bit 26 */
2744 #define CAN_FS1R_FSC27_Pos (27U)
2745 #define CAN_FS1R_FSC27_Msk (0x1U << CAN_FS1R_FSC27_Pos) /*!< 0x08000000 */
2746 #define CAN_FS1R_FSC27 CAN_FS1R_FSC27_Msk /*!<Filter Scale Configuration bit 27 */
2747
2748 /****************** Bit definition for CAN_FFA1R register *******************/
2749 #define CAN_FFA1R_FFA_Pos (0U)
2750 #define CAN_FFA1R_FFA_Msk (0xFFFFFFFU << CAN_FFA1R_FFA_Pos) /*!< 0x0FFFFFFF */
2751 #define CAN_FFA1R_FFA CAN_FFA1R_FFA_Msk /*!<Filter FIFO Assignment */
2752 #define CAN_FFA1R_FFA0_Pos (0U)
2753 #define CAN_FFA1R_FFA0_Msk (0x1U << CAN_FFA1R_FFA0_Pos) /*!< 0x00000001 */
2754 #define CAN_FFA1R_FFA0 CAN_FFA1R_FFA0_Msk /*!<Filter FIFO Assignment bit 0 */
2755 #define CAN_FFA1R_FFA1_Pos (1U)
2756 #define CAN_FFA1R_FFA1_Msk (0x1U << CAN_FFA1R_FFA1_Pos) /*!< 0x00000002 */
2757 #define CAN_FFA1R_FFA1 CAN_FFA1R_FFA1_Msk /*!<Filter FIFO Assignment bit 1 */
2758 #define CAN_FFA1R_FFA2_Pos (2U)
2759 #define CAN_FFA1R_FFA2_Msk (0x1U << CAN_FFA1R_FFA2_Pos) /*!< 0x00000004 */
2760 #define CAN_FFA1R_FFA2 CAN_FFA1R_FFA2_Msk /*!<Filter FIFO Assignment bit 2 */
2761 #define CAN_FFA1R_FFA3_Pos (3U)
2762 #define CAN_FFA1R_FFA3_Msk (0x1U << CAN_FFA1R_FFA3_Pos) /*!< 0x00000008 */
2763 #define CAN_FFA1R_FFA3 CAN_FFA1R_FFA3_Msk /*!<Filter FIFO Assignment bit 3 */
2764 #define CAN_FFA1R_FFA4_Pos (4U)
2765 #define CAN_FFA1R_FFA4_Msk (0x1U << CAN_FFA1R_FFA4_Pos) /*!< 0x00000010 */
2766 #define CAN_FFA1R_FFA4 CAN_FFA1R_FFA4_Msk /*!<Filter FIFO Assignment bit 4 */
2767 #define CAN_FFA1R_FFA5_Pos (5U)
2768 #define CAN_FFA1R_FFA5_Msk (0x1U << CAN_FFA1R_FFA5_Pos) /*!< 0x00000020 */
2769 #define CAN_FFA1R_FFA5 CAN_FFA1R_FFA5_Msk /*!<Filter FIFO Assignment bit 5 */
2770 #define CAN_FFA1R_FFA6_Pos (6U)
2771 #define CAN_FFA1R_FFA6_Msk (0x1U << CAN_FFA1R_FFA6_Pos) /*!< 0x00000040 */
2772 #define CAN_FFA1R_FFA6 CAN_FFA1R_FFA6_Msk /*!<Filter FIFO Assignment bit 6 */
2773 #define CAN_FFA1R_FFA7_Pos (7U)
2774 #define CAN_FFA1R_FFA7_Msk (0x1U << CAN_FFA1R_FFA7_Pos) /*!< 0x00000080 */
2775 #define CAN_FFA1R_FFA7 CAN_FFA1R_FFA7_Msk /*!<Filter FIFO Assignment bit 7 */
2776 #define CAN_FFA1R_FFA8_Pos (8U)
2777 #define CAN_FFA1R_FFA8_Msk (0x1U << CAN_FFA1R_FFA8_Pos) /*!< 0x00000100 */
2778 #define CAN_FFA1R_FFA8 CAN_FFA1R_FFA8_Msk /*!<Filter FIFO Assignment bit 8 */
2779 #define CAN_FFA1R_FFA9_Pos (9U)
2780 #define CAN_FFA1R_FFA9_Msk (0x1U << CAN_FFA1R_FFA9_Pos) /*!< 0x00000200 */
2781 #define CAN_FFA1R_FFA9 CAN_FFA1R_FFA9_Msk /*!<Filter FIFO Assignment bit 9 */
2782 #define CAN_FFA1R_FFA10_Pos (10U)
2783 #define CAN_FFA1R_FFA10_Msk (0x1U << CAN_FFA1R_FFA10_Pos) /*!< 0x00000400 */
2784 #define CAN_FFA1R_FFA10 CAN_FFA1R_FFA10_Msk /*!<Filter FIFO Assignment bit 10 */
2785 #define CAN_FFA1R_FFA11_Pos (11U)
2786 #define CAN_FFA1R_FFA11_Msk (0x1U << CAN_FFA1R_FFA11_Pos) /*!< 0x00000800 */
2787 #define CAN_FFA1R_FFA11 CAN_FFA1R_FFA11_Msk /*!<Filter FIFO Assignment bit 11 */
2788 #define CAN_FFA1R_FFA12_Pos (12U)
2789 #define CAN_FFA1R_FFA12_Msk (0x1U << CAN_FFA1R_FFA12_Pos) /*!< 0x00001000 */
2790 #define CAN_FFA1R_FFA12 CAN_FFA1R_FFA12_Msk /*!<Filter FIFO Assignment bit 12 */
2791 #define CAN_FFA1R_FFA13_Pos (13U)
2792 #define CAN_FFA1R_FFA13_Msk (0x1U << CAN_FFA1R_FFA13_Pos) /*!< 0x00002000 */
2793 #define CAN_FFA1R_FFA13 CAN_FFA1R_FFA13_Msk /*!<Filter FIFO Assignment bit 13 */
2794 #define CAN_FFA1R_FFA14_Pos (14U)
2795 #define CAN_FFA1R_FFA14_Msk (0x1U << CAN_FFA1R_FFA14_Pos) /*!< 0x00004000 */
2796 #define CAN_FFA1R_FFA14 CAN_FFA1R_FFA14_Msk /*!<Filter FIFO Assignment bit 14 */
2797 #define CAN_FFA1R_FFA15_Pos (15U)
2798 #define CAN_FFA1R_FFA15_Msk (0x1U << CAN_FFA1R_FFA15_Pos) /*!< 0x00008000 */
2799 #define CAN_FFA1R_FFA15 CAN_FFA1R_FFA15_Msk /*!<Filter FIFO Assignment bit 15 */
2800 #define CAN_FFA1R_FFA16_Pos (16U)
2801 #define CAN_FFA1R_FFA16_Msk (0x1U << CAN_FFA1R_FFA16_Pos) /*!< 0x00010000 */
2802 #define CAN_FFA1R_FFA16 CAN_FFA1R_FFA16_Msk /*!<Filter FIFO Assignment bit 16 */
2803 #define CAN_FFA1R_FFA17_Pos (17U)
2804 #define CAN_FFA1R_FFA17_Msk (0x1U << CAN_FFA1R_FFA17_Pos) /*!< 0x00020000 */
2805 #define CAN_FFA1R_FFA17 CAN_FFA1R_FFA17_Msk /*!<Filter FIFO Assignment bit 17 */
2806 #define CAN_FFA1R_FFA18_Pos (18U)
2807 #define CAN_FFA1R_FFA18_Msk (0x1U << CAN_FFA1R_FFA18_Pos) /*!< 0x00040000 */
2808 #define CAN_FFA1R_FFA18 CAN_FFA1R_FFA18_Msk /*!<Filter FIFO Assignment bit 18 */
2809 #define CAN_FFA1R_FFA19_Pos (19U)
2810 #define CAN_FFA1R_FFA19_Msk (0x1U << CAN_FFA1R_FFA19_Pos) /*!< 0x00080000 */
2811 #define CAN_FFA1R_FFA19 CAN_FFA1R_FFA19_Msk /*!<Filter FIFO Assignment bit 19 */
2812 #define CAN_FFA1R_FFA20_Pos (20U)
2813 #define CAN_FFA1R_FFA20_Msk (0x1U << CAN_FFA1R_FFA20_Pos) /*!< 0x00100000 */
2814 #define CAN_FFA1R_FFA20 CAN_FFA1R_FFA20_Msk /*!<Filter FIFO Assignment bit 20 */
2815 #define CAN_FFA1R_FFA21_Pos (21U)
2816 #define CAN_FFA1R_FFA21_Msk (0x1U << CAN_FFA1R_FFA21_Pos) /*!< 0x00200000 */
2817 #define CAN_FFA1R_FFA21 CAN_FFA1R_FFA21_Msk /*!<Filter FIFO Assignment bit 21 */
2818 #define CAN_FFA1R_FFA22_Pos (22U)
2819 #define CAN_FFA1R_FFA22_Msk (0x1U << CAN_FFA1R_FFA22_Pos) /*!< 0x00400000 */
2820 #define CAN_FFA1R_FFA22 CAN_FFA1R_FFA22_Msk /*!<Filter FIFO Assignment bit 22 */
2821 #define CAN_FFA1R_FFA23_Pos (23U)
2822 #define CAN_FFA1R_FFA23_Msk (0x1U << CAN_FFA1R_FFA23_Pos) /*!< 0x00800000 */
2823 #define CAN_FFA1R_FFA23 CAN_FFA1R_FFA23_Msk /*!<Filter FIFO Assignment bit 23 */
2824 #define CAN_FFA1R_FFA24_Pos (24U)
2825 #define CAN_FFA1R_FFA24_Msk (0x1U << CAN_FFA1R_FFA24_Pos) /*!< 0x01000000 */
2826 #define CAN_FFA1R_FFA24 CAN_FFA1R_FFA24_Msk /*!<Filter FIFO Assignment bit 24 */
2827 #define CAN_FFA1R_FFA25_Pos (25U)
2828 #define CAN_FFA1R_FFA25_Msk (0x1U << CAN_FFA1R_FFA25_Pos) /*!< 0x02000000 */
2829 #define CAN_FFA1R_FFA25 CAN_FFA1R_FFA25_Msk /*!<Filter FIFO Assignment bit 25 */
2830 #define CAN_FFA1R_FFA26_Pos (26U)
2831 #define CAN_FFA1R_FFA26_Msk (0x1U << CAN_FFA1R_FFA26_Pos) /*!< 0x04000000 */
2832 #define CAN_FFA1R_FFA26 CAN_FFA1R_FFA26_Msk /*!<Filter FIFO Assignment bit 26 */
2833 #define CAN_FFA1R_FFA27_Pos (27U)
2834 #define CAN_FFA1R_FFA27_Msk (0x1U << CAN_FFA1R_FFA27_Pos) /*!< 0x08000000 */
2835 #define CAN_FFA1R_FFA27 CAN_FFA1R_FFA27_Msk /*!<Filter FIFO Assignment bit 27 */
2836
2837 /******************* Bit definition for CAN_FA1R register *******************/
2838 #define CAN_FA1R_FACT_Pos (0U)
2839 #define CAN_FA1R_FACT_Msk (0xFFFFFFFU << CAN_FA1R_FACT_Pos) /*!< 0x0FFFFFFF */
2840 #define CAN_FA1R_FACT CAN_FA1R_FACT_Msk /*!<Filter Active */
2841 #define CAN_FA1R_FACT0_Pos (0U)
2842 #define CAN_FA1R_FACT0_Msk (0x1U << CAN_FA1R_FACT0_Pos) /*!< 0x00000001 */
2843 #define CAN_FA1R_FACT0 CAN_FA1R_FACT0_Msk /*!<Filter Active bit 0 */
2844 #define CAN_FA1R_FACT1_Pos (1U)
2845 #define CAN_FA1R_FACT1_Msk (0x1U << CAN_FA1R_FACT1_Pos) /*!< 0x00000002 */
2846 #define CAN_FA1R_FACT1 CAN_FA1R_FACT1_Msk /*!<Filter Active bit 1 */
2847 #define CAN_FA1R_FACT2_Pos (2U)
2848 #define CAN_FA1R_FACT2_Msk (0x1U << CAN_FA1R_FACT2_Pos) /*!< 0x00000004 */
2849 #define CAN_FA1R_FACT2 CAN_FA1R_FACT2_Msk /*!<Filter Active bit 2 */
2850 #define CAN_FA1R_FACT3_Pos (3U)
2851 #define CAN_FA1R_FACT3_Msk (0x1U << CAN_FA1R_FACT3_Pos) /*!< 0x00000008 */
2852 #define CAN_FA1R_FACT3 CAN_FA1R_FACT3_Msk /*!<Filter Active bit 3 */
2853 #define CAN_FA1R_FACT4_Pos (4U)
2854 #define CAN_FA1R_FACT4_Msk (0x1U << CAN_FA1R_FACT4_Pos) /*!< 0x00000010 */
2855 #define CAN_FA1R_FACT4 CAN_FA1R_FACT4_Msk /*!<Filter Active bit 4 */
2856 #define CAN_FA1R_FACT5_Pos (5U)
2857 #define CAN_FA1R_FACT5_Msk (0x1U << CAN_FA1R_FACT5_Pos) /*!< 0x00000020 */
2858 #define CAN_FA1R_FACT5 CAN_FA1R_FACT5_Msk /*!<Filter Active bit 5 */
2859 #define CAN_FA1R_FACT6_Pos (6U)
2860 #define CAN_FA1R_FACT6_Msk (0x1U << CAN_FA1R_FACT6_Pos) /*!< 0x00000040 */
2861 #define CAN_FA1R_FACT6 CAN_FA1R_FACT6_Msk /*!<Filter Active bit 6 */
2862 #define CAN_FA1R_FACT7_Pos (7U)
2863 #define CAN_FA1R_FACT7_Msk (0x1U << CAN_FA1R_FACT7_Pos) /*!< 0x00000080 */
2864 #define CAN_FA1R_FACT7 CAN_FA1R_FACT7_Msk /*!<Filter Active bit 7 */
2865 #define CAN_FA1R_FACT8_Pos (8U)
2866 #define CAN_FA1R_FACT8_Msk (0x1U << CAN_FA1R_FACT8_Pos) /*!< 0x00000100 */
2867 #define CAN_FA1R_FACT8 CAN_FA1R_FACT8_Msk /*!<Filter Active bit 8 */
2868 #define CAN_FA1R_FACT9_Pos (9U)
2869 #define CAN_FA1R_FACT9_Msk (0x1U << CAN_FA1R_FACT9_Pos) /*!< 0x00000200 */
2870 #define CAN_FA1R_FACT9 CAN_FA1R_FACT9_Msk /*!<Filter Active bit 9 */
2871 #define CAN_FA1R_FACT10_Pos (10U)
2872 #define CAN_FA1R_FACT10_Msk (0x1U << CAN_FA1R_FACT10_Pos) /*!< 0x00000400 */
2873 #define CAN_FA1R_FACT10 CAN_FA1R_FACT10_Msk /*!<Filter Active bit 10 */
2874 #define CAN_FA1R_FACT11_Pos (11U)
2875 #define CAN_FA1R_FACT11_Msk (0x1U << CAN_FA1R_FACT11_Pos) /*!< 0x00000800 */
2876 #define CAN_FA1R_FACT11 CAN_FA1R_FACT11_Msk /*!<Filter Active bit 11 */
2877 #define CAN_FA1R_FACT12_Pos (12U)
2878 #define CAN_FA1R_FACT12_Msk (0x1U << CAN_FA1R_FACT12_Pos) /*!< 0x00001000 */
2879 #define CAN_FA1R_FACT12 CAN_FA1R_FACT12_Msk /*!<Filter Active bit 12 */
2880 #define CAN_FA1R_FACT13_Pos (13U)
2881 #define CAN_FA1R_FACT13_Msk (0x1U << CAN_FA1R_FACT13_Pos) /*!< 0x00002000 */
2882 #define CAN_FA1R_FACT13 CAN_FA1R_FACT13_Msk /*!<Filter Active bit 13 */
2883 #define CAN_FA1R_FACT14_Pos (14U)
2884 #define CAN_FA1R_FACT14_Msk (0x1U << CAN_FA1R_FACT14_Pos) /*!< 0x00004000 */
2885 #define CAN_FA1R_FACT14 CAN_FA1R_FACT14_Msk /*!<Filter Active bit 14 */
2886 #define CAN_FA1R_FACT15_Pos (15U)
2887 #define CAN_FA1R_FACT15_Msk (0x1U << CAN_FA1R_FACT15_Pos) /*!< 0x00008000 */
2888 #define CAN_FA1R_FACT15 CAN_FA1R_FACT15_Msk /*!<Filter Active bit 15 */
2889 #define CAN_FA1R_FACT16_Pos (16U)
2890 #define CAN_FA1R_FACT16_Msk (0x1U << CAN_FA1R_FACT16_Pos) /*!< 0x00010000 */
2891 #define CAN_FA1R_FACT16 CAN_FA1R_FACT16_Msk /*!<Filter Active bit 16 */
2892 #define CAN_FA1R_FACT17_Pos (17U)
2893 #define CAN_FA1R_FACT17_Msk (0x1U << CAN_FA1R_FACT17_Pos) /*!< 0x00020000 */
2894 #define CAN_FA1R_FACT17 CAN_FA1R_FACT17_Msk /*!<Filter Active bit 17 */
2895 #define CAN_FA1R_FACT18_Pos (18U)
2896 #define CAN_FA1R_FACT18_Msk (0x1U << CAN_FA1R_FACT18_Pos) /*!< 0x00040000 */
2897 #define CAN_FA1R_FACT18 CAN_FA1R_FACT18_Msk /*!<Filter Active bit 18 */
2898 #define CAN_FA1R_FACT19_Pos (19U)
2899 #define CAN_FA1R_FACT19_Msk (0x1U << CAN_FA1R_FACT19_Pos) /*!< 0x00080000 */
2900 #define CAN_FA1R_FACT19 CAN_FA1R_FACT19_Msk /*!<Filter Active bit 19 */
2901 #define CAN_FA1R_FACT20_Pos (20U)
2902 #define CAN_FA1R_FACT20_Msk (0x1U << CAN_FA1R_FACT20_Pos) /*!< 0x00100000 */
2903 #define CAN_FA1R_FACT20 CAN_FA1R_FACT20_Msk /*!<Filter Active bit 20 */
2904 #define CAN_FA1R_FACT21_Pos (21U)
2905 #define CAN_FA1R_FACT21_Msk (0x1U << CAN_FA1R_FACT21_Pos) /*!< 0x00200000 */
2906 #define CAN_FA1R_FACT21 CAN_FA1R_FACT21_Msk /*!<Filter Active bit 21 */
2907 #define CAN_FA1R_FACT22_Pos (22U)
2908 #define CAN_FA1R_FACT22_Msk (0x1U << CAN_FA1R_FACT22_Pos) /*!< 0x00400000 */
2909 #define CAN_FA1R_FACT22 CAN_FA1R_FACT22_Msk /*!<Filter Active bit 22 */
2910 #define CAN_FA1R_FACT23_Pos (23U)
2911 #define CAN_FA1R_FACT23_Msk (0x1U << CAN_FA1R_FACT23_Pos) /*!< 0x00800000 */
2912 #define CAN_FA1R_FACT23 CAN_FA1R_FACT23_Msk /*!<Filter Active bit 23 */
2913 #define CAN_FA1R_FACT24_Pos (24U)
2914 #define CAN_FA1R_FACT24_Msk (0x1U << CAN_FA1R_FACT24_Pos) /*!< 0x01000000 */
2915 #define CAN_FA1R_FACT24 CAN_FA1R_FACT24_Msk /*!<Filter Active bit 24 */
2916 #define CAN_FA1R_FACT25_Pos (25U)
2917 #define CAN_FA1R_FACT25_Msk (0x1U << CAN_FA1R_FACT25_Pos) /*!< 0x02000000 */
2918 #define CAN_FA1R_FACT25 CAN_FA1R_FACT25_Msk /*!<Filter Active bit 25 */
2919 #define CAN_FA1R_FACT26_Pos (26U)
2920 #define CAN_FA1R_FACT26_Msk (0x1U << CAN_FA1R_FACT26_Pos) /*!< 0x04000000 */
2921 #define CAN_FA1R_FACT26 CAN_FA1R_FACT26_Msk /*!<Filter Active bit 26 */
2922 #define CAN_FA1R_FACT27_Pos (27U)
2923 #define CAN_FA1R_FACT27_Msk (0x1U << CAN_FA1R_FACT27_Pos) /*!< 0x08000000 */
2924 #define CAN_FA1R_FACT27 CAN_FA1R_FACT27_Msk /*!<Filter Active bit 27 */
2925
2926
2927 /******************* Bit definition for CAN_F0R1 register *******************/
2928 #define CAN_F0R1_FB0_Pos (0U)
2929 #define CAN_F0R1_FB0_Msk (0x1U << CAN_F0R1_FB0_Pos) /*!< 0x00000001 */
2930 #define CAN_F0R1_FB0 CAN_F0R1_FB0_Msk /*!<Filter bit 0 */
2931 #define CAN_F0R1_FB1_Pos (1U)
2932 #define CAN_F0R1_FB1_Msk (0x1U << CAN_F0R1_FB1_Pos) /*!< 0x00000002 */
2933 #define CAN_F0R1_FB1 CAN_F0R1_FB1_Msk /*!<Filter bit 1 */
2934 #define CAN_F0R1_FB2_Pos (2U)
2935 #define CAN_F0R1_FB2_Msk (0x1U << CAN_F0R1_FB2_Pos) /*!< 0x00000004 */
2936 #define CAN_F0R1_FB2 CAN_F0R1_FB2_Msk /*!<Filter bit 2 */
2937 #define CAN_F0R1_FB3_Pos (3U)
2938 #define CAN_F0R1_FB3_Msk (0x1U << CAN_F0R1_FB3_Pos) /*!< 0x00000008 */
2939 #define CAN_F0R1_FB3 CAN_F0R1_FB3_Msk /*!<Filter bit 3 */
2940 #define CAN_F0R1_FB4_Pos (4U)
2941 #define CAN_F0R1_FB4_Msk (0x1U << CAN_F0R1_FB4_Pos) /*!< 0x00000010 */
2942 #define CAN_F0R1_FB4 CAN_F0R1_FB4_Msk /*!<Filter bit 4 */
2943 #define CAN_F0R1_FB5_Pos (5U)
2944 #define CAN_F0R1_FB5_Msk (0x1U << CAN_F0R1_FB5_Pos) /*!< 0x00000020 */
2945 #define CAN_F0R1_FB5 CAN_F0R1_FB5_Msk /*!<Filter bit 5 */
2946 #define CAN_F0R1_FB6_Pos (6U)
2947 #define CAN_F0R1_FB6_Msk (0x1U << CAN_F0R1_FB6_Pos) /*!< 0x00000040 */
2948 #define CAN_F0R1_FB6 CAN_F0R1_FB6_Msk /*!<Filter bit 6 */
2949 #define CAN_F0R1_FB7_Pos (7U)
2950 #define CAN_F0R1_FB7_Msk (0x1U << CAN_F0R1_FB7_Pos) /*!< 0x00000080 */
2951 #define CAN_F0R1_FB7 CAN_F0R1_FB7_Msk /*!<Filter bit 7 */
2952 #define CAN_F0R1_FB8_Pos (8U)
2953 #define CAN_F0R1_FB8_Msk (0x1U << CAN_F0R1_FB8_Pos) /*!< 0x00000100 */
2954 #define CAN_F0R1_FB8 CAN_F0R1_FB8_Msk /*!<Filter bit 8 */
2955 #define CAN_F0R1_FB9_Pos (9U)
2956 #define CAN_F0R1_FB9_Msk (0x1U << CAN_F0R1_FB9_Pos) /*!< 0x00000200 */
2957 #define CAN_F0R1_FB9 CAN_F0R1_FB9_Msk /*!<Filter bit 9 */
2958 #define CAN_F0R1_FB10_Pos (10U)
2959 #define CAN_F0R1_FB10_Msk (0x1U << CAN_F0R1_FB10_Pos) /*!< 0x00000400 */
2960 #define CAN_F0R1_FB10 CAN_F0R1_FB10_Msk /*!<Filter bit 10 */
2961 #define CAN_F0R1_FB11_Pos (11U)
2962 #define CAN_F0R1_FB11_Msk (0x1U << CAN_F0R1_FB11_Pos) /*!< 0x00000800 */
2963 #define CAN_F0R1_FB11 CAN_F0R1_FB11_Msk /*!<Filter bit 11 */
2964 #define CAN_F0R1_FB12_Pos (12U)
2965 #define CAN_F0R1_FB12_Msk (0x1U << CAN_F0R1_FB12_Pos) /*!< 0x00001000 */
2966 #define CAN_F0R1_FB12 CAN_F0R1_FB12_Msk /*!<Filter bit 12 */
2967 #define CAN_F0R1_FB13_Pos (13U)
2968 #define CAN_F0R1_FB13_Msk (0x1U << CAN_F0R1_FB13_Pos) /*!< 0x00002000 */
2969 #define CAN_F0R1_FB13 CAN_F0R1_FB13_Msk /*!<Filter bit 13 */
2970 #define CAN_F0R1_FB14_Pos (14U)
2971 #define CAN_F0R1_FB14_Msk (0x1U << CAN_F0R1_FB14_Pos) /*!< 0x00004000 */
2972 #define CAN_F0R1_FB14 CAN_F0R1_FB14_Msk /*!<Filter bit 14 */
2973 #define CAN_F0R1_FB15_Pos (15U)
2974 #define CAN_F0R1_FB15_Msk (0x1U << CAN_F0R1_FB15_Pos) /*!< 0x00008000 */
2975 #define CAN_F0R1_FB15 CAN_F0R1_FB15_Msk /*!<Filter bit 15 */
2976 #define CAN_F0R1_FB16_Pos (16U)
2977 #define CAN_F0R1_FB16_Msk (0x1U << CAN_F0R1_FB16_Pos) /*!< 0x00010000 */
2978 #define CAN_F0R1_FB16 CAN_F0R1_FB16_Msk /*!<Filter bit 16 */
2979 #define CAN_F0R1_FB17_Pos (17U)
2980 #define CAN_F0R1_FB17_Msk (0x1U << CAN_F0R1_FB17_Pos) /*!< 0x00020000 */
2981 #define CAN_F0R1_FB17 CAN_F0R1_FB17_Msk /*!<Filter bit 17 */
2982 #define CAN_F0R1_FB18_Pos (18U)
2983 #define CAN_F0R1_FB18_Msk (0x1U << CAN_F0R1_FB18_Pos) /*!< 0x00040000 */
2984 #define CAN_F0R1_FB18 CAN_F0R1_FB18_Msk /*!<Filter bit 18 */
2985 #define CAN_F0R1_FB19_Pos (19U)
2986 #define CAN_F0R1_FB19_Msk (0x1U << CAN_F0R1_FB19_Pos) /*!< 0x00080000 */
2987 #define CAN_F0R1_FB19 CAN_F0R1_FB19_Msk /*!<Filter bit 19 */
2988 #define CAN_F0R1_FB20_Pos (20U)
2989 #define CAN_F0R1_FB20_Msk (0x1U << CAN_F0R1_FB20_Pos) /*!< 0x00100000 */
2990 #define CAN_F0R1_FB20 CAN_F0R1_FB20_Msk /*!<Filter bit 20 */
2991 #define CAN_F0R1_FB21_Pos (21U)
2992 #define CAN_F0R1_FB21_Msk (0x1U << CAN_F0R1_FB21_Pos) /*!< 0x00200000 */
2993 #define CAN_F0R1_FB21 CAN_F0R1_FB21_Msk /*!<Filter bit 21 */
2994 #define CAN_F0R1_FB22_Pos (22U)
2995 #define CAN_F0R1_FB22_Msk (0x1U << CAN_F0R1_FB22_Pos) /*!< 0x00400000 */
2996 #define CAN_F0R1_FB22 CAN_F0R1_FB22_Msk /*!<Filter bit 22 */
2997 #define CAN_F0R1_FB23_Pos (23U)
2998 #define CAN_F0R1_FB23_Msk (0x1U << CAN_F0R1_FB23_Pos) /*!< 0x00800000 */
2999 #define CAN_F0R1_FB23 CAN_F0R1_FB23_Msk /*!<Filter bit 23 */
3000 #define CAN_F0R1_FB24_Pos (24U)
3001 #define CAN_F0R1_FB24_Msk (0x1U << CAN_F0R1_FB24_Pos) /*!< 0x01000000 */
3002 #define CAN_F0R1_FB24 CAN_F0R1_FB24_Msk /*!<Filter bit 24 */
3003 #define CAN_F0R1_FB25_Pos (25U)
3004 #define CAN_F0R1_FB25_Msk (0x1U << CAN_F0R1_FB25_Pos) /*!< 0x02000000 */
3005 #define CAN_F0R1_FB25 CAN_F0R1_FB25_Msk /*!<Filter bit 25 */
3006 #define CAN_F0R1_FB26_Pos (26U)
3007 #define CAN_F0R1_FB26_Msk (0x1U << CAN_F0R1_FB26_Pos) /*!< 0x04000000 */
3008 #define CAN_F0R1_FB26 CAN_F0R1_FB26_Msk /*!<Filter bit 26 */
3009 #define CAN_F0R1_FB27_Pos (27U)
3010 #define CAN_F0R1_FB27_Msk (0x1U << CAN_F0R1_FB27_Pos) /*!< 0x08000000 */
3011 #define CAN_F0R1_FB27 CAN_F0R1_FB27_Msk /*!<Filter bit 27 */
3012 #define CAN_F0R1_FB28_Pos (28U)
3013 #define CAN_F0R1_FB28_Msk (0x1U << CAN_F0R1_FB28_Pos) /*!< 0x10000000 */
3014 #define CAN_F0R1_FB28 CAN_F0R1_FB28_Msk /*!<Filter bit 28 */
3015 #define CAN_F0R1_FB29_Pos (29U)
3016 #define CAN_F0R1_FB29_Msk (0x1U << CAN_F0R1_FB29_Pos) /*!< 0x20000000 */
3017 #define CAN_F0R1_FB29 CAN_F0R1_FB29_Msk /*!<Filter bit 29 */
3018 #define CAN_F0R1_FB30_Pos (30U)
3019 #define CAN_F0R1_FB30_Msk (0x1U << CAN_F0R1_FB30_Pos) /*!< 0x40000000 */
3020 #define CAN_F0R1_FB30 CAN_F0R1_FB30_Msk /*!<Filter bit 30 */
3021 #define CAN_F0R1_FB31_Pos (31U)
3022 #define CAN_F0R1_FB31_Msk (0x1U << CAN_F0R1_FB31_Pos) /*!< 0x80000000 */
3023 #define CAN_F0R1_FB31 CAN_F0R1_FB31_Msk /*!<Filter bit 31 */
3024
3025 /******************* Bit definition for CAN_F1R1 register *******************/
3026 #define CAN_F1R1_FB0_Pos (0U)
3027 #define CAN_F1R1_FB0_Msk (0x1U << CAN_F1R1_FB0_Pos) /*!< 0x00000001 */
3028 #define CAN_F1R1_FB0 CAN_F1R1_FB0_Msk /*!<Filter bit 0 */
3029 #define CAN_F1R1_FB1_Pos (1U)
3030 #define CAN_F1R1_FB1_Msk (0x1U << CAN_F1R1_FB1_Pos) /*!< 0x00000002 */
3031 #define CAN_F1R1_FB1 CAN_F1R1_FB1_Msk /*!<Filter bit 1 */
3032 #define CAN_F1R1_FB2_Pos (2U)
3033 #define CAN_F1R1_FB2_Msk (0x1U << CAN_F1R1_FB2_Pos) /*!< 0x00000004 */
3034 #define CAN_F1R1_FB2 CAN_F1R1_FB2_Msk /*!<Filter bit 2 */
3035 #define CAN_F1R1_FB3_Pos (3U)
3036 #define CAN_F1R1_FB3_Msk (0x1U << CAN_F1R1_FB3_Pos) /*!< 0x00000008 */
3037 #define CAN_F1R1_FB3 CAN_F1R1_FB3_Msk /*!<Filter bit 3 */
3038 #define CAN_F1R1_FB4_Pos (4U)
3039 #define CAN_F1R1_FB4_Msk (0x1U << CAN_F1R1_FB4_Pos) /*!< 0x00000010 */
3040 #define CAN_F1R1_FB4 CAN_F1R1_FB4_Msk /*!<Filter bit 4 */
3041 #define CAN_F1R1_FB5_Pos (5U)
3042 #define CAN_F1R1_FB5_Msk (0x1U << CAN_F1R1_FB5_Pos) /*!< 0x00000020 */
3043 #define CAN_F1R1_FB5 CAN_F1R1_FB5_Msk /*!<Filter bit 5 */
3044 #define CAN_F1R1_FB6_Pos (6U)
3045 #define CAN_F1R1_FB6_Msk (0x1U << CAN_F1R1_FB6_Pos) /*!< 0x00000040 */
3046 #define CAN_F1R1_FB6 CAN_F1R1_FB6_Msk /*!<Filter bit 6 */
3047 #define CAN_F1R1_FB7_Pos (7U)
3048 #define CAN_F1R1_FB7_Msk (0x1U << CAN_F1R1_FB7_Pos) /*!< 0x00000080 */
3049 #define CAN_F1R1_FB7 CAN_F1R1_FB7_Msk /*!<Filter bit 7 */
3050 #define CAN_F1R1_FB8_Pos (8U)
3051 #define CAN_F1R1_FB8_Msk (0x1U << CAN_F1R1_FB8_Pos) /*!< 0x00000100 */
3052 #define CAN_F1R1_FB8 CAN_F1R1_FB8_Msk /*!<Filter bit 8 */
3053 #define CAN_F1R1_FB9_Pos (9U)
3054 #define CAN_F1R1_FB9_Msk (0x1U << CAN_F1R1_FB9_Pos) /*!< 0x00000200 */
3055 #define CAN_F1R1_FB9 CAN_F1R1_FB9_Msk /*!<Filter bit 9 */
3056 #define CAN_F1R1_FB10_Pos (10U)
3057 #define CAN_F1R1_FB10_Msk (0x1U << CAN_F1R1_FB10_Pos) /*!< 0x00000400 */
3058 #define CAN_F1R1_FB10 CAN_F1R1_FB10_Msk /*!<Filter bit 10 */
3059 #define CAN_F1R1_FB11_Pos (11U)
3060 #define CAN_F1R1_FB11_Msk (0x1U << CAN_F1R1_FB11_Pos) /*!< 0x00000800 */
3061 #define CAN_F1R1_FB11 CAN_F1R1_FB11_Msk /*!<Filter bit 11 */
3062 #define CAN_F1R1_FB12_Pos (12U)
3063 #define CAN_F1R1_FB12_Msk (0x1U << CAN_F1R1_FB12_Pos) /*!< 0x00001000 */
3064 #define CAN_F1R1_FB12 CAN_F1R1_FB12_Msk /*!<Filter bit 12 */
3065 #define CAN_F1R1_FB13_Pos (13U)
3066 #define CAN_F1R1_FB13_Msk (0x1U << CAN_F1R1_FB13_Pos) /*!< 0x00002000 */
3067 #define CAN_F1R1_FB13 CAN_F1R1_FB13_Msk /*!<Filter bit 13 */
3068 #define CAN_F1R1_FB14_Pos (14U)
3069 #define CAN_F1R1_FB14_Msk (0x1U << CAN_F1R1_FB14_Pos) /*!< 0x00004000 */
3070 #define CAN_F1R1_FB14 CAN_F1R1_FB14_Msk /*!<Filter bit 14 */
3071 #define CAN_F1R1_FB15_Pos (15U)
3072 #define CAN_F1R1_FB15_Msk (0x1U << CAN_F1R1_FB15_Pos) /*!< 0x00008000 */
3073 #define CAN_F1R1_FB15 CAN_F1R1_FB15_Msk /*!<Filter bit 15 */
3074 #define CAN_F1R1_FB16_Pos (16U)
3075 #define CAN_F1R1_FB16_Msk (0x1U << CAN_F1R1_FB16_Pos) /*!< 0x00010000 */
3076 #define CAN_F1R1_FB16 CAN_F1R1_FB16_Msk /*!<Filter bit 16 */
3077 #define CAN_F1R1_FB17_Pos (17U)
3078 #define CAN_F1R1_FB17_Msk (0x1U << CAN_F1R1_FB17_Pos) /*!< 0x00020000 */
3079 #define CAN_F1R1_FB17 CAN_F1R1_FB17_Msk /*!<Filter bit 17 */
3080 #define CAN_F1R1_FB18_Pos (18U)
3081 #define CAN_F1R1_FB18_Msk (0x1U << CAN_F1R1_FB18_Pos) /*!< 0x00040000 */
3082 #define CAN_F1R1_FB18 CAN_F1R1_FB18_Msk /*!<Filter bit 18 */
3083 #define CAN_F1R1_FB19_Pos (19U)
3084 #define CAN_F1R1_FB19_Msk (0x1U << CAN_F1R1_FB19_Pos) /*!< 0x00080000 */
3085 #define CAN_F1R1_FB19 CAN_F1R1_FB19_Msk /*!<Filter bit 19 */
3086 #define CAN_F1R1_FB20_Pos (20U)
3087 #define CAN_F1R1_FB20_Msk (0x1U << CAN_F1R1_FB20_Pos) /*!< 0x00100000 */
3088 #define CAN_F1R1_FB20 CAN_F1R1_FB20_Msk /*!<Filter bit 20 */
3089 #define CAN_F1R1_FB21_Pos (21U)
3090 #define CAN_F1R1_FB21_Msk (0x1U << CAN_F1R1_FB21_Pos) /*!< 0x00200000 */
3091 #define CAN_F1R1_FB21 CAN_F1R1_FB21_Msk /*!<Filter bit 21 */
3092 #define CAN_F1R1_FB22_Pos (22U)
3093 #define CAN_F1R1_FB22_Msk (0x1U << CAN_F1R1_FB22_Pos) /*!< 0x00400000 */
3094 #define CAN_F1R1_FB22 CAN_F1R1_FB22_Msk /*!<Filter bit 22 */
3095 #define CAN_F1R1_FB23_Pos (23U)
3096 #define CAN_F1R1_FB23_Msk (0x1U << CAN_F1R1_FB23_Pos) /*!< 0x00800000 */
3097 #define CAN_F1R1_FB23 CAN_F1R1_FB23_Msk /*!<Filter bit 23 */
3098 #define CAN_F1R1_FB24_Pos (24U)
3099 #define CAN_F1R1_FB24_Msk (0x1U << CAN_F1R1_FB24_Pos) /*!< 0x01000000 */
3100 #define CAN_F1R1_FB24 CAN_F1R1_FB24_Msk /*!<Filter bit 24 */
3101 #define CAN_F1R1_FB25_Pos (25U)
3102 #define CAN_F1R1_FB25_Msk (0x1U << CAN_F1R1_FB25_Pos) /*!< 0x02000000 */
3103 #define CAN_F1R1_FB25 CAN_F1R1_FB25_Msk /*!<Filter bit 25 */
3104 #define CAN_F1R1_FB26_Pos (26U)
3105 #define CAN_F1R1_FB26_Msk (0x1U << CAN_F1R1_FB26_Pos) /*!< 0x04000000 */
3106 #define CAN_F1R1_FB26 CAN_F1R1_FB26_Msk /*!<Filter bit 26 */
3107 #define CAN_F1R1_FB27_Pos (27U)
3108 #define CAN_F1R1_FB27_Msk (0x1U << CAN_F1R1_FB27_Pos) /*!< 0x08000000 */
3109 #define CAN_F1R1_FB27 CAN_F1R1_FB27_Msk /*!<Filter bit 27 */
3110 #define CAN_F1R1_FB28_Pos (28U)
3111 #define CAN_F1R1_FB28_Msk (0x1U << CAN_F1R1_FB28_Pos) /*!< 0x10000000 */
3112 #define CAN_F1R1_FB28 CAN_F1R1_FB28_Msk /*!<Filter bit 28 */
3113 #define CAN_F1R1_FB29_Pos (29U)
3114 #define CAN_F1R1_FB29_Msk (0x1U << CAN_F1R1_FB29_Pos) /*!< 0x20000000 */
3115 #define CAN_F1R1_FB29 CAN_F1R1_FB29_Msk /*!<Filter bit 29 */
3116 #define CAN_F1R1_FB30_Pos (30U)
3117 #define CAN_F1R1_FB30_Msk (0x1U << CAN_F1R1_FB30_Pos) /*!< 0x40000000 */
3118 #define CAN_F1R1_FB30 CAN_F1R1_FB30_Msk /*!<Filter bit 30 */
3119 #define CAN_F1R1_FB31_Pos (31U)
3120 #define CAN_F1R1_FB31_Msk (0x1U << CAN_F1R1_FB31_Pos) /*!< 0x80000000 */
3121 #define CAN_F1R1_FB31 CAN_F1R1_FB31_Msk /*!<Filter bit 31 */
3122
3123 /******************* Bit definition for CAN_F2R1 register *******************/
3124 #define CAN_F2R1_FB0_Pos (0U)
3125 #define CAN_F2R1_FB0_Msk (0x1U << CAN_F2R1_FB0_Pos) /*!< 0x00000001 */
3126 #define CAN_F2R1_FB0 CAN_F2R1_FB0_Msk /*!<Filter bit 0 */
3127 #define CAN_F2R1_FB1_Pos (1U)
3128 #define CAN_F2R1_FB1_Msk (0x1U << CAN_F2R1_FB1_Pos) /*!< 0x00000002 */
3129 #define CAN_F2R1_FB1 CAN_F2R1_FB1_Msk /*!<Filter bit 1 */
3130 #define CAN_F2R1_FB2_Pos (2U)
3131 #define CAN_F2R1_FB2_Msk (0x1U << CAN_F2R1_FB2_Pos) /*!< 0x00000004 */
3132 #define CAN_F2R1_FB2 CAN_F2R1_FB2_Msk /*!<Filter bit 2 */
3133 #define CAN_F2R1_FB3_Pos (3U)
3134 #define CAN_F2R1_FB3_Msk (0x1U << CAN_F2R1_FB3_Pos) /*!< 0x00000008 */
3135 #define CAN_F2R1_FB3 CAN_F2R1_FB3_Msk /*!<Filter bit 3 */
3136 #define CAN_F2R1_FB4_Pos (4U)
3137 #define CAN_F2R1_FB4_Msk (0x1U << CAN_F2R1_FB4_Pos) /*!< 0x00000010 */
3138 #define CAN_F2R1_FB4 CAN_F2R1_FB4_Msk /*!<Filter bit 4 */
3139 #define CAN_F2R1_FB5_Pos (5U)
3140 #define CAN_F2R1_FB5_Msk (0x1U << CAN_F2R1_FB5_Pos) /*!< 0x00000020 */
3141 #define CAN_F2R1_FB5 CAN_F2R1_FB5_Msk /*!<Filter bit 5 */
3142 #define CAN_F2R1_FB6_Pos (6U)
3143 #define CAN_F2R1_FB6_Msk (0x1U << CAN_F2R1_FB6_Pos) /*!< 0x00000040 */
3144 #define CAN_F2R1_FB6 CAN_F2R1_FB6_Msk /*!<Filter bit 6 */
3145 #define CAN_F2R1_FB7_Pos (7U)
3146 #define CAN_F2R1_FB7_Msk (0x1U << CAN_F2R1_FB7_Pos) /*!< 0x00000080 */
3147 #define CAN_F2R1_FB7 CAN_F2R1_FB7_Msk /*!<Filter bit 7 */
3148 #define CAN_F2R1_FB8_Pos (8U)
3149 #define CAN_F2R1_FB8_Msk (0x1U << CAN_F2R1_FB8_Pos) /*!< 0x00000100 */
3150 #define CAN_F2R1_FB8 CAN_F2R1_FB8_Msk /*!<Filter bit 8 */
3151 #define CAN_F2R1_FB9_Pos (9U)
3152 #define CAN_F2R1_FB9_Msk (0x1U << CAN_F2R1_FB9_Pos) /*!< 0x00000200 */
3153 #define CAN_F2R1_FB9 CAN_F2R1_FB9_Msk /*!<Filter bit 9 */
3154 #define CAN_F2R1_FB10_Pos (10U)
3155 #define CAN_F2R1_FB10_Msk (0x1U << CAN_F2R1_FB10_Pos) /*!< 0x00000400 */
3156 #define CAN_F2R1_FB10 CAN_F2R1_FB10_Msk /*!<Filter bit 10 */
3157 #define CAN_F2R1_FB11_Pos (11U)
3158 #define CAN_F2R1_FB11_Msk (0x1U << CAN_F2R1_FB11_Pos) /*!< 0x00000800 */
3159 #define CAN_F2R1_FB11 CAN_F2R1_FB11_Msk /*!<Filter bit 11 */
3160 #define CAN_F2R1_FB12_Pos (12U)
3161 #define CAN_F2R1_FB12_Msk (0x1U << CAN_F2R1_FB12_Pos) /*!< 0x00001000 */
3162 #define CAN_F2R1_FB12 CAN_F2R1_FB12_Msk /*!<Filter bit 12 */
3163 #define CAN_F2R1_FB13_Pos (13U)
3164 #define CAN_F2R1_FB13_Msk (0x1U << CAN_F2R1_FB13_Pos) /*!< 0x00002000 */
3165 #define CAN_F2R1_FB13 CAN_F2R1_FB13_Msk /*!<Filter bit 13 */
3166 #define CAN_F2R1_FB14_Pos (14U)
3167 #define CAN_F2R1_FB14_Msk (0x1U << CAN_F2R1_FB14_Pos) /*!< 0x00004000 */
3168 #define CAN_F2R1_FB14 CAN_F2R1_FB14_Msk /*!<Filter bit 14 */
3169 #define CAN_F2R1_FB15_Pos (15U)
3170 #define CAN_F2R1_FB15_Msk (0x1U << CAN_F2R1_FB15_Pos) /*!< 0x00008000 */
3171 #define CAN_F2R1_FB15 CAN_F2R1_FB15_Msk /*!<Filter bit 15 */
3172 #define CAN_F2R1_FB16_Pos (16U)
3173 #define CAN_F2R1_FB16_Msk (0x1U << CAN_F2R1_FB16_Pos) /*!< 0x00010000 */
3174 #define CAN_F2R1_FB16 CAN_F2R1_FB16_Msk /*!<Filter bit 16 */
3175 #define CAN_F2R1_FB17_Pos (17U)
3176 #define CAN_F2R1_FB17_Msk (0x1U << CAN_F2R1_FB17_Pos) /*!< 0x00020000 */
3177 #define CAN_F2R1_FB17 CAN_F2R1_FB17_Msk /*!<Filter bit 17 */
3178 #define CAN_F2R1_FB18_Pos (18U)
3179 #define CAN_F2R1_FB18_Msk (0x1U << CAN_F2R1_FB18_Pos) /*!< 0x00040000 */
3180 #define CAN_F2R1_FB18 CAN_F2R1_FB18_Msk /*!<Filter bit 18 */
3181 #define CAN_F2R1_FB19_Pos (19U)
3182 #define CAN_F2R1_FB19_Msk (0x1U << CAN_F2R1_FB19_Pos) /*!< 0x00080000 */
3183 #define CAN_F2R1_FB19 CAN_F2R1_FB19_Msk /*!<Filter bit 19 */
3184 #define CAN_F2R1_FB20_Pos (20U)
3185 #define CAN_F2R1_FB20_Msk (0x1U << CAN_F2R1_FB20_Pos) /*!< 0x00100000 */
3186 #define CAN_F2R1_FB20 CAN_F2R1_FB20_Msk /*!<Filter bit 20 */
3187 #define CAN_F2R1_FB21_Pos (21U)
3188 #define CAN_F2R1_FB21_Msk (0x1U << CAN_F2R1_FB21_Pos) /*!< 0x00200000 */
3189 #define CAN_F2R1_FB21 CAN_F2R1_FB21_Msk /*!<Filter bit 21 */
3190 #define CAN_F2R1_FB22_Pos (22U)
3191 #define CAN_F2R1_FB22_Msk (0x1U << CAN_F2R1_FB22_Pos) /*!< 0x00400000 */
3192 #define CAN_F2R1_FB22 CAN_F2R1_FB22_Msk /*!<Filter bit 22 */
3193 #define CAN_F2R1_FB23_Pos (23U)
3194 #define CAN_F2R1_FB23_Msk (0x1U << CAN_F2R1_FB23_Pos) /*!< 0x00800000 */
3195 #define CAN_F2R1_FB23 CAN_F2R1_FB23_Msk /*!<Filter bit 23 */
3196 #define CAN_F2R1_FB24_Pos (24U)
3197 #define CAN_F2R1_FB24_Msk (0x1U << CAN_F2R1_FB24_Pos) /*!< 0x01000000 */
3198 #define CAN_F2R1_FB24 CAN_F2R1_FB24_Msk /*!<Filter bit 24 */
3199 #define CAN_F2R1_FB25_Pos (25U)
3200 #define CAN_F2R1_FB25_Msk (0x1U << CAN_F2R1_FB25_Pos) /*!< 0x02000000 */
3201 #define CAN_F2R1_FB25 CAN_F2R1_FB25_Msk /*!<Filter bit 25 */
3202 #define CAN_F2R1_FB26_Pos (26U)
3203 #define CAN_F2R1_FB26_Msk (0x1U << CAN_F2R1_FB26_Pos) /*!< 0x04000000 */
3204 #define CAN_F2R1_FB26 CAN_F2R1_FB26_Msk /*!<Filter bit 26 */
3205 #define CAN_F2R1_FB27_Pos (27U)
3206 #define CAN_F2R1_FB27_Msk (0x1U << CAN_F2R1_FB27_Pos) /*!< 0x08000000 */
3207 #define CAN_F2R1_FB27 CAN_F2R1_FB27_Msk /*!<Filter bit 27 */
3208 #define CAN_F2R1_FB28_Pos (28U)
3209 #define CAN_F2R1_FB28_Msk (0x1U << CAN_F2R1_FB28_Pos) /*!< 0x10000000 */
3210 #define CAN_F2R1_FB28 CAN_F2R1_FB28_Msk /*!<Filter bit 28 */
3211 #define CAN_F2R1_FB29_Pos (29U)
3212 #define CAN_F2R1_FB29_Msk (0x1U << CAN_F2R1_FB29_Pos) /*!< 0x20000000 */
3213 #define CAN_F2R1_FB29 CAN_F2R1_FB29_Msk /*!<Filter bit 29 */
3214 #define CAN_F2R1_FB30_Pos (30U)
3215 #define CAN_F2R1_FB30_Msk (0x1U << CAN_F2R1_FB30_Pos) /*!< 0x40000000 */
3216 #define CAN_F2R1_FB30 CAN_F2R1_FB30_Msk /*!<Filter bit 30 */
3217 #define CAN_F2R1_FB31_Pos (31U)
3218 #define CAN_F2R1_FB31_Msk (0x1U << CAN_F2R1_FB31_Pos) /*!< 0x80000000 */
3219 #define CAN_F2R1_FB31 CAN_F2R1_FB31_Msk /*!<Filter bit 31 */
3220
3221 /******************* Bit definition for CAN_F3R1 register *******************/
3222 #define CAN_F3R1_FB0_Pos (0U)
3223 #define CAN_F3R1_FB0_Msk (0x1U << CAN_F3R1_FB0_Pos) /*!< 0x00000001 */
3224 #define CAN_F3R1_FB0 CAN_F3R1_FB0_Msk /*!<Filter bit 0 */
3225 #define CAN_F3R1_FB1_Pos (1U)
3226 #define CAN_F3R1_FB1_Msk (0x1U << CAN_F3R1_FB1_Pos) /*!< 0x00000002 */
3227 #define CAN_F3R1_FB1 CAN_F3R1_FB1_Msk /*!<Filter bit 1 */
3228 #define CAN_F3R1_FB2_Pos (2U)
3229 #define CAN_F3R1_FB2_Msk (0x1U << CAN_F3R1_FB2_Pos) /*!< 0x00000004 */
3230 #define CAN_F3R1_FB2 CAN_F3R1_FB2_Msk /*!<Filter bit 2 */
3231 #define CAN_F3R1_FB3_Pos (3U)
3232 #define CAN_F3R1_FB3_Msk (0x1U << CAN_F3R1_FB3_Pos) /*!< 0x00000008 */
3233 #define CAN_F3R1_FB3 CAN_F3R1_FB3_Msk /*!<Filter bit 3 */
3234 #define CAN_F3R1_FB4_Pos (4U)
3235 #define CAN_F3R1_FB4_Msk (0x1U << CAN_F3R1_FB4_Pos) /*!< 0x00000010 */
3236 #define CAN_F3R1_FB4 CAN_F3R1_FB4_Msk /*!<Filter bit 4 */
3237 #define CAN_F3R1_FB5_Pos (5U)
3238 #define CAN_F3R1_FB5_Msk (0x1U << CAN_F3R1_FB5_Pos) /*!< 0x00000020 */
3239 #define CAN_F3R1_FB5 CAN_F3R1_FB5_Msk /*!<Filter bit 5 */
3240 #define CAN_F3R1_FB6_Pos (6U)
3241 #define CAN_F3R1_FB6_Msk (0x1U << CAN_F3R1_FB6_Pos) /*!< 0x00000040 */
3242 #define CAN_F3R1_FB6 CAN_F3R1_FB6_Msk /*!<Filter bit 6 */
3243 #define CAN_F3R1_FB7_Pos (7U)
3244 #define CAN_F3R1_FB7_Msk (0x1U << CAN_F3R1_FB7_Pos) /*!< 0x00000080 */
3245 #define CAN_F3R1_FB7 CAN_F3R1_FB7_Msk /*!<Filter bit 7 */
3246 #define CAN_F3R1_FB8_Pos (8U)
3247 #define CAN_F3R1_FB8_Msk (0x1U << CAN_F3R1_FB8_Pos) /*!< 0x00000100 */
3248 #define CAN_F3R1_FB8 CAN_F3R1_FB8_Msk /*!<Filter bit 8 */
3249 #define CAN_F3R1_FB9_Pos (9U)
3250 #define CAN_F3R1_FB9_Msk (0x1U << CAN_F3R1_FB9_Pos) /*!< 0x00000200 */
3251 #define CAN_F3R1_FB9 CAN_F3R1_FB9_Msk /*!<Filter bit 9 */
3252 #define CAN_F3R1_FB10_Pos (10U)
3253 #define CAN_F3R1_FB10_Msk (0x1U << CAN_F3R1_FB10_Pos) /*!< 0x00000400 */
3254 #define CAN_F3R1_FB10 CAN_F3R1_FB10_Msk /*!<Filter bit 10 */
3255 #define CAN_F3R1_FB11_Pos (11U)
3256 #define CAN_F3R1_FB11_Msk (0x1U << CAN_F3R1_FB11_Pos) /*!< 0x00000800 */
3257 #define CAN_F3R1_FB11 CAN_F3R1_FB11_Msk /*!<Filter bit 11 */
3258 #define CAN_F3R1_FB12_Pos (12U)
3259 #define CAN_F3R1_FB12_Msk (0x1U << CAN_F3R1_FB12_Pos) /*!< 0x00001000 */
3260 #define CAN_F3R1_FB12 CAN_F3R1_FB12_Msk /*!<Filter bit 12 */
3261 #define CAN_F3R1_FB13_Pos (13U)
3262 #define CAN_F3R1_FB13_Msk (0x1U << CAN_F3R1_FB13_Pos) /*!< 0x00002000 */
3263 #define CAN_F3R1_FB13 CAN_F3R1_FB13_Msk /*!<Filter bit 13 */
3264 #define CAN_F3R1_FB14_Pos (14U)
3265 #define CAN_F3R1_FB14_Msk (0x1U << CAN_F3R1_FB14_Pos) /*!< 0x00004000 */
3266 #define CAN_F3R1_FB14 CAN_F3R1_FB14_Msk /*!<Filter bit 14 */
3267 #define CAN_F3R1_FB15_Pos (15U)
3268 #define CAN_F3R1_FB15_Msk (0x1U << CAN_F3R1_FB15_Pos) /*!< 0x00008000 */
3269 #define CAN_F3R1_FB15 CAN_F3R1_FB15_Msk /*!<Filter bit 15 */
3270 #define CAN_F3R1_FB16_Pos (16U)
3271 #define CAN_F3R1_FB16_Msk (0x1U << CAN_F3R1_FB16_Pos) /*!< 0x00010000 */
3272 #define CAN_F3R1_FB16 CAN_F3R1_FB16_Msk /*!<Filter bit 16 */
3273 #define CAN_F3R1_FB17_Pos (17U)
3274 #define CAN_F3R1_FB17_Msk (0x1U << CAN_F3R1_FB17_Pos) /*!< 0x00020000 */
3275 #define CAN_F3R1_FB17 CAN_F3R1_FB17_Msk /*!<Filter bit 17 */
3276 #define CAN_F3R1_FB18_Pos (18U)
3277 #define CAN_F3R1_FB18_Msk (0x1U << CAN_F3R1_FB18_Pos) /*!< 0x00040000 */
3278 #define CAN_F3R1_FB18 CAN_F3R1_FB18_Msk /*!<Filter bit 18 */
3279 #define CAN_F3R1_FB19_Pos (19U)
3280 #define CAN_F3R1_FB19_Msk (0x1U << CAN_F3R1_FB19_Pos) /*!< 0x00080000 */
3281 #define CAN_F3R1_FB19 CAN_F3R1_FB19_Msk /*!<Filter bit 19 */
3282 #define CAN_F3R1_FB20_Pos (20U)
3283 #define CAN_F3R1_FB20_Msk (0x1U << CAN_F3R1_FB20_Pos) /*!< 0x00100000 */
3284 #define CAN_F3R1_FB20 CAN_F3R1_FB20_Msk /*!<Filter bit 20 */
3285 #define CAN_F3R1_FB21_Pos (21U)
3286 #define CAN_F3R1_FB21_Msk (0x1U << CAN_F3R1_FB21_Pos) /*!< 0x00200000 */
3287 #define CAN_F3R1_FB21 CAN_F3R1_FB21_Msk /*!<Filter bit 21 */
3288 #define CAN_F3R1_FB22_Pos (22U)
3289 #define CAN_F3R1_FB22_Msk (0x1U << CAN_F3R1_FB22_Pos) /*!< 0x00400000 */
3290 #define CAN_F3R1_FB22 CAN_F3R1_FB22_Msk /*!<Filter bit 22 */
3291 #define CAN_F3R1_FB23_Pos (23U)
3292 #define CAN_F3R1_FB23_Msk (0x1U << CAN_F3R1_FB23_Pos) /*!< 0x00800000 */
3293 #define CAN_F3R1_FB23 CAN_F3R1_FB23_Msk /*!<Filter bit 23 */
3294 #define CAN_F3R1_FB24_Pos (24U)
3295 #define CAN_F3R1_FB24_Msk (0x1U << CAN_F3R1_FB24_Pos) /*!< 0x01000000 */
3296 #define CAN_F3R1_FB24 CAN_F3R1_FB24_Msk /*!<Filter bit 24 */
3297 #define CAN_F3R1_FB25_Pos (25U)
3298 #define CAN_F3R1_FB25_Msk (0x1U << CAN_F3R1_FB25_Pos) /*!< 0x02000000 */
3299 #define CAN_F3R1_FB25 CAN_F3R1_FB25_Msk /*!<Filter bit 25 */
3300 #define CAN_F3R1_FB26_Pos (26U)
3301 #define CAN_F3R1_FB26_Msk (0x1U << CAN_F3R1_FB26_Pos) /*!< 0x04000000 */
3302 #define CAN_F3R1_FB26 CAN_F3R1_FB26_Msk /*!<Filter bit 26 */
3303 #define CAN_F3R1_FB27_Pos (27U)
3304 #define CAN_F3R1_FB27_Msk (0x1U << CAN_F3R1_FB27_Pos) /*!< 0x08000000 */
3305 #define CAN_F3R1_FB27 CAN_F3R1_FB27_Msk /*!<Filter bit 27 */
3306 #define CAN_F3R1_FB28_Pos (28U)
3307 #define CAN_F3R1_FB28_Msk (0x1U << CAN_F3R1_FB28_Pos) /*!< 0x10000000 */
3308 #define CAN_F3R1_FB28 CAN_F3R1_FB28_Msk /*!<Filter bit 28 */
3309 #define CAN_F3R1_FB29_Pos (29U)
3310 #define CAN_F3R1_FB29_Msk (0x1U << CAN_F3R1_FB29_Pos) /*!< 0x20000000 */
3311 #define CAN_F3R1_FB29 CAN_F3R1_FB29_Msk /*!<Filter bit 29 */
3312 #define CAN_F3R1_FB30_Pos (30U)
3313 #define CAN_F3R1_FB30_Msk (0x1U << CAN_F3R1_FB30_Pos) /*!< 0x40000000 */
3314 #define CAN_F3R1_FB30 CAN_F3R1_FB30_Msk /*!<Filter bit 30 */
3315 #define CAN_F3R1_FB31_Pos (31U)
3316 #define CAN_F3R1_FB31_Msk (0x1U << CAN_F3R1_FB31_Pos) /*!< 0x80000000 */
3317 #define CAN_F3R1_FB31 CAN_F3R1_FB31_Msk /*!<Filter bit 31 */
3318
3319 /******************* Bit definition for CAN_F4R1 register *******************/
3320 #define CAN_F4R1_FB0_Pos (0U)
3321 #define CAN_F4R1_FB0_Msk (0x1U << CAN_F4R1_FB0_Pos) /*!< 0x00000001 */
3322 #define CAN_F4R1_FB0 CAN_F4R1_FB0_Msk /*!<Filter bit 0 */
3323 #define CAN_F4R1_FB1_Pos (1U)
3324 #define CAN_F4R1_FB1_Msk (0x1U << CAN_F4R1_FB1_Pos) /*!< 0x00000002 */
3325 #define CAN_F4R1_FB1 CAN_F4R1_FB1_Msk /*!<Filter bit 1 */
3326 #define CAN_F4R1_FB2_Pos (2U)
3327 #define CAN_F4R1_FB2_Msk (0x1U << CAN_F4R1_FB2_Pos) /*!< 0x00000004 */
3328 #define CAN_F4R1_FB2 CAN_F4R1_FB2_Msk /*!<Filter bit 2 */
3329 #define CAN_F4R1_FB3_Pos (3U)
3330 #define CAN_F4R1_FB3_Msk (0x1U << CAN_F4R1_FB3_Pos) /*!< 0x00000008 */
3331 #define CAN_F4R1_FB3 CAN_F4R1_FB3_Msk /*!<Filter bit 3 */
3332 #define CAN_F4R1_FB4_Pos (4U)
3333 #define CAN_F4R1_FB4_Msk (0x1U << CAN_F4R1_FB4_Pos) /*!< 0x00000010 */
3334 #define CAN_F4R1_FB4 CAN_F4R1_FB4_Msk /*!<Filter bit 4 */
3335 #define CAN_F4R1_FB5_Pos (5U)
3336 #define CAN_F4R1_FB5_Msk (0x1U << CAN_F4R1_FB5_Pos) /*!< 0x00000020 */
3337 #define CAN_F4R1_FB5 CAN_F4R1_FB5_Msk /*!<Filter bit 5 */
3338 #define CAN_F4R1_FB6_Pos (6U)
3339 #define CAN_F4R1_FB6_Msk (0x1U << CAN_F4R1_FB6_Pos) /*!< 0x00000040 */
3340 #define CAN_F4R1_FB6 CAN_F4R1_FB6_Msk /*!<Filter bit 6 */
3341 #define CAN_F4R1_FB7_Pos (7U)
3342 #define CAN_F4R1_FB7_Msk (0x1U << CAN_F4R1_FB7_Pos) /*!< 0x00000080 */
3343 #define CAN_F4R1_FB7 CAN_F4R1_FB7_Msk /*!<Filter bit 7 */
3344 #define CAN_F4R1_FB8_Pos (8U)
3345 #define CAN_F4R1_FB8_Msk (0x1U << CAN_F4R1_FB8_Pos) /*!< 0x00000100 */
3346 #define CAN_F4R1_FB8 CAN_F4R1_FB8_Msk /*!<Filter bit 8 */
3347 #define CAN_F4R1_FB9_Pos (9U)
3348 #define CAN_F4R1_FB9_Msk (0x1U << CAN_F4R1_FB9_Pos) /*!< 0x00000200 */
3349 #define CAN_F4R1_FB9 CAN_F4R1_FB9_Msk /*!<Filter bit 9 */
3350 #define CAN_F4R1_FB10_Pos (10U)
3351 #define CAN_F4R1_FB10_Msk (0x1U << CAN_F4R1_FB10_Pos) /*!< 0x00000400 */
3352 #define CAN_F4R1_FB10 CAN_F4R1_FB10_Msk /*!<Filter bit 10 */
3353 #define CAN_F4R1_FB11_Pos (11U)
3354 #define CAN_F4R1_FB11_Msk (0x1U << CAN_F4R1_FB11_Pos) /*!< 0x00000800 */
3355 #define CAN_F4R1_FB11 CAN_F4R1_FB11_Msk /*!<Filter bit 11 */
3356 #define CAN_F4R1_FB12_Pos (12U)
3357 #define CAN_F4R1_FB12_Msk (0x1U << CAN_F4R1_FB12_Pos) /*!< 0x00001000 */
3358 #define CAN_F4R1_FB12 CAN_F4R1_FB12_Msk /*!<Filter bit 12 */
3359 #define CAN_F4R1_FB13_Pos (13U)
3360 #define CAN_F4R1_FB13_Msk (0x1U << CAN_F4R1_FB13_Pos) /*!< 0x00002000 */
3361 #define CAN_F4R1_FB13 CAN_F4R1_FB13_Msk /*!<Filter bit 13 */
3362 #define CAN_F4R1_FB14_Pos (14U)
3363 #define CAN_F4R1_FB14_Msk (0x1U << CAN_F4R1_FB14_Pos) /*!< 0x00004000 */
3364 #define CAN_F4R1_FB14 CAN_F4R1_FB14_Msk /*!<Filter bit 14 */
3365 #define CAN_F4R1_FB15_Pos (15U)
3366 #define CAN_F4R1_FB15_Msk (0x1U << CAN_F4R1_FB15_Pos) /*!< 0x00008000 */
3367 #define CAN_F4R1_FB15 CAN_F4R1_FB15_Msk /*!<Filter bit 15 */
3368 #define CAN_F4R1_FB16_Pos (16U)
3369 #define CAN_F4R1_FB16_Msk (0x1U << CAN_F4R1_FB16_Pos) /*!< 0x00010000 */
3370 #define CAN_F4R1_FB16 CAN_F4R1_FB16_Msk /*!<Filter bit 16 */
3371 #define CAN_F4R1_FB17_Pos (17U)
3372 #define CAN_F4R1_FB17_Msk (0x1U << CAN_F4R1_FB17_Pos) /*!< 0x00020000 */
3373 #define CAN_F4R1_FB17 CAN_F4R1_FB17_Msk /*!<Filter bit 17 */
3374 #define CAN_F4R1_FB18_Pos (18U)
3375 #define CAN_F4R1_FB18_Msk (0x1U << CAN_F4R1_FB18_Pos) /*!< 0x00040000 */
3376 #define CAN_F4R1_FB18 CAN_F4R1_FB18_Msk /*!<Filter bit 18 */
3377 #define CAN_F4R1_FB19_Pos (19U)
3378 #define CAN_F4R1_FB19_Msk (0x1U << CAN_F4R1_FB19_Pos) /*!< 0x00080000 */
3379 #define CAN_F4R1_FB19 CAN_F4R1_FB19_Msk /*!<Filter bit 19 */
3380 #define CAN_F4R1_FB20_Pos (20U)
3381 #define CAN_F4R1_FB20_Msk (0x1U << CAN_F4R1_FB20_Pos) /*!< 0x00100000 */
3382 #define CAN_F4R1_FB20 CAN_F4R1_FB20_Msk /*!<Filter bit 20 */
3383 #define CAN_F4R1_FB21_Pos (21U)
3384 #define CAN_F4R1_FB21_Msk (0x1U << CAN_F4R1_FB21_Pos) /*!< 0x00200000 */
3385 #define CAN_F4R1_FB21 CAN_F4R1_FB21_Msk /*!<Filter bit 21 */
3386 #define CAN_F4R1_FB22_Pos (22U)
3387 #define CAN_F4R1_FB22_Msk (0x1U << CAN_F4R1_FB22_Pos) /*!< 0x00400000 */
3388 #define CAN_F4R1_FB22 CAN_F4R1_FB22_Msk /*!<Filter bit 22 */
3389 #define CAN_F4R1_FB23_Pos (23U)
3390 #define CAN_F4R1_FB23_Msk (0x1U << CAN_F4R1_FB23_Pos) /*!< 0x00800000 */
3391 #define CAN_F4R1_FB23 CAN_F4R1_FB23_Msk /*!<Filter bit 23 */
3392 #define CAN_F4R1_FB24_Pos (24U)
3393 #define CAN_F4R1_FB24_Msk (0x1U << CAN_F4R1_FB24_Pos) /*!< 0x01000000 */
3394 #define CAN_F4R1_FB24 CAN_F4R1_FB24_Msk /*!<Filter bit 24 */
3395 #define CAN_F4R1_FB25_Pos (25U)
3396 #define CAN_F4R1_FB25_Msk (0x1U << CAN_F4R1_FB25_Pos) /*!< 0x02000000 */
3397 #define CAN_F4R1_FB25 CAN_F4R1_FB25_Msk /*!<Filter bit 25 */
3398 #define CAN_F4R1_FB26_Pos (26U)
3399 #define CAN_F4R1_FB26_Msk (0x1U << CAN_F4R1_FB26_Pos) /*!< 0x04000000 */
3400 #define CAN_F4R1_FB26 CAN_F4R1_FB26_Msk /*!<Filter bit 26 */
3401 #define CAN_F4R1_FB27_Pos (27U)
3402 #define CAN_F4R1_FB27_Msk (0x1U << CAN_F4R1_FB27_Pos) /*!< 0x08000000 */
3403 #define CAN_F4R1_FB27 CAN_F4R1_FB27_Msk /*!<Filter bit 27 */
3404 #define CAN_F4R1_FB28_Pos (28U)
3405 #define CAN_F4R1_FB28_Msk (0x1U << CAN_F4R1_FB28_Pos) /*!< 0x10000000 */
3406 #define CAN_F4R1_FB28 CAN_F4R1_FB28_Msk /*!<Filter bit 28 */
3407 #define CAN_F4R1_FB29_Pos (29U)
3408 #define CAN_F4R1_FB29_Msk (0x1U << CAN_F4R1_FB29_Pos) /*!< 0x20000000 */
3409 #define CAN_F4R1_FB29 CAN_F4R1_FB29_Msk /*!<Filter bit 29 */
3410 #define CAN_F4R1_FB30_Pos (30U)
3411 #define CAN_F4R1_FB30_Msk (0x1U << CAN_F4R1_FB30_Pos) /*!< 0x40000000 */
3412 #define CAN_F4R1_FB30 CAN_F4R1_FB30_Msk /*!<Filter bit 30 */
3413 #define CAN_F4R1_FB31_Pos (31U)
3414 #define CAN_F4R1_FB31_Msk (0x1U << CAN_F4R1_FB31_Pos) /*!< 0x80000000 */
3415 #define CAN_F4R1_FB31 CAN_F4R1_FB31_Msk /*!<Filter bit 31 */
3416
3417 /******************* Bit definition for CAN_F5R1 register *******************/
3418 #define CAN_F5R1_FB0_Pos (0U)
3419 #define CAN_F5R1_FB0_Msk (0x1U << CAN_F5R1_FB0_Pos) /*!< 0x00000001 */
3420 #define CAN_F5R1_FB0 CAN_F5R1_FB0_Msk /*!<Filter bit 0 */
3421 #define CAN_F5R1_FB1_Pos (1U)
3422 #define CAN_F5R1_FB1_Msk (0x1U << CAN_F5R1_FB1_Pos) /*!< 0x00000002 */
3423 #define CAN_F5R1_FB1 CAN_F5R1_FB1_Msk /*!<Filter bit 1 */
3424 #define CAN_F5R1_FB2_Pos (2U)
3425 #define CAN_F5R1_FB2_Msk (0x1U << CAN_F5R1_FB2_Pos) /*!< 0x00000004 */
3426 #define CAN_F5R1_FB2 CAN_F5R1_FB2_Msk /*!<Filter bit 2 */
3427 #define CAN_F5R1_FB3_Pos (3U)
3428 #define CAN_F5R1_FB3_Msk (0x1U << CAN_F5R1_FB3_Pos) /*!< 0x00000008 */
3429 #define CAN_F5R1_FB3 CAN_F5R1_FB3_Msk /*!<Filter bit 3 */
3430 #define CAN_F5R1_FB4_Pos (4U)
3431 #define CAN_F5R1_FB4_Msk (0x1U << CAN_F5R1_FB4_Pos) /*!< 0x00000010 */
3432 #define CAN_F5R1_FB4 CAN_F5R1_FB4_Msk /*!<Filter bit 4 */
3433 #define CAN_F5R1_FB5_Pos (5U)
3434 #define CAN_F5R1_FB5_Msk (0x1U << CAN_F5R1_FB5_Pos) /*!< 0x00000020 */
3435 #define CAN_F5R1_FB5 CAN_F5R1_FB5_Msk /*!<Filter bit 5 */
3436 #define CAN_F5R1_FB6_Pos (6U)
3437 #define CAN_F5R1_FB6_Msk (0x1U << CAN_F5R1_FB6_Pos) /*!< 0x00000040 */
3438 #define CAN_F5R1_FB6 CAN_F5R1_FB6_Msk /*!<Filter bit 6 */
3439 #define CAN_F5R1_FB7_Pos (7U)
3440 #define CAN_F5R1_FB7_Msk (0x1U << CAN_F5R1_FB7_Pos) /*!< 0x00000080 */
3441 #define CAN_F5R1_FB7 CAN_F5R1_FB7_Msk /*!<Filter bit 7 */
3442 #define CAN_F5R1_FB8_Pos (8U)
3443 #define CAN_F5R1_FB8_Msk (0x1U << CAN_F5R1_FB8_Pos) /*!< 0x00000100 */
3444 #define CAN_F5R1_FB8 CAN_F5R1_FB8_Msk /*!<Filter bit 8 */
3445 #define CAN_F5R1_FB9_Pos (9U)
3446 #define CAN_F5R1_FB9_Msk (0x1U << CAN_F5R1_FB9_Pos) /*!< 0x00000200 */
3447 #define CAN_F5R1_FB9 CAN_F5R1_FB9_Msk /*!<Filter bit 9 */
3448 #define CAN_F5R1_FB10_Pos (10U)
3449 #define CAN_F5R1_FB10_Msk (0x1U << CAN_F5R1_FB10_Pos) /*!< 0x00000400 */
3450 #define CAN_F5R1_FB10 CAN_F5R1_FB10_Msk /*!<Filter bit 10 */
3451 #define CAN_F5R1_FB11_Pos (11U)
3452 #define CAN_F5R1_FB11_Msk (0x1U << CAN_F5R1_FB11_Pos) /*!< 0x00000800 */
3453 #define CAN_F5R1_FB11 CAN_F5R1_FB11_Msk /*!<Filter bit 11 */
3454 #define CAN_F5R1_FB12_Pos (12U)
3455 #define CAN_F5R1_FB12_Msk (0x1U << CAN_F5R1_FB12_Pos) /*!< 0x00001000 */
3456 #define CAN_F5R1_FB12 CAN_F5R1_FB12_Msk /*!<Filter bit 12 */
3457 #define CAN_F5R1_FB13_Pos (13U)
3458 #define CAN_F5R1_FB13_Msk (0x1U << CAN_F5R1_FB13_Pos) /*!< 0x00002000 */
3459 #define CAN_F5R1_FB13 CAN_F5R1_FB13_Msk /*!<Filter bit 13 */
3460 #define CAN_F5R1_FB14_Pos (14U)
3461 #define CAN_F5R1_FB14_Msk (0x1U << CAN_F5R1_FB14_Pos) /*!< 0x00004000 */
3462 #define CAN_F5R1_FB14 CAN_F5R1_FB14_Msk /*!<Filter bit 14 */
3463 #define CAN_F5R1_FB15_Pos (15U)
3464 #define CAN_F5R1_FB15_Msk (0x1U << CAN_F5R1_FB15_Pos) /*!< 0x00008000 */
3465 #define CAN_F5R1_FB15 CAN_F5R1_FB15_Msk /*!<Filter bit 15 */
3466 #define CAN_F5R1_FB16_Pos (16U)
3467 #define CAN_F5R1_FB16_Msk (0x1U << CAN_F5R1_FB16_Pos) /*!< 0x00010000 */
3468 #define CAN_F5R1_FB16 CAN_F5R1_FB16_Msk /*!<Filter bit 16 */
3469 #define CAN_F5R1_FB17_Pos (17U)
3470 #define CAN_F5R1_FB17_Msk (0x1U << CAN_F5R1_FB17_Pos) /*!< 0x00020000 */
3471 #define CAN_F5R1_FB17 CAN_F5R1_FB17_Msk /*!<Filter bit 17 */
3472 #define CAN_F5R1_FB18_Pos (18U)
3473 #define CAN_F5R1_FB18_Msk (0x1U << CAN_F5R1_FB18_Pos) /*!< 0x00040000 */
3474 #define CAN_F5R1_FB18 CAN_F5R1_FB18_Msk /*!<Filter bit 18 */
3475 #define CAN_F5R1_FB19_Pos (19U)
3476 #define CAN_F5R1_FB19_Msk (0x1U << CAN_F5R1_FB19_Pos) /*!< 0x00080000 */
3477 #define CAN_F5R1_FB19 CAN_F5R1_FB19_Msk /*!<Filter bit 19 */
3478 #define CAN_F5R1_FB20_Pos (20U)
3479 #define CAN_F5R1_FB20_Msk (0x1U << CAN_F5R1_FB20_Pos) /*!< 0x00100000 */
3480 #define CAN_F5R1_FB20 CAN_F5R1_FB20_Msk /*!<Filter bit 20 */
3481 #define CAN_F5R1_FB21_Pos (21U)
3482 #define CAN_F5R1_FB21_Msk (0x1U << CAN_F5R1_FB21_Pos) /*!< 0x00200000 */
3483 #define CAN_F5R1_FB21 CAN_F5R1_FB21_Msk /*!<Filter bit 21 */
3484 #define CAN_F5R1_FB22_Pos (22U)
3485 #define CAN_F5R1_FB22_Msk (0x1U << CAN_F5R1_FB22_Pos) /*!< 0x00400000 */
3486 #define CAN_F5R1_FB22 CAN_F5R1_FB22_Msk /*!<Filter bit 22 */
3487 #define CAN_F5R1_FB23_Pos (23U)
3488 #define CAN_F5R1_FB23_Msk (0x1U << CAN_F5R1_FB23_Pos) /*!< 0x00800000 */
3489 #define CAN_F5R1_FB23 CAN_F5R1_FB23_Msk /*!<Filter bit 23 */
3490 #define CAN_F5R1_FB24_Pos (24U)
3491 #define CAN_F5R1_FB24_Msk (0x1U << CAN_F5R1_FB24_Pos) /*!< 0x01000000 */
3492 #define CAN_F5R1_FB24 CAN_F5R1_FB24_Msk /*!<Filter bit 24 */
3493 #define CAN_F5R1_FB25_Pos (25U)
3494 #define CAN_F5R1_FB25_Msk (0x1U << CAN_F5R1_FB25_Pos) /*!< 0x02000000 */
3495 #define CAN_F5R1_FB25 CAN_F5R1_FB25_Msk /*!<Filter bit 25 */
3496 #define CAN_F5R1_FB26_Pos (26U)
3497 #define CAN_F5R1_FB26_Msk (0x1U << CAN_F5R1_FB26_Pos) /*!< 0x04000000 */
3498 #define CAN_F5R1_FB26 CAN_F5R1_FB26_Msk /*!<Filter bit 26 */
3499 #define CAN_F5R1_FB27_Pos (27U)
3500 #define CAN_F5R1_FB27_Msk (0x1U << CAN_F5R1_FB27_Pos) /*!< 0x08000000 */
3501 #define CAN_F5R1_FB27 CAN_F5R1_FB27_Msk /*!<Filter bit 27 */
3502 #define CAN_F5R1_FB28_Pos (28U)
3503 #define CAN_F5R1_FB28_Msk (0x1U << CAN_F5R1_FB28_Pos) /*!< 0x10000000 */
3504 #define CAN_F5R1_FB28 CAN_F5R1_FB28_Msk /*!<Filter bit 28 */
3505 #define CAN_F5R1_FB29_Pos (29U)
3506 #define CAN_F5R1_FB29_Msk (0x1U << CAN_F5R1_FB29_Pos) /*!< 0x20000000 */
3507 #define CAN_F5R1_FB29 CAN_F5R1_FB29_Msk /*!<Filter bit 29 */
3508 #define CAN_F5R1_FB30_Pos (30U)
3509 #define CAN_F5R1_FB30_Msk (0x1U << CAN_F5R1_FB30_Pos) /*!< 0x40000000 */
3510 #define CAN_F5R1_FB30 CAN_F5R1_FB30_Msk /*!<Filter bit 30 */
3511 #define CAN_F5R1_FB31_Pos (31U)
3512 #define CAN_F5R1_FB31_Msk (0x1U << CAN_F5R1_FB31_Pos) /*!< 0x80000000 */
3513 #define CAN_F5R1_FB31 CAN_F5R1_FB31_Msk /*!<Filter bit 31 */
3514
3515 /******************* Bit definition for CAN_F6R1 register *******************/
3516 #define CAN_F6R1_FB0_Pos (0U)
3517 #define CAN_F6R1_FB0_Msk (0x1U << CAN_F6R1_FB0_Pos) /*!< 0x00000001 */
3518 #define CAN_F6R1_FB0 CAN_F6R1_FB0_Msk /*!<Filter bit 0 */
3519 #define CAN_F6R1_FB1_Pos (1U)
3520 #define CAN_F6R1_FB1_Msk (0x1U << CAN_F6R1_FB1_Pos) /*!< 0x00000002 */
3521 #define CAN_F6R1_FB1 CAN_F6R1_FB1_Msk /*!<Filter bit 1 */
3522 #define CAN_F6R1_FB2_Pos (2U)
3523 #define CAN_F6R1_FB2_Msk (0x1U << CAN_F6R1_FB2_Pos) /*!< 0x00000004 */
3524 #define CAN_F6R1_FB2 CAN_F6R1_FB2_Msk /*!<Filter bit 2 */
3525 #define CAN_F6R1_FB3_Pos (3U)
3526 #define CAN_F6R1_FB3_Msk (0x1U << CAN_F6R1_FB3_Pos) /*!< 0x00000008 */
3527 #define CAN_F6R1_FB3 CAN_F6R1_FB3_Msk /*!<Filter bit 3 */
3528 #define CAN_F6R1_FB4_Pos (4U)
3529 #define CAN_F6R1_FB4_Msk (0x1U << CAN_F6R1_FB4_Pos) /*!< 0x00000010 */
3530 #define CAN_F6R1_FB4 CAN_F6R1_FB4_Msk /*!<Filter bit 4 */
3531 #define CAN_F6R1_FB5_Pos (5U)
3532 #define CAN_F6R1_FB5_Msk (0x1U << CAN_F6R1_FB5_Pos) /*!< 0x00000020 */
3533 #define CAN_F6R1_FB5 CAN_F6R1_FB5_Msk /*!<Filter bit 5 */
3534 #define CAN_F6R1_FB6_Pos (6U)
3535 #define CAN_F6R1_FB6_Msk (0x1U << CAN_F6R1_FB6_Pos) /*!< 0x00000040 */
3536 #define CAN_F6R1_FB6 CAN_F6R1_FB6_Msk /*!<Filter bit 6 */
3537 #define CAN_F6R1_FB7_Pos (7U)
3538 #define CAN_F6R1_FB7_Msk (0x1U << CAN_F6R1_FB7_Pos) /*!< 0x00000080 */
3539 #define CAN_F6R1_FB7 CAN_F6R1_FB7_Msk /*!<Filter bit 7 */
3540 #define CAN_F6R1_FB8_Pos (8U)
3541 #define CAN_F6R1_FB8_Msk (0x1U << CAN_F6R1_FB8_Pos) /*!< 0x00000100 */
3542 #define CAN_F6R1_FB8 CAN_F6R1_FB8_Msk /*!<Filter bit 8 */
3543 #define CAN_F6R1_FB9_Pos (9U)
3544 #define CAN_F6R1_FB9_Msk (0x1U << CAN_F6R1_FB9_Pos) /*!< 0x00000200 */
3545 #define CAN_F6R1_FB9 CAN_F6R1_FB9_Msk /*!<Filter bit 9 */
3546 #define CAN_F6R1_FB10_Pos (10U)
3547 #define CAN_F6R1_FB10_Msk (0x1U << CAN_F6R1_FB10_Pos) /*!< 0x00000400 */
3548 #define CAN_F6R1_FB10 CAN_F6R1_FB10_Msk /*!<Filter bit 10 */
3549 #define CAN_F6R1_FB11_Pos (11U)
3550 #define CAN_F6R1_FB11_Msk (0x1U << CAN_F6R1_FB11_Pos) /*!< 0x00000800 */
3551 #define CAN_F6R1_FB11 CAN_F6R1_FB11_Msk /*!<Filter bit 11 */
3552 #define CAN_F6R1_FB12_Pos (12U)
3553 #define CAN_F6R1_FB12_Msk (0x1U << CAN_F6R1_FB12_Pos) /*!< 0x00001000 */
3554 #define CAN_F6R1_FB12 CAN_F6R1_FB12_Msk /*!<Filter bit 12 */
3555 #define CAN_F6R1_FB13_Pos (13U)
3556 #define CAN_F6R1_FB13_Msk (0x1U << CAN_F6R1_FB13_Pos) /*!< 0x00002000 */
3557 #define CAN_F6R1_FB13 CAN_F6R1_FB13_Msk /*!<Filter bit 13 */
3558 #define CAN_F6R1_FB14_Pos (14U)
3559 #define CAN_F6R1_FB14_Msk (0x1U << CAN_F6R1_FB14_Pos) /*!< 0x00004000 */
3560 #define CAN_F6R1_FB14 CAN_F6R1_FB14_Msk /*!<Filter bit 14 */
3561 #define CAN_F6R1_FB15_Pos (15U)
3562 #define CAN_F6R1_FB15_Msk (0x1U << CAN_F6R1_FB15_Pos) /*!< 0x00008000 */
3563 #define CAN_F6R1_FB15 CAN_F6R1_FB15_Msk /*!<Filter bit 15 */
3564 #define CAN_F6R1_FB16_Pos (16U)
3565 #define CAN_F6R1_FB16_Msk (0x1U << CAN_F6R1_FB16_Pos) /*!< 0x00010000 */
3566 #define CAN_F6R1_FB16 CAN_F6R1_FB16_Msk /*!<Filter bit 16 */
3567 #define CAN_F6R1_FB17_Pos (17U)
3568 #define CAN_F6R1_FB17_Msk (0x1U << CAN_F6R1_FB17_Pos) /*!< 0x00020000 */
3569 #define CAN_F6R1_FB17 CAN_F6R1_FB17_Msk /*!<Filter bit 17 */
3570 #define CAN_F6R1_FB18_Pos (18U)
3571 #define CAN_F6R1_FB18_Msk (0x1U << CAN_F6R1_FB18_Pos) /*!< 0x00040000 */
3572 #define CAN_F6R1_FB18 CAN_F6R1_FB18_Msk /*!<Filter bit 18 */
3573 #define CAN_F6R1_FB19_Pos (19U)
3574 #define CAN_F6R1_FB19_Msk (0x1U << CAN_F6R1_FB19_Pos) /*!< 0x00080000 */
3575 #define CAN_F6R1_FB19 CAN_F6R1_FB19_Msk /*!<Filter bit 19 */
3576 #define CAN_F6R1_FB20_Pos (20U)
3577 #define CAN_F6R1_FB20_Msk (0x1U << CAN_F6R1_FB20_Pos) /*!< 0x00100000 */
3578 #define CAN_F6R1_FB20 CAN_F6R1_FB20_Msk /*!<Filter bit 20 */
3579 #define CAN_F6R1_FB21_Pos (21U)
3580 #define CAN_F6R1_FB21_Msk (0x1U << CAN_F6R1_FB21_Pos) /*!< 0x00200000 */
3581 #define CAN_F6R1_FB21 CAN_F6R1_FB21_Msk /*!<Filter bit 21 */
3582 #define CAN_F6R1_FB22_Pos (22U)
3583 #define CAN_F6R1_FB22_Msk (0x1U << CAN_F6R1_FB22_Pos) /*!< 0x00400000 */
3584 #define CAN_F6R1_FB22 CAN_F6R1_FB22_Msk /*!<Filter bit 22 */
3585 #define CAN_F6R1_FB23_Pos (23U)
3586 #define CAN_F6R1_FB23_Msk (0x1U << CAN_F6R1_FB23_Pos) /*!< 0x00800000 */
3587 #define CAN_F6R1_FB23 CAN_F6R1_FB23_Msk /*!<Filter bit 23 */
3588 #define CAN_F6R1_FB24_Pos (24U)
3589 #define CAN_F6R1_FB24_Msk (0x1U << CAN_F6R1_FB24_Pos) /*!< 0x01000000 */
3590 #define CAN_F6R1_FB24 CAN_F6R1_FB24_Msk /*!<Filter bit 24 */
3591 #define CAN_F6R1_FB25_Pos (25U)
3592 #define CAN_F6R1_FB25_Msk (0x1U << CAN_F6R1_FB25_Pos) /*!< 0x02000000 */
3593 #define CAN_F6R1_FB25 CAN_F6R1_FB25_Msk /*!<Filter bit 25 */
3594 #define CAN_F6R1_FB26_Pos (26U)
3595 #define CAN_F6R1_FB26_Msk (0x1U << CAN_F6R1_FB26_Pos) /*!< 0x04000000 */
3596 #define CAN_F6R1_FB26 CAN_F6R1_FB26_Msk /*!<Filter bit 26 */
3597 #define CAN_F6R1_FB27_Pos (27U)
3598 #define CAN_F6R1_FB27_Msk (0x1U << CAN_F6R1_FB27_Pos) /*!< 0x08000000 */
3599 #define CAN_F6R1_FB27 CAN_F6R1_FB27_Msk /*!<Filter bit 27 */
3600 #define CAN_F6R1_FB28_Pos (28U)
3601 #define CAN_F6R1_FB28_Msk (0x1U << CAN_F6R1_FB28_Pos) /*!< 0x10000000 */
3602 #define CAN_F6R1_FB28 CAN_F6R1_FB28_Msk /*!<Filter bit 28 */
3603 #define CAN_F6R1_FB29_Pos (29U)
3604 #define CAN_F6R1_FB29_Msk (0x1U << CAN_F6R1_FB29_Pos) /*!< 0x20000000 */
3605 #define CAN_F6R1_FB29 CAN_F6R1_FB29_Msk /*!<Filter bit 29 */
3606 #define CAN_F6R1_FB30_Pos (30U)
3607 #define CAN_F6R1_FB30_Msk (0x1U << CAN_F6R1_FB30_Pos) /*!< 0x40000000 */
3608 #define CAN_F6R1_FB30 CAN_F6R1_FB30_Msk /*!<Filter bit 30 */
3609 #define CAN_F6R1_FB31_Pos (31U)
3610 #define CAN_F6R1_FB31_Msk (0x1U << CAN_F6R1_FB31_Pos) /*!< 0x80000000 */
3611 #define CAN_F6R1_FB31 CAN_F6R1_FB31_Msk /*!<Filter bit 31 */
3612
3613 /******************* Bit definition for CAN_F7R1 register *******************/
3614 #define CAN_F7R1_FB0_Pos (0U)
3615 #define CAN_F7R1_FB0_Msk (0x1U << CAN_F7R1_FB0_Pos) /*!< 0x00000001 */
3616 #define CAN_F7R1_FB0 CAN_F7R1_FB0_Msk /*!<Filter bit 0 */
3617 #define CAN_F7R1_FB1_Pos (1U)
3618 #define CAN_F7R1_FB1_Msk (0x1U << CAN_F7R1_FB1_Pos) /*!< 0x00000002 */
3619 #define CAN_F7R1_FB1 CAN_F7R1_FB1_Msk /*!<Filter bit 1 */
3620 #define CAN_F7R1_FB2_Pos (2U)
3621 #define CAN_F7R1_FB2_Msk (0x1U << CAN_F7R1_FB2_Pos) /*!< 0x00000004 */
3622 #define CAN_F7R1_FB2 CAN_F7R1_FB2_Msk /*!<Filter bit 2 */
3623 #define CAN_F7R1_FB3_Pos (3U)
3624 #define CAN_F7R1_FB3_Msk (0x1U << CAN_F7R1_FB3_Pos) /*!< 0x00000008 */
3625 #define CAN_F7R1_FB3 CAN_F7R1_FB3_Msk /*!<Filter bit 3 */
3626 #define CAN_F7R1_FB4_Pos (4U)
3627 #define CAN_F7R1_FB4_Msk (0x1U << CAN_F7R1_FB4_Pos) /*!< 0x00000010 */
3628 #define CAN_F7R1_FB4 CAN_F7R1_FB4_Msk /*!<Filter bit 4 */
3629 #define CAN_F7R1_FB5_Pos (5U)
3630 #define CAN_F7R1_FB5_Msk (0x1U << CAN_F7R1_FB5_Pos) /*!< 0x00000020 */
3631 #define CAN_F7R1_FB5 CAN_F7R1_FB5_Msk /*!<Filter bit 5 */
3632 #define CAN_F7R1_FB6_Pos (6U)
3633 #define CAN_F7R1_FB6_Msk (0x1U << CAN_F7R1_FB6_Pos) /*!< 0x00000040 */
3634 #define CAN_F7R1_FB6 CAN_F7R1_FB6_Msk /*!<Filter bit 6 */
3635 #define CAN_F7R1_FB7_Pos (7U)
3636 #define CAN_F7R1_FB7_Msk (0x1U << CAN_F7R1_FB7_Pos) /*!< 0x00000080 */
3637 #define CAN_F7R1_FB7 CAN_F7R1_FB7_Msk /*!<Filter bit 7 */
3638 #define CAN_F7R1_FB8_Pos (8U)
3639 #define CAN_F7R1_FB8_Msk (0x1U << CAN_F7R1_FB8_Pos) /*!< 0x00000100 */
3640 #define CAN_F7R1_FB8 CAN_F7R1_FB8_Msk /*!<Filter bit 8 */
3641 #define CAN_F7R1_FB9_Pos (9U)
3642 #define CAN_F7R1_FB9_Msk (0x1U << CAN_F7R1_FB9_Pos) /*!< 0x00000200 */
3643 #define CAN_F7R1_FB9 CAN_F7R1_FB9_Msk /*!<Filter bit 9 */
3644 #define CAN_F7R1_FB10_Pos (10U)
3645 #define CAN_F7R1_FB10_Msk (0x1U << CAN_F7R1_FB10_Pos) /*!< 0x00000400 */
3646 #define CAN_F7R1_FB10 CAN_F7R1_FB10_Msk /*!<Filter bit 10 */
3647 #define CAN_F7R1_FB11_Pos (11U)
3648 #define CAN_F7R1_FB11_Msk (0x1U << CAN_F7R1_FB11_Pos) /*!< 0x00000800 */
3649 #define CAN_F7R1_FB11 CAN_F7R1_FB11_Msk /*!<Filter bit 11 */
3650 #define CAN_F7R1_FB12_Pos (12U)
3651 #define CAN_F7R1_FB12_Msk (0x1U << CAN_F7R1_FB12_Pos) /*!< 0x00001000 */
3652 #define CAN_F7R1_FB12 CAN_F7R1_FB12_Msk /*!<Filter bit 12 */
3653 #define CAN_F7R1_FB13_Pos (13U)
3654 #define CAN_F7R1_FB13_Msk (0x1U << CAN_F7R1_FB13_Pos) /*!< 0x00002000 */
3655 #define CAN_F7R1_FB13 CAN_F7R1_FB13_Msk /*!<Filter bit 13 */
3656 #define CAN_F7R1_FB14_Pos (14U)
3657 #define CAN_F7R1_FB14_Msk (0x1U << CAN_F7R1_FB14_Pos) /*!< 0x00004000 */
3658 #define CAN_F7R1_FB14 CAN_F7R1_FB14_Msk /*!<Filter bit 14 */
3659 #define CAN_F7R1_FB15_Pos (15U)
3660 #define CAN_F7R1_FB15_Msk (0x1U << CAN_F7R1_FB15_Pos) /*!< 0x00008000 */
3661 #define CAN_F7R1_FB15 CAN_F7R1_FB15_Msk /*!<Filter bit 15 */
3662 #define CAN_F7R1_FB16_Pos (16U)
3663 #define CAN_F7R1_FB16_Msk (0x1U << CAN_F7R1_FB16_Pos) /*!< 0x00010000 */
3664 #define CAN_F7R1_FB16 CAN_F7R1_FB16_Msk /*!<Filter bit 16 */
3665 #define CAN_F7R1_FB17_Pos (17U)
3666 #define CAN_F7R1_FB17_Msk (0x1U << CAN_F7R1_FB17_Pos) /*!< 0x00020000 */
3667 #define CAN_F7R1_FB17 CAN_F7R1_FB17_Msk /*!<Filter bit 17 */
3668 #define CAN_F7R1_FB18_Pos (18U)
3669 #define CAN_F7R1_FB18_Msk (0x1U << CAN_F7R1_FB18_Pos) /*!< 0x00040000 */
3670 #define CAN_F7R1_FB18 CAN_F7R1_FB18_Msk /*!<Filter bit 18 */
3671 #define CAN_F7R1_FB19_Pos (19U)
3672 #define CAN_F7R1_FB19_Msk (0x1U << CAN_F7R1_FB19_Pos) /*!< 0x00080000 */
3673 #define CAN_F7R1_FB19 CAN_F7R1_FB19_Msk /*!<Filter bit 19 */
3674 #define CAN_F7R1_FB20_Pos (20U)
3675 #define CAN_F7R1_FB20_Msk (0x1U << CAN_F7R1_FB20_Pos) /*!< 0x00100000 */
3676 #define CAN_F7R1_FB20 CAN_F7R1_FB20_Msk /*!<Filter bit 20 */
3677 #define CAN_F7R1_FB21_Pos (21U)
3678 #define CAN_F7R1_FB21_Msk (0x1U << CAN_F7R1_FB21_Pos) /*!< 0x00200000 */
3679 #define CAN_F7R1_FB21 CAN_F7R1_FB21_Msk /*!<Filter bit 21 */
3680 #define CAN_F7R1_FB22_Pos (22U)
3681 #define CAN_F7R1_FB22_Msk (0x1U << CAN_F7R1_FB22_Pos) /*!< 0x00400000 */
3682 #define CAN_F7R1_FB22 CAN_F7R1_FB22_Msk /*!<Filter bit 22 */
3683 #define CAN_F7R1_FB23_Pos (23U)
3684 #define CAN_F7R1_FB23_Msk (0x1U << CAN_F7R1_FB23_Pos) /*!< 0x00800000 */
3685 #define CAN_F7R1_FB23 CAN_F7R1_FB23_Msk /*!<Filter bit 23 */
3686 #define CAN_F7R1_FB24_Pos (24U)
3687 #define CAN_F7R1_FB24_Msk (0x1U << CAN_F7R1_FB24_Pos) /*!< 0x01000000 */
3688 #define CAN_F7R1_FB24 CAN_F7R1_FB24_Msk /*!<Filter bit 24 */
3689 #define CAN_F7R1_FB25_Pos (25U)
3690 #define CAN_F7R1_FB25_Msk (0x1U << CAN_F7R1_FB25_Pos) /*!< 0x02000000 */
3691 #define CAN_F7R1_FB25 CAN_F7R1_FB25_Msk /*!<Filter bit 25 */
3692 #define CAN_F7R1_FB26_Pos (26U)
3693 #define CAN_F7R1_FB26_Msk (0x1U << CAN_F7R1_FB26_Pos) /*!< 0x04000000 */
3694 #define CAN_F7R1_FB26 CAN_F7R1_FB26_Msk /*!<Filter bit 26 */
3695 #define CAN_F7R1_FB27_Pos (27U)
3696 #define CAN_F7R1_FB27_Msk (0x1U << CAN_F7R1_FB27_Pos) /*!< 0x08000000 */
3697 #define CAN_F7R1_FB27 CAN_F7R1_FB27_Msk /*!<Filter bit 27 */
3698 #define CAN_F7R1_FB28_Pos (28U)
3699 #define CAN_F7R1_FB28_Msk (0x1U << CAN_F7R1_FB28_Pos) /*!< 0x10000000 */
3700 #define CAN_F7R1_FB28 CAN_F7R1_FB28_Msk /*!<Filter bit 28 */
3701 #define CAN_F7R1_FB29_Pos (29U)
3702 #define CAN_F7R1_FB29_Msk (0x1U << CAN_F7R1_FB29_Pos) /*!< 0x20000000 */
3703 #define CAN_F7R1_FB29 CAN_F7R1_FB29_Msk /*!<Filter bit 29 */
3704 #define CAN_F7R1_FB30_Pos (30U)
3705 #define CAN_F7R1_FB30_Msk (0x1U << CAN_F7R1_FB30_Pos) /*!< 0x40000000 */
3706 #define CAN_F7R1_FB30 CAN_F7R1_FB30_Msk /*!<Filter bit 30 */
3707 #define CAN_F7R1_FB31_Pos (31U)
3708 #define CAN_F7R1_FB31_Msk (0x1U << CAN_F7R1_FB31_Pos) /*!< 0x80000000 */
3709 #define CAN_F7R1_FB31 CAN_F7R1_FB31_Msk /*!<Filter bit 31 */
3710
3711 /******************* Bit definition for CAN_F8R1 register *******************/
3712 #define CAN_F8R1_FB0_Pos (0U)
3713 #define CAN_F8R1_FB0_Msk (0x1U << CAN_F8R1_FB0_Pos) /*!< 0x00000001 */
3714 #define CAN_F8R1_FB0 CAN_F8R1_FB0_Msk /*!<Filter bit 0 */
3715 #define CAN_F8R1_FB1_Pos (1U)
3716 #define CAN_F8R1_FB1_Msk (0x1U << CAN_F8R1_FB1_Pos) /*!< 0x00000002 */
3717 #define CAN_F8R1_FB1 CAN_F8R1_FB1_Msk /*!<Filter bit 1 */
3718 #define CAN_F8R1_FB2_Pos (2U)
3719 #define CAN_F8R1_FB2_Msk (0x1U << CAN_F8R1_FB2_Pos) /*!< 0x00000004 */
3720 #define CAN_F8R1_FB2 CAN_F8R1_FB2_Msk /*!<Filter bit 2 */
3721 #define CAN_F8R1_FB3_Pos (3U)
3722 #define CAN_F8R1_FB3_Msk (0x1U << CAN_F8R1_FB3_Pos) /*!< 0x00000008 */
3723 #define CAN_F8R1_FB3 CAN_F8R1_FB3_Msk /*!<Filter bit 3 */
3724 #define CAN_F8R1_FB4_Pos (4U)
3725 #define CAN_F8R1_FB4_Msk (0x1U << CAN_F8R1_FB4_Pos) /*!< 0x00000010 */
3726 #define CAN_F8R1_FB4 CAN_F8R1_FB4_Msk /*!<Filter bit 4 */
3727 #define CAN_F8R1_FB5_Pos (5U)
3728 #define CAN_F8R1_FB5_Msk (0x1U << CAN_F8R1_FB5_Pos) /*!< 0x00000020 */
3729 #define CAN_F8R1_FB5 CAN_F8R1_FB5_Msk /*!<Filter bit 5 */
3730 #define CAN_F8R1_FB6_Pos (6U)
3731 #define CAN_F8R1_FB6_Msk (0x1U << CAN_F8R1_FB6_Pos) /*!< 0x00000040 */
3732 #define CAN_F8R1_FB6 CAN_F8R1_FB6_Msk /*!<Filter bit 6 */
3733 #define CAN_F8R1_FB7_Pos (7U)
3734 #define CAN_F8R1_FB7_Msk (0x1U << CAN_F8R1_FB7_Pos) /*!< 0x00000080 */
3735 #define CAN_F8R1_FB7 CAN_F8R1_FB7_Msk /*!<Filter bit 7 */
3736 #define CAN_F8R1_FB8_Pos (8U)
3737 #define CAN_F8R1_FB8_Msk (0x1U << CAN_F8R1_FB8_Pos) /*!< 0x00000100 */
3738 #define CAN_F8R1_FB8 CAN_F8R1_FB8_Msk /*!<Filter bit 8 */
3739 #define CAN_F8R1_FB9_Pos (9U)
3740 #define CAN_F8R1_FB9_Msk (0x1U << CAN_F8R1_FB9_Pos) /*!< 0x00000200 */
3741 #define CAN_F8R1_FB9 CAN_F8R1_FB9_Msk /*!<Filter bit 9 */
3742 #define CAN_F8R1_FB10_Pos (10U)
3743 #define CAN_F8R1_FB10_Msk (0x1U << CAN_F8R1_FB10_Pos) /*!< 0x00000400 */
3744 #define CAN_F8R1_FB10 CAN_F8R1_FB10_Msk /*!<Filter bit 10 */
3745 #define CAN_F8R1_FB11_Pos (11U)
3746 #define CAN_F8R1_FB11_Msk (0x1U << CAN_F8R1_FB11_Pos) /*!< 0x00000800 */
3747 #define CAN_F8R1_FB11 CAN_F8R1_FB11_Msk /*!<Filter bit 11 */
3748 #define CAN_F8R1_FB12_Pos (12U)
3749 #define CAN_F8R1_FB12_Msk (0x1U << CAN_F8R1_FB12_Pos) /*!< 0x00001000 */
3750 #define CAN_F8R1_FB12 CAN_F8R1_FB12_Msk /*!<Filter bit 12 */
3751 #define CAN_F8R1_FB13_Pos (13U)
3752 #define CAN_F8R1_FB13_Msk (0x1U << CAN_F8R1_FB13_Pos) /*!< 0x00002000 */
3753 #define CAN_F8R1_FB13 CAN_F8R1_FB13_Msk /*!<Filter bit 13 */
3754 #define CAN_F8R1_FB14_Pos (14U)
3755 #define CAN_F8R1_FB14_Msk (0x1U << CAN_F8R1_FB14_Pos) /*!< 0x00004000 */
3756 #define CAN_F8R1_FB14 CAN_F8R1_FB14_Msk /*!<Filter bit 14 */
3757 #define CAN_F8R1_FB15_Pos (15U)
3758 #define CAN_F8R1_FB15_Msk (0x1U << CAN_F8R1_FB15_Pos) /*!< 0x00008000 */
3759 #define CAN_F8R1_FB15 CAN_F8R1_FB15_Msk /*!<Filter bit 15 */
3760 #define CAN_F8R1_FB16_Pos (16U)
3761 #define CAN_F8R1_FB16_Msk (0x1U << CAN_F8R1_FB16_Pos) /*!< 0x00010000 */
3762 #define CAN_F8R1_FB16 CAN_F8R1_FB16_Msk /*!<Filter bit 16 */
3763 #define CAN_F8R1_FB17_Pos (17U)
3764 #define CAN_F8R1_FB17_Msk (0x1U << CAN_F8R1_FB17_Pos) /*!< 0x00020000 */
3765 #define CAN_F8R1_FB17 CAN_F8R1_FB17_Msk /*!<Filter bit 17 */
3766 #define CAN_F8R1_FB18_Pos (18U)
3767 #define CAN_F8R1_FB18_Msk (0x1U << CAN_F8R1_FB18_Pos) /*!< 0x00040000 */
3768 #define CAN_F8R1_FB18 CAN_F8R1_FB18_Msk /*!<Filter bit 18 */
3769 #define CAN_F8R1_FB19_Pos (19U)
3770 #define CAN_F8R1_FB19_Msk (0x1U << CAN_F8R1_FB19_Pos) /*!< 0x00080000 */
3771 #define CAN_F8R1_FB19 CAN_F8R1_FB19_Msk /*!<Filter bit 19 */
3772 #define CAN_F8R1_FB20_Pos (20U)
3773 #define CAN_F8R1_FB20_Msk (0x1U << CAN_F8R1_FB20_Pos) /*!< 0x00100000 */
3774 #define CAN_F8R1_FB20 CAN_F8R1_FB20_Msk /*!<Filter bit 20 */
3775 #define CAN_F8R1_FB21_Pos (21U)
3776 #define CAN_F8R1_FB21_Msk (0x1U << CAN_F8R1_FB21_Pos) /*!< 0x00200000 */
3777 #define CAN_F8R1_FB21 CAN_F8R1_FB21_Msk /*!<Filter bit 21 */
3778 #define CAN_F8R1_FB22_Pos (22U)
3779 #define CAN_F8R1_FB22_Msk (0x1U << CAN_F8R1_FB22_Pos) /*!< 0x00400000 */
3780 #define CAN_F8R1_FB22 CAN_F8R1_FB22_Msk /*!<Filter bit 22 */
3781 #define CAN_F8R1_FB23_Pos (23U)
3782 #define CAN_F8R1_FB23_Msk (0x1U << CAN_F8R1_FB23_Pos) /*!< 0x00800000 */
3783 #define CAN_F8R1_FB23 CAN_F8R1_FB23_Msk /*!<Filter bit 23 */
3784 #define CAN_F8R1_FB24_Pos (24U)
3785 #define CAN_F8R1_FB24_Msk (0x1U << CAN_F8R1_FB24_Pos) /*!< 0x01000000 */
3786 #define CAN_F8R1_FB24 CAN_F8R1_FB24_Msk /*!<Filter bit 24 */
3787 #define CAN_F8R1_FB25_Pos (25U)
3788 #define CAN_F8R1_FB25_Msk (0x1U << CAN_F8R1_FB25_Pos) /*!< 0x02000000 */
3789 #define CAN_F8R1_FB25 CAN_F8R1_FB25_Msk /*!<Filter bit 25 */
3790 #define CAN_F8R1_FB26_Pos (26U)
3791 #define CAN_F8R1_FB26_Msk (0x1U << CAN_F8R1_FB26_Pos) /*!< 0x04000000 */
3792 #define CAN_F8R1_FB26 CAN_F8R1_FB26_Msk /*!<Filter bit 26 */
3793 #define CAN_F8R1_FB27_Pos (27U)
3794 #define CAN_F8R1_FB27_Msk (0x1U << CAN_F8R1_FB27_Pos) /*!< 0x08000000 */
3795 #define CAN_F8R1_FB27 CAN_F8R1_FB27_Msk /*!<Filter bit 27 */
3796 #define CAN_F8R1_FB28_Pos (28U)
3797 #define CAN_F8R1_FB28_Msk (0x1U << CAN_F8R1_FB28_Pos) /*!< 0x10000000 */
3798 #define CAN_F8R1_FB28 CAN_F8R1_FB28_Msk /*!<Filter bit 28 */
3799 #define CAN_F8R1_FB29_Pos (29U)
3800 #define CAN_F8R1_FB29_Msk (0x1U << CAN_F8R1_FB29_Pos) /*!< 0x20000000 */
3801 #define CAN_F8R1_FB29 CAN_F8R1_FB29_Msk /*!<Filter bit 29 */
3802 #define CAN_F8R1_FB30_Pos (30U)
3803 #define CAN_F8R1_FB30_Msk (0x1U << CAN_F8R1_FB30_Pos) /*!< 0x40000000 */
3804 #define CAN_F8R1_FB30 CAN_F8R1_FB30_Msk /*!<Filter bit 30 */
3805 #define CAN_F8R1_FB31_Pos (31U)
3806 #define CAN_F8R1_FB31_Msk (0x1U << CAN_F8R1_FB31_Pos) /*!< 0x80000000 */
3807 #define CAN_F8R1_FB31 CAN_F8R1_FB31_Msk /*!<Filter bit 31 */
3808
3809 /******************* Bit definition for CAN_F9R1 register *******************/
3810 #define CAN_F9R1_FB0_Pos (0U)
3811 #define CAN_F9R1_FB0_Msk (0x1U << CAN_F9R1_FB0_Pos) /*!< 0x00000001 */
3812 #define CAN_F9R1_FB0 CAN_F9R1_FB0_Msk /*!<Filter bit 0 */
3813 #define CAN_F9R1_FB1_Pos (1U)
3814 #define CAN_F9R1_FB1_Msk (0x1U << CAN_F9R1_FB1_Pos) /*!< 0x00000002 */
3815 #define CAN_F9R1_FB1 CAN_F9R1_FB1_Msk /*!<Filter bit 1 */
3816 #define CAN_F9R1_FB2_Pos (2U)
3817 #define CAN_F9R1_FB2_Msk (0x1U << CAN_F9R1_FB2_Pos) /*!< 0x00000004 */
3818 #define CAN_F9R1_FB2 CAN_F9R1_FB2_Msk /*!<Filter bit 2 */
3819 #define CAN_F9R1_FB3_Pos (3U)
3820 #define CAN_F9R1_FB3_Msk (0x1U << CAN_F9R1_FB3_Pos) /*!< 0x00000008 */
3821 #define CAN_F9R1_FB3 CAN_F9R1_FB3_Msk /*!<Filter bit 3 */
3822 #define CAN_F9R1_FB4_Pos (4U)
3823 #define CAN_F9R1_FB4_Msk (0x1U << CAN_F9R1_FB4_Pos) /*!< 0x00000010 */
3824 #define CAN_F9R1_FB4 CAN_F9R1_FB4_Msk /*!<Filter bit 4 */
3825 #define CAN_F9R1_FB5_Pos (5U)
3826 #define CAN_F9R1_FB5_Msk (0x1U << CAN_F9R1_FB5_Pos) /*!< 0x00000020 */
3827 #define CAN_F9R1_FB5 CAN_F9R1_FB5_Msk /*!<Filter bit 5 */
3828 #define CAN_F9R1_FB6_Pos (6U)
3829 #define CAN_F9R1_FB6_Msk (0x1U << CAN_F9R1_FB6_Pos) /*!< 0x00000040 */
3830 #define CAN_F9R1_FB6 CAN_F9R1_FB6_Msk /*!<Filter bit 6 */
3831 #define CAN_F9R1_FB7_Pos (7U)
3832 #define CAN_F9R1_FB7_Msk (0x1U << CAN_F9R1_FB7_Pos) /*!< 0x00000080 */
3833 #define CAN_F9R1_FB7 CAN_F9R1_FB7_Msk /*!<Filter bit 7 */
3834 #define CAN_F9R1_FB8_Pos (8U)
3835 #define CAN_F9R1_FB8_Msk (0x1U << CAN_F9R1_FB8_Pos) /*!< 0x00000100 */
3836 #define CAN_F9R1_FB8 CAN_F9R1_FB8_Msk /*!<Filter bit 8 */
3837 #define CAN_F9R1_FB9_Pos (9U)
3838 #define CAN_F9R1_FB9_Msk (0x1U << CAN_F9R1_FB9_Pos) /*!< 0x00000200 */
3839 #define CAN_F9R1_FB9 CAN_F9R1_FB9_Msk /*!<Filter bit 9 */
3840 #define CAN_F9R1_FB10_Pos (10U)
3841 #define CAN_F9R1_FB10_Msk (0x1U << CAN_F9R1_FB10_Pos) /*!< 0x00000400 */
3842 #define CAN_F9R1_FB10 CAN_F9R1_FB10_Msk /*!<Filter bit 10 */
3843 #define CAN_F9R1_FB11_Pos (11U)
3844 #define CAN_F9R1_FB11_Msk (0x1U << CAN_F9R1_FB11_Pos) /*!< 0x00000800 */
3845 #define CAN_F9R1_FB11 CAN_F9R1_FB11_Msk /*!<Filter bit 11 */
3846 #define CAN_F9R1_FB12_Pos (12U)
3847 #define CAN_F9R1_FB12_Msk (0x1U << CAN_F9R1_FB12_Pos) /*!< 0x00001000 */
3848 #define CAN_F9R1_FB12 CAN_F9R1_FB12_Msk /*!<Filter bit 12 */
3849 #define CAN_F9R1_FB13_Pos (13U)
3850 #define CAN_F9R1_FB13_Msk (0x1U << CAN_F9R1_FB13_Pos) /*!< 0x00002000 */
3851 #define CAN_F9R1_FB13 CAN_F9R1_FB13_Msk /*!<Filter bit 13 */
3852 #define CAN_F9R1_FB14_Pos (14U)
3853 #define CAN_F9R1_FB14_Msk (0x1U << CAN_F9R1_FB14_Pos) /*!< 0x00004000 */
3854 #define CAN_F9R1_FB14 CAN_F9R1_FB14_Msk /*!<Filter bit 14 */
3855 #define CAN_F9R1_FB15_Pos (15U)
3856 #define CAN_F9R1_FB15_Msk (0x1U << CAN_F9R1_FB15_Pos) /*!< 0x00008000 */
3857 #define CAN_F9R1_FB15 CAN_F9R1_FB15_Msk /*!<Filter bit 15 */
3858 #define CAN_F9R1_FB16_Pos (16U)
3859 #define CAN_F9R1_FB16_Msk (0x1U << CAN_F9R1_FB16_Pos) /*!< 0x00010000 */
3860 #define CAN_F9R1_FB16 CAN_F9R1_FB16_Msk /*!<Filter bit 16 */
3861 #define CAN_F9R1_FB17_Pos (17U)
3862 #define CAN_F9R1_FB17_Msk (0x1U << CAN_F9R1_FB17_Pos) /*!< 0x00020000 */
3863 #define CAN_F9R1_FB17 CAN_F9R1_FB17_Msk /*!<Filter bit 17 */
3864 #define CAN_F9R1_FB18_Pos (18U)
3865 #define CAN_F9R1_FB18_Msk (0x1U << CAN_F9R1_FB18_Pos) /*!< 0x00040000 */
3866 #define CAN_F9R1_FB18 CAN_F9R1_FB18_Msk /*!<Filter bit 18 */
3867 #define CAN_F9R1_FB19_Pos (19U)
3868 #define CAN_F9R1_FB19_Msk (0x1U << CAN_F9R1_FB19_Pos) /*!< 0x00080000 */
3869 #define CAN_F9R1_FB19 CAN_F9R1_FB19_Msk /*!<Filter bit 19 */
3870 #define CAN_F9R1_FB20_Pos (20U)
3871 #define CAN_F9R1_FB20_Msk (0x1U << CAN_F9R1_FB20_Pos) /*!< 0x00100000 */
3872 #define CAN_F9R1_FB20 CAN_F9R1_FB20_Msk /*!<Filter bit 20 */
3873 #define CAN_F9R1_FB21_Pos (21U)
3874 #define CAN_F9R1_FB21_Msk (0x1U << CAN_F9R1_FB21_Pos) /*!< 0x00200000 */
3875 #define CAN_F9R1_FB21 CAN_F9R1_FB21_Msk /*!<Filter bit 21 */
3876 #define CAN_F9R1_FB22_Pos (22U)
3877 #define CAN_F9R1_FB22_Msk (0x1U << CAN_F9R1_FB22_Pos) /*!< 0x00400000 */
3878 #define CAN_F9R1_FB22 CAN_F9R1_FB22_Msk /*!<Filter bit 22 */
3879 #define CAN_F9R1_FB23_Pos (23U)
3880 #define CAN_F9R1_FB23_Msk (0x1U << CAN_F9R1_FB23_Pos) /*!< 0x00800000 */
3881 #define CAN_F9R1_FB23 CAN_F9R1_FB23_Msk /*!<Filter bit 23 */
3882 #define CAN_F9R1_FB24_Pos (24U)
3883 #define CAN_F9R1_FB24_Msk (0x1U << CAN_F9R1_FB24_Pos) /*!< 0x01000000 */
3884 #define CAN_F9R1_FB24 CAN_F9R1_FB24_Msk /*!<Filter bit 24 */
3885 #define CAN_F9R1_FB25_Pos (25U)
3886 #define CAN_F9R1_FB25_Msk (0x1U << CAN_F9R1_FB25_Pos) /*!< 0x02000000 */
3887 #define CAN_F9R1_FB25 CAN_F9R1_FB25_Msk /*!<Filter bit 25 */
3888 #define CAN_F9R1_FB26_Pos (26U)
3889 #define CAN_F9R1_FB26_Msk (0x1U << CAN_F9R1_FB26_Pos) /*!< 0x04000000 */
3890 #define CAN_F9R1_FB26 CAN_F9R1_FB26_Msk /*!<Filter bit 26 */
3891 #define CAN_F9R1_FB27_Pos (27U)
3892 #define CAN_F9R1_FB27_Msk (0x1U << CAN_F9R1_FB27_Pos) /*!< 0x08000000 */
3893 #define CAN_F9R1_FB27 CAN_F9R1_FB27_Msk /*!<Filter bit 27 */
3894 #define CAN_F9R1_FB28_Pos (28U)
3895 #define CAN_F9R1_FB28_Msk (0x1U << CAN_F9R1_FB28_Pos) /*!< 0x10000000 */
3896 #define CAN_F9R1_FB28 CAN_F9R1_FB28_Msk /*!<Filter bit 28 */
3897 #define CAN_F9R1_FB29_Pos (29U)
3898 #define CAN_F9R1_FB29_Msk (0x1U << CAN_F9R1_FB29_Pos) /*!< 0x20000000 */
3899 #define CAN_F9R1_FB29 CAN_F9R1_FB29_Msk /*!<Filter bit 29 */
3900 #define CAN_F9R1_FB30_Pos (30U)
3901 #define CAN_F9R1_FB30_Msk (0x1U << CAN_F9R1_FB30_Pos) /*!< 0x40000000 */
3902 #define CAN_F9R1_FB30 CAN_F9R1_FB30_Msk /*!<Filter bit 30 */
3903 #define CAN_F9R1_FB31_Pos (31U)
3904 #define CAN_F9R1_FB31_Msk (0x1U << CAN_F9R1_FB31_Pos) /*!< 0x80000000 */
3905 #define CAN_F9R1_FB31 CAN_F9R1_FB31_Msk /*!<Filter bit 31 */
3906
3907 /******************* Bit definition for CAN_F10R1 register ******************/
3908 #define CAN_F10R1_FB0_Pos (0U)
3909 #define CAN_F10R1_FB0_Msk (0x1U << CAN_F10R1_FB0_Pos) /*!< 0x00000001 */
3910 #define CAN_F10R1_FB0 CAN_F10R1_FB0_Msk /*!<Filter bit 0 */
3911 #define CAN_F10R1_FB1_Pos (1U)
3912 #define CAN_F10R1_FB1_Msk (0x1U << CAN_F10R1_FB1_Pos) /*!< 0x00000002 */
3913 #define CAN_F10R1_FB1 CAN_F10R1_FB1_Msk /*!<Filter bit 1 */
3914 #define CAN_F10R1_FB2_Pos (2U)
3915 #define CAN_F10R1_FB2_Msk (0x1U << CAN_F10R1_FB2_Pos) /*!< 0x00000004 */
3916 #define CAN_F10R1_FB2 CAN_F10R1_FB2_Msk /*!<Filter bit 2 */
3917 #define CAN_F10R1_FB3_Pos (3U)
3918 #define CAN_F10R1_FB3_Msk (0x1U << CAN_F10R1_FB3_Pos) /*!< 0x00000008 */
3919 #define CAN_F10R1_FB3 CAN_F10R1_FB3_Msk /*!<Filter bit 3 */
3920 #define CAN_F10R1_FB4_Pos (4U)
3921 #define CAN_F10R1_FB4_Msk (0x1U << CAN_F10R1_FB4_Pos) /*!< 0x00000010 */
3922 #define CAN_F10R1_FB4 CAN_F10R1_FB4_Msk /*!<Filter bit 4 */
3923 #define CAN_F10R1_FB5_Pos (5U)
3924 #define CAN_F10R1_FB5_Msk (0x1U << CAN_F10R1_FB5_Pos) /*!< 0x00000020 */
3925 #define CAN_F10R1_FB5 CAN_F10R1_FB5_Msk /*!<Filter bit 5 */
3926 #define CAN_F10R1_FB6_Pos (6U)
3927 #define CAN_F10R1_FB6_Msk (0x1U << CAN_F10R1_FB6_Pos) /*!< 0x00000040 */
3928 #define CAN_F10R1_FB6 CAN_F10R1_FB6_Msk /*!<Filter bit 6 */
3929 #define CAN_F10R1_FB7_Pos (7U)
3930 #define CAN_F10R1_FB7_Msk (0x1U << CAN_F10R1_FB7_Pos) /*!< 0x00000080 */
3931 #define CAN_F10R1_FB7 CAN_F10R1_FB7_Msk /*!<Filter bit 7 */
3932 #define CAN_F10R1_FB8_Pos (8U)
3933 #define CAN_F10R1_FB8_Msk (0x1U << CAN_F10R1_FB8_Pos) /*!< 0x00000100 */
3934 #define CAN_F10R1_FB8 CAN_F10R1_FB8_Msk /*!<Filter bit 8 */
3935 #define CAN_F10R1_FB9_Pos (9U)
3936 #define CAN_F10R1_FB9_Msk (0x1U << CAN_F10R1_FB9_Pos) /*!< 0x00000200 */
3937 #define CAN_F10R1_FB9 CAN_F10R1_FB9_Msk /*!<Filter bit 9 */
3938 #define CAN_F10R1_FB10_Pos (10U)
3939 #define CAN_F10R1_FB10_Msk (0x1U << CAN_F10R1_FB10_Pos) /*!< 0x00000400 */
3940 #define CAN_F10R1_FB10 CAN_F10R1_FB10_Msk /*!<Filter bit 10 */
3941 #define CAN_F10R1_FB11_Pos (11U)
3942 #define CAN_F10R1_FB11_Msk (0x1U << CAN_F10R1_FB11_Pos) /*!< 0x00000800 */
3943 #define CAN_F10R1_FB11 CAN_F10R1_FB11_Msk /*!<Filter bit 11 */
3944 #define CAN_F10R1_FB12_Pos (12U)
3945 #define CAN_F10R1_FB12_Msk (0x1U << CAN_F10R1_FB12_Pos) /*!< 0x00001000 */
3946 #define CAN_F10R1_FB12 CAN_F10R1_FB12_Msk /*!<Filter bit 12 */
3947 #define CAN_F10R1_FB13_Pos (13U)
3948 #define CAN_F10R1_FB13_Msk (0x1U << CAN_F10R1_FB13_Pos) /*!< 0x00002000 */
3949 #define CAN_F10R1_FB13 CAN_F10R1_FB13_Msk /*!<Filter bit 13 */
3950 #define CAN_F10R1_FB14_Pos (14U)
3951 #define CAN_F10R1_FB14_Msk (0x1U << CAN_F10R1_FB14_Pos) /*!< 0x00004000 */
3952 #define CAN_F10R1_FB14 CAN_F10R1_FB14_Msk /*!<Filter bit 14 */
3953 #define CAN_F10R1_FB15_Pos (15U)
3954 #define CAN_F10R1_FB15_Msk (0x1U << CAN_F10R1_FB15_Pos) /*!< 0x00008000 */
3955 #define CAN_F10R1_FB15 CAN_F10R1_FB15_Msk /*!<Filter bit 15 */
3956 #define CAN_F10R1_FB16_Pos (16U)
3957 #define CAN_F10R1_FB16_Msk (0x1U << CAN_F10R1_FB16_Pos) /*!< 0x00010000 */
3958 #define CAN_F10R1_FB16 CAN_F10R1_FB16_Msk /*!<Filter bit 16 */
3959 #define CAN_F10R1_FB17_Pos (17U)
3960 #define CAN_F10R1_FB17_Msk (0x1U << CAN_F10R1_FB17_Pos) /*!< 0x00020000 */
3961 #define CAN_F10R1_FB17 CAN_F10R1_FB17_Msk /*!<Filter bit 17 */
3962 #define CAN_F10R1_FB18_Pos (18U)
3963 #define CAN_F10R1_FB18_Msk (0x1U << CAN_F10R1_FB18_Pos) /*!< 0x00040000 */
3964 #define CAN_F10R1_FB18 CAN_F10R1_FB18_Msk /*!<Filter bit 18 */
3965 #define CAN_F10R1_FB19_Pos (19U)
3966 #define CAN_F10R1_FB19_Msk (0x1U << CAN_F10R1_FB19_Pos) /*!< 0x00080000 */
3967 #define CAN_F10R1_FB19 CAN_F10R1_FB19_Msk /*!<Filter bit 19 */
3968 #define CAN_F10R1_FB20_Pos (20U)
3969 #define CAN_F10R1_FB20_Msk (0x1U << CAN_F10R1_FB20_Pos) /*!< 0x00100000 */
3970 #define CAN_F10R1_FB20 CAN_F10R1_FB20_Msk /*!<Filter bit 20 */
3971 #define CAN_F10R1_FB21_Pos (21U)
3972 #define CAN_F10R1_FB21_Msk (0x1U << CAN_F10R1_FB21_Pos) /*!< 0x00200000 */
3973 #define CAN_F10R1_FB21 CAN_F10R1_FB21_Msk /*!<Filter bit 21 */
3974 #define CAN_F10R1_FB22_Pos (22U)
3975 #define CAN_F10R1_FB22_Msk (0x1U << CAN_F10R1_FB22_Pos) /*!< 0x00400000 */
3976 #define CAN_F10R1_FB22 CAN_F10R1_FB22_Msk /*!<Filter bit 22 */
3977 #define CAN_F10R1_FB23_Pos (23U)
3978 #define CAN_F10R1_FB23_Msk (0x1U << CAN_F10R1_FB23_Pos) /*!< 0x00800000 */
3979 #define CAN_F10R1_FB23 CAN_F10R1_FB23_Msk /*!<Filter bit 23 */
3980 #define CAN_F10R1_FB24_Pos (24U)
3981 #define CAN_F10R1_FB24_Msk (0x1U << CAN_F10R1_FB24_Pos) /*!< 0x01000000 */
3982 #define CAN_F10R1_FB24 CAN_F10R1_FB24_Msk /*!<Filter bit 24 */
3983 #define CAN_F10R1_FB25_Pos (25U)
3984 #define CAN_F10R1_FB25_Msk (0x1U << CAN_F10R1_FB25_Pos) /*!< 0x02000000 */
3985 #define CAN_F10R1_FB25 CAN_F10R1_FB25_Msk /*!<Filter bit 25 */
3986 #define CAN_F10R1_FB26_Pos (26U)
3987 #define CAN_F10R1_FB26_Msk (0x1U << CAN_F10R1_FB26_Pos) /*!< 0x04000000 */
3988 #define CAN_F10R1_FB26 CAN_F10R1_FB26_Msk /*!<Filter bit 26 */
3989 #define CAN_F10R1_FB27_Pos (27U)
3990 #define CAN_F10R1_FB27_Msk (0x1U << CAN_F10R1_FB27_Pos) /*!< 0x08000000 */
3991 #define CAN_F10R1_FB27 CAN_F10R1_FB27_Msk /*!<Filter bit 27 */
3992 #define CAN_F10R1_FB28_Pos (28U)
3993 #define CAN_F10R1_FB28_Msk (0x1U << CAN_F10R1_FB28_Pos) /*!< 0x10000000 */
3994 #define CAN_F10R1_FB28 CAN_F10R1_FB28_Msk /*!<Filter bit 28 */
3995 #define CAN_F10R1_FB29_Pos (29U)
3996 #define CAN_F10R1_FB29_Msk (0x1U << CAN_F10R1_FB29_Pos) /*!< 0x20000000 */
3997 #define CAN_F10R1_FB29 CAN_F10R1_FB29_Msk /*!<Filter bit 29 */
3998 #define CAN_F10R1_FB30_Pos (30U)
3999 #define CAN_F10R1_FB30_Msk (0x1U << CAN_F10R1_FB30_Pos) /*!< 0x40000000 */
4000 #define CAN_F10R1_FB30 CAN_F10R1_FB30_Msk /*!<Filter bit 30 */
4001 #define CAN_F10R1_FB31_Pos (31U)
4002 #define CAN_F10R1_FB31_Msk (0x1U << CAN_F10R1_FB31_Pos) /*!< 0x80000000 */
4003 #define CAN_F10R1_FB31 CAN_F10R1_FB31_Msk /*!<Filter bit 31 */
4004
4005 /******************* Bit definition for CAN_F11R1 register ******************/
4006 #define CAN_F11R1_FB0_Pos (0U)
4007 #define CAN_F11R1_FB0_Msk (0x1U << CAN_F11R1_FB0_Pos) /*!< 0x00000001 */
4008 #define CAN_F11R1_FB0 CAN_F11R1_FB0_Msk /*!<Filter bit 0 */
4009 #define CAN_F11R1_FB1_Pos (1U)
4010 #define CAN_F11R1_FB1_Msk (0x1U << CAN_F11R1_FB1_Pos) /*!< 0x00000002 */
4011 #define CAN_F11R1_FB1 CAN_F11R1_FB1_Msk /*!<Filter bit 1 */
4012 #define CAN_F11R1_FB2_Pos (2U)
4013 #define CAN_F11R1_FB2_Msk (0x1U << CAN_F11R1_FB2_Pos) /*!< 0x00000004 */
4014 #define CAN_F11R1_FB2 CAN_F11R1_FB2_Msk /*!<Filter bit 2 */
4015 #define CAN_F11R1_FB3_Pos (3U)
4016 #define CAN_F11R1_FB3_Msk (0x1U << CAN_F11R1_FB3_Pos) /*!< 0x00000008 */
4017 #define CAN_F11R1_FB3 CAN_F11R1_FB3_Msk /*!<Filter bit 3 */
4018 #define CAN_F11R1_FB4_Pos (4U)
4019 #define CAN_F11R1_FB4_Msk (0x1U << CAN_F11R1_FB4_Pos) /*!< 0x00000010 */
4020 #define CAN_F11R1_FB4 CAN_F11R1_FB4_Msk /*!<Filter bit 4 */
4021 #define CAN_F11R1_FB5_Pos (5U)
4022 #define CAN_F11R1_FB5_Msk (0x1U << CAN_F11R1_FB5_Pos) /*!< 0x00000020 */
4023 #define CAN_F11R1_FB5 CAN_F11R1_FB5_Msk /*!<Filter bit 5 */
4024 #define CAN_F11R1_FB6_Pos (6U)
4025 #define CAN_F11R1_FB6_Msk (0x1U << CAN_F11R1_FB6_Pos) /*!< 0x00000040 */
4026 #define CAN_F11R1_FB6 CAN_F11R1_FB6_Msk /*!<Filter bit 6 */
4027 #define CAN_F11R1_FB7_Pos (7U)
4028 #define CAN_F11R1_FB7_Msk (0x1U << CAN_F11R1_FB7_Pos) /*!< 0x00000080 */
4029 #define CAN_F11R1_FB7 CAN_F11R1_FB7_Msk /*!<Filter bit 7 */
4030 #define CAN_F11R1_FB8_Pos (8U)
4031 #define CAN_F11R1_FB8_Msk (0x1U << CAN_F11R1_FB8_Pos) /*!< 0x00000100 */
4032 #define CAN_F11R1_FB8 CAN_F11R1_FB8_Msk /*!<Filter bit 8 */
4033 #define CAN_F11R1_FB9_Pos (9U)
4034 #define CAN_F11R1_FB9_Msk (0x1U << CAN_F11R1_FB9_Pos) /*!< 0x00000200 */
4035 #define CAN_F11R1_FB9 CAN_F11R1_FB9_Msk /*!<Filter bit 9 */
4036 #define CAN_F11R1_FB10_Pos (10U)
4037 #define CAN_F11R1_FB10_Msk (0x1U << CAN_F11R1_FB10_Pos) /*!< 0x00000400 */
4038 #define CAN_F11R1_FB10 CAN_F11R1_FB10_Msk /*!<Filter bit 10 */
4039 #define CAN_F11R1_FB11_Pos (11U)
4040 #define CAN_F11R1_FB11_Msk (0x1U << CAN_F11R1_FB11_Pos) /*!< 0x00000800 */
4041 #define CAN_F11R1_FB11 CAN_F11R1_FB11_Msk /*!<Filter bit 11 */
4042 #define CAN_F11R1_FB12_Pos (12U)
4043 #define CAN_F11R1_FB12_Msk (0x1U << CAN_F11R1_FB12_Pos) /*!< 0x00001000 */
4044 #define CAN_F11R1_FB12 CAN_F11R1_FB12_Msk /*!<Filter bit 12 */
4045 #define CAN_F11R1_FB13_Pos (13U)
4046 #define CAN_F11R1_FB13_Msk (0x1U << CAN_F11R1_FB13_Pos) /*!< 0x00002000 */
4047 #define CAN_F11R1_FB13 CAN_F11R1_FB13_Msk /*!<Filter bit 13 */
4048 #define CAN_F11R1_FB14_Pos (14U)
4049 #define CAN_F11R1_FB14_Msk (0x1U << CAN_F11R1_FB14_Pos) /*!< 0x00004000 */
4050 #define CAN_F11R1_FB14 CAN_F11R1_FB14_Msk /*!<Filter bit 14 */
4051 #define CAN_F11R1_FB15_Pos (15U)
4052 #define CAN_F11R1_FB15_Msk (0x1U << CAN_F11R1_FB15_Pos) /*!< 0x00008000 */
4053 #define CAN_F11R1_FB15 CAN_F11R1_FB15_Msk /*!<Filter bit 15 */
4054 #define CAN_F11R1_FB16_Pos (16U)
4055 #define CAN_F11R1_FB16_Msk (0x1U << CAN_F11R1_FB16_Pos) /*!< 0x00010000 */
4056 #define CAN_F11R1_FB16 CAN_F11R1_FB16_Msk /*!<Filter bit 16 */
4057 #define CAN_F11R1_FB17_Pos (17U)
4058 #define CAN_F11R1_FB17_Msk (0x1U << CAN_F11R1_FB17_Pos) /*!< 0x00020000 */
4059 #define CAN_F11R1_FB17 CAN_F11R1_FB17_Msk /*!<Filter bit 17 */
4060 #define CAN_F11R1_FB18_Pos (18U)
4061 #define CAN_F11R1_FB18_Msk (0x1U << CAN_F11R1_FB18_Pos) /*!< 0x00040000 */
4062 #define CAN_F11R1_FB18 CAN_F11R1_FB18_Msk /*!<Filter bit 18 */
4063 #define CAN_F11R1_FB19_Pos (19U)
4064 #define CAN_F11R1_FB19_Msk (0x1U << CAN_F11R1_FB19_Pos) /*!< 0x00080000 */
4065 #define CAN_F11R1_FB19 CAN_F11R1_FB19_Msk /*!<Filter bit 19 */
4066 #define CAN_F11R1_FB20_Pos (20U)
4067 #define CAN_F11R1_FB20_Msk (0x1U << CAN_F11R1_FB20_Pos) /*!< 0x00100000 */
4068 #define CAN_F11R1_FB20 CAN_F11R1_FB20_Msk /*!<Filter bit 20 */
4069 #define CAN_F11R1_FB21_Pos (21U)
4070 #define CAN_F11R1_FB21_Msk (0x1U << CAN_F11R1_FB21_Pos) /*!< 0x00200000 */
4071 #define CAN_F11R1_FB21 CAN_F11R1_FB21_Msk /*!<Filter bit 21 */
4072 #define CAN_F11R1_FB22_Pos (22U)
4073 #define CAN_F11R1_FB22_Msk (0x1U << CAN_F11R1_FB22_Pos) /*!< 0x00400000 */
4074 #define CAN_F11R1_FB22 CAN_F11R1_FB22_Msk /*!<Filter bit 22 */
4075 #define CAN_F11R1_FB23_Pos (23U)
4076 #define CAN_F11R1_FB23_Msk (0x1U << CAN_F11R1_FB23_Pos) /*!< 0x00800000 */
4077 #define CAN_F11R1_FB23 CAN_F11R1_FB23_Msk /*!<Filter bit 23 */
4078 #define CAN_F11R1_FB24_Pos (24U)
4079 #define CAN_F11R1_FB24_Msk (0x1U << CAN_F11R1_FB24_Pos) /*!< 0x01000000 */
4080 #define CAN_F11R1_FB24 CAN_F11R1_FB24_Msk /*!<Filter bit 24 */
4081 #define CAN_F11R1_FB25_Pos (25U)
4082 #define CAN_F11R1_FB25_Msk (0x1U << CAN_F11R1_FB25_Pos) /*!< 0x02000000 */
4083 #define CAN_F11R1_FB25 CAN_F11R1_FB25_Msk /*!<Filter bit 25 */
4084 #define CAN_F11R1_FB26_Pos (26U)
4085 #define CAN_F11R1_FB26_Msk (0x1U << CAN_F11R1_FB26_Pos) /*!< 0x04000000 */
4086 #define CAN_F11R1_FB26 CAN_F11R1_FB26_Msk /*!<Filter bit 26 */
4087 #define CAN_F11R1_FB27_Pos (27U)
4088 #define CAN_F11R1_FB27_Msk (0x1U << CAN_F11R1_FB27_Pos) /*!< 0x08000000 */
4089 #define CAN_F11R1_FB27 CAN_F11R1_FB27_Msk /*!<Filter bit 27 */
4090 #define CAN_F11R1_FB28_Pos (28U)
4091 #define CAN_F11R1_FB28_Msk (0x1U << CAN_F11R1_FB28_Pos) /*!< 0x10000000 */
4092 #define CAN_F11R1_FB28 CAN_F11R1_FB28_Msk /*!<Filter bit 28 */
4093 #define CAN_F11R1_FB29_Pos (29U)
4094 #define CAN_F11R1_FB29_Msk (0x1U << CAN_F11R1_FB29_Pos) /*!< 0x20000000 */
4095 #define CAN_F11R1_FB29 CAN_F11R1_FB29_Msk /*!<Filter bit 29 */
4096 #define CAN_F11R1_FB30_Pos (30U)
4097 #define CAN_F11R1_FB30_Msk (0x1U << CAN_F11R1_FB30_Pos) /*!< 0x40000000 */
4098 #define CAN_F11R1_FB30 CAN_F11R1_FB30_Msk /*!<Filter bit 30 */
4099 #define CAN_F11R1_FB31_Pos (31U)
4100 #define CAN_F11R1_FB31_Msk (0x1U << CAN_F11R1_FB31_Pos) /*!< 0x80000000 */
4101 #define CAN_F11R1_FB31 CAN_F11R1_FB31_Msk /*!<Filter bit 31 */
4102
4103 /******************* Bit definition for CAN_F12R1 register ******************/
4104 #define CAN_F12R1_FB0_Pos (0U)
4105 #define CAN_F12R1_FB0_Msk (0x1U << CAN_F12R1_FB0_Pos) /*!< 0x00000001 */
4106 #define CAN_F12R1_FB0 CAN_F12R1_FB0_Msk /*!<Filter bit 0 */
4107 #define CAN_F12R1_FB1_Pos (1U)
4108 #define CAN_F12R1_FB1_Msk (0x1U << CAN_F12R1_FB1_Pos) /*!< 0x00000002 */
4109 #define CAN_F12R1_FB1 CAN_F12R1_FB1_Msk /*!<Filter bit 1 */
4110 #define CAN_F12R1_FB2_Pos (2U)
4111 #define CAN_F12R1_FB2_Msk (0x1U << CAN_F12R1_FB2_Pos) /*!< 0x00000004 */
4112 #define CAN_F12R1_FB2 CAN_F12R1_FB2_Msk /*!<Filter bit 2 */
4113 #define CAN_F12R1_FB3_Pos (3U)
4114 #define CAN_F12R1_FB3_Msk (0x1U << CAN_F12R1_FB3_Pos) /*!< 0x00000008 */
4115 #define CAN_F12R1_FB3 CAN_F12R1_FB3_Msk /*!<Filter bit 3 */
4116 #define CAN_F12R1_FB4_Pos (4U)
4117 #define CAN_F12R1_FB4_Msk (0x1U << CAN_F12R1_FB4_Pos) /*!< 0x00000010 */
4118 #define CAN_F12R1_FB4 CAN_F12R1_FB4_Msk /*!<Filter bit 4 */
4119 #define CAN_F12R1_FB5_Pos (5U)
4120 #define CAN_F12R1_FB5_Msk (0x1U << CAN_F12R1_FB5_Pos) /*!< 0x00000020 */
4121 #define CAN_F12R1_FB5 CAN_F12R1_FB5_Msk /*!<Filter bit 5 */
4122 #define CAN_F12R1_FB6_Pos (6U)
4123 #define CAN_F12R1_FB6_Msk (0x1U << CAN_F12R1_FB6_Pos) /*!< 0x00000040 */
4124 #define CAN_F12R1_FB6 CAN_F12R1_FB6_Msk /*!<Filter bit 6 */
4125 #define CAN_F12R1_FB7_Pos (7U)
4126 #define CAN_F12R1_FB7_Msk (0x1U << CAN_F12R1_FB7_Pos) /*!< 0x00000080 */
4127 #define CAN_F12R1_FB7 CAN_F12R1_FB7_Msk /*!<Filter bit 7 */
4128 #define CAN_F12R1_FB8_Pos (8U)
4129 #define CAN_F12R1_FB8_Msk (0x1U << CAN_F12R1_FB8_Pos) /*!< 0x00000100 */
4130 #define CAN_F12R1_FB8 CAN_F12R1_FB8_Msk /*!<Filter bit 8 */
4131 #define CAN_F12R1_FB9_Pos (9U)
4132 #define CAN_F12R1_FB9_Msk (0x1U << CAN_F12R1_FB9_Pos) /*!< 0x00000200 */
4133 #define CAN_F12R1_FB9 CAN_F12R1_FB9_Msk /*!<Filter bit 9 */
4134 #define CAN_F12R1_FB10_Pos (10U)
4135 #define CAN_F12R1_FB10_Msk (0x1U << CAN_F12R1_FB10_Pos) /*!< 0x00000400 */
4136 #define CAN_F12R1_FB10 CAN_F12R1_FB10_Msk /*!<Filter bit 10 */
4137 #define CAN_F12R1_FB11_Pos (11U)
4138 #define CAN_F12R1_FB11_Msk (0x1U << CAN_F12R1_FB11_Pos) /*!< 0x00000800 */
4139 #define CAN_F12R1_FB11 CAN_F12R1_FB11_Msk /*!<Filter bit 11 */
4140 #define CAN_F12R1_FB12_Pos (12U)
4141 #define CAN_F12R1_FB12_Msk (0x1U << CAN_F12R1_FB12_Pos) /*!< 0x00001000 */
4142 #define CAN_F12R1_FB12 CAN_F12R1_FB12_Msk /*!<Filter bit 12 */
4143 #define CAN_F12R1_FB13_Pos (13U)
4144 #define CAN_F12R1_FB13_Msk (0x1U << CAN_F12R1_FB13_Pos) /*!< 0x00002000 */
4145 #define CAN_F12R1_FB13 CAN_F12R1_FB13_Msk /*!<Filter bit 13 */
4146 #define CAN_F12R1_FB14_Pos (14U)
4147 #define CAN_F12R1_FB14_Msk (0x1U << CAN_F12R1_FB14_Pos) /*!< 0x00004000 */
4148 #define CAN_F12R1_FB14 CAN_F12R1_FB14_Msk /*!<Filter bit 14 */
4149 #define CAN_F12R1_FB15_Pos (15U)
4150 #define CAN_F12R1_FB15_Msk (0x1U << CAN_F12R1_FB15_Pos) /*!< 0x00008000 */
4151 #define CAN_F12R1_FB15 CAN_F12R1_FB15_Msk /*!<Filter bit 15 */
4152 #define CAN_F12R1_FB16_Pos (16U)
4153 #define CAN_F12R1_FB16_Msk (0x1U << CAN_F12R1_FB16_Pos) /*!< 0x00010000 */
4154 #define CAN_F12R1_FB16 CAN_F12R1_FB16_Msk /*!<Filter bit 16 */
4155 #define CAN_F12R1_FB17_Pos (17U)
4156 #define CAN_F12R1_FB17_Msk (0x1U << CAN_F12R1_FB17_Pos) /*!< 0x00020000 */
4157 #define CAN_F12R1_FB17 CAN_F12R1_FB17_Msk /*!<Filter bit 17 */
4158 #define CAN_F12R1_FB18_Pos (18U)
4159 #define CAN_F12R1_FB18_Msk (0x1U << CAN_F12R1_FB18_Pos) /*!< 0x00040000 */
4160 #define CAN_F12R1_FB18 CAN_F12R1_FB18_Msk /*!<Filter bit 18 */
4161 #define CAN_F12R1_FB19_Pos (19U)
4162 #define CAN_F12R1_FB19_Msk (0x1U << CAN_F12R1_FB19_Pos) /*!< 0x00080000 */
4163 #define CAN_F12R1_FB19 CAN_F12R1_FB19_Msk /*!<Filter bit 19 */
4164 #define CAN_F12R1_FB20_Pos (20U)
4165 #define CAN_F12R1_FB20_Msk (0x1U << CAN_F12R1_FB20_Pos) /*!< 0x00100000 */
4166 #define CAN_F12R1_FB20 CAN_F12R1_FB20_Msk /*!<Filter bit 20 */
4167 #define CAN_F12R1_FB21_Pos (21U)
4168 #define CAN_F12R1_FB21_Msk (0x1U << CAN_F12R1_FB21_Pos) /*!< 0x00200000 */
4169 #define CAN_F12R1_FB21 CAN_F12R1_FB21_Msk /*!<Filter bit 21 */
4170 #define CAN_F12R1_FB22_Pos (22U)
4171 #define CAN_F12R1_FB22_Msk (0x1U << CAN_F12R1_FB22_Pos) /*!< 0x00400000 */
4172 #define CAN_F12R1_FB22 CAN_F12R1_FB22_Msk /*!<Filter bit 22 */
4173 #define CAN_F12R1_FB23_Pos (23U)
4174 #define CAN_F12R1_FB23_Msk (0x1U << CAN_F12R1_FB23_Pos) /*!< 0x00800000 */
4175 #define CAN_F12R1_FB23 CAN_F12R1_FB23_Msk /*!<Filter bit 23 */
4176 #define CAN_F12R1_FB24_Pos (24U)
4177 #define CAN_F12R1_FB24_Msk (0x1U << CAN_F12R1_FB24_Pos) /*!< 0x01000000 */
4178 #define CAN_F12R1_FB24 CAN_F12R1_FB24_Msk /*!<Filter bit 24 */
4179 #define CAN_F12R1_FB25_Pos (25U)
4180 #define CAN_F12R1_FB25_Msk (0x1U << CAN_F12R1_FB25_Pos) /*!< 0x02000000 */
4181 #define CAN_F12R1_FB25 CAN_F12R1_FB25_Msk /*!<Filter bit 25 */
4182 #define CAN_F12R1_FB26_Pos (26U)
4183 #define CAN_F12R1_FB26_Msk (0x1U << CAN_F12R1_FB26_Pos) /*!< 0x04000000 */
4184 #define CAN_F12R1_FB26 CAN_F12R1_FB26_Msk /*!<Filter bit 26 */
4185 #define CAN_F12R1_FB27_Pos (27U)
4186 #define CAN_F12R1_FB27_Msk (0x1U << CAN_F12R1_FB27_Pos) /*!< 0x08000000 */
4187 #define CAN_F12R1_FB27 CAN_F12R1_FB27_Msk /*!<Filter bit 27 */
4188 #define CAN_F12R1_FB28_Pos (28U)
4189 #define CAN_F12R1_FB28_Msk (0x1U << CAN_F12R1_FB28_Pos) /*!< 0x10000000 */
4190 #define CAN_F12R1_FB28 CAN_F12R1_FB28_Msk /*!<Filter bit 28 */
4191 #define CAN_F12R1_FB29_Pos (29U)
4192 #define CAN_F12R1_FB29_Msk (0x1U << CAN_F12R1_FB29_Pos) /*!< 0x20000000 */
4193 #define CAN_F12R1_FB29 CAN_F12R1_FB29_Msk /*!<Filter bit 29 */
4194 #define CAN_F12R1_FB30_Pos (30U)
4195 #define CAN_F12R1_FB30_Msk (0x1U << CAN_F12R1_FB30_Pos) /*!< 0x40000000 */
4196 #define CAN_F12R1_FB30 CAN_F12R1_FB30_Msk /*!<Filter bit 30 */
4197 #define CAN_F12R1_FB31_Pos (31U)
4198 #define CAN_F12R1_FB31_Msk (0x1U << CAN_F12R1_FB31_Pos) /*!< 0x80000000 */
4199 #define CAN_F12R1_FB31 CAN_F12R1_FB31_Msk /*!<Filter bit 31 */
4200
4201 /******************* Bit definition for CAN_F13R1 register ******************/
4202 #define CAN_F13R1_FB0_Pos (0U)
4203 #define CAN_F13R1_FB0_Msk (0x1U << CAN_F13R1_FB0_Pos) /*!< 0x00000001 */
4204 #define CAN_F13R1_FB0 CAN_F13R1_FB0_Msk /*!<Filter bit 0 */
4205 #define CAN_F13R1_FB1_Pos (1U)
4206 #define CAN_F13R1_FB1_Msk (0x1U << CAN_F13R1_FB1_Pos) /*!< 0x00000002 */
4207 #define CAN_F13R1_FB1 CAN_F13R1_FB1_Msk /*!<Filter bit 1 */
4208 #define CAN_F13R1_FB2_Pos (2U)
4209 #define CAN_F13R1_FB2_Msk (0x1U << CAN_F13R1_FB2_Pos) /*!< 0x00000004 */
4210 #define CAN_F13R1_FB2 CAN_F13R1_FB2_Msk /*!<Filter bit 2 */
4211 #define CAN_F13R1_FB3_Pos (3U)
4212 #define CAN_F13R1_FB3_Msk (0x1U << CAN_F13R1_FB3_Pos) /*!< 0x00000008 */
4213 #define CAN_F13R1_FB3 CAN_F13R1_FB3_Msk /*!<Filter bit 3 */
4214 #define CAN_F13R1_FB4_Pos (4U)
4215 #define CAN_F13R1_FB4_Msk (0x1U << CAN_F13R1_FB4_Pos) /*!< 0x00000010 */
4216 #define CAN_F13R1_FB4 CAN_F13R1_FB4_Msk /*!<Filter bit 4 */
4217 #define CAN_F13R1_FB5_Pos (5U)
4218 #define CAN_F13R1_FB5_Msk (0x1U << CAN_F13R1_FB5_Pos) /*!< 0x00000020 */
4219 #define CAN_F13R1_FB5 CAN_F13R1_FB5_Msk /*!<Filter bit 5 */
4220 #define CAN_F13R1_FB6_Pos (6U)
4221 #define CAN_F13R1_FB6_Msk (0x1U << CAN_F13R1_FB6_Pos) /*!< 0x00000040 */
4222 #define CAN_F13R1_FB6 CAN_F13R1_FB6_Msk /*!<Filter bit 6 */
4223 #define CAN_F13R1_FB7_Pos (7U)
4224 #define CAN_F13R1_FB7_Msk (0x1U << CAN_F13R1_FB7_Pos) /*!< 0x00000080 */
4225 #define CAN_F13R1_FB7 CAN_F13R1_FB7_Msk /*!<Filter bit 7 */
4226 #define CAN_F13R1_FB8_Pos (8U)
4227 #define CAN_F13R1_FB8_Msk (0x1U << CAN_F13R1_FB8_Pos) /*!< 0x00000100 */
4228 #define CAN_F13R1_FB8 CAN_F13R1_FB8_Msk /*!<Filter bit 8 */
4229 #define CAN_F13R1_FB9_Pos (9U)
4230 #define CAN_F13R1_FB9_Msk (0x1U << CAN_F13R1_FB9_Pos) /*!< 0x00000200 */
4231 #define CAN_F13R1_FB9 CAN_F13R1_FB9_Msk /*!<Filter bit 9 */
4232 #define CAN_F13R1_FB10_Pos (10U)
4233 #define CAN_F13R1_FB10_Msk (0x1U << CAN_F13R1_FB10_Pos) /*!< 0x00000400 */
4234 #define CAN_F13R1_FB10 CAN_F13R1_FB10_Msk /*!<Filter bit 10 */
4235 #define CAN_F13R1_FB11_Pos (11U)
4236 #define CAN_F13R1_FB11_Msk (0x1U << CAN_F13R1_FB11_Pos) /*!< 0x00000800 */
4237 #define CAN_F13R1_FB11 CAN_F13R1_FB11_Msk /*!<Filter bit 11 */
4238 #define CAN_F13R1_FB12_Pos (12U)
4239 #define CAN_F13R1_FB12_Msk (0x1U << CAN_F13R1_FB12_Pos) /*!< 0x00001000 */
4240 #define CAN_F13R1_FB12 CAN_F13R1_FB12_Msk /*!<Filter bit 12 */
4241 #define CAN_F13R1_FB13_Pos (13U)
4242 #define CAN_F13R1_FB13_Msk (0x1U << CAN_F13R1_FB13_Pos) /*!< 0x00002000 */
4243 #define CAN_F13R1_FB13 CAN_F13R1_FB13_Msk /*!<Filter bit 13 */
4244 #define CAN_F13R1_FB14_Pos (14U)
4245 #define CAN_F13R1_FB14_Msk (0x1U << CAN_F13R1_FB14_Pos) /*!< 0x00004000 */
4246 #define CAN_F13R1_FB14 CAN_F13R1_FB14_Msk /*!<Filter bit 14 */
4247 #define CAN_F13R1_FB15_Pos (15U)
4248 #define CAN_F13R1_FB15_Msk (0x1U << CAN_F13R1_FB15_Pos) /*!< 0x00008000 */
4249 #define CAN_F13R1_FB15 CAN_F13R1_FB15_Msk /*!<Filter bit 15 */
4250 #define CAN_F13R1_FB16_Pos (16U)
4251 #define CAN_F13R1_FB16_Msk (0x1U << CAN_F13R1_FB16_Pos) /*!< 0x00010000 */
4252 #define CAN_F13R1_FB16 CAN_F13R1_FB16_Msk /*!<Filter bit 16 */
4253 #define CAN_F13R1_FB17_Pos (17U)
4254 #define CAN_F13R1_FB17_Msk (0x1U << CAN_F13R1_FB17_Pos) /*!< 0x00020000 */
4255 #define CAN_F13R1_FB17 CAN_F13R1_FB17_Msk /*!<Filter bit 17 */
4256 #define CAN_F13R1_FB18_Pos (18U)
4257 #define CAN_F13R1_FB18_Msk (0x1U << CAN_F13R1_FB18_Pos) /*!< 0x00040000 */
4258 #define CAN_F13R1_FB18 CAN_F13R1_FB18_Msk /*!<Filter bit 18 */
4259 #define CAN_F13R1_FB19_Pos (19U)
4260 #define CAN_F13R1_FB19_Msk (0x1U << CAN_F13R1_FB19_Pos) /*!< 0x00080000 */
4261 #define CAN_F13R1_FB19 CAN_F13R1_FB19_Msk /*!<Filter bit 19 */
4262 #define CAN_F13R1_FB20_Pos (20U)
4263 #define CAN_F13R1_FB20_Msk (0x1U << CAN_F13R1_FB20_Pos) /*!< 0x00100000 */
4264 #define CAN_F13R1_FB20 CAN_F13R1_FB20_Msk /*!<Filter bit 20 */
4265 #define CAN_F13R1_FB21_Pos (21U)
4266 #define CAN_F13R1_FB21_Msk (0x1U << CAN_F13R1_FB21_Pos) /*!< 0x00200000 */
4267 #define CAN_F13R1_FB21 CAN_F13R1_FB21_Msk /*!<Filter bit 21 */
4268 #define CAN_F13R1_FB22_Pos (22U)
4269 #define CAN_F13R1_FB22_Msk (0x1U << CAN_F13R1_FB22_Pos) /*!< 0x00400000 */
4270 #define CAN_F13R1_FB22 CAN_F13R1_FB22_Msk /*!<Filter bit 22 */
4271 #define CAN_F13R1_FB23_Pos (23U)
4272 #define CAN_F13R1_FB23_Msk (0x1U << CAN_F13R1_FB23_Pos) /*!< 0x00800000 */
4273 #define CAN_F13R1_FB23 CAN_F13R1_FB23_Msk /*!<Filter bit 23 */
4274 #define CAN_F13R1_FB24_Pos (24U)
4275 #define CAN_F13R1_FB24_Msk (0x1U << CAN_F13R1_FB24_Pos) /*!< 0x01000000 */
4276 #define CAN_F13R1_FB24 CAN_F13R1_FB24_Msk /*!<Filter bit 24 */
4277 #define CAN_F13R1_FB25_Pos (25U)
4278 #define CAN_F13R1_FB25_Msk (0x1U << CAN_F13R1_FB25_Pos) /*!< 0x02000000 */
4279 #define CAN_F13R1_FB25 CAN_F13R1_FB25_Msk /*!<Filter bit 25 */
4280 #define CAN_F13R1_FB26_Pos (26U)
4281 #define CAN_F13R1_FB26_Msk (0x1U << CAN_F13R1_FB26_Pos) /*!< 0x04000000 */
4282 #define CAN_F13R1_FB26 CAN_F13R1_FB26_Msk /*!<Filter bit 26 */
4283 #define CAN_F13R1_FB27_Pos (27U)
4284 #define CAN_F13R1_FB27_Msk (0x1U << CAN_F13R1_FB27_Pos) /*!< 0x08000000 */
4285 #define CAN_F13R1_FB27 CAN_F13R1_FB27_Msk /*!<Filter bit 27 */
4286 #define CAN_F13R1_FB28_Pos (28U)
4287 #define CAN_F13R1_FB28_Msk (0x1U << CAN_F13R1_FB28_Pos) /*!< 0x10000000 */
4288 #define CAN_F13R1_FB28 CAN_F13R1_FB28_Msk /*!<Filter bit 28 */
4289 #define CAN_F13R1_FB29_Pos (29U)
4290 #define CAN_F13R1_FB29_Msk (0x1U << CAN_F13R1_FB29_Pos) /*!< 0x20000000 */
4291 #define CAN_F13R1_FB29 CAN_F13R1_FB29_Msk /*!<Filter bit 29 */
4292 #define CAN_F13R1_FB30_Pos (30U)
4293 #define CAN_F13R1_FB30_Msk (0x1U << CAN_F13R1_FB30_Pos) /*!< 0x40000000 */
4294 #define CAN_F13R1_FB30 CAN_F13R1_FB30_Msk /*!<Filter bit 30 */
4295 #define CAN_F13R1_FB31_Pos (31U)
4296 #define CAN_F13R1_FB31_Msk (0x1U << CAN_F13R1_FB31_Pos) /*!< 0x80000000 */
4297 #define CAN_F13R1_FB31 CAN_F13R1_FB31_Msk /*!<Filter bit 31 */
4298
4299 /******************* Bit definition for CAN_F0R2 register *******************/
4300 #define CAN_F0R2_FB0_Pos (0U)
4301 #define CAN_F0R2_FB0_Msk (0x1U << CAN_F0R2_FB0_Pos) /*!< 0x00000001 */
4302 #define CAN_F0R2_FB0 CAN_F0R2_FB0_Msk /*!<Filter bit 0 */
4303 #define CAN_F0R2_FB1_Pos (1U)
4304 #define CAN_F0R2_FB1_Msk (0x1U << CAN_F0R2_FB1_Pos) /*!< 0x00000002 */
4305 #define CAN_F0R2_FB1 CAN_F0R2_FB1_Msk /*!<Filter bit 1 */
4306 #define CAN_F0R2_FB2_Pos (2U)
4307 #define CAN_F0R2_FB2_Msk (0x1U << CAN_F0R2_FB2_Pos) /*!< 0x00000004 */
4308 #define CAN_F0R2_FB2 CAN_F0R2_FB2_Msk /*!<Filter bit 2 */
4309 #define CAN_F0R2_FB3_Pos (3U)
4310 #define CAN_F0R2_FB3_Msk (0x1U << CAN_F0R2_FB3_Pos) /*!< 0x00000008 */
4311 #define CAN_F0R2_FB3 CAN_F0R2_FB3_Msk /*!<Filter bit 3 */
4312 #define CAN_F0R2_FB4_Pos (4U)
4313 #define CAN_F0R2_FB4_Msk (0x1U << CAN_F0R2_FB4_Pos) /*!< 0x00000010 */
4314 #define CAN_F0R2_FB4 CAN_F0R2_FB4_Msk /*!<Filter bit 4 */
4315 #define CAN_F0R2_FB5_Pos (5U)
4316 #define CAN_F0R2_FB5_Msk (0x1U << CAN_F0R2_FB5_Pos) /*!< 0x00000020 */
4317 #define CAN_F0R2_FB5 CAN_F0R2_FB5_Msk /*!<Filter bit 5 */
4318 #define CAN_F0R2_FB6_Pos (6U)
4319 #define CAN_F0R2_FB6_Msk (0x1U << CAN_F0R2_FB6_Pos) /*!< 0x00000040 */
4320 #define CAN_F0R2_FB6 CAN_F0R2_FB6_Msk /*!<Filter bit 6 */
4321 #define CAN_F0R2_FB7_Pos (7U)
4322 #define CAN_F0R2_FB7_Msk (0x1U << CAN_F0R2_FB7_Pos) /*!< 0x00000080 */
4323 #define CAN_F0R2_FB7 CAN_F0R2_FB7_Msk /*!<Filter bit 7 */
4324 #define CAN_F0R2_FB8_Pos (8U)
4325 #define CAN_F0R2_FB8_Msk (0x1U << CAN_F0R2_FB8_Pos) /*!< 0x00000100 */
4326 #define CAN_F0R2_FB8 CAN_F0R2_FB8_Msk /*!<Filter bit 8 */
4327 #define CAN_F0R2_FB9_Pos (9U)
4328 #define CAN_F0R2_FB9_Msk (0x1U << CAN_F0R2_FB9_Pos) /*!< 0x00000200 */
4329 #define CAN_F0R2_FB9 CAN_F0R2_FB9_Msk /*!<Filter bit 9 */
4330 #define CAN_F0R2_FB10_Pos (10U)
4331 #define CAN_F0R2_FB10_Msk (0x1U << CAN_F0R2_FB10_Pos) /*!< 0x00000400 */
4332 #define CAN_F0R2_FB10 CAN_F0R2_FB10_Msk /*!<Filter bit 10 */
4333 #define CAN_F0R2_FB11_Pos (11U)
4334 #define CAN_F0R2_FB11_Msk (0x1U << CAN_F0R2_FB11_Pos) /*!< 0x00000800 */
4335 #define CAN_F0R2_FB11 CAN_F0R2_FB11_Msk /*!<Filter bit 11 */
4336 #define CAN_F0R2_FB12_Pos (12U)
4337 #define CAN_F0R2_FB12_Msk (0x1U << CAN_F0R2_FB12_Pos) /*!< 0x00001000 */
4338 #define CAN_F0R2_FB12 CAN_F0R2_FB12_Msk /*!<Filter bit 12 */
4339 #define CAN_F0R2_FB13_Pos (13U)
4340 #define CAN_F0R2_FB13_Msk (0x1U << CAN_F0R2_FB13_Pos) /*!< 0x00002000 */
4341 #define CAN_F0R2_FB13 CAN_F0R2_FB13_Msk /*!<Filter bit 13 */
4342 #define CAN_F0R2_FB14_Pos (14U)
4343 #define CAN_F0R2_FB14_Msk (0x1U << CAN_F0R2_FB14_Pos) /*!< 0x00004000 */
4344 #define CAN_F0R2_FB14 CAN_F0R2_FB14_Msk /*!<Filter bit 14 */
4345 #define CAN_F0R2_FB15_Pos (15U)
4346 #define CAN_F0R2_FB15_Msk (0x1U << CAN_F0R2_FB15_Pos) /*!< 0x00008000 */
4347 #define CAN_F0R2_FB15 CAN_F0R2_FB15_Msk /*!<Filter bit 15 */
4348 #define CAN_F0R2_FB16_Pos (16U)
4349 #define CAN_F0R2_FB16_Msk (0x1U << CAN_F0R2_FB16_Pos) /*!< 0x00010000 */
4350 #define CAN_F0R2_FB16 CAN_F0R2_FB16_Msk /*!<Filter bit 16 */
4351 #define CAN_F0R2_FB17_Pos (17U)
4352 #define CAN_F0R2_FB17_Msk (0x1U << CAN_F0R2_FB17_Pos) /*!< 0x00020000 */
4353 #define CAN_F0R2_FB17 CAN_F0R2_FB17_Msk /*!<Filter bit 17 */
4354 #define CAN_F0R2_FB18_Pos (18U)
4355 #define CAN_F0R2_FB18_Msk (0x1U << CAN_F0R2_FB18_Pos) /*!< 0x00040000 */
4356 #define CAN_F0R2_FB18 CAN_F0R2_FB18_Msk /*!<Filter bit 18 */
4357 #define CAN_F0R2_FB19_Pos (19U)
4358 #define CAN_F0R2_FB19_Msk (0x1U << CAN_F0R2_FB19_Pos) /*!< 0x00080000 */
4359 #define CAN_F0R2_FB19 CAN_F0R2_FB19_Msk /*!<Filter bit 19 */
4360 #define CAN_F0R2_FB20_Pos (20U)
4361 #define CAN_F0R2_FB20_Msk (0x1U << CAN_F0R2_FB20_Pos) /*!< 0x00100000 */
4362 #define CAN_F0R2_FB20 CAN_F0R2_FB20_Msk /*!<Filter bit 20 */
4363 #define CAN_F0R2_FB21_Pos (21U)
4364 #define CAN_F0R2_FB21_Msk (0x1U << CAN_F0R2_FB21_Pos) /*!< 0x00200000 */
4365 #define CAN_F0R2_FB21 CAN_F0R2_FB21_Msk /*!<Filter bit 21 */
4366 #define CAN_F0R2_FB22_Pos (22U)
4367 #define CAN_F0R2_FB22_Msk (0x1U << CAN_F0R2_FB22_Pos) /*!< 0x00400000 */
4368 #define CAN_F0R2_FB22 CAN_F0R2_FB22_Msk /*!<Filter bit 22 */
4369 #define CAN_F0R2_FB23_Pos (23U)
4370 #define CAN_F0R2_FB23_Msk (0x1U << CAN_F0R2_FB23_Pos) /*!< 0x00800000 */
4371 #define CAN_F0R2_FB23 CAN_F0R2_FB23_Msk /*!<Filter bit 23 */
4372 #define CAN_F0R2_FB24_Pos (24U)
4373 #define CAN_F0R2_FB24_Msk (0x1U << CAN_F0R2_FB24_Pos) /*!< 0x01000000 */
4374 #define CAN_F0R2_FB24 CAN_F0R2_FB24_Msk /*!<Filter bit 24 */
4375 #define CAN_F0R2_FB25_Pos (25U)
4376 #define CAN_F0R2_FB25_Msk (0x1U << CAN_F0R2_FB25_Pos) /*!< 0x02000000 */
4377 #define CAN_F0R2_FB25 CAN_F0R2_FB25_Msk /*!<Filter bit 25 */
4378 #define CAN_F0R2_FB26_Pos (26U)
4379 #define CAN_F0R2_FB26_Msk (0x1U << CAN_F0R2_FB26_Pos) /*!< 0x04000000 */
4380 #define CAN_F0R2_FB26 CAN_F0R2_FB26_Msk /*!<Filter bit 26 */
4381 #define CAN_F0R2_FB27_Pos (27U)
4382 #define CAN_F0R2_FB27_Msk (0x1U << CAN_F0R2_FB27_Pos) /*!< 0x08000000 */
4383 #define CAN_F0R2_FB27 CAN_F0R2_FB27_Msk /*!<Filter bit 27 */
4384 #define CAN_F0R2_FB28_Pos (28U)
4385 #define CAN_F0R2_FB28_Msk (0x1U << CAN_F0R2_FB28_Pos) /*!< 0x10000000 */
4386 #define CAN_F0R2_FB28 CAN_F0R2_FB28_Msk /*!<Filter bit 28 */
4387 #define CAN_F0R2_FB29_Pos (29U)
4388 #define CAN_F0R2_FB29_Msk (0x1U << CAN_F0R2_FB29_Pos) /*!< 0x20000000 */
4389 #define CAN_F0R2_FB29 CAN_F0R2_FB29_Msk /*!<Filter bit 29 */
4390 #define CAN_F0R2_FB30_Pos (30U)
4391 #define CAN_F0R2_FB30_Msk (0x1U << CAN_F0R2_FB30_Pos) /*!< 0x40000000 */
4392 #define CAN_F0R2_FB30 CAN_F0R2_FB30_Msk /*!<Filter bit 30 */
4393 #define CAN_F0R2_FB31_Pos (31U)
4394 #define CAN_F0R2_FB31_Msk (0x1U << CAN_F0R2_FB31_Pos) /*!< 0x80000000 */
4395 #define CAN_F0R2_FB31 CAN_F0R2_FB31_Msk /*!<Filter bit 31 */
4396
4397 /******************* Bit definition for CAN_F1R2 register *******************/
4398 #define CAN_F1R2_FB0_Pos (0U)
4399 #define CAN_F1R2_FB0_Msk (0x1U << CAN_F1R2_FB0_Pos) /*!< 0x00000001 */
4400 #define CAN_F1R2_FB0 CAN_F1R2_FB0_Msk /*!<Filter bit 0 */
4401 #define CAN_F1R2_FB1_Pos (1U)
4402 #define CAN_F1R2_FB1_Msk (0x1U << CAN_F1R2_FB1_Pos) /*!< 0x00000002 */
4403 #define CAN_F1R2_FB1 CAN_F1R2_FB1_Msk /*!<Filter bit 1 */
4404 #define CAN_F1R2_FB2_Pos (2U)
4405 #define CAN_F1R2_FB2_Msk (0x1U << CAN_F1R2_FB2_Pos) /*!< 0x00000004 */
4406 #define CAN_F1R2_FB2 CAN_F1R2_FB2_Msk /*!<Filter bit 2 */
4407 #define CAN_F1R2_FB3_Pos (3U)
4408 #define CAN_F1R2_FB3_Msk (0x1U << CAN_F1R2_FB3_Pos) /*!< 0x00000008 */
4409 #define CAN_F1R2_FB3 CAN_F1R2_FB3_Msk /*!<Filter bit 3 */
4410 #define CAN_F1R2_FB4_Pos (4U)
4411 #define CAN_F1R2_FB4_Msk (0x1U << CAN_F1R2_FB4_Pos) /*!< 0x00000010 */
4412 #define CAN_F1R2_FB4 CAN_F1R2_FB4_Msk /*!<Filter bit 4 */
4413 #define CAN_F1R2_FB5_Pos (5U)
4414 #define CAN_F1R2_FB5_Msk (0x1U << CAN_F1R2_FB5_Pos) /*!< 0x00000020 */
4415 #define CAN_F1R2_FB5 CAN_F1R2_FB5_Msk /*!<Filter bit 5 */
4416 #define CAN_F1R2_FB6_Pos (6U)
4417 #define CAN_F1R2_FB6_Msk (0x1U << CAN_F1R2_FB6_Pos) /*!< 0x00000040 */
4418 #define CAN_F1R2_FB6 CAN_F1R2_FB6_Msk /*!<Filter bit 6 */
4419 #define CAN_F1R2_FB7_Pos (7U)
4420 #define CAN_F1R2_FB7_Msk (0x1U << CAN_F1R2_FB7_Pos) /*!< 0x00000080 */
4421 #define CAN_F1R2_FB7 CAN_F1R2_FB7_Msk /*!<Filter bit 7 */
4422 #define CAN_F1R2_FB8_Pos (8U)
4423 #define CAN_F1R2_FB8_Msk (0x1U << CAN_F1R2_FB8_Pos) /*!< 0x00000100 */
4424 #define CAN_F1R2_FB8 CAN_F1R2_FB8_Msk /*!<Filter bit 8 */
4425 #define CAN_F1R2_FB9_Pos (9U)
4426 #define CAN_F1R2_FB9_Msk (0x1U << CAN_F1R2_FB9_Pos) /*!< 0x00000200 */
4427 #define CAN_F1R2_FB9 CAN_F1R2_FB9_Msk /*!<Filter bit 9 */
4428 #define CAN_F1R2_FB10_Pos (10U)
4429 #define CAN_F1R2_FB10_Msk (0x1U << CAN_F1R2_FB10_Pos) /*!< 0x00000400 */
4430 #define CAN_F1R2_FB10 CAN_F1R2_FB10_Msk /*!<Filter bit 10 */
4431 #define CAN_F1R2_FB11_Pos (11U)
4432 #define CAN_F1R2_FB11_Msk (0x1U << CAN_F1R2_FB11_Pos) /*!< 0x00000800 */
4433 #define CAN_F1R2_FB11 CAN_F1R2_FB11_Msk /*!<Filter bit 11 */
4434 #define CAN_F1R2_FB12_Pos (12U)
4435 #define CAN_F1R2_FB12_Msk (0x1U << CAN_F1R2_FB12_Pos) /*!< 0x00001000 */
4436 #define CAN_F1R2_FB12 CAN_F1R2_FB12_Msk /*!<Filter bit 12 */
4437 #define CAN_F1R2_FB13_Pos (13U)
4438 #define CAN_F1R2_FB13_Msk (0x1U << CAN_F1R2_FB13_Pos) /*!< 0x00002000 */
4439 #define CAN_F1R2_FB13 CAN_F1R2_FB13_Msk /*!<Filter bit 13 */
4440 #define CAN_F1R2_FB14_Pos (14U)
4441 #define CAN_F1R2_FB14_Msk (0x1U << CAN_F1R2_FB14_Pos) /*!< 0x00004000 */
4442 #define CAN_F1R2_FB14 CAN_F1R2_FB14_Msk /*!<Filter bit 14 */
4443 #define CAN_F1R2_FB15_Pos (15U)
4444 #define CAN_F1R2_FB15_Msk (0x1U << CAN_F1R2_FB15_Pos) /*!< 0x00008000 */
4445 #define CAN_F1R2_FB15 CAN_F1R2_FB15_Msk /*!<Filter bit 15 */
4446 #define CAN_F1R2_FB16_Pos (16U)
4447 #define CAN_F1R2_FB16_Msk (0x1U << CAN_F1R2_FB16_Pos) /*!< 0x00010000 */
4448 #define CAN_F1R2_FB16 CAN_F1R2_FB16_Msk /*!<Filter bit 16 */
4449 #define CAN_F1R2_FB17_Pos (17U)
4450 #define CAN_F1R2_FB17_Msk (0x1U << CAN_F1R2_FB17_Pos) /*!< 0x00020000 */
4451 #define CAN_F1R2_FB17 CAN_F1R2_FB17_Msk /*!<Filter bit 17 */
4452 #define CAN_F1R2_FB18_Pos (18U)
4453 #define CAN_F1R2_FB18_Msk (0x1U << CAN_F1R2_FB18_Pos) /*!< 0x00040000 */
4454 #define CAN_F1R2_FB18 CAN_F1R2_FB18_Msk /*!<Filter bit 18 */
4455 #define CAN_F1R2_FB19_Pos (19U)
4456 #define CAN_F1R2_FB19_Msk (0x1U << CAN_F1R2_FB19_Pos) /*!< 0x00080000 */
4457 #define CAN_F1R2_FB19 CAN_F1R2_FB19_Msk /*!<Filter bit 19 */
4458 #define CAN_F1R2_FB20_Pos (20U)
4459 #define CAN_F1R2_FB20_Msk (0x1U << CAN_F1R2_FB20_Pos) /*!< 0x00100000 */
4460 #define CAN_F1R2_FB20 CAN_F1R2_FB20_Msk /*!<Filter bit 20 */
4461 #define CAN_F1R2_FB21_Pos (21U)
4462 #define CAN_F1R2_FB21_Msk (0x1U << CAN_F1R2_FB21_Pos) /*!< 0x00200000 */
4463 #define CAN_F1R2_FB21 CAN_F1R2_FB21_Msk /*!<Filter bit 21 */
4464 #define CAN_F1R2_FB22_Pos (22U)
4465 #define CAN_F1R2_FB22_Msk (0x1U << CAN_F1R2_FB22_Pos) /*!< 0x00400000 */
4466 #define CAN_F1R2_FB22 CAN_F1R2_FB22_Msk /*!<Filter bit 22 */
4467 #define CAN_F1R2_FB23_Pos (23U)
4468 #define CAN_F1R2_FB23_Msk (0x1U << CAN_F1R2_FB23_Pos) /*!< 0x00800000 */
4469 #define CAN_F1R2_FB23 CAN_F1R2_FB23_Msk /*!<Filter bit 23 */
4470 #define CAN_F1R2_FB24_Pos (24U)
4471 #define CAN_F1R2_FB24_Msk (0x1U << CAN_F1R2_FB24_Pos) /*!< 0x01000000 */
4472 #define CAN_F1R2_FB24 CAN_F1R2_FB24_Msk /*!<Filter bit 24 */
4473 #define CAN_F1R2_FB25_Pos (25U)
4474 #define CAN_F1R2_FB25_Msk (0x1U << CAN_F1R2_FB25_Pos) /*!< 0x02000000 */
4475 #define CAN_F1R2_FB25 CAN_F1R2_FB25_Msk /*!<Filter bit 25 */
4476 #define CAN_F1R2_FB26_Pos (26U)
4477 #define CAN_F1R2_FB26_Msk (0x1U << CAN_F1R2_FB26_Pos) /*!< 0x04000000 */
4478 #define CAN_F1R2_FB26 CAN_F1R2_FB26_Msk /*!<Filter bit 26 */
4479 #define CAN_F1R2_FB27_Pos (27U)
4480 #define CAN_F1R2_FB27_Msk (0x1U << CAN_F1R2_FB27_Pos) /*!< 0x08000000 */
4481 #define CAN_F1R2_FB27 CAN_F1R2_FB27_Msk /*!<Filter bit 27 */
4482 #define CAN_F1R2_FB28_Pos (28U)
4483 #define CAN_F1R2_FB28_Msk (0x1U << CAN_F1R2_FB28_Pos) /*!< 0x10000000 */
4484 #define CAN_F1R2_FB28 CAN_F1R2_FB28_Msk /*!<Filter bit 28 */
4485 #define CAN_F1R2_FB29_Pos (29U)
4486 #define CAN_F1R2_FB29_Msk (0x1U << CAN_F1R2_FB29_Pos) /*!< 0x20000000 */
4487 #define CAN_F1R2_FB29 CAN_F1R2_FB29_Msk /*!<Filter bit 29 */
4488 #define CAN_F1R2_FB30_Pos (30U)
4489 #define CAN_F1R2_FB30_Msk (0x1U << CAN_F1R2_FB30_Pos) /*!< 0x40000000 */
4490 #define CAN_F1R2_FB30 CAN_F1R2_FB30_Msk /*!<Filter bit 30 */
4491 #define CAN_F1R2_FB31_Pos (31U)
4492 #define CAN_F1R2_FB31_Msk (0x1U << CAN_F1R2_FB31_Pos) /*!< 0x80000000 */
4493 #define CAN_F1R2_FB31 CAN_F1R2_FB31_Msk /*!<Filter bit 31 */
4494
4495 /******************* Bit definition for CAN_F2R2 register *******************/
4496 #define CAN_F2R2_FB0_Pos (0U)
4497 #define CAN_F2R2_FB0_Msk (0x1U << CAN_F2R2_FB0_Pos) /*!< 0x00000001 */
4498 #define CAN_F2R2_FB0 CAN_F2R2_FB0_Msk /*!<Filter bit 0 */
4499 #define CAN_F2R2_FB1_Pos (1U)
4500 #define CAN_F2R2_FB1_Msk (0x1U << CAN_F2R2_FB1_Pos) /*!< 0x00000002 */
4501 #define CAN_F2R2_FB1 CAN_F2R2_FB1_Msk /*!<Filter bit 1 */
4502 #define CAN_F2R2_FB2_Pos (2U)
4503 #define CAN_F2R2_FB2_Msk (0x1U << CAN_F2R2_FB2_Pos) /*!< 0x00000004 */
4504 #define CAN_F2R2_FB2 CAN_F2R2_FB2_Msk /*!<Filter bit 2 */
4505 #define CAN_F2R2_FB3_Pos (3U)
4506 #define CAN_F2R2_FB3_Msk (0x1U << CAN_F2R2_FB3_Pos) /*!< 0x00000008 */
4507 #define CAN_F2R2_FB3 CAN_F2R2_FB3_Msk /*!<Filter bit 3 */
4508 #define CAN_F2R2_FB4_Pos (4U)
4509 #define CAN_F2R2_FB4_Msk (0x1U << CAN_F2R2_FB4_Pos) /*!< 0x00000010 */
4510 #define CAN_F2R2_FB4 CAN_F2R2_FB4_Msk /*!<Filter bit 4 */
4511 #define CAN_F2R2_FB5_Pos (5U)
4512 #define CAN_F2R2_FB5_Msk (0x1U << CAN_F2R2_FB5_Pos) /*!< 0x00000020 */
4513 #define CAN_F2R2_FB5 CAN_F2R2_FB5_Msk /*!<Filter bit 5 */
4514 #define CAN_F2R2_FB6_Pos (6U)
4515 #define CAN_F2R2_FB6_Msk (0x1U << CAN_F2R2_FB6_Pos) /*!< 0x00000040 */
4516 #define CAN_F2R2_FB6 CAN_F2R2_FB6_Msk /*!<Filter bit 6 */
4517 #define CAN_F2R2_FB7_Pos (7U)
4518 #define CAN_F2R2_FB7_Msk (0x1U << CAN_F2R2_FB7_Pos) /*!< 0x00000080 */
4519 #define CAN_F2R2_FB7 CAN_F2R2_FB7_Msk /*!<Filter bit 7 */
4520 #define CAN_F2R2_FB8_Pos (8U)
4521 #define CAN_F2R2_FB8_Msk (0x1U << CAN_F2R2_FB8_Pos) /*!< 0x00000100 */
4522 #define CAN_F2R2_FB8 CAN_F2R2_FB8_Msk /*!<Filter bit 8 */
4523 #define CAN_F2R2_FB9_Pos (9U)
4524 #define CAN_F2R2_FB9_Msk (0x1U << CAN_F2R2_FB9_Pos) /*!< 0x00000200 */
4525 #define CAN_F2R2_FB9 CAN_F2R2_FB9_Msk /*!<Filter bit 9 */
4526 #define CAN_F2R2_FB10_Pos (10U)
4527 #define CAN_F2R2_FB10_Msk (0x1U << CAN_F2R2_FB10_Pos) /*!< 0x00000400 */
4528 #define CAN_F2R2_FB10 CAN_F2R2_FB10_Msk /*!<Filter bit 10 */
4529 #define CAN_F2R2_FB11_Pos (11U)
4530 #define CAN_F2R2_FB11_Msk (0x1U << CAN_F2R2_FB11_Pos) /*!< 0x00000800 */
4531 #define CAN_F2R2_FB11 CAN_F2R2_FB11_Msk /*!<Filter bit 11 */
4532 #define CAN_F2R2_FB12_Pos (12U)
4533 #define CAN_F2R2_FB12_Msk (0x1U << CAN_F2R2_FB12_Pos) /*!< 0x00001000 */
4534 #define CAN_F2R2_FB12 CAN_F2R2_FB12_Msk /*!<Filter bit 12 */
4535 #define CAN_F2R2_FB13_Pos (13U)
4536 #define CAN_F2R2_FB13_Msk (0x1U << CAN_F2R2_FB13_Pos) /*!< 0x00002000 */
4537 #define CAN_F2R2_FB13 CAN_F2R2_FB13_Msk /*!<Filter bit 13 */
4538 #define CAN_F2R2_FB14_Pos (14U)
4539 #define CAN_F2R2_FB14_Msk (0x1U << CAN_F2R2_FB14_Pos) /*!< 0x00004000 */
4540 #define CAN_F2R2_FB14 CAN_F2R2_FB14_Msk /*!<Filter bit 14 */
4541 #define CAN_F2R2_FB15_Pos (15U)
4542 #define CAN_F2R2_FB15_Msk (0x1U << CAN_F2R2_FB15_Pos) /*!< 0x00008000 */
4543 #define CAN_F2R2_FB15 CAN_F2R2_FB15_Msk /*!<Filter bit 15 */
4544 #define CAN_F2R2_FB16_Pos (16U)
4545 #define CAN_F2R2_FB16_Msk (0x1U << CAN_F2R2_FB16_Pos) /*!< 0x00010000 */
4546 #define CAN_F2R2_FB16 CAN_F2R2_FB16_Msk /*!<Filter bit 16 */
4547 #define CAN_F2R2_FB17_Pos (17U)
4548 #define CAN_F2R2_FB17_Msk (0x1U << CAN_F2R2_FB17_Pos) /*!< 0x00020000 */
4549 #define CAN_F2R2_FB17 CAN_F2R2_FB17_Msk /*!<Filter bit 17 */
4550 #define CAN_F2R2_FB18_Pos (18U)
4551 #define CAN_F2R2_FB18_Msk (0x1U << CAN_F2R2_FB18_Pos) /*!< 0x00040000 */
4552 #define CAN_F2R2_FB18 CAN_F2R2_FB18_Msk /*!<Filter bit 18 */
4553 #define CAN_F2R2_FB19_Pos (19U)
4554 #define CAN_F2R2_FB19_Msk (0x1U << CAN_F2R2_FB19_Pos) /*!< 0x00080000 */
4555 #define CAN_F2R2_FB19 CAN_F2R2_FB19_Msk /*!<Filter bit 19 */
4556 #define CAN_F2R2_FB20_Pos (20U)
4557 #define CAN_F2R2_FB20_Msk (0x1U << CAN_F2R2_FB20_Pos) /*!< 0x00100000 */
4558 #define CAN_F2R2_FB20 CAN_F2R2_FB20_Msk /*!<Filter bit 20 */
4559 #define CAN_F2R2_FB21_Pos (21U)
4560 #define CAN_F2R2_FB21_Msk (0x1U << CAN_F2R2_FB21_Pos) /*!< 0x00200000 */
4561 #define CAN_F2R2_FB21 CAN_F2R2_FB21_Msk /*!<Filter bit 21 */
4562 #define CAN_F2R2_FB22_Pos (22U)
4563 #define CAN_F2R2_FB22_Msk (0x1U << CAN_F2R2_FB22_Pos) /*!< 0x00400000 */
4564 #define CAN_F2R2_FB22 CAN_F2R2_FB22_Msk /*!<Filter bit 22 */
4565 #define CAN_F2R2_FB23_Pos (23U)
4566 #define CAN_F2R2_FB23_Msk (0x1U << CAN_F2R2_FB23_Pos) /*!< 0x00800000 */
4567 #define CAN_F2R2_FB23 CAN_F2R2_FB23_Msk /*!<Filter bit 23 */
4568 #define CAN_F2R2_FB24_Pos (24U)
4569 #define CAN_F2R2_FB24_Msk (0x1U << CAN_F2R2_FB24_Pos) /*!< 0x01000000 */
4570 #define CAN_F2R2_FB24 CAN_F2R2_FB24_Msk /*!<Filter bit 24 */
4571 #define CAN_F2R2_FB25_Pos (25U)
4572 #define CAN_F2R2_FB25_Msk (0x1U << CAN_F2R2_FB25_Pos) /*!< 0x02000000 */
4573 #define CAN_F2R2_FB25 CAN_F2R2_FB25_Msk /*!<Filter bit 25 */
4574 #define CAN_F2R2_FB26_Pos (26U)
4575 #define CAN_F2R2_FB26_Msk (0x1U << CAN_F2R2_FB26_Pos) /*!< 0x04000000 */
4576 #define CAN_F2R2_FB26 CAN_F2R2_FB26_Msk /*!<Filter bit 26 */
4577 #define CAN_F2R2_FB27_Pos (27U)
4578 #define CAN_F2R2_FB27_Msk (0x1U << CAN_F2R2_FB27_Pos) /*!< 0x08000000 */
4579 #define CAN_F2R2_FB27 CAN_F2R2_FB27_Msk /*!<Filter bit 27 */
4580 #define CAN_F2R2_FB28_Pos (28U)
4581 #define CAN_F2R2_FB28_Msk (0x1U << CAN_F2R2_FB28_Pos) /*!< 0x10000000 */
4582 #define CAN_F2R2_FB28 CAN_F2R2_FB28_Msk /*!<Filter bit 28 */
4583 #define CAN_F2R2_FB29_Pos (29U)
4584 #define CAN_F2R2_FB29_Msk (0x1U << CAN_F2R2_FB29_Pos) /*!< 0x20000000 */
4585 #define CAN_F2R2_FB29 CAN_F2R2_FB29_Msk /*!<Filter bit 29 */
4586 #define CAN_F2R2_FB30_Pos (30U)
4587 #define CAN_F2R2_FB30_Msk (0x1U << CAN_F2R2_FB30_Pos) /*!< 0x40000000 */
4588 #define CAN_F2R2_FB30 CAN_F2R2_FB30_Msk /*!<Filter bit 30 */
4589 #define CAN_F2R2_FB31_Pos (31U)
4590 #define CAN_F2R2_FB31_Msk (0x1U << CAN_F2R2_FB31_Pos) /*!< 0x80000000 */
4591 #define CAN_F2R2_FB31 CAN_F2R2_FB31_Msk /*!<Filter bit 31 */
4592
4593 /******************* Bit definition for CAN_F3R2 register *******************/
4594 #define CAN_F3R2_FB0_Pos (0U)
4595 #define CAN_F3R2_FB0_Msk (0x1U << CAN_F3R2_FB0_Pos) /*!< 0x00000001 */
4596 #define CAN_F3R2_FB0 CAN_F3R2_FB0_Msk /*!<Filter bit 0 */
4597 #define CAN_F3R2_FB1_Pos (1U)
4598 #define CAN_F3R2_FB1_Msk (0x1U << CAN_F3R2_FB1_Pos) /*!< 0x00000002 */
4599 #define CAN_F3R2_FB1 CAN_F3R2_FB1_Msk /*!<Filter bit 1 */
4600 #define CAN_F3R2_FB2_Pos (2U)
4601 #define CAN_F3R2_FB2_Msk (0x1U << CAN_F3R2_FB2_Pos) /*!< 0x00000004 */
4602 #define CAN_F3R2_FB2 CAN_F3R2_FB2_Msk /*!<Filter bit 2 */
4603 #define CAN_F3R2_FB3_Pos (3U)
4604 #define CAN_F3R2_FB3_Msk (0x1U << CAN_F3R2_FB3_Pos) /*!< 0x00000008 */
4605 #define CAN_F3R2_FB3 CAN_F3R2_FB3_Msk /*!<Filter bit 3 */
4606 #define CAN_F3R2_FB4_Pos (4U)
4607 #define CAN_F3R2_FB4_Msk (0x1U << CAN_F3R2_FB4_Pos) /*!< 0x00000010 */
4608 #define CAN_F3R2_FB4 CAN_F3R2_FB4_Msk /*!<Filter bit 4 */
4609 #define CAN_F3R2_FB5_Pos (5U)
4610 #define CAN_F3R2_FB5_Msk (0x1U << CAN_F3R2_FB5_Pos) /*!< 0x00000020 */
4611 #define CAN_F3R2_FB5 CAN_F3R2_FB5_Msk /*!<Filter bit 5 */
4612 #define CAN_F3R2_FB6_Pos (6U)
4613 #define CAN_F3R2_FB6_Msk (0x1U << CAN_F3R2_FB6_Pos) /*!< 0x00000040 */
4614 #define CAN_F3R2_FB6 CAN_F3R2_FB6_Msk /*!<Filter bit 6 */
4615 #define CAN_F3R2_FB7_Pos (7U)
4616 #define CAN_F3R2_FB7_Msk (0x1U << CAN_F3R2_FB7_Pos) /*!< 0x00000080 */
4617 #define CAN_F3R2_FB7 CAN_F3R2_FB7_Msk /*!<Filter bit 7 */
4618 #define CAN_F3R2_FB8_Pos (8U)
4619 #define CAN_F3R2_FB8_Msk (0x1U << CAN_F3R2_FB8_Pos) /*!< 0x00000100 */
4620 #define CAN_F3R2_FB8 CAN_F3R2_FB8_Msk /*!<Filter bit 8 */
4621 #define CAN_F3R2_FB9_Pos (9U)
4622 #define CAN_F3R2_FB9_Msk (0x1U << CAN_F3R2_FB9_Pos) /*!< 0x00000200 */
4623 #define CAN_F3R2_FB9 CAN_F3R2_FB9_Msk /*!<Filter bit 9 */
4624 #define CAN_F3R2_FB10_Pos (10U)
4625 #define CAN_F3R2_FB10_Msk (0x1U << CAN_F3R2_FB10_Pos) /*!< 0x00000400 */
4626 #define CAN_F3R2_FB10 CAN_F3R2_FB10_Msk /*!<Filter bit 10 */
4627 #define CAN_F3R2_FB11_Pos (11U)
4628 #define CAN_F3R2_FB11_Msk (0x1U << CAN_F3R2_FB11_Pos) /*!< 0x00000800 */
4629 #define CAN_F3R2_FB11 CAN_F3R2_FB11_Msk /*!<Filter bit 11 */
4630 #define CAN_F3R2_FB12_Pos (12U)
4631 #define CAN_F3R2_FB12_Msk (0x1U << CAN_F3R2_FB12_Pos) /*!< 0x00001000 */
4632 #define CAN_F3R2_FB12 CAN_F3R2_FB12_Msk /*!<Filter bit 12 */
4633 #define CAN_F3R2_FB13_Pos (13U)
4634 #define CAN_F3R2_FB13_Msk (0x1U << CAN_F3R2_FB13_Pos) /*!< 0x00002000 */
4635 #define CAN_F3R2_FB13 CAN_F3R2_FB13_Msk /*!<Filter bit 13 */
4636 #define CAN_F3R2_FB14_Pos (14U)
4637 #define CAN_F3R2_FB14_Msk (0x1U << CAN_F3R2_FB14_Pos) /*!< 0x00004000 */
4638 #define CAN_F3R2_FB14 CAN_F3R2_FB14_Msk /*!<Filter bit 14 */
4639 #define CAN_F3R2_FB15_Pos (15U)
4640 #define CAN_F3R2_FB15_Msk (0x1U << CAN_F3R2_FB15_Pos) /*!< 0x00008000 */
4641 #define CAN_F3R2_FB15 CAN_F3R2_FB15_Msk /*!<Filter bit 15 */
4642 #define CAN_F3R2_FB16_Pos (16U)
4643 #define CAN_F3R2_FB16_Msk (0x1U << CAN_F3R2_FB16_Pos) /*!< 0x00010000 */
4644 #define CAN_F3R2_FB16 CAN_F3R2_FB16_Msk /*!<Filter bit 16 */
4645 #define CAN_F3R2_FB17_Pos (17U)
4646 #define CAN_F3R2_FB17_Msk (0x1U << CAN_F3R2_FB17_Pos) /*!< 0x00020000 */
4647 #define CAN_F3R2_FB17 CAN_F3R2_FB17_Msk /*!<Filter bit 17 */
4648 #define CAN_F3R2_FB18_Pos (18U)
4649 #define CAN_F3R2_FB18_Msk (0x1U << CAN_F3R2_FB18_Pos) /*!< 0x00040000 */
4650 #define CAN_F3R2_FB18 CAN_F3R2_FB18_Msk /*!<Filter bit 18 */
4651 #define CAN_F3R2_FB19_Pos (19U)
4652 #define CAN_F3R2_FB19_Msk (0x1U << CAN_F3R2_FB19_Pos) /*!< 0x00080000 */
4653 #define CAN_F3R2_FB19 CAN_F3R2_FB19_Msk /*!<Filter bit 19 */
4654 #define CAN_F3R2_FB20_Pos (20U)
4655 #define CAN_F3R2_FB20_Msk (0x1U << CAN_F3R2_FB20_Pos) /*!< 0x00100000 */
4656 #define CAN_F3R2_FB20 CAN_F3R2_FB20_Msk /*!<Filter bit 20 */
4657 #define CAN_F3R2_FB21_Pos (21U)
4658 #define CAN_F3R2_FB21_Msk (0x1U << CAN_F3R2_FB21_Pos) /*!< 0x00200000 */
4659 #define CAN_F3R2_FB21 CAN_F3R2_FB21_Msk /*!<Filter bit 21 */
4660 #define CAN_F3R2_FB22_Pos (22U)
4661 #define CAN_F3R2_FB22_Msk (0x1U << CAN_F3R2_FB22_Pos) /*!< 0x00400000 */
4662 #define CAN_F3R2_FB22 CAN_F3R2_FB22_Msk /*!<Filter bit 22 */
4663 #define CAN_F3R2_FB23_Pos (23U)
4664 #define CAN_F3R2_FB23_Msk (0x1U << CAN_F3R2_FB23_Pos) /*!< 0x00800000 */
4665 #define CAN_F3R2_FB23 CAN_F3R2_FB23_Msk /*!<Filter bit 23 */
4666 #define CAN_F3R2_FB24_Pos (24U)
4667 #define CAN_F3R2_FB24_Msk (0x1U << CAN_F3R2_FB24_Pos) /*!< 0x01000000 */
4668 #define CAN_F3R2_FB24 CAN_F3R2_FB24_Msk /*!<Filter bit 24 */
4669 #define CAN_F3R2_FB25_Pos (25U)
4670 #define CAN_F3R2_FB25_Msk (0x1U << CAN_F3R2_FB25_Pos) /*!< 0x02000000 */
4671 #define CAN_F3R2_FB25 CAN_F3R2_FB25_Msk /*!<Filter bit 25 */
4672 #define CAN_F3R2_FB26_Pos (26U)
4673 #define CAN_F3R2_FB26_Msk (0x1U << CAN_F3R2_FB26_Pos) /*!< 0x04000000 */
4674 #define CAN_F3R2_FB26 CAN_F3R2_FB26_Msk /*!<Filter bit 26 */
4675 #define CAN_F3R2_FB27_Pos (27U)
4676 #define CAN_F3R2_FB27_Msk (0x1U << CAN_F3R2_FB27_Pos) /*!< 0x08000000 */
4677 #define CAN_F3R2_FB27 CAN_F3R2_FB27_Msk /*!<Filter bit 27 */
4678 #define CAN_F3R2_FB28_Pos (28U)
4679 #define CAN_F3R2_FB28_Msk (0x1U << CAN_F3R2_FB28_Pos) /*!< 0x10000000 */
4680 #define CAN_F3R2_FB28 CAN_F3R2_FB28_Msk /*!<Filter bit 28 */
4681 #define CAN_F3R2_FB29_Pos (29U)
4682 #define CAN_F3R2_FB29_Msk (0x1U << CAN_F3R2_FB29_Pos) /*!< 0x20000000 */
4683 #define CAN_F3R2_FB29 CAN_F3R2_FB29_Msk /*!<Filter bit 29 */
4684 #define CAN_F3R2_FB30_Pos (30U)
4685 #define CAN_F3R2_FB30_Msk (0x1U << CAN_F3R2_FB30_Pos) /*!< 0x40000000 */
4686 #define CAN_F3R2_FB30 CAN_F3R2_FB30_Msk /*!<Filter bit 30 */
4687 #define CAN_F3R2_FB31_Pos (31U)
4688 #define CAN_F3R2_FB31_Msk (0x1U << CAN_F3R2_FB31_Pos) /*!< 0x80000000 */
4689 #define CAN_F3R2_FB31 CAN_F3R2_FB31_Msk /*!<Filter bit 31 */
4690
4691 /******************* Bit definition for CAN_F4R2 register *******************/
4692 #define CAN_F4R2_FB0_Pos (0U)
4693 #define CAN_F4R2_FB0_Msk (0x1U << CAN_F4R2_FB0_Pos) /*!< 0x00000001 */
4694 #define CAN_F4R2_FB0 CAN_F4R2_FB0_Msk /*!<Filter bit 0 */
4695 #define CAN_F4R2_FB1_Pos (1U)
4696 #define CAN_F4R2_FB1_Msk (0x1U << CAN_F4R2_FB1_Pos) /*!< 0x00000002 */
4697 #define CAN_F4R2_FB1 CAN_F4R2_FB1_Msk /*!<Filter bit 1 */
4698 #define CAN_F4R2_FB2_Pos (2U)
4699 #define CAN_F4R2_FB2_Msk (0x1U << CAN_F4R2_FB2_Pos) /*!< 0x00000004 */
4700 #define CAN_F4R2_FB2 CAN_F4R2_FB2_Msk /*!<Filter bit 2 */
4701 #define CAN_F4R2_FB3_Pos (3U)
4702 #define CAN_F4R2_FB3_Msk (0x1U << CAN_F4R2_FB3_Pos) /*!< 0x00000008 */
4703 #define CAN_F4R2_FB3 CAN_F4R2_FB3_Msk /*!<Filter bit 3 */
4704 #define CAN_F4R2_FB4_Pos (4U)
4705 #define CAN_F4R2_FB4_Msk (0x1U << CAN_F4R2_FB4_Pos) /*!< 0x00000010 */
4706 #define CAN_F4R2_FB4 CAN_F4R2_FB4_Msk /*!<Filter bit 4 */
4707 #define CAN_F4R2_FB5_Pos (5U)
4708 #define CAN_F4R2_FB5_Msk (0x1U << CAN_F4R2_FB5_Pos) /*!< 0x00000020 */
4709 #define CAN_F4R2_FB5 CAN_F4R2_FB5_Msk /*!<Filter bit 5 */
4710 #define CAN_F4R2_FB6_Pos (6U)
4711 #define CAN_F4R2_FB6_Msk (0x1U << CAN_F4R2_FB6_Pos) /*!< 0x00000040 */
4712 #define CAN_F4R2_FB6 CAN_F4R2_FB6_Msk /*!<Filter bit 6 */
4713 #define CAN_F4R2_FB7_Pos (7U)
4714 #define CAN_F4R2_FB7_Msk (0x1U << CAN_F4R2_FB7_Pos) /*!< 0x00000080 */
4715 #define CAN_F4R2_FB7 CAN_F4R2_FB7_Msk /*!<Filter bit 7 */
4716 #define CAN_F4R2_FB8_Pos (8U)
4717 #define CAN_F4R2_FB8_Msk (0x1U << CAN_F4R2_FB8_Pos) /*!< 0x00000100 */
4718 #define CAN_F4R2_FB8 CAN_F4R2_FB8_Msk /*!<Filter bit 8 */
4719 #define CAN_F4R2_FB9_Pos (9U)
4720 #define CAN_F4R2_FB9_Msk (0x1U << CAN_F4R2_FB9_Pos) /*!< 0x00000200 */
4721 #define CAN_F4R2_FB9 CAN_F4R2_FB9_Msk /*!<Filter bit 9 */
4722 #define CAN_F4R2_FB10_Pos (10U)
4723 #define CAN_F4R2_FB10_Msk (0x1U << CAN_F4R2_FB10_Pos) /*!< 0x00000400 */
4724 #define CAN_F4R2_FB10 CAN_F4R2_FB10_Msk /*!<Filter bit 10 */
4725 #define CAN_F4R2_FB11_Pos (11U)
4726 #define CAN_F4R2_FB11_Msk (0x1U << CAN_F4R2_FB11_Pos) /*!< 0x00000800 */
4727 #define CAN_F4R2_FB11 CAN_F4R2_FB11_Msk /*!<Filter bit 11 */
4728 #define CAN_F4R2_FB12_Pos (12U)
4729 #define CAN_F4R2_FB12_Msk (0x1U << CAN_F4R2_FB12_Pos) /*!< 0x00001000 */
4730 #define CAN_F4R2_FB12 CAN_F4R2_FB12_Msk /*!<Filter bit 12 */
4731 #define CAN_F4R2_FB13_Pos (13U)
4732 #define CAN_F4R2_FB13_Msk (0x1U << CAN_F4R2_FB13_Pos) /*!< 0x00002000 */
4733 #define CAN_F4R2_FB13 CAN_F4R2_FB13_Msk /*!<Filter bit 13 */
4734 #define CAN_F4R2_FB14_Pos (14U)
4735 #define CAN_F4R2_FB14_Msk (0x1U << CAN_F4R2_FB14_Pos) /*!< 0x00004000 */
4736 #define CAN_F4R2_FB14 CAN_F4R2_FB14_Msk /*!<Filter bit 14 */
4737 #define CAN_F4R2_FB15_Pos (15U)
4738 #define CAN_F4R2_FB15_Msk (0x1U << CAN_F4R2_FB15_Pos) /*!< 0x00008000 */
4739 #define CAN_F4R2_FB15 CAN_F4R2_FB15_Msk /*!<Filter bit 15 */
4740 #define CAN_F4R2_FB16_Pos (16U)
4741 #define CAN_F4R2_FB16_Msk (0x1U << CAN_F4R2_FB16_Pos) /*!< 0x00010000 */
4742 #define CAN_F4R2_FB16 CAN_F4R2_FB16_Msk /*!<Filter bit 16 */
4743 #define CAN_F4R2_FB17_Pos (17U)
4744 #define CAN_F4R2_FB17_Msk (0x1U << CAN_F4R2_FB17_Pos) /*!< 0x00020000 */
4745 #define CAN_F4R2_FB17 CAN_F4R2_FB17_Msk /*!<Filter bit 17 */
4746 #define CAN_F4R2_FB18_Pos (18U)
4747 #define CAN_F4R2_FB18_Msk (0x1U << CAN_F4R2_FB18_Pos) /*!< 0x00040000 */
4748 #define CAN_F4R2_FB18 CAN_F4R2_FB18_Msk /*!<Filter bit 18 */
4749 #define CAN_F4R2_FB19_Pos (19U)
4750 #define CAN_F4R2_FB19_Msk (0x1U << CAN_F4R2_FB19_Pos) /*!< 0x00080000 */
4751 #define CAN_F4R2_FB19 CAN_F4R2_FB19_Msk /*!<Filter bit 19 */
4752 #define CAN_F4R2_FB20_Pos (20U)
4753 #define CAN_F4R2_FB20_Msk (0x1U << CAN_F4R2_FB20_Pos) /*!< 0x00100000 */
4754 #define CAN_F4R2_FB20 CAN_F4R2_FB20_Msk /*!<Filter bit 20 */
4755 #define CAN_F4R2_FB21_Pos (21U)
4756 #define CAN_F4R2_FB21_Msk (0x1U << CAN_F4R2_FB21_Pos) /*!< 0x00200000 */
4757 #define CAN_F4R2_FB21 CAN_F4R2_FB21_Msk /*!<Filter bit 21 */
4758 #define CAN_F4R2_FB22_Pos (22U)
4759 #define CAN_F4R2_FB22_Msk (0x1U << CAN_F4R2_FB22_Pos) /*!< 0x00400000 */
4760 #define CAN_F4R2_FB22 CAN_F4R2_FB22_Msk /*!<Filter bit 22 */
4761 #define CAN_F4R2_FB23_Pos (23U)
4762 #define CAN_F4R2_FB23_Msk (0x1U << CAN_F4R2_FB23_Pos) /*!< 0x00800000 */
4763 #define CAN_F4R2_FB23 CAN_F4R2_FB23_Msk /*!<Filter bit 23 */
4764 #define CAN_F4R2_FB24_Pos (24U)
4765 #define CAN_F4R2_FB24_Msk (0x1U << CAN_F4R2_FB24_Pos) /*!< 0x01000000 */
4766 #define CAN_F4R2_FB24 CAN_F4R2_FB24_Msk /*!<Filter bit 24 */
4767 #define CAN_F4R2_FB25_Pos (25U)
4768 #define CAN_F4R2_FB25_Msk (0x1U << CAN_F4R2_FB25_Pos) /*!< 0x02000000 */
4769 #define CAN_F4R2_FB25 CAN_F4R2_FB25_Msk /*!<Filter bit 25 */
4770 #define CAN_F4R2_FB26_Pos (26U)
4771 #define CAN_F4R2_FB26_Msk (0x1U << CAN_F4R2_FB26_Pos) /*!< 0x04000000 */
4772 #define CAN_F4R2_FB26 CAN_F4R2_FB26_Msk /*!<Filter bit 26 */
4773 #define CAN_F4R2_FB27_Pos (27U)
4774 #define CAN_F4R2_FB27_Msk (0x1U << CAN_F4R2_FB27_Pos) /*!< 0x08000000 */
4775 #define CAN_F4R2_FB27 CAN_F4R2_FB27_Msk /*!<Filter bit 27 */
4776 #define CAN_F4R2_FB28_Pos (28U)
4777 #define CAN_F4R2_FB28_Msk (0x1U << CAN_F4R2_FB28_Pos) /*!< 0x10000000 */
4778 #define CAN_F4R2_FB28 CAN_F4R2_FB28_Msk /*!<Filter bit 28 */
4779 #define CAN_F4R2_FB29_Pos (29U)
4780 #define CAN_F4R2_FB29_Msk (0x1U << CAN_F4R2_FB29_Pos) /*!< 0x20000000 */
4781 #define CAN_F4R2_FB29 CAN_F4R2_FB29_Msk /*!<Filter bit 29 */
4782 #define CAN_F4R2_FB30_Pos (30U)
4783 #define CAN_F4R2_FB30_Msk (0x1U << CAN_F4R2_FB30_Pos) /*!< 0x40000000 */
4784 #define CAN_F4R2_FB30 CAN_F4R2_FB30_Msk /*!<Filter bit 30 */
4785 #define CAN_F4R2_FB31_Pos (31U)
4786 #define CAN_F4R2_FB31_Msk (0x1U << CAN_F4R2_FB31_Pos) /*!< 0x80000000 */
4787 #define CAN_F4R2_FB31 CAN_F4R2_FB31_Msk /*!<Filter bit 31 */
4788
4789 /******************* Bit definition for CAN_F5R2 register *******************/
4790 #define CAN_F5R2_FB0_Pos (0U)
4791 #define CAN_F5R2_FB0_Msk (0x1U << CAN_F5R2_FB0_Pos) /*!< 0x00000001 */
4792 #define CAN_F5R2_FB0 CAN_F5R2_FB0_Msk /*!<Filter bit 0 */
4793 #define CAN_F5R2_FB1_Pos (1U)
4794 #define CAN_F5R2_FB1_Msk (0x1U << CAN_F5R2_FB1_Pos) /*!< 0x00000002 */
4795 #define CAN_F5R2_FB1 CAN_F5R2_FB1_Msk /*!<Filter bit 1 */
4796 #define CAN_F5R2_FB2_Pos (2U)
4797 #define CAN_F5R2_FB2_Msk (0x1U << CAN_F5R2_FB2_Pos) /*!< 0x00000004 */
4798 #define CAN_F5R2_FB2 CAN_F5R2_FB2_Msk /*!<Filter bit 2 */
4799 #define CAN_F5R2_FB3_Pos (3U)
4800 #define CAN_F5R2_FB3_Msk (0x1U << CAN_F5R2_FB3_Pos) /*!< 0x00000008 */
4801 #define CAN_F5R2_FB3 CAN_F5R2_FB3_Msk /*!<Filter bit 3 */
4802 #define CAN_F5R2_FB4_Pos (4U)
4803 #define CAN_F5R2_FB4_Msk (0x1U << CAN_F5R2_FB4_Pos) /*!< 0x00000010 */
4804 #define CAN_F5R2_FB4 CAN_F5R2_FB4_Msk /*!<Filter bit 4 */
4805 #define CAN_F5R2_FB5_Pos (5U)
4806 #define CAN_F5R2_FB5_Msk (0x1U << CAN_F5R2_FB5_Pos) /*!< 0x00000020 */
4807 #define CAN_F5R2_FB5 CAN_F5R2_FB5_Msk /*!<Filter bit 5 */
4808 #define CAN_F5R2_FB6_Pos (6U)
4809 #define CAN_F5R2_FB6_Msk (0x1U << CAN_F5R2_FB6_Pos) /*!< 0x00000040 */
4810 #define CAN_F5R2_FB6 CAN_F5R2_FB6_Msk /*!<Filter bit 6 */
4811 #define CAN_F5R2_FB7_Pos (7U)
4812 #define CAN_F5R2_FB7_Msk (0x1U << CAN_F5R2_FB7_Pos) /*!< 0x00000080 */
4813 #define CAN_F5R2_FB7 CAN_F5R2_FB7_Msk /*!<Filter bit 7 */
4814 #define CAN_F5R2_FB8_Pos (8U)
4815 #define CAN_F5R2_FB8_Msk (0x1U << CAN_F5R2_FB8_Pos) /*!< 0x00000100 */
4816 #define CAN_F5R2_FB8 CAN_F5R2_FB8_Msk /*!<Filter bit 8 */
4817 #define CAN_F5R2_FB9_Pos (9U)
4818 #define CAN_F5R2_FB9_Msk (0x1U << CAN_F5R2_FB9_Pos) /*!< 0x00000200 */
4819 #define CAN_F5R2_FB9 CAN_F5R2_FB9_Msk /*!<Filter bit 9 */
4820 #define CAN_F5R2_FB10_Pos (10U)
4821 #define CAN_F5R2_FB10_Msk (0x1U << CAN_F5R2_FB10_Pos) /*!< 0x00000400 */
4822 #define CAN_F5R2_FB10 CAN_F5R2_FB10_Msk /*!<Filter bit 10 */
4823 #define CAN_F5R2_FB11_Pos (11U)
4824 #define CAN_F5R2_FB11_Msk (0x1U << CAN_F5R2_FB11_Pos) /*!< 0x00000800 */
4825 #define CAN_F5R2_FB11 CAN_F5R2_FB11_Msk /*!<Filter bit 11 */
4826 #define CAN_F5R2_FB12_Pos (12U)
4827 #define CAN_F5R2_FB12_Msk (0x1U << CAN_F5R2_FB12_Pos) /*!< 0x00001000 */
4828 #define CAN_F5R2_FB12 CAN_F5R2_FB12_Msk /*!<Filter bit 12 */
4829 #define CAN_F5R2_FB13_Pos (13U)
4830 #define CAN_F5R2_FB13_Msk (0x1U << CAN_F5R2_FB13_Pos) /*!< 0x00002000 */
4831 #define CAN_F5R2_FB13 CAN_F5R2_FB13_Msk /*!<Filter bit 13 */
4832 #define CAN_F5R2_FB14_Pos (14U)
4833 #define CAN_F5R2_FB14_Msk (0x1U << CAN_F5R2_FB14_Pos) /*!< 0x00004000 */
4834 #define CAN_F5R2_FB14 CAN_F5R2_FB14_Msk /*!<Filter bit 14 */
4835 #define CAN_F5R2_FB15_Pos (15U)
4836 #define CAN_F5R2_FB15_Msk (0x1U << CAN_F5R2_FB15_Pos) /*!< 0x00008000 */
4837 #define CAN_F5R2_FB15 CAN_F5R2_FB15_Msk /*!<Filter bit 15 */
4838 #define CAN_F5R2_FB16_Pos (16U)
4839 #define CAN_F5R2_FB16_Msk (0x1U << CAN_F5R2_FB16_Pos) /*!< 0x00010000 */
4840 #define CAN_F5R2_FB16 CAN_F5R2_FB16_Msk /*!<Filter bit 16 */
4841 #define CAN_F5R2_FB17_Pos (17U)
4842 #define CAN_F5R2_FB17_Msk (0x1U << CAN_F5R2_FB17_Pos) /*!< 0x00020000 */
4843 #define CAN_F5R2_FB17 CAN_F5R2_FB17_Msk /*!<Filter bit 17 */
4844 #define CAN_F5R2_FB18_Pos (18U)
4845 #define CAN_F5R2_FB18_Msk (0x1U << CAN_F5R2_FB18_Pos) /*!< 0x00040000 */
4846 #define CAN_F5R2_FB18 CAN_F5R2_FB18_Msk /*!<Filter bit 18 */
4847 #define CAN_F5R2_FB19_Pos (19U)
4848 #define CAN_F5R2_FB19_Msk (0x1U << CAN_F5R2_FB19_Pos) /*!< 0x00080000 */
4849 #define CAN_F5R2_FB19 CAN_F5R2_FB19_Msk /*!<Filter bit 19 */
4850 #define CAN_F5R2_FB20_Pos (20U)
4851 #define CAN_F5R2_FB20_Msk (0x1U << CAN_F5R2_FB20_Pos) /*!< 0x00100000 */
4852 #define CAN_F5R2_FB20 CAN_F5R2_FB20_Msk /*!<Filter bit 20 */
4853 #define CAN_F5R2_FB21_Pos (21U)
4854 #define CAN_F5R2_FB21_Msk (0x1U << CAN_F5R2_FB21_Pos) /*!< 0x00200000 */
4855 #define CAN_F5R2_FB21 CAN_F5R2_FB21_Msk /*!<Filter bit 21 */
4856 #define CAN_F5R2_FB22_Pos (22U)
4857 #define CAN_F5R2_FB22_Msk (0x1U << CAN_F5R2_FB22_Pos) /*!< 0x00400000 */
4858 #define CAN_F5R2_FB22 CAN_F5R2_FB22_Msk /*!<Filter bit 22 */
4859 #define CAN_F5R2_FB23_Pos (23U)
4860 #define CAN_F5R2_FB23_Msk (0x1U << CAN_F5R2_FB23_Pos) /*!< 0x00800000 */
4861 #define CAN_F5R2_FB23 CAN_F5R2_FB23_Msk /*!<Filter bit 23 */
4862 #define CAN_F5R2_FB24_Pos (24U)
4863 #define CAN_F5R2_FB24_Msk (0x1U << CAN_F5R2_FB24_Pos) /*!< 0x01000000 */
4864 #define CAN_F5R2_FB24 CAN_F5R2_FB24_Msk /*!<Filter bit 24 */
4865 #define CAN_F5R2_FB25_Pos (25U)
4866 #define CAN_F5R2_FB25_Msk (0x1U << CAN_F5R2_FB25_Pos) /*!< 0x02000000 */
4867 #define CAN_F5R2_FB25 CAN_F5R2_FB25_Msk /*!<Filter bit 25 */
4868 #define CAN_F5R2_FB26_Pos (26U)
4869 #define CAN_F5R2_FB26_Msk (0x1U << CAN_F5R2_FB26_Pos) /*!< 0x04000000 */
4870 #define CAN_F5R2_FB26 CAN_F5R2_FB26_Msk /*!<Filter bit 26 */
4871 #define CAN_F5R2_FB27_Pos (27U)
4872 #define CAN_F5R2_FB27_Msk (0x1U << CAN_F5R2_FB27_Pos) /*!< 0x08000000 */
4873 #define CAN_F5R2_FB27 CAN_F5R2_FB27_Msk /*!<Filter bit 27 */
4874 #define CAN_F5R2_FB28_Pos (28U)
4875 #define CAN_F5R2_FB28_Msk (0x1U << CAN_F5R2_FB28_Pos) /*!< 0x10000000 */
4876 #define CAN_F5R2_FB28 CAN_F5R2_FB28_Msk /*!<Filter bit 28 */
4877 #define CAN_F5R2_FB29_Pos (29U)
4878 #define CAN_F5R2_FB29_Msk (0x1U << CAN_F5R2_FB29_Pos) /*!< 0x20000000 */
4879 #define CAN_F5R2_FB29 CAN_F5R2_FB29_Msk /*!<Filter bit 29 */
4880 #define CAN_F5R2_FB30_Pos (30U)
4881 #define CAN_F5R2_FB30_Msk (0x1U << CAN_F5R2_FB30_Pos) /*!< 0x40000000 */
4882 #define CAN_F5R2_FB30 CAN_F5R2_FB30_Msk /*!<Filter bit 30 */
4883 #define CAN_F5R2_FB31_Pos (31U)
4884 #define CAN_F5R2_FB31_Msk (0x1U << CAN_F5R2_FB31_Pos) /*!< 0x80000000 */
4885 #define CAN_F5R2_FB31 CAN_F5R2_FB31_Msk /*!<Filter bit 31 */
4886
4887 /******************* Bit definition for CAN_F6R2 register *******************/
4888 #define CAN_F6R2_FB0_Pos (0U)
4889 #define CAN_F6R2_FB0_Msk (0x1U << CAN_F6R2_FB0_Pos) /*!< 0x00000001 */
4890 #define CAN_F6R2_FB0 CAN_F6R2_FB0_Msk /*!<Filter bit 0 */
4891 #define CAN_F6R2_FB1_Pos (1U)
4892 #define CAN_F6R2_FB1_Msk (0x1U << CAN_F6R2_FB1_Pos) /*!< 0x00000002 */
4893 #define CAN_F6R2_FB1 CAN_F6R2_FB1_Msk /*!<Filter bit 1 */
4894 #define CAN_F6R2_FB2_Pos (2U)
4895 #define CAN_F6R2_FB2_Msk (0x1U << CAN_F6R2_FB2_Pos) /*!< 0x00000004 */
4896 #define CAN_F6R2_FB2 CAN_F6R2_FB2_Msk /*!<Filter bit 2 */
4897 #define CAN_F6R2_FB3_Pos (3U)
4898 #define CAN_F6R2_FB3_Msk (0x1U << CAN_F6R2_FB3_Pos) /*!< 0x00000008 */
4899 #define CAN_F6R2_FB3 CAN_F6R2_FB3_Msk /*!<Filter bit 3 */
4900 #define CAN_F6R2_FB4_Pos (4U)
4901 #define CAN_F6R2_FB4_Msk (0x1U << CAN_F6R2_FB4_Pos) /*!< 0x00000010 */
4902 #define CAN_F6R2_FB4 CAN_F6R2_FB4_Msk /*!<Filter bit 4 */
4903 #define CAN_F6R2_FB5_Pos (5U)
4904 #define CAN_F6R2_FB5_Msk (0x1U << CAN_F6R2_FB5_Pos) /*!< 0x00000020 */
4905 #define CAN_F6R2_FB5 CAN_F6R2_FB5_Msk /*!<Filter bit 5 */
4906 #define CAN_F6R2_FB6_Pos (6U)
4907 #define CAN_F6R2_FB6_Msk (0x1U << CAN_F6R2_FB6_Pos) /*!< 0x00000040 */
4908 #define CAN_F6R2_FB6 CAN_F6R2_FB6_Msk /*!<Filter bit 6 */
4909 #define CAN_F6R2_FB7_Pos (7U)
4910 #define CAN_F6R2_FB7_Msk (0x1U << CAN_F6R2_FB7_Pos) /*!< 0x00000080 */
4911 #define CAN_F6R2_FB7 CAN_F6R2_FB7_Msk /*!<Filter bit 7 */
4912 #define CAN_F6R2_FB8_Pos (8U)
4913 #define CAN_F6R2_FB8_Msk (0x1U << CAN_F6R2_FB8_Pos) /*!< 0x00000100 */
4914 #define CAN_F6R2_FB8 CAN_F6R2_FB8_Msk /*!<Filter bit 8 */
4915 #define CAN_F6R2_FB9_Pos (9U)
4916 #define CAN_F6R2_FB9_Msk (0x1U << CAN_F6R2_FB9_Pos) /*!< 0x00000200 */
4917 #define CAN_F6R2_FB9 CAN_F6R2_FB9_Msk /*!<Filter bit 9 */
4918 #define CAN_F6R2_FB10_Pos (10U)
4919 #define CAN_F6R2_FB10_Msk (0x1U << CAN_F6R2_FB10_Pos) /*!< 0x00000400 */
4920 #define CAN_F6R2_FB10 CAN_F6R2_FB10_Msk /*!<Filter bit 10 */
4921 #define CAN_F6R2_FB11_Pos (11U)
4922 #define CAN_F6R2_FB11_Msk (0x1U << CAN_F6R2_FB11_Pos) /*!< 0x00000800 */
4923 #define CAN_F6R2_FB11 CAN_F6R2_FB11_Msk /*!<Filter bit 11 */
4924 #define CAN_F6R2_FB12_Pos (12U)
4925 #define CAN_F6R2_FB12_Msk (0x1U << CAN_F6R2_FB12_Pos) /*!< 0x00001000 */
4926 #define CAN_F6R2_FB12 CAN_F6R2_FB12_Msk /*!<Filter bit 12 */
4927 #define CAN_F6R2_FB13_Pos (13U)
4928 #define CAN_F6R2_FB13_Msk (0x1U << CAN_F6R2_FB13_Pos) /*!< 0x00002000 */
4929 #define CAN_F6R2_FB13 CAN_F6R2_FB13_Msk /*!<Filter bit 13 */
4930 #define CAN_F6R2_FB14_Pos (14U)
4931 #define CAN_F6R2_FB14_Msk (0x1U << CAN_F6R2_FB14_Pos) /*!< 0x00004000 */
4932 #define CAN_F6R2_FB14 CAN_F6R2_FB14_Msk /*!<Filter bit 14 */
4933 #define CAN_F6R2_FB15_Pos (15U)
4934 #define CAN_F6R2_FB15_Msk (0x1U << CAN_F6R2_FB15_Pos) /*!< 0x00008000 */
4935 #define CAN_F6R2_FB15 CAN_F6R2_FB15_Msk /*!<Filter bit 15 */
4936 #define CAN_F6R2_FB16_Pos (16U)
4937 #define CAN_F6R2_FB16_Msk (0x1U << CAN_F6R2_FB16_Pos) /*!< 0x00010000 */
4938 #define CAN_F6R2_FB16 CAN_F6R2_FB16_Msk /*!<Filter bit 16 */
4939 #define CAN_F6R2_FB17_Pos (17U)
4940 #define CAN_F6R2_FB17_Msk (0x1U << CAN_F6R2_FB17_Pos) /*!< 0x00020000 */
4941 #define CAN_F6R2_FB17 CAN_F6R2_FB17_Msk /*!<Filter bit 17 */
4942 #define CAN_F6R2_FB18_Pos (18U)
4943 #define CAN_F6R2_FB18_Msk (0x1U << CAN_F6R2_FB18_Pos) /*!< 0x00040000 */
4944 #define CAN_F6R2_FB18 CAN_F6R2_FB18_Msk /*!<Filter bit 18 */
4945 #define CAN_F6R2_FB19_Pos (19U)
4946 #define CAN_F6R2_FB19_Msk (0x1U << CAN_F6R2_FB19_Pos) /*!< 0x00080000 */
4947 #define CAN_F6R2_FB19 CAN_F6R2_FB19_Msk /*!<Filter bit 19 */
4948 #define CAN_F6R2_FB20_Pos (20U)
4949 #define CAN_F6R2_FB20_Msk (0x1U << CAN_F6R2_FB20_Pos) /*!< 0x00100000 */
4950 #define CAN_F6R2_FB20 CAN_F6R2_FB20_Msk /*!<Filter bit 20 */
4951 #define CAN_F6R2_FB21_Pos (21U)
4952 #define CAN_F6R2_FB21_Msk (0x1U << CAN_F6R2_FB21_Pos) /*!< 0x00200000 */
4953 #define CAN_F6R2_FB21 CAN_F6R2_FB21_Msk /*!<Filter bit 21 */
4954 #define CAN_F6R2_FB22_Pos (22U)
4955 #define CAN_F6R2_FB22_Msk (0x1U << CAN_F6R2_FB22_Pos) /*!< 0x00400000 */
4956 #define CAN_F6R2_FB22 CAN_F6R2_FB22_Msk /*!<Filter bit 22 */
4957 #define CAN_F6R2_FB23_Pos (23U)
4958 #define CAN_F6R2_FB23_Msk (0x1U << CAN_F6R2_FB23_Pos) /*!< 0x00800000 */
4959 #define CAN_F6R2_FB23 CAN_F6R2_FB23_Msk /*!<Filter bit 23 */
4960 #define CAN_F6R2_FB24_Pos (24U)
4961 #define CAN_F6R2_FB24_Msk (0x1U << CAN_F6R2_FB24_Pos) /*!< 0x01000000 */
4962 #define CAN_F6R2_FB24 CAN_F6R2_FB24_Msk /*!<Filter bit 24 */
4963 #define CAN_F6R2_FB25_Pos (25U)
4964 #define CAN_F6R2_FB25_Msk (0x1U << CAN_F6R2_FB25_Pos) /*!< 0x02000000 */
4965 #define CAN_F6R2_FB25 CAN_F6R2_FB25_Msk /*!<Filter bit 25 */
4966 #define CAN_F6R2_FB26_Pos (26U)
4967 #define CAN_F6R2_FB26_Msk (0x1U << CAN_F6R2_FB26_Pos) /*!< 0x04000000 */
4968 #define CAN_F6R2_FB26 CAN_F6R2_FB26_Msk /*!<Filter bit 26 */
4969 #define CAN_F6R2_FB27_Pos (27U)
4970 #define CAN_F6R2_FB27_Msk (0x1U << CAN_F6R2_FB27_Pos) /*!< 0x08000000 */
4971 #define CAN_F6R2_FB27 CAN_F6R2_FB27_Msk /*!<Filter bit 27 */
4972 #define CAN_F6R2_FB28_Pos (28U)
4973 #define CAN_F6R2_FB28_Msk (0x1U << CAN_F6R2_FB28_Pos) /*!< 0x10000000 */
4974 #define CAN_F6R2_FB28 CAN_F6R2_FB28_Msk /*!<Filter bit 28 */
4975 #define CAN_F6R2_FB29_Pos (29U)
4976 #define CAN_F6R2_FB29_Msk (0x1U << CAN_F6R2_FB29_Pos) /*!< 0x20000000 */
4977 #define CAN_F6R2_FB29 CAN_F6R2_FB29_Msk /*!<Filter bit 29 */
4978 #define CAN_F6R2_FB30_Pos (30U)
4979 #define CAN_F6R2_FB30_Msk (0x1U << CAN_F6R2_FB30_Pos) /*!< 0x40000000 */
4980 #define CAN_F6R2_FB30 CAN_F6R2_FB30_Msk /*!<Filter bit 30 */
4981 #define CAN_F6R2_FB31_Pos (31U)
4982 #define CAN_F6R2_FB31_Msk (0x1U << CAN_F6R2_FB31_Pos) /*!< 0x80000000 */
4983 #define CAN_F6R2_FB31 CAN_F6R2_FB31_Msk /*!<Filter bit 31 */
4984
4985 /******************* Bit definition for CAN_F7R2 register *******************/
4986 #define CAN_F7R2_FB0_Pos (0U)
4987 #define CAN_F7R2_FB0_Msk (0x1U << CAN_F7R2_FB0_Pos) /*!< 0x00000001 */
4988 #define CAN_F7R2_FB0 CAN_F7R2_FB0_Msk /*!<Filter bit 0 */
4989 #define CAN_F7R2_FB1_Pos (1U)
4990 #define CAN_F7R2_FB1_Msk (0x1U << CAN_F7R2_FB1_Pos) /*!< 0x00000002 */
4991 #define CAN_F7R2_FB1 CAN_F7R2_FB1_Msk /*!<Filter bit 1 */
4992 #define CAN_F7R2_FB2_Pos (2U)
4993 #define CAN_F7R2_FB2_Msk (0x1U << CAN_F7R2_FB2_Pos) /*!< 0x00000004 */
4994 #define CAN_F7R2_FB2 CAN_F7R2_FB2_Msk /*!<Filter bit 2 */
4995 #define CAN_F7R2_FB3_Pos (3U)
4996 #define CAN_F7R2_FB3_Msk (0x1U << CAN_F7R2_FB3_Pos) /*!< 0x00000008 */
4997 #define CAN_F7R2_FB3 CAN_F7R2_FB3_Msk /*!<Filter bit 3 */
4998 #define CAN_F7R2_FB4_Pos (4U)
4999 #define CAN_F7R2_FB4_Msk (0x1U << CAN_F7R2_FB4_Pos) /*!< 0x00000010 */
5000 #define CAN_F7R2_FB4 CAN_F7R2_FB4_Msk /*!<Filter bit 4 */
5001 #define CAN_F7R2_FB5_Pos (5U)
5002 #define CAN_F7R2_FB5_Msk (0x1U << CAN_F7R2_FB5_Pos) /*!< 0x00000020 */
5003 #define CAN_F7R2_FB5 CAN_F7R2_FB5_Msk /*!<Filter bit 5 */
5004 #define CAN_F7R2_FB6_Pos (6U)
5005 #define CAN_F7R2_FB6_Msk (0x1U << CAN_F7R2_FB6_Pos) /*!< 0x00000040 */
5006 #define CAN_F7R2_FB6 CAN_F7R2_FB6_Msk /*!<Filter bit 6 */
5007 #define CAN_F7R2_FB7_Pos (7U)
5008 #define CAN_F7R2_FB7_Msk (0x1U << CAN_F7R2_FB7_Pos) /*!< 0x00000080 */
5009 #define CAN_F7R2_FB7 CAN_F7R2_FB7_Msk /*!<Filter bit 7 */
5010 #define CAN_F7R2_FB8_Pos (8U)
5011 #define CAN_F7R2_FB8_Msk (0x1U << CAN_F7R2_FB8_Pos) /*!< 0x00000100 */
5012 #define CAN_F7R2_FB8 CAN_F7R2_FB8_Msk /*!<Filter bit 8 */
5013 #define CAN_F7R2_FB9_Pos (9U)
5014 #define CAN_F7R2_FB9_Msk (0x1U << CAN_F7R2_FB9_Pos) /*!< 0x00000200 */
5015 #define CAN_F7R2_FB9 CAN_F7R2_FB9_Msk /*!<Filter bit 9 */
5016 #define CAN_F7R2_FB10_Pos (10U)
5017 #define CAN_F7R2_FB10_Msk (0x1U << CAN_F7R2_FB10_Pos) /*!< 0x00000400 */
5018 #define CAN_F7R2_FB10 CAN_F7R2_FB10_Msk /*!<Filter bit 10 */
5019 #define CAN_F7R2_FB11_Pos (11U)
5020 #define CAN_F7R2_FB11_Msk (0x1U << CAN_F7R2_FB11_Pos) /*!< 0x00000800 */
5021 #define CAN_F7R2_FB11 CAN_F7R2_FB11_Msk /*!<Filter bit 11 */
5022 #define CAN_F7R2_FB12_Pos (12U)
5023 #define CAN_F7R2_FB12_Msk (0x1U << CAN_F7R2_FB12_Pos) /*!< 0x00001000 */
5024 #define CAN_F7R2_FB12 CAN_F7R2_FB12_Msk /*!<Filter bit 12 */
5025 #define CAN_F7R2_FB13_Pos (13U)
5026 #define CAN_F7R2_FB13_Msk (0x1U << CAN_F7R2_FB13_Pos) /*!< 0x00002000 */
5027 #define CAN_F7R2_FB13 CAN_F7R2_FB13_Msk /*!<Filter bit 13 */
5028 #define CAN_F7R2_FB14_Pos (14U)
5029 #define CAN_F7R2_FB14_Msk (0x1U << CAN_F7R2_FB14_Pos) /*!< 0x00004000 */
5030 #define CAN_F7R2_FB14 CAN_F7R2_FB14_Msk /*!<Filter bit 14 */
5031 #define CAN_F7R2_FB15_Pos (15U)
5032 #define CAN_F7R2_FB15_Msk (0x1U << CAN_F7R2_FB15_Pos) /*!< 0x00008000 */
5033 #define CAN_F7R2_FB15 CAN_F7R2_FB15_Msk /*!<Filter bit 15 */
5034 #define CAN_F7R2_FB16_Pos (16U)
5035 #define CAN_F7R2_FB16_Msk (0x1U << CAN_F7R2_FB16_Pos) /*!< 0x00010000 */
5036 #define CAN_F7R2_FB16 CAN_F7R2_FB16_Msk /*!<Filter bit 16 */
5037 #define CAN_F7R2_FB17_Pos (17U)
5038 #define CAN_F7R2_FB17_Msk (0x1U << CAN_F7R2_FB17_Pos) /*!< 0x00020000 */
5039 #define CAN_F7R2_FB17 CAN_F7R2_FB17_Msk /*!<Filter bit 17 */
5040 #define CAN_F7R2_FB18_Pos (18U)
5041 #define CAN_F7R2_FB18_Msk (0x1U << CAN_F7R2_FB18_Pos) /*!< 0x00040000 */
5042 #define CAN_F7R2_FB18 CAN_F7R2_FB18_Msk /*!<Filter bit 18 */
5043 #define CAN_F7R2_FB19_Pos (19U)
5044 #define CAN_F7R2_FB19_Msk (0x1U << CAN_F7R2_FB19_Pos) /*!< 0x00080000 */
5045 #define CAN_F7R2_FB19 CAN_F7R2_FB19_Msk /*!<Filter bit 19 */
5046 #define CAN_F7R2_FB20_Pos (20U)
5047 #define CAN_F7R2_FB20_Msk (0x1U << CAN_F7R2_FB20_Pos) /*!< 0x00100000 */
5048 #define CAN_F7R2_FB20 CAN_F7R2_FB20_Msk /*!<Filter bit 20 */
5049 #define CAN_F7R2_FB21_Pos (21U)
5050 #define CAN_F7R2_FB21_Msk (0x1U << CAN_F7R2_FB21_Pos) /*!< 0x00200000 */
5051 #define CAN_F7R2_FB21 CAN_F7R2_FB21_Msk /*!<Filter bit 21 */
5052 #define CAN_F7R2_FB22_Pos (22U)
5053 #define CAN_F7R2_FB22_Msk (0x1U << CAN_F7R2_FB22_Pos) /*!< 0x00400000 */
5054 #define CAN_F7R2_FB22 CAN_F7R2_FB22_Msk /*!<Filter bit 22 */
5055 #define CAN_F7R2_FB23_Pos (23U)
5056 #define CAN_F7R2_FB23_Msk (0x1U << CAN_F7R2_FB23_Pos) /*!< 0x00800000 */
5057 #define CAN_F7R2_FB23 CAN_F7R2_FB23_Msk /*!<Filter bit 23 */
5058 #define CAN_F7R2_FB24_Pos (24U)
5059 #define CAN_F7R2_FB24_Msk (0x1U << CAN_F7R2_FB24_Pos) /*!< 0x01000000 */
5060 #define CAN_F7R2_FB24 CAN_F7R2_FB24_Msk /*!<Filter bit 24 */
5061 #define CAN_F7R2_FB25_Pos (25U)
5062 #define CAN_F7R2_FB25_Msk (0x1U << CAN_F7R2_FB25_Pos) /*!< 0x02000000 */
5063 #define CAN_F7R2_FB25 CAN_F7R2_FB25_Msk /*!<Filter bit 25 */
5064 #define CAN_F7R2_FB26_Pos (26U)
5065 #define CAN_F7R2_FB26_Msk (0x1U << CAN_F7R2_FB26_Pos) /*!< 0x04000000 */
5066 #define CAN_F7R2_FB26 CAN_F7R2_FB26_Msk /*!<Filter bit 26 */
5067 #define CAN_F7R2_FB27_Pos (27U)
5068 #define CAN_F7R2_FB27_Msk (0x1U << CAN_F7R2_FB27_Pos) /*!< 0x08000000 */
5069 #define CAN_F7R2_FB27 CAN_F7R2_FB27_Msk /*!<Filter bit 27 */
5070 #define CAN_F7R2_FB28_Pos (28U)
5071 #define CAN_F7R2_FB28_Msk (0x1U << CAN_F7R2_FB28_Pos) /*!< 0x10000000 */
5072 #define CAN_F7R2_FB28 CAN_F7R2_FB28_Msk /*!<Filter bit 28 */
5073 #define CAN_F7R2_FB29_Pos (29U)
5074 #define CAN_F7R2_FB29_Msk (0x1U << CAN_F7R2_FB29_Pos) /*!< 0x20000000 */
5075 #define CAN_F7R2_FB29 CAN_F7R2_FB29_Msk /*!<Filter bit 29 */
5076 #define CAN_F7R2_FB30_Pos (30U)
5077 #define CAN_F7R2_FB30_Msk (0x1U << CAN_F7R2_FB30_Pos) /*!< 0x40000000 */
5078 #define CAN_F7R2_FB30 CAN_F7R2_FB30_Msk /*!<Filter bit 30 */
5079 #define CAN_F7R2_FB31_Pos (31U)
5080 #define CAN_F7R2_FB31_Msk (0x1U << CAN_F7R2_FB31_Pos) /*!< 0x80000000 */
5081 #define CAN_F7R2_FB31 CAN_F7R2_FB31_Msk /*!<Filter bit 31 */
5082
5083 /******************* Bit definition for CAN_F8R2 register *******************/
5084 #define CAN_F8R2_FB0_Pos (0U)
5085 #define CAN_F8R2_FB0_Msk (0x1U << CAN_F8R2_FB0_Pos) /*!< 0x00000001 */
5086 #define CAN_F8R2_FB0 CAN_F8R2_FB0_Msk /*!<Filter bit 0 */
5087 #define CAN_F8R2_FB1_Pos (1U)
5088 #define CAN_F8R2_FB1_Msk (0x1U << CAN_F8R2_FB1_Pos) /*!< 0x00000002 */
5089 #define CAN_F8R2_FB1 CAN_F8R2_FB1_Msk /*!<Filter bit 1 */
5090 #define CAN_F8R2_FB2_Pos (2U)
5091 #define CAN_F8R2_FB2_Msk (0x1U << CAN_F8R2_FB2_Pos) /*!< 0x00000004 */
5092 #define CAN_F8R2_FB2 CAN_F8R2_FB2_Msk /*!<Filter bit 2 */
5093 #define CAN_F8R2_FB3_Pos (3U)
5094 #define CAN_F8R2_FB3_Msk (0x1U << CAN_F8R2_FB3_Pos) /*!< 0x00000008 */
5095 #define CAN_F8R2_FB3 CAN_F8R2_FB3_Msk /*!<Filter bit 3 */
5096 #define CAN_F8R2_FB4_Pos (4U)
5097 #define CAN_F8R2_FB4_Msk (0x1U << CAN_F8R2_FB4_Pos) /*!< 0x00000010 */
5098 #define CAN_F8R2_FB4 CAN_F8R2_FB4_Msk /*!<Filter bit 4 */
5099 #define CAN_F8R2_FB5_Pos (5U)
5100 #define CAN_F8R2_FB5_Msk (0x1U << CAN_F8R2_FB5_Pos) /*!< 0x00000020 */
5101 #define CAN_F8R2_FB5 CAN_F8R2_FB5_Msk /*!<Filter bit 5 */
5102 #define CAN_F8R2_FB6_Pos (6U)
5103 #define CAN_F8R2_FB6_Msk (0x1U << CAN_F8R2_FB6_Pos) /*!< 0x00000040 */
5104 #define CAN_F8R2_FB6 CAN_F8R2_FB6_Msk /*!<Filter bit 6 */
5105 #define CAN_F8R2_FB7_Pos (7U)
5106 #define CAN_F8R2_FB7_Msk (0x1U << CAN_F8R2_FB7_Pos) /*!< 0x00000080 */
5107 #define CAN_F8R2_FB7 CAN_F8R2_FB7_Msk /*!<Filter bit 7 */
5108 #define CAN_F8R2_FB8_Pos (8U)
5109 #define CAN_F8R2_FB8_Msk (0x1U << CAN_F8R2_FB8_Pos) /*!< 0x00000100 */
5110 #define CAN_F8R2_FB8 CAN_F8R2_FB8_Msk /*!<Filter bit 8 */
5111 #define CAN_F8R2_FB9_Pos (9U)
5112 #define CAN_F8R2_FB9_Msk (0x1U << CAN_F8R2_FB9_Pos) /*!< 0x00000200 */
5113 #define CAN_F8R2_FB9 CAN_F8R2_FB9_Msk /*!<Filter bit 9 */
5114 #define CAN_F8R2_FB10_Pos (10U)
5115 #define CAN_F8R2_FB10_Msk (0x1U << CAN_F8R2_FB10_Pos) /*!< 0x00000400 */
5116 #define CAN_F8R2_FB10 CAN_F8R2_FB10_Msk /*!<Filter bit 10 */
5117 #define CAN_F8R2_FB11_Pos (11U)
5118 #define CAN_F8R2_FB11_Msk (0x1U << CAN_F8R2_FB11_Pos) /*!< 0x00000800 */
5119 #define CAN_F8R2_FB11 CAN_F8R2_FB11_Msk /*!<Filter bit 11 */
5120 #define CAN_F8R2_FB12_Pos (12U)
5121 #define CAN_F8R2_FB12_Msk (0x1U << CAN_F8R2_FB12_Pos) /*!< 0x00001000 */
5122 #define CAN_F8R2_FB12 CAN_F8R2_FB12_Msk /*!<Filter bit 12 */
5123 #define CAN_F8R2_FB13_Pos (13U)
5124 #define CAN_F8R2_FB13_Msk (0x1U << CAN_F8R2_FB13_Pos) /*!< 0x00002000 */
5125 #define CAN_F8R2_FB13 CAN_F8R2_FB13_Msk /*!<Filter bit 13 */
5126 #define CAN_F8R2_FB14_Pos (14U)
5127 #define CAN_F8R2_FB14_Msk (0x1U << CAN_F8R2_FB14_Pos) /*!< 0x00004000 */
5128 #define CAN_F8R2_FB14 CAN_F8R2_FB14_Msk /*!<Filter bit 14 */
5129 #define CAN_F8R2_FB15_Pos (15U)
5130 #define CAN_F8R2_FB15_Msk (0x1U << CAN_F8R2_FB15_Pos) /*!< 0x00008000 */
5131 #define CAN_F8R2_FB15 CAN_F8R2_FB15_Msk /*!<Filter bit 15 */
5132 #define CAN_F8R2_FB16_Pos (16U)
5133 #define CAN_F8R2_FB16_Msk (0x1U << CAN_F8R2_FB16_Pos) /*!< 0x00010000 */
5134 #define CAN_F8R2_FB16 CAN_F8R2_FB16_Msk /*!<Filter bit 16 */
5135 #define CAN_F8R2_FB17_Pos (17U)
5136 #define CAN_F8R2_FB17_Msk (0x1U << CAN_F8R2_FB17_Pos) /*!< 0x00020000 */
5137 #define CAN_F8R2_FB17 CAN_F8R2_FB17_Msk /*!<Filter bit 17 */
5138 #define CAN_F8R2_FB18_Pos (18U)
5139 #define CAN_F8R2_FB18_Msk (0x1U << CAN_F8R2_FB18_Pos) /*!< 0x00040000 */
5140 #define CAN_F8R2_FB18 CAN_F8R2_FB18_Msk /*!<Filter bit 18 */
5141 #define CAN_F8R2_FB19_Pos (19U)
5142 #define CAN_F8R2_FB19_Msk (0x1U << CAN_F8R2_FB19_Pos) /*!< 0x00080000 */
5143 #define CAN_F8R2_FB19 CAN_F8R2_FB19_Msk /*!<Filter bit 19 */
5144 #define CAN_F8R2_FB20_Pos (20U)
5145 #define CAN_F8R2_FB20_Msk (0x1U << CAN_F8R2_FB20_Pos) /*!< 0x00100000 */
5146 #define CAN_F8R2_FB20 CAN_F8R2_FB20_Msk /*!<Filter bit 20 */
5147 #define CAN_F8R2_FB21_Pos (21U)
5148 #define CAN_F8R2_FB21_Msk (0x1U << CAN_F8R2_FB21_Pos) /*!< 0x00200000 */
5149 #define CAN_F8R2_FB21 CAN_F8R2_FB21_Msk /*!<Filter bit 21 */
5150 #define CAN_F8R2_FB22_Pos (22U)
5151 #define CAN_F8R2_FB22_Msk (0x1U << CAN_F8R2_FB22_Pos) /*!< 0x00400000 */
5152 #define CAN_F8R2_FB22 CAN_F8R2_FB22_Msk /*!<Filter bit 22 */
5153 #define CAN_F8R2_FB23_Pos (23U)
5154 #define CAN_F8R2_FB23_Msk (0x1U << CAN_F8R2_FB23_Pos) /*!< 0x00800000 */
5155 #define CAN_F8R2_FB23 CAN_F8R2_FB23_Msk /*!<Filter bit 23 */
5156 #define CAN_F8R2_FB24_Pos (24U)
5157 #define CAN_F8R2_FB24_Msk (0x1U << CAN_F8R2_FB24_Pos) /*!< 0x01000000 */
5158 #define CAN_F8R2_FB24 CAN_F8R2_FB24_Msk /*!<Filter bit 24 */
5159 #define CAN_F8R2_FB25_Pos (25U)
5160 #define CAN_F8R2_FB25_Msk (0x1U << CAN_F8R2_FB25_Pos) /*!< 0x02000000 */
5161 #define CAN_F8R2_FB25 CAN_F8R2_FB25_Msk /*!<Filter bit 25 */
5162 #define CAN_F8R2_FB26_Pos (26U)
5163 #define CAN_F8R2_FB26_Msk (0x1U << CAN_F8R2_FB26_Pos) /*!< 0x04000000 */
5164 #define CAN_F8R2_FB26 CAN_F8R2_FB26_Msk /*!<Filter bit 26 */
5165 #define CAN_F8R2_FB27_Pos (27U)
5166 #define CAN_F8R2_FB27_Msk (0x1U << CAN_F8R2_FB27_Pos) /*!< 0x08000000 */
5167 #define CAN_F8R2_FB27 CAN_F8R2_FB27_Msk /*!<Filter bit 27 */
5168 #define CAN_F8R2_FB28_Pos (28U)
5169 #define CAN_F8R2_FB28_Msk (0x1U << CAN_F8R2_FB28_Pos) /*!< 0x10000000 */
5170 #define CAN_F8R2_FB28 CAN_F8R2_FB28_Msk /*!<Filter bit 28 */
5171 #define CAN_F8R2_FB29_Pos (29U)
5172 #define CAN_F8R2_FB29_Msk (0x1U << CAN_F8R2_FB29_Pos) /*!< 0x20000000 */
5173 #define CAN_F8R2_FB29 CAN_F8R2_FB29_Msk /*!<Filter bit 29 */
5174 #define CAN_F8R2_FB30_Pos (30U)
5175 #define CAN_F8R2_FB30_Msk (0x1U << CAN_F8R2_FB30_Pos) /*!< 0x40000000 */
5176 #define CAN_F8R2_FB30 CAN_F8R2_FB30_Msk /*!<Filter bit 30 */
5177 #define CAN_F8R2_FB31_Pos (31U)
5178 #define CAN_F8R2_FB31_Msk (0x1U << CAN_F8R2_FB31_Pos) /*!< 0x80000000 */
5179 #define CAN_F8R2_FB31 CAN_F8R2_FB31_Msk /*!<Filter bit 31 */
5180
5181 /******************* Bit definition for CAN_F9R2 register *******************/
5182 #define CAN_F9R2_FB0_Pos (0U)
5183 #define CAN_F9R2_FB0_Msk (0x1U << CAN_F9R2_FB0_Pos) /*!< 0x00000001 */
5184 #define CAN_F9R2_FB0 CAN_F9R2_FB0_Msk /*!<Filter bit 0 */
5185 #define CAN_F9R2_FB1_Pos (1U)
5186 #define CAN_F9R2_FB1_Msk (0x1U << CAN_F9R2_FB1_Pos) /*!< 0x00000002 */
5187 #define CAN_F9R2_FB1 CAN_F9R2_FB1_Msk /*!<Filter bit 1 */
5188 #define CAN_F9R2_FB2_Pos (2U)
5189 #define CAN_F9R2_FB2_Msk (0x1U << CAN_F9R2_FB2_Pos) /*!< 0x00000004 */
5190 #define CAN_F9R2_FB2 CAN_F9R2_FB2_Msk /*!<Filter bit 2 */
5191 #define CAN_F9R2_FB3_Pos (3U)
5192 #define CAN_F9R2_FB3_Msk (0x1U << CAN_F9R2_FB3_Pos) /*!< 0x00000008 */
5193 #define CAN_F9R2_FB3 CAN_F9R2_FB3_Msk /*!<Filter bit 3 */
5194 #define CAN_F9R2_FB4_Pos (4U)
5195 #define CAN_F9R2_FB4_Msk (0x1U << CAN_F9R2_FB4_Pos) /*!< 0x00000010 */
5196 #define CAN_F9R2_FB4 CAN_F9R2_FB4_Msk /*!<Filter bit 4 */
5197 #define CAN_F9R2_FB5_Pos (5U)
5198 #define CAN_F9R2_FB5_Msk (0x1U << CAN_F9R2_FB5_Pos) /*!< 0x00000020 */
5199 #define CAN_F9R2_FB5 CAN_F9R2_FB5_Msk /*!<Filter bit 5 */
5200 #define CAN_F9R2_FB6_Pos (6U)
5201 #define CAN_F9R2_FB6_Msk (0x1U << CAN_F9R2_FB6_Pos) /*!< 0x00000040 */
5202 #define CAN_F9R2_FB6 CAN_F9R2_FB6_Msk /*!<Filter bit 6 */
5203 #define CAN_F9R2_FB7_Pos (7U)
5204 #define CAN_F9R2_FB7_Msk (0x1U << CAN_F9R2_FB7_Pos) /*!< 0x00000080 */
5205 #define CAN_F9R2_FB7 CAN_F9R2_FB7_Msk /*!<Filter bit 7 */
5206 #define CAN_F9R2_FB8_Pos (8U)
5207 #define CAN_F9R2_FB8_Msk (0x1U << CAN_F9R2_FB8_Pos) /*!< 0x00000100 */
5208 #define CAN_F9R2_FB8 CAN_F9R2_FB8_Msk /*!<Filter bit 8 */
5209 #define CAN_F9R2_FB9_Pos (9U)
5210 #define CAN_F9R2_FB9_Msk (0x1U << CAN_F9R2_FB9_Pos) /*!< 0x00000200 */
5211 #define CAN_F9R2_FB9 CAN_F9R2_FB9_Msk /*!<Filter bit 9 */
5212 #define CAN_F9R2_FB10_Pos (10U)
5213 #define CAN_F9R2_FB10_Msk (0x1U << CAN_F9R2_FB10_Pos) /*!< 0x00000400 */
5214 #define CAN_F9R2_FB10 CAN_F9R2_FB10_Msk /*!<Filter bit 10 */
5215 #define CAN_F9R2_FB11_Pos (11U)
5216 #define CAN_F9R2_FB11_Msk (0x1U << CAN_F9R2_FB11_Pos) /*!< 0x00000800 */
5217 #define CAN_F9R2_FB11 CAN_F9R2_FB11_Msk /*!<Filter bit 11 */
5218 #define CAN_F9R2_FB12_Pos (12U)
5219 #define CAN_F9R2_FB12_Msk (0x1U << CAN_F9R2_FB12_Pos) /*!< 0x00001000 */
5220 #define CAN_F9R2_FB12 CAN_F9R2_FB12_Msk /*!<Filter bit 12 */
5221 #define CAN_F9R2_FB13_Pos (13U)
5222 #define CAN_F9R2_FB13_Msk (0x1U << CAN_F9R2_FB13_Pos) /*!< 0x00002000 */
5223 #define CAN_F9R2_FB13 CAN_F9R2_FB13_Msk /*!<Filter bit 13 */
5224 #define CAN_F9R2_FB14_Pos (14U)
5225 #define CAN_F9R2_FB14_Msk (0x1U << CAN_F9R2_FB14_Pos) /*!< 0x00004000 */
5226 #define CAN_F9R2_FB14 CAN_F9R2_FB14_Msk /*!<Filter bit 14 */
5227 #define CAN_F9R2_FB15_Pos (15U)
5228 #define CAN_F9R2_FB15_Msk (0x1U << CAN_F9R2_FB15_Pos) /*!< 0x00008000 */
5229 #define CAN_F9R2_FB15 CAN_F9R2_FB15_Msk /*!<Filter bit 15 */
5230 #define CAN_F9R2_FB16_Pos (16U)
5231 #define CAN_F9R2_FB16_Msk (0x1U << CAN_F9R2_FB16_Pos) /*!< 0x00010000 */
5232 #define CAN_F9R2_FB16 CAN_F9R2_FB16_Msk /*!<Filter bit 16 */
5233 #define CAN_F9R2_FB17_Pos (17U)
5234 #define CAN_F9R2_FB17_Msk (0x1U << CAN_F9R2_FB17_Pos) /*!< 0x00020000 */
5235 #define CAN_F9R2_FB17 CAN_F9R2_FB17_Msk /*!<Filter bit 17 */
5236 #define CAN_F9R2_FB18_Pos (18U)
5237 #define CAN_F9R2_FB18_Msk (0x1U << CAN_F9R2_FB18_Pos) /*!< 0x00040000 */
5238 #define CAN_F9R2_FB18 CAN_F9R2_FB18_Msk /*!<Filter bit 18 */
5239 #define CAN_F9R2_FB19_Pos (19U)
5240 #define CAN_F9R2_FB19_Msk (0x1U << CAN_F9R2_FB19_Pos) /*!< 0x00080000 */
5241 #define CAN_F9R2_FB19 CAN_F9R2_FB19_Msk /*!<Filter bit 19 */
5242 #define CAN_F9R2_FB20_Pos (20U)
5243 #define CAN_F9R2_FB20_Msk (0x1U << CAN_F9R2_FB20_Pos) /*!< 0x00100000 */
5244 #define CAN_F9R2_FB20 CAN_F9R2_FB20_Msk /*!<Filter bit 20 */
5245 #define CAN_F9R2_FB21_Pos (21U)
5246 #define CAN_F9R2_FB21_Msk (0x1U << CAN_F9R2_FB21_Pos) /*!< 0x00200000 */
5247 #define CAN_F9R2_FB21 CAN_F9R2_FB21_Msk /*!<Filter bit 21 */
5248 #define CAN_F9R2_FB22_Pos (22U)
5249 #define CAN_F9R2_FB22_Msk (0x1U << CAN_F9R2_FB22_Pos) /*!< 0x00400000 */
5250 #define CAN_F9R2_FB22 CAN_F9R2_FB22_Msk /*!<Filter bit 22 */
5251 #define CAN_F9R2_FB23_Pos (23U)
5252 #define CAN_F9R2_FB23_Msk (0x1U << CAN_F9R2_FB23_Pos) /*!< 0x00800000 */
5253 #define CAN_F9R2_FB23 CAN_F9R2_FB23_Msk /*!<Filter bit 23 */
5254 #define CAN_F9R2_FB24_Pos (24U)
5255 #define CAN_F9R2_FB24_Msk (0x1U << CAN_F9R2_FB24_Pos) /*!< 0x01000000 */
5256 #define CAN_F9R2_FB24 CAN_F9R2_FB24_Msk /*!<Filter bit 24 */
5257 #define CAN_F9R2_FB25_Pos (25U)
5258 #define CAN_F9R2_FB25_Msk (0x1U << CAN_F9R2_FB25_Pos) /*!< 0x02000000 */
5259 #define CAN_F9R2_FB25 CAN_F9R2_FB25_Msk /*!<Filter bit 25 */
5260 #define CAN_F9R2_FB26_Pos (26U)
5261 #define CAN_F9R2_FB26_Msk (0x1U << CAN_F9R2_FB26_Pos) /*!< 0x04000000 */
5262 #define CAN_F9R2_FB26 CAN_F9R2_FB26_Msk /*!<Filter bit 26 */
5263 #define CAN_F9R2_FB27_Pos (27U)
5264 #define CAN_F9R2_FB27_Msk (0x1U << CAN_F9R2_FB27_Pos) /*!< 0x08000000 */
5265 #define CAN_F9R2_FB27 CAN_F9R2_FB27_Msk /*!<Filter bit 27 */
5266 #define CAN_F9R2_FB28_Pos (28U)
5267 #define CAN_F9R2_FB28_Msk (0x1U << CAN_F9R2_FB28_Pos) /*!< 0x10000000 */
5268 #define CAN_F9R2_FB28 CAN_F9R2_FB28_Msk /*!<Filter bit 28 */
5269 #define CAN_F9R2_FB29_Pos (29U)
5270 #define CAN_F9R2_FB29_Msk (0x1U << CAN_F9R2_FB29_Pos) /*!< 0x20000000 */
5271 #define CAN_F9R2_FB29 CAN_F9R2_FB29_Msk /*!<Filter bit 29 */
5272 #define CAN_F9R2_FB30_Pos (30U)
5273 #define CAN_F9R2_FB30_Msk (0x1U << CAN_F9R2_FB30_Pos) /*!< 0x40000000 */
5274 #define CAN_F9R2_FB30 CAN_F9R2_FB30_Msk /*!<Filter bit 30 */
5275 #define CAN_F9R2_FB31_Pos (31U)
5276 #define CAN_F9R2_FB31_Msk (0x1U << CAN_F9R2_FB31_Pos) /*!< 0x80000000 */
5277 #define CAN_F9R2_FB31 CAN_F9R2_FB31_Msk /*!<Filter bit 31 */
5278
5279 /******************* Bit definition for CAN_F10R2 register ******************/
5280 #define CAN_F10R2_FB0_Pos (0U)
5281 #define CAN_F10R2_FB0_Msk (0x1U << CAN_F10R2_FB0_Pos) /*!< 0x00000001 */
5282 #define CAN_F10R2_FB0 CAN_F10R2_FB0_Msk /*!<Filter bit 0 */
5283 #define CAN_F10R2_FB1_Pos (1U)
5284 #define CAN_F10R2_FB1_Msk (0x1U << CAN_F10R2_FB1_Pos) /*!< 0x00000002 */
5285 #define CAN_F10R2_FB1 CAN_F10R2_FB1_Msk /*!<Filter bit 1 */
5286 #define CAN_F10R2_FB2_Pos (2U)
5287 #define CAN_F10R2_FB2_Msk (0x1U << CAN_F10R2_FB2_Pos) /*!< 0x00000004 */
5288 #define CAN_F10R2_FB2 CAN_F10R2_FB2_Msk /*!<Filter bit 2 */
5289 #define CAN_F10R2_FB3_Pos (3U)
5290 #define CAN_F10R2_FB3_Msk (0x1U << CAN_F10R2_FB3_Pos) /*!< 0x00000008 */
5291 #define CAN_F10R2_FB3 CAN_F10R2_FB3_Msk /*!<Filter bit 3 */
5292 #define CAN_F10R2_FB4_Pos (4U)
5293 #define CAN_F10R2_FB4_Msk (0x1U << CAN_F10R2_FB4_Pos) /*!< 0x00000010 */
5294 #define CAN_F10R2_FB4 CAN_F10R2_FB4_Msk /*!<Filter bit 4 */
5295 #define CAN_F10R2_FB5_Pos (5U)
5296 #define CAN_F10R2_FB5_Msk (0x1U << CAN_F10R2_FB5_Pos) /*!< 0x00000020 */
5297 #define CAN_F10R2_FB5 CAN_F10R2_FB5_Msk /*!<Filter bit 5 */
5298 #define CAN_F10R2_FB6_Pos (6U)
5299 #define CAN_F10R2_FB6_Msk (0x1U << CAN_F10R2_FB6_Pos) /*!< 0x00000040 */
5300 #define CAN_F10R2_FB6 CAN_F10R2_FB6_Msk /*!<Filter bit 6 */
5301 #define CAN_F10R2_FB7_Pos (7U)
5302 #define CAN_F10R2_FB7_Msk (0x1U << CAN_F10R2_FB7_Pos) /*!< 0x00000080 */
5303 #define CAN_F10R2_FB7 CAN_F10R2_FB7_Msk /*!<Filter bit 7 */
5304 #define CAN_F10R2_FB8_Pos (8U)
5305 #define CAN_F10R2_FB8_Msk (0x1U << CAN_F10R2_FB8_Pos) /*!< 0x00000100 */
5306 #define CAN_F10R2_FB8 CAN_F10R2_FB8_Msk /*!<Filter bit 8 */
5307 #define CAN_F10R2_FB9_Pos (9U)
5308 #define CAN_F10R2_FB9_Msk (0x1U << CAN_F10R2_FB9_Pos) /*!< 0x00000200 */
5309 #define CAN_F10R2_FB9 CAN_F10R2_FB9_Msk /*!<Filter bit 9 */
5310 #define CAN_F10R2_FB10_Pos (10U)
5311 #define CAN_F10R2_FB10_Msk (0x1U << CAN_F10R2_FB10_Pos) /*!< 0x00000400 */
5312 #define CAN_F10R2_FB10 CAN_F10R2_FB10_Msk /*!<Filter bit 10 */
5313 #define CAN_F10R2_FB11_Pos (11U)
5314 #define CAN_F10R2_FB11_Msk (0x1U << CAN_F10R2_FB11_Pos) /*!< 0x00000800 */
5315 #define CAN_F10R2_FB11 CAN_F10R2_FB11_Msk /*!<Filter bit 11 */
5316 #define CAN_F10R2_FB12_Pos (12U)
5317 #define CAN_F10R2_FB12_Msk (0x1U << CAN_F10R2_FB12_Pos) /*!< 0x00001000 */
5318 #define CAN_F10R2_FB12 CAN_F10R2_FB12_Msk /*!<Filter bit 12 */
5319 #define CAN_F10R2_FB13_Pos (13U)
5320 #define CAN_F10R2_FB13_Msk (0x1U << CAN_F10R2_FB13_Pos) /*!< 0x00002000 */
5321 #define CAN_F10R2_FB13 CAN_F10R2_FB13_Msk /*!<Filter bit 13 */
5322 #define CAN_F10R2_FB14_Pos (14U)
5323 #define CAN_F10R2_FB14_Msk (0x1U << CAN_F10R2_FB14_Pos) /*!< 0x00004000 */
5324 #define CAN_F10R2_FB14 CAN_F10R2_FB14_Msk /*!<Filter bit 14 */
5325 #define CAN_F10R2_FB15_Pos (15U)
5326 #define CAN_F10R2_FB15_Msk (0x1U << CAN_F10R2_FB15_Pos) /*!< 0x00008000 */
5327 #define CAN_F10R2_FB15 CAN_F10R2_FB15_Msk /*!<Filter bit 15 */
5328 #define CAN_F10R2_FB16_Pos (16U)
5329 #define CAN_F10R2_FB16_Msk (0x1U << CAN_F10R2_FB16_Pos) /*!< 0x00010000 */
5330 #define CAN_F10R2_FB16 CAN_F10R2_FB16_Msk /*!<Filter bit 16 */
5331 #define CAN_F10R2_FB17_Pos (17U)
5332 #define CAN_F10R2_FB17_Msk (0x1U << CAN_F10R2_FB17_Pos) /*!< 0x00020000 */
5333 #define CAN_F10R2_FB17 CAN_F10R2_FB17_Msk /*!<Filter bit 17 */
5334 #define CAN_F10R2_FB18_Pos (18U)
5335 #define CAN_F10R2_FB18_Msk (0x1U << CAN_F10R2_FB18_Pos) /*!< 0x00040000 */
5336 #define CAN_F10R2_FB18 CAN_F10R2_FB18_Msk /*!<Filter bit 18 */
5337 #define CAN_F10R2_FB19_Pos (19U)
5338 #define CAN_F10R2_FB19_Msk (0x1U << CAN_F10R2_FB19_Pos) /*!< 0x00080000 */
5339 #define CAN_F10R2_FB19 CAN_F10R2_FB19_Msk /*!<Filter bit 19 */
5340 #define CAN_F10R2_FB20_Pos (20U)
5341 #define CAN_F10R2_FB20_Msk (0x1U << CAN_F10R2_FB20_Pos) /*!< 0x00100000 */
5342 #define CAN_F10R2_FB20 CAN_F10R2_FB20_Msk /*!<Filter bit 20 */
5343 #define CAN_F10R2_FB21_Pos (21U)
5344 #define CAN_F10R2_FB21_Msk (0x1U << CAN_F10R2_FB21_Pos) /*!< 0x00200000 */
5345 #define CAN_F10R2_FB21 CAN_F10R2_FB21_Msk /*!<Filter bit 21 */
5346 #define CAN_F10R2_FB22_Pos (22U)
5347 #define CAN_F10R2_FB22_Msk (0x1U << CAN_F10R2_FB22_Pos) /*!< 0x00400000 */
5348 #define CAN_F10R2_FB22 CAN_F10R2_FB22_Msk /*!<Filter bit 22 */
5349 #define CAN_F10R2_FB23_Pos (23U)
5350 #define CAN_F10R2_FB23_Msk (0x1U << CAN_F10R2_FB23_Pos) /*!< 0x00800000 */
5351 #define CAN_F10R2_FB23 CAN_F10R2_FB23_Msk /*!<Filter bit 23 */
5352 #define CAN_F10R2_FB24_Pos (24U)
5353 #define CAN_F10R2_FB24_Msk (0x1U << CAN_F10R2_FB24_Pos) /*!< 0x01000000 */
5354 #define CAN_F10R2_FB24 CAN_F10R2_FB24_Msk /*!<Filter bit 24 */
5355 #define CAN_F10R2_FB25_Pos (25U)
5356 #define CAN_F10R2_FB25_Msk (0x1U << CAN_F10R2_FB25_Pos) /*!< 0x02000000 */
5357 #define CAN_F10R2_FB25 CAN_F10R2_FB25_Msk /*!<Filter bit 25 */
5358 #define CAN_F10R2_FB26_Pos (26U)
5359 #define CAN_F10R2_FB26_Msk (0x1U << CAN_F10R2_FB26_Pos) /*!< 0x04000000 */
5360 #define CAN_F10R2_FB26 CAN_F10R2_FB26_Msk /*!<Filter bit 26 */
5361 #define CAN_F10R2_FB27_Pos (27U)
5362 #define CAN_F10R2_FB27_Msk (0x1U << CAN_F10R2_FB27_Pos) /*!< 0x08000000 */
5363 #define CAN_F10R2_FB27 CAN_F10R2_FB27_Msk /*!<Filter bit 27 */
5364 #define CAN_F10R2_FB28_Pos (28U)
5365 #define CAN_F10R2_FB28_Msk (0x1U << CAN_F10R2_FB28_Pos) /*!< 0x10000000 */
5366 #define CAN_F10R2_FB28 CAN_F10R2_FB28_Msk /*!<Filter bit 28 */
5367 #define CAN_F10R2_FB29_Pos (29U)
5368 #define CAN_F10R2_FB29_Msk (0x1U << CAN_F10R2_FB29_Pos) /*!< 0x20000000 */
5369 #define CAN_F10R2_FB29 CAN_F10R2_FB29_Msk /*!<Filter bit 29 */
5370 #define CAN_F10R2_FB30_Pos (30U)
5371 #define CAN_F10R2_FB30_Msk (0x1U << CAN_F10R2_FB30_Pos) /*!< 0x40000000 */
5372 #define CAN_F10R2_FB30 CAN_F10R2_FB30_Msk /*!<Filter bit 30 */
5373 #define CAN_F10R2_FB31_Pos (31U)
5374 #define CAN_F10R2_FB31_Msk (0x1U << CAN_F10R2_FB31_Pos) /*!< 0x80000000 */
5375 #define CAN_F10R2_FB31 CAN_F10R2_FB31_Msk /*!<Filter bit 31 */
5376
5377 /******************* Bit definition for CAN_F11R2 register ******************/
5378 #define CAN_F11R2_FB0_Pos (0U)
5379 #define CAN_F11R2_FB0_Msk (0x1U << CAN_F11R2_FB0_Pos) /*!< 0x00000001 */
5380 #define CAN_F11R2_FB0 CAN_F11R2_FB0_Msk /*!<Filter bit 0 */
5381 #define CAN_F11R2_FB1_Pos (1U)
5382 #define CAN_F11R2_FB1_Msk (0x1U << CAN_F11R2_FB1_Pos) /*!< 0x00000002 */
5383 #define CAN_F11R2_FB1 CAN_F11R2_FB1_Msk /*!<Filter bit 1 */
5384 #define CAN_F11R2_FB2_Pos (2U)
5385 #define CAN_F11R2_FB2_Msk (0x1U << CAN_F11R2_FB2_Pos) /*!< 0x00000004 */
5386 #define CAN_F11R2_FB2 CAN_F11R2_FB2_Msk /*!<Filter bit 2 */
5387 #define CAN_F11R2_FB3_Pos (3U)
5388 #define CAN_F11R2_FB3_Msk (0x1U << CAN_F11R2_FB3_Pos) /*!< 0x00000008 */
5389 #define CAN_F11R2_FB3 CAN_F11R2_FB3_Msk /*!<Filter bit 3 */
5390 #define CAN_F11R2_FB4_Pos (4U)
5391 #define CAN_F11R2_FB4_Msk (0x1U << CAN_F11R2_FB4_Pos) /*!< 0x00000010 */
5392 #define CAN_F11R2_FB4 CAN_F11R2_FB4_Msk /*!<Filter bit 4 */
5393 #define CAN_F11R2_FB5_Pos (5U)
5394 #define CAN_F11R2_FB5_Msk (0x1U << CAN_F11R2_FB5_Pos) /*!< 0x00000020 */
5395 #define CAN_F11R2_FB5 CAN_F11R2_FB5_Msk /*!<Filter bit 5 */
5396 #define CAN_F11R2_FB6_Pos (6U)
5397 #define CAN_F11R2_FB6_Msk (0x1U << CAN_F11R2_FB6_Pos) /*!< 0x00000040 */
5398 #define CAN_F11R2_FB6 CAN_F11R2_FB6_Msk /*!<Filter bit 6 */
5399 #define CAN_F11R2_FB7_Pos (7U)
5400 #define CAN_F11R2_FB7_Msk (0x1U << CAN_F11R2_FB7_Pos) /*!< 0x00000080 */
5401 #define CAN_F11R2_FB7 CAN_F11R2_FB7_Msk /*!<Filter bit 7 */
5402 #define CAN_F11R2_FB8_Pos (8U)
5403 #define CAN_F11R2_FB8_Msk (0x1U << CAN_F11R2_FB8_Pos) /*!< 0x00000100 */
5404 #define CAN_F11R2_FB8 CAN_F11R2_FB8_Msk /*!<Filter bit 8 */
5405 #define CAN_F11R2_FB9_Pos (9U)
5406 #define CAN_F11R2_FB9_Msk (0x1U << CAN_F11R2_FB9_Pos) /*!< 0x00000200 */
5407 #define CAN_F11R2_FB9 CAN_F11R2_FB9_Msk /*!<Filter bit 9 */
5408 #define CAN_F11R2_FB10_Pos (10U)
5409 #define CAN_F11R2_FB10_Msk (0x1U << CAN_F11R2_FB10_Pos) /*!< 0x00000400 */
5410 #define CAN_F11R2_FB10 CAN_F11R2_FB10_Msk /*!<Filter bit 10 */
5411 #define CAN_F11R2_FB11_Pos (11U)
5412 #define CAN_F11R2_FB11_Msk (0x1U << CAN_F11R2_FB11_Pos) /*!< 0x00000800 */
5413 #define CAN_F11R2_FB11 CAN_F11R2_FB11_Msk /*!<Filter bit 11 */
5414 #define CAN_F11R2_FB12_Pos (12U)
5415 #define CAN_F11R2_FB12_Msk (0x1U << CAN_F11R2_FB12_Pos) /*!< 0x00001000 */
5416 #define CAN_F11R2_FB12 CAN_F11R2_FB12_Msk /*!<Filter bit 12 */
5417 #define CAN_F11R2_FB13_Pos (13U)
5418 #define CAN_F11R2_FB13_Msk (0x1U << CAN_F11R2_FB13_Pos) /*!< 0x00002000 */
5419 #define CAN_F11R2_FB13 CAN_F11R2_FB13_Msk /*!<Filter bit 13 */
5420 #define CAN_F11R2_FB14_Pos (14U)
5421 #define CAN_F11R2_FB14_Msk (0x1U << CAN_F11R2_FB14_Pos) /*!< 0x00004000 */
5422 #define CAN_F11R2_FB14 CAN_F11R2_FB14_Msk /*!<Filter bit 14 */
5423 #define CAN_F11R2_FB15_Pos (15U)
5424 #define CAN_F11R2_FB15_Msk (0x1U << CAN_F11R2_FB15_Pos) /*!< 0x00008000 */
5425 #define CAN_F11R2_FB15 CAN_F11R2_FB15_Msk /*!<Filter bit 15 */
5426 #define CAN_F11R2_FB16_Pos (16U)
5427 #define CAN_F11R2_FB16_Msk (0x1U << CAN_F11R2_FB16_Pos) /*!< 0x00010000 */
5428 #define CAN_F11R2_FB16 CAN_F11R2_FB16_Msk /*!<Filter bit 16 */
5429 #define CAN_F11R2_FB17_Pos (17U)
5430 #define CAN_F11R2_FB17_Msk (0x1U << CAN_F11R2_FB17_Pos) /*!< 0x00020000 */
5431 #define CAN_F11R2_FB17 CAN_F11R2_FB17_Msk /*!<Filter bit 17 */
5432 #define CAN_F11R2_FB18_Pos (18U)
5433 #define CAN_F11R2_FB18_Msk (0x1U << CAN_F11R2_FB18_Pos) /*!< 0x00040000 */
5434 #define CAN_F11R2_FB18 CAN_F11R2_FB18_Msk /*!<Filter bit 18 */
5435 #define CAN_F11R2_FB19_Pos (19U)
5436 #define CAN_F11R2_FB19_Msk (0x1U << CAN_F11R2_FB19_Pos) /*!< 0x00080000 */
5437 #define CAN_F11R2_FB19 CAN_F11R2_FB19_Msk /*!<Filter bit 19 */
5438 #define CAN_F11R2_FB20_Pos (20U)
5439 #define CAN_F11R2_FB20_Msk (0x1U << CAN_F11R2_FB20_Pos) /*!< 0x00100000 */
5440 #define CAN_F11R2_FB20 CAN_F11R2_FB20_Msk /*!<Filter bit 20 */
5441 #define CAN_F11R2_FB21_Pos (21U)
5442 #define CAN_F11R2_FB21_Msk (0x1U << CAN_F11R2_FB21_Pos) /*!< 0x00200000 */
5443 #define CAN_F11R2_FB21 CAN_F11R2_FB21_Msk /*!<Filter bit 21 */
5444 #define CAN_F11R2_FB22_Pos (22U)
5445 #define CAN_F11R2_FB22_Msk (0x1U << CAN_F11R2_FB22_Pos) /*!< 0x00400000 */
5446 #define CAN_F11R2_FB22 CAN_F11R2_FB22_Msk /*!<Filter bit 22 */
5447 #define CAN_F11R2_FB23_Pos (23U)
5448 #define CAN_F11R2_FB23_Msk (0x1U << CAN_F11R2_FB23_Pos) /*!< 0x00800000 */
5449 #define CAN_F11R2_FB23 CAN_F11R2_FB23_Msk /*!<Filter bit 23 */
5450 #define CAN_F11R2_FB24_Pos (24U)
5451 #define CAN_F11R2_FB24_Msk (0x1U << CAN_F11R2_FB24_Pos) /*!< 0x01000000 */
5452 #define CAN_F11R2_FB24 CAN_F11R2_FB24_Msk /*!<Filter bit 24 */
5453 #define CAN_F11R2_FB25_Pos (25U)
5454 #define CAN_F11R2_FB25_Msk (0x1U << CAN_F11R2_FB25_Pos) /*!< 0x02000000 */
5455 #define CAN_F11R2_FB25 CAN_F11R2_FB25_Msk /*!<Filter bit 25 */
5456 #define CAN_F11R2_FB26_Pos (26U)
5457 #define CAN_F11R2_FB26_Msk (0x1U << CAN_F11R2_FB26_Pos) /*!< 0x04000000 */
5458 #define CAN_F11R2_FB26 CAN_F11R2_FB26_Msk /*!<Filter bit 26 */
5459 #define CAN_F11R2_FB27_Pos (27U)
5460 #define CAN_F11R2_FB27_Msk (0x1U << CAN_F11R2_FB27_Pos) /*!< 0x08000000 */
5461 #define CAN_F11R2_FB27 CAN_F11R2_FB27_Msk /*!<Filter bit 27 */
5462 #define CAN_F11R2_FB28_Pos (28U)
5463 #define CAN_F11R2_FB28_Msk (0x1U << CAN_F11R2_FB28_Pos) /*!< 0x10000000 */
5464 #define CAN_F11R2_FB28 CAN_F11R2_FB28_Msk /*!<Filter bit 28 */
5465 #define CAN_F11R2_FB29_Pos (29U)
5466 #define CAN_F11R2_FB29_Msk (0x1U << CAN_F11R2_FB29_Pos) /*!< 0x20000000 */
5467 #define CAN_F11R2_FB29 CAN_F11R2_FB29_Msk /*!<Filter bit 29 */
5468 #define CAN_F11R2_FB30_Pos (30U)
5469 #define CAN_F11R2_FB30_Msk (0x1U << CAN_F11R2_FB30_Pos) /*!< 0x40000000 */
5470 #define CAN_F11R2_FB30 CAN_F11R2_FB30_Msk /*!<Filter bit 30 */
5471 #define CAN_F11R2_FB31_Pos (31U)
5472 #define CAN_F11R2_FB31_Msk (0x1U << CAN_F11R2_FB31_Pos) /*!< 0x80000000 */
5473 #define CAN_F11R2_FB31 CAN_F11R2_FB31_Msk /*!<Filter bit 31 */
5474
5475 /******************* Bit definition for CAN_F12R2 register ******************/
5476 #define CAN_F12R2_FB0_Pos (0U)
5477 #define CAN_F12R2_FB0_Msk (0x1U << CAN_F12R2_FB0_Pos) /*!< 0x00000001 */
5478 #define CAN_F12R2_FB0 CAN_F12R2_FB0_Msk /*!<Filter bit 0 */
5479 #define CAN_F12R2_FB1_Pos (1U)
5480 #define CAN_F12R2_FB1_Msk (0x1U << CAN_F12R2_FB1_Pos) /*!< 0x00000002 */
5481 #define CAN_F12R2_FB1 CAN_F12R2_FB1_Msk /*!<Filter bit 1 */
5482 #define CAN_F12R2_FB2_Pos (2U)
5483 #define CAN_F12R2_FB2_Msk (0x1U << CAN_F12R2_FB2_Pos) /*!< 0x00000004 */
5484 #define CAN_F12R2_FB2 CAN_F12R2_FB2_Msk /*!<Filter bit 2 */
5485 #define CAN_F12R2_FB3_Pos (3U)
5486 #define CAN_F12R2_FB3_Msk (0x1U << CAN_F12R2_FB3_Pos) /*!< 0x00000008 */
5487 #define CAN_F12R2_FB3 CAN_F12R2_FB3_Msk /*!<Filter bit 3 */
5488 #define CAN_F12R2_FB4_Pos (4U)
5489 #define CAN_F12R2_FB4_Msk (0x1U << CAN_F12R2_FB4_Pos) /*!< 0x00000010 */
5490 #define CAN_F12R2_FB4 CAN_F12R2_FB4_Msk /*!<Filter bit 4 */
5491 #define CAN_F12R2_FB5_Pos (5U)
5492 #define CAN_F12R2_FB5_Msk (0x1U << CAN_F12R2_FB5_Pos) /*!< 0x00000020 */
5493 #define CAN_F12R2_FB5 CAN_F12R2_FB5_Msk /*!<Filter bit 5 */
5494 #define CAN_F12R2_FB6_Pos (6U)
5495 #define CAN_F12R2_FB6_Msk (0x1U << CAN_F12R2_FB6_Pos) /*!< 0x00000040 */
5496 #define CAN_F12R2_FB6 CAN_F12R2_FB6_Msk /*!<Filter bit 6 */
5497 #define CAN_F12R2_FB7_Pos (7U)
5498 #define CAN_F12R2_FB7_Msk (0x1U << CAN_F12R2_FB7_Pos) /*!< 0x00000080 */
5499 #define CAN_F12R2_FB7 CAN_F12R2_FB7_Msk /*!<Filter bit 7 */
5500 #define CAN_F12R2_FB8_Pos (8U)
5501 #define CAN_F12R2_FB8_Msk (0x1U << CAN_F12R2_FB8_Pos) /*!< 0x00000100 */
5502 #define CAN_F12R2_FB8 CAN_F12R2_FB8_Msk /*!<Filter bit 8 */
5503 #define CAN_F12R2_FB9_Pos (9U)
5504 #define CAN_F12R2_FB9_Msk (0x1U << CAN_F12R2_FB9_Pos) /*!< 0x00000200 */
5505 #define CAN_F12R2_FB9 CAN_F12R2_FB9_Msk /*!<Filter bit 9 */
5506 #define CAN_F12R2_FB10_Pos (10U)
5507 #define CAN_F12R2_FB10_Msk (0x1U << CAN_F12R2_FB10_Pos) /*!< 0x00000400 */
5508 #define CAN_F12R2_FB10 CAN_F12R2_FB10_Msk /*!<Filter bit 10 */
5509 #define CAN_F12R2_FB11_Pos (11U)
5510 #define CAN_F12R2_FB11_Msk (0x1U << CAN_F12R2_FB11_Pos) /*!< 0x00000800 */
5511 #define CAN_F12R2_FB11 CAN_F12R2_FB11_Msk /*!<Filter bit 11 */
5512 #define CAN_F12R2_FB12_Pos (12U)
5513 #define CAN_F12R2_FB12_Msk (0x1U << CAN_F12R2_FB12_Pos) /*!< 0x00001000 */
5514 #define CAN_F12R2_FB12 CAN_F12R2_FB12_Msk /*!<Filter bit 12 */
5515 #define CAN_F12R2_FB13_Pos (13U)
5516 #define CAN_F12R2_FB13_Msk (0x1U << CAN_F12R2_FB13_Pos) /*!< 0x00002000 */
5517 #define CAN_F12R2_FB13 CAN_F12R2_FB13_Msk /*!<Filter bit 13 */
5518 #define CAN_F12R2_FB14_Pos (14U)
5519 #define CAN_F12R2_FB14_Msk (0x1U << CAN_F12R2_FB14_Pos) /*!< 0x00004000 */
5520 #define CAN_F12R2_FB14 CAN_F12R2_FB14_Msk /*!<Filter bit 14 */
5521 #define CAN_F12R2_FB15_Pos (15U)
5522 #define CAN_F12R2_FB15_Msk (0x1U << CAN_F12R2_FB15_Pos) /*!< 0x00008000 */
5523 #define CAN_F12R2_FB15 CAN_F12R2_FB15_Msk /*!<Filter bit 15 */
5524 #define CAN_F12R2_FB16_Pos (16U)
5525 #define CAN_F12R2_FB16_Msk (0x1U << CAN_F12R2_FB16_Pos) /*!< 0x00010000 */
5526 #define CAN_F12R2_FB16 CAN_F12R2_FB16_Msk /*!<Filter bit 16 */
5527 #define CAN_F12R2_FB17_Pos (17U)
5528 #define CAN_F12R2_FB17_Msk (0x1U << CAN_F12R2_FB17_Pos) /*!< 0x00020000 */
5529 #define CAN_F12R2_FB17 CAN_F12R2_FB17_Msk /*!<Filter bit 17 */
5530 #define CAN_F12R2_FB18_Pos (18U)
5531 #define CAN_F12R2_FB18_Msk (0x1U << CAN_F12R2_FB18_Pos) /*!< 0x00040000 */
5532 #define CAN_F12R2_FB18 CAN_F12R2_FB18_Msk /*!<Filter bit 18 */
5533 #define CAN_F12R2_FB19_Pos (19U)
5534 #define CAN_F12R2_FB19_Msk (0x1U << CAN_F12R2_FB19_Pos) /*!< 0x00080000 */
5535 #define CAN_F12R2_FB19 CAN_F12R2_FB19_Msk /*!<Filter bit 19 */
5536 #define CAN_F12R2_FB20_Pos (20U)
5537 #define CAN_F12R2_FB20_Msk (0x1U << CAN_F12R2_FB20_Pos) /*!< 0x00100000 */
5538 #define CAN_F12R2_FB20 CAN_F12R2_FB20_Msk /*!<Filter bit 20 */
5539 #define CAN_F12R2_FB21_Pos (21U)
5540 #define CAN_F12R2_FB21_Msk (0x1U << CAN_F12R2_FB21_Pos) /*!< 0x00200000 */
5541 #define CAN_F12R2_FB21 CAN_F12R2_FB21_Msk /*!<Filter bit 21 */
5542 #define CAN_F12R2_FB22_Pos (22U)
5543 #define CAN_F12R2_FB22_Msk (0x1U << CAN_F12R2_FB22_Pos) /*!< 0x00400000 */
5544 #define CAN_F12R2_FB22 CAN_F12R2_FB22_Msk /*!<Filter bit 22 */
5545 #define CAN_F12R2_FB23_Pos (23U)
5546 #define CAN_F12R2_FB23_Msk (0x1U << CAN_F12R2_FB23_Pos) /*!< 0x00800000 */
5547 #define CAN_F12R2_FB23 CAN_F12R2_FB23_Msk /*!<Filter bit 23 */
5548 #define CAN_F12R2_FB24_Pos (24U)
5549 #define CAN_F12R2_FB24_Msk (0x1U << CAN_F12R2_FB24_Pos) /*!< 0x01000000 */
5550 #define CAN_F12R2_FB24 CAN_F12R2_FB24_Msk /*!<Filter bit 24 */
5551 #define CAN_F12R2_FB25_Pos (25U)
5552 #define CAN_F12R2_FB25_Msk (0x1U << CAN_F12R2_FB25_Pos) /*!< 0x02000000 */
5553 #define CAN_F12R2_FB25 CAN_F12R2_FB25_Msk /*!<Filter bit 25 */
5554 #define CAN_F12R2_FB26_Pos (26U)
5555 #define CAN_F12R2_FB26_Msk (0x1U << CAN_F12R2_FB26_Pos) /*!< 0x04000000 */
5556 #define CAN_F12R2_FB26 CAN_F12R2_FB26_Msk /*!<Filter bit 26 */
5557 #define CAN_F12R2_FB27_Pos (27U)
5558 #define CAN_F12R2_FB27_Msk (0x1U << CAN_F12R2_FB27_Pos) /*!< 0x08000000 */
5559 #define CAN_F12R2_FB27 CAN_F12R2_FB27_Msk /*!<Filter bit 27 */
5560 #define CAN_F12R2_FB28_Pos (28U)
5561 #define CAN_F12R2_FB28_Msk (0x1U << CAN_F12R2_FB28_Pos) /*!< 0x10000000 */
5562 #define CAN_F12R2_FB28 CAN_F12R2_FB28_Msk /*!<Filter bit 28 */
5563 #define CAN_F12R2_FB29_Pos (29U)
5564 #define CAN_F12R2_FB29_Msk (0x1U << CAN_F12R2_FB29_Pos) /*!< 0x20000000 */
5565 #define CAN_F12R2_FB29 CAN_F12R2_FB29_Msk /*!<Filter bit 29 */
5566 #define CAN_F12R2_FB30_Pos (30U)
5567 #define CAN_F12R2_FB30_Msk (0x1U << CAN_F12R2_FB30_Pos) /*!< 0x40000000 */
5568 #define CAN_F12R2_FB30 CAN_F12R2_FB30_Msk /*!<Filter bit 30 */
5569 #define CAN_F12R2_FB31_Pos (31U)
5570 #define CAN_F12R2_FB31_Msk (0x1U << CAN_F12R2_FB31_Pos) /*!< 0x80000000 */
5571 #define CAN_F12R2_FB31 CAN_F12R2_FB31_Msk /*!<Filter bit 31 */
5572
5573 /******************* Bit definition for CAN_F13R2 register ******************/
5574 #define CAN_F13R2_FB0_Pos (0U)
5575 #define CAN_F13R2_FB0_Msk (0x1U << CAN_F13R2_FB0_Pos) /*!< 0x00000001 */
5576 #define CAN_F13R2_FB0 CAN_F13R2_FB0_Msk /*!<Filter bit 0 */
5577 #define CAN_F13R2_FB1_Pos (1U)
5578 #define CAN_F13R2_FB1_Msk (0x1U << CAN_F13R2_FB1_Pos) /*!< 0x00000002 */
5579 #define CAN_F13R2_FB1 CAN_F13R2_FB1_Msk /*!<Filter bit 1 */
5580 #define CAN_F13R2_FB2_Pos (2U)
5581 #define CAN_F13R2_FB2_Msk (0x1U << CAN_F13R2_FB2_Pos) /*!< 0x00000004 */
5582 #define CAN_F13R2_FB2 CAN_F13R2_FB2_Msk /*!<Filter bit 2 */
5583 #define CAN_F13R2_FB3_Pos (3U)
5584 #define CAN_F13R2_FB3_Msk (0x1U << CAN_F13R2_FB3_Pos) /*!< 0x00000008 */
5585 #define CAN_F13R2_FB3 CAN_F13R2_FB3_Msk /*!<Filter bit 3 */
5586 #define CAN_F13R2_FB4_Pos (4U)
5587 #define CAN_F13R2_FB4_Msk (0x1U << CAN_F13R2_FB4_Pos) /*!< 0x00000010 */
5588 #define CAN_F13R2_FB4 CAN_F13R2_FB4_Msk /*!<Filter bit 4 */
5589 #define CAN_F13R2_FB5_Pos (5U)
5590 #define CAN_F13R2_FB5_Msk (0x1U << CAN_F13R2_FB5_Pos) /*!< 0x00000020 */
5591 #define CAN_F13R2_FB5 CAN_F13R2_FB5_Msk /*!<Filter bit 5 */
5592 #define CAN_F13R2_FB6_Pos (6U)
5593 #define CAN_F13R2_FB6_Msk (0x1U << CAN_F13R2_FB6_Pos) /*!< 0x00000040 */
5594 #define CAN_F13R2_FB6 CAN_F13R2_FB6_Msk /*!<Filter bit 6 */
5595 #define CAN_F13R2_FB7_Pos (7U)
5596 #define CAN_F13R2_FB7_Msk (0x1U << CAN_F13R2_FB7_Pos) /*!< 0x00000080 */
5597 #define CAN_F13R2_FB7 CAN_F13R2_FB7_Msk /*!<Filter bit 7 */
5598 #define CAN_F13R2_FB8_Pos (8U)
5599 #define CAN_F13R2_FB8_Msk (0x1U << CAN_F13R2_FB8_Pos) /*!< 0x00000100 */
5600 #define CAN_F13R2_FB8 CAN_F13R2_FB8_Msk /*!<Filter bit 8 */
5601 #define CAN_F13R2_FB9_Pos (9U)
5602 #define CAN_F13R2_FB9_Msk (0x1U << CAN_F13R2_FB9_Pos) /*!< 0x00000200 */
5603 #define CAN_F13R2_FB9 CAN_F13R2_FB9_Msk /*!<Filter bit 9 */
5604 #define CAN_F13R2_FB10_Pos (10U)
5605 #define CAN_F13R2_FB10_Msk (0x1U << CAN_F13R2_FB10_Pos) /*!< 0x00000400 */
5606 #define CAN_F13R2_FB10 CAN_F13R2_FB10_Msk /*!<Filter bit 10 */
5607 #define CAN_F13R2_FB11_Pos (11U)
5608 #define CAN_F13R2_FB11_Msk (0x1U << CAN_F13R2_FB11_Pos) /*!< 0x00000800 */
5609 #define CAN_F13R2_FB11 CAN_F13R2_FB11_Msk /*!<Filter bit 11 */
5610 #define CAN_F13R2_FB12_Pos (12U)
5611 #define CAN_F13R2_FB12_Msk (0x1U << CAN_F13R2_FB12_Pos) /*!< 0x00001000 */
5612 #define CAN_F13R2_FB12 CAN_F13R2_FB12_Msk /*!<Filter bit 12 */
5613 #define CAN_F13R2_FB13_Pos (13U)
5614 #define CAN_F13R2_FB13_Msk (0x1U << CAN_F13R2_FB13_Pos) /*!< 0x00002000 */
5615 #define CAN_F13R2_FB13 CAN_F13R2_FB13_Msk /*!<Filter bit 13 */
5616 #define CAN_F13R2_FB14_Pos (14U)
5617 #define CAN_F13R2_FB14_Msk (0x1U << CAN_F13R2_FB14_Pos) /*!< 0x00004000 */
5618 #define CAN_F13R2_FB14 CAN_F13R2_FB14_Msk /*!<Filter bit 14 */
5619 #define CAN_F13R2_FB15_Pos (15U)
5620 #define CAN_F13R2_FB15_Msk (0x1U << CAN_F13R2_FB15_Pos) /*!< 0x00008000 */
5621 #define CAN_F13R2_FB15 CAN_F13R2_FB15_Msk /*!<Filter bit 15 */
5622 #define CAN_F13R2_FB16_Pos (16U)
5623 #define CAN_F13R2_FB16_Msk (0x1U << CAN_F13R2_FB16_Pos) /*!< 0x00010000 */
5624 #define CAN_F13R2_FB16 CAN_F13R2_FB16_Msk /*!<Filter bit 16 */
5625 #define CAN_F13R2_FB17_Pos (17U)
5626 #define CAN_F13R2_FB17_Msk (0x1U << CAN_F13R2_FB17_Pos) /*!< 0x00020000 */
5627 #define CAN_F13R2_FB17 CAN_F13R2_FB17_Msk /*!<Filter bit 17 */
5628 #define CAN_F13R2_FB18_Pos (18U)
5629 #define CAN_F13R2_FB18_Msk (0x1U << CAN_F13R2_FB18_Pos) /*!< 0x00040000 */
5630 #define CAN_F13R2_FB18 CAN_F13R2_FB18_Msk /*!<Filter bit 18 */
5631 #define CAN_F13R2_FB19_Pos (19U)
5632 #define CAN_F13R2_FB19_Msk (0x1U << CAN_F13R2_FB19_Pos) /*!< 0x00080000 */
5633 #define CAN_F13R2_FB19 CAN_F13R2_FB19_Msk /*!<Filter bit 19 */
5634 #define CAN_F13R2_FB20_Pos (20U)
5635 #define CAN_F13R2_FB20_Msk (0x1U << CAN_F13R2_FB20_Pos) /*!< 0x00100000 */
5636 #define CAN_F13R2_FB20 CAN_F13R2_FB20_Msk /*!<Filter bit 20 */
5637 #define CAN_F13R2_FB21_Pos (21U)
5638 #define CAN_F13R2_FB21_Msk (0x1U << CAN_F13R2_FB21_Pos) /*!< 0x00200000 */
5639 #define CAN_F13R2_FB21 CAN_F13R2_FB21_Msk /*!<Filter bit 21 */
5640 #define CAN_F13R2_FB22_Pos (22U)
5641 #define CAN_F13R2_FB22_Msk (0x1U << CAN_F13R2_FB22_Pos) /*!< 0x00400000 */
5642 #define CAN_F13R2_FB22 CAN_F13R2_FB22_Msk /*!<Filter bit 22 */
5643 #define CAN_F13R2_FB23_Pos (23U)
5644 #define CAN_F13R2_FB23_Msk (0x1U << CAN_F13R2_FB23_Pos) /*!< 0x00800000 */
5645 #define CAN_F13R2_FB23 CAN_F13R2_FB23_Msk /*!<Filter bit 23 */
5646 #define CAN_F13R2_FB24_Pos (24U)
5647 #define CAN_F13R2_FB24_Msk (0x1U << CAN_F13R2_FB24_Pos) /*!< 0x01000000 */
5648 #define CAN_F13R2_FB24 CAN_F13R2_FB24_Msk /*!<Filter bit 24 */
5649 #define CAN_F13R2_FB25_Pos (25U)
5650 #define CAN_F13R2_FB25_Msk (0x1U << CAN_F13R2_FB25_Pos) /*!< 0x02000000 */
5651 #define CAN_F13R2_FB25 CAN_F13R2_FB25_Msk /*!<Filter bit 25 */
5652 #define CAN_F13R2_FB26_Pos (26U)
5653 #define CAN_F13R2_FB26_Msk (0x1U << CAN_F13R2_FB26_Pos) /*!< 0x04000000 */
5654 #define CAN_F13R2_FB26 CAN_F13R2_FB26_Msk /*!<Filter bit 26 */
5655 #define CAN_F13R2_FB27_Pos (27U)
5656 #define CAN_F13R2_FB27_Msk (0x1U << CAN_F13R2_FB27_Pos) /*!< 0x08000000 */
5657 #define CAN_F13R2_FB27 CAN_F13R2_FB27_Msk /*!<Filter bit 27 */
5658 #define CAN_F13R2_FB28_Pos (28U)
5659 #define CAN_F13R2_FB28_Msk (0x1U << CAN_F13R2_FB28_Pos) /*!< 0x10000000 */
5660 #define CAN_F13R2_FB28 CAN_F13R2_FB28_Msk /*!<Filter bit 28 */
5661 #define CAN_F13R2_FB29_Pos (29U)
5662 #define CAN_F13R2_FB29_Msk (0x1U << CAN_F13R2_FB29_Pos) /*!< 0x20000000 */
5663 #define CAN_F13R2_FB29 CAN_F13R2_FB29_Msk /*!<Filter bit 29 */
5664 #define CAN_F13R2_FB30_Pos (30U)
5665 #define CAN_F13R2_FB30_Msk (0x1U << CAN_F13R2_FB30_Pos) /*!< 0x40000000 */
5666 #define CAN_F13R2_FB30 CAN_F13R2_FB30_Msk /*!<Filter bit 30 */
5667 #define CAN_F13R2_FB31_Pos (31U)
5668 #define CAN_F13R2_FB31_Msk (0x1U << CAN_F13R2_FB31_Pos) /*!< 0x80000000 */
5669 #define CAN_F13R2_FB31 CAN_F13R2_FB31_Msk /*!<Filter bit 31 */
5670
5671 /******************************************************************************/
5672 /* */
5673 /* CRC calculation unit */
5674 /* */
5675 /******************************************************************************/
5676 /******************* Bit definition for CRC_DR register *********************/
5677 #define CRC_DR_DR_Pos (0U)
5678 #define CRC_DR_DR_Msk (0xFFFFFFFFU << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */
5679 #define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */
5680
5681
5682 /******************* Bit definition for CRC_IDR register ********************/
5683 #define CRC_IDR_IDR_Pos (0U)
5684 #define CRC_IDR_IDR_Msk (0xFFU << CRC_IDR_IDR_Pos) /*!< 0x000000FF */
5685 #define CRC_IDR_IDR CRC_IDR_IDR_Msk /*!< General-purpose 8-bit data register bits */
5686
5687
5688 /******************** Bit definition for CRC_CR register ********************/
5689 #define CRC_CR_RESET_Pos (0U)
5690 #define CRC_CR_RESET_Msk (0x1U << CRC_CR_RESET_Pos) /*!< 0x00000001 */
5691 #define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET bit */
5692
5693 /******************************************************************************/
5694 /* */
5695 /* Digital to Analog Converter */
5696 /* */
5697 /******************************************************************************/
5698 /*
5699 * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
5700 */
5701 #define DAC_CHANNEL2_SUPPORT /*!< DAC feature available only on specific devices: availability of DAC channel 2 */
5702 /******************** Bit definition for DAC_CR register ********************/
5703 #define DAC_CR_EN1_Pos (0U)
5704 #define DAC_CR_EN1_Msk (0x1U << DAC_CR_EN1_Pos) /*!< 0x00000001 */
5705 #define DAC_CR_EN1 DAC_CR_EN1_Msk /*!<DAC channel1 enable */
5706 #define DAC_CR_BOFF1_Pos (1U)
5707 #define DAC_CR_BOFF1_Msk (0x1U << DAC_CR_BOFF1_Pos) /*!< 0x00000002 */
5708 #define DAC_CR_BOFF1 DAC_CR_BOFF1_Msk /*!<DAC channel1 output buffer disable */
5709 #define DAC_CR_TEN1_Pos (2U)
5710 #define DAC_CR_TEN1_Msk (0x1U << DAC_CR_TEN1_Pos) /*!< 0x00000004 */
5711 #define DAC_CR_TEN1 DAC_CR_TEN1_Msk /*!<DAC channel1 Trigger enable */
5712
5713 #define DAC_CR_TSEL1_Pos (3U)
5714 #define DAC_CR_TSEL1_Msk (0x7U << DAC_CR_TSEL1_Pos) /*!< 0x00000038 */
5715 #define DAC_CR_TSEL1 DAC_CR_TSEL1_Msk /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */
5716 #define DAC_CR_TSEL1_0 (0x1U << DAC_CR_TSEL1_Pos) /*!< 0x00000008 */
5717 #define DAC_CR_TSEL1_1 (0x2U << DAC_CR_TSEL1_Pos) /*!< 0x00000010 */
5718 #define DAC_CR_TSEL1_2 (0x4U << DAC_CR_TSEL1_Pos) /*!< 0x00000020 */
5719
5720 #define DAC_CR_WAVE1_Pos (6U)
5721 #define DAC_CR_WAVE1_Msk (0x3U << DAC_CR_WAVE1_Pos) /*!< 0x000000C0 */
5722 #define DAC_CR_WAVE1 DAC_CR_WAVE1_Msk /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
5723 #define DAC_CR_WAVE1_0 (0x1U << DAC_CR_WAVE1_Pos) /*!< 0x00000040 */
5724 #define DAC_CR_WAVE1_1 (0x2U << DAC_CR_WAVE1_Pos) /*!< 0x00000080 */
5725
5726 #define DAC_CR_MAMP1_Pos (8U)
5727 #define DAC_CR_MAMP1_Msk (0xFU << DAC_CR_MAMP1_Pos) /*!< 0x00000F00 */
5728 #define DAC_CR_MAMP1 DAC_CR_MAMP1_Msk /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
5729 #define DAC_CR_MAMP1_0 (0x1U << DAC_CR_MAMP1_Pos) /*!< 0x00000100 */
5730 #define DAC_CR_MAMP1_1 (0x2U << DAC_CR_MAMP1_Pos) /*!< 0x00000200 */
5731 #define DAC_CR_MAMP1_2 (0x4U << DAC_CR_MAMP1_Pos) /*!< 0x00000400 */
5732 #define DAC_CR_MAMP1_3 (0x8U << DAC_CR_MAMP1_Pos) /*!< 0x00000800 */
5733
5734 #define DAC_CR_DMAEN1_Pos (12U)
5735 #define DAC_CR_DMAEN1_Msk (0x1U << DAC_CR_DMAEN1_Pos) /*!< 0x00001000 */
5736 #define DAC_CR_DMAEN1 DAC_CR_DMAEN1_Msk /*!<DAC channel1 DMA enable */
5737 #define DAC_CR_DMAUDRIE1_Pos (13U)
5738 #define DAC_CR_DMAUDRIE1_Msk (0x1U << DAC_CR_DMAUDRIE1_Pos) /*!< 0x00002000 */
5739 #define DAC_CR_DMAUDRIE1 DAC_CR_DMAUDRIE1_Msk /*!<DAC channel1 DMA underrun interrupt enable*/
5740 #define DAC_CR_EN2_Pos (16U)
5741 #define DAC_CR_EN2_Msk (0x1U << DAC_CR_EN2_Pos) /*!< 0x00010000 */
5742 #define DAC_CR_EN2 DAC_CR_EN2_Msk /*!<DAC channel2 enable */
5743 #define DAC_CR_BOFF2_Pos (17U)
5744 #define DAC_CR_BOFF2_Msk (0x1U << DAC_CR_BOFF2_Pos) /*!< 0x00020000 */
5745 #define DAC_CR_BOFF2 DAC_CR_BOFF2_Msk /*!<DAC channel2 output buffer disable */
5746 #define DAC_CR_TEN2_Pos (18U)
5747 #define DAC_CR_TEN2_Msk (0x1U << DAC_CR_TEN2_Pos) /*!< 0x00040000 */
5748 #define DAC_CR_TEN2 DAC_CR_TEN2_Msk /*!<DAC channel2 Trigger enable */
5749
5750 #define DAC_CR_TSEL2_Pos (19U)
5751 #define DAC_CR_TSEL2_Msk (0x7U << DAC_CR_TSEL2_Pos) /*!< 0x00380000 */
5752 #define DAC_CR_TSEL2 DAC_CR_TSEL2_Msk /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */
5753 #define DAC_CR_TSEL2_0 (0x1U << DAC_CR_TSEL2_Pos) /*!< 0x00080000 */
5754 #define DAC_CR_TSEL2_1 (0x2U << DAC_CR_TSEL2_Pos) /*!< 0x00100000 */
5755 #define DAC_CR_TSEL2_2 (0x4U << DAC_CR_TSEL2_Pos) /*!< 0x00200000 */
5756
5757 #define DAC_CR_WAVE2_Pos (22U)
5758 #define DAC_CR_WAVE2_Msk (0x3U << DAC_CR_WAVE2_Pos) /*!< 0x00C00000 */
5759 #define DAC_CR_WAVE2 DAC_CR_WAVE2_Msk /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
5760 #define DAC_CR_WAVE2_0 (0x1U << DAC_CR_WAVE2_Pos) /*!< 0x00400000 */
5761 #define DAC_CR_WAVE2_1 (0x2U << DAC_CR_WAVE2_Pos) /*!< 0x00800000 */
5762
5763 #define DAC_CR_MAMP2_Pos (24U)
5764 #define DAC_CR_MAMP2_Msk (0xFU << DAC_CR_MAMP2_Pos) /*!< 0x0F000000 */
5765 #define DAC_CR_MAMP2 DAC_CR_MAMP2_Msk /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
5766 #define DAC_CR_MAMP2_0 (0x1U << DAC_CR_MAMP2_Pos) /*!< 0x01000000 */
5767 #define DAC_CR_MAMP2_1 (0x2U << DAC_CR_MAMP2_Pos) /*!< 0x02000000 */
5768 #define DAC_CR_MAMP2_2 (0x4U << DAC_CR_MAMP2_Pos) /*!< 0x04000000 */
5769 #define DAC_CR_MAMP2_3 (0x8U << DAC_CR_MAMP2_Pos) /*!< 0x08000000 */
5770
5771 #define DAC_CR_DMAEN2_Pos (28U)
5772 #define DAC_CR_DMAEN2_Msk (0x1U << DAC_CR_DMAEN2_Pos) /*!< 0x10000000 */
5773 #define DAC_CR_DMAEN2 DAC_CR_DMAEN2_Msk /*!<DAC channel2 DMA enabled */
5774 #define DAC_CR_DMAUDRIE2_Pos (29U)
5775 #define DAC_CR_DMAUDRIE2_Msk (0x1U << DAC_CR_DMAUDRIE2_Pos) /*!< 0x20000000 */
5776 #define DAC_CR_DMAUDRIE2 DAC_CR_DMAUDRIE2_Msk /*!<DAC channel2 DMA underrun interrupt enable*/
5777
5778 /***************** Bit definition for DAC_SWTRIGR register ******************/
5779 #define DAC_SWTRIGR_SWTRIG1_Pos (0U)
5780 #define DAC_SWTRIGR_SWTRIG1_Msk (0x1U << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */
5781 #define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk /*!<DAC channel1 software trigger */
5782 #define DAC_SWTRIGR_SWTRIG2_Pos (1U)
5783 #define DAC_SWTRIGR_SWTRIG2_Msk (0x1U << DAC_SWTRIGR_SWTRIG2_Pos) /*!< 0x00000002 */
5784 #define DAC_SWTRIGR_SWTRIG2 DAC_SWTRIGR_SWTRIG2_Msk /*!<DAC channel2 software trigger */
5785
5786 /***************** Bit definition for DAC_DHR12R1 register ******************/
5787 #define DAC_DHR12R1_DACC1DHR_Pos (0U)
5788 #define DAC_DHR12R1_DACC1DHR_Msk (0xFFFU << DAC_DHR12R1_DACC1DHR_Pos) /*!< 0x00000FFF */
5789 #define DAC_DHR12R1_DACC1DHR DAC_DHR12R1_DACC1DHR_Msk /*!<DAC channel1 12-bit Right aligned data */
5790
5791 /***************** Bit definition for DAC_DHR12L1 register ******************/
5792 #define DAC_DHR12L1_DACC1DHR_Pos (4U)
5793 #define DAC_DHR12L1_DACC1DHR_Msk (0xFFFU << DAC_DHR12L1_DACC1DHR_Pos) /*!< 0x0000FFF0 */
5794 #define DAC_DHR12L1_DACC1DHR DAC_DHR12L1_DACC1DHR_Msk /*!<DAC channel1 12-bit Left aligned data */
5795
5796 /****************** Bit definition for DAC_DHR8R1 register ******************/
5797 #define DAC_DHR8R1_DACC1DHR_Pos (0U)
5798 #define DAC_DHR8R1_DACC1DHR_Msk (0xFFU << DAC_DHR8R1_DACC1DHR_Pos) /*!< 0x000000FF */
5799 #define DAC_DHR8R1_DACC1DHR DAC_DHR8R1_DACC1DHR_Msk /*!<DAC channel1 8-bit Right aligned data */
5800
5801 /***************** Bit definition for DAC_DHR12R2 register ******************/
5802 #define DAC_DHR12R2_DACC2DHR_Pos (0U)
5803 #define DAC_DHR12R2_DACC2DHR_Msk (0xFFFU << DAC_DHR12R2_DACC2DHR_Pos) /*!< 0x00000FFF */
5804 #define DAC_DHR12R2_DACC2DHR DAC_DHR12R2_DACC2DHR_Msk /*!<DAC channel2 12-bit Right aligned data */
5805
5806 /***************** Bit definition for DAC_DHR12L2 register ******************/
5807 #define DAC_DHR12L2_DACC2DHR_Pos (4U)
5808 #define DAC_DHR12L2_DACC2DHR_Msk (0xFFFU << DAC_DHR12L2_DACC2DHR_Pos) /*!< 0x0000FFF0 */
5809 #define DAC_DHR12L2_DACC2DHR DAC_DHR12L2_DACC2DHR_Msk /*!<DAC channel2 12-bit Left aligned data */
5810
5811 /****************** Bit definition for DAC_DHR8R2 register ******************/
5812 #define DAC_DHR8R2_DACC2DHR_Pos (0U)
5813 #define DAC_DHR8R2_DACC2DHR_Msk (0xFFU << DAC_DHR8R2_DACC2DHR_Pos) /*!< 0x000000FF */
5814 #define DAC_DHR8R2_DACC2DHR DAC_DHR8R2_DACC2DHR_Msk /*!<DAC channel2 8-bit Right aligned data */
5815
5816 /***************** Bit definition for DAC_DHR12RD register ******************/
5817 #define DAC_DHR12RD_DACC1DHR_Pos (0U)
5818 #define DAC_DHR12RD_DACC1DHR_Msk (0xFFFU << DAC_DHR12RD_DACC1DHR_Pos) /*!< 0x00000FFF */
5819 #define DAC_DHR12RD_DACC1DHR DAC_DHR12RD_DACC1DHR_Msk /*!<DAC channel1 12-bit Right aligned data */
5820 #define DAC_DHR12RD_DACC2DHR_Pos (16U)
5821 #define DAC_DHR12RD_DACC2DHR_Msk (0xFFFU << DAC_DHR12RD_DACC2DHR_Pos) /*!< 0x0FFF0000 */
5822 #define DAC_DHR12RD_DACC2DHR DAC_DHR12RD_DACC2DHR_Msk /*!<DAC channel2 12-bit Right aligned data */
5823
5824 /***************** Bit definition for DAC_DHR12LD register ******************/
5825 #define DAC_DHR12LD_DACC1DHR_Pos (4U)
5826 #define DAC_DHR12LD_DACC1DHR_Msk (0xFFFU << DAC_DHR12LD_DACC1DHR_Pos) /*!< 0x0000FFF0 */
5827 #define DAC_DHR12LD_DACC1DHR DAC_DHR12LD_DACC1DHR_Msk /*!<DAC channel1 12-bit Left aligned data */
5828 #define DAC_DHR12LD_DACC2DHR_Pos (20U)
5829 #define DAC_DHR12LD_DACC2DHR_Msk (0xFFFU << DAC_DHR12LD_DACC2DHR_Pos) /*!< 0xFFF00000 */
5830 #define DAC_DHR12LD_DACC2DHR DAC_DHR12LD_DACC2DHR_Msk /*!<DAC channel2 12-bit Left aligned data */
5831
5832 /****************** Bit definition for DAC_DHR8RD register ******************/
5833 #define DAC_DHR8RD_DACC1DHR_Pos (0U)
5834 #define DAC_DHR8RD_DACC1DHR_Msk (0xFFU << DAC_DHR8RD_DACC1DHR_Pos) /*!< 0x000000FF */
5835 #define DAC_DHR8RD_DACC1DHR DAC_DHR8RD_DACC1DHR_Msk /*!<DAC channel1 8-bit Right aligned data */
5836 #define DAC_DHR8RD_DACC2DHR_Pos (8U)
5837 #define DAC_DHR8RD_DACC2DHR_Msk (0xFFU << DAC_DHR8RD_DACC2DHR_Pos) /*!< 0x0000FF00 */
5838 #define DAC_DHR8RD_DACC2DHR DAC_DHR8RD_DACC2DHR_Msk /*!<DAC channel2 8-bit Right aligned data */
5839
5840 /******************* Bit definition for DAC_DOR1 register *******************/
5841 #define DAC_DOR1_DACC1DOR_Pos (0U)
5842 #define DAC_DOR1_DACC1DOR_Msk (0xFFFU << DAC_DOR1_DACC1DOR_Pos) /*!< 0x00000FFF */
5843 #define DAC_DOR1_DACC1DOR DAC_DOR1_DACC1DOR_Msk /*!<DAC channel1 data output */
5844
5845 /******************* Bit definition for DAC_DOR2 register *******************/
5846 #define DAC_DOR2_DACC2DOR_Pos (0U)
5847 #define DAC_DOR2_DACC2DOR_Msk (0xFFFU << DAC_DOR2_DACC2DOR_Pos) /*!< 0x00000FFF */
5848 #define DAC_DOR2_DACC2DOR DAC_DOR2_DACC2DOR_Msk /*!<DAC channel2 data output */
5849
5850 /******************** Bit definition for DAC_SR register ********************/
5851 #define DAC_SR_DMAUDR1_Pos (13U)
5852 #define DAC_SR_DMAUDR1_Msk (0x1U << DAC_SR_DMAUDR1_Pos) /*!< 0x00002000 */
5853 #define DAC_SR_DMAUDR1 DAC_SR_DMAUDR1_Msk /*!<DAC channel1 DMA underrun flag */
5854 #define DAC_SR_DMAUDR2_Pos (29U)
5855 #define DAC_SR_DMAUDR2_Msk (0x1U << DAC_SR_DMAUDR2_Pos) /*!< 0x20000000 */
5856 #define DAC_SR_DMAUDR2 DAC_SR_DMAUDR2_Msk /*!<DAC channel2 DMA underrun flag */
5857
5858 /******************************************************************************/
5859 /* */
5860 /* DCMI */
5861 /* */
5862 /******************************************************************************/
5863 /******************** Bits definition for DCMI_CR register ******************/
5864 #define DCMI_CR_CAPTURE_Pos (0U)
5865 #define DCMI_CR_CAPTURE_Msk (0x1U << DCMI_CR_CAPTURE_Pos) /*!< 0x00000001 */
5866 #define DCMI_CR_CAPTURE DCMI_CR_CAPTURE_Msk
5867 #define DCMI_CR_CM_Pos (1U)
5868 #define DCMI_CR_CM_Msk (0x1U << DCMI_CR_CM_Pos) /*!< 0x00000002 */
5869 #define DCMI_CR_CM DCMI_CR_CM_Msk
5870 #define DCMI_CR_CROP_Pos (2U)
5871 #define DCMI_CR_CROP_Msk (0x1U << DCMI_CR_CROP_Pos) /*!< 0x00000004 */
5872 #define DCMI_CR_CROP DCMI_CR_CROP_Msk
5873 #define DCMI_CR_JPEG_Pos (3U)
5874 #define DCMI_CR_JPEG_Msk (0x1U << DCMI_CR_JPEG_Pos) /*!< 0x00000008 */
5875 #define DCMI_CR_JPEG DCMI_CR_JPEG_Msk
5876 #define DCMI_CR_ESS_Pos (4U)
5877 #define DCMI_CR_ESS_Msk (0x1U << DCMI_CR_ESS_Pos) /*!< 0x00000010 */
5878 #define DCMI_CR_ESS DCMI_CR_ESS_Msk
5879 #define DCMI_CR_PCKPOL_Pos (5U)
5880 #define DCMI_CR_PCKPOL_Msk (0x1U << DCMI_CR_PCKPOL_Pos) /*!< 0x00000020 */
5881 #define DCMI_CR_PCKPOL DCMI_CR_PCKPOL_Msk
5882 #define DCMI_CR_HSPOL_Pos (6U)
5883 #define DCMI_CR_HSPOL_Msk (0x1U << DCMI_CR_HSPOL_Pos) /*!< 0x00000040 */
5884 #define DCMI_CR_HSPOL DCMI_CR_HSPOL_Msk
5885 #define DCMI_CR_VSPOL_Pos (7U)
5886 #define DCMI_CR_VSPOL_Msk (0x1U << DCMI_CR_VSPOL_Pos) /*!< 0x00000080 */
5887 #define DCMI_CR_VSPOL DCMI_CR_VSPOL_Msk
5888 #define DCMI_CR_FCRC_0 0x00000100U
5889 #define DCMI_CR_FCRC_1 0x00000200U
5890 #define DCMI_CR_EDM_0 0x00000400U
5891 #define DCMI_CR_EDM_1 0x00000800U
5892 #define DCMI_CR_OUTEN_Pos (13U)
5893 #define DCMI_CR_OUTEN_Msk (0x1U << DCMI_CR_OUTEN_Pos) /*!< 0x00002000 */
5894 #define DCMI_CR_OUTEN DCMI_CR_OUTEN_Msk
5895 #define DCMI_CR_ENABLE_Pos (14U)
5896 #define DCMI_CR_ENABLE_Msk (0x1U << DCMI_CR_ENABLE_Pos) /*!< 0x00004000 */
5897 #define DCMI_CR_ENABLE DCMI_CR_ENABLE_Msk
5898 #define DCMI_CR_BSM_0 0x00010000U
5899 #define DCMI_CR_BSM_1 0x00020000U
5900 #define DCMI_CR_OEBS_Pos (18U)
5901 #define DCMI_CR_OEBS_Msk (0x1U << DCMI_CR_OEBS_Pos) /*!< 0x00040000 */
5902 #define DCMI_CR_OEBS DCMI_CR_OEBS_Msk
5903 #define DCMI_CR_LSM_Pos (19U)
5904 #define DCMI_CR_LSM_Msk (0x1U << DCMI_CR_LSM_Pos) /*!< 0x00080000 */
5905 #define DCMI_CR_LSM DCMI_CR_LSM_Msk
5906 #define DCMI_CR_OELS_Pos (20U)
5907 #define DCMI_CR_OELS_Msk (0x1U << DCMI_CR_OELS_Pos) /*!< 0x00100000 */
5908 #define DCMI_CR_OELS DCMI_CR_OELS_Msk
5909
5910 /******************** Bits definition for DCMI_SR register ******************/
5911 #define DCMI_SR_HSYNC_Pos (0U)
5912 #define DCMI_SR_HSYNC_Msk (0x1U << DCMI_SR_HSYNC_Pos) /*!< 0x00000001 */
5913 #define DCMI_SR_HSYNC DCMI_SR_HSYNC_Msk
5914 #define DCMI_SR_VSYNC_Pos (1U)
5915 #define DCMI_SR_VSYNC_Msk (0x1U << DCMI_SR_VSYNC_Pos) /*!< 0x00000002 */
5916 #define DCMI_SR_VSYNC DCMI_SR_VSYNC_Msk
5917 #define DCMI_SR_FNE_Pos (2U)
5918 #define DCMI_SR_FNE_Msk (0x1U << DCMI_SR_FNE_Pos) /*!< 0x00000004 */
5919 #define DCMI_SR_FNE DCMI_SR_FNE_Msk
5920
5921 /******************** Bits definition for DCMI_RIS register *****************/
5922 #define DCMI_RIS_FRAME_RIS_Pos (0U)
5923 #define DCMI_RIS_FRAME_RIS_Msk (0x1U << DCMI_RIS_FRAME_RIS_Pos) /*!< 0x00000001 */
5924 #define DCMI_RIS_FRAME_RIS DCMI_RIS_FRAME_RIS_Msk
5925 #define DCMI_RIS_OVR_RIS_Pos (1U)
5926 #define DCMI_RIS_OVR_RIS_Msk (0x1U << DCMI_RIS_OVR_RIS_Pos) /*!< 0x00000002 */
5927 #define DCMI_RIS_OVR_RIS DCMI_RIS_OVR_RIS_Msk
5928 #define DCMI_RIS_ERR_RIS_Pos (2U)
5929 #define DCMI_RIS_ERR_RIS_Msk (0x1U << DCMI_RIS_ERR_RIS_Pos) /*!< 0x00000004 */
5930 #define DCMI_RIS_ERR_RIS DCMI_RIS_ERR_RIS_Msk
5931 #define DCMI_RIS_VSYNC_RIS_Pos (3U)
5932 #define DCMI_RIS_VSYNC_RIS_Msk (0x1U << DCMI_RIS_VSYNC_RIS_Pos) /*!< 0x00000008 */
5933 #define DCMI_RIS_VSYNC_RIS DCMI_RIS_VSYNC_RIS_Msk
5934 #define DCMI_RIS_LINE_RIS_Pos (4U)
5935 #define DCMI_RIS_LINE_RIS_Msk (0x1U << DCMI_RIS_LINE_RIS_Pos) /*!< 0x00000010 */
5936 #define DCMI_RIS_LINE_RIS DCMI_RIS_LINE_RIS_Msk
5937 /* Legacy defines */
5938 #define DCMI_RISR_FRAME_RIS DCMI_RIS_FRAME_RIS
5939 #define DCMI_RISR_OVR_RIS DCMI_RIS_OVR_RIS
5940 #define DCMI_RISR_ERR_RIS DCMI_RIS_ERR_RIS
5941 #define DCMI_RISR_VSYNC_RIS DCMI_RIS_VSYNC_RIS
5942 #define DCMI_RISR_LINE_RIS DCMI_RIS_LINE_RIS
5943 #define DCMI_RISR_OVF_RIS DCMI_RIS_OVR_RIS
5944
5945 /******************** Bits definition for DCMI_IER register *****************/
5946 #define DCMI_IER_FRAME_IE_Pos (0U)
5947 #define DCMI_IER_FRAME_IE_Msk (0x1U << DCMI_IER_FRAME_IE_Pos) /*!< 0x00000001 */
5948 #define DCMI_IER_FRAME_IE DCMI_IER_FRAME_IE_Msk
5949 #define DCMI_IER_OVR_IE_Pos (1U)
5950 #define DCMI_IER_OVR_IE_Msk (0x1U << DCMI_IER_OVR_IE_Pos) /*!< 0x00000002 */
5951 #define DCMI_IER_OVR_IE DCMI_IER_OVR_IE_Msk
5952 #define DCMI_IER_ERR_IE_Pos (2U)
5953 #define DCMI_IER_ERR_IE_Msk (0x1U << DCMI_IER_ERR_IE_Pos) /*!< 0x00000004 */
5954 #define DCMI_IER_ERR_IE DCMI_IER_ERR_IE_Msk
5955 #define DCMI_IER_VSYNC_IE_Pos (3U)
5956 #define DCMI_IER_VSYNC_IE_Msk (0x1U << DCMI_IER_VSYNC_IE_Pos) /*!< 0x00000008 */
5957 #define DCMI_IER_VSYNC_IE DCMI_IER_VSYNC_IE_Msk
5958 #define DCMI_IER_LINE_IE_Pos (4U)
5959 #define DCMI_IER_LINE_IE_Msk (0x1U << DCMI_IER_LINE_IE_Pos) /*!< 0x00000010 */
5960 #define DCMI_IER_LINE_IE DCMI_IER_LINE_IE_Msk
5961 /* Legacy defines */
5962 #define DCMI_IER_OVF_IE DCMI_IER_OVR_IE
5963
5964 /******************** Bits definition for DCMI_MIS register *****************/
5965 #define DCMI_MIS_FRAME_MIS_Pos (0U)
5966 #define DCMI_MIS_FRAME_MIS_Msk (0x1U << DCMI_MIS_FRAME_MIS_Pos) /*!< 0x00000001 */
5967 #define DCMI_MIS_FRAME_MIS DCMI_MIS_FRAME_MIS_Msk
5968 #define DCMI_MIS_OVR_MIS_Pos (1U)
5969 #define DCMI_MIS_OVR_MIS_Msk (0x1U << DCMI_MIS_OVR_MIS_Pos) /*!< 0x00000002 */
5970 #define DCMI_MIS_OVR_MIS DCMI_MIS_OVR_MIS_Msk
5971 #define DCMI_MIS_ERR_MIS_Pos (2U)
5972 #define DCMI_MIS_ERR_MIS_Msk (0x1U << DCMI_MIS_ERR_MIS_Pos) /*!< 0x00000004 */
5973 #define DCMI_MIS_ERR_MIS DCMI_MIS_ERR_MIS_Msk
5974 #define DCMI_MIS_VSYNC_MIS_Pos (3U)
5975 #define DCMI_MIS_VSYNC_MIS_Msk (0x1U << DCMI_MIS_VSYNC_MIS_Pos) /*!< 0x00000008 */
5976 #define DCMI_MIS_VSYNC_MIS DCMI_MIS_VSYNC_MIS_Msk
5977 #define DCMI_MIS_LINE_MIS_Pos (4U)
5978 #define DCMI_MIS_LINE_MIS_Msk (0x1U << DCMI_MIS_LINE_MIS_Pos) /*!< 0x00000010 */
5979 #define DCMI_MIS_LINE_MIS DCMI_MIS_LINE_MIS_Msk
5980
5981 /* Legacy defines */
5982 #define DCMI_MISR_FRAME_MIS DCMI_MIS_FRAME_MIS
5983 #define DCMI_MISR_OVF_MIS DCMI_MIS_OVR_MIS
5984 #define DCMI_MISR_ERR_MIS DCMI_MIS_ERR_MIS
5985 #define DCMI_MISR_VSYNC_MIS DCMI_MIS_VSYNC_MIS
5986 #define DCMI_MISR_LINE_MIS DCMI_MIS_LINE_MIS
5987
5988 /******************** Bits definition for DCMI_ICR register *****************/
5989 #define DCMI_ICR_FRAME_ISC_Pos (0U)
5990 #define DCMI_ICR_FRAME_ISC_Msk (0x1U << DCMI_ICR_FRAME_ISC_Pos) /*!< 0x00000001 */
5991 #define DCMI_ICR_FRAME_ISC DCMI_ICR_FRAME_ISC_Msk
5992 #define DCMI_ICR_OVR_ISC_Pos (1U)
5993 #define DCMI_ICR_OVR_ISC_Msk (0x1U << DCMI_ICR_OVR_ISC_Pos) /*!< 0x00000002 */
5994 #define DCMI_ICR_OVR_ISC DCMI_ICR_OVR_ISC_Msk
5995 #define DCMI_ICR_ERR_ISC_Pos (2U)
5996 #define DCMI_ICR_ERR_ISC_Msk (0x1U << DCMI_ICR_ERR_ISC_Pos) /*!< 0x00000004 */
5997 #define DCMI_ICR_ERR_ISC DCMI_ICR_ERR_ISC_Msk
5998 #define DCMI_ICR_VSYNC_ISC_Pos (3U)
5999 #define DCMI_ICR_VSYNC_ISC_Msk (0x1U << DCMI_ICR_VSYNC_ISC_Pos) /*!< 0x00000008 */
6000 #define DCMI_ICR_VSYNC_ISC DCMI_ICR_VSYNC_ISC_Msk
6001 #define DCMI_ICR_LINE_ISC_Pos (4U)
6002 #define DCMI_ICR_LINE_ISC_Msk (0x1U << DCMI_ICR_LINE_ISC_Pos) /*!< 0x00000010 */
6003 #define DCMI_ICR_LINE_ISC DCMI_ICR_LINE_ISC_Msk
6004
6005 /* Legacy defines */
6006 #define DCMI_ICR_OVF_ISC DCMI_ICR_OVR_ISC
6007
6008 /******************** Bits definition for DCMI_ESCR register ******************/
6009 #define DCMI_ESCR_FSC_Pos (0U)
6010 #define DCMI_ESCR_FSC_Msk (0xFFU << DCMI_ESCR_FSC_Pos) /*!< 0x000000FF */
6011 #define DCMI_ESCR_FSC DCMI_ESCR_FSC_Msk
6012 #define DCMI_ESCR_LSC_Pos (8U)
6013 #define DCMI_ESCR_LSC_Msk (0xFFU << DCMI_ESCR_LSC_Pos) /*!< 0x0000FF00 */
6014 #define DCMI_ESCR_LSC DCMI_ESCR_LSC_Msk
6015 #define DCMI_ESCR_LEC_Pos (16U)
6016 #define DCMI_ESCR_LEC_Msk (0xFFU << DCMI_ESCR_LEC_Pos) /*!< 0x00FF0000 */
6017 #define DCMI_ESCR_LEC DCMI_ESCR_LEC_Msk
6018 #define DCMI_ESCR_FEC_Pos (24U)
6019 #define DCMI_ESCR_FEC_Msk (0xFFU << DCMI_ESCR_FEC_Pos) /*!< 0xFF000000 */
6020 #define DCMI_ESCR_FEC DCMI_ESCR_FEC_Msk
6021
6022 /******************** Bits definition for DCMI_ESUR register ******************/
6023 #define DCMI_ESUR_FSU_Pos (0U)
6024 #define DCMI_ESUR_FSU_Msk (0xFFU << DCMI_ESUR_FSU_Pos) /*!< 0x000000FF */
6025 #define DCMI_ESUR_FSU DCMI_ESUR_FSU_Msk
6026 #define DCMI_ESUR_LSU_Pos (8U)
6027 #define DCMI_ESUR_LSU_Msk (0xFFU << DCMI_ESUR_LSU_Pos) /*!< 0x0000FF00 */
6028 #define DCMI_ESUR_LSU DCMI_ESUR_LSU_Msk
6029 #define DCMI_ESUR_LEU_Pos (16U)
6030 #define DCMI_ESUR_LEU_Msk (0xFFU << DCMI_ESUR_LEU_Pos) /*!< 0x00FF0000 */
6031 #define DCMI_ESUR_LEU DCMI_ESUR_LEU_Msk
6032 #define DCMI_ESUR_FEU_Pos (24U)
6033 #define DCMI_ESUR_FEU_Msk (0xFFU << DCMI_ESUR_FEU_Pos) /*!< 0xFF000000 */
6034 #define DCMI_ESUR_FEU DCMI_ESUR_FEU_Msk
6035
6036 /******************** Bits definition for DCMI_CWSTRT register ******************/
6037 #define DCMI_CWSTRT_HOFFCNT_Pos (0U)
6038 #define DCMI_CWSTRT_HOFFCNT_Msk (0x3FFFU << DCMI_CWSTRT_HOFFCNT_Pos) /*!< 0x00003FFF */
6039 #define DCMI_CWSTRT_HOFFCNT DCMI_CWSTRT_HOFFCNT_Msk
6040 #define DCMI_CWSTRT_VST_Pos (16U)
6041 #define DCMI_CWSTRT_VST_Msk (0x1FFFU << DCMI_CWSTRT_VST_Pos) /*!< 0x1FFF0000 */
6042 #define DCMI_CWSTRT_VST DCMI_CWSTRT_VST_Msk
6043
6044 /******************** Bits definition for DCMI_CWSIZE register ******************/
6045 #define DCMI_CWSIZE_CAPCNT_Pos (0U)
6046 #define DCMI_CWSIZE_CAPCNT_Msk (0x3FFFU << DCMI_CWSIZE_CAPCNT_Pos) /*!< 0x00003FFF */
6047 #define DCMI_CWSIZE_CAPCNT DCMI_CWSIZE_CAPCNT_Msk
6048 #define DCMI_CWSIZE_VLINE_Pos (16U)
6049 #define DCMI_CWSIZE_VLINE_Msk (0x3FFFU << DCMI_CWSIZE_VLINE_Pos) /*!< 0x3FFF0000 */
6050 #define DCMI_CWSIZE_VLINE DCMI_CWSIZE_VLINE_Msk
6051
6052 /******************** Bits definition for DCMI_DR register *********************/
6053 #define DCMI_DR_BYTE0_Pos (0U)
6054 #define DCMI_DR_BYTE0_Msk (0xFFU << DCMI_DR_BYTE0_Pos) /*!< 0x000000FF */
6055 #define DCMI_DR_BYTE0 DCMI_DR_BYTE0_Msk
6056 #define DCMI_DR_BYTE1_Pos (8U)
6057 #define DCMI_DR_BYTE1_Msk (0xFFU << DCMI_DR_BYTE1_Pos) /*!< 0x0000FF00 */
6058 #define DCMI_DR_BYTE1 DCMI_DR_BYTE1_Msk
6059 #define DCMI_DR_BYTE2_Pos (16U)
6060 #define DCMI_DR_BYTE2_Msk (0xFFU << DCMI_DR_BYTE2_Pos) /*!< 0x00FF0000 */
6061 #define DCMI_DR_BYTE2 DCMI_DR_BYTE2_Msk
6062 #define DCMI_DR_BYTE3_Pos (24U)
6063 #define DCMI_DR_BYTE3_Msk (0xFFU << DCMI_DR_BYTE3_Pos) /*!< 0xFF000000 */
6064 #define DCMI_DR_BYTE3 DCMI_DR_BYTE3_Msk
6065
6066 /******************************************************************************/
6067 /* */
6068 /* DMA Controller */
6069 /* */
6070 /******************************************************************************/
6071 /******************** Bits definition for DMA_SxCR register *****************/
6072 #define DMA_SxCR_CHSEL_Pos (25U)
6073 #define DMA_SxCR_CHSEL_Msk (0x7U << DMA_SxCR_CHSEL_Pos) /*!< 0x0E000000 */
6074 #define DMA_SxCR_CHSEL DMA_SxCR_CHSEL_Msk
6075 #define DMA_SxCR_CHSEL_0 0x02000000U
6076 #define DMA_SxCR_CHSEL_1 0x04000000U
6077 #define DMA_SxCR_CHSEL_2 0x08000000U
6078 #define DMA_SxCR_MBURST_Pos (23U)
6079 #define DMA_SxCR_MBURST_Msk (0x3U << DMA_SxCR_MBURST_Pos) /*!< 0x01800000 */
6080 #define DMA_SxCR_MBURST DMA_SxCR_MBURST_Msk
6081 #define DMA_SxCR_MBURST_0 (0x1U << DMA_SxCR_MBURST_Pos) /*!< 0x00800000 */
6082 #define DMA_SxCR_MBURST_1 (0x2U << DMA_SxCR_MBURST_Pos) /*!< 0x01000000 */
6083 #define DMA_SxCR_PBURST_Pos (21U)
6084 #define DMA_SxCR_PBURST_Msk (0x3U << DMA_SxCR_PBURST_Pos) /*!< 0x00600000 */
6085 #define DMA_SxCR_PBURST DMA_SxCR_PBURST_Msk
6086 #define DMA_SxCR_PBURST_0 (0x1U << DMA_SxCR_PBURST_Pos) /*!< 0x00200000 */
6087 #define DMA_SxCR_PBURST_1 (0x2U << DMA_SxCR_PBURST_Pos) /*!< 0x00400000 */
6088 #define DMA_SxCR_CT_Pos (19U)
6089 #define DMA_SxCR_CT_Msk (0x1U << DMA_SxCR_CT_Pos) /*!< 0x00080000 */
6090 #define DMA_SxCR_CT DMA_SxCR_CT_Msk
6091 #define DMA_SxCR_DBM_Pos (18U)
6092 #define DMA_SxCR_DBM_Msk (0x1U << DMA_SxCR_DBM_Pos) /*!< 0x00040000 */
6093 #define DMA_SxCR_DBM DMA_SxCR_DBM_Msk
6094 #define DMA_SxCR_PL_Pos (16U)
6095 #define DMA_SxCR_PL_Msk (0x3U << DMA_SxCR_PL_Pos) /*!< 0x00030000 */
6096 #define DMA_SxCR_PL DMA_SxCR_PL_Msk
6097 #define DMA_SxCR_PL_0 (0x1U << DMA_SxCR_PL_Pos) /*!< 0x00010000 */
6098 #define DMA_SxCR_PL_1 (0x2U << DMA_SxCR_PL_Pos) /*!< 0x00020000 */
6099 #define DMA_SxCR_PINCOS_Pos (15U)
6100 #define DMA_SxCR_PINCOS_Msk (0x1U << DMA_SxCR_PINCOS_Pos) /*!< 0x00008000 */
6101 #define DMA_SxCR_PINCOS DMA_SxCR_PINCOS_Msk
6102 #define DMA_SxCR_MSIZE_Pos (13U)
6103 #define DMA_SxCR_MSIZE_Msk (0x3U << DMA_SxCR_MSIZE_Pos) /*!< 0x00006000 */
6104 #define DMA_SxCR_MSIZE DMA_SxCR_MSIZE_Msk
6105 #define DMA_SxCR_MSIZE_0 (0x1U << DMA_SxCR_MSIZE_Pos) /*!< 0x00002000 */
6106 #define DMA_SxCR_MSIZE_1 (0x2U << DMA_SxCR_MSIZE_Pos) /*!< 0x00004000 */
6107 #define DMA_SxCR_PSIZE_Pos (11U)
6108 #define DMA_SxCR_PSIZE_Msk (0x3U << DMA_SxCR_PSIZE_Pos) /*!< 0x00001800 */
6109 #define DMA_SxCR_PSIZE DMA_SxCR_PSIZE_Msk
6110 #define DMA_SxCR_PSIZE_0 (0x1U << DMA_SxCR_PSIZE_Pos) /*!< 0x00000800 */
6111 #define DMA_SxCR_PSIZE_1 (0x2U << DMA_SxCR_PSIZE_Pos) /*!< 0x00001000 */
6112 #define DMA_SxCR_MINC_Pos (10U)
6113 #define DMA_SxCR_MINC_Msk (0x1U << DMA_SxCR_MINC_Pos) /*!< 0x00000400 */
6114 #define DMA_SxCR_MINC DMA_SxCR_MINC_Msk
6115 #define DMA_SxCR_PINC_Pos (9U)
6116 #define DMA_SxCR_PINC_Msk (0x1U << DMA_SxCR_PINC_Pos) /*!< 0x00000200 */
6117 #define DMA_SxCR_PINC DMA_SxCR_PINC_Msk
6118 #define DMA_SxCR_CIRC_Pos (8U)
6119 #define DMA_SxCR_CIRC_Msk (0x1U << DMA_SxCR_CIRC_Pos) /*!< 0x00000100 */
6120 #define DMA_SxCR_CIRC DMA_SxCR_CIRC_Msk
6121 #define DMA_SxCR_DIR_Pos (6U)
6122 #define DMA_SxCR_DIR_Msk (0x3U << DMA_SxCR_DIR_Pos) /*!< 0x000000C0 */
6123 #define DMA_SxCR_DIR DMA_SxCR_DIR_Msk
6124 #define DMA_SxCR_DIR_0 (0x1U << DMA_SxCR_DIR_Pos) /*!< 0x00000040 */
6125 #define DMA_SxCR_DIR_1 (0x2U << DMA_SxCR_DIR_Pos) /*!< 0x00000080 */
6126 #define DMA_SxCR_PFCTRL_Pos (5U)
6127 #define DMA_SxCR_PFCTRL_Msk (0x1U << DMA_SxCR_PFCTRL_Pos) /*!< 0x00000020 */
6128 #define DMA_SxCR_PFCTRL DMA_SxCR_PFCTRL_Msk
6129 #define DMA_SxCR_TCIE_Pos (4U)
6130 #define DMA_SxCR_TCIE_Msk (0x1U << DMA_SxCR_TCIE_Pos) /*!< 0x00000010 */
6131 #define DMA_SxCR_TCIE DMA_SxCR_TCIE_Msk
6132 #define DMA_SxCR_HTIE_Pos (3U)
6133 #define DMA_SxCR_HTIE_Msk (0x1U << DMA_SxCR_HTIE_Pos) /*!< 0x00000008 */
6134 #define DMA_SxCR_HTIE DMA_SxCR_HTIE_Msk
6135 #define DMA_SxCR_TEIE_Pos (2U)
6136 #define DMA_SxCR_TEIE_Msk (0x1U << DMA_SxCR_TEIE_Pos) /*!< 0x00000004 */
6137 #define DMA_SxCR_TEIE DMA_SxCR_TEIE_Msk
6138 #define DMA_SxCR_DMEIE_Pos (1U)
6139 #define DMA_SxCR_DMEIE_Msk (0x1U << DMA_SxCR_DMEIE_Pos) /*!< 0x00000002 */
6140 #define DMA_SxCR_DMEIE DMA_SxCR_DMEIE_Msk
6141 #define DMA_SxCR_EN_Pos (0U)
6142 #define DMA_SxCR_EN_Msk (0x1U << DMA_SxCR_EN_Pos) /*!< 0x00000001 */
6143 #define DMA_SxCR_EN DMA_SxCR_EN_Msk
6144
6145 /* Legacy defines */
6146 #define DMA_SxCR_ACK_Pos (20U)
6147 #define DMA_SxCR_ACK_Msk (0x1U << DMA_SxCR_ACK_Pos) /*!< 0x00100000 */
6148 #define DMA_SxCR_ACK DMA_SxCR_ACK_Msk
6149
6150 /******************** Bits definition for DMA_SxCNDTR register **************/
6151 #define DMA_SxNDT_Pos (0U)
6152 #define DMA_SxNDT_Msk (0xFFFFU << DMA_SxNDT_Pos) /*!< 0x0000FFFF */
6153 #define DMA_SxNDT DMA_SxNDT_Msk
6154 #define DMA_SxNDT_0 (0x0001U << DMA_SxNDT_Pos) /*!< 0x00000001 */
6155 #define DMA_SxNDT_1 (0x0002U << DMA_SxNDT_Pos) /*!< 0x00000002 */
6156 #define DMA_SxNDT_2 (0x0004U << DMA_SxNDT_Pos) /*!< 0x00000004 */
6157 #define DMA_SxNDT_3 (0x0008U << DMA_SxNDT_Pos) /*!< 0x00000008 */
6158 #define DMA_SxNDT_4 (0x0010U << DMA_SxNDT_Pos) /*!< 0x00000010 */
6159 #define DMA_SxNDT_5 (0x0020U << DMA_SxNDT_Pos) /*!< 0x00000020 */
6160 #define DMA_SxNDT_6 (0x0040U << DMA_SxNDT_Pos) /*!< 0x00000040 */
6161 #define DMA_SxNDT_7 (0x0080U << DMA_SxNDT_Pos) /*!< 0x00000080 */
6162 #define DMA_SxNDT_8 (0x0100U << DMA_SxNDT_Pos) /*!< 0x00000100 */
6163 #define DMA_SxNDT_9 (0x0200U << DMA_SxNDT_Pos) /*!< 0x00000200 */
6164 #define DMA_SxNDT_10 (0x0400U << DMA_SxNDT_Pos) /*!< 0x00000400 */
6165 #define DMA_SxNDT_11 (0x0800U << DMA_SxNDT_Pos) /*!< 0x00000800 */
6166 #define DMA_SxNDT_12 (0x1000U << DMA_SxNDT_Pos) /*!< 0x00001000 */
6167 #define DMA_SxNDT_13 (0x2000U << DMA_SxNDT_Pos) /*!< 0x00002000 */
6168 #define DMA_SxNDT_14 (0x4000U << DMA_SxNDT_Pos) /*!< 0x00004000 */
6169 #define DMA_SxNDT_15 (0x8000U << DMA_SxNDT_Pos) /*!< 0x00008000 */
6170
6171 /******************** Bits definition for DMA_SxFCR register ****************/
6172 #define DMA_SxFCR_FEIE_Pos (7U)
6173 #define DMA_SxFCR_FEIE_Msk (0x1U << DMA_SxFCR_FEIE_Pos) /*!< 0x00000080 */
6174 #define DMA_SxFCR_FEIE DMA_SxFCR_FEIE_Msk
6175 #define DMA_SxFCR_FS_Pos (3U)
6176 #define DMA_SxFCR_FS_Msk (0x7U << DMA_SxFCR_FS_Pos) /*!< 0x00000038 */
6177 #define DMA_SxFCR_FS DMA_SxFCR_FS_Msk
6178 #define DMA_SxFCR_FS_0 (0x1U << DMA_SxFCR_FS_Pos) /*!< 0x00000008 */
6179 #define DMA_SxFCR_FS_1 (0x2U << DMA_SxFCR_FS_Pos) /*!< 0x00000010 */
6180 #define DMA_SxFCR_FS_2 (0x4U << DMA_SxFCR_FS_Pos) /*!< 0x00000020 */
6181 #define DMA_SxFCR_DMDIS_Pos (2U)
6182 #define DMA_SxFCR_DMDIS_Msk (0x1U << DMA_SxFCR_DMDIS_Pos) /*!< 0x00000004 */
6183 #define DMA_SxFCR_DMDIS DMA_SxFCR_DMDIS_Msk
6184 #define DMA_SxFCR_FTH_Pos (0U)
6185 #define DMA_SxFCR_FTH_Msk (0x3U << DMA_SxFCR_FTH_Pos) /*!< 0x00000003 */
6186 #define DMA_SxFCR_FTH DMA_SxFCR_FTH_Msk
6187 #define DMA_SxFCR_FTH_0 (0x1U << DMA_SxFCR_FTH_Pos) /*!< 0x00000001 */
6188 #define DMA_SxFCR_FTH_1 (0x2U << DMA_SxFCR_FTH_Pos) /*!< 0x00000002 */
6189
6190 /******************** Bits definition for DMA_LISR register *****************/
6191 #define DMA_LISR_TCIF3_Pos (27U)
6192 #define DMA_LISR_TCIF3_Msk (0x1U << DMA_LISR_TCIF3_Pos) /*!< 0x08000000 */
6193 #define DMA_LISR_TCIF3 DMA_LISR_TCIF3_Msk
6194 #define DMA_LISR_HTIF3_Pos (26U)
6195 #define DMA_LISR_HTIF3_Msk (0x1U << DMA_LISR_HTIF3_Pos) /*!< 0x04000000 */
6196 #define DMA_LISR_HTIF3 DMA_LISR_HTIF3_Msk
6197 #define DMA_LISR_TEIF3_Pos (25U)
6198 #define DMA_LISR_TEIF3_Msk (0x1U << DMA_LISR_TEIF3_Pos) /*!< 0x02000000 */
6199 #define DMA_LISR_TEIF3 DMA_LISR_TEIF3_Msk
6200 #define DMA_LISR_DMEIF3_Pos (24U)
6201 #define DMA_LISR_DMEIF3_Msk (0x1U << DMA_LISR_DMEIF3_Pos) /*!< 0x01000000 */
6202 #define DMA_LISR_DMEIF3 DMA_LISR_DMEIF3_Msk
6203 #define DMA_LISR_FEIF3_Pos (22U)
6204 #define DMA_LISR_FEIF3_Msk (0x1U << DMA_LISR_FEIF3_Pos) /*!< 0x00400000 */
6205 #define DMA_LISR_FEIF3 DMA_LISR_FEIF3_Msk
6206 #define DMA_LISR_TCIF2_Pos (21U)
6207 #define DMA_LISR_TCIF2_Msk (0x1U << DMA_LISR_TCIF2_Pos) /*!< 0x00200000 */
6208 #define DMA_LISR_TCIF2 DMA_LISR_TCIF2_Msk
6209 #define DMA_LISR_HTIF2_Pos (20U)
6210 #define DMA_LISR_HTIF2_Msk (0x1U << DMA_LISR_HTIF2_Pos) /*!< 0x00100000 */
6211 #define DMA_LISR_HTIF2 DMA_LISR_HTIF2_Msk
6212 #define DMA_LISR_TEIF2_Pos (19U)
6213 #define DMA_LISR_TEIF2_Msk (0x1U << DMA_LISR_TEIF2_Pos) /*!< 0x00080000 */
6214 #define DMA_LISR_TEIF2 DMA_LISR_TEIF2_Msk
6215 #define DMA_LISR_DMEIF2_Pos (18U)
6216 #define DMA_LISR_DMEIF2_Msk (0x1U << DMA_LISR_DMEIF2_Pos) /*!< 0x00040000 */
6217 #define DMA_LISR_DMEIF2 DMA_LISR_DMEIF2_Msk
6218 #define DMA_LISR_FEIF2_Pos (16U)
6219 #define DMA_LISR_FEIF2_Msk (0x1U << DMA_LISR_FEIF2_Pos) /*!< 0x00010000 */
6220 #define DMA_LISR_FEIF2 DMA_LISR_FEIF2_Msk
6221 #define DMA_LISR_TCIF1_Pos (11U)
6222 #define DMA_LISR_TCIF1_Msk (0x1U << DMA_LISR_TCIF1_Pos) /*!< 0x00000800 */
6223 #define DMA_LISR_TCIF1 DMA_LISR_TCIF1_Msk
6224 #define DMA_LISR_HTIF1_Pos (10U)
6225 #define DMA_LISR_HTIF1_Msk (0x1U << DMA_LISR_HTIF1_Pos) /*!< 0x00000400 */
6226 #define DMA_LISR_HTIF1 DMA_LISR_HTIF1_Msk
6227 #define DMA_LISR_TEIF1_Pos (9U)
6228 #define DMA_LISR_TEIF1_Msk (0x1U << DMA_LISR_TEIF1_Pos) /*!< 0x00000200 */
6229 #define DMA_LISR_TEIF1 DMA_LISR_TEIF1_Msk
6230 #define DMA_LISR_DMEIF1_Pos (8U)
6231 #define DMA_LISR_DMEIF1_Msk (0x1U << DMA_LISR_DMEIF1_Pos) /*!< 0x00000100 */
6232 #define DMA_LISR_DMEIF1 DMA_LISR_DMEIF1_Msk
6233 #define DMA_LISR_FEIF1_Pos (6U)
6234 #define DMA_LISR_FEIF1_Msk (0x1U << DMA_LISR_FEIF1_Pos) /*!< 0x00000040 */
6235 #define DMA_LISR_FEIF1 DMA_LISR_FEIF1_Msk
6236 #define DMA_LISR_TCIF0_Pos (5U)
6237 #define DMA_LISR_TCIF0_Msk (0x1U << DMA_LISR_TCIF0_Pos) /*!< 0x00000020 */
6238 #define DMA_LISR_TCIF0 DMA_LISR_TCIF0_Msk
6239 #define DMA_LISR_HTIF0_Pos (4U)
6240 #define DMA_LISR_HTIF0_Msk (0x1U << DMA_LISR_HTIF0_Pos) /*!< 0x00000010 */
6241 #define DMA_LISR_HTIF0 DMA_LISR_HTIF0_Msk
6242 #define DMA_LISR_TEIF0_Pos (3U)
6243 #define DMA_LISR_TEIF0_Msk (0x1U << DMA_LISR_TEIF0_Pos) /*!< 0x00000008 */
6244 #define DMA_LISR_TEIF0 DMA_LISR_TEIF0_Msk
6245 #define DMA_LISR_DMEIF0_Pos (2U)
6246 #define DMA_LISR_DMEIF0_Msk (0x1U << DMA_LISR_DMEIF0_Pos) /*!< 0x00000004 */
6247 #define DMA_LISR_DMEIF0 DMA_LISR_DMEIF0_Msk
6248 #define DMA_LISR_FEIF0_Pos (0U)
6249 #define DMA_LISR_FEIF0_Msk (0x1U << DMA_LISR_FEIF0_Pos) /*!< 0x00000001 */
6250 #define DMA_LISR_FEIF0 DMA_LISR_FEIF0_Msk
6251
6252 /******************** Bits definition for DMA_HISR register *****************/
6253 #define DMA_HISR_TCIF7_Pos (27U)
6254 #define DMA_HISR_TCIF7_Msk (0x1U << DMA_HISR_TCIF7_Pos) /*!< 0x08000000 */
6255 #define DMA_HISR_TCIF7 DMA_HISR_TCIF7_Msk
6256 #define DMA_HISR_HTIF7_Pos (26U)
6257 #define DMA_HISR_HTIF7_Msk (0x1U << DMA_HISR_HTIF7_Pos) /*!< 0x04000000 */
6258 #define DMA_HISR_HTIF7 DMA_HISR_HTIF7_Msk
6259 #define DMA_HISR_TEIF7_Pos (25U)
6260 #define DMA_HISR_TEIF7_Msk (0x1U << DMA_HISR_TEIF7_Pos) /*!< 0x02000000 */
6261 #define DMA_HISR_TEIF7 DMA_HISR_TEIF7_Msk
6262 #define DMA_HISR_DMEIF7_Pos (24U)
6263 #define DMA_HISR_DMEIF7_Msk (0x1U << DMA_HISR_DMEIF7_Pos) /*!< 0x01000000 */
6264 #define DMA_HISR_DMEIF7 DMA_HISR_DMEIF7_Msk
6265 #define DMA_HISR_FEIF7_Pos (22U)
6266 #define DMA_HISR_FEIF7_Msk (0x1U << DMA_HISR_FEIF7_Pos) /*!< 0x00400000 */
6267 #define DMA_HISR_FEIF7 DMA_HISR_FEIF7_Msk
6268 #define DMA_HISR_TCIF6_Pos (21U)
6269 #define DMA_HISR_TCIF6_Msk (0x1U << DMA_HISR_TCIF6_Pos) /*!< 0x00200000 */
6270 #define DMA_HISR_TCIF6 DMA_HISR_TCIF6_Msk
6271 #define DMA_HISR_HTIF6_Pos (20U)
6272 #define DMA_HISR_HTIF6_Msk (0x1U << DMA_HISR_HTIF6_Pos) /*!< 0x00100000 */
6273 #define DMA_HISR_HTIF6 DMA_HISR_HTIF6_Msk
6274 #define DMA_HISR_TEIF6_Pos (19U)
6275 #define DMA_HISR_TEIF6_Msk (0x1U << DMA_HISR_TEIF6_Pos) /*!< 0x00080000 */
6276 #define DMA_HISR_TEIF6 DMA_HISR_TEIF6_Msk
6277 #define DMA_HISR_DMEIF6_Pos (18U)
6278 #define DMA_HISR_DMEIF6_Msk (0x1U << DMA_HISR_DMEIF6_Pos) /*!< 0x00040000 */
6279 #define DMA_HISR_DMEIF6 DMA_HISR_DMEIF6_Msk
6280 #define DMA_HISR_FEIF6_Pos (16U)
6281 #define DMA_HISR_FEIF6_Msk (0x1U << DMA_HISR_FEIF6_Pos) /*!< 0x00010000 */
6282 #define DMA_HISR_FEIF6 DMA_HISR_FEIF6_Msk
6283 #define DMA_HISR_TCIF5_Pos (11U)
6284 #define DMA_HISR_TCIF5_Msk (0x1U << DMA_HISR_TCIF5_Pos) /*!< 0x00000800 */
6285 #define DMA_HISR_TCIF5 DMA_HISR_TCIF5_Msk
6286 #define DMA_HISR_HTIF5_Pos (10U)
6287 #define DMA_HISR_HTIF5_Msk (0x1U << DMA_HISR_HTIF5_Pos) /*!< 0x00000400 */
6288 #define DMA_HISR_HTIF5 DMA_HISR_HTIF5_Msk
6289 #define DMA_HISR_TEIF5_Pos (9U)
6290 #define DMA_HISR_TEIF5_Msk (0x1U << DMA_HISR_TEIF5_Pos) /*!< 0x00000200 */
6291 #define DMA_HISR_TEIF5 DMA_HISR_TEIF5_Msk
6292 #define DMA_HISR_DMEIF5_Pos (8U)
6293 #define DMA_HISR_DMEIF5_Msk (0x1U << DMA_HISR_DMEIF5_Pos) /*!< 0x00000100 */
6294 #define DMA_HISR_DMEIF5 DMA_HISR_DMEIF5_Msk
6295 #define DMA_HISR_FEIF5_Pos (6U)
6296 #define DMA_HISR_FEIF5_Msk (0x1U << DMA_HISR_FEIF5_Pos) /*!< 0x00000040 */
6297 #define DMA_HISR_FEIF5 DMA_HISR_FEIF5_Msk
6298 #define DMA_HISR_TCIF4_Pos (5U)
6299 #define DMA_HISR_TCIF4_Msk (0x1U << DMA_HISR_TCIF4_Pos) /*!< 0x00000020 */
6300 #define DMA_HISR_TCIF4 DMA_HISR_TCIF4_Msk
6301 #define DMA_HISR_HTIF4_Pos (4U)
6302 #define DMA_HISR_HTIF4_Msk (0x1U << DMA_HISR_HTIF4_Pos) /*!< 0x00000010 */
6303 #define DMA_HISR_HTIF4 DMA_HISR_HTIF4_Msk
6304 #define DMA_HISR_TEIF4_Pos (3U)
6305 #define DMA_HISR_TEIF4_Msk (0x1U << DMA_HISR_TEIF4_Pos) /*!< 0x00000008 */
6306 #define DMA_HISR_TEIF4 DMA_HISR_TEIF4_Msk
6307 #define DMA_HISR_DMEIF4_Pos (2U)
6308 #define DMA_HISR_DMEIF4_Msk (0x1U << DMA_HISR_DMEIF4_Pos) /*!< 0x00000004 */
6309 #define DMA_HISR_DMEIF4 DMA_HISR_DMEIF4_Msk
6310 #define DMA_HISR_FEIF4_Pos (0U)
6311 #define DMA_HISR_FEIF4_Msk (0x1U << DMA_HISR_FEIF4_Pos) /*!< 0x00000001 */
6312 #define DMA_HISR_FEIF4 DMA_HISR_FEIF4_Msk
6313
6314 /******************** Bits definition for DMA_LIFCR register ****************/
6315 #define DMA_LIFCR_CTCIF3_Pos (27U)
6316 #define DMA_LIFCR_CTCIF3_Msk (0x1U << DMA_LIFCR_CTCIF3_Pos) /*!< 0x08000000 */
6317 #define DMA_LIFCR_CTCIF3 DMA_LIFCR_CTCIF3_Msk
6318 #define DMA_LIFCR_CHTIF3_Pos (26U)
6319 #define DMA_LIFCR_CHTIF3_Msk (0x1U << DMA_LIFCR_CHTIF3_Pos) /*!< 0x04000000 */
6320 #define DMA_LIFCR_CHTIF3 DMA_LIFCR_CHTIF3_Msk
6321 #define DMA_LIFCR_CTEIF3_Pos (25U)
6322 #define DMA_LIFCR_CTEIF3_Msk (0x1U << DMA_LIFCR_CTEIF3_Pos) /*!< 0x02000000 */
6323 #define DMA_LIFCR_CTEIF3 DMA_LIFCR_CTEIF3_Msk
6324 #define DMA_LIFCR_CDMEIF3_Pos (24U)
6325 #define DMA_LIFCR_CDMEIF3_Msk (0x1U << DMA_LIFCR_CDMEIF3_Pos) /*!< 0x01000000 */
6326 #define DMA_LIFCR_CDMEIF3 DMA_LIFCR_CDMEIF3_Msk
6327 #define DMA_LIFCR_CFEIF3_Pos (22U)
6328 #define DMA_LIFCR_CFEIF3_Msk (0x1U << DMA_LIFCR_CFEIF3_Pos) /*!< 0x00400000 */
6329 #define DMA_LIFCR_CFEIF3 DMA_LIFCR_CFEIF3_Msk
6330 #define DMA_LIFCR_CTCIF2_Pos (21U)
6331 #define DMA_LIFCR_CTCIF2_Msk (0x1U << DMA_LIFCR_CTCIF2_Pos) /*!< 0x00200000 */
6332 #define DMA_LIFCR_CTCIF2 DMA_LIFCR_CTCIF2_Msk
6333 #define DMA_LIFCR_CHTIF2_Pos (20U)
6334 #define DMA_LIFCR_CHTIF2_Msk (0x1U << DMA_LIFCR_CHTIF2_Pos) /*!< 0x00100000 */
6335 #define DMA_LIFCR_CHTIF2 DMA_LIFCR_CHTIF2_Msk
6336 #define DMA_LIFCR_CTEIF2_Pos (19U)
6337 #define DMA_LIFCR_CTEIF2_Msk (0x1U << DMA_LIFCR_CTEIF2_Pos) /*!< 0x00080000 */
6338 #define DMA_LIFCR_CTEIF2 DMA_LIFCR_CTEIF2_Msk
6339 #define DMA_LIFCR_CDMEIF2_Pos (18U)
6340 #define DMA_LIFCR_CDMEIF2_Msk (0x1U << DMA_LIFCR_CDMEIF2_Pos) /*!< 0x00040000 */
6341 #define DMA_LIFCR_CDMEIF2 DMA_LIFCR_CDMEIF2_Msk
6342 #define DMA_LIFCR_CFEIF2_Pos (16U)
6343 #define DMA_LIFCR_CFEIF2_Msk (0x1U << DMA_LIFCR_CFEIF2_Pos) /*!< 0x00010000 */
6344 #define DMA_LIFCR_CFEIF2 DMA_LIFCR_CFEIF2_Msk
6345 #define DMA_LIFCR_CTCIF1_Pos (11U)
6346 #define DMA_LIFCR_CTCIF1_Msk (0x1U << DMA_LIFCR_CTCIF1_Pos) /*!< 0x00000800 */
6347 #define DMA_LIFCR_CTCIF1 DMA_LIFCR_CTCIF1_Msk
6348 #define DMA_LIFCR_CHTIF1_Pos (10U)
6349 #define DMA_LIFCR_CHTIF1_Msk (0x1U << DMA_LIFCR_CHTIF1_Pos) /*!< 0x00000400 */
6350 #define DMA_LIFCR_CHTIF1 DMA_LIFCR_CHTIF1_Msk
6351 #define DMA_LIFCR_CTEIF1_Pos (9U)
6352 #define DMA_LIFCR_CTEIF1_Msk (0x1U << DMA_LIFCR_CTEIF1_Pos) /*!< 0x00000200 */
6353 #define DMA_LIFCR_CTEIF1 DMA_LIFCR_CTEIF1_Msk
6354 #define DMA_LIFCR_CDMEIF1_Pos (8U)
6355 #define DMA_LIFCR_CDMEIF1_Msk (0x1U << DMA_LIFCR_CDMEIF1_Pos) /*!< 0x00000100 */
6356 #define DMA_LIFCR_CDMEIF1 DMA_LIFCR_CDMEIF1_Msk
6357 #define DMA_LIFCR_CFEIF1_Pos (6U)
6358 #define DMA_LIFCR_CFEIF1_Msk (0x1U << DMA_LIFCR_CFEIF1_Pos) /*!< 0x00000040 */
6359 #define DMA_LIFCR_CFEIF1 DMA_LIFCR_CFEIF1_Msk
6360 #define DMA_LIFCR_CTCIF0_Pos (5U)
6361 #define DMA_LIFCR_CTCIF0_Msk (0x1U << DMA_LIFCR_CTCIF0_Pos) /*!< 0x00000020 */
6362 #define DMA_LIFCR_CTCIF0 DMA_LIFCR_CTCIF0_Msk
6363 #define DMA_LIFCR_CHTIF0_Pos (4U)
6364 #define DMA_LIFCR_CHTIF0_Msk (0x1U << DMA_LIFCR_CHTIF0_Pos) /*!< 0x00000010 */
6365 #define DMA_LIFCR_CHTIF0 DMA_LIFCR_CHTIF0_Msk
6366 #define DMA_LIFCR_CTEIF0_Pos (3U)
6367 #define DMA_LIFCR_CTEIF0_Msk (0x1U << DMA_LIFCR_CTEIF0_Pos) /*!< 0x00000008 */
6368 #define DMA_LIFCR_CTEIF0 DMA_LIFCR_CTEIF0_Msk
6369 #define DMA_LIFCR_CDMEIF0_Pos (2U)
6370 #define DMA_LIFCR_CDMEIF0_Msk (0x1U << DMA_LIFCR_CDMEIF0_Pos) /*!< 0x00000004 */
6371 #define DMA_LIFCR_CDMEIF0 DMA_LIFCR_CDMEIF0_Msk
6372 #define DMA_LIFCR_CFEIF0_Pos (0U)
6373 #define DMA_LIFCR_CFEIF0_Msk (0x1U << DMA_LIFCR_CFEIF0_Pos) /*!< 0x00000001 */
6374 #define DMA_LIFCR_CFEIF0 DMA_LIFCR_CFEIF0_Msk
6375
6376 /******************** Bits definition for DMA_HIFCR register ****************/
6377 #define DMA_HIFCR_CTCIF7_Pos (27U)
6378 #define DMA_HIFCR_CTCIF7_Msk (0x1U << DMA_HIFCR_CTCIF7_Pos) /*!< 0x08000000 */
6379 #define DMA_HIFCR_CTCIF7 DMA_HIFCR_CTCIF7_Msk
6380 #define DMA_HIFCR_CHTIF7_Pos (26U)
6381 #define DMA_HIFCR_CHTIF7_Msk (0x1U << DMA_HIFCR_CHTIF7_Pos) /*!< 0x04000000 */
6382 #define DMA_HIFCR_CHTIF7 DMA_HIFCR_CHTIF7_Msk
6383 #define DMA_HIFCR_CTEIF7_Pos (25U)
6384 #define DMA_HIFCR_CTEIF7_Msk (0x1U << DMA_HIFCR_CTEIF7_Pos) /*!< 0x02000000 */
6385 #define DMA_HIFCR_CTEIF7 DMA_HIFCR_CTEIF7_Msk
6386 #define DMA_HIFCR_CDMEIF7_Pos (24U)
6387 #define DMA_HIFCR_CDMEIF7_Msk (0x1U << DMA_HIFCR_CDMEIF7_Pos) /*!< 0x01000000 */
6388 #define DMA_HIFCR_CDMEIF7 DMA_HIFCR_CDMEIF7_Msk
6389 #define DMA_HIFCR_CFEIF7_Pos (22U)
6390 #define DMA_HIFCR_CFEIF7_Msk (0x1U << DMA_HIFCR_CFEIF7_Pos) /*!< 0x00400000 */
6391 #define DMA_HIFCR_CFEIF7 DMA_HIFCR_CFEIF7_Msk
6392 #define DMA_HIFCR_CTCIF6_Pos (21U)
6393 #define DMA_HIFCR_CTCIF6_Msk (0x1U << DMA_HIFCR_CTCIF6_Pos) /*!< 0x00200000 */
6394 #define DMA_HIFCR_CTCIF6 DMA_HIFCR_CTCIF6_Msk
6395 #define DMA_HIFCR_CHTIF6_Pos (20U)
6396 #define DMA_HIFCR_CHTIF6_Msk (0x1U << DMA_HIFCR_CHTIF6_Pos) /*!< 0x00100000 */
6397 #define DMA_HIFCR_CHTIF6 DMA_HIFCR_CHTIF6_Msk
6398 #define DMA_HIFCR_CTEIF6_Pos (19U)
6399 #define DMA_HIFCR_CTEIF6_Msk (0x1U << DMA_HIFCR_CTEIF6_Pos) /*!< 0x00080000 */
6400 #define DMA_HIFCR_CTEIF6 DMA_HIFCR_CTEIF6_Msk
6401 #define DMA_HIFCR_CDMEIF6_Pos (18U)
6402 #define DMA_HIFCR_CDMEIF6_Msk (0x1U << DMA_HIFCR_CDMEIF6_Pos) /*!< 0x00040000 */
6403 #define DMA_HIFCR_CDMEIF6 DMA_HIFCR_CDMEIF6_Msk
6404 #define DMA_HIFCR_CFEIF6_Pos (16U)
6405 #define DMA_HIFCR_CFEIF6_Msk (0x1U << DMA_HIFCR_CFEIF6_Pos) /*!< 0x00010000 */
6406 #define DMA_HIFCR_CFEIF6 DMA_HIFCR_CFEIF6_Msk
6407 #define DMA_HIFCR_CTCIF5_Pos (11U)
6408 #define DMA_HIFCR_CTCIF5_Msk (0x1U << DMA_HIFCR_CTCIF5_Pos) /*!< 0x00000800 */
6409 #define DMA_HIFCR_CTCIF5 DMA_HIFCR_CTCIF5_Msk
6410 #define DMA_HIFCR_CHTIF5_Pos (10U)
6411 #define DMA_HIFCR_CHTIF5_Msk (0x1U << DMA_HIFCR_CHTIF5_Pos) /*!< 0x00000400 */
6412 #define DMA_HIFCR_CHTIF5 DMA_HIFCR_CHTIF5_Msk
6413 #define DMA_HIFCR_CTEIF5_Pos (9U)
6414 #define DMA_HIFCR_CTEIF5_Msk (0x1U << DMA_HIFCR_CTEIF5_Pos) /*!< 0x00000200 */
6415 #define DMA_HIFCR_CTEIF5 DMA_HIFCR_CTEIF5_Msk
6416 #define DMA_HIFCR_CDMEIF5_Pos (8U)
6417 #define DMA_HIFCR_CDMEIF5_Msk (0x1U << DMA_HIFCR_CDMEIF5_Pos) /*!< 0x00000100 */
6418 #define DMA_HIFCR_CDMEIF5 DMA_HIFCR_CDMEIF5_Msk
6419 #define DMA_HIFCR_CFEIF5_Pos (6U)
6420 #define DMA_HIFCR_CFEIF5_Msk (0x1U << DMA_HIFCR_CFEIF5_Pos) /*!< 0x00000040 */
6421 #define DMA_HIFCR_CFEIF5 DMA_HIFCR_CFEIF5_Msk
6422 #define DMA_HIFCR_CTCIF4_Pos (5U)
6423 #define DMA_HIFCR_CTCIF4_Msk (0x1U << DMA_HIFCR_CTCIF4_Pos) /*!< 0x00000020 */
6424 #define DMA_HIFCR_CTCIF4 DMA_HIFCR_CTCIF4_Msk
6425 #define DMA_HIFCR_CHTIF4_Pos (4U)
6426 #define DMA_HIFCR_CHTIF4_Msk (0x1U << DMA_HIFCR_CHTIF4_Pos) /*!< 0x00000010 */
6427 #define DMA_HIFCR_CHTIF4 DMA_HIFCR_CHTIF4_Msk
6428 #define DMA_HIFCR_CTEIF4_Pos (3U)
6429 #define DMA_HIFCR_CTEIF4_Msk (0x1U << DMA_HIFCR_CTEIF4_Pos) /*!< 0x00000008 */
6430 #define DMA_HIFCR_CTEIF4 DMA_HIFCR_CTEIF4_Msk
6431 #define DMA_HIFCR_CDMEIF4_Pos (2U)
6432 #define DMA_HIFCR_CDMEIF4_Msk (0x1U << DMA_HIFCR_CDMEIF4_Pos) /*!< 0x00000004 */
6433 #define DMA_HIFCR_CDMEIF4 DMA_HIFCR_CDMEIF4_Msk
6434 #define DMA_HIFCR_CFEIF4_Pos (0U)
6435 #define DMA_HIFCR_CFEIF4_Msk (0x1U << DMA_HIFCR_CFEIF4_Pos) /*!< 0x00000001 */
6436 #define DMA_HIFCR_CFEIF4 DMA_HIFCR_CFEIF4_Msk
6437
6438 /****************** Bit definition for DMA_SxPAR register ********************/
6439 #define DMA_SxPAR_PA_Pos (0U)
6440 #define DMA_SxPAR_PA_Msk (0xFFFFFFFFU << DMA_SxPAR_PA_Pos) /*!< 0xFFFFFFFF */
6441 #define DMA_SxPAR_PA DMA_SxPAR_PA_Msk /*!< Peripheral Address */
6442
6443 /****************** Bit definition for DMA_SxM0AR register ********************/
6444 #define DMA_SxM0AR_M0A_Pos (0U)
6445 #define DMA_SxM0AR_M0A_Msk (0xFFFFFFFFU << DMA_SxM0AR_M0A_Pos) /*!< 0xFFFFFFFF */
6446 #define DMA_SxM0AR_M0A DMA_SxM0AR_M0A_Msk /*!< Memory Address */
6447
6448 /****************** Bit definition for DMA_SxM1AR register ********************/
6449 #define DMA_SxM1AR_M1A_Pos (0U)
6450 #define DMA_SxM1AR_M1A_Msk (0xFFFFFFFFU << DMA_SxM1AR_M1A_Pos) /*!< 0xFFFFFFFF */
6451 #define DMA_SxM1AR_M1A DMA_SxM1AR_M1A_Msk /*!< Memory Address */
6452
6453
6454 /******************************************************************************/
6455 /* */
6456 /* AHB Master DMA2D Controller (DMA2D) */
6457 /* */
6458 /******************************************************************************/
6459
6460 /******************** Bit definition for DMA2D_CR register ******************/
6461
6462 #define DMA2D_CR_START_Pos (0U)
6463 #define DMA2D_CR_START_Msk (0x1U << DMA2D_CR_START_Pos) /*!< 0x00000001 */
6464 #define DMA2D_CR_START DMA2D_CR_START_Msk /*!< Start transfer */
6465 #define DMA2D_CR_SUSP_Pos (1U)
6466 #define DMA2D_CR_SUSP_Msk (0x1U << DMA2D_CR_SUSP_Pos) /*!< 0x00000002 */
6467 #define DMA2D_CR_SUSP DMA2D_CR_SUSP_Msk /*!< Suspend transfer */
6468 #define DMA2D_CR_ABORT_Pos (2U)
6469 #define DMA2D_CR_ABORT_Msk (0x1U << DMA2D_CR_ABORT_Pos) /*!< 0x00000004 */
6470 #define DMA2D_CR_ABORT DMA2D_CR_ABORT_Msk /*!< Abort transfer */
6471 #define DMA2D_CR_TEIE_Pos (8U)
6472 #define DMA2D_CR_TEIE_Msk (0x1U << DMA2D_CR_TEIE_Pos) /*!< 0x00000100 */
6473 #define DMA2D_CR_TEIE DMA2D_CR_TEIE_Msk /*!< Transfer Error Interrupt Enable */
6474 #define DMA2D_CR_TCIE_Pos (9U)
6475 #define DMA2D_CR_TCIE_Msk (0x1U << DMA2D_CR_TCIE_Pos) /*!< 0x00000200 */
6476 #define DMA2D_CR_TCIE DMA2D_CR_TCIE_Msk /*!< Transfer Complete Interrupt Enable */
6477 #define DMA2D_CR_TWIE_Pos (10U)
6478 #define DMA2D_CR_TWIE_Msk (0x1U << DMA2D_CR_TWIE_Pos) /*!< 0x00000400 */
6479 #define DMA2D_CR_TWIE DMA2D_CR_TWIE_Msk /*!< Transfer Watermark Interrupt Enable */
6480 #define DMA2D_CR_CAEIE_Pos (11U)
6481 #define DMA2D_CR_CAEIE_Msk (0x1U << DMA2D_CR_CAEIE_Pos) /*!< 0x00000800 */
6482 #define DMA2D_CR_CAEIE DMA2D_CR_CAEIE_Msk /*!< CLUT Access Error Interrupt Enable */
6483 #define DMA2D_CR_CTCIE_Pos (12U)
6484 #define DMA2D_CR_CTCIE_Msk (0x1U << DMA2D_CR_CTCIE_Pos) /*!< 0x00001000 */
6485 #define DMA2D_CR_CTCIE DMA2D_CR_CTCIE_Msk /*!< CLUT Transfer Complete Interrupt Enable */
6486 #define DMA2D_CR_CEIE_Pos (13U)
6487 #define DMA2D_CR_CEIE_Msk (0x1U << DMA2D_CR_CEIE_Pos) /*!< 0x00002000 */
6488 #define DMA2D_CR_CEIE DMA2D_CR_CEIE_Msk /*!< Configuration Error Interrupt Enable */
6489 #define DMA2D_CR_MODE_Pos (16U)
6490 #define DMA2D_CR_MODE_Msk (0x3U << DMA2D_CR_MODE_Pos) /*!< 0x00030000 */
6491 #define DMA2D_CR_MODE DMA2D_CR_MODE_Msk /*!< DMA2D Mode[1:0] */
6492 #define DMA2D_CR_MODE_0 (0x1U << DMA2D_CR_MODE_Pos) /*!< 0x00010000 */
6493 #define DMA2D_CR_MODE_1 (0x2U << DMA2D_CR_MODE_Pos) /*!< 0x00020000 */
6494
6495 /******************** Bit definition for DMA2D_ISR register *****************/
6496
6497 #define DMA2D_ISR_TEIF_Pos (0U)
6498 #define DMA2D_ISR_TEIF_Msk (0x1U << DMA2D_ISR_TEIF_Pos) /*!< 0x00000001 */
6499 #define DMA2D_ISR_TEIF DMA2D_ISR_TEIF_Msk /*!< Transfer Error Interrupt Flag */
6500 #define DMA2D_ISR_TCIF_Pos (1U)
6501 #define DMA2D_ISR_TCIF_Msk (0x1U << DMA2D_ISR_TCIF_Pos) /*!< 0x00000002 */
6502 #define DMA2D_ISR_TCIF DMA2D_ISR_TCIF_Msk /*!< Transfer Complete Interrupt Flag */
6503 #define DMA2D_ISR_TWIF_Pos (2U)
6504 #define DMA2D_ISR_TWIF_Msk (0x1U << DMA2D_ISR_TWIF_Pos) /*!< 0x00000004 */
6505 #define DMA2D_ISR_TWIF DMA2D_ISR_TWIF_Msk /*!< Transfer Watermark Interrupt Flag */
6506 #define DMA2D_ISR_CAEIF_Pos (3U)
6507 #define DMA2D_ISR_CAEIF_Msk (0x1U << DMA2D_ISR_CAEIF_Pos) /*!< 0x00000008 */
6508 #define DMA2D_ISR_CAEIF DMA2D_ISR_CAEIF_Msk /*!< CLUT Access Error Interrupt Flag */
6509 #define DMA2D_ISR_CTCIF_Pos (4U)
6510 #define DMA2D_ISR_CTCIF_Msk (0x1U << DMA2D_ISR_CTCIF_Pos) /*!< 0x00000010 */
6511 #define DMA2D_ISR_CTCIF DMA2D_ISR_CTCIF_Msk /*!< CLUT Transfer Complete Interrupt Flag */
6512 #define DMA2D_ISR_CEIF_Pos (5U)
6513 #define DMA2D_ISR_CEIF_Msk (0x1U << DMA2D_ISR_CEIF_Pos) /*!< 0x00000020 */
6514 #define DMA2D_ISR_CEIF DMA2D_ISR_CEIF_Msk /*!< Configuration Error Interrupt Flag */
6515
6516 /******************** Bit definition for DMA2D_IFCR register ****************/
6517
6518 #define DMA2D_IFCR_CTEIF_Pos (0U)
6519 #define DMA2D_IFCR_CTEIF_Msk (0x1U << DMA2D_IFCR_CTEIF_Pos) /*!< 0x00000001 */
6520 #define DMA2D_IFCR_CTEIF DMA2D_IFCR_CTEIF_Msk /*!< Clears Transfer Error Interrupt Flag */
6521 #define DMA2D_IFCR_CTCIF_Pos (1U)
6522 #define DMA2D_IFCR_CTCIF_Msk (0x1U << DMA2D_IFCR_CTCIF_Pos) /*!< 0x00000002 */
6523 #define DMA2D_IFCR_CTCIF DMA2D_IFCR_CTCIF_Msk /*!< Clears Transfer Complete Interrupt Flag */
6524 #define DMA2D_IFCR_CTWIF_Pos (2U)
6525 #define DMA2D_IFCR_CTWIF_Msk (0x1U << DMA2D_IFCR_CTWIF_Pos) /*!< 0x00000004 */
6526 #define DMA2D_IFCR_CTWIF DMA2D_IFCR_CTWIF_Msk /*!< Clears Transfer Watermark Interrupt Flag */
6527 #define DMA2D_IFCR_CAECIF_Pos (3U)
6528 #define DMA2D_IFCR_CAECIF_Msk (0x1U << DMA2D_IFCR_CAECIF_Pos) /*!< 0x00000008 */
6529 #define DMA2D_IFCR_CAECIF DMA2D_IFCR_CAECIF_Msk /*!< Clears CLUT Access Error Interrupt Flag */
6530 #define DMA2D_IFCR_CCTCIF_Pos (4U)
6531 #define DMA2D_IFCR_CCTCIF_Msk (0x1U << DMA2D_IFCR_CCTCIF_Pos) /*!< 0x00000010 */
6532 #define DMA2D_IFCR_CCTCIF DMA2D_IFCR_CCTCIF_Msk /*!< Clears CLUT Transfer Complete Interrupt Flag */
6533 #define DMA2D_IFCR_CCEIF_Pos (5U)
6534 #define DMA2D_IFCR_CCEIF_Msk (0x1U << DMA2D_IFCR_CCEIF_Pos) /*!< 0x00000020 */
6535 #define DMA2D_IFCR_CCEIF DMA2D_IFCR_CCEIF_Msk /*!< Clears Configuration Error Interrupt Flag */
6536
6537 /* Legacy defines */
6538 #define DMA2D_IFSR_CTEIF DMA2D_IFCR_CTEIF /*!< Clears Transfer Error Interrupt Flag */
6539 #define DMA2D_IFSR_CTCIF DMA2D_IFCR_CTCIF /*!< Clears Transfer Complete Interrupt Flag */
6540 #define DMA2D_IFSR_CTWIF DMA2D_IFCR_CTWIF /*!< Clears Transfer Watermark Interrupt Flag */
6541 #define DMA2D_IFSR_CCAEIF DMA2D_IFCR_CAECIF /*!< Clears CLUT Access Error Interrupt Flag */
6542 #define DMA2D_IFSR_CCTCIF DMA2D_IFCR_CCTCIF /*!< Clears CLUT Transfer Complete Interrupt Flag */
6543 #define DMA2D_IFSR_CCEIF DMA2D_IFCR_CCEIF /*!< Clears Configuration Error Interrupt Flag */
6544
6545 /******************** Bit definition for DMA2D_FGMAR register ***************/
6546
6547 #define DMA2D_FGMAR_MA_Pos (0U)
6548 #define DMA2D_FGMAR_MA_Msk (0xFFFFFFFFU << DMA2D_FGMAR_MA_Pos) /*!< 0xFFFFFFFF */
6549 #define DMA2D_FGMAR_MA DMA2D_FGMAR_MA_Msk /*!< Memory Address */
6550
6551 /******************** Bit definition for DMA2D_FGOR register ****************/
6552
6553 #define DMA2D_FGOR_LO_Pos (0U)
6554 #define DMA2D_FGOR_LO_Msk (0x3FFFU << DMA2D_FGOR_LO_Pos) /*!< 0x00003FFF */
6555 #define DMA2D_FGOR_LO DMA2D_FGOR_LO_Msk /*!< Line Offset */
6556
6557 /******************** Bit definition for DMA2D_BGMAR register ***************/
6558
6559 #define DMA2D_BGMAR_MA_Pos (0U)
6560 #define DMA2D_BGMAR_MA_Msk (0xFFFFFFFFU << DMA2D_BGMAR_MA_Pos) /*!< 0xFFFFFFFF */
6561 #define DMA2D_BGMAR_MA DMA2D_BGMAR_MA_Msk /*!< Memory Address */
6562
6563 /******************** Bit definition for DMA2D_BGOR register ****************/
6564
6565 #define DMA2D_BGOR_LO_Pos (0U)
6566 #define DMA2D_BGOR_LO_Msk (0x3FFFU << DMA2D_BGOR_LO_Pos) /*!< 0x00003FFF */
6567 #define DMA2D_BGOR_LO DMA2D_BGOR_LO_Msk /*!< Line Offset */
6568
6569 /******************** Bit definition for DMA2D_FGPFCCR register *************/
6570
6571 #define DMA2D_FGPFCCR_CM_Pos (0U)
6572 #define DMA2D_FGPFCCR_CM_Msk (0xFU << DMA2D_FGPFCCR_CM_Pos) /*!< 0x0000000F */
6573 #define DMA2D_FGPFCCR_CM DMA2D_FGPFCCR_CM_Msk /*!< Input color mode CM[3:0] */
6574 #define DMA2D_FGPFCCR_CM_0 (0x1U << DMA2D_FGPFCCR_CM_Pos) /*!< 0x00000001 */
6575 #define DMA2D_FGPFCCR_CM_1 (0x2U << DMA2D_FGPFCCR_CM_Pos) /*!< 0x00000002 */
6576 #define DMA2D_FGPFCCR_CM_2 (0x4U << DMA2D_FGPFCCR_CM_Pos) /*!< 0x00000004 */
6577 #define DMA2D_FGPFCCR_CM_3 (0x8U << DMA2D_FGPFCCR_CM_Pos) /*!< 0x00000008 */
6578 #define DMA2D_FGPFCCR_CCM_Pos (4U)
6579 #define DMA2D_FGPFCCR_CCM_Msk (0x1U << DMA2D_FGPFCCR_CCM_Pos) /*!< 0x00000010 */
6580 #define DMA2D_FGPFCCR_CCM DMA2D_FGPFCCR_CCM_Msk /*!< CLUT Color mode */
6581 #define DMA2D_FGPFCCR_START_Pos (5U)
6582 #define DMA2D_FGPFCCR_START_Msk (0x1U << DMA2D_FGPFCCR_START_Pos) /*!< 0x00000020 */
6583 #define DMA2D_FGPFCCR_START DMA2D_FGPFCCR_START_Msk /*!< Start */
6584 #define DMA2D_FGPFCCR_CS_Pos (8U)
6585 #define DMA2D_FGPFCCR_CS_Msk (0xFFU << DMA2D_FGPFCCR_CS_Pos) /*!< 0x0000FF00 */
6586 #define DMA2D_FGPFCCR_CS DMA2D_FGPFCCR_CS_Msk /*!< CLUT size */
6587 #define DMA2D_FGPFCCR_AM_Pos (16U)
6588 #define DMA2D_FGPFCCR_AM_Msk (0x3U << DMA2D_FGPFCCR_AM_Pos) /*!< 0x00030000 */
6589 #define DMA2D_FGPFCCR_AM DMA2D_FGPFCCR_AM_Msk /*!< Alpha mode AM[1:0] */
6590 #define DMA2D_FGPFCCR_AM_0 (0x1U << DMA2D_FGPFCCR_AM_Pos) /*!< 0x00010000 */
6591 #define DMA2D_FGPFCCR_AM_1 (0x2U << DMA2D_FGPFCCR_AM_Pos) /*!< 0x00020000 */
6592 #define DMA2D_FGPFCCR_ALPHA_Pos (24U)
6593 #define DMA2D_FGPFCCR_ALPHA_Msk (0xFFU << DMA2D_FGPFCCR_ALPHA_Pos) /*!< 0xFF000000 */
6594 #define DMA2D_FGPFCCR_ALPHA DMA2D_FGPFCCR_ALPHA_Msk /*!< Alpha value */
6595
6596 /******************** Bit definition for DMA2D_FGCOLR register **************/
6597
6598 #define DMA2D_FGCOLR_BLUE_Pos (0U)
6599 #define DMA2D_FGCOLR_BLUE_Msk (0xFFU << DMA2D_FGCOLR_BLUE_Pos) /*!< 0x000000FF */
6600 #define DMA2D_FGCOLR_BLUE DMA2D_FGCOLR_BLUE_Msk /*!< Blue Value */
6601 #define DMA2D_FGCOLR_GREEN_Pos (8U)
6602 #define DMA2D_FGCOLR_GREEN_Msk (0xFFU << DMA2D_FGCOLR_GREEN_Pos) /*!< 0x0000FF00 */
6603 #define DMA2D_FGCOLR_GREEN DMA2D_FGCOLR_GREEN_Msk /*!< Green Value */
6604 #define DMA2D_FGCOLR_RED_Pos (16U)
6605 #define DMA2D_FGCOLR_RED_Msk (0xFFU << DMA2D_FGCOLR_RED_Pos) /*!< 0x00FF0000 */
6606 #define DMA2D_FGCOLR_RED DMA2D_FGCOLR_RED_Msk /*!< Red Value */
6607
6608 /******************** Bit definition for DMA2D_BGPFCCR register *************/
6609
6610 #define DMA2D_BGPFCCR_CM_Pos (0U)
6611 #define DMA2D_BGPFCCR_CM_Msk (0xFU << DMA2D_BGPFCCR_CM_Pos) /*!< 0x0000000F */
6612 #define DMA2D_BGPFCCR_CM DMA2D_BGPFCCR_CM_Msk /*!< Input color mode CM[3:0] */
6613 #define DMA2D_BGPFCCR_CM_0 (0x1U << DMA2D_BGPFCCR_CM_Pos) /*!< 0x00000001 */
6614 #define DMA2D_BGPFCCR_CM_1 (0x2U << DMA2D_BGPFCCR_CM_Pos) /*!< 0x00000002 */
6615 #define DMA2D_BGPFCCR_CM_2 (0x4U << DMA2D_BGPFCCR_CM_Pos) /*!< 0x00000004 */
6616 #define DMA2D_BGPFCCR_CM_3 0x00000008U /*!< Input color mode CM bit 3 */
6617 #define DMA2D_BGPFCCR_CCM_Pos (4U)
6618 #define DMA2D_BGPFCCR_CCM_Msk (0x1U << DMA2D_BGPFCCR_CCM_Pos) /*!< 0x00000010 */
6619 #define DMA2D_BGPFCCR_CCM DMA2D_BGPFCCR_CCM_Msk /*!< CLUT Color mode */
6620 #define DMA2D_BGPFCCR_START_Pos (5U)
6621 #define DMA2D_BGPFCCR_START_Msk (0x1U << DMA2D_BGPFCCR_START_Pos) /*!< 0x00000020 */
6622 #define DMA2D_BGPFCCR_START DMA2D_BGPFCCR_START_Msk /*!< Start */
6623 #define DMA2D_BGPFCCR_CS_Pos (8U)
6624 #define DMA2D_BGPFCCR_CS_Msk (0xFFU << DMA2D_BGPFCCR_CS_Pos) /*!< 0x0000FF00 */
6625 #define DMA2D_BGPFCCR_CS DMA2D_BGPFCCR_CS_Msk /*!< CLUT size */
6626 #define DMA2D_BGPFCCR_AM_Pos (16U)
6627 #define DMA2D_BGPFCCR_AM_Msk (0x3U << DMA2D_BGPFCCR_AM_Pos) /*!< 0x00030000 */
6628 #define DMA2D_BGPFCCR_AM DMA2D_BGPFCCR_AM_Msk /*!< Alpha mode AM[1:0] */
6629 #define DMA2D_BGPFCCR_AM_0 (0x1U << DMA2D_BGPFCCR_AM_Pos) /*!< 0x00010000 */
6630 #define DMA2D_BGPFCCR_AM_1 (0x2U << DMA2D_BGPFCCR_AM_Pos) /*!< 0x00020000 */
6631 #define DMA2D_BGPFCCR_ALPHA_Pos (24U)
6632 #define DMA2D_BGPFCCR_ALPHA_Msk (0xFFU << DMA2D_BGPFCCR_ALPHA_Pos) /*!< 0xFF000000 */
6633 #define DMA2D_BGPFCCR_ALPHA DMA2D_BGPFCCR_ALPHA_Msk /*!< background Input Alpha value */
6634
6635 /******************** Bit definition for DMA2D_BGCOLR register **************/
6636
6637 #define DMA2D_BGCOLR_BLUE_Pos (0U)
6638 #define DMA2D_BGCOLR_BLUE_Msk (0xFFU << DMA2D_BGCOLR_BLUE_Pos) /*!< 0x000000FF */
6639 #define DMA2D_BGCOLR_BLUE DMA2D_BGCOLR_BLUE_Msk /*!< Blue Value */
6640 #define DMA2D_BGCOLR_GREEN_Pos (8U)
6641 #define DMA2D_BGCOLR_GREEN_Msk (0xFFU << DMA2D_BGCOLR_GREEN_Pos) /*!< 0x0000FF00 */
6642 #define DMA2D_BGCOLR_GREEN DMA2D_BGCOLR_GREEN_Msk /*!< Green Value */
6643 #define DMA2D_BGCOLR_RED_Pos (16U)
6644 #define DMA2D_BGCOLR_RED_Msk (0xFFU << DMA2D_BGCOLR_RED_Pos) /*!< 0x00FF0000 */
6645 #define DMA2D_BGCOLR_RED DMA2D_BGCOLR_RED_Msk /*!< Red Value */
6646
6647 /******************** Bit definition for DMA2D_FGCMAR register **************/
6648
6649 #define DMA2D_FGCMAR_MA_Pos (0U)
6650 #define DMA2D_FGCMAR_MA_Msk (0xFFFFFFFFU << DMA2D_FGCMAR_MA_Pos) /*!< 0xFFFFFFFF */
6651 #define DMA2D_FGCMAR_MA DMA2D_FGCMAR_MA_Msk /*!< Memory Address */
6652
6653 /******************** Bit definition for DMA2D_BGCMAR register **************/
6654
6655 #define DMA2D_BGCMAR_MA_Pos (0U)
6656 #define DMA2D_BGCMAR_MA_Msk (0xFFFFFFFFU << DMA2D_BGCMAR_MA_Pos) /*!< 0xFFFFFFFF */
6657 #define DMA2D_BGCMAR_MA DMA2D_BGCMAR_MA_Msk /*!< Memory Address */
6658
6659 /******************** Bit definition for DMA2D_OPFCCR register **************/
6660
6661 #define DMA2D_OPFCCR_CM_Pos (0U)
6662 #define DMA2D_OPFCCR_CM_Msk (0x7U << DMA2D_OPFCCR_CM_Pos) /*!< 0x00000007 */
6663 #define DMA2D_OPFCCR_CM DMA2D_OPFCCR_CM_Msk /*!< Color mode CM[2:0] */
6664 #define DMA2D_OPFCCR_CM_0 (0x1U << DMA2D_OPFCCR_CM_Pos) /*!< 0x00000001 */
6665 #define DMA2D_OPFCCR_CM_1 (0x2U << DMA2D_OPFCCR_CM_Pos) /*!< 0x00000002 */
6666 #define DMA2D_OPFCCR_CM_2 (0x4U << DMA2D_OPFCCR_CM_Pos) /*!< 0x00000004 */
6667
6668 /******************** Bit definition for DMA2D_OCOLR register ***************/
6669
6670 /*!<Mode_ARGB8888/RGB888 */
6671
6672 #define DMA2D_OCOLR_BLUE_1 0x000000FFU /*!< BLUE Value */
6673 #define DMA2D_OCOLR_GREEN_1 0x0000FF00U /*!< GREEN Value */
6674 #define DMA2D_OCOLR_RED_1 0x00FF0000U /*!< Red Value */
6675 #define DMA2D_OCOLR_ALPHA_1 0xFF000000U /*!< Alpha Channel Value */
6676
6677 /*!<Mode_RGB565 */
6678 #define DMA2D_OCOLR_BLUE_2 0x0000001FU /*!< BLUE Value */
6679 #define DMA2D_OCOLR_GREEN_2 0x000007E0U /*!< GREEN Value */
6680 #define DMA2D_OCOLR_RED_2 0x0000F800U /*!< Red Value */
6681
6682 /*!<Mode_ARGB1555 */
6683 #define DMA2D_OCOLR_BLUE_3 0x0000001FU /*!< BLUE Value */
6684 #define DMA2D_OCOLR_GREEN_3 0x000003E0U /*!< GREEN Value */
6685 #define DMA2D_OCOLR_RED_3 0x00007C00U /*!< Red Value */
6686 #define DMA2D_OCOLR_ALPHA_3 0x00008000U /*!< Alpha Channel Value */
6687
6688 /*!<Mode_ARGB4444 */
6689 #define DMA2D_OCOLR_BLUE_4 0x0000000FU /*!< BLUE Value */
6690 #define DMA2D_OCOLR_GREEN_4 0x000000F0U /*!< GREEN Value */
6691 #define DMA2D_OCOLR_RED_4 0x00000F00U /*!< Red Value */
6692 #define DMA2D_OCOLR_ALPHA_4 0x0000F000U /*!< Alpha Channel Value */
6693
6694 /******************** Bit definition for DMA2D_OMAR register ****************/
6695
6696 #define DMA2D_OMAR_MA_Pos (0U)
6697 #define DMA2D_OMAR_MA_Msk (0xFFFFFFFFU << DMA2D_OMAR_MA_Pos) /*!< 0xFFFFFFFF */
6698 #define DMA2D_OMAR_MA DMA2D_OMAR_MA_Msk /*!< Memory Address */
6699
6700 /******************** Bit definition for DMA2D_OOR register *****************/
6701
6702 #define DMA2D_OOR_LO_Pos (0U)
6703 #define DMA2D_OOR_LO_Msk (0x3FFFU << DMA2D_OOR_LO_Pos) /*!< 0x00003FFF */
6704 #define DMA2D_OOR_LO DMA2D_OOR_LO_Msk /*!< Line Offset */
6705
6706 /******************** Bit definition for DMA2D_NLR register *****************/
6707
6708 #define DMA2D_NLR_NL_Pos (0U)
6709 #define DMA2D_NLR_NL_Msk (0xFFFFU << DMA2D_NLR_NL_Pos) /*!< 0x0000FFFF */
6710 #define DMA2D_NLR_NL DMA2D_NLR_NL_Msk /*!< Number of Lines */
6711 #define DMA2D_NLR_PL_Pos (16U)
6712 #define DMA2D_NLR_PL_Msk (0x3FFFU << DMA2D_NLR_PL_Pos) /*!< 0x3FFF0000 */
6713 #define DMA2D_NLR_PL DMA2D_NLR_PL_Msk /*!< Pixel per Lines */
6714
6715 /******************** Bit definition for DMA2D_LWR register *****************/
6716
6717 #define DMA2D_LWR_LW_Pos (0U)
6718 #define DMA2D_LWR_LW_Msk (0xFFFFU << DMA2D_LWR_LW_Pos) /*!< 0x0000FFFF */
6719 #define DMA2D_LWR_LW DMA2D_LWR_LW_Msk /*!< Line Watermark */
6720
6721 /******************** Bit definition for DMA2D_AMTCR register ***************/
6722
6723 #define DMA2D_AMTCR_EN_Pos (0U)
6724 #define DMA2D_AMTCR_EN_Msk (0x1U << DMA2D_AMTCR_EN_Pos) /*!< 0x00000001 */
6725 #define DMA2D_AMTCR_EN DMA2D_AMTCR_EN_Msk /*!< Enable */
6726 #define DMA2D_AMTCR_DT_Pos (8U)
6727 #define DMA2D_AMTCR_DT_Msk (0xFFU << DMA2D_AMTCR_DT_Pos) /*!< 0x0000FF00 */
6728 #define DMA2D_AMTCR_DT DMA2D_AMTCR_DT_Msk /*!< Dead Time */
6729
6730 /******************** Bit definition for DMA2D_FGCLUT register **************/
6731
6732 /******************** Bit definition for DMA2D_BGCLUT register **************/
6733
6734
6735 /******************************************************************************/
6736 /* */
6737 /* Display Serial Interface (DSI) */
6738 /* */
6739 /******************************************************************************/
6740 /******************* Bit definition for DSI_VR register *****************/
6741 #define DSI_VR_Pos (1U)
6742 #define DSI_VR_Msk (0x18999815U << DSI_VR_Pos) /*!< 0x3133302A */
6743 #define DSI_VR DSI_VR_Msk /*!< DSI Host Version */
6744
6745 /******************* Bit definition for DSI_CR register *****************/
6746 #define DSI_CR_EN_Pos (0U)
6747 #define DSI_CR_EN_Msk (0x1U << DSI_CR_EN_Pos) /*!< 0x00000001 */
6748 #define DSI_CR_EN DSI_CR_EN_Msk /*!< DSI Host power up and reset */
6749
6750 /******************* Bit definition for DSI_CCR register ****************/
6751 #define DSI_CCR_TXECKDIV_Pos (0U)
6752 #define DSI_CCR_TXECKDIV_Msk (0xFFU << DSI_CCR_TXECKDIV_Pos) /*!< 0x000000FF */
6753 #define DSI_CCR_TXECKDIV DSI_CCR_TXECKDIV_Msk /*!< TX Escape Clock Division */
6754 #define DSI_CCR_TXECKDIV0_Pos (0U)
6755 #define DSI_CCR_TXECKDIV0_Msk (0x1U << DSI_CCR_TXECKDIV0_Pos) /*!< 0x00000001 */
6756 #define DSI_CCR_TXECKDIV0 DSI_CCR_TXECKDIV0_Msk
6757 #define DSI_CCR_TXECKDIV1_Pos (1U)
6758 #define DSI_CCR_TXECKDIV1_Msk (0x1U << DSI_CCR_TXECKDIV1_Pos) /*!< 0x00000002 */
6759 #define DSI_CCR_TXECKDIV1 DSI_CCR_TXECKDIV1_Msk
6760 #define DSI_CCR_TXECKDIV2_Pos (2U)
6761 #define DSI_CCR_TXECKDIV2_Msk (0x1U << DSI_CCR_TXECKDIV2_Pos) /*!< 0x00000004 */
6762 #define DSI_CCR_TXECKDIV2 DSI_CCR_TXECKDIV2_Msk
6763 #define DSI_CCR_TXECKDIV3_Pos (3U)
6764 #define DSI_CCR_TXECKDIV3_Msk (0x1U << DSI_CCR_TXECKDIV3_Pos) /*!< 0x00000008 */
6765 #define DSI_CCR_TXECKDIV3 DSI_CCR_TXECKDIV3_Msk
6766 #define DSI_CCR_TXECKDIV4_Pos (4U)
6767 #define DSI_CCR_TXECKDIV4_Msk (0x1U << DSI_CCR_TXECKDIV4_Pos) /*!< 0x00000010 */
6768 #define DSI_CCR_TXECKDIV4 DSI_CCR_TXECKDIV4_Msk
6769 #define DSI_CCR_TXECKDIV5_Pos (5U)
6770 #define DSI_CCR_TXECKDIV5_Msk (0x1U << DSI_CCR_TXECKDIV5_Pos) /*!< 0x00000020 */
6771 #define DSI_CCR_TXECKDIV5 DSI_CCR_TXECKDIV5_Msk
6772 #define DSI_CCR_TXECKDIV6_Pos (6U)
6773 #define DSI_CCR_TXECKDIV6_Msk (0x1U << DSI_CCR_TXECKDIV6_Pos) /*!< 0x00000040 */
6774 #define DSI_CCR_TXECKDIV6 DSI_CCR_TXECKDIV6_Msk
6775 #define DSI_CCR_TXECKDIV7_Pos (7U)
6776 #define DSI_CCR_TXECKDIV7_Msk (0x1U << DSI_CCR_TXECKDIV7_Pos) /*!< 0x00000080 */
6777 #define DSI_CCR_TXECKDIV7 DSI_CCR_TXECKDIV7_Msk
6778
6779 #define DSI_CCR_TOCKDIV_Pos (8U)
6780 #define DSI_CCR_TOCKDIV_Msk (0xFFU << DSI_CCR_TOCKDIV_Pos) /*!< 0x0000FF00 */
6781 #define DSI_CCR_TOCKDIV DSI_CCR_TOCKDIV_Msk /*!< Timeout Clock Division */
6782 #define DSI_CCR_TOCKDIV0_Pos (8U)
6783 #define DSI_CCR_TOCKDIV0_Msk (0x1U << DSI_CCR_TOCKDIV0_Pos) /*!< 0x00000100 */
6784 #define DSI_CCR_TOCKDIV0 DSI_CCR_TOCKDIV0_Msk
6785 #define DSI_CCR_TOCKDIV1_Pos (9U)
6786 #define DSI_CCR_TOCKDIV1_Msk (0x1U << DSI_CCR_TOCKDIV1_Pos) /*!< 0x00000200 */
6787 #define DSI_CCR_TOCKDIV1 DSI_CCR_TOCKDIV1_Msk
6788 #define DSI_CCR_TOCKDIV2_Pos (10U)
6789 #define DSI_CCR_TOCKDIV2_Msk (0x1U << DSI_CCR_TOCKDIV2_Pos) /*!< 0x00000400 */
6790 #define DSI_CCR_TOCKDIV2 DSI_CCR_TOCKDIV2_Msk
6791 #define DSI_CCR_TOCKDIV3_Pos (11U)
6792 #define DSI_CCR_TOCKDIV3_Msk (0x1U << DSI_CCR_TOCKDIV3_Pos) /*!< 0x00000800 */
6793 #define DSI_CCR_TOCKDIV3 DSI_CCR_TOCKDIV3_Msk
6794 #define DSI_CCR_TOCKDIV4_Pos (12U)
6795 #define DSI_CCR_TOCKDIV4_Msk (0x1U << DSI_CCR_TOCKDIV4_Pos) /*!< 0x00001000 */
6796 #define DSI_CCR_TOCKDIV4 DSI_CCR_TOCKDIV4_Msk
6797 #define DSI_CCR_TOCKDIV5_Pos (13U)
6798 #define DSI_CCR_TOCKDIV5_Msk (0x1U << DSI_CCR_TOCKDIV5_Pos) /*!< 0x00002000 */
6799 #define DSI_CCR_TOCKDIV5 DSI_CCR_TOCKDIV5_Msk
6800 #define DSI_CCR_TOCKDIV6_Pos (14U)
6801 #define DSI_CCR_TOCKDIV6_Msk (0x1U << DSI_CCR_TOCKDIV6_Pos) /*!< 0x00004000 */
6802 #define DSI_CCR_TOCKDIV6 DSI_CCR_TOCKDIV6_Msk
6803 #define DSI_CCR_TOCKDIV7_Pos (15U)
6804 #define DSI_CCR_TOCKDIV7_Msk (0x1U << DSI_CCR_TOCKDIV7_Pos) /*!< 0x00008000 */
6805 #define DSI_CCR_TOCKDIV7 DSI_CCR_TOCKDIV7_Msk
6806
6807 /******************* Bit definition for DSI_LVCIDR register *************/
6808 #define DSI_LVCIDR_VCID_Pos (0U)
6809 #define DSI_LVCIDR_VCID_Msk (0x3U << DSI_LVCIDR_VCID_Pos) /*!< 0x00000003 */
6810 #define DSI_LVCIDR_VCID DSI_LVCIDR_VCID_Msk /*!< Virtual Channel ID */
6811 #define DSI_LVCIDR_VCID0_Pos (0U)
6812 #define DSI_LVCIDR_VCID0_Msk (0x1U << DSI_LVCIDR_VCID0_Pos) /*!< 0x00000001 */
6813 #define DSI_LVCIDR_VCID0 DSI_LVCIDR_VCID0_Msk
6814 #define DSI_LVCIDR_VCID1_Pos (1U)
6815 #define DSI_LVCIDR_VCID1_Msk (0x1U << DSI_LVCIDR_VCID1_Pos) /*!< 0x00000002 */
6816 #define DSI_LVCIDR_VCID1 DSI_LVCIDR_VCID1_Msk
6817
6818 /******************* Bit definition for DSI_LCOLCR register *************/
6819 #define DSI_LCOLCR_COLC_Pos (0U)
6820 #define DSI_LCOLCR_COLC_Msk (0xFU << DSI_LCOLCR_COLC_Pos) /*!< 0x0000000F */
6821 #define DSI_LCOLCR_COLC DSI_LCOLCR_COLC_Msk /*!< Color Coding */
6822 #define DSI_LCOLCR_COLC0_Pos (0U)
6823 #define DSI_LCOLCR_COLC0_Msk (0x1U << DSI_LCOLCR_COLC0_Pos) /*!< 0x00000001 */
6824 #define DSI_LCOLCR_COLC0 DSI_LCOLCR_COLC0_Msk
6825 #define DSI_LCOLCR_COLC1_Pos (5U)
6826 #define DSI_LCOLCR_COLC1_Msk (0x1U << DSI_LCOLCR_COLC1_Pos) /*!< 0x00000020 */
6827 #define DSI_LCOLCR_COLC1 DSI_LCOLCR_COLC1_Msk
6828 #define DSI_LCOLCR_COLC2_Pos (6U)
6829 #define DSI_LCOLCR_COLC2_Msk (0x1U << DSI_LCOLCR_COLC2_Pos) /*!< 0x00000040 */
6830 #define DSI_LCOLCR_COLC2 DSI_LCOLCR_COLC2_Msk
6831 #define DSI_LCOLCR_COLC3_Pos (7U)
6832 #define DSI_LCOLCR_COLC3_Msk (0x1U << DSI_LCOLCR_COLC3_Pos) /*!< 0x00000080 */
6833 #define DSI_LCOLCR_COLC3 DSI_LCOLCR_COLC3_Msk
6834
6835 #define DSI_LCOLCR_LPE_Pos (8U)
6836 #define DSI_LCOLCR_LPE_Msk (0x1U << DSI_LCOLCR_LPE_Pos) /*!< 0x00000100 */
6837 #define DSI_LCOLCR_LPE DSI_LCOLCR_LPE_Msk /*!< Loosly Packet Enable */
6838
6839 /******************* Bit definition for DSI_LPCR register ***************/
6840 #define DSI_LPCR_DEP_Pos (0U)
6841 #define DSI_LPCR_DEP_Msk (0x1U << DSI_LPCR_DEP_Pos) /*!< 0x00000001 */
6842 #define DSI_LPCR_DEP DSI_LPCR_DEP_Msk /*!< Data Enable Polarity */
6843 #define DSI_LPCR_VSP_Pos (1U)
6844 #define DSI_LPCR_VSP_Msk (0x1U << DSI_LPCR_VSP_Pos) /*!< 0x00000002 */
6845 #define DSI_LPCR_VSP DSI_LPCR_VSP_Msk /*!< VSYNC Polarity */
6846 #define DSI_LPCR_HSP_Pos (2U)
6847 #define DSI_LPCR_HSP_Msk (0x1U << DSI_LPCR_HSP_Pos) /*!< 0x00000004 */
6848 #define DSI_LPCR_HSP DSI_LPCR_HSP_Msk /*!< HSYNC Polarity */
6849
6850 /******************* Bit definition for DSI_LPMCR register **************/
6851 #define DSI_LPMCR_VLPSIZE_Pos (0U)
6852 #define DSI_LPMCR_VLPSIZE_Msk (0xFFU << DSI_LPMCR_VLPSIZE_Pos) /*!< 0x000000FF */
6853 #define DSI_LPMCR_VLPSIZE DSI_LPMCR_VLPSIZE_Msk /*!< VACT Largest Packet Size */
6854 #define DSI_LPMCR_VLPSIZE0_Pos (0U)
6855 #define DSI_LPMCR_VLPSIZE0_Msk (0x1U << DSI_LPMCR_VLPSIZE0_Pos) /*!< 0x00000001 */
6856 #define DSI_LPMCR_VLPSIZE0 DSI_LPMCR_VLPSIZE0_Msk
6857 #define DSI_LPMCR_VLPSIZE1_Pos (1U)
6858 #define DSI_LPMCR_VLPSIZE1_Msk (0x1U << DSI_LPMCR_VLPSIZE1_Pos) /*!< 0x00000002 */
6859 #define DSI_LPMCR_VLPSIZE1 DSI_LPMCR_VLPSIZE1_Msk
6860 #define DSI_LPMCR_VLPSIZE2_Pos (2U)
6861 #define DSI_LPMCR_VLPSIZE2_Msk (0x1U << DSI_LPMCR_VLPSIZE2_Pos) /*!< 0x00000004 */
6862 #define DSI_LPMCR_VLPSIZE2 DSI_LPMCR_VLPSIZE2_Msk
6863 #define DSI_LPMCR_VLPSIZE3_Pos (3U)
6864 #define DSI_LPMCR_VLPSIZE3_Msk (0x1U << DSI_LPMCR_VLPSIZE3_Pos) /*!< 0x00000008 */
6865 #define DSI_LPMCR_VLPSIZE3 DSI_LPMCR_VLPSIZE3_Msk
6866 #define DSI_LPMCR_VLPSIZE4_Pos (4U)
6867 #define DSI_LPMCR_VLPSIZE4_Msk (0x1U << DSI_LPMCR_VLPSIZE4_Pos) /*!< 0x00000010 */
6868 #define DSI_LPMCR_VLPSIZE4 DSI_LPMCR_VLPSIZE4_Msk
6869 #define DSI_LPMCR_VLPSIZE5_Pos (5U)
6870 #define DSI_LPMCR_VLPSIZE5_Msk (0x1U << DSI_LPMCR_VLPSIZE5_Pos) /*!< 0x00000020 */
6871 #define DSI_LPMCR_VLPSIZE5 DSI_LPMCR_VLPSIZE5_Msk
6872 #define DSI_LPMCR_VLPSIZE6_Pos (6U)
6873 #define DSI_LPMCR_VLPSIZE6_Msk (0x1U << DSI_LPMCR_VLPSIZE6_Pos) /*!< 0x00000040 */
6874 #define DSI_LPMCR_VLPSIZE6 DSI_LPMCR_VLPSIZE6_Msk
6875 #define DSI_LPMCR_VLPSIZE7_Pos (7U)
6876 #define DSI_LPMCR_VLPSIZE7_Msk (0x1U << DSI_LPMCR_VLPSIZE7_Pos) /*!< 0x00000080 */
6877 #define DSI_LPMCR_VLPSIZE7 DSI_LPMCR_VLPSIZE7_Msk
6878
6879 #define DSI_LPMCR_LPSIZE_Pos (16U)
6880 #define DSI_LPMCR_LPSIZE_Msk (0xFFU << DSI_LPMCR_LPSIZE_Pos) /*!< 0x00FF0000 */
6881 #define DSI_LPMCR_LPSIZE DSI_LPMCR_LPSIZE_Msk /*!< Largest Packet Size */
6882 #define DSI_LPMCR_LPSIZE0_Pos (16U)
6883 #define DSI_LPMCR_LPSIZE0_Msk (0x1U << DSI_LPMCR_LPSIZE0_Pos) /*!< 0x00010000 */
6884 #define DSI_LPMCR_LPSIZE0 DSI_LPMCR_LPSIZE0_Msk
6885 #define DSI_LPMCR_LPSIZE1_Pos (17U)
6886 #define DSI_LPMCR_LPSIZE1_Msk (0x1U << DSI_LPMCR_LPSIZE1_Pos) /*!< 0x00020000 */
6887 #define DSI_LPMCR_LPSIZE1 DSI_LPMCR_LPSIZE1_Msk
6888 #define DSI_LPMCR_LPSIZE2_Pos (18U)
6889 #define DSI_LPMCR_LPSIZE2_Msk (0x1U << DSI_LPMCR_LPSIZE2_Pos) /*!< 0x00040000 */
6890 #define DSI_LPMCR_LPSIZE2 DSI_LPMCR_LPSIZE2_Msk
6891 #define DSI_LPMCR_LPSIZE3_Pos (19U)
6892 #define DSI_LPMCR_LPSIZE3_Msk (0x1U << DSI_LPMCR_LPSIZE3_Pos) /*!< 0x00080000 */
6893 #define DSI_LPMCR_LPSIZE3 DSI_LPMCR_LPSIZE3_Msk
6894 #define DSI_LPMCR_LPSIZE4_Pos (20U)
6895 #define DSI_LPMCR_LPSIZE4_Msk (0x1U << DSI_LPMCR_LPSIZE4_Pos) /*!< 0x00100000 */
6896 #define DSI_LPMCR_LPSIZE4 DSI_LPMCR_LPSIZE4_Msk
6897 #define DSI_LPMCR_LPSIZE5_Pos (21U)
6898 #define DSI_LPMCR_LPSIZE5_Msk (0x1U << DSI_LPMCR_LPSIZE5_Pos) /*!< 0x00200000 */
6899 #define DSI_LPMCR_LPSIZE5 DSI_LPMCR_LPSIZE5_Msk
6900 #define DSI_LPMCR_LPSIZE6_Pos (22U)
6901 #define DSI_LPMCR_LPSIZE6_Msk (0x1U << DSI_LPMCR_LPSIZE6_Pos) /*!< 0x00400000 */
6902 #define DSI_LPMCR_LPSIZE6 DSI_LPMCR_LPSIZE6_Msk
6903 #define DSI_LPMCR_LPSIZE7_Pos (23U)
6904 #define DSI_LPMCR_LPSIZE7_Msk (0x1U << DSI_LPMCR_LPSIZE7_Pos) /*!< 0x00800000 */
6905 #define DSI_LPMCR_LPSIZE7 DSI_LPMCR_LPSIZE7_Msk
6906
6907 /******************* Bit definition for DSI_PCR register ****************/
6908 #define DSI_PCR_ETTXE_Pos (0U)
6909 #define DSI_PCR_ETTXE_Msk (0x1U << DSI_PCR_ETTXE_Pos) /*!< 0x00000001 */
6910 #define DSI_PCR_ETTXE DSI_PCR_ETTXE_Msk /*!< EoTp Transmission Enable */
6911 #define DSI_PCR_ETRXE_Pos (1U)
6912 #define DSI_PCR_ETRXE_Msk (0x1U << DSI_PCR_ETRXE_Pos) /*!< 0x00000002 */
6913 #define DSI_PCR_ETRXE DSI_PCR_ETRXE_Msk /*!< EoTp Reception Enable */
6914 #define DSI_PCR_BTAE_Pos (2U)
6915 #define DSI_PCR_BTAE_Msk (0x1U << DSI_PCR_BTAE_Pos) /*!< 0x00000004 */
6916 #define DSI_PCR_BTAE DSI_PCR_BTAE_Msk /*!< Bus Turn Around Enable */
6917 #define DSI_PCR_ECCRXE_Pos (3U)
6918 #define DSI_PCR_ECCRXE_Msk (0x1U << DSI_PCR_ECCRXE_Pos) /*!< 0x00000008 */
6919 #define DSI_PCR_ECCRXE DSI_PCR_ECCRXE_Msk /*!< ECC Reception Enable */
6920 #define DSI_PCR_CRCRXE_Pos (4U)
6921 #define DSI_PCR_CRCRXE_Msk (0x1U << DSI_PCR_CRCRXE_Pos) /*!< 0x00000010 */
6922 #define DSI_PCR_CRCRXE DSI_PCR_CRCRXE_Msk /*!< CRC Reception Enable */
6923
6924 /******************* Bit definition for DSI_GVCIDR register *************/
6925 #define DSI_GVCIDR_VCID_Pos (0U)
6926 #define DSI_GVCIDR_VCID_Msk (0x3U << DSI_GVCIDR_VCID_Pos) /*!< 0x00000003 */
6927 #define DSI_GVCIDR_VCID DSI_GVCIDR_VCID_Msk /*!< Virtual Channel ID */
6928 #define DSI_GVCIDR_VCID0_Pos (0U)
6929 #define DSI_GVCIDR_VCID0_Msk (0x1U << DSI_GVCIDR_VCID0_Pos) /*!< 0x00000001 */
6930 #define DSI_GVCIDR_VCID0 DSI_GVCIDR_VCID0_Msk
6931 #define DSI_GVCIDR_VCID1_Pos (1U)
6932 #define DSI_GVCIDR_VCID1_Msk (0x1U << DSI_GVCIDR_VCID1_Pos) /*!< 0x00000002 */
6933 #define DSI_GVCIDR_VCID1 DSI_GVCIDR_VCID1_Msk
6934
6935 /******************* Bit definition for DSI_MCR register ****************/
6936 #define DSI_MCR_CMDM_Pos (0U)
6937 #define DSI_MCR_CMDM_Msk (0x1U << DSI_MCR_CMDM_Pos) /*!< 0x00000001 */
6938 #define DSI_MCR_CMDM DSI_MCR_CMDM_Msk /*!< Command Mode */
6939
6940 /******************* Bit definition for DSI_VMCR register ***************/
6941 #define DSI_VMCR_VMT_Pos (0U)
6942 #define DSI_VMCR_VMT_Msk (0x3U << DSI_VMCR_VMT_Pos) /*!< 0x00000003 */
6943 #define DSI_VMCR_VMT DSI_VMCR_VMT_Msk /*!< Video Mode Type */
6944 #define DSI_VMCR_VMT0_Pos (0U)
6945 #define DSI_VMCR_VMT0_Msk (0x1U << DSI_VMCR_VMT0_Pos) /*!< 0x00000001 */
6946 #define DSI_VMCR_VMT0 DSI_VMCR_VMT0_Msk
6947 #define DSI_VMCR_VMT1_Pos (1U)
6948 #define DSI_VMCR_VMT1_Msk (0x1U << DSI_VMCR_VMT1_Pos) /*!< 0x00000002 */
6949 #define DSI_VMCR_VMT1 DSI_VMCR_VMT1_Msk
6950
6951 #define DSI_VMCR_LPVSAE_Pos (8U)
6952 #define DSI_VMCR_LPVSAE_Msk (0x1U << DSI_VMCR_LPVSAE_Pos) /*!< 0x00000100 */
6953 #define DSI_VMCR_LPVSAE DSI_VMCR_LPVSAE_Msk /*!< Low-Power Vertical Sync Active Enable */
6954 #define DSI_VMCR_LPVBPE_Pos (9U)
6955 #define DSI_VMCR_LPVBPE_Msk (0x1U << DSI_VMCR_LPVBPE_Pos) /*!< 0x00000200 */
6956 #define DSI_VMCR_LPVBPE DSI_VMCR_LPVBPE_Msk /*!< Low-power Vertical Back-Porch Enable */
6957 #define DSI_VMCR_LPVFPE_Pos (10U)
6958 #define DSI_VMCR_LPVFPE_Msk (0x1U << DSI_VMCR_LPVFPE_Pos) /*!< 0x00000400 */
6959 #define DSI_VMCR_LPVFPE DSI_VMCR_LPVFPE_Msk /*!< Low-power Vertical Front-porch Enable */
6960 #define DSI_VMCR_LPVAE_Pos (11U)
6961 #define DSI_VMCR_LPVAE_Msk (0x1U << DSI_VMCR_LPVAE_Pos) /*!< 0x00000800 */
6962 #define DSI_VMCR_LPVAE DSI_VMCR_LPVAE_Msk /*!< Low-Power Vertical Active Enable */
6963 #define DSI_VMCR_LPHBPE_Pos (12U)
6964 #define DSI_VMCR_LPHBPE_Msk (0x1U << DSI_VMCR_LPHBPE_Pos) /*!< 0x00001000 */
6965 #define DSI_VMCR_LPHBPE DSI_VMCR_LPHBPE_Msk /*!< Low-Power Horizontal Back-Porch Enable */
6966 #define DSI_VMCR_LPHFPE_Pos (13U)
6967 #define DSI_VMCR_LPHFPE_Msk (0x1U << DSI_VMCR_LPHFPE_Pos) /*!< 0x00002000 */
6968 #define DSI_VMCR_LPHFPE DSI_VMCR_LPHFPE_Msk /*!< Low-Power Horizontal Front-Porch Enable */
6969 #define DSI_VMCR_FBTAAE_Pos (14U)
6970 #define DSI_VMCR_FBTAAE_Msk (0x1U << DSI_VMCR_FBTAAE_Pos) /*!< 0x00004000 */
6971 #define DSI_VMCR_FBTAAE DSI_VMCR_FBTAAE_Msk /*!< Frame Bus-Turn-Around Acknowledge Enable */
6972 #define DSI_VMCR_LPCE_Pos (15U)
6973 #define DSI_VMCR_LPCE_Msk (0x1U << DSI_VMCR_LPCE_Pos) /*!< 0x00008000 */
6974 #define DSI_VMCR_LPCE DSI_VMCR_LPCE_Msk /*!< Low-Power Command Enable */
6975 #define DSI_VMCR_PGE_Pos (16U)
6976 #define DSI_VMCR_PGE_Msk (0x1U << DSI_VMCR_PGE_Pos) /*!< 0x00010000 */
6977 #define DSI_VMCR_PGE DSI_VMCR_PGE_Msk /*!< Pattern Generator Enable */
6978 #define DSI_VMCR_PGM_Pos (20U)
6979 #define DSI_VMCR_PGM_Msk (0x1U << DSI_VMCR_PGM_Pos) /*!< 0x00100000 */
6980 #define DSI_VMCR_PGM DSI_VMCR_PGM_Msk /*!< Pattern Generator Mode */
6981 #define DSI_VMCR_PGO_Pos (24U)
6982 #define DSI_VMCR_PGO_Msk (0x1U << DSI_VMCR_PGO_Pos) /*!< 0x01000000 */
6983 #define DSI_VMCR_PGO DSI_VMCR_PGO_Msk /*!< Pattern Generator Orientation */
6984
6985 /******************* Bit definition for DSI_VPCR register ***************/
6986 #define DSI_VPCR_VPSIZE_Pos (0U)
6987 #define DSI_VPCR_VPSIZE_Msk (0x3FFFU << DSI_VPCR_VPSIZE_Pos) /*!< 0x00003FFF */
6988 #define DSI_VPCR_VPSIZE DSI_VPCR_VPSIZE_Msk /*!< Video Packet Size */
6989 #define DSI_VPCR_VPSIZE0_Pos (0U)
6990 #define DSI_VPCR_VPSIZE0_Msk (0x1U << DSI_VPCR_VPSIZE0_Pos) /*!< 0x00000001 */
6991 #define DSI_VPCR_VPSIZE0 DSI_VPCR_VPSIZE0_Msk
6992 #define DSI_VPCR_VPSIZE1_Pos (1U)
6993 #define DSI_VPCR_VPSIZE1_Msk (0x1U << DSI_VPCR_VPSIZE1_Pos) /*!< 0x00000002 */
6994 #define DSI_VPCR_VPSIZE1 DSI_VPCR_VPSIZE1_Msk
6995 #define DSI_VPCR_VPSIZE2_Pos (2U)
6996 #define DSI_VPCR_VPSIZE2_Msk (0x1U << DSI_VPCR_VPSIZE2_Pos) /*!< 0x00000004 */
6997 #define DSI_VPCR_VPSIZE2 DSI_VPCR_VPSIZE2_Msk
6998 #define DSI_VPCR_VPSIZE3_Pos (3U)
6999 #define DSI_VPCR_VPSIZE3_Msk (0x1U << DSI_VPCR_VPSIZE3_Pos) /*!< 0x00000008 */
7000 #define DSI_VPCR_VPSIZE3 DSI_VPCR_VPSIZE3_Msk
7001 #define DSI_VPCR_VPSIZE4_Pos (4U)
7002 #define DSI_VPCR_VPSIZE4_Msk (0x1U << DSI_VPCR_VPSIZE4_Pos) /*!< 0x00000010 */
7003 #define DSI_VPCR_VPSIZE4 DSI_VPCR_VPSIZE4_Msk
7004 #define DSI_VPCR_VPSIZE5_Pos (5U)
7005 #define DSI_VPCR_VPSIZE5_Msk (0x1U << DSI_VPCR_VPSIZE5_Pos) /*!< 0x00000020 */
7006 #define DSI_VPCR_VPSIZE5 DSI_VPCR_VPSIZE5_Msk
7007 #define DSI_VPCR_VPSIZE6_Pos (6U)
7008 #define DSI_VPCR_VPSIZE6_Msk (0x1U << DSI_VPCR_VPSIZE6_Pos) /*!< 0x00000040 */
7009 #define DSI_VPCR_VPSIZE6 DSI_VPCR_VPSIZE6_Msk
7010 #define DSI_VPCR_VPSIZE7_Pos (7U)
7011 #define DSI_VPCR_VPSIZE7_Msk (0x1U << DSI_VPCR_VPSIZE7_Pos) /*!< 0x00000080 */
7012 #define DSI_VPCR_VPSIZE7 DSI_VPCR_VPSIZE7_Msk
7013 #define DSI_VPCR_VPSIZE8_Pos (8U)
7014 #define DSI_VPCR_VPSIZE8_Msk (0x1U << DSI_VPCR_VPSIZE8_Pos) /*!< 0x00000100 */
7015 #define DSI_VPCR_VPSIZE8 DSI_VPCR_VPSIZE8_Msk
7016 #define DSI_VPCR_VPSIZE9_Pos (9U)
7017 #define DSI_VPCR_VPSIZE9_Msk (0x1U << DSI_VPCR_VPSIZE9_Pos) /*!< 0x00000200 */
7018 #define DSI_VPCR_VPSIZE9 DSI_VPCR_VPSIZE9_Msk
7019 #define DSI_VPCR_VPSIZE10_Pos (10U)
7020 #define DSI_VPCR_VPSIZE10_Msk (0x1U << DSI_VPCR_VPSIZE10_Pos) /*!< 0x00000400 */
7021 #define DSI_VPCR_VPSIZE10 DSI_VPCR_VPSIZE10_Msk
7022 #define DSI_VPCR_VPSIZE11_Pos (11U)
7023 #define DSI_VPCR_VPSIZE11_Msk (0x1U << DSI_VPCR_VPSIZE11_Pos) /*!< 0x00000800 */
7024 #define DSI_VPCR_VPSIZE11 DSI_VPCR_VPSIZE11_Msk
7025 #define DSI_VPCR_VPSIZE12_Pos (12U)
7026 #define DSI_VPCR_VPSIZE12_Msk (0x1U << DSI_VPCR_VPSIZE12_Pos) /*!< 0x00001000 */
7027 #define DSI_VPCR_VPSIZE12 DSI_VPCR_VPSIZE12_Msk
7028 #define DSI_VPCR_VPSIZE13_Pos (13U)
7029 #define DSI_VPCR_VPSIZE13_Msk (0x1U << DSI_VPCR_VPSIZE13_Pos) /*!< 0x00002000 */
7030 #define DSI_VPCR_VPSIZE13 DSI_VPCR_VPSIZE13_Msk
7031
7032 /******************* Bit definition for DSI_VCCR register ***************/
7033 #define DSI_VCCR_NUMC_Pos (0U)
7034 #define DSI_VCCR_NUMC_Msk (0x1FFFU << DSI_VCCR_NUMC_Pos) /*!< 0x00001FFF */
7035 #define DSI_VCCR_NUMC DSI_VCCR_NUMC_Msk /*!< Number of Chunks */
7036 #define DSI_VCCR_NUMC0_Pos (0U)
7037 #define DSI_VCCR_NUMC0_Msk (0x1U << DSI_VCCR_NUMC0_Pos) /*!< 0x00000001 */
7038 #define DSI_VCCR_NUMC0 DSI_VCCR_NUMC0_Msk
7039 #define DSI_VCCR_NUMC1_Pos (1U)
7040 #define DSI_VCCR_NUMC1_Msk (0x1U << DSI_VCCR_NUMC1_Pos) /*!< 0x00000002 */
7041 #define DSI_VCCR_NUMC1 DSI_VCCR_NUMC1_Msk
7042 #define DSI_VCCR_NUMC2_Pos (2U)
7043 #define DSI_VCCR_NUMC2_Msk (0x1U << DSI_VCCR_NUMC2_Pos) /*!< 0x00000004 */
7044 #define DSI_VCCR_NUMC2 DSI_VCCR_NUMC2_Msk
7045 #define DSI_VCCR_NUMC3_Pos (3U)
7046 #define DSI_VCCR_NUMC3_Msk (0x1U << DSI_VCCR_NUMC3_Pos) /*!< 0x00000008 */
7047 #define DSI_VCCR_NUMC3 DSI_VCCR_NUMC3_Msk
7048 #define DSI_VCCR_NUMC4_Pos (4U)
7049 #define DSI_VCCR_NUMC4_Msk (0x1U << DSI_VCCR_NUMC4_Pos) /*!< 0x00000010 */
7050 #define DSI_VCCR_NUMC4 DSI_VCCR_NUMC4_Msk
7051 #define DSI_VCCR_NUMC5_Pos (5U)
7052 #define DSI_VCCR_NUMC5_Msk (0x1U << DSI_VCCR_NUMC5_Pos) /*!< 0x00000020 */
7053 #define DSI_VCCR_NUMC5 DSI_VCCR_NUMC5_Msk
7054 #define DSI_VCCR_NUMC6_Pos (6U)
7055 #define DSI_VCCR_NUMC6_Msk (0x1U << DSI_VCCR_NUMC6_Pos) /*!< 0x00000040 */
7056 #define DSI_VCCR_NUMC6 DSI_VCCR_NUMC6_Msk
7057 #define DSI_VCCR_NUMC7_Pos (7U)
7058 #define DSI_VCCR_NUMC7_Msk (0x1U << DSI_VCCR_NUMC7_Pos) /*!< 0x00000080 */
7059 #define DSI_VCCR_NUMC7 DSI_VCCR_NUMC7_Msk
7060 #define DSI_VCCR_NUMC8_Pos (8U)
7061 #define DSI_VCCR_NUMC8_Msk (0x1U << DSI_VCCR_NUMC8_Pos) /*!< 0x00000100 */
7062 #define DSI_VCCR_NUMC8 DSI_VCCR_NUMC8_Msk
7063 #define DSI_VCCR_NUMC9_Pos (9U)
7064 #define DSI_VCCR_NUMC9_Msk (0x1U << DSI_VCCR_NUMC9_Pos) /*!< 0x00000200 */
7065 #define DSI_VCCR_NUMC9 DSI_VCCR_NUMC9_Msk
7066 #define DSI_VCCR_NUMC10_Pos (10U)
7067 #define DSI_VCCR_NUMC10_Msk (0x1U << DSI_VCCR_NUMC10_Pos) /*!< 0x00000400 */
7068 #define DSI_VCCR_NUMC10 DSI_VCCR_NUMC10_Msk
7069 #define DSI_VCCR_NUMC11_Pos (11U)
7070 #define DSI_VCCR_NUMC11_Msk (0x1U << DSI_VCCR_NUMC11_Pos) /*!< 0x00000800 */
7071 #define DSI_VCCR_NUMC11 DSI_VCCR_NUMC11_Msk
7072 #define DSI_VCCR_NUMC12_Pos (12U)
7073 #define DSI_VCCR_NUMC12_Msk (0x1U << DSI_VCCR_NUMC12_Pos) /*!< 0x00001000 */
7074 #define DSI_VCCR_NUMC12 DSI_VCCR_NUMC12_Msk
7075
7076 /******************* Bit definition for DSI_VNPCR register **************/
7077 #define DSI_VNPCR_NPSIZE_Pos (0U)
7078 #define DSI_VNPCR_NPSIZE_Msk (0x1FFFU << DSI_VNPCR_NPSIZE_Pos) /*!< 0x00001FFF */
7079 #define DSI_VNPCR_NPSIZE DSI_VNPCR_NPSIZE_Msk /*!< Null Packet Size */
7080 #define DSI_VNPCR_NPSIZE0_Pos (0U)
7081 #define DSI_VNPCR_NPSIZE0_Msk (0x1U << DSI_VNPCR_NPSIZE0_Pos) /*!< 0x00000001 */
7082 #define DSI_VNPCR_NPSIZE0 DSI_VNPCR_NPSIZE0_Msk
7083 #define DSI_VNPCR_NPSIZE1_Pos (1U)
7084 #define DSI_VNPCR_NPSIZE1_Msk (0x1U << DSI_VNPCR_NPSIZE1_Pos) /*!< 0x00000002 */
7085 #define DSI_VNPCR_NPSIZE1 DSI_VNPCR_NPSIZE1_Msk
7086 #define DSI_VNPCR_NPSIZE2_Pos (2U)
7087 #define DSI_VNPCR_NPSIZE2_Msk (0x1U << DSI_VNPCR_NPSIZE2_Pos) /*!< 0x00000004 */
7088 #define DSI_VNPCR_NPSIZE2 DSI_VNPCR_NPSIZE2_Msk
7089 #define DSI_VNPCR_NPSIZE3_Pos (3U)
7090 #define DSI_VNPCR_NPSIZE3_Msk (0x1U << DSI_VNPCR_NPSIZE3_Pos) /*!< 0x00000008 */
7091 #define DSI_VNPCR_NPSIZE3 DSI_VNPCR_NPSIZE3_Msk
7092 #define DSI_VNPCR_NPSIZE4_Pos (4U)
7093 #define DSI_VNPCR_NPSIZE4_Msk (0x1U << DSI_VNPCR_NPSIZE4_Pos) /*!< 0x00000010 */
7094 #define DSI_VNPCR_NPSIZE4 DSI_VNPCR_NPSIZE4_Msk
7095 #define DSI_VNPCR_NPSIZE5_Pos (5U)
7096 #define DSI_VNPCR_NPSIZE5_Msk (0x1U << DSI_VNPCR_NPSIZE5_Pos) /*!< 0x00000020 */
7097 #define DSI_VNPCR_NPSIZE5 DSI_VNPCR_NPSIZE5_Msk
7098 #define DSI_VNPCR_NPSIZE6_Pos (6U)
7099 #define DSI_VNPCR_NPSIZE6_Msk (0x1U << DSI_VNPCR_NPSIZE6_Pos) /*!< 0x00000040 */
7100 #define DSI_VNPCR_NPSIZE6 DSI_VNPCR_NPSIZE6_Msk
7101 #define DSI_VNPCR_NPSIZE7_Pos (7U)
7102 #define DSI_VNPCR_NPSIZE7_Msk (0x1U << DSI_VNPCR_NPSIZE7_Pos) /*!< 0x00000080 */
7103 #define DSI_VNPCR_NPSIZE7 DSI_VNPCR_NPSIZE7_Msk
7104 #define DSI_VNPCR_NPSIZE8_Pos (8U)
7105 #define DSI_VNPCR_NPSIZE8_Msk (0x1U << DSI_VNPCR_NPSIZE8_Pos) /*!< 0x00000100 */
7106 #define DSI_VNPCR_NPSIZE8 DSI_VNPCR_NPSIZE8_Msk
7107 #define DSI_VNPCR_NPSIZE9_Pos (9U)
7108 #define DSI_VNPCR_NPSIZE9_Msk (0x1U << DSI_VNPCR_NPSIZE9_Pos) /*!< 0x00000200 */
7109 #define DSI_VNPCR_NPSIZE9 DSI_VNPCR_NPSIZE9_Msk
7110 #define DSI_VNPCR_NPSIZE10_Pos (10U)
7111 #define DSI_VNPCR_NPSIZE10_Msk (0x1U << DSI_VNPCR_NPSIZE10_Pos) /*!< 0x00000400 */
7112 #define DSI_VNPCR_NPSIZE10 DSI_VNPCR_NPSIZE10_Msk
7113 #define DSI_VNPCR_NPSIZE11_Pos (11U)
7114 #define DSI_VNPCR_NPSIZE11_Msk (0x1U << DSI_VNPCR_NPSIZE11_Pos) /*!< 0x00000800 */
7115 #define DSI_VNPCR_NPSIZE11 DSI_VNPCR_NPSIZE11_Msk
7116 #define DSI_VNPCR_NPSIZE12_Pos (12U)
7117 #define DSI_VNPCR_NPSIZE12_Msk (0x1U << DSI_VNPCR_NPSIZE12_Pos) /*!< 0x00001000 */
7118 #define DSI_VNPCR_NPSIZE12 DSI_VNPCR_NPSIZE12_Msk
7119
7120 /******************* Bit definition for DSI_VHSACR register *************/
7121 #define DSI_VHSACR_HSA_Pos (0U)
7122 #define DSI_VHSACR_HSA_Msk (0xFFFU << DSI_VHSACR_HSA_Pos) /*!< 0x00000FFF */
7123 #define DSI_VHSACR_HSA DSI_VHSACR_HSA_Msk /*!< Horizontal Synchronism Active duration */
7124 #define DSI_VHSACR_HSA0_Pos (0U)
7125 #define DSI_VHSACR_HSA0_Msk (0x1U << DSI_VHSACR_HSA0_Pos) /*!< 0x00000001 */
7126 #define DSI_VHSACR_HSA0 DSI_VHSACR_HSA0_Msk
7127 #define DSI_VHSACR_HSA1_Pos (1U)
7128 #define DSI_VHSACR_HSA1_Msk (0x1U << DSI_VHSACR_HSA1_Pos) /*!< 0x00000002 */
7129 #define DSI_VHSACR_HSA1 DSI_VHSACR_HSA1_Msk
7130 #define DSI_VHSACR_HSA2_Pos (2U)
7131 #define DSI_VHSACR_HSA2_Msk (0x1U << DSI_VHSACR_HSA2_Pos) /*!< 0x00000004 */
7132 #define DSI_VHSACR_HSA2 DSI_VHSACR_HSA2_Msk
7133 #define DSI_VHSACR_HSA3_Pos (3U)
7134 #define DSI_VHSACR_HSA3_Msk (0x1U << DSI_VHSACR_HSA3_Pos) /*!< 0x00000008 */
7135 #define DSI_VHSACR_HSA3 DSI_VHSACR_HSA3_Msk
7136 #define DSI_VHSACR_HSA4_Pos (4U)
7137 #define DSI_VHSACR_HSA4_Msk (0x1U << DSI_VHSACR_HSA4_Pos) /*!< 0x00000010 */
7138 #define DSI_VHSACR_HSA4 DSI_VHSACR_HSA4_Msk
7139 #define DSI_VHSACR_HSA5_Pos (5U)
7140 #define DSI_VHSACR_HSA5_Msk (0x1U << DSI_VHSACR_HSA5_Pos) /*!< 0x00000020 */
7141 #define DSI_VHSACR_HSA5 DSI_VHSACR_HSA5_Msk
7142 #define DSI_VHSACR_HSA6_Pos (6U)
7143 #define DSI_VHSACR_HSA6_Msk (0x1U << DSI_VHSACR_HSA6_Pos) /*!< 0x00000040 */
7144 #define DSI_VHSACR_HSA6 DSI_VHSACR_HSA6_Msk
7145 #define DSI_VHSACR_HSA7_Pos (7U)
7146 #define DSI_VHSACR_HSA7_Msk (0x1U << DSI_VHSACR_HSA7_Pos) /*!< 0x00000080 */
7147 #define DSI_VHSACR_HSA7 DSI_VHSACR_HSA7_Msk
7148 #define DSI_VHSACR_HSA8_Pos (8U)
7149 #define DSI_VHSACR_HSA8_Msk (0x1U << DSI_VHSACR_HSA8_Pos) /*!< 0x00000100 */
7150 #define DSI_VHSACR_HSA8 DSI_VHSACR_HSA8_Msk
7151 #define DSI_VHSACR_HSA9_Pos (9U)
7152 #define DSI_VHSACR_HSA9_Msk (0x1U << DSI_VHSACR_HSA9_Pos) /*!< 0x00000200 */
7153 #define DSI_VHSACR_HSA9 DSI_VHSACR_HSA9_Msk
7154 #define DSI_VHSACR_HSA10_Pos (10U)
7155 #define DSI_VHSACR_HSA10_Msk (0x1U << DSI_VHSACR_HSA10_Pos) /*!< 0x00000400 */
7156 #define DSI_VHSACR_HSA10 DSI_VHSACR_HSA10_Msk
7157 #define DSI_VHSACR_HSA11_Pos (11U)
7158 #define DSI_VHSACR_HSA11_Msk (0x1U << DSI_VHSACR_HSA11_Pos) /*!< 0x00000800 */
7159 #define DSI_VHSACR_HSA11 DSI_VHSACR_HSA11_Msk
7160
7161 /******************* Bit definition for DSI_VHBPCR register *************/
7162 #define DSI_VHBPCR_HBP_Pos (0U)
7163 #define DSI_VHBPCR_HBP_Msk (0xFFFU << DSI_VHBPCR_HBP_Pos) /*!< 0x00000FFF */
7164 #define DSI_VHBPCR_HBP DSI_VHBPCR_HBP_Msk /*!< Horizontal Back-Porch duration */
7165 #define DSI_VHBPCR_HBP0_Pos (0U)
7166 #define DSI_VHBPCR_HBP0_Msk (0x1U << DSI_VHBPCR_HBP0_Pos) /*!< 0x00000001 */
7167 #define DSI_VHBPCR_HBP0 DSI_VHBPCR_HBP0_Msk
7168 #define DSI_VHBPCR_HBP1_Pos (1U)
7169 #define DSI_VHBPCR_HBP1_Msk (0x1U << DSI_VHBPCR_HBP1_Pos) /*!< 0x00000002 */
7170 #define DSI_VHBPCR_HBP1 DSI_VHBPCR_HBP1_Msk
7171 #define DSI_VHBPCR_HBP2_Pos (2U)
7172 #define DSI_VHBPCR_HBP2_Msk (0x1U << DSI_VHBPCR_HBP2_Pos) /*!< 0x00000004 */
7173 #define DSI_VHBPCR_HBP2 DSI_VHBPCR_HBP2_Msk
7174 #define DSI_VHBPCR_HBP3_Pos (3U)
7175 #define DSI_VHBPCR_HBP3_Msk (0x1U << DSI_VHBPCR_HBP3_Pos) /*!< 0x00000008 */
7176 #define DSI_VHBPCR_HBP3 DSI_VHBPCR_HBP3_Msk
7177 #define DSI_VHBPCR_HBP4_Pos (4U)
7178 #define DSI_VHBPCR_HBP4_Msk (0x1U << DSI_VHBPCR_HBP4_Pos) /*!< 0x00000010 */
7179 #define DSI_VHBPCR_HBP4 DSI_VHBPCR_HBP4_Msk
7180 #define DSI_VHBPCR_HBP5_Pos (5U)
7181 #define DSI_VHBPCR_HBP5_Msk (0x1U << DSI_VHBPCR_HBP5_Pos) /*!< 0x00000020 */
7182 #define DSI_VHBPCR_HBP5 DSI_VHBPCR_HBP5_Msk
7183 #define DSI_VHBPCR_HBP6_Pos (6U)
7184 #define DSI_VHBPCR_HBP6_Msk (0x1U << DSI_VHBPCR_HBP6_Pos) /*!< 0x00000040 */
7185 #define DSI_VHBPCR_HBP6 DSI_VHBPCR_HBP6_Msk
7186 #define DSI_VHBPCR_HBP7_Pos (7U)
7187 #define DSI_VHBPCR_HBP7_Msk (0x1U << DSI_VHBPCR_HBP7_Pos) /*!< 0x00000080 */
7188 #define DSI_VHBPCR_HBP7 DSI_VHBPCR_HBP7_Msk
7189 #define DSI_VHBPCR_HBP8_Pos (8U)
7190 #define DSI_VHBPCR_HBP8_Msk (0x1U << DSI_VHBPCR_HBP8_Pos) /*!< 0x00000100 */
7191 #define DSI_VHBPCR_HBP8 DSI_VHBPCR_HBP8_Msk
7192 #define DSI_VHBPCR_HBP9_Pos (9U)
7193 #define DSI_VHBPCR_HBP9_Msk (0x1U << DSI_VHBPCR_HBP9_Pos) /*!< 0x00000200 */
7194 #define DSI_VHBPCR_HBP9 DSI_VHBPCR_HBP9_Msk
7195 #define DSI_VHBPCR_HBP10_Pos (10U)
7196 #define DSI_VHBPCR_HBP10_Msk (0x1U << DSI_VHBPCR_HBP10_Pos) /*!< 0x00000400 */
7197 #define DSI_VHBPCR_HBP10 DSI_VHBPCR_HBP10_Msk
7198 #define DSI_VHBPCR_HBP11_Pos (11U)
7199 #define DSI_VHBPCR_HBP11_Msk (0x1U << DSI_VHBPCR_HBP11_Pos) /*!< 0x00000800 */
7200 #define DSI_VHBPCR_HBP11 DSI_VHBPCR_HBP11_Msk
7201
7202 /******************* Bit definition for DSI_VLCR register ***************/
7203 #define DSI_VLCR_HLINE_Pos (0U)
7204 #define DSI_VLCR_HLINE_Msk (0x7FFFU << DSI_VLCR_HLINE_Pos) /*!< 0x00007FFF */
7205 #define DSI_VLCR_HLINE DSI_VLCR_HLINE_Msk /*!< Horizontal Line duration */
7206 #define DSI_VLCR_HLINE0_Pos (0U)
7207 #define DSI_VLCR_HLINE0_Msk (0x1U << DSI_VLCR_HLINE0_Pos) /*!< 0x00000001 */
7208 #define DSI_VLCR_HLINE0 DSI_VLCR_HLINE0_Msk
7209 #define DSI_VLCR_HLINE1_Pos (1U)
7210 #define DSI_VLCR_HLINE1_Msk (0x1U << DSI_VLCR_HLINE1_Pos) /*!< 0x00000002 */
7211 #define DSI_VLCR_HLINE1 DSI_VLCR_HLINE1_Msk
7212 #define DSI_VLCR_HLINE2_Pos (2U)
7213 #define DSI_VLCR_HLINE2_Msk (0x1U << DSI_VLCR_HLINE2_Pos) /*!< 0x00000004 */
7214 #define DSI_VLCR_HLINE2 DSI_VLCR_HLINE2_Msk
7215 #define DSI_VLCR_HLINE3_Pos (3U)
7216 #define DSI_VLCR_HLINE3_Msk (0x1U << DSI_VLCR_HLINE3_Pos) /*!< 0x00000008 */
7217 #define DSI_VLCR_HLINE3 DSI_VLCR_HLINE3_Msk
7218 #define DSI_VLCR_HLINE4_Pos (4U)
7219 #define DSI_VLCR_HLINE4_Msk (0x1U << DSI_VLCR_HLINE4_Pos) /*!< 0x00000010 */
7220 #define DSI_VLCR_HLINE4 DSI_VLCR_HLINE4_Msk
7221 #define DSI_VLCR_HLINE5_Pos (5U)
7222 #define DSI_VLCR_HLINE5_Msk (0x1U << DSI_VLCR_HLINE5_Pos) /*!< 0x00000020 */
7223 #define DSI_VLCR_HLINE5 DSI_VLCR_HLINE5_Msk
7224 #define DSI_VLCR_HLINE6_Pos (6U)
7225 #define DSI_VLCR_HLINE6_Msk (0x1U << DSI_VLCR_HLINE6_Pos) /*!< 0x00000040 */
7226 #define DSI_VLCR_HLINE6 DSI_VLCR_HLINE6_Msk
7227 #define DSI_VLCR_HLINE7_Pos (7U)
7228 #define DSI_VLCR_HLINE7_Msk (0x1U << DSI_VLCR_HLINE7_Pos) /*!< 0x00000080 */
7229 #define DSI_VLCR_HLINE7 DSI_VLCR_HLINE7_Msk
7230 #define DSI_VLCR_HLINE8_Pos (8U)
7231 #define DSI_VLCR_HLINE8_Msk (0x1U << DSI_VLCR_HLINE8_Pos) /*!< 0x00000100 */
7232 #define DSI_VLCR_HLINE8 DSI_VLCR_HLINE8_Msk
7233 #define DSI_VLCR_HLINE9_Pos (9U)
7234 #define DSI_VLCR_HLINE9_Msk (0x1U << DSI_VLCR_HLINE9_Pos) /*!< 0x00000200 */
7235 #define DSI_VLCR_HLINE9 DSI_VLCR_HLINE9_Msk
7236 #define DSI_VLCR_HLINE10_Pos (10U)
7237 #define DSI_VLCR_HLINE10_Msk (0x1U << DSI_VLCR_HLINE10_Pos) /*!< 0x00000400 */
7238 #define DSI_VLCR_HLINE10 DSI_VLCR_HLINE10_Msk
7239 #define DSI_VLCR_HLINE11_Pos (11U)
7240 #define DSI_VLCR_HLINE11_Msk (0x1U << DSI_VLCR_HLINE11_Pos) /*!< 0x00000800 */
7241 #define DSI_VLCR_HLINE11 DSI_VLCR_HLINE11_Msk
7242 #define DSI_VLCR_HLINE12_Pos (12U)
7243 #define DSI_VLCR_HLINE12_Msk (0x1U << DSI_VLCR_HLINE12_Pos) /*!< 0x00001000 */
7244 #define DSI_VLCR_HLINE12 DSI_VLCR_HLINE12_Msk
7245 #define DSI_VLCR_HLINE13_Pos (13U)
7246 #define DSI_VLCR_HLINE13_Msk (0x1U << DSI_VLCR_HLINE13_Pos) /*!< 0x00002000 */
7247 #define DSI_VLCR_HLINE13 DSI_VLCR_HLINE13_Msk
7248 #define DSI_VLCR_HLINE14_Pos (14U)
7249 #define DSI_VLCR_HLINE14_Msk (0x1U << DSI_VLCR_HLINE14_Pos) /*!< 0x00004000 */
7250 #define DSI_VLCR_HLINE14 DSI_VLCR_HLINE14_Msk
7251
7252 /******************* Bit definition for DSI_VVSACR register *************/
7253 #define DSI_VVSACR_VSA_Pos (0U)
7254 #define DSI_VVSACR_VSA_Msk (0x3FFU << DSI_VVSACR_VSA_Pos) /*!< 0x000003FF */
7255 #define DSI_VVSACR_VSA DSI_VVSACR_VSA_Msk /*!< Vertical Synchronism Active duration */
7256 #define DSI_VVSACR_VSA0_Pos (0U)
7257 #define DSI_VVSACR_VSA0_Msk (0x1U << DSI_VVSACR_VSA0_Pos) /*!< 0x00000001 */
7258 #define DSI_VVSACR_VSA0 DSI_VVSACR_VSA0_Msk
7259 #define DSI_VVSACR_VSA1_Pos (1U)
7260 #define DSI_VVSACR_VSA1_Msk (0x1U << DSI_VVSACR_VSA1_Pos) /*!< 0x00000002 */
7261 #define DSI_VVSACR_VSA1 DSI_VVSACR_VSA1_Msk
7262 #define DSI_VVSACR_VSA2_Pos (2U)
7263 #define DSI_VVSACR_VSA2_Msk (0x1U << DSI_VVSACR_VSA2_Pos) /*!< 0x00000004 */
7264 #define DSI_VVSACR_VSA2 DSI_VVSACR_VSA2_Msk
7265 #define DSI_VVSACR_VSA3_Pos (3U)
7266 #define DSI_VVSACR_VSA3_Msk (0x1U << DSI_VVSACR_VSA3_Pos) /*!< 0x00000008 */
7267 #define DSI_VVSACR_VSA3 DSI_VVSACR_VSA3_Msk
7268 #define DSI_VVSACR_VSA4_Pos (4U)
7269 #define DSI_VVSACR_VSA4_Msk (0x1U << DSI_VVSACR_VSA4_Pos) /*!< 0x00000010 */
7270 #define DSI_VVSACR_VSA4 DSI_VVSACR_VSA4_Msk
7271 #define DSI_VVSACR_VSA5_Pos (5U)
7272 #define DSI_VVSACR_VSA5_Msk (0x1U << DSI_VVSACR_VSA5_Pos) /*!< 0x00000020 */
7273 #define DSI_VVSACR_VSA5 DSI_VVSACR_VSA5_Msk
7274 #define DSI_VVSACR_VSA6_Pos (6U)
7275 #define DSI_VVSACR_VSA6_Msk (0x1U << DSI_VVSACR_VSA6_Pos) /*!< 0x00000040 */
7276 #define DSI_VVSACR_VSA6 DSI_VVSACR_VSA6_Msk
7277 #define DSI_VVSACR_VSA7_Pos (7U)
7278 #define DSI_VVSACR_VSA7_Msk (0x1U << DSI_VVSACR_VSA7_Pos) /*!< 0x00000080 */
7279 #define DSI_VVSACR_VSA7 DSI_VVSACR_VSA7_Msk
7280 #define DSI_VVSACR_VSA8_Pos (8U)
7281 #define DSI_VVSACR_VSA8_Msk (0x1U << DSI_VVSACR_VSA8_Pos) /*!< 0x00000100 */
7282 #define DSI_VVSACR_VSA8 DSI_VVSACR_VSA8_Msk
7283 #define DSI_VVSACR_VSA9_Pos (9U)
7284 #define DSI_VVSACR_VSA9_Msk (0x1U << DSI_VVSACR_VSA9_Pos) /*!< 0x00000200 */
7285 #define DSI_VVSACR_VSA9 DSI_VVSACR_VSA9_Msk
7286
7287 /******************* Bit definition for DSI_VVBPCR register *************/
7288 #define DSI_VVBPCR_VBP_Pos (0U)
7289 #define DSI_VVBPCR_VBP_Msk (0x3FFU << DSI_VVBPCR_VBP_Pos) /*!< 0x000003FF */
7290 #define DSI_VVBPCR_VBP DSI_VVBPCR_VBP_Msk /*!< Vertical Back-Porch duration */
7291 #define DSI_VVBPCR_VBP0_Pos (0U)
7292 #define DSI_VVBPCR_VBP0_Msk (0x1U << DSI_VVBPCR_VBP0_Pos) /*!< 0x00000001 */
7293 #define DSI_VVBPCR_VBP0 DSI_VVBPCR_VBP0_Msk
7294 #define DSI_VVBPCR_VBP1_Pos (1U)
7295 #define DSI_VVBPCR_VBP1_Msk (0x1U << DSI_VVBPCR_VBP1_Pos) /*!< 0x00000002 */
7296 #define DSI_VVBPCR_VBP1 DSI_VVBPCR_VBP1_Msk
7297 #define DSI_VVBPCR_VBP2_Pos (2U)
7298 #define DSI_VVBPCR_VBP2_Msk (0x1U << DSI_VVBPCR_VBP2_Pos) /*!< 0x00000004 */
7299 #define DSI_VVBPCR_VBP2 DSI_VVBPCR_VBP2_Msk
7300 #define DSI_VVBPCR_VBP3_Pos (3U)
7301 #define DSI_VVBPCR_VBP3_Msk (0x1U << DSI_VVBPCR_VBP3_Pos) /*!< 0x00000008 */
7302 #define DSI_VVBPCR_VBP3 DSI_VVBPCR_VBP3_Msk
7303 #define DSI_VVBPCR_VBP4_Pos (4U)
7304 #define DSI_VVBPCR_VBP4_Msk (0x1U << DSI_VVBPCR_VBP4_Pos) /*!< 0x00000010 */
7305 #define DSI_VVBPCR_VBP4 DSI_VVBPCR_VBP4_Msk
7306 #define DSI_VVBPCR_VBP5_Pos (5U)
7307 #define DSI_VVBPCR_VBP5_Msk (0x1U << DSI_VVBPCR_VBP5_Pos) /*!< 0x00000020 */
7308 #define DSI_VVBPCR_VBP5 DSI_VVBPCR_VBP5_Msk
7309 #define DSI_VVBPCR_VBP6_Pos (6U)
7310 #define DSI_VVBPCR_VBP6_Msk (0x1U << DSI_VVBPCR_VBP6_Pos) /*!< 0x00000040 */
7311 #define DSI_VVBPCR_VBP6 DSI_VVBPCR_VBP6_Msk
7312 #define DSI_VVBPCR_VBP7_Pos (7U)
7313 #define DSI_VVBPCR_VBP7_Msk (0x1U << DSI_VVBPCR_VBP7_Pos) /*!< 0x00000080 */
7314 #define DSI_VVBPCR_VBP7 DSI_VVBPCR_VBP7_Msk
7315 #define DSI_VVBPCR_VBP8_Pos (8U)
7316 #define DSI_VVBPCR_VBP8_Msk (0x1U << DSI_VVBPCR_VBP8_Pos) /*!< 0x00000100 */
7317 #define DSI_VVBPCR_VBP8 DSI_VVBPCR_VBP8_Msk
7318 #define DSI_VVBPCR_VBP9_Pos (9U)
7319 #define DSI_VVBPCR_VBP9_Msk (0x1U << DSI_VVBPCR_VBP9_Pos) /*!< 0x00000200 */
7320 #define DSI_VVBPCR_VBP9 DSI_VVBPCR_VBP9_Msk
7321
7322 /******************* Bit definition for DSI_VVFPCR register *************/
7323 #define DSI_VVFPCR_VFP_Pos (0U)
7324 #define DSI_VVFPCR_VFP_Msk (0x3FFU << DSI_VVFPCR_VFP_Pos) /*!< 0x000003FF */
7325 #define DSI_VVFPCR_VFP DSI_VVFPCR_VFP_Msk /*!< Vertical Front-Porch duration */
7326 #define DSI_VVFPCR_VFP0_Pos (0U)
7327 #define DSI_VVFPCR_VFP0_Msk (0x1U << DSI_VVFPCR_VFP0_Pos) /*!< 0x00000001 */
7328 #define DSI_VVFPCR_VFP0 DSI_VVFPCR_VFP0_Msk
7329 #define DSI_VVFPCR_VFP1_Pos (1U)
7330 #define DSI_VVFPCR_VFP1_Msk (0x1U << DSI_VVFPCR_VFP1_Pos) /*!< 0x00000002 */
7331 #define DSI_VVFPCR_VFP1 DSI_VVFPCR_VFP1_Msk
7332 #define DSI_VVFPCR_VFP2_Pos (2U)
7333 #define DSI_VVFPCR_VFP2_Msk (0x1U << DSI_VVFPCR_VFP2_Pos) /*!< 0x00000004 */
7334 #define DSI_VVFPCR_VFP2 DSI_VVFPCR_VFP2_Msk
7335 #define DSI_VVFPCR_VFP3_Pos (3U)
7336 #define DSI_VVFPCR_VFP3_Msk (0x1U << DSI_VVFPCR_VFP3_Pos) /*!< 0x00000008 */
7337 #define DSI_VVFPCR_VFP3 DSI_VVFPCR_VFP3_Msk
7338 #define DSI_VVFPCR_VFP4_Pos (4U)
7339 #define DSI_VVFPCR_VFP4_Msk (0x1U << DSI_VVFPCR_VFP4_Pos) /*!< 0x00000010 */
7340 #define DSI_VVFPCR_VFP4 DSI_VVFPCR_VFP4_Msk
7341 #define DSI_VVFPCR_VFP5_Pos (5U)
7342 #define DSI_VVFPCR_VFP5_Msk (0x1U << DSI_VVFPCR_VFP5_Pos) /*!< 0x00000020 */
7343 #define DSI_VVFPCR_VFP5 DSI_VVFPCR_VFP5_Msk
7344 #define DSI_VVFPCR_VFP6_Pos (6U)
7345 #define DSI_VVFPCR_VFP6_Msk (0x1U << DSI_VVFPCR_VFP6_Pos) /*!< 0x00000040 */
7346 #define DSI_VVFPCR_VFP6 DSI_VVFPCR_VFP6_Msk
7347 #define DSI_VVFPCR_VFP7_Pos (7U)
7348 #define DSI_VVFPCR_VFP7_Msk (0x1U << DSI_VVFPCR_VFP7_Pos) /*!< 0x00000080 */
7349 #define DSI_VVFPCR_VFP7 DSI_VVFPCR_VFP7_Msk
7350 #define DSI_VVFPCR_VFP8_Pos (8U)
7351 #define DSI_VVFPCR_VFP8_Msk (0x1U << DSI_VVFPCR_VFP8_Pos) /*!< 0x00000100 */
7352 #define DSI_VVFPCR_VFP8 DSI_VVFPCR_VFP8_Msk
7353 #define DSI_VVFPCR_VFP9_Pos (9U)
7354 #define DSI_VVFPCR_VFP9_Msk (0x1U << DSI_VVFPCR_VFP9_Pos) /*!< 0x00000200 */
7355 #define DSI_VVFPCR_VFP9 DSI_VVFPCR_VFP9_Msk
7356
7357 /******************* Bit definition for DSI_VVACR register **************/
7358 #define DSI_VVACR_VA_Pos (0U)
7359 #define DSI_VVACR_VA_Msk (0x3FFFU << DSI_VVACR_VA_Pos) /*!< 0x00003FFF */
7360 #define DSI_VVACR_VA DSI_VVACR_VA_Msk /*!< Vertical Active duration */
7361 #define DSI_VVACR_VA0_Pos (0U)
7362 #define DSI_VVACR_VA0_Msk (0x1U << DSI_VVACR_VA0_Pos) /*!< 0x00000001 */
7363 #define DSI_VVACR_VA0 DSI_VVACR_VA0_Msk
7364 #define DSI_VVACR_VA1_Pos (1U)
7365 #define DSI_VVACR_VA1_Msk (0x1U << DSI_VVACR_VA1_Pos) /*!< 0x00000002 */
7366 #define DSI_VVACR_VA1 DSI_VVACR_VA1_Msk
7367 #define DSI_VVACR_VA2_Pos (2U)
7368 #define DSI_VVACR_VA2_Msk (0x1U << DSI_VVACR_VA2_Pos) /*!< 0x00000004 */
7369 #define DSI_VVACR_VA2 DSI_VVACR_VA2_Msk
7370 #define DSI_VVACR_VA3_Pos (3U)
7371 #define DSI_VVACR_VA3_Msk (0x1U << DSI_VVACR_VA3_Pos) /*!< 0x00000008 */
7372 #define DSI_VVACR_VA3 DSI_VVACR_VA3_Msk
7373 #define DSI_VVACR_VA4_Pos (4U)
7374 #define DSI_VVACR_VA4_Msk (0x1U << DSI_VVACR_VA4_Pos) /*!< 0x00000010 */
7375 #define DSI_VVACR_VA4 DSI_VVACR_VA4_Msk
7376 #define DSI_VVACR_VA5_Pos (5U)
7377 #define DSI_VVACR_VA5_Msk (0x1U << DSI_VVACR_VA5_Pos) /*!< 0x00000020 */
7378 #define DSI_VVACR_VA5 DSI_VVACR_VA5_Msk
7379 #define DSI_VVACR_VA6_Pos (6U)
7380 #define DSI_VVACR_VA6_Msk (0x1U << DSI_VVACR_VA6_Pos) /*!< 0x00000040 */
7381 #define DSI_VVACR_VA6 DSI_VVACR_VA6_Msk
7382 #define DSI_VVACR_VA7_Pos (7U)
7383 #define DSI_VVACR_VA7_Msk (0x1U << DSI_VVACR_VA7_Pos) /*!< 0x00000080 */
7384 #define DSI_VVACR_VA7 DSI_VVACR_VA7_Msk
7385 #define DSI_VVACR_VA8_Pos (8U)
7386 #define DSI_VVACR_VA8_Msk (0x1U << DSI_VVACR_VA8_Pos) /*!< 0x00000100 */
7387 #define DSI_VVACR_VA8 DSI_VVACR_VA8_Msk
7388 #define DSI_VVACR_VA9_Pos (9U)
7389 #define DSI_VVACR_VA9_Msk (0x1U << DSI_VVACR_VA9_Pos) /*!< 0x00000200 */
7390 #define DSI_VVACR_VA9 DSI_VVACR_VA9_Msk
7391 #define DSI_VVACR_VA10_Pos (10U)
7392 #define DSI_VVACR_VA10_Msk (0x1U << DSI_VVACR_VA10_Pos) /*!< 0x00000400 */
7393 #define DSI_VVACR_VA10 DSI_VVACR_VA10_Msk
7394 #define DSI_VVACR_VA11_Pos (11U)
7395 #define DSI_VVACR_VA11_Msk (0x1U << DSI_VVACR_VA11_Pos) /*!< 0x00000800 */
7396 #define DSI_VVACR_VA11 DSI_VVACR_VA11_Msk
7397 #define DSI_VVACR_VA12_Pos (12U)
7398 #define DSI_VVACR_VA12_Msk (0x1U << DSI_VVACR_VA12_Pos) /*!< 0x00001000 */
7399 #define DSI_VVACR_VA12 DSI_VVACR_VA12_Msk
7400 #define DSI_VVACR_VA13_Pos (13U)
7401 #define DSI_VVACR_VA13_Msk (0x1U << DSI_VVACR_VA13_Pos) /*!< 0x00002000 */
7402 #define DSI_VVACR_VA13 DSI_VVACR_VA13_Msk
7403
7404 /******************* Bit definition for DSI_LCCR register ***************/
7405 #define DSI_LCCR_CMDSIZE_Pos (0U)
7406 #define DSI_LCCR_CMDSIZE_Msk (0xFFFFU << DSI_LCCR_CMDSIZE_Pos) /*!< 0x0000FFFF */
7407 #define DSI_LCCR_CMDSIZE DSI_LCCR_CMDSIZE_Msk /*!< Command Size */
7408 #define DSI_LCCR_CMDSIZE0_Pos (0U)
7409 #define DSI_LCCR_CMDSIZE0_Msk (0x1U << DSI_LCCR_CMDSIZE0_Pos) /*!< 0x00000001 */
7410 #define DSI_LCCR_CMDSIZE0 DSI_LCCR_CMDSIZE0_Msk
7411 #define DSI_LCCR_CMDSIZE1_Pos (1U)
7412 #define DSI_LCCR_CMDSIZE1_Msk (0x1U << DSI_LCCR_CMDSIZE1_Pos) /*!< 0x00000002 */
7413 #define DSI_LCCR_CMDSIZE1 DSI_LCCR_CMDSIZE1_Msk
7414 #define DSI_LCCR_CMDSIZE2_Pos (2U)
7415 #define DSI_LCCR_CMDSIZE2_Msk (0x1U << DSI_LCCR_CMDSIZE2_Pos) /*!< 0x00000004 */
7416 #define DSI_LCCR_CMDSIZE2 DSI_LCCR_CMDSIZE2_Msk
7417 #define DSI_LCCR_CMDSIZE3_Pos (3U)
7418 #define DSI_LCCR_CMDSIZE3_Msk (0x1U << DSI_LCCR_CMDSIZE3_Pos) /*!< 0x00000008 */
7419 #define DSI_LCCR_CMDSIZE3 DSI_LCCR_CMDSIZE3_Msk
7420 #define DSI_LCCR_CMDSIZE4_Pos (4U)
7421 #define DSI_LCCR_CMDSIZE4_Msk (0x1U << DSI_LCCR_CMDSIZE4_Pos) /*!< 0x00000010 */
7422 #define DSI_LCCR_CMDSIZE4 DSI_LCCR_CMDSIZE4_Msk
7423 #define DSI_LCCR_CMDSIZE5_Pos (5U)
7424 #define DSI_LCCR_CMDSIZE5_Msk (0x1U << DSI_LCCR_CMDSIZE5_Pos) /*!< 0x00000020 */
7425 #define DSI_LCCR_CMDSIZE5 DSI_LCCR_CMDSIZE5_Msk
7426 #define DSI_LCCR_CMDSIZE6_Pos (6U)
7427 #define DSI_LCCR_CMDSIZE6_Msk (0x1U << DSI_LCCR_CMDSIZE6_Pos) /*!< 0x00000040 */
7428 #define DSI_LCCR_CMDSIZE6 DSI_LCCR_CMDSIZE6_Msk
7429 #define DSI_LCCR_CMDSIZE7_Pos (7U)
7430 #define DSI_LCCR_CMDSIZE7_Msk (0x1U << DSI_LCCR_CMDSIZE7_Pos) /*!< 0x00000080 */
7431 #define DSI_LCCR_CMDSIZE7 DSI_LCCR_CMDSIZE7_Msk
7432 #define DSI_LCCR_CMDSIZE8_Pos (8U)
7433 #define DSI_LCCR_CMDSIZE8_Msk (0x1U << DSI_LCCR_CMDSIZE8_Pos) /*!< 0x00000100 */
7434 #define DSI_LCCR_CMDSIZE8 DSI_LCCR_CMDSIZE8_Msk
7435 #define DSI_LCCR_CMDSIZE9_Pos (9U)
7436 #define DSI_LCCR_CMDSIZE9_Msk (0x1U << DSI_LCCR_CMDSIZE9_Pos) /*!< 0x00000200 */
7437 #define DSI_LCCR_CMDSIZE9 DSI_LCCR_CMDSIZE9_Msk
7438 #define DSI_LCCR_CMDSIZE10_Pos (10U)
7439 #define DSI_LCCR_CMDSIZE10_Msk (0x1U << DSI_LCCR_CMDSIZE10_Pos) /*!< 0x00000400 */
7440 #define DSI_LCCR_CMDSIZE10 DSI_LCCR_CMDSIZE10_Msk
7441 #define DSI_LCCR_CMDSIZE11_Pos (11U)
7442 #define DSI_LCCR_CMDSIZE11_Msk (0x1U << DSI_LCCR_CMDSIZE11_Pos) /*!< 0x00000800 */
7443 #define DSI_LCCR_CMDSIZE11 DSI_LCCR_CMDSIZE11_Msk
7444 #define DSI_LCCR_CMDSIZE12_Pos (12U)
7445 #define DSI_LCCR_CMDSIZE12_Msk (0x1U << DSI_LCCR_CMDSIZE12_Pos) /*!< 0x00001000 */
7446 #define DSI_LCCR_CMDSIZE12 DSI_LCCR_CMDSIZE12_Msk
7447 #define DSI_LCCR_CMDSIZE13_Pos (13U)
7448 #define DSI_LCCR_CMDSIZE13_Msk (0x1U << DSI_LCCR_CMDSIZE13_Pos) /*!< 0x00002000 */
7449 #define DSI_LCCR_CMDSIZE13 DSI_LCCR_CMDSIZE13_Msk
7450 #define DSI_LCCR_CMDSIZE14_Pos (14U)
7451 #define DSI_LCCR_CMDSIZE14_Msk (0x1U << DSI_LCCR_CMDSIZE14_Pos) /*!< 0x00004000 */
7452 #define DSI_LCCR_CMDSIZE14 DSI_LCCR_CMDSIZE14_Msk
7453 #define DSI_LCCR_CMDSIZE15_Pos (15U)
7454 #define DSI_LCCR_CMDSIZE15_Msk (0x1U << DSI_LCCR_CMDSIZE15_Pos) /*!< 0x00008000 */
7455 #define DSI_LCCR_CMDSIZE15 DSI_LCCR_CMDSIZE15_Msk
7456
7457 /******************* Bit definition for DSI_CMCR register ***************/
7458 #define DSI_CMCR_TEARE_Pos (0U)
7459 #define DSI_CMCR_TEARE_Msk (0x1U << DSI_CMCR_TEARE_Pos) /*!< 0x00000001 */
7460 #define DSI_CMCR_TEARE DSI_CMCR_TEARE_Msk /*!< Tearing Effect Acknowledge Request Enable */
7461 #define DSI_CMCR_ARE_Pos (1U)
7462 #define DSI_CMCR_ARE_Msk (0x1U << DSI_CMCR_ARE_Pos) /*!< 0x00000002 */
7463 #define DSI_CMCR_ARE DSI_CMCR_ARE_Msk /*!< Acknowledge Request Enable */
7464 #define DSI_CMCR_GSW0TX_Pos (8U)
7465 #define DSI_CMCR_GSW0TX_Msk (0x1U << DSI_CMCR_GSW0TX_Pos) /*!< 0x00000100 */
7466 #define DSI_CMCR_GSW0TX DSI_CMCR_GSW0TX_Msk /*!< Generic Short Write Zero parameters Transmission */
7467 #define DSI_CMCR_GSW1TX_Pos (9U)
7468 #define DSI_CMCR_GSW1TX_Msk (0x1U << DSI_CMCR_GSW1TX_Pos) /*!< 0x00000200 */
7469 #define DSI_CMCR_GSW1TX DSI_CMCR_GSW1TX_Msk /*!< Generic Short Write One parameters Transmission */
7470 #define DSI_CMCR_GSW2TX_Pos (10U)
7471 #define DSI_CMCR_GSW2TX_Msk (0x1U << DSI_CMCR_GSW2TX_Pos) /*!< 0x00000400 */
7472 #define DSI_CMCR_GSW2TX DSI_CMCR_GSW2TX_Msk /*!< Generic Short Write Two parameters Transmission */
7473 #define DSI_CMCR_GSR0TX_Pos (11U)
7474 #define DSI_CMCR_GSR0TX_Msk (0x1U << DSI_CMCR_GSR0TX_Pos) /*!< 0x00000800 */
7475 #define DSI_CMCR_GSR0TX DSI_CMCR_GSR0TX_Msk /*!< Generic Short Read Zero parameters Transmission */
7476 #define DSI_CMCR_GSR1TX_Pos (12U)
7477 #define DSI_CMCR_GSR1TX_Msk (0x1U << DSI_CMCR_GSR1TX_Pos) /*!< 0x00001000 */
7478 #define DSI_CMCR_GSR1TX DSI_CMCR_GSR1TX_Msk /*!< Generic Short Read One parameters Transmission */
7479 #define DSI_CMCR_GSR2TX_Pos (13U)
7480 #define DSI_CMCR_GSR2TX_Msk (0x1U << DSI_CMCR_GSR2TX_Pos) /*!< 0x00002000 */
7481 #define DSI_CMCR_GSR2TX DSI_CMCR_GSR2TX_Msk /*!< Generic Short Read Two parameters Transmission */
7482 #define DSI_CMCR_GLWTX_Pos (14U)
7483 #define DSI_CMCR_GLWTX_Msk (0x1U << DSI_CMCR_GLWTX_Pos) /*!< 0x00004000 */
7484 #define DSI_CMCR_GLWTX DSI_CMCR_GLWTX_Msk /*!< Generic Long Write Transmission */
7485 #define DSI_CMCR_DSW0TX_Pos (16U)
7486 #define DSI_CMCR_DSW0TX_Msk (0x1U << DSI_CMCR_DSW0TX_Pos) /*!< 0x00010000 */
7487 #define DSI_CMCR_DSW0TX DSI_CMCR_DSW0TX_Msk /*!< DCS Short Write Zero parameter Transmission */
7488 #define DSI_CMCR_DSW1TX_Pos (17U)
7489 #define DSI_CMCR_DSW1TX_Msk (0x1U << DSI_CMCR_DSW1TX_Pos) /*!< 0x00020000 */
7490 #define DSI_CMCR_DSW1TX DSI_CMCR_DSW1TX_Msk /*!< DCS Short Read One parameter Transmission */
7491 #define DSI_CMCR_DSR0TX_Pos (18U)
7492 #define DSI_CMCR_DSR0TX_Msk (0x1U << DSI_CMCR_DSR0TX_Pos) /*!< 0x00040000 */
7493 #define DSI_CMCR_DSR0TX DSI_CMCR_DSR0TX_Msk /*!< DCS Short Read Zero parameter Transmission */
7494 #define DSI_CMCR_DLWTX_Pos (19U)
7495 #define DSI_CMCR_DLWTX_Msk (0x1U << DSI_CMCR_DLWTX_Pos) /*!< 0x00080000 */
7496 #define DSI_CMCR_DLWTX DSI_CMCR_DLWTX_Msk /*!< DCS Long Write Transmission */
7497 #define DSI_CMCR_MRDPS_Pos (24U)
7498 #define DSI_CMCR_MRDPS_Msk (0x1U << DSI_CMCR_MRDPS_Pos) /*!< 0x01000000 */
7499 #define DSI_CMCR_MRDPS DSI_CMCR_MRDPS_Msk /*!< Maximum Read Packet Size */
7500
7501 /******************* Bit definition for DSI_GHCR register ***************/
7502 #define DSI_GHCR_DT_Pos (0U)
7503 #define DSI_GHCR_DT_Msk (0x3FU << DSI_GHCR_DT_Pos) /*!< 0x0000003F */
7504 #define DSI_GHCR_DT DSI_GHCR_DT_Msk /*!< Type */
7505 #define DSI_GHCR_DT0_Pos (0U)
7506 #define DSI_GHCR_DT0_Msk (0x1U << DSI_GHCR_DT0_Pos) /*!< 0x00000001 */
7507 #define DSI_GHCR_DT0 DSI_GHCR_DT0_Msk
7508 #define DSI_GHCR_DT1_Pos (1U)
7509 #define DSI_GHCR_DT1_Msk (0x1U << DSI_GHCR_DT1_Pos) /*!< 0x00000002 */
7510 #define DSI_GHCR_DT1 DSI_GHCR_DT1_Msk
7511 #define DSI_GHCR_DT2_Pos (2U)
7512 #define DSI_GHCR_DT2_Msk (0x1U << DSI_GHCR_DT2_Pos) /*!< 0x00000004 */
7513 #define DSI_GHCR_DT2 DSI_GHCR_DT2_Msk
7514 #define DSI_GHCR_DT3_Pos (3U)
7515 #define DSI_GHCR_DT3_Msk (0x1U << DSI_GHCR_DT3_Pos) /*!< 0x00000008 */
7516 #define DSI_GHCR_DT3 DSI_GHCR_DT3_Msk
7517 #define DSI_GHCR_DT4_Pos (4U)
7518 #define DSI_GHCR_DT4_Msk (0x1U << DSI_GHCR_DT4_Pos) /*!< 0x00000010 */
7519 #define DSI_GHCR_DT4 DSI_GHCR_DT4_Msk
7520 #define DSI_GHCR_DT5_Pos (5U)
7521 #define DSI_GHCR_DT5_Msk (0x1U << DSI_GHCR_DT5_Pos) /*!< 0x00000020 */
7522 #define DSI_GHCR_DT5 DSI_GHCR_DT5_Msk
7523
7524 #define DSI_GHCR_VCID_Pos (6U)
7525 #define DSI_GHCR_VCID_Msk (0x3U << DSI_GHCR_VCID_Pos) /*!< 0x000000C0 */
7526 #define DSI_GHCR_VCID DSI_GHCR_VCID_Msk /*!< Channel */
7527 #define DSI_GHCR_VCID0_Pos (6U)
7528 #define DSI_GHCR_VCID0_Msk (0x1U << DSI_GHCR_VCID0_Pos) /*!< 0x00000040 */
7529 #define DSI_GHCR_VCID0 DSI_GHCR_VCID0_Msk
7530 #define DSI_GHCR_VCID1_Pos (7U)
7531 #define DSI_GHCR_VCID1_Msk (0x1U << DSI_GHCR_VCID1_Pos) /*!< 0x00000080 */
7532 #define DSI_GHCR_VCID1 DSI_GHCR_VCID1_Msk
7533
7534 #define DSI_GHCR_WCLSB_Pos (8U)
7535 #define DSI_GHCR_WCLSB_Msk (0xFFU << DSI_GHCR_WCLSB_Pos) /*!< 0x0000FF00 */
7536 #define DSI_GHCR_WCLSB DSI_GHCR_WCLSB_Msk /*!< WordCount LSB */
7537 #define DSI_GHCR_WCLSB0_Pos (8U)
7538 #define DSI_GHCR_WCLSB0_Msk (0x1U << DSI_GHCR_WCLSB0_Pos) /*!< 0x00000100 */
7539 #define DSI_GHCR_WCLSB0 DSI_GHCR_WCLSB0_Msk
7540 #define DSI_GHCR_WCLSB1_Pos (9U)
7541 #define DSI_GHCR_WCLSB1_Msk (0x1U << DSI_GHCR_WCLSB1_Pos) /*!< 0x00000200 */
7542 #define DSI_GHCR_WCLSB1 DSI_GHCR_WCLSB1_Msk
7543 #define DSI_GHCR_WCLSB2_Pos (10U)
7544 #define DSI_GHCR_WCLSB2_Msk (0x1U << DSI_GHCR_WCLSB2_Pos) /*!< 0x00000400 */
7545 #define DSI_GHCR_WCLSB2 DSI_GHCR_WCLSB2_Msk
7546 #define DSI_GHCR_WCLSB3_Pos (11U)
7547 #define DSI_GHCR_WCLSB3_Msk (0x1U << DSI_GHCR_WCLSB3_Pos) /*!< 0x00000800 */
7548 #define DSI_GHCR_WCLSB3 DSI_GHCR_WCLSB3_Msk
7549 #define DSI_GHCR_WCLSB4_Pos (12U)
7550 #define DSI_GHCR_WCLSB4_Msk (0x1U << DSI_GHCR_WCLSB4_Pos) /*!< 0x00001000 */
7551 #define DSI_GHCR_WCLSB4 DSI_GHCR_WCLSB4_Msk
7552 #define DSI_GHCR_WCLSB5_Pos (13U)
7553 #define DSI_GHCR_WCLSB5_Msk (0x1U << DSI_GHCR_WCLSB5_Pos) /*!< 0x00002000 */
7554 #define DSI_GHCR_WCLSB5 DSI_GHCR_WCLSB5_Msk
7555 #define DSI_GHCR_WCLSB6_Pos (14U)
7556 #define DSI_GHCR_WCLSB6_Msk (0x1U << DSI_GHCR_WCLSB6_Pos) /*!< 0x00004000 */
7557 #define DSI_GHCR_WCLSB6 DSI_GHCR_WCLSB6_Msk
7558 #define DSI_GHCR_WCLSB7_Pos (15U)
7559 #define DSI_GHCR_WCLSB7_Msk (0x1U << DSI_GHCR_WCLSB7_Pos) /*!< 0x00008000 */
7560 #define DSI_GHCR_WCLSB7 DSI_GHCR_WCLSB7_Msk
7561
7562 #define DSI_GHCR_WCMSB_Pos (16U)
7563 #define DSI_GHCR_WCMSB_Msk (0xFFU << DSI_GHCR_WCMSB_Pos) /*!< 0x00FF0000 */
7564 #define DSI_GHCR_WCMSB DSI_GHCR_WCMSB_Msk /*!< WordCount MSB */
7565 #define DSI_GHCR_WCMSB0_Pos (16U)
7566 #define DSI_GHCR_WCMSB0_Msk (0x1U << DSI_GHCR_WCMSB0_Pos) /*!< 0x00010000 */
7567 #define DSI_GHCR_WCMSB0 DSI_GHCR_WCMSB0_Msk
7568 #define DSI_GHCR_WCMSB1_Pos (17U)
7569 #define DSI_GHCR_WCMSB1_Msk (0x1U << DSI_GHCR_WCMSB1_Pos) /*!< 0x00020000 */
7570 #define DSI_GHCR_WCMSB1 DSI_GHCR_WCMSB1_Msk
7571 #define DSI_GHCR_WCMSB2_Pos (18U)
7572 #define DSI_GHCR_WCMSB2_Msk (0x1U << DSI_GHCR_WCMSB2_Pos) /*!< 0x00040000 */
7573 #define DSI_GHCR_WCMSB2 DSI_GHCR_WCMSB2_Msk
7574 #define DSI_GHCR_WCMSB3_Pos (19U)
7575 #define DSI_GHCR_WCMSB3_Msk (0x1U << DSI_GHCR_WCMSB3_Pos) /*!< 0x00080000 */
7576 #define DSI_GHCR_WCMSB3 DSI_GHCR_WCMSB3_Msk
7577 #define DSI_GHCR_WCMSB4_Pos (20U)
7578 #define DSI_GHCR_WCMSB4_Msk (0x1U << DSI_GHCR_WCMSB4_Pos) /*!< 0x00100000 */
7579 #define DSI_GHCR_WCMSB4 DSI_GHCR_WCMSB4_Msk
7580 #define DSI_GHCR_WCMSB5_Pos (21U)
7581 #define DSI_GHCR_WCMSB5_Msk (0x1U << DSI_GHCR_WCMSB5_Pos) /*!< 0x00200000 */
7582 #define DSI_GHCR_WCMSB5 DSI_GHCR_WCMSB5_Msk
7583 #define DSI_GHCR_WCMSB6_Pos (22U)
7584 #define DSI_GHCR_WCMSB6_Msk (0x1U << DSI_GHCR_WCMSB6_Pos) /*!< 0x00400000 */
7585 #define DSI_GHCR_WCMSB6 DSI_GHCR_WCMSB6_Msk
7586 #define DSI_GHCR_WCMSB7_Pos (23U)
7587 #define DSI_GHCR_WCMSB7_Msk (0x1U << DSI_GHCR_WCMSB7_Pos) /*!< 0x00800000 */
7588 #define DSI_GHCR_WCMSB7 DSI_GHCR_WCMSB7_Msk
7589
7590 /******************* Bit definition for DSI_GPDR register ***************/
7591 #define DSI_GPDR_DATA1_Pos (0U)
7592 #define DSI_GPDR_DATA1_Msk (0xFFU << DSI_GPDR_DATA1_Pos) /*!< 0x000000FF */
7593 #define DSI_GPDR_DATA1 DSI_GPDR_DATA1_Msk /*!< Payload Byte 1 */
7594 #define DSI_GPDR_DATA1_0 (0x01U << DSI_GPDR_DATA1_Pos) /*!< 0x00000001 */
7595 #define DSI_GPDR_DATA1_1 (0x02U << DSI_GPDR_DATA1_Pos) /*!< 0x00000002 */
7596 #define DSI_GPDR_DATA1_2 (0x04U << DSI_GPDR_DATA1_Pos) /*!< 0x00000004 */
7597 #define DSI_GPDR_DATA1_3 (0x08U << DSI_GPDR_DATA1_Pos) /*!< 0x00000008 */
7598 #define DSI_GPDR_DATA1_4 (0x10U << DSI_GPDR_DATA1_Pos) /*!< 0x00000010 */
7599 #define DSI_GPDR_DATA1_5 (0x20U << DSI_GPDR_DATA1_Pos) /*!< 0x00000020 */
7600 #define DSI_GPDR_DATA1_6 (0x40U << DSI_GPDR_DATA1_Pos) /*!< 0x00000040 */
7601 #define DSI_GPDR_DATA1_7 (0x80U << DSI_GPDR_DATA1_Pos) /*!< 0x00000080 */
7602
7603 #define DSI_GPDR_DATA2_Pos (8U)
7604 #define DSI_GPDR_DATA2_Msk (0xFFU << DSI_GPDR_DATA2_Pos) /*!< 0x0000FF00 */
7605 #define DSI_GPDR_DATA2 DSI_GPDR_DATA2_Msk /*!< Payload Byte 2 */
7606 #define DSI_GPDR_DATA2_0 (0x01U << DSI_GPDR_DATA2_Pos) /*!< 0x00000100 */
7607 #define DSI_GPDR_DATA2_1 (0x02U << DSI_GPDR_DATA2_Pos) /*!< 0x00000200 */
7608 #define DSI_GPDR_DATA2_2 (0x04U << DSI_GPDR_DATA2_Pos) /*!< 0x00000400 */
7609 #define DSI_GPDR_DATA2_3 (0x08U << DSI_GPDR_DATA2_Pos) /*!< 0x00000800 */
7610 #define DSI_GPDR_DATA2_4 (0x10U << DSI_GPDR_DATA2_Pos) /*!< 0x00001000 */
7611 #define DSI_GPDR_DATA2_5 (0x20U << DSI_GPDR_DATA2_Pos) /*!< 0x00002000 */
7612 #define DSI_GPDR_DATA2_6 (0x40U << DSI_GPDR_DATA2_Pos) /*!< 0x00004000 */
7613 #define DSI_GPDR_DATA2_7 (0x80U << DSI_GPDR_DATA2_Pos) /*!< 0x00008000 */
7614
7615 #define DSI_GPDR_DATA3_Pos (16U)
7616 #define DSI_GPDR_DATA3_Msk (0xFFU << DSI_GPDR_DATA3_Pos) /*!< 0x00FF0000 */
7617 #define DSI_GPDR_DATA3 DSI_GPDR_DATA3_Msk /*!< Payload Byte 3 */
7618 #define DSI_GPDR_DATA3_0 (0x01U << DSI_GPDR_DATA3_Pos) /*!< 0x00010000 */
7619 #define DSI_GPDR_DATA3_1 (0x02U << DSI_GPDR_DATA3_Pos) /*!< 0x00020000 */
7620 #define DSI_GPDR_DATA3_2 (0x04U << DSI_GPDR_DATA3_Pos) /*!< 0x00040000 */
7621 #define DSI_GPDR_DATA3_3 (0x08U << DSI_GPDR_DATA3_Pos) /*!< 0x00080000 */
7622 #define DSI_GPDR_DATA3_4 (0x10U << DSI_GPDR_DATA3_Pos) /*!< 0x00100000 */
7623 #define DSI_GPDR_DATA3_5 (0x20U << DSI_GPDR_DATA3_Pos) /*!< 0x00200000 */
7624 #define DSI_GPDR_DATA3_6 (0x40U << DSI_GPDR_DATA3_Pos) /*!< 0x00400000 */
7625 #define DSI_GPDR_DATA3_7 (0x80U << DSI_GPDR_DATA3_Pos) /*!< 0x00800000 */
7626
7627 #define DSI_GPDR_DATA4_Pos (24U)
7628 #define DSI_GPDR_DATA4_Msk (0xFFU << DSI_GPDR_DATA4_Pos) /*!< 0xFF000000 */
7629 #define DSI_GPDR_DATA4 DSI_GPDR_DATA4_Msk /*!< Payload Byte 4 */
7630 #define DSI_GPDR_DATA4_0 (0x01U << DSI_GPDR_DATA4_Pos) /*!< 0x01000000 */
7631 #define DSI_GPDR_DATA4_1 (0x02U << DSI_GPDR_DATA4_Pos) /*!< 0x02000000 */
7632 #define DSI_GPDR_DATA4_2 (0x04U << DSI_GPDR_DATA4_Pos) /*!< 0x04000000 */
7633 #define DSI_GPDR_DATA4_3 (0x08U << DSI_GPDR_DATA4_Pos) /*!< 0x08000000 */
7634 #define DSI_GPDR_DATA4_4 (0x10U << DSI_GPDR_DATA4_Pos) /*!< 0x10000000 */
7635 #define DSI_GPDR_DATA4_5 (0x20U << DSI_GPDR_DATA4_Pos) /*!< 0x20000000 */
7636 #define DSI_GPDR_DATA4_6 (0x40U << DSI_GPDR_DATA4_Pos) /*!< 0x40000000 */
7637 #define DSI_GPDR_DATA4_7 (0x80U << DSI_GPDR_DATA4_Pos) /*!< 0x80000000 */
7638
7639 /******************* Bit definition for DSI_GPSR register ***************/
7640 #define DSI_GPSR_CMDFE_Pos (0U)
7641 #define DSI_GPSR_CMDFE_Msk (0x1U << DSI_GPSR_CMDFE_Pos) /*!< 0x00000001 */
7642 #define DSI_GPSR_CMDFE DSI_GPSR_CMDFE_Msk /*!< Command FIFO Empty */
7643 #define DSI_GPSR_CMDFF_Pos (1U)
7644 #define DSI_GPSR_CMDFF_Msk (0x1U << DSI_GPSR_CMDFF_Pos) /*!< 0x00000002 */
7645 #define DSI_GPSR_CMDFF DSI_GPSR_CMDFF_Msk /*!< Command FIFO Full */
7646 #define DSI_GPSR_PWRFE_Pos (2U)
7647 #define DSI_GPSR_PWRFE_Msk (0x1U << DSI_GPSR_PWRFE_Pos) /*!< 0x00000004 */
7648 #define DSI_GPSR_PWRFE DSI_GPSR_PWRFE_Msk /*!< Payload Write FIFO Empty */
7649 #define DSI_GPSR_PWRFF_Pos (3U)
7650 #define DSI_GPSR_PWRFF_Msk (0x1U << DSI_GPSR_PWRFF_Pos) /*!< 0x00000008 */
7651 #define DSI_GPSR_PWRFF DSI_GPSR_PWRFF_Msk /*!< Payload Write FIFO Full */
7652 #define DSI_GPSR_PRDFE_Pos (4U)
7653 #define DSI_GPSR_PRDFE_Msk (0x1U << DSI_GPSR_PRDFE_Pos) /*!< 0x00000010 */
7654 #define DSI_GPSR_PRDFE DSI_GPSR_PRDFE_Msk /*!< Payload Read FIFO Empty */
7655 #define DSI_GPSR_PRDFF_Pos (5U)
7656 #define DSI_GPSR_PRDFF_Msk (0x1U << DSI_GPSR_PRDFF_Pos) /*!< 0x00000020 */
7657 #define DSI_GPSR_PRDFF DSI_GPSR_PRDFF_Msk /*!< Payload Read FIFO Full */
7658 #define DSI_GPSR_RCB_Pos (6U)
7659 #define DSI_GPSR_RCB_Msk (0x1U << DSI_GPSR_RCB_Pos) /*!< 0x00000040 */
7660 #define DSI_GPSR_RCB DSI_GPSR_RCB_Msk /*!< Read Command Busy */
7661
7662 /******************* Bit definition for DSI_TCCR0 register **************/
7663 #define DSI_TCCR0_LPRX_TOCNT_Pos (0U)
7664 #define DSI_TCCR0_LPRX_TOCNT_Msk (0xFFFFU << DSI_TCCR0_LPRX_TOCNT_Pos) /*!< 0x0000FFFF */
7665 #define DSI_TCCR0_LPRX_TOCNT DSI_TCCR0_LPRX_TOCNT_Msk /*!< Low-power Reception Timeout Counter */
7666 #define DSI_TCCR0_LPRX_TOCNT0_Pos (0U)
7667 #define DSI_TCCR0_LPRX_TOCNT0_Msk (0x1U << DSI_TCCR0_LPRX_TOCNT0_Pos) /*!< 0x00000001 */
7668 #define DSI_TCCR0_LPRX_TOCNT0 DSI_TCCR0_LPRX_TOCNT0_Msk
7669 #define DSI_TCCR0_LPRX_TOCNT1_Pos (1U)
7670 #define DSI_TCCR0_LPRX_TOCNT1_Msk (0x1U << DSI_TCCR0_LPRX_TOCNT1_Pos) /*!< 0x00000002 */
7671 #define DSI_TCCR0_LPRX_TOCNT1 DSI_TCCR0_LPRX_TOCNT1_Msk
7672 #define DSI_TCCR0_LPRX_TOCNT2_Pos (2U)
7673 #define DSI_TCCR0_LPRX_TOCNT2_Msk (0x1U << DSI_TCCR0_LPRX_TOCNT2_Pos) /*!< 0x00000004 */
7674 #define DSI_TCCR0_LPRX_TOCNT2 DSI_TCCR0_LPRX_TOCNT2_Msk
7675 #define DSI_TCCR0_LPRX_TOCNT3_Pos (3U)
7676 #define DSI_TCCR0_LPRX_TOCNT3_Msk (0x1U << DSI_TCCR0_LPRX_TOCNT3_Pos) /*!< 0x00000008 */
7677 #define DSI_TCCR0_LPRX_TOCNT3 DSI_TCCR0_LPRX_TOCNT3_Msk
7678 #define DSI_TCCR0_LPRX_TOCNT4_Pos (4U)
7679 #define DSI_TCCR0_LPRX_TOCNT4_Msk (0x1U << DSI_TCCR0_LPRX_TOCNT4_Pos) /*!< 0x00000010 */
7680 #define DSI_TCCR0_LPRX_TOCNT4 DSI_TCCR0_LPRX_TOCNT4_Msk
7681 #define DSI_TCCR0_LPRX_TOCNT5_Pos (5U)
7682 #define DSI_TCCR0_LPRX_TOCNT5_Msk (0x1U << DSI_TCCR0_LPRX_TOCNT5_Pos) /*!< 0x00000020 */
7683 #define DSI_TCCR0_LPRX_TOCNT5 DSI_TCCR0_LPRX_TOCNT5_Msk
7684 #define DSI_TCCR0_LPRX_TOCNT6_Pos (6U)
7685 #define DSI_TCCR0_LPRX_TOCNT6_Msk (0x1U << DSI_TCCR0_LPRX_TOCNT6_Pos) /*!< 0x00000040 */
7686 #define DSI_TCCR0_LPRX_TOCNT6 DSI_TCCR0_LPRX_TOCNT6_Msk
7687 #define DSI_TCCR0_LPRX_TOCNT7_Pos (7U)
7688 #define DSI_TCCR0_LPRX_TOCNT7_Msk (0x1U << DSI_TCCR0_LPRX_TOCNT7_Pos) /*!< 0x00000080 */
7689 #define DSI_TCCR0_LPRX_TOCNT7 DSI_TCCR0_LPRX_TOCNT7_Msk
7690 #define DSI_TCCR0_LPRX_TOCNT8_Pos (8U)
7691 #define DSI_TCCR0_LPRX_TOCNT8_Msk (0x1U << DSI_TCCR0_LPRX_TOCNT8_Pos) /*!< 0x00000100 */
7692 #define DSI_TCCR0_LPRX_TOCNT8 DSI_TCCR0_LPRX_TOCNT8_Msk
7693 #define DSI_TCCR0_LPRX_TOCNT9_Pos (9U)
7694 #define DSI_TCCR0_LPRX_TOCNT9_Msk (0x1U << DSI_TCCR0_LPRX_TOCNT9_Pos) /*!< 0x00000200 */
7695 #define DSI_TCCR0_LPRX_TOCNT9 DSI_TCCR0_LPRX_TOCNT9_Msk
7696 #define DSI_TCCR0_LPRX_TOCNT10_Pos (10U)
7697 #define DSI_TCCR0_LPRX_TOCNT10_Msk (0x1U << DSI_TCCR0_LPRX_TOCNT10_Pos) /*!< 0x00000400 */
7698 #define DSI_TCCR0_LPRX_TOCNT10 DSI_TCCR0_LPRX_TOCNT10_Msk
7699 #define DSI_TCCR0_LPRX_TOCNT11_Pos (11U)
7700 #define DSI_TCCR0_LPRX_TOCNT11_Msk (0x1U << DSI_TCCR0_LPRX_TOCNT11_Pos) /*!< 0x00000800 */
7701 #define DSI_TCCR0_LPRX_TOCNT11 DSI_TCCR0_LPRX_TOCNT11_Msk
7702 #define DSI_TCCR0_LPRX_TOCNT12_Pos (12U)
7703 #define DSI_TCCR0_LPRX_TOCNT12_Msk (0x1U << DSI_TCCR0_LPRX_TOCNT12_Pos) /*!< 0x00001000 */
7704 #define DSI_TCCR0_LPRX_TOCNT12 DSI_TCCR0_LPRX_TOCNT12_Msk
7705 #define DSI_TCCR0_LPRX_TOCNT13_Pos (13U)
7706 #define DSI_TCCR0_LPRX_TOCNT13_Msk (0x1U << DSI_TCCR0_LPRX_TOCNT13_Pos) /*!< 0x00002000 */
7707 #define DSI_TCCR0_LPRX_TOCNT13 DSI_TCCR0_LPRX_TOCNT13_Msk
7708 #define DSI_TCCR0_LPRX_TOCNT14_Pos (14U)
7709 #define DSI_TCCR0_LPRX_TOCNT14_Msk (0x1U << DSI_TCCR0_LPRX_TOCNT14_Pos) /*!< 0x00004000 */
7710 #define DSI_TCCR0_LPRX_TOCNT14 DSI_TCCR0_LPRX_TOCNT14_Msk
7711 #define DSI_TCCR0_LPRX_TOCNT15_Pos (15U)
7712 #define DSI_TCCR0_LPRX_TOCNT15_Msk (0x1U << DSI_TCCR0_LPRX_TOCNT15_Pos) /*!< 0x00008000 */
7713 #define DSI_TCCR0_LPRX_TOCNT15 DSI_TCCR0_LPRX_TOCNT15_Msk
7714
7715 #define DSI_TCCR0_HSTX_TOCNT_Pos (16U)
7716 #define DSI_TCCR0_HSTX_TOCNT_Msk (0xFFFFU << DSI_TCCR0_HSTX_TOCNT_Pos) /*!< 0xFFFF0000 */
7717 #define DSI_TCCR0_HSTX_TOCNT DSI_TCCR0_HSTX_TOCNT_Msk /*!< High-Speed Transmission Timeout Counter */
7718 #define DSI_TCCR0_HSTX_TOCNT0_Pos (16U)
7719 #define DSI_TCCR0_HSTX_TOCNT0_Msk (0x1U << DSI_TCCR0_HSTX_TOCNT0_Pos) /*!< 0x00010000 */
7720 #define DSI_TCCR0_HSTX_TOCNT0 DSI_TCCR0_HSTX_TOCNT0_Msk
7721 #define DSI_TCCR0_HSTX_TOCNT1_Pos (17U)
7722 #define DSI_TCCR0_HSTX_TOCNT1_Msk (0x1U << DSI_TCCR0_HSTX_TOCNT1_Pos) /*!< 0x00020000 */
7723 #define DSI_TCCR0_HSTX_TOCNT1 DSI_TCCR0_HSTX_TOCNT1_Msk
7724 #define DSI_TCCR0_HSTX_TOCNT2_Pos (18U)
7725 #define DSI_TCCR0_HSTX_TOCNT2_Msk (0x1U << DSI_TCCR0_HSTX_TOCNT2_Pos) /*!< 0x00040000 */
7726 #define DSI_TCCR0_HSTX_TOCNT2 DSI_TCCR0_HSTX_TOCNT2_Msk
7727 #define DSI_TCCR0_HSTX_TOCNT3_Pos (19U)
7728 #define DSI_TCCR0_HSTX_TOCNT3_Msk (0x1U << DSI_TCCR0_HSTX_TOCNT3_Pos) /*!< 0x00080000 */
7729 #define DSI_TCCR0_HSTX_TOCNT3 DSI_TCCR0_HSTX_TOCNT3_Msk
7730 #define DSI_TCCR0_HSTX_TOCNT4_Pos (20U)
7731 #define DSI_TCCR0_HSTX_TOCNT4_Msk (0x1U << DSI_TCCR0_HSTX_TOCNT4_Pos) /*!< 0x00100000 */
7732 #define DSI_TCCR0_HSTX_TOCNT4 DSI_TCCR0_HSTX_TOCNT4_Msk
7733 #define DSI_TCCR0_HSTX_TOCNT5_Pos (21U)
7734 #define DSI_TCCR0_HSTX_TOCNT5_Msk (0x1U << DSI_TCCR0_HSTX_TOCNT5_Pos) /*!< 0x00200000 */
7735 #define DSI_TCCR0_HSTX_TOCNT5 DSI_TCCR0_HSTX_TOCNT5_Msk
7736 #define DSI_TCCR0_HSTX_TOCNT6_Pos (22U)
7737 #define DSI_TCCR0_HSTX_TOCNT6_Msk (0x1U << DSI_TCCR0_HSTX_TOCNT6_Pos) /*!< 0x00400000 */
7738 #define DSI_TCCR0_HSTX_TOCNT6 DSI_TCCR0_HSTX_TOCNT6_Msk
7739 #define DSI_TCCR0_HSTX_TOCNT7_Pos (23U)
7740 #define DSI_TCCR0_HSTX_TOCNT7_Msk (0x1U << DSI_TCCR0_HSTX_TOCNT7_Pos) /*!< 0x00800000 */
7741 #define DSI_TCCR0_HSTX_TOCNT7 DSI_TCCR0_HSTX_TOCNT7_Msk
7742 #define DSI_TCCR0_HSTX_TOCNT8_Pos (24U)
7743 #define DSI_TCCR0_HSTX_TOCNT8_Msk (0x1U << DSI_TCCR0_HSTX_TOCNT8_Pos) /*!< 0x01000000 */
7744 #define DSI_TCCR0_HSTX_TOCNT8 DSI_TCCR0_HSTX_TOCNT8_Msk
7745 #define DSI_TCCR0_HSTX_TOCNT9_Pos (25U)
7746 #define DSI_TCCR0_HSTX_TOCNT9_Msk (0x1U << DSI_TCCR0_HSTX_TOCNT9_Pos) /*!< 0x02000000 */
7747 #define DSI_TCCR0_HSTX_TOCNT9 DSI_TCCR0_HSTX_TOCNT9_Msk
7748 #define DSI_TCCR0_HSTX_TOCNT10_Pos (26U)
7749 #define DSI_TCCR0_HSTX_TOCNT10_Msk (0x1U << DSI_TCCR0_HSTX_TOCNT10_Pos) /*!< 0x04000000 */
7750 #define DSI_TCCR0_HSTX_TOCNT10 DSI_TCCR0_HSTX_TOCNT10_Msk
7751 #define DSI_TCCR0_HSTX_TOCNT11_Pos (27U)
7752 #define DSI_TCCR0_HSTX_TOCNT11_Msk (0x1U << DSI_TCCR0_HSTX_TOCNT11_Pos) /*!< 0x08000000 */
7753 #define DSI_TCCR0_HSTX_TOCNT11 DSI_TCCR0_HSTX_TOCNT11_Msk
7754 #define DSI_TCCR0_HSTX_TOCNT12_Pos (28U)
7755 #define DSI_TCCR0_HSTX_TOCNT12_Msk (0x1U << DSI_TCCR0_HSTX_TOCNT12_Pos) /*!< 0x10000000 */
7756 #define DSI_TCCR0_HSTX_TOCNT12 DSI_TCCR0_HSTX_TOCNT12_Msk
7757 #define DSI_TCCR0_HSTX_TOCNT13_Pos (29U)
7758 #define DSI_TCCR0_HSTX_TOCNT13_Msk (0x1U << DSI_TCCR0_HSTX_TOCNT13_Pos) /*!< 0x20000000 */
7759 #define DSI_TCCR0_HSTX_TOCNT13 DSI_TCCR0_HSTX_TOCNT13_Msk
7760 #define DSI_TCCR0_HSTX_TOCNT14_Pos (30U)
7761 #define DSI_TCCR0_HSTX_TOCNT14_Msk (0x1U << DSI_TCCR0_HSTX_TOCNT14_Pos) /*!< 0x40000000 */
7762 #define DSI_TCCR0_HSTX_TOCNT14 DSI_TCCR0_HSTX_TOCNT14_Msk
7763 #define DSI_TCCR0_HSTX_TOCNT15_Pos (31U)
7764 #define DSI_TCCR0_HSTX_TOCNT15_Msk (0x1U << DSI_TCCR0_HSTX_TOCNT15_Pos) /*!< 0x80000000 */
7765 #define DSI_TCCR0_HSTX_TOCNT15 DSI_TCCR0_HSTX_TOCNT15_Msk
7766
7767 /******************* Bit definition for DSI_TCCR1 register **************/
7768 #define DSI_TCCR1_HSRD_TOCNT_Pos (0U)
7769 #define DSI_TCCR1_HSRD_TOCNT_Msk (0xFFFFU << DSI_TCCR1_HSRD_TOCNT_Pos) /*!< 0x0000FFFF */
7770 #define DSI_TCCR1_HSRD_TOCNT DSI_TCCR1_HSRD_TOCNT_Msk /*!< High-Speed Read Timeout Counter */
7771 #define DSI_TCCR1_HSRD_TOCNT0_Pos (0U)
7772 #define DSI_TCCR1_HSRD_TOCNT0_Msk (0x1U << DSI_TCCR1_HSRD_TOCNT0_Pos) /*!< 0x00000001 */
7773 #define DSI_TCCR1_HSRD_TOCNT0 DSI_TCCR1_HSRD_TOCNT0_Msk
7774 #define DSI_TCCR1_HSRD_TOCNT1_Pos (1U)
7775 #define DSI_TCCR1_HSRD_TOCNT1_Msk (0x1U << DSI_TCCR1_HSRD_TOCNT1_Pos) /*!< 0x00000002 */
7776 #define DSI_TCCR1_HSRD_TOCNT1 DSI_TCCR1_HSRD_TOCNT1_Msk
7777 #define DSI_TCCR1_HSRD_TOCNT2_Pos (2U)
7778 #define DSI_TCCR1_HSRD_TOCNT2_Msk (0x1U << DSI_TCCR1_HSRD_TOCNT2_Pos) /*!< 0x00000004 */
7779 #define DSI_TCCR1_HSRD_TOCNT2 DSI_TCCR1_HSRD_TOCNT2_Msk
7780 #define DSI_TCCR1_HSRD_TOCNT3_Pos (3U)
7781 #define DSI_TCCR1_HSRD_TOCNT3_Msk (0x1U << DSI_TCCR1_HSRD_TOCNT3_Pos) /*!< 0x00000008 */
7782 #define DSI_TCCR1_HSRD_TOCNT3 DSI_TCCR1_HSRD_TOCNT3_Msk
7783 #define DSI_TCCR1_HSRD_TOCNT4_Pos (4U)
7784 #define DSI_TCCR1_HSRD_TOCNT4_Msk (0x1U << DSI_TCCR1_HSRD_TOCNT4_Pos) /*!< 0x00000010 */
7785 #define DSI_TCCR1_HSRD_TOCNT4 DSI_TCCR1_HSRD_TOCNT4_Msk
7786 #define DSI_TCCR1_HSRD_TOCNT5_Pos (5U)
7787 #define DSI_TCCR1_HSRD_TOCNT5_Msk (0x1U << DSI_TCCR1_HSRD_TOCNT5_Pos) /*!< 0x00000020 */
7788 #define DSI_TCCR1_HSRD_TOCNT5 DSI_TCCR1_HSRD_TOCNT5_Msk
7789 #define DSI_TCCR1_HSRD_TOCNT6_Pos (6U)
7790 #define DSI_TCCR1_HSRD_TOCNT6_Msk (0x1U << DSI_TCCR1_HSRD_TOCNT6_Pos) /*!< 0x00000040 */
7791 #define DSI_TCCR1_HSRD_TOCNT6 DSI_TCCR1_HSRD_TOCNT6_Msk
7792 #define DSI_TCCR1_HSRD_TOCNT7_Pos (7U)
7793 #define DSI_TCCR1_HSRD_TOCNT7_Msk (0x1U << DSI_TCCR1_HSRD_TOCNT7_Pos) /*!< 0x00000080 */
7794 #define DSI_TCCR1_HSRD_TOCNT7 DSI_TCCR1_HSRD_TOCNT7_Msk
7795 #define DSI_TCCR1_HSRD_TOCNT8_Pos (8U)
7796 #define DSI_TCCR1_HSRD_TOCNT8_Msk (0x1U << DSI_TCCR1_HSRD_TOCNT8_Pos) /*!< 0x00000100 */
7797 #define DSI_TCCR1_HSRD_TOCNT8 DSI_TCCR1_HSRD_TOCNT8_Msk
7798 #define DSI_TCCR1_HSRD_TOCNT9_Pos (9U)
7799 #define DSI_TCCR1_HSRD_TOCNT9_Msk (0x1U << DSI_TCCR1_HSRD_TOCNT9_Pos) /*!< 0x00000200 */
7800 #define DSI_TCCR1_HSRD_TOCNT9 DSI_TCCR1_HSRD_TOCNT9_Msk
7801 #define DSI_TCCR1_HSRD_TOCNT10_Pos (10U)
7802 #define DSI_TCCR1_HSRD_TOCNT10_Msk (0x1U << DSI_TCCR1_HSRD_TOCNT10_Pos) /*!< 0x00000400 */
7803 #define DSI_TCCR1_HSRD_TOCNT10 DSI_TCCR1_HSRD_TOCNT10_Msk
7804 #define DSI_TCCR1_HSRD_TOCNT11_Pos (11U)
7805 #define DSI_TCCR1_HSRD_TOCNT11_Msk (0x1U << DSI_TCCR1_HSRD_TOCNT11_Pos) /*!< 0x00000800 */
7806 #define DSI_TCCR1_HSRD_TOCNT11 DSI_TCCR1_HSRD_TOCNT11_Msk
7807 #define DSI_TCCR1_HSRD_TOCNT12_Pos (12U)
7808 #define DSI_TCCR1_HSRD_TOCNT12_Msk (0x1U << DSI_TCCR1_HSRD_TOCNT12_Pos) /*!< 0x00001000 */
7809 #define DSI_TCCR1_HSRD_TOCNT12 DSI_TCCR1_HSRD_TOCNT12_Msk
7810 #define DSI_TCCR1_HSRD_TOCNT13_Pos (13U)
7811 #define DSI_TCCR1_HSRD_TOCNT13_Msk (0x1U << DSI_TCCR1_HSRD_TOCNT13_Pos) /*!< 0x00002000 */
7812 #define DSI_TCCR1_HSRD_TOCNT13 DSI_TCCR1_HSRD_TOCNT13_Msk
7813 #define DSI_TCCR1_HSRD_TOCNT14_Pos (14U)
7814 #define DSI_TCCR1_HSRD_TOCNT14_Msk (0x1U << DSI_TCCR1_HSRD_TOCNT14_Pos) /*!< 0x00004000 */
7815 #define DSI_TCCR1_HSRD_TOCNT14 DSI_TCCR1_HSRD_TOCNT14_Msk
7816 #define DSI_TCCR1_HSRD_TOCNT15_Pos (15U)
7817 #define DSI_TCCR1_HSRD_TOCNT15_Msk (0x1U << DSI_TCCR1_HSRD_TOCNT15_Pos) /*!< 0x00008000 */
7818 #define DSI_TCCR1_HSRD_TOCNT15 DSI_TCCR1_HSRD_TOCNT15_Msk
7819
7820 /******************* Bit definition for DSI_TCCR2 register **************/
7821 #define DSI_TCCR2_LPRD_TOCNT_Pos (0U)
7822 #define DSI_TCCR2_LPRD_TOCNT_Msk (0xFFFFU << DSI_TCCR2_LPRD_TOCNT_Pos) /*!< 0x0000FFFF */
7823 #define DSI_TCCR2_LPRD_TOCNT DSI_TCCR2_LPRD_TOCNT_Msk /*!< Low-Power Read Timeout Counter */
7824 #define DSI_TCCR2_LPRD_TOCNT0_Pos (0U)
7825 #define DSI_TCCR2_LPRD_TOCNT0_Msk (0x1U << DSI_TCCR2_LPRD_TOCNT0_Pos) /*!< 0x00000001 */
7826 #define DSI_TCCR2_LPRD_TOCNT0 DSI_TCCR2_LPRD_TOCNT0_Msk
7827 #define DSI_TCCR2_LPRD_TOCNT1_Pos (1U)
7828 #define DSI_TCCR2_LPRD_TOCNT1_Msk (0x1U << DSI_TCCR2_LPRD_TOCNT1_Pos) /*!< 0x00000002 */
7829 #define DSI_TCCR2_LPRD_TOCNT1 DSI_TCCR2_LPRD_TOCNT1_Msk
7830 #define DSI_TCCR2_LPRD_TOCNT2_Pos (2U)
7831 #define DSI_TCCR2_LPRD_TOCNT2_Msk (0x1U << DSI_TCCR2_LPRD_TOCNT2_Pos) /*!< 0x00000004 */
7832 #define DSI_TCCR2_LPRD_TOCNT2 DSI_TCCR2_LPRD_TOCNT2_Msk
7833 #define DSI_TCCR2_LPRD_TOCNT3_Pos (3U)
7834 #define DSI_TCCR2_LPRD_TOCNT3_Msk (0x1U << DSI_TCCR2_LPRD_TOCNT3_Pos) /*!< 0x00000008 */
7835 #define DSI_TCCR2_LPRD_TOCNT3 DSI_TCCR2_LPRD_TOCNT3_Msk
7836 #define DSI_TCCR2_LPRD_TOCNT4_Pos (4U)
7837 #define DSI_TCCR2_LPRD_TOCNT4_Msk (0x1U << DSI_TCCR2_LPRD_TOCNT4_Pos) /*!< 0x00000010 */
7838 #define DSI_TCCR2_LPRD_TOCNT4 DSI_TCCR2_LPRD_TOCNT4_Msk
7839 #define DSI_TCCR2_LPRD_TOCNT5_Pos (5U)
7840 #define DSI_TCCR2_LPRD_TOCNT5_Msk (0x1U << DSI_TCCR2_LPRD_TOCNT5_Pos) /*!< 0x00000020 */
7841 #define DSI_TCCR2_LPRD_TOCNT5 DSI_TCCR2_LPRD_TOCNT5_Msk
7842 #define DSI_TCCR2_LPRD_TOCNT6_Pos (6U)
7843 #define DSI_TCCR2_LPRD_TOCNT6_Msk (0x1U << DSI_TCCR2_LPRD_TOCNT6_Pos) /*!< 0x00000040 */
7844 #define DSI_TCCR2_LPRD_TOCNT6 DSI_TCCR2_LPRD_TOCNT6_Msk
7845 #define DSI_TCCR2_LPRD_TOCNT7_Pos (7U)
7846 #define DSI_TCCR2_LPRD_TOCNT7_Msk (0x1U << DSI_TCCR2_LPRD_TOCNT7_Pos) /*!< 0x00000080 */
7847 #define DSI_TCCR2_LPRD_TOCNT7 DSI_TCCR2_LPRD_TOCNT7_Msk
7848 #define DSI_TCCR2_LPRD_TOCNT8_Pos (8U)
7849 #define DSI_TCCR2_LPRD_TOCNT8_Msk (0x1U << DSI_TCCR2_LPRD_TOCNT8_Pos) /*!< 0x00000100 */
7850 #define DSI_TCCR2_LPRD_TOCNT8 DSI_TCCR2_LPRD_TOCNT8_Msk
7851 #define DSI_TCCR2_LPRD_TOCNT9_Pos (9U)
7852 #define DSI_TCCR2_LPRD_TOCNT9_Msk (0x1U << DSI_TCCR2_LPRD_TOCNT9_Pos) /*!< 0x00000200 */
7853 #define DSI_TCCR2_LPRD_TOCNT9 DSI_TCCR2_LPRD_TOCNT9_Msk
7854 #define DSI_TCCR2_LPRD_TOCNT10_Pos (10U)
7855 #define DSI_TCCR2_LPRD_TOCNT10_Msk (0x1U << DSI_TCCR2_LPRD_TOCNT10_Pos) /*!< 0x00000400 */
7856 #define DSI_TCCR2_LPRD_TOCNT10 DSI_TCCR2_LPRD_TOCNT10_Msk
7857 #define DSI_TCCR2_LPRD_TOCNT11_Pos (11U)
7858 #define DSI_TCCR2_LPRD_TOCNT11_Msk (0x1U << DSI_TCCR2_LPRD_TOCNT11_Pos) /*!< 0x00000800 */
7859 #define DSI_TCCR2_LPRD_TOCNT11 DSI_TCCR2_LPRD_TOCNT11_Msk
7860 #define DSI_TCCR2_LPRD_TOCNT12_Pos (12U)
7861 #define DSI_TCCR2_LPRD_TOCNT12_Msk (0x1U << DSI_TCCR2_LPRD_TOCNT12_Pos) /*!< 0x00001000 */
7862 #define DSI_TCCR2_LPRD_TOCNT12 DSI_TCCR2_LPRD_TOCNT12_Msk
7863 #define DSI_TCCR2_LPRD_TOCNT13_Pos (13U)
7864 #define DSI_TCCR2_LPRD_TOCNT13_Msk (0x1U << DSI_TCCR2_LPRD_TOCNT13_Pos) /*!< 0x00002000 */
7865 #define DSI_TCCR2_LPRD_TOCNT13 DSI_TCCR2_LPRD_TOCNT13_Msk
7866 #define DSI_TCCR2_LPRD_TOCNT14_Pos (14U)
7867 #define DSI_TCCR2_LPRD_TOCNT14_Msk (0x1U << DSI_TCCR2_LPRD_TOCNT14_Pos) /*!< 0x00004000 */
7868 #define DSI_TCCR2_LPRD_TOCNT14 DSI_TCCR2_LPRD_TOCNT14_Msk
7869 #define DSI_TCCR2_LPRD_TOCNT15_Pos (15U)
7870 #define DSI_TCCR2_LPRD_TOCNT15_Msk (0x1U << DSI_TCCR2_LPRD_TOCNT15_Pos) /*!< 0x00008000 */
7871 #define DSI_TCCR2_LPRD_TOCNT15 DSI_TCCR2_LPRD_TOCNT15_Msk
7872
7873 /******************* Bit definition for DSI_TCCR3 register **************/
7874 #define DSI_TCCR3_HSWR_TOCNT_Pos (0U)
7875 #define DSI_TCCR3_HSWR_TOCNT_Msk (0xFFFFU << DSI_TCCR3_HSWR_TOCNT_Pos) /*!< 0x0000FFFF */
7876 #define DSI_TCCR3_HSWR_TOCNT DSI_TCCR3_HSWR_TOCNT_Msk /*!< High-Speed Write Timeout Counter */
7877 #define DSI_TCCR3_HSWR_TOCNT0_Pos (0U)
7878 #define DSI_TCCR3_HSWR_TOCNT0_Msk (0x1U << DSI_TCCR3_HSWR_TOCNT0_Pos) /*!< 0x00000001 */
7879 #define DSI_TCCR3_HSWR_TOCNT0 DSI_TCCR3_HSWR_TOCNT0_Msk
7880 #define DSI_TCCR3_HSWR_TOCNT1_Pos (1U)
7881 #define DSI_TCCR3_HSWR_TOCNT1_Msk (0x1U << DSI_TCCR3_HSWR_TOCNT1_Pos) /*!< 0x00000002 */
7882 #define DSI_TCCR3_HSWR_TOCNT1 DSI_TCCR3_HSWR_TOCNT1_Msk
7883 #define DSI_TCCR3_HSWR_TOCNT2_Pos (2U)
7884 #define DSI_TCCR3_HSWR_TOCNT2_Msk (0x1U << DSI_TCCR3_HSWR_TOCNT2_Pos) /*!< 0x00000004 */
7885 #define DSI_TCCR3_HSWR_TOCNT2 DSI_TCCR3_HSWR_TOCNT2_Msk
7886 #define DSI_TCCR3_HSWR_TOCNT3_Pos (3U)
7887 #define DSI_TCCR3_HSWR_TOCNT3_Msk (0x1U << DSI_TCCR3_HSWR_TOCNT3_Pos) /*!< 0x00000008 */
7888 #define DSI_TCCR3_HSWR_TOCNT3 DSI_TCCR3_HSWR_TOCNT3_Msk
7889 #define DSI_TCCR3_HSWR_TOCNT4_Pos (4U)
7890 #define DSI_TCCR3_HSWR_TOCNT4_Msk (0x1U << DSI_TCCR3_HSWR_TOCNT4_Pos) /*!< 0x00000010 */
7891 #define DSI_TCCR3_HSWR_TOCNT4 DSI_TCCR3_HSWR_TOCNT4_Msk
7892 #define DSI_TCCR3_HSWR_TOCNT5_Pos (5U)
7893 #define DSI_TCCR3_HSWR_TOCNT5_Msk (0x1U << DSI_TCCR3_HSWR_TOCNT5_Pos) /*!< 0x00000020 */
7894 #define DSI_TCCR3_HSWR_TOCNT5 DSI_TCCR3_HSWR_TOCNT5_Msk
7895 #define DSI_TCCR3_HSWR_TOCNT6_Pos (6U)
7896 #define DSI_TCCR3_HSWR_TOCNT6_Msk (0x1U << DSI_TCCR3_HSWR_TOCNT6_Pos) /*!< 0x00000040 */
7897 #define DSI_TCCR3_HSWR_TOCNT6 DSI_TCCR3_HSWR_TOCNT6_Msk
7898 #define DSI_TCCR3_HSWR_TOCNT7_Pos (7U)
7899 #define DSI_TCCR3_HSWR_TOCNT7_Msk (0x1U << DSI_TCCR3_HSWR_TOCNT7_Pos) /*!< 0x00000080 */
7900 #define DSI_TCCR3_HSWR_TOCNT7 DSI_TCCR3_HSWR_TOCNT7_Msk
7901 #define DSI_TCCR3_HSWR_TOCNT8_Pos (8U)
7902 #define DSI_TCCR3_HSWR_TOCNT8_Msk (0x1U << DSI_TCCR3_HSWR_TOCNT8_Pos) /*!< 0x00000100 */
7903 #define DSI_TCCR3_HSWR_TOCNT8 DSI_TCCR3_HSWR_TOCNT8_Msk
7904 #define DSI_TCCR3_HSWR_TOCNT9_Pos (9U)
7905 #define DSI_TCCR3_HSWR_TOCNT9_Msk (0x1U << DSI_TCCR3_HSWR_TOCNT9_Pos) /*!< 0x00000200 */
7906 #define DSI_TCCR3_HSWR_TOCNT9 DSI_TCCR3_HSWR_TOCNT9_Msk
7907 #define DSI_TCCR3_HSWR_TOCNT10_Pos (10U)
7908 #define DSI_TCCR3_HSWR_TOCNT10_Msk (0x1U << DSI_TCCR3_HSWR_TOCNT10_Pos) /*!< 0x00000400 */
7909 #define DSI_TCCR3_HSWR_TOCNT10 DSI_TCCR3_HSWR_TOCNT10_Msk
7910 #define DSI_TCCR3_HSWR_TOCNT11_Pos (11U)
7911 #define DSI_TCCR3_HSWR_TOCNT11_Msk (0x1U << DSI_TCCR3_HSWR_TOCNT11_Pos) /*!< 0x00000800 */
7912 #define DSI_TCCR3_HSWR_TOCNT11 DSI_TCCR3_HSWR_TOCNT11_Msk
7913 #define DSI_TCCR3_HSWR_TOCNT12_Pos (12U)
7914 #define DSI_TCCR3_HSWR_TOCNT12_Msk (0x1U << DSI_TCCR3_HSWR_TOCNT12_Pos) /*!< 0x00001000 */
7915 #define DSI_TCCR3_HSWR_TOCNT12 DSI_TCCR3_HSWR_TOCNT12_Msk
7916 #define DSI_TCCR3_HSWR_TOCNT13_Pos (13U)
7917 #define DSI_TCCR3_HSWR_TOCNT13_Msk (0x1U << DSI_TCCR3_HSWR_TOCNT13_Pos) /*!< 0x00002000 */
7918 #define DSI_TCCR3_HSWR_TOCNT13 DSI_TCCR3_HSWR_TOCNT13_Msk
7919 #define DSI_TCCR3_HSWR_TOCNT14_Pos (14U)
7920 #define DSI_TCCR3_HSWR_TOCNT14_Msk (0x1U << DSI_TCCR3_HSWR_TOCNT14_Pos) /*!< 0x00004000 */
7921 #define DSI_TCCR3_HSWR_TOCNT14 DSI_TCCR3_HSWR_TOCNT14_Msk
7922 #define DSI_TCCR3_HSWR_TOCNT15_Pos (15U)
7923 #define DSI_TCCR3_HSWR_TOCNT15_Msk (0x1U << DSI_TCCR3_HSWR_TOCNT15_Pos) /*!< 0x00008000 */
7924 #define DSI_TCCR3_HSWR_TOCNT15 DSI_TCCR3_HSWR_TOCNT15_Msk
7925
7926 #define DSI_TCCR3_PM_Pos (24U)
7927 #define DSI_TCCR3_PM_Msk (0x1U << DSI_TCCR3_PM_Pos) /*!< 0x01000000 */
7928 #define DSI_TCCR3_PM DSI_TCCR3_PM_Msk /*!< Presp Mode */
7929
7930 /******************* Bit definition for DSI_TCCR4 register **************/
7931 #define DSI_TCCR4_LPWR_TOCNT_Pos (0U)
7932 #define DSI_TCCR4_LPWR_TOCNT_Msk (0xFFFFU << DSI_TCCR4_LPWR_TOCNT_Pos) /*!< 0x0000FFFF */
7933 #define DSI_TCCR4_LPWR_TOCNT DSI_TCCR4_LPWR_TOCNT_Msk /*!< Low-Power Write Timeout Counter */
7934 #define DSI_TCCR4_LPWR_TOCNT0_Pos (0U)
7935 #define DSI_TCCR4_LPWR_TOCNT0_Msk (0x1U << DSI_TCCR4_LPWR_TOCNT0_Pos) /*!< 0x00000001 */
7936 #define DSI_TCCR4_LPWR_TOCNT0 DSI_TCCR4_LPWR_TOCNT0_Msk
7937 #define DSI_TCCR4_LPWR_TOCNT1_Pos (1U)
7938 #define DSI_TCCR4_LPWR_TOCNT1_Msk (0x1U << DSI_TCCR4_LPWR_TOCNT1_Pos) /*!< 0x00000002 */
7939 #define DSI_TCCR4_LPWR_TOCNT1 DSI_TCCR4_LPWR_TOCNT1_Msk
7940 #define DSI_TCCR4_LPWR_TOCNT2_Pos (2U)
7941 #define DSI_TCCR4_LPWR_TOCNT2_Msk (0x1U << DSI_TCCR4_LPWR_TOCNT2_Pos) /*!< 0x00000004 */
7942 #define DSI_TCCR4_LPWR_TOCNT2 DSI_TCCR4_LPWR_TOCNT2_Msk
7943 #define DSI_TCCR4_LPWR_TOCNT3_Pos (3U)
7944 #define DSI_TCCR4_LPWR_TOCNT3_Msk (0x1U << DSI_TCCR4_LPWR_TOCNT3_Pos) /*!< 0x00000008 */
7945 #define DSI_TCCR4_LPWR_TOCNT3 DSI_TCCR4_LPWR_TOCNT3_Msk
7946 #define DSI_TCCR4_LPWR_TOCNT4_Pos (4U)
7947 #define DSI_TCCR4_LPWR_TOCNT4_Msk (0x1U << DSI_TCCR4_LPWR_TOCNT4_Pos) /*!< 0x00000010 */
7948 #define DSI_TCCR4_LPWR_TOCNT4 DSI_TCCR4_LPWR_TOCNT4_Msk
7949 #define DSI_TCCR4_LPWR_TOCNT5_Pos (5U)
7950 #define DSI_TCCR4_LPWR_TOCNT5_Msk (0x1U << DSI_TCCR4_LPWR_TOCNT5_Pos) /*!< 0x00000020 */
7951 #define DSI_TCCR4_LPWR_TOCNT5 DSI_TCCR4_LPWR_TOCNT5_Msk
7952 #define DSI_TCCR4_LPWR_TOCNT6_Pos (6U)
7953 #define DSI_TCCR4_LPWR_TOCNT6_Msk (0x1U << DSI_TCCR4_LPWR_TOCNT6_Pos) /*!< 0x00000040 */
7954 #define DSI_TCCR4_LPWR_TOCNT6 DSI_TCCR4_LPWR_TOCNT6_Msk
7955 #define DSI_TCCR4_LPWR_TOCNT7_Pos (7U)
7956 #define DSI_TCCR4_LPWR_TOCNT7_Msk (0x1U << DSI_TCCR4_LPWR_TOCNT7_Pos) /*!< 0x00000080 */
7957 #define DSI_TCCR4_LPWR_TOCNT7 DSI_TCCR4_LPWR_TOCNT7_Msk
7958 #define DSI_TCCR4_LPWR_TOCNT8_Pos (8U)
7959 #define DSI_TCCR4_LPWR_TOCNT8_Msk (0x1U << DSI_TCCR4_LPWR_TOCNT8_Pos) /*!< 0x00000100 */
7960 #define DSI_TCCR4_LPWR_TOCNT8 DSI_TCCR4_LPWR_TOCNT8_Msk
7961 #define DSI_TCCR4_LPWR_TOCNT9_Pos (9U)
7962 #define DSI_TCCR4_LPWR_TOCNT9_Msk (0x1U << DSI_TCCR4_LPWR_TOCNT9_Pos) /*!< 0x00000200 */
7963 #define DSI_TCCR4_LPWR_TOCNT9 DSI_TCCR4_LPWR_TOCNT9_Msk
7964 #define DSI_TCCR4_LPWR_TOCNT10_Pos (10U)
7965 #define DSI_TCCR4_LPWR_TOCNT10_Msk (0x1U << DSI_TCCR4_LPWR_TOCNT10_Pos) /*!< 0x00000400 */
7966 #define DSI_TCCR4_LPWR_TOCNT10 DSI_TCCR4_LPWR_TOCNT10_Msk
7967 #define DSI_TCCR4_LPWR_TOCNT11_Pos (11U)
7968 #define DSI_TCCR4_LPWR_TOCNT11_Msk (0x1U << DSI_TCCR4_LPWR_TOCNT11_Pos) /*!< 0x00000800 */
7969 #define DSI_TCCR4_LPWR_TOCNT11 DSI_TCCR4_LPWR_TOCNT11_Msk
7970 #define DSI_TCCR4_LPWR_TOCNT12_Pos (12U)
7971 #define DSI_TCCR4_LPWR_TOCNT12_Msk (0x1U << DSI_TCCR4_LPWR_TOCNT12_Pos) /*!< 0x00001000 */
7972 #define DSI_TCCR4_LPWR_TOCNT12 DSI_TCCR4_LPWR_TOCNT12_Msk
7973 #define DSI_TCCR4_LPWR_TOCNT13_Pos (13U)
7974 #define DSI_TCCR4_LPWR_TOCNT13_Msk (0x1U << DSI_TCCR4_LPWR_TOCNT13_Pos) /*!< 0x00002000 */
7975 #define DSI_TCCR4_LPWR_TOCNT13 DSI_TCCR4_LPWR_TOCNT13_Msk
7976 #define DSI_TCCR4_LPWR_TOCNT14_Pos (14U)
7977 #define DSI_TCCR4_LPWR_TOCNT14_Msk (0x1U << DSI_TCCR4_LPWR_TOCNT14_Pos) /*!< 0x00004000 */
7978 #define DSI_TCCR4_LPWR_TOCNT14 DSI_TCCR4_LPWR_TOCNT14_Msk
7979 #define DSI_TCCR4_LPWR_TOCNT15_Pos (15U)
7980 #define DSI_TCCR4_LPWR_TOCNT15_Msk (0x1U << DSI_TCCR4_LPWR_TOCNT15_Pos) /*!< 0x00008000 */
7981 #define DSI_TCCR4_LPWR_TOCNT15 DSI_TCCR4_LPWR_TOCNT15_Msk
7982
7983 /******************* Bit definition for DSI_TCCR5 register **************/
7984 #define DSI_TCCR5_BTA_TOCNT_Pos (0U)
7985 #define DSI_TCCR5_BTA_TOCNT_Msk (0xFFFFU << DSI_TCCR5_BTA_TOCNT_Pos) /*!< 0x0000FFFF */
7986 #define DSI_TCCR5_BTA_TOCNT DSI_TCCR5_BTA_TOCNT_Msk /*!< Bus-Turn-Around Timeout Counter */
7987 #define DSI_TCCR5_BTA_TOCNT0_Pos (0U)
7988 #define DSI_TCCR5_BTA_TOCNT0_Msk (0x1U << DSI_TCCR5_BTA_TOCNT0_Pos) /*!< 0x00000001 */
7989 #define DSI_TCCR5_BTA_TOCNT0 DSI_TCCR5_BTA_TOCNT0_Msk
7990 #define DSI_TCCR5_BTA_TOCNT1_Pos (1U)
7991 #define DSI_TCCR5_BTA_TOCNT1_Msk (0x1U << DSI_TCCR5_BTA_TOCNT1_Pos) /*!< 0x00000002 */
7992 #define DSI_TCCR5_BTA_TOCNT1 DSI_TCCR5_BTA_TOCNT1_Msk
7993 #define DSI_TCCR5_BTA_TOCNT2_Pos (2U)
7994 #define DSI_TCCR5_BTA_TOCNT2_Msk (0x1U << DSI_TCCR5_BTA_TOCNT2_Pos) /*!< 0x00000004 */
7995 #define DSI_TCCR5_BTA_TOCNT2 DSI_TCCR5_BTA_TOCNT2_Msk
7996 #define DSI_TCCR5_BTA_TOCNT3_Pos (3U)
7997 #define DSI_TCCR5_BTA_TOCNT3_Msk (0x1U << DSI_TCCR5_BTA_TOCNT3_Pos) /*!< 0x00000008 */
7998 #define DSI_TCCR5_BTA_TOCNT3 DSI_TCCR5_BTA_TOCNT3_Msk
7999 #define DSI_TCCR5_BTA_TOCNT4_Pos (4U)
8000 #define DSI_TCCR5_BTA_TOCNT4_Msk (0x1U << DSI_TCCR5_BTA_TOCNT4_Pos) /*!< 0x00000010 */
8001 #define DSI_TCCR5_BTA_TOCNT4 DSI_TCCR5_BTA_TOCNT4_Msk
8002 #define DSI_TCCR5_BTA_TOCNT5_Pos (5U)
8003 #define DSI_TCCR5_BTA_TOCNT5_Msk (0x1U << DSI_TCCR5_BTA_TOCNT5_Pos) /*!< 0x00000020 */
8004 #define DSI_TCCR5_BTA_TOCNT5 DSI_TCCR5_BTA_TOCNT5_Msk
8005 #define DSI_TCCR5_BTA_TOCNT6_Pos (6U)
8006 #define DSI_TCCR5_BTA_TOCNT6_Msk (0x1U << DSI_TCCR5_BTA_TOCNT6_Pos) /*!< 0x00000040 */
8007 #define DSI_TCCR5_BTA_TOCNT6 DSI_TCCR5_BTA_TOCNT6_Msk
8008 #define DSI_TCCR5_BTA_TOCNT7_Pos (7U)
8009 #define DSI_TCCR5_BTA_TOCNT7_Msk (0x1U << DSI_TCCR5_BTA_TOCNT7_Pos) /*!< 0x00000080 */
8010 #define DSI_TCCR5_BTA_TOCNT7 DSI_TCCR5_BTA_TOCNT7_Msk
8011 #define DSI_TCCR5_BTA_TOCNT8_Pos (8U)
8012 #define DSI_TCCR5_BTA_TOCNT8_Msk (0x1U << DSI_TCCR5_BTA_TOCNT8_Pos) /*!< 0x00000100 */
8013 #define DSI_TCCR5_BTA_TOCNT8 DSI_TCCR5_BTA_TOCNT8_Msk
8014 #define DSI_TCCR5_BTA_TOCNT9_Pos (9U)
8015 #define DSI_TCCR5_BTA_TOCNT9_Msk (0x1U << DSI_TCCR5_BTA_TOCNT9_Pos) /*!< 0x00000200 */
8016 #define DSI_TCCR5_BTA_TOCNT9 DSI_TCCR5_BTA_TOCNT9_Msk
8017 #define DSI_TCCR5_BTA_TOCNT10_Pos (10U)
8018 #define DSI_TCCR5_BTA_TOCNT10_Msk (0x1U << DSI_TCCR5_BTA_TOCNT10_Pos) /*!< 0x00000400 */
8019 #define DSI_TCCR5_BTA_TOCNT10 DSI_TCCR5_BTA_TOCNT10_Msk
8020 #define DSI_TCCR5_BTA_TOCNT11_Pos (11U)
8021 #define DSI_TCCR5_BTA_TOCNT11_Msk (0x1U << DSI_TCCR5_BTA_TOCNT11_Pos) /*!< 0x00000800 */
8022 #define DSI_TCCR5_BTA_TOCNT11 DSI_TCCR5_BTA_TOCNT11_Msk
8023 #define DSI_TCCR5_BTA_TOCNT12_Pos (12U)
8024 #define DSI_TCCR5_BTA_TOCNT12_Msk (0x1U << DSI_TCCR5_BTA_TOCNT12_Pos) /*!< 0x00001000 */
8025 #define DSI_TCCR5_BTA_TOCNT12 DSI_TCCR5_BTA_TOCNT12_Msk
8026 #define DSI_TCCR5_BTA_TOCNT13_Pos (13U)
8027 #define DSI_TCCR5_BTA_TOCNT13_Msk (0x1U << DSI_TCCR5_BTA_TOCNT13_Pos) /*!< 0x00002000 */
8028 #define DSI_TCCR5_BTA_TOCNT13 DSI_TCCR5_BTA_TOCNT13_Msk
8029 #define DSI_TCCR5_BTA_TOCNT14_Pos (14U)
8030 #define DSI_TCCR5_BTA_TOCNT14_Msk (0x1U << DSI_TCCR5_BTA_TOCNT14_Pos) /*!< 0x00004000 */
8031 #define DSI_TCCR5_BTA_TOCNT14 DSI_TCCR5_BTA_TOCNT14_Msk
8032 #define DSI_TCCR5_BTA_TOCNT15_Pos (15U)
8033 #define DSI_TCCR5_BTA_TOCNT15_Msk (0x1U << DSI_TCCR5_BTA_TOCNT15_Pos) /*!< 0x00008000 */
8034 #define DSI_TCCR5_BTA_TOCNT15 DSI_TCCR5_BTA_TOCNT15_Msk
8035
8036 /******************* Bit definition for DSI_TDCR register ***************/
8037 #define DSI_TDCR_3DM 0x00000003U /*!< 3D Mode */
8038 #define DSI_TDCR_3DM0 0x00000001U
8039 #define DSI_TDCR_3DM1 0x00000002U
8040
8041 #define DSI_TDCR_3DF 0x0000000CU /*!< 3D Format */
8042 #define DSI_TDCR_3DF0 0x00000004U
8043 #define DSI_TDCR_3DF1 0x00000008U
8044
8045 #define DSI_TDCR_SVS_Pos (4U)
8046 #define DSI_TDCR_SVS_Msk (0x1U << DSI_TDCR_SVS_Pos) /*!< 0x00000010 */
8047 #define DSI_TDCR_SVS DSI_TDCR_SVS_Msk /*!< Second VSYNC */
8048 #define DSI_TDCR_RF_Pos (5U)
8049 #define DSI_TDCR_RF_Msk (0x1U << DSI_TDCR_RF_Pos) /*!< 0x00000020 */
8050 #define DSI_TDCR_RF DSI_TDCR_RF_Msk /*!< Right First */
8051 #define DSI_TDCR_S3DC_Pos (16U)
8052 #define DSI_TDCR_S3DC_Msk (0x1U << DSI_TDCR_S3DC_Pos) /*!< 0x00010000 */
8053 #define DSI_TDCR_S3DC DSI_TDCR_S3DC_Msk /*!< Send 3D Control */
8054
8055 /******************* Bit definition for DSI_CLCR register ***************/
8056 #define DSI_CLCR_DPCC_Pos (0U)
8057 #define DSI_CLCR_DPCC_Msk (0x1U << DSI_CLCR_DPCC_Pos) /*!< 0x00000001 */
8058 #define DSI_CLCR_DPCC DSI_CLCR_DPCC_Msk /*!< D-PHY Clock Control */
8059 #define DSI_CLCR_ACR_Pos (1U)
8060 #define DSI_CLCR_ACR_Msk (0x1U << DSI_CLCR_ACR_Pos) /*!< 0x00000002 */
8061 #define DSI_CLCR_ACR DSI_CLCR_ACR_Msk /*!< Automatic Clocklane Control */
8062
8063 /******************* Bit definition for DSI_CLTCR register **************/
8064 #define DSI_CLTCR_LP2HS_TIME_Pos (0U)
8065 #define DSI_CLTCR_LP2HS_TIME_Msk (0x3FFU << DSI_CLTCR_LP2HS_TIME_Pos) /*!< 0x000003FF */
8066 #define DSI_CLTCR_LP2HS_TIME DSI_CLTCR_LP2HS_TIME_Msk /*!< Low-Power to High-Speed Time */
8067 #define DSI_CLTCR_LP2HS_TIME0_Pos (0U)
8068 #define DSI_CLTCR_LP2HS_TIME0_Msk (0x1U << DSI_CLTCR_LP2HS_TIME0_Pos) /*!< 0x00000001 */
8069 #define DSI_CLTCR_LP2HS_TIME0 DSI_CLTCR_LP2HS_TIME0_Msk
8070 #define DSI_CLTCR_LP2HS_TIME1_Pos (1U)
8071 #define DSI_CLTCR_LP2HS_TIME1_Msk (0x1U << DSI_CLTCR_LP2HS_TIME1_Pos) /*!< 0x00000002 */
8072 #define DSI_CLTCR_LP2HS_TIME1 DSI_CLTCR_LP2HS_TIME1_Msk
8073 #define DSI_CLTCR_LP2HS_TIME2_Pos (2U)
8074 #define DSI_CLTCR_LP2HS_TIME2_Msk (0x1U << DSI_CLTCR_LP2HS_TIME2_Pos) /*!< 0x00000004 */
8075 #define DSI_CLTCR_LP2HS_TIME2 DSI_CLTCR_LP2HS_TIME2_Msk
8076 #define DSI_CLTCR_LP2HS_TIME3_Pos (3U)
8077 #define DSI_CLTCR_LP2HS_TIME3_Msk (0x1U << DSI_CLTCR_LP2HS_TIME3_Pos) /*!< 0x00000008 */
8078 #define DSI_CLTCR_LP2HS_TIME3 DSI_CLTCR_LP2HS_TIME3_Msk
8079 #define DSI_CLTCR_LP2HS_TIME4_Pos (4U)
8080 #define DSI_CLTCR_LP2HS_TIME4_Msk (0x1U << DSI_CLTCR_LP2HS_TIME4_Pos) /*!< 0x00000010 */
8081 #define DSI_CLTCR_LP2HS_TIME4 DSI_CLTCR_LP2HS_TIME4_Msk
8082 #define DSI_CLTCR_LP2HS_TIME5_Pos (5U)
8083 #define DSI_CLTCR_LP2HS_TIME5_Msk (0x1U << DSI_CLTCR_LP2HS_TIME5_Pos) /*!< 0x00000020 */
8084 #define DSI_CLTCR_LP2HS_TIME5 DSI_CLTCR_LP2HS_TIME5_Msk
8085 #define DSI_CLTCR_LP2HS_TIME6_Pos (6U)
8086 #define DSI_CLTCR_LP2HS_TIME6_Msk (0x1U << DSI_CLTCR_LP2HS_TIME6_Pos) /*!< 0x00000040 */
8087 #define DSI_CLTCR_LP2HS_TIME6 DSI_CLTCR_LP2HS_TIME6_Msk
8088 #define DSI_CLTCR_LP2HS_TIME7_Pos (7U)
8089 #define DSI_CLTCR_LP2HS_TIME7_Msk (0x1U << DSI_CLTCR_LP2HS_TIME7_Pos) /*!< 0x00000080 */
8090 #define DSI_CLTCR_LP2HS_TIME7 DSI_CLTCR_LP2HS_TIME7_Msk
8091 #define DSI_CLTCR_LP2HS_TIME8_Pos (8U)
8092 #define DSI_CLTCR_LP2HS_TIME8_Msk (0x1U << DSI_CLTCR_LP2HS_TIME8_Pos) /*!< 0x00000100 */
8093 #define DSI_CLTCR_LP2HS_TIME8 DSI_CLTCR_LP2HS_TIME8_Msk
8094 #define DSI_CLTCR_LP2HS_TIME9_Pos (9U)
8095 #define DSI_CLTCR_LP2HS_TIME9_Msk (0x1U << DSI_CLTCR_LP2HS_TIME9_Pos) /*!< 0x00000200 */
8096 #define DSI_CLTCR_LP2HS_TIME9 DSI_CLTCR_LP2HS_TIME9_Msk
8097
8098 #define DSI_CLTCR_HS2LP_TIME_Pos (16U)
8099 #define DSI_CLTCR_HS2LP_TIME_Msk (0x3FFU << DSI_CLTCR_HS2LP_TIME_Pos) /*!< 0x03FF0000 */
8100 #define DSI_CLTCR_HS2LP_TIME DSI_CLTCR_HS2LP_TIME_Msk /*!< High-Speed to Low-Power Time */
8101 #define DSI_CLTCR_HS2LP_TIME0_Pos (16U)
8102 #define DSI_CLTCR_HS2LP_TIME0_Msk (0x1U << DSI_CLTCR_HS2LP_TIME0_Pos) /*!< 0x00010000 */
8103 #define DSI_CLTCR_HS2LP_TIME0 DSI_CLTCR_HS2LP_TIME0_Msk
8104 #define DSI_CLTCR_HS2LP_TIME1_Pos (17U)
8105 #define DSI_CLTCR_HS2LP_TIME1_Msk (0x1U << DSI_CLTCR_HS2LP_TIME1_Pos) /*!< 0x00020000 */
8106 #define DSI_CLTCR_HS2LP_TIME1 DSI_CLTCR_HS2LP_TIME1_Msk
8107 #define DSI_CLTCR_HS2LP_TIME2_Pos (18U)
8108 #define DSI_CLTCR_HS2LP_TIME2_Msk (0x1U << DSI_CLTCR_HS2LP_TIME2_Pos) /*!< 0x00040000 */
8109 #define DSI_CLTCR_HS2LP_TIME2 DSI_CLTCR_HS2LP_TIME2_Msk
8110 #define DSI_CLTCR_HS2LP_TIME3_Pos (19U)
8111 #define DSI_CLTCR_HS2LP_TIME3_Msk (0x1U << DSI_CLTCR_HS2LP_TIME3_Pos) /*!< 0x00080000 */
8112 #define DSI_CLTCR_HS2LP_TIME3 DSI_CLTCR_HS2LP_TIME3_Msk
8113 #define DSI_CLTCR_HS2LP_TIME4_Pos (20U)
8114 #define DSI_CLTCR_HS2LP_TIME4_Msk (0x1U << DSI_CLTCR_HS2LP_TIME4_Pos) /*!< 0x00100000 */
8115 #define DSI_CLTCR_HS2LP_TIME4 DSI_CLTCR_HS2LP_TIME4_Msk
8116 #define DSI_CLTCR_HS2LP_TIME5_Pos (21U)
8117 #define DSI_CLTCR_HS2LP_TIME5_Msk (0x1U << DSI_CLTCR_HS2LP_TIME5_Pos) /*!< 0x00200000 */
8118 #define DSI_CLTCR_HS2LP_TIME5 DSI_CLTCR_HS2LP_TIME5_Msk
8119 #define DSI_CLTCR_HS2LP_TIME6_Pos (22U)
8120 #define DSI_CLTCR_HS2LP_TIME6_Msk (0x1U << DSI_CLTCR_HS2LP_TIME6_Pos) /*!< 0x00400000 */
8121 #define DSI_CLTCR_HS2LP_TIME6 DSI_CLTCR_HS2LP_TIME6_Msk
8122 #define DSI_CLTCR_HS2LP_TIME7_Pos (23U)
8123 #define DSI_CLTCR_HS2LP_TIME7_Msk (0x1U << DSI_CLTCR_HS2LP_TIME7_Pos) /*!< 0x00800000 */
8124 #define DSI_CLTCR_HS2LP_TIME7 DSI_CLTCR_HS2LP_TIME7_Msk
8125 #define DSI_CLTCR_HS2LP_TIME8_Pos (24U)
8126 #define DSI_CLTCR_HS2LP_TIME8_Msk (0x1U << DSI_CLTCR_HS2LP_TIME8_Pos) /*!< 0x01000000 */
8127 #define DSI_CLTCR_HS2LP_TIME8 DSI_CLTCR_HS2LP_TIME8_Msk
8128 #define DSI_CLTCR_HS2LP_TIME9_Pos (25U)
8129 #define DSI_CLTCR_HS2LP_TIME9_Msk (0x1U << DSI_CLTCR_HS2LP_TIME9_Pos) /*!< 0x02000000 */
8130 #define DSI_CLTCR_HS2LP_TIME9 DSI_CLTCR_HS2LP_TIME9_Msk
8131
8132 /******************* Bit definition for DSI_DLTCR register **************/
8133 #define DSI_DLTCR_MRD_TIME_Pos (0U)
8134 #define DSI_DLTCR_MRD_TIME_Msk (0x7FFFU << DSI_DLTCR_MRD_TIME_Pos) /*!< 0x00007FFF */
8135 #define DSI_DLTCR_MRD_TIME DSI_DLTCR_MRD_TIME_Msk /*!< Maximum Read Time */
8136 #define DSI_DLTCR_MRD_TIME0_Pos (0U)
8137 #define DSI_DLTCR_MRD_TIME0_Msk (0x1U << DSI_DLTCR_MRD_TIME0_Pos) /*!< 0x00000001 */
8138 #define DSI_DLTCR_MRD_TIME0 DSI_DLTCR_MRD_TIME0_Msk
8139 #define DSI_DLTCR_MRD_TIME1_Pos (1U)
8140 #define DSI_DLTCR_MRD_TIME1_Msk (0x1U << DSI_DLTCR_MRD_TIME1_Pos) /*!< 0x00000002 */
8141 #define DSI_DLTCR_MRD_TIME1 DSI_DLTCR_MRD_TIME1_Msk
8142 #define DSI_DLTCR_MRD_TIME2_Pos (2U)
8143 #define DSI_DLTCR_MRD_TIME2_Msk (0x1U << DSI_DLTCR_MRD_TIME2_Pos) /*!< 0x00000004 */
8144 #define DSI_DLTCR_MRD_TIME2 DSI_DLTCR_MRD_TIME2_Msk
8145 #define DSI_DLTCR_MRD_TIME3_Pos (3U)
8146 #define DSI_DLTCR_MRD_TIME3_Msk (0x1U << DSI_DLTCR_MRD_TIME3_Pos) /*!< 0x00000008 */
8147 #define DSI_DLTCR_MRD_TIME3 DSI_DLTCR_MRD_TIME3_Msk
8148 #define DSI_DLTCR_MRD_TIME4_Pos (4U)
8149 #define DSI_DLTCR_MRD_TIME4_Msk (0x1U << DSI_DLTCR_MRD_TIME4_Pos) /*!< 0x00000010 */
8150 #define DSI_DLTCR_MRD_TIME4 DSI_DLTCR_MRD_TIME4_Msk
8151 #define DSI_DLTCR_MRD_TIME5_Pos (5U)
8152 #define DSI_DLTCR_MRD_TIME5_Msk (0x1U << DSI_DLTCR_MRD_TIME5_Pos) /*!< 0x00000020 */
8153 #define DSI_DLTCR_MRD_TIME5 DSI_DLTCR_MRD_TIME5_Msk
8154 #define DSI_DLTCR_MRD_TIME6_Pos (6U)
8155 #define DSI_DLTCR_MRD_TIME6_Msk (0x1U << DSI_DLTCR_MRD_TIME6_Pos) /*!< 0x00000040 */
8156 #define DSI_DLTCR_MRD_TIME6 DSI_DLTCR_MRD_TIME6_Msk
8157 #define DSI_DLTCR_MRD_TIME7_Pos (7U)
8158 #define DSI_DLTCR_MRD_TIME7_Msk (0x1U << DSI_DLTCR_MRD_TIME7_Pos) /*!< 0x00000080 */
8159 #define DSI_DLTCR_MRD_TIME7 DSI_DLTCR_MRD_TIME7_Msk
8160 #define DSI_DLTCR_MRD_TIME8_Pos (8U)
8161 #define DSI_DLTCR_MRD_TIME8_Msk (0x1U << DSI_DLTCR_MRD_TIME8_Pos) /*!< 0x00000100 */
8162 #define DSI_DLTCR_MRD_TIME8 DSI_DLTCR_MRD_TIME8_Msk
8163 #define DSI_DLTCR_MRD_TIME9_Pos (9U)
8164 #define DSI_DLTCR_MRD_TIME9_Msk (0x1U << DSI_DLTCR_MRD_TIME9_Pos) /*!< 0x00000200 */
8165 #define DSI_DLTCR_MRD_TIME9 DSI_DLTCR_MRD_TIME9_Msk
8166 #define DSI_DLTCR_MRD_TIME10_Pos (10U)
8167 #define DSI_DLTCR_MRD_TIME10_Msk (0x1U << DSI_DLTCR_MRD_TIME10_Pos) /*!< 0x00000400 */
8168 #define DSI_DLTCR_MRD_TIME10 DSI_DLTCR_MRD_TIME10_Msk
8169 #define DSI_DLTCR_MRD_TIME11_Pos (11U)
8170 #define DSI_DLTCR_MRD_TIME11_Msk (0x1U << DSI_DLTCR_MRD_TIME11_Pos) /*!< 0x00000800 */
8171 #define DSI_DLTCR_MRD_TIME11 DSI_DLTCR_MRD_TIME11_Msk
8172 #define DSI_DLTCR_MRD_TIME12_Pos (12U)
8173 #define DSI_DLTCR_MRD_TIME12_Msk (0x1U << DSI_DLTCR_MRD_TIME12_Pos) /*!< 0x00001000 */
8174 #define DSI_DLTCR_MRD_TIME12 DSI_DLTCR_MRD_TIME12_Msk
8175 #define DSI_DLTCR_MRD_TIME13_Pos (13U)
8176 #define DSI_DLTCR_MRD_TIME13_Msk (0x1U << DSI_DLTCR_MRD_TIME13_Pos) /*!< 0x00002000 */
8177 #define DSI_DLTCR_MRD_TIME13 DSI_DLTCR_MRD_TIME13_Msk
8178 #define DSI_DLTCR_MRD_TIME14_Pos (14U)
8179 #define DSI_DLTCR_MRD_TIME14_Msk (0x1U << DSI_DLTCR_MRD_TIME14_Pos) /*!< 0x00004000 */
8180 #define DSI_DLTCR_MRD_TIME14 DSI_DLTCR_MRD_TIME14_Msk
8181
8182 #define DSI_DLTCR_LP2HS_TIME_Pos (16U)
8183 #define DSI_DLTCR_LP2HS_TIME_Msk (0xFFU << DSI_DLTCR_LP2HS_TIME_Pos) /*!< 0x00FF0000 */
8184 #define DSI_DLTCR_LP2HS_TIME DSI_DLTCR_LP2HS_TIME_Msk /*!< Low-Power To High-Speed Time */
8185 #define DSI_DLTCR_LP2HS_TIME0_Pos (16U)
8186 #define DSI_DLTCR_LP2HS_TIME0_Msk (0x1U << DSI_DLTCR_LP2HS_TIME0_Pos) /*!< 0x00010000 */
8187 #define DSI_DLTCR_LP2HS_TIME0 DSI_DLTCR_LP2HS_TIME0_Msk
8188 #define DSI_DLTCR_LP2HS_TIME1_Pos (17U)
8189 #define DSI_DLTCR_LP2HS_TIME1_Msk (0x1U << DSI_DLTCR_LP2HS_TIME1_Pos) /*!< 0x00020000 */
8190 #define DSI_DLTCR_LP2HS_TIME1 DSI_DLTCR_LP2HS_TIME1_Msk
8191 #define DSI_DLTCR_LP2HS_TIME2_Pos (18U)
8192 #define DSI_DLTCR_LP2HS_TIME2_Msk (0x1U << DSI_DLTCR_LP2HS_TIME2_Pos) /*!< 0x00040000 */
8193 #define DSI_DLTCR_LP2HS_TIME2 DSI_DLTCR_LP2HS_TIME2_Msk
8194 #define DSI_DLTCR_LP2HS_TIME3_Pos (19U)
8195 #define DSI_DLTCR_LP2HS_TIME3_Msk (0x1U << DSI_DLTCR_LP2HS_TIME3_Pos) /*!< 0x00080000 */
8196 #define DSI_DLTCR_LP2HS_TIME3 DSI_DLTCR_LP2HS_TIME3_Msk
8197 #define DSI_DLTCR_LP2HS_TIME4_Pos (20U)
8198 #define DSI_DLTCR_LP2HS_TIME4_Msk (0x1U << DSI_DLTCR_LP2HS_TIME4_Pos) /*!< 0x00100000 */
8199 #define DSI_DLTCR_LP2HS_TIME4 DSI_DLTCR_LP2HS_TIME4_Msk
8200 #define DSI_DLTCR_LP2HS_TIME5_Pos (21U)
8201 #define DSI_DLTCR_LP2HS_TIME5_Msk (0x1U << DSI_DLTCR_LP2HS_TIME5_Pos) /*!< 0x00200000 */
8202 #define DSI_DLTCR_LP2HS_TIME5 DSI_DLTCR_LP2HS_TIME5_Msk
8203 #define DSI_DLTCR_LP2HS_TIME6_Pos (22U)
8204 #define DSI_DLTCR_LP2HS_TIME6_Msk (0x1U << DSI_DLTCR_LP2HS_TIME6_Pos) /*!< 0x00400000 */
8205 #define DSI_DLTCR_LP2HS_TIME6 DSI_DLTCR_LP2HS_TIME6_Msk
8206 #define DSI_DLTCR_LP2HS_TIME7_Pos (23U)
8207 #define DSI_DLTCR_LP2HS_TIME7_Msk (0x1U << DSI_DLTCR_LP2HS_TIME7_Pos) /*!< 0x00800000 */
8208 #define DSI_DLTCR_LP2HS_TIME7 DSI_DLTCR_LP2HS_TIME7_Msk
8209
8210 #define DSI_DLTCR_HS2LP_TIME_Pos (24U)
8211 #define DSI_DLTCR_HS2LP_TIME_Msk (0xFFU << DSI_DLTCR_HS2LP_TIME_Pos) /*!< 0xFF000000 */
8212 #define DSI_DLTCR_HS2LP_TIME DSI_DLTCR_HS2LP_TIME_Msk /*!< High-Speed To Low-Power Time */
8213 #define DSI_DLTCR_HS2LP_TIME0_Pos (24U)
8214 #define DSI_DLTCR_HS2LP_TIME0_Msk (0x1U << DSI_DLTCR_HS2LP_TIME0_Pos) /*!< 0x01000000 */
8215 #define DSI_DLTCR_HS2LP_TIME0 DSI_DLTCR_HS2LP_TIME0_Msk
8216 #define DSI_DLTCR_HS2LP_TIME1_Pos (25U)
8217 #define DSI_DLTCR_HS2LP_TIME1_Msk (0x1U << DSI_DLTCR_HS2LP_TIME1_Pos) /*!< 0x02000000 */
8218 #define DSI_DLTCR_HS2LP_TIME1 DSI_DLTCR_HS2LP_TIME1_Msk
8219 #define DSI_DLTCR_HS2LP_TIME2_Pos (26U)
8220 #define DSI_DLTCR_HS2LP_TIME2_Msk (0x1U << DSI_DLTCR_HS2LP_TIME2_Pos) /*!< 0x04000000 */
8221 #define DSI_DLTCR_HS2LP_TIME2 DSI_DLTCR_HS2LP_TIME2_Msk
8222 #define DSI_DLTCR_HS2LP_TIME3_Pos (27U)
8223 #define DSI_DLTCR_HS2LP_TIME3_Msk (0x1U << DSI_DLTCR_HS2LP_TIME3_Pos) /*!< 0x08000000 */
8224 #define DSI_DLTCR_HS2LP_TIME3 DSI_DLTCR_HS2LP_TIME3_Msk
8225 #define DSI_DLTCR_HS2LP_TIME4_Pos (28U)
8226 #define DSI_DLTCR_HS2LP_TIME4_Msk (0x1U << DSI_DLTCR_HS2LP_TIME4_Pos) /*!< 0x10000000 */
8227 #define DSI_DLTCR_HS2LP_TIME4 DSI_DLTCR_HS2LP_TIME4_Msk
8228 #define DSI_DLTCR_HS2LP_TIME5_Pos (29U)
8229 #define DSI_DLTCR_HS2LP_TIME5_Msk (0x1U << DSI_DLTCR_HS2LP_TIME5_Pos) /*!< 0x20000000 */
8230 #define DSI_DLTCR_HS2LP_TIME5 DSI_DLTCR_HS2LP_TIME5_Msk
8231 #define DSI_DLTCR_HS2LP_TIME6_Pos (30U)
8232 #define DSI_DLTCR_HS2LP_TIME6_Msk (0x1U << DSI_DLTCR_HS2LP_TIME6_Pos) /*!< 0x40000000 */
8233 #define DSI_DLTCR_HS2LP_TIME6 DSI_DLTCR_HS2LP_TIME6_Msk
8234 #define DSI_DLTCR_HS2LP_TIME7_Pos (31U)
8235 #define DSI_DLTCR_HS2LP_TIME7_Msk (0x1U << DSI_DLTCR_HS2LP_TIME7_Pos) /*!< 0x80000000 */
8236 #define DSI_DLTCR_HS2LP_TIME7 DSI_DLTCR_HS2LP_TIME7_Msk
8237
8238 /******************* Bit definition for DSI_PCTLR register **************/
8239 #define DSI_PCTLR_DEN_Pos (1U)
8240 #define DSI_PCTLR_DEN_Msk (0x1U << DSI_PCTLR_DEN_Pos) /*!< 0x00000002 */
8241 #define DSI_PCTLR_DEN DSI_PCTLR_DEN_Msk /*!< Digital Enable */
8242 #define DSI_PCTLR_CKE_Pos (2U)
8243 #define DSI_PCTLR_CKE_Msk (0x1U << DSI_PCTLR_CKE_Pos) /*!< 0x00000004 */
8244 #define DSI_PCTLR_CKE DSI_PCTLR_CKE_Msk /*!< Clock Enable */
8245
8246 /******************* Bit definition for DSI_PCONFR register *************/
8247 #define DSI_PCONFR_NL_Pos (0U)
8248 #define DSI_PCONFR_NL_Msk (0x3U << DSI_PCONFR_NL_Pos) /*!< 0x00000003 */
8249 #define DSI_PCONFR_NL DSI_PCONFR_NL_Msk /*!< Number of Lanes */
8250 #define DSI_PCONFR_NL0_Pos (0U)
8251 #define DSI_PCONFR_NL0_Msk (0x1U << DSI_PCONFR_NL0_Pos) /*!< 0x00000001 */
8252 #define DSI_PCONFR_NL0 DSI_PCONFR_NL0_Msk
8253 #define DSI_PCONFR_NL1_Pos (1U)
8254 #define DSI_PCONFR_NL1_Msk (0x1U << DSI_PCONFR_NL1_Pos) /*!< 0x00000002 */
8255 #define DSI_PCONFR_NL1 DSI_PCONFR_NL1_Msk
8256
8257 #define DSI_PCONFR_SW_TIME_Pos (8U)
8258 #define DSI_PCONFR_SW_TIME_Msk (0xFFU << DSI_PCONFR_SW_TIME_Pos) /*!< 0x0000FF00 */
8259 #define DSI_PCONFR_SW_TIME DSI_PCONFR_SW_TIME_Msk /*!< Stop Wait Time */
8260 #define DSI_PCONFR_SW_TIME0_Pos (8U)
8261 #define DSI_PCONFR_SW_TIME0_Msk (0x1U << DSI_PCONFR_SW_TIME0_Pos) /*!< 0x00000100 */
8262 #define DSI_PCONFR_SW_TIME0 DSI_PCONFR_SW_TIME0_Msk
8263 #define DSI_PCONFR_SW_TIME1_Pos (9U)
8264 #define DSI_PCONFR_SW_TIME1_Msk (0x1U << DSI_PCONFR_SW_TIME1_Pos) /*!< 0x00000200 */
8265 #define DSI_PCONFR_SW_TIME1 DSI_PCONFR_SW_TIME1_Msk
8266 #define DSI_PCONFR_SW_TIME2_Pos (10U)
8267 #define DSI_PCONFR_SW_TIME2_Msk (0x1U << DSI_PCONFR_SW_TIME2_Pos) /*!< 0x00000400 */
8268 #define DSI_PCONFR_SW_TIME2 DSI_PCONFR_SW_TIME2_Msk
8269 #define DSI_PCONFR_SW_TIME3_Pos (11U)
8270 #define DSI_PCONFR_SW_TIME3_Msk (0x1U << DSI_PCONFR_SW_TIME3_Pos) /*!< 0x00000800 */
8271 #define DSI_PCONFR_SW_TIME3 DSI_PCONFR_SW_TIME3_Msk
8272 #define DSI_PCONFR_SW_TIME4_Pos (12U)
8273 #define DSI_PCONFR_SW_TIME4_Msk (0x1U << DSI_PCONFR_SW_TIME4_Pos) /*!< 0x00001000 */
8274 #define DSI_PCONFR_SW_TIME4 DSI_PCONFR_SW_TIME4_Msk
8275 #define DSI_PCONFR_SW_TIME5_Pos (13U)
8276 #define DSI_PCONFR_SW_TIME5_Msk (0x1U << DSI_PCONFR_SW_TIME5_Pos) /*!< 0x00002000 */
8277 #define DSI_PCONFR_SW_TIME5 DSI_PCONFR_SW_TIME5_Msk
8278 #define DSI_PCONFR_SW_TIME6_Pos (14U)
8279 #define DSI_PCONFR_SW_TIME6_Msk (0x1U << DSI_PCONFR_SW_TIME6_Pos) /*!< 0x00004000 */
8280 #define DSI_PCONFR_SW_TIME6 DSI_PCONFR_SW_TIME6_Msk
8281 #define DSI_PCONFR_SW_TIME7_Pos (15U)
8282 #define DSI_PCONFR_SW_TIME7_Msk (0x1U << DSI_PCONFR_SW_TIME7_Pos) /*!< 0x00008000 */
8283 #define DSI_PCONFR_SW_TIME7 DSI_PCONFR_SW_TIME7_Msk
8284
8285 /******************* Bit definition for DSI_PUCR register ***************/
8286 #define DSI_PUCR_URCL_Pos (0U)
8287 #define DSI_PUCR_URCL_Msk (0x1U << DSI_PUCR_URCL_Pos) /*!< 0x00000001 */
8288 #define DSI_PUCR_URCL DSI_PUCR_URCL_Msk /*!< ULPS Request on Clock Lane */
8289 #define DSI_PUCR_UECL_Pos (1U)
8290 #define DSI_PUCR_UECL_Msk (0x1U << DSI_PUCR_UECL_Pos) /*!< 0x00000002 */
8291 #define DSI_PUCR_UECL DSI_PUCR_UECL_Msk /*!< ULPS Exit on Clock Lane */
8292 #define DSI_PUCR_URDL_Pos (2U)
8293 #define DSI_PUCR_URDL_Msk (0x1U << DSI_PUCR_URDL_Pos) /*!< 0x00000004 */
8294 #define DSI_PUCR_URDL DSI_PUCR_URDL_Msk /*!< ULPS Request on Data Lane */
8295 #define DSI_PUCR_UEDL_Pos (3U)
8296 #define DSI_PUCR_UEDL_Msk (0x1U << DSI_PUCR_UEDL_Pos) /*!< 0x00000008 */
8297 #define DSI_PUCR_UEDL DSI_PUCR_UEDL_Msk /*!< ULPS Exit on Data Lane */
8298
8299 /******************* Bit definition for DSI_PTTCR register **************/
8300 #define DSI_PTTCR_TX_TRIG_Pos (0U)
8301 #define DSI_PTTCR_TX_TRIG_Msk (0xFU << DSI_PTTCR_TX_TRIG_Pos) /*!< 0x0000000F */
8302 #define DSI_PTTCR_TX_TRIG DSI_PTTCR_TX_TRIG_Msk /*!< Transmission Trigger */
8303 #define DSI_PTTCR_TX_TRIG0_Pos (0U)
8304 #define DSI_PTTCR_TX_TRIG0_Msk (0x1U << DSI_PTTCR_TX_TRIG0_Pos) /*!< 0x00000001 */
8305 #define DSI_PTTCR_TX_TRIG0 DSI_PTTCR_TX_TRIG0_Msk
8306 #define DSI_PTTCR_TX_TRIG1_Pos (1U)
8307 #define DSI_PTTCR_TX_TRIG1_Msk (0x1U << DSI_PTTCR_TX_TRIG1_Pos) /*!< 0x00000002 */
8308 #define DSI_PTTCR_TX_TRIG1 DSI_PTTCR_TX_TRIG1_Msk
8309 #define DSI_PTTCR_TX_TRIG2_Pos (2U)
8310 #define DSI_PTTCR_TX_TRIG2_Msk (0x1U << DSI_PTTCR_TX_TRIG2_Pos) /*!< 0x00000004 */
8311 #define DSI_PTTCR_TX_TRIG2 DSI_PTTCR_TX_TRIG2_Msk
8312 #define DSI_PTTCR_TX_TRIG3_Pos (3U)
8313 #define DSI_PTTCR_TX_TRIG3_Msk (0x1U << DSI_PTTCR_TX_TRIG3_Pos) /*!< 0x00000008 */
8314 #define DSI_PTTCR_TX_TRIG3 DSI_PTTCR_TX_TRIG3_Msk
8315
8316 /******************* Bit definition for DSI_PSR register ****************/
8317 #define DSI_PSR_PD_Pos (1U)
8318 #define DSI_PSR_PD_Msk (0x1U << DSI_PSR_PD_Pos) /*!< 0x00000002 */
8319 #define DSI_PSR_PD DSI_PSR_PD_Msk /*!< PHY Direction */
8320 #define DSI_PSR_PSSC_Pos (2U)
8321 #define DSI_PSR_PSSC_Msk (0x1U << DSI_PSR_PSSC_Pos) /*!< 0x00000004 */
8322 #define DSI_PSR_PSSC DSI_PSR_PSSC_Msk /*!< PHY Stop State Clock lane */
8323 #define DSI_PSR_UANC_Pos (3U)
8324 #define DSI_PSR_UANC_Msk (0x1U << DSI_PSR_UANC_Pos) /*!< 0x00000008 */
8325 #define DSI_PSR_UANC DSI_PSR_UANC_Msk /*!< ULPS Active Not Clock lane */
8326 #define DSI_PSR_PSS0_Pos (4U)
8327 #define DSI_PSR_PSS0_Msk (0x1U << DSI_PSR_PSS0_Pos) /*!< 0x00000010 */
8328 #define DSI_PSR_PSS0 DSI_PSR_PSS0_Msk /*!< PHY Stop State lane 0 */
8329 #define DSI_PSR_UAN0_Pos (5U)
8330 #define DSI_PSR_UAN0_Msk (0x1U << DSI_PSR_UAN0_Pos) /*!< 0x00000020 */
8331 #define DSI_PSR_UAN0 DSI_PSR_UAN0_Msk /*!< ULPS Active Not lane 0 */
8332 #define DSI_PSR_RUE0_Pos (6U)
8333 #define DSI_PSR_RUE0_Msk (0x1U << DSI_PSR_RUE0_Pos) /*!< 0x00000040 */
8334 #define DSI_PSR_RUE0 DSI_PSR_RUE0_Msk /*!< RX ULPS Escape lane 0 */
8335 #define DSI_PSR_PSS1_Pos (7U)
8336 #define DSI_PSR_PSS1_Msk (0x1U << DSI_PSR_PSS1_Pos) /*!< 0x00000080 */
8337 #define DSI_PSR_PSS1 DSI_PSR_PSS1_Msk /*!< PHY Stop State lane 1 */
8338 #define DSI_PSR_UAN1_Pos (8U)
8339 #define DSI_PSR_UAN1_Msk (0x1U << DSI_PSR_UAN1_Pos) /*!< 0x00000100 */
8340 #define DSI_PSR_UAN1 DSI_PSR_UAN1_Msk /*!< ULPS Active Not lane 1 */
8341
8342 /******************* Bit definition for DSI_ISR0 register ***************/
8343 #define DSI_ISR0_AE0_Pos (0U)
8344 #define DSI_ISR0_AE0_Msk (0x1U << DSI_ISR0_AE0_Pos) /*!< 0x00000001 */
8345 #define DSI_ISR0_AE0 DSI_ISR0_AE0_Msk /*!< Acknowledge Error 0 */
8346 #define DSI_ISR0_AE1_Pos (1U)
8347 #define DSI_ISR0_AE1_Msk (0x1U << DSI_ISR0_AE1_Pos) /*!< 0x00000002 */
8348 #define DSI_ISR0_AE1 DSI_ISR0_AE1_Msk /*!< Acknowledge Error 1 */
8349 #define DSI_ISR0_AE2_Pos (2U)
8350 #define DSI_ISR0_AE2_Msk (0x1U << DSI_ISR0_AE2_Pos) /*!< 0x00000004 */
8351 #define DSI_ISR0_AE2 DSI_ISR0_AE2_Msk /*!< Acknowledge Error 2 */
8352 #define DSI_ISR0_AE3_Pos (3U)
8353 #define DSI_ISR0_AE3_Msk (0x1U << DSI_ISR0_AE3_Pos) /*!< 0x00000008 */
8354 #define DSI_ISR0_AE3 DSI_ISR0_AE3_Msk /*!< Acknowledge Error 3 */
8355 #define DSI_ISR0_AE4_Pos (4U)
8356 #define DSI_ISR0_AE4_Msk (0x1U << DSI_ISR0_AE4_Pos) /*!< 0x00000010 */
8357 #define DSI_ISR0_AE4 DSI_ISR0_AE4_Msk /*!< Acknowledge Error 4 */
8358 #define DSI_ISR0_AE5_Pos (5U)
8359 #define DSI_ISR0_AE5_Msk (0x1U << DSI_ISR0_AE5_Pos) /*!< 0x00000020 */
8360 #define DSI_ISR0_AE5 DSI_ISR0_AE5_Msk /*!< Acknowledge Error 5 */
8361 #define DSI_ISR0_AE6_Pos (6U)
8362 #define DSI_ISR0_AE6_Msk (0x1U << DSI_ISR0_AE6_Pos) /*!< 0x00000040 */
8363 #define DSI_ISR0_AE6 DSI_ISR0_AE6_Msk /*!< Acknowledge Error 6 */
8364 #define DSI_ISR0_AE7_Pos (7U)
8365 #define DSI_ISR0_AE7_Msk (0x1U << DSI_ISR0_AE7_Pos) /*!< 0x00000080 */
8366 #define DSI_ISR0_AE7 DSI_ISR0_AE7_Msk /*!< Acknowledge Error 7 */
8367 #define DSI_ISR0_AE8_Pos (8U)
8368 #define DSI_ISR0_AE8_Msk (0x1U << DSI_ISR0_AE8_Pos) /*!< 0x00000100 */
8369 #define DSI_ISR0_AE8 DSI_ISR0_AE8_Msk /*!< Acknowledge Error 8 */
8370 #define DSI_ISR0_AE9_Pos (9U)
8371 #define DSI_ISR0_AE9_Msk (0x1U << DSI_ISR0_AE9_Pos) /*!< 0x00000200 */
8372 #define DSI_ISR0_AE9 DSI_ISR0_AE9_Msk /*!< Acknowledge Error 9 */
8373 #define DSI_ISR0_AE10_Pos (10U)
8374 #define DSI_ISR0_AE10_Msk (0x1U << DSI_ISR0_AE10_Pos) /*!< 0x00000400 */
8375 #define DSI_ISR0_AE10 DSI_ISR0_AE10_Msk /*!< Acknowledge Error 10 */
8376 #define DSI_ISR0_AE11_Pos (11U)
8377 #define DSI_ISR0_AE11_Msk (0x1U << DSI_ISR0_AE11_Pos) /*!< 0x00000800 */
8378 #define DSI_ISR0_AE11 DSI_ISR0_AE11_Msk /*!< Acknowledge Error 11 */
8379 #define DSI_ISR0_AE12_Pos (12U)
8380 #define DSI_ISR0_AE12_Msk (0x1U << DSI_ISR0_AE12_Pos) /*!< 0x00001000 */
8381 #define DSI_ISR0_AE12 DSI_ISR0_AE12_Msk /*!< Acknowledge Error 12 */
8382 #define DSI_ISR0_AE13_Pos (13U)
8383 #define DSI_ISR0_AE13_Msk (0x1U << DSI_ISR0_AE13_Pos) /*!< 0x00002000 */
8384 #define DSI_ISR0_AE13 DSI_ISR0_AE13_Msk /*!< Acknowledge Error 13 */
8385 #define DSI_ISR0_AE14_Pos (14U)
8386 #define DSI_ISR0_AE14_Msk (0x1U << DSI_ISR0_AE14_Pos) /*!< 0x00004000 */
8387 #define DSI_ISR0_AE14 DSI_ISR0_AE14_Msk /*!< Acknowledge Error 14 */
8388 #define DSI_ISR0_AE15_Pos (15U)
8389 #define DSI_ISR0_AE15_Msk (0x1U << DSI_ISR0_AE15_Pos) /*!< 0x00008000 */
8390 #define DSI_ISR0_AE15 DSI_ISR0_AE15_Msk /*!< Acknowledge Error 15 */
8391 #define DSI_ISR0_PE0_Pos (16U)
8392 #define DSI_ISR0_PE0_Msk (0x1U << DSI_ISR0_PE0_Pos) /*!< 0x00010000 */
8393 #define DSI_ISR0_PE0 DSI_ISR0_PE0_Msk /*!< PHY Error 0 */
8394 #define DSI_ISR0_PE1_Pos (17U)
8395 #define DSI_ISR0_PE1_Msk (0x1U << DSI_ISR0_PE1_Pos) /*!< 0x00020000 */
8396 #define DSI_ISR0_PE1 DSI_ISR0_PE1_Msk /*!< PHY Error 1 */
8397 #define DSI_ISR0_PE2_Pos (18U)
8398 #define DSI_ISR0_PE2_Msk (0x1U << DSI_ISR0_PE2_Pos) /*!< 0x00040000 */
8399 #define DSI_ISR0_PE2 DSI_ISR0_PE2_Msk /*!< PHY Error 2 */
8400 #define DSI_ISR0_PE3_Pos (19U)
8401 #define DSI_ISR0_PE3_Msk (0x1U << DSI_ISR0_PE3_Pos) /*!< 0x00080000 */
8402 #define DSI_ISR0_PE3 DSI_ISR0_PE3_Msk /*!< PHY Error 3 */
8403 #define DSI_ISR0_PE4_Pos (20U)
8404 #define DSI_ISR0_PE4_Msk (0x1U << DSI_ISR0_PE4_Pos) /*!< 0x00100000 */
8405 #define DSI_ISR0_PE4 DSI_ISR0_PE4_Msk /*!< PHY Error 4 */
8406
8407 /******************* Bit definition for DSI_ISR1 register ***************/
8408 #define DSI_ISR1_TOHSTX_Pos (0U)
8409 #define DSI_ISR1_TOHSTX_Msk (0x1U << DSI_ISR1_TOHSTX_Pos) /*!< 0x00000001 */
8410 #define DSI_ISR1_TOHSTX DSI_ISR1_TOHSTX_Msk /*!< Timeout High-Speed Transmission */
8411 #define DSI_ISR1_TOLPRX_Pos (1U)
8412 #define DSI_ISR1_TOLPRX_Msk (0x1U << DSI_ISR1_TOLPRX_Pos) /*!< 0x00000002 */
8413 #define DSI_ISR1_TOLPRX DSI_ISR1_TOLPRX_Msk /*!< Timeout Low-Power Reception */
8414 #define DSI_ISR1_ECCSE_Pos (2U)
8415 #define DSI_ISR1_ECCSE_Msk (0x1U << DSI_ISR1_ECCSE_Pos) /*!< 0x00000004 */
8416 #define DSI_ISR1_ECCSE DSI_ISR1_ECCSE_Msk /*!< ECC Single-bit Error */
8417 #define DSI_ISR1_ECCME_Pos (3U)
8418 #define DSI_ISR1_ECCME_Msk (0x1U << DSI_ISR1_ECCME_Pos) /*!< 0x00000008 */
8419 #define DSI_ISR1_ECCME DSI_ISR1_ECCME_Msk /*!< ECC Multi-bit Error */
8420 #define DSI_ISR1_CRCE_Pos (4U)
8421 #define DSI_ISR1_CRCE_Msk (0x1U << DSI_ISR1_CRCE_Pos) /*!< 0x00000010 */
8422 #define DSI_ISR1_CRCE DSI_ISR1_CRCE_Msk /*!< CRC Error */
8423 #define DSI_ISR1_PSE_Pos (5U)
8424 #define DSI_ISR1_PSE_Msk (0x1U << DSI_ISR1_PSE_Pos) /*!< 0x00000020 */
8425 #define DSI_ISR1_PSE DSI_ISR1_PSE_Msk /*!< Packet Size Error */
8426 #define DSI_ISR1_EOTPE_Pos (6U)
8427 #define DSI_ISR1_EOTPE_Msk (0x1U << DSI_ISR1_EOTPE_Pos) /*!< 0x00000040 */
8428 #define DSI_ISR1_EOTPE DSI_ISR1_EOTPE_Msk /*!< EoTp Error */
8429 #define DSI_ISR1_LPWRE_Pos (7U)
8430 #define DSI_ISR1_LPWRE_Msk (0x1U << DSI_ISR1_LPWRE_Pos) /*!< 0x00000080 */
8431 #define DSI_ISR1_LPWRE DSI_ISR1_LPWRE_Msk /*!< LTDC Payload Write Error */
8432 #define DSI_ISR1_GCWRE_Pos (8U)
8433 #define DSI_ISR1_GCWRE_Msk (0x1U << DSI_ISR1_GCWRE_Pos) /*!< 0x00000100 */
8434 #define DSI_ISR1_GCWRE DSI_ISR1_GCWRE_Msk /*!< Generic Command Write Error */
8435 #define DSI_ISR1_GPWRE_Pos (9U)
8436 #define DSI_ISR1_GPWRE_Msk (0x1U << DSI_ISR1_GPWRE_Pos) /*!< 0x00000200 */
8437 #define DSI_ISR1_GPWRE DSI_ISR1_GPWRE_Msk /*!< Generic Payload Write Error */
8438 #define DSI_ISR1_GPTXE_Pos (10U)
8439 #define DSI_ISR1_GPTXE_Msk (0x1U << DSI_ISR1_GPTXE_Pos) /*!< 0x00000400 */
8440 #define DSI_ISR1_GPTXE DSI_ISR1_GPTXE_Msk /*!< Generic Payload Transmit Error */
8441 #define DSI_ISR1_GPRDE_Pos (11U)
8442 #define DSI_ISR1_GPRDE_Msk (0x1U << DSI_ISR1_GPRDE_Pos) /*!< 0x00000800 */
8443 #define DSI_ISR1_GPRDE DSI_ISR1_GPRDE_Msk /*!< Generic Payload Read Error */
8444 #define DSI_ISR1_GPRXE_Pos (12U)
8445 #define DSI_ISR1_GPRXE_Msk (0x1U << DSI_ISR1_GPRXE_Pos) /*!< 0x00001000 */
8446 #define DSI_ISR1_GPRXE DSI_ISR1_GPRXE_Msk /*!< Generic Payload Receive Error */
8447
8448 /******************* Bit definition for DSI_IER0 register ***************/
8449 #define DSI_IER0_AE0IE_Pos (0U)
8450 #define DSI_IER0_AE0IE_Msk (0x1U << DSI_IER0_AE0IE_Pos) /*!< 0x00000001 */
8451 #define DSI_IER0_AE0IE DSI_IER0_AE0IE_Msk /*!< Acknowledge Error 0 Interrupt Enable */
8452 #define DSI_IER0_AE1IE_Pos (1U)
8453 #define DSI_IER0_AE1IE_Msk (0x1U << DSI_IER0_AE1IE_Pos) /*!< 0x00000002 */
8454 #define DSI_IER0_AE1IE DSI_IER0_AE1IE_Msk /*!< Acknowledge Error 1 Interrupt Enable */
8455 #define DSI_IER0_AE2IE_Pos (2U)
8456 #define DSI_IER0_AE2IE_Msk (0x1U << DSI_IER0_AE2IE_Pos) /*!< 0x00000004 */
8457 #define DSI_IER0_AE2IE DSI_IER0_AE2IE_Msk /*!< Acknowledge Error 2 Interrupt Enable */
8458 #define DSI_IER0_AE3IE_Pos (3U)
8459 #define DSI_IER0_AE3IE_Msk (0x1U << DSI_IER0_AE3IE_Pos) /*!< 0x00000008 */
8460 #define DSI_IER0_AE3IE DSI_IER0_AE3IE_Msk /*!< Acknowledge Error 3 Interrupt Enable */
8461 #define DSI_IER0_AE4IE_Pos (4U)
8462 #define DSI_IER0_AE4IE_Msk (0x1U << DSI_IER0_AE4IE_Pos) /*!< 0x00000010 */
8463 #define DSI_IER0_AE4IE DSI_IER0_AE4IE_Msk /*!< Acknowledge Error 4 Interrupt Enable */
8464 #define DSI_IER0_AE5IE_Pos (5U)
8465 #define DSI_IER0_AE5IE_Msk (0x1U << DSI_IER0_AE5IE_Pos) /*!< 0x00000020 */
8466 #define DSI_IER0_AE5IE DSI_IER0_AE5IE_Msk /*!< Acknowledge Error 5 Interrupt Enable */
8467 #define DSI_IER0_AE6IE_Pos (6U)
8468 #define DSI_IER0_AE6IE_Msk (0x1U << DSI_IER0_AE6IE_Pos) /*!< 0x00000040 */
8469 #define DSI_IER0_AE6IE DSI_IER0_AE6IE_Msk /*!< Acknowledge Error 6 Interrupt Enable */
8470 #define DSI_IER0_AE7IE_Pos (7U)
8471 #define DSI_IER0_AE7IE_Msk (0x1U << DSI_IER0_AE7IE_Pos) /*!< 0x00000080 */
8472 #define DSI_IER0_AE7IE DSI_IER0_AE7IE_Msk /*!< Acknowledge Error 7 Interrupt Enable */
8473 #define DSI_IER0_AE8IE_Pos (8U)
8474 #define DSI_IER0_AE8IE_Msk (0x1U << DSI_IER0_AE8IE_Pos) /*!< 0x00000100 */
8475 #define DSI_IER0_AE8IE DSI_IER0_AE8IE_Msk /*!< Acknowledge Error 8 Interrupt Enable */
8476 #define DSI_IER0_AE9IE_Pos (9U)
8477 #define DSI_IER0_AE9IE_Msk (0x1U << DSI_IER0_AE9IE_Pos) /*!< 0x00000200 */
8478 #define DSI_IER0_AE9IE DSI_IER0_AE9IE_Msk /*!< Acknowledge Error 9 Interrupt Enable */
8479 #define DSI_IER0_AE10IE_Pos (10U)
8480 #define DSI_IER0_AE10IE_Msk (0x1U << DSI_IER0_AE10IE_Pos) /*!< 0x00000400 */
8481 #define DSI_IER0_AE10IE DSI_IER0_AE10IE_Msk /*!< Acknowledge Error 10 Interrupt Enable */
8482 #define DSI_IER0_AE11IE_Pos (11U)
8483 #define DSI_IER0_AE11IE_Msk (0x1U << DSI_IER0_AE11IE_Pos) /*!< 0x00000800 */
8484 #define DSI_IER0_AE11IE DSI_IER0_AE11IE_Msk /*!< Acknowledge Error 11 Interrupt Enable */
8485 #define DSI_IER0_AE12IE_Pos (12U)
8486 #define DSI_IER0_AE12IE_Msk (0x1U << DSI_IER0_AE12IE_Pos) /*!< 0x00001000 */
8487 #define DSI_IER0_AE12IE DSI_IER0_AE12IE_Msk /*!< Acknowledge Error 12 Interrupt Enable */
8488 #define DSI_IER0_AE13IE_Pos (13U)
8489 #define DSI_IER0_AE13IE_Msk (0x1U << DSI_IER0_AE13IE_Pos) /*!< 0x00002000 */
8490 #define DSI_IER0_AE13IE DSI_IER0_AE13IE_Msk /*!< Acknowledge Error 13 Interrupt Enable */
8491 #define DSI_IER0_AE14IE_Pos (14U)
8492 #define DSI_IER0_AE14IE_Msk (0x1U << DSI_IER0_AE14IE_Pos) /*!< 0x00004000 */
8493 #define DSI_IER0_AE14IE DSI_IER0_AE14IE_Msk /*!< Acknowledge Error 14 Interrupt Enable */
8494 #define DSI_IER0_AE15IE_Pos (15U)
8495 #define DSI_IER0_AE15IE_Msk (0x1U << DSI_IER0_AE15IE_Pos) /*!< 0x00008000 */
8496 #define DSI_IER0_AE15IE DSI_IER0_AE15IE_Msk /*!< Acknowledge Error 15 Interrupt Enable */
8497 #define DSI_IER0_PE0IE_Pos (16U)
8498 #define DSI_IER0_PE0IE_Msk (0x1U << DSI_IER0_PE0IE_Pos) /*!< 0x00010000 */
8499 #define DSI_IER0_PE0IE DSI_IER0_PE0IE_Msk /*!< PHY Error 0 Interrupt Enable */
8500 #define DSI_IER0_PE1IE_Pos (17U)
8501 #define DSI_IER0_PE1IE_Msk (0x1U << DSI_IER0_PE1IE_Pos) /*!< 0x00020000 */
8502 #define DSI_IER0_PE1IE DSI_IER0_PE1IE_Msk /*!< PHY Error 1 Interrupt Enable */
8503 #define DSI_IER0_PE2IE_Pos (18U)
8504 #define DSI_IER0_PE2IE_Msk (0x1U << DSI_IER0_PE2IE_Pos) /*!< 0x00040000 */
8505 #define DSI_IER0_PE2IE DSI_IER0_PE2IE_Msk /*!< PHY Error 2 Interrupt Enable */
8506 #define DSI_IER0_PE3IE_Pos (19U)
8507 #define DSI_IER0_PE3IE_Msk (0x1U << DSI_IER0_PE3IE_Pos) /*!< 0x00080000 */
8508 #define DSI_IER0_PE3IE DSI_IER0_PE3IE_Msk /*!< PHY Error 3 Interrupt Enable */
8509 #define DSI_IER0_PE4IE_Pos (20U)
8510 #define DSI_IER0_PE4IE_Msk (0x1U << DSI_IER0_PE4IE_Pos) /*!< 0x00100000 */
8511 #define DSI_IER0_PE4IE DSI_IER0_PE4IE_Msk /*!< PHY Error 4 Interrupt Enable */
8512
8513 /******************* Bit definition for DSI_IER1 register ***************/
8514 #define DSI_IER1_TOHSTXIE_Pos (0U)
8515 #define DSI_IER1_TOHSTXIE_Msk (0x1U << DSI_IER1_TOHSTXIE_Pos) /*!< 0x00000001 */
8516 #define DSI_IER1_TOHSTXIE DSI_IER1_TOHSTXIE_Msk /*!< Timeout High-Speed Transmission Interrupt Enable */
8517 #define DSI_IER1_TOLPRXIE_Pos (1U)
8518 #define DSI_IER1_TOLPRXIE_Msk (0x1U << DSI_IER1_TOLPRXIE_Pos) /*!< 0x00000002 */
8519 #define DSI_IER1_TOLPRXIE DSI_IER1_TOLPRXIE_Msk /*!< Timeout Low-Power Reception Interrupt Enable */
8520 #define DSI_IER1_ECCSEIE_Pos (2U)
8521 #define DSI_IER1_ECCSEIE_Msk (0x1U << DSI_IER1_ECCSEIE_Pos) /*!< 0x00000004 */
8522 #define DSI_IER1_ECCSEIE DSI_IER1_ECCSEIE_Msk /*!< ECC Single-bit Error Interrupt Enable */
8523 #define DSI_IER1_ECCMEIE_Pos (3U)
8524 #define DSI_IER1_ECCMEIE_Msk (0x1U << DSI_IER1_ECCMEIE_Pos) /*!< 0x00000008 */
8525 #define DSI_IER1_ECCMEIE DSI_IER1_ECCMEIE_Msk /*!< ECC Multi-bit Error Interrupt Enable */
8526 #define DSI_IER1_CRCEIE_Pos (4U)
8527 #define DSI_IER1_CRCEIE_Msk (0x1U << DSI_IER1_CRCEIE_Pos) /*!< 0x00000010 */
8528 #define DSI_IER1_CRCEIE DSI_IER1_CRCEIE_Msk /*!< CRC Error Interrupt Enable */
8529 #define DSI_IER1_PSEIE_Pos (5U)
8530 #define DSI_IER1_PSEIE_Msk (0x1U << DSI_IER1_PSEIE_Pos) /*!< 0x00000020 */
8531 #define DSI_IER1_PSEIE DSI_IER1_PSEIE_Msk /*!< Packet Size Error Interrupt Enable */
8532 #define DSI_IER1_EOTPEIE_Pos (6U)
8533 #define DSI_IER1_EOTPEIE_Msk (0x1U << DSI_IER1_EOTPEIE_Pos) /*!< 0x00000040 */
8534 #define DSI_IER1_EOTPEIE DSI_IER1_EOTPEIE_Msk /*!< EoTp Error Interrupt Enable */
8535 #define DSI_IER1_LPWREIE_Pos (7U)
8536 #define DSI_IER1_LPWREIE_Msk (0x1U << DSI_IER1_LPWREIE_Pos) /*!< 0x00000080 */
8537 #define DSI_IER1_LPWREIE DSI_IER1_LPWREIE_Msk /*!< LTDC Payload Write Error Interrupt Enable */
8538 #define DSI_IER1_GCWREIE_Pos (8U)
8539 #define DSI_IER1_GCWREIE_Msk (0x1U << DSI_IER1_GCWREIE_Pos) /*!< 0x00000100 */
8540 #define DSI_IER1_GCWREIE DSI_IER1_GCWREIE_Msk /*!< Generic Command Write Error Interrupt Enable */
8541 #define DSI_IER1_GPWREIE_Pos (9U)
8542 #define DSI_IER1_GPWREIE_Msk (0x1U << DSI_IER1_GPWREIE_Pos) /*!< 0x00000200 */
8543 #define DSI_IER1_GPWREIE DSI_IER1_GPWREIE_Msk /*!< Generic Payload Write Error Interrupt Enable */
8544 #define DSI_IER1_GPTXEIE_Pos (10U)
8545 #define DSI_IER1_GPTXEIE_Msk (0x1U << DSI_IER1_GPTXEIE_Pos) /*!< 0x00000400 */
8546 #define DSI_IER1_GPTXEIE DSI_IER1_GPTXEIE_Msk /*!< Generic Payload Transmit Error Interrupt Enable */
8547 #define DSI_IER1_GPRDEIE_Pos (11U)
8548 #define DSI_IER1_GPRDEIE_Msk (0x1U << DSI_IER1_GPRDEIE_Pos) /*!< 0x00000800 */
8549 #define DSI_IER1_GPRDEIE DSI_IER1_GPRDEIE_Msk /*!< Generic Payload Read Error Interrupt Enable */
8550 #define DSI_IER1_GPRXEIE_Pos (12U)
8551 #define DSI_IER1_GPRXEIE_Msk (0x1U << DSI_IER1_GPRXEIE_Pos) /*!< 0x00001000 */
8552 #define DSI_IER1_GPRXEIE DSI_IER1_GPRXEIE_Msk /*!< Generic Payload Receive Error Interrupt Enable */
8553
8554 /******************* Bit definition for DSI_FIR0 register ***************/
8555 #define DSI_FIR0_FAE0_Pos (0U)
8556 #define DSI_FIR0_FAE0_Msk (0x1U << DSI_FIR0_FAE0_Pos) /*!< 0x00000001 */
8557 #define DSI_FIR0_FAE0 DSI_FIR0_FAE0_Msk /*!< Force Acknowledge Error 0 */
8558 #define DSI_FIR0_FAE1_Pos (1U)
8559 #define DSI_FIR0_FAE1_Msk (0x1U << DSI_FIR0_FAE1_Pos) /*!< 0x00000002 */
8560 #define DSI_FIR0_FAE1 DSI_FIR0_FAE1_Msk /*!< Force Acknowledge Error 1 */
8561 #define DSI_FIR0_FAE2_Pos (2U)
8562 #define DSI_FIR0_FAE2_Msk (0x1U << DSI_FIR0_FAE2_Pos) /*!< 0x00000004 */
8563 #define DSI_FIR0_FAE2 DSI_FIR0_FAE2_Msk /*!< Force Acknowledge Error 2 */
8564 #define DSI_FIR0_FAE3_Pos (3U)
8565 #define DSI_FIR0_FAE3_Msk (0x1U << DSI_FIR0_FAE3_Pos) /*!< 0x00000008 */
8566 #define DSI_FIR0_FAE3 DSI_FIR0_FAE3_Msk /*!< Force Acknowledge Error 3 */
8567 #define DSI_FIR0_FAE4_Pos (4U)
8568 #define DSI_FIR0_FAE4_Msk (0x1U << DSI_FIR0_FAE4_Pos) /*!< 0x00000010 */
8569 #define DSI_FIR0_FAE4 DSI_FIR0_FAE4_Msk /*!< Force Acknowledge Error 4 */
8570 #define DSI_FIR0_FAE5_Pos (5U)
8571 #define DSI_FIR0_FAE5_Msk (0x1U << DSI_FIR0_FAE5_Pos) /*!< 0x00000020 */
8572 #define DSI_FIR0_FAE5 DSI_FIR0_FAE5_Msk /*!< Force Acknowledge Error 5 */
8573 #define DSI_FIR0_FAE6_Pos (6U)
8574 #define DSI_FIR0_FAE6_Msk (0x1U << DSI_FIR0_FAE6_Pos) /*!< 0x00000040 */
8575 #define DSI_FIR0_FAE6 DSI_FIR0_FAE6_Msk /*!< Force Acknowledge Error 6 */
8576 #define DSI_FIR0_FAE7_Pos (7U)
8577 #define DSI_FIR0_FAE7_Msk (0x1U << DSI_FIR0_FAE7_Pos) /*!< 0x00000080 */
8578 #define DSI_FIR0_FAE7 DSI_FIR0_FAE7_Msk /*!< Force Acknowledge Error 7 */
8579 #define DSI_FIR0_FAE8_Pos (8U)
8580 #define DSI_FIR0_FAE8_Msk (0x1U << DSI_FIR0_FAE8_Pos) /*!< 0x00000100 */
8581 #define DSI_FIR0_FAE8 DSI_FIR0_FAE8_Msk /*!< Force Acknowledge Error 8 */
8582 #define DSI_FIR0_FAE9_Pos (9U)
8583 #define DSI_FIR0_FAE9_Msk (0x1U << DSI_FIR0_FAE9_Pos) /*!< 0x00000200 */
8584 #define DSI_FIR0_FAE9 DSI_FIR0_FAE9_Msk /*!< Force Acknowledge Error 9 */
8585 #define DSI_FIR0_FAE10_Pos (10U)
8586 #define DSI_FIR0_FAE10_Msk (0x1U << DSI_FIR0_FAE10_Pos) /*!< 0x00000400 */
8587 #define DSI_FIR0_FAE10 DSI_FIR0_FAE10_Msk /*!< Force Acknowledge Error 10 */
8588 #define DSI_FIR0_FAE11_Pos (11U)
8589 #define DSI_FIR0_FAE11_Msk (0x1U << DSI_FIR0_FAE11_Pos) /*!< 0x00000800 */
8590 #define DSI_FIR0_FAE11 DSI_FIR0_FAE11_Msk /*!< Force Acknowledge Error 11 */
8591 #define DSI_FIR0_FAE12_Pos (12U)
8592 #define DSI_FIR0_FAE12_Msk (0x1U << DSI_FIR0_FAE12_Pos) /*!< 0x00001000 */
8593 #define DSI_FIR0_FAE12 DSI_FIR0_FAE12_Msk /*!< Force Acknowledge Error 12 */
8594 #define DSI_FIR0_FAE13_Pos (13U)
8595 #define DSI_FIR0_FAE13_Msk (0x1U << DSI_FIR0_FAE13_Pos) /*!< 0x00002000 */
8596 #define DSI_FIR0_FAE13 DSI_FIR0_FAE13_Msk /*!< Force Acknowledge Error 13 */
8597 #define DSI_FIR0_FAE14_Pos (14U)
8598 #define DSI_FIR0_FAE14_Msk (0x1U << DSI_FIR0_FAE14_Pos) /*!< 0x00004000 */
8599 #define DSI_FIR0_FAE14 DSI_FIR0_FAE14_Msk /*!< Force Acknowledge Error 14 */
8600 #define DSI_FIR0_FAE15_Pos (15U)
8601 #define DSI_FIR0_FAE15_Msk (0x1U << DSI_FIR0_FAE15_Pos) /*!< 0x00008000 */
8602 #define DSI_FIR0_FAE15 DSI_FIR0_FAE15_Msk /*!< Force Acknowledge Error 15 */
8603 #define DSI_FIR0_FPE0_Pos (16U)
8604 #define DSI_FIR0_FPE0_Msk (0x1U << DSI_FIR0_FPE0_Pos) /*!< 0x00010000 */
8605 #define DSI_FIR0_FPE0 DSI_FIR0_FPE0_Msk /*!< Force PHY Error 0 */
8606 #define DSI_FIR0_FPE1_Pos (17U)
8607 #define DSI_FIR0_FPE1_Msk (0x1U << DSI_FIR0_FPE1_Pos) /*!< 0x00020000 */
8608 #define DSI_FIR0_FPE1 DSI_FIR0_FPE1_Msk /*!< Force PHY Error 1 */
8609 #define DSI_FIR0_FPE2_Pos (18U)
8610 #define DSI_FIR0_FPE2_Msk (0x1U << DSI_FIR0_FPE2_Pos) /*!< 0x00040000 */
8611 #define DSI_FIR0_FPE2 DSI_FIR0_FPE2_Msk /*!< Force PHY Error 2 */
8612 #define DSI_FIR0_FPE3_Pos (19U)
8613 #define DSI_FIR0_FPE3_Msk (0x1U << DSI_FIR0_FPE3_Pos) /*!< 0x00080000 */
8614 #define DSI_FIR0_FPE3 DSI_FIR0_FPE3_Msk /*!< Force PHY Error 3 */
8615 #define DSI_FIR0_FPE4_Pos (20U)
8616 #define DSI_FIR0_FPE4_Msk (0x1U << DSI_FIR0_FPE4_Pos) /*!< 0x00100000 */
8617 #define DSI_FIR0_FPE4 DSI_FIR0_FPE4_Msk /*!< Force PHY Error 4 */
8618
8619 /******************* Bit definition for DSI_FIR1 register ***************/
8620 #define DSI_FIR1_FTOHSTX_Pos (0U)
8621 #define DSI_FIR1_FTOHSTX_Msk (0x1U << DSI_FIR1_FTOHSTX_Pos) /*!< 0x00000001 */
8622 #define DSI_FIR1_FTOHSTX DSI_FIR1_FTOHSTX_Msk /*!< Force Timeout High-Speed Transmission */
8623 #define DSI_FIR1_FTOLPRX_Pos (1U)
8624 #define DSI_FIR1_FTOLPRX_Msk (0x1U << DSI_FIR1_FTOLPRX_Pos) /*!< 0x00000002 */
8625 #define DSI_FIR1_FTOLPRX DSI_FIR1_FTOLPRX_Msk /*!< Force Timeout Low-Power Reception */
8626 #define DSI_FIR1_FECCSE_Pos (2U)
8627 #define DSI_FIR1_FECCSE_Msk (0x1U << DSI_FIR1_FECCSE_Pos) /*!< 0x00000004 */
8628 #define DSI_FIR1_FECCSE DSI_FIR1_FECCSE_Msk /*!< Force ECC Single-bit Error */
8629 #define DSI_FIR1_FECCME_Pos (3U)
8630 #define DSI_FIR1_FECCME_Msk (0x1U << DSI_FIR1_FECCME_Pos) /*!< 0x00000008 */
8631 #define DSI_FIR1_FECCME DSI_FIR1_FECCME_Msk /*!< Force ECC Multi-bit Error */
8632 #define DSI_FIR1_FCRCE_Pos (4U)
8633 #define DSI_FIR1_FCRCE_Msk (0x1U << DSI_FIR1_FCRCE_Pos) /*!< 0x00000010 */
8634 #define DSI_FIR1_FCRCE DSI_FIR1_FCRCE_Msk /*!< Force CRC Error */
8635 #define DSI_FIR1_FPSE_Pos (5U)
8636 #define DSI_FIR1_FPSE_Msk (0x1U << DSI_FIR1_FPSE_Pos) /*!< 0x00000020 */
8637 #define DSI_FIR1_FPSE DSI_FIR1_FPSE_Msk /*!< Force Packet Size Error */
8638 #define DSI_FIR1_FEOTPE_Pos (6U)
8639 #define DSI_FIR1_FEOTPE_Msk (0x1U << DSI_FIR1_FEOTPE_Pos) /*!< 0x00000040 */
8640 #define DSI_FIR1_FEOTPE DSI_FIR1_FEOTPE_Msk /*!< Force EoTp Error */
8641 #define DSI_FIR1_FLPWRE_Pos (7U)
8642 #define DSI_FIR1_FLPWRE_Msk (0x1U << DSI_FIR1_FLPWRE_Pos) /*!< 0x00000080 */
8643 #define DSI_FIR1_FLPWRE DSI_FIR1_FLPWRE_Msk /*!< Force LTDC Payload Write Error */
8644 #define DSI_FIR1_FGCWRE_Pos (8U)
8645 #define DSI_FIR1_FGCWRE_Msk (0x1U << DSI_FIR1_FGCWRE_Pos) /*!< 0x00000100 */
8646 #define DSI_FIR1_FGCWRE DSI_FIR1_FGCWRE_Msk /*!< Force Generic Command Write Error */
8647 #define DSI_FIR1_FGPWRE_Pos (9U)
8648 #define DSI_FIR1_FGPWRE_Msk (0x1U << DSI_FIR1_FGPWRE_Pos) /*!< 0x00000200 */
8649 #define DSI_FIR1_FGPWRE DSI_FIR1_FGPWRE_Msk /*!< Force Generic Payload Write Error */
8650 #define DSI_FIR1_FGPTXE_Pos (10U)
8651 #define DSI_FIR1_FGPTXE_Msk (0x1U << DSI_FIR1_FGPTXE_Pos) /*!< 0x00000400 */
8652 #define DSI_FIR1_FGPTXE DSI_FIR1_FGPTXE_Msk /*!< Force Generic Payload Transmit Error */
8653 #define DSI_FIR1_FGPRDE_Pos (11U)
8654 #define DSI_FIR1_FGPRDE_Msk (0x1U << DSI_FIR1_FGPRDE_Pos) /*!< 0x00000800 */
8655 #define DSI_FIR1_FGPRDE DSI_FIR1_FGPRDE_Msk /*!< Force Generic Payload Read Error */
8656 #define DSI_FIR1_FGPRXE_Pos (12U)
8657 #define DSI_FIR1_FGPRXE_Msk (0x1U << DSI_FIR1_FGPRXE_Pos) /*!< 0x00001000 */
8658 #define DSI_FIR1_FGPRXE DSI_FIR1_FGPRXE_Msk /*!< Force Generic Payload Receive Error */
8659
8660 /******************* Bit definition for DSI_VSCR register ***************/
8661 #define DSI_VSCR_EN_Pos (0U)
8662 #define DSI_VSCR_EN_Msk (0x1U << DSI_VSCR_EN_Pos) /*!< 0x00000001 */
8663 #define DSI_VSCR_EN DSI_VSCR_EN_Msk /*!< Enable */
8664 #define DSI_VSCR_UR_Pos (8U)
8665 #define DSI_VSCR_UR_Msk (0x1U << DSI_VSCR_UR_Pos) /*!< 0x00000100 */
8666 #define DSI_VSCR_UR DSI_VSCR_UR_Msk /*!< Update Register */
8667
8668 /******************* Bit definition for DSI_LCVCIDR register ************/
8669 #define DSI_LCVCIDR_VCID_Pos (0U)
8670 #define DSI_LCVCIDR_VCID_Msk (0x3U << DSI_LCVCIDR_VCID_Pos) /*!< 0x00000003 */
8671 #define DSI_LCVCIDR_VCID DSI_LCVCIDR_VCID_Msk /*!< Virtual Channel ID */
8672 #define DSI_LCVCIDR_VCID0_Pos (0U)
8673 #define DSI_LCVCIDR_VCID0_Msk (0x1U << DSI_LCVCIDR_VCID0_Pos) /*!< 0x00000001 */
8674 #define DSI_LCVCIDR_VCID0 DSI_LCVCIDR_VCID0_Msk
8675 #define DSI_LCVCIDR_VCID1_Pos (1U)
8676 #define DSI_LCVCIDR_VCID1_Msk (0x1U << DSI_LCVCIDR_VCID1_Pos) /*!< 0x00000002 */
8677 #define DSI_LCVCIDR_VCID1 DSI_LCVCIDR_VCID1_Msk
8678
8679 /******************* Bit definition for DSI_LCCCR register **************/
8680 #define DSI_LCCCR_COLC_Pos (0U)
8681 #define DSI_LCCCR_COLC_Msk (0xFU << DSI_LCCCR_COLC_Pos) /*!< 0x0000000F */
8682 #define DSI_LCCCR_COLC DSI_LCCCR_COLC_Msk /*!< Color Coding */
8683 #define DSI_LCCCR_COLC0_Pos (0U)
8684 #define DSI_LCCCR_COLC0_Msk (0x1U << DSI_LCCCR_COLC0_Pos) /*!< 0x00000001 */
8685 #define DSI_LCCCR_COLC0 DSI_LCCCR_COLC0_Msk
8686 #define DSI_LCCCR_COLC1_Pos (1U)
8687 #define DSI_LCCCR_COLC1_Msk (0x1U << DSI_LCCCR_COLC1_Pos) /*!< 0x00000002 */
8688 #define DSI_LCCCR_COLC1 DSI_LCCCR_COLC1_Msk
8689 #define DSI_LCCCR_COLC2_Pos (2U)
8690 #define DSI_LCCCR_COLC2_Msk (0x1U << DSI_LCCCR_COLC2_Pos) /*!< 0x00000004 */
8691 #define DSI_LCCCR_COLC2 DSI_LCCCR_COLC2_Msk
8692 #define DSI_LCCCR_COLC3_Pos (3U)
8693 #define DSI_LCCCR_COLC3_Msk (0x1U << DSI_LCCCR_COLC3_Pos) /*!< 0x00000008 */
8694 #define DSI_LCCCR_COLC3 DSI_LCCCR_COLC3_Msk
8695
8696 #define DSI_LCCCR_LPE_Pos (8U)
8697 #define DSI_LCCCR_LPE_Msk (0x1U << DSI_LCCCR_LPE_Pos) /*!< 0x00000100 */
8698 #define DSI_LCCCR_LPE DSI_LCCCR_LPE_Msk /*!< Loosely Packed Enable */
8699
8700 /******************* Bit definition for DSI_LPMCCR register *************/
8701 #define DSI_LPMCCR_VLPSIZE_Pos (0U)
8702 #define DSI_LPMCCR_VLPSIZE_Msk (0xFFU << DSI_LPMCCR_VLPSIZE_Pos) /*!< 0x000000FF */
8703 #define DSI_LPMCCR_VLPSIZE DSI_LPMCCR_VLPSIZE_Msk /*!< VACT Largest Packet Size */
8704 #define DSI_LPMCCR_VLPSIZE0_Pos (0U)
8705 #define DSI_LPMCCR_VLPSIZE0_Msk (0x1U << DSI_LPMCCR_VLPSIZE0_Pos) /*!< 0x00000001 */
8706 #define DSI_LPMCCR_VLPSIZE0 DSI_LPMCCR_VLPSIZE0_Msk
8707 #define DSI_LPMCCR_VLPSIZE1_Pos (1U)
8708 #define DSI_LPMCCR_VLPSIZE1_Msk (0x1U << DSI_LPMCCR_VLPSIZE1_Pos) /*!< 0x00000002 */
8709 #define DSI_LPMCCR_VLPSIZE1 DSI_LPMCCR_VLPSIZE1_Msk
8710 #define DSI_LPMCCR_VLPSIZE2_Pos (2U)
8711 #define DSI_LPMCCR_VLPSIZE2_Msk (0x1U << DSI_LPMCCR_VLPSIZE2_Pos) /*!< 0x00000004 */
8712 #define DSI_LPMCCR_VLPSIZE2 DSI_LPMCCR_VLPSIZE2_Msk
8713 #define DSI_LPMCCR_VLPSIZE3_Pos (3U)
8714 #define DSI_LPMCCR_VLPSIZE3_Msk (0x1U << DSI_LPMCCR_VLPSIZE3_Pos) /*!< 0x00000008 */
8715 #define DSI_LPMCCR_VLPSIZE3 DSI_LPMCCR_VLPSIZE3_Msk
8716 #define DSI_LPMCCR_VLPSIZE4_Pos (4U)
8717 #define DSI_LPMCCR_VLPSIZE4_Msk (0x1U << DSI_LPMCCR_VLPSIZE4_Pos) /*!< 0x00000010 */
8718 #define DSI_LPMCCR_VLPSIZE4 DSI_LPMCCR_VLPSIZE4_Msk
8719 #define DSI_LPMCCR_VLPSIZE5_Pos (5U)
8720 #define DSI_LPMCCR_VLPSIZE5_Msk (0x1U << DSI_LPMCCR_VLPSIZE5_Pos) /*!< 0x00000020 */
8721 #define DSI_LPMCCR_VLPSIZE5 DSI_LPMCCR_VLPSIZE5_Msk
8722 #define DSI_LPMCCR_VLPSIZE6_Pos (6U)
8723 #define DSI_LPMCCR_VLPSIZE6_Msk (0x1U << DSI_LPMCCR_VLPSIZE6_Pos) /*!< 0x00000040 */
8724 #define DSI_LPMCCR_VLPSIZE6 DSI_LPMCCR_VLPSIZE6_Msk
8725 #define DSI_LPMCCR_VLPSIZE7_Pos (7U)
8726 #define DSI_LPMCCR_VLPSIZE7_Msk (0x1U << DSI_LPMCCR_VLPSIZE7_Pos) /*!< 0x00000080 */
8727 #define DSI_LPMCCR_VLPSIZE7 DSI_LPMCCR_VLPSIZE7_Msk
8728
8729 #define DSI_LPMCCR_LPSIZE_Pos (16U)
8730 #define DSI_LPMCCR_LPSIZE_Msk (0xFFU << DSI_LPMCCR_LPSIZE_Pos) /*!< 0x00FF0000 */
8731 #define DSI_LPMCCR_LPSIZE DSI_LPMCCR_LPSIZE_Msk /*!< Largest Packet Size */
8732 #define DSI_LPMCCR_LPSIZE0_Pos (16U)
8733 #define DSI_LPMCCR_LPSIZE0_Msk (0x1U << DSI_LPMCCR_LPSIZE0_Pos) /*!< 0x00010000 */
8734 #define DSI_LPMCCR_LPSIZE0 DSI_LPMCCR_LPSIZE0_Msk
8735 #define DSI_LPMCCR_LPSIZE1_Pos (17U)
8736 #define DSI_LPMCCR_LPSIZE1_Msk (0x1U << DSI_LPMCCR_LPSIZE1_Pos) /*!< 0x00020000 */
8737 #define DSI_LPMCCR_LPSIZE1 DSI_LPMCCR_LPSIZE1_Msk
8738 #define DSI_LPMCCR_LPSIZE2_Pos (18U)
8739 #define DSI_LPMCCR_LPSIZE2_Msk (0x1U << DSI_LPMCCR_LPSIZE2_Pos) /*!< 0x00040000 */
8740 #define DSI_LPMCCR_LPSIZE2 DSI_LPMCCR_LPSIZE2_Msk
8741 #define DSI_LPMCCR_LPSIZE3_Pos (19U)
8742 #define DSI_LPMCCR_LPSIZE3_Msk (0x1U << DSI_LPMCCR_LPSIZE3_Pos) /*!< 0x00080000 */
8743 #define DSI_LPMCCR_LPSIZE3 DSI_LPMCCR_LPSIZE3_Msk
8744 #define DSI_LPMCCR_LPSIZE4_Pos (20U)
8745 #define DSI_LPMCCR_LPSIZE4_Msk (0x1U << DSI_LPMCCR_LPSIZE4_Pos) /*!< 0x00100000 */
8746 #define DSI_LPMCCR_LPSIZE4 DSI_LPMCCR_LPSIZE4_Msk
8747 #define DSI_LPMCCR_LPSIZE5_Pos (21U)
8748 #define DSI_LPMCCR_LPSIZE5_Msk (0x1U << DSI_LPMCCR_LPSIZE5_Pos) /*!< 0x00200000 */
8749 #define DSI_LPMCCR_LPSIZE5 DSI_LPMCCR_LPSIZE5_Msk
8750 #define DSI_LPMCCR_LPSIZE6_Pos (22U)
8751 #define DSI_LPMCCR_LPSIZE6_Msk (0x1U << DSI_LPMCCR_LPSIZE6_Pos) /*!< 0x00400000 */
8752 #define DSI_LPMCCR_LPSIZE6 DSI_LPMCCR_LPSIZE6_Msk
8753 #define DSI_LPMCCR_LPSIZE7_Pos (23U)
8754 #define DSI_LPMCCR_LPSIZE7_Msk (0x1U << DSI_LPMCCR_LPSIZE7_Pos) /*!< 0x00800000 */
8755 #define DSI_LPMCCR_LPSIZE7 DSI_LPMCCR_LPSIZE7_Msk
8756
8757 /******************* Bit definition for DSI_VMCCR register **************/
8758 #define DSI_VMCCR_VMT_Pos (0U)
8759 #define DSI_VMCCR_VMT_Msk (0x3U << DSI_VMCCR_VMT_Pos) /*!< 0x00000003 */
8760 #define DSI_VMCCR_VMT DSI_VMCCR_VMT_Msk /*!< Video Mode Type */
8761 #define DSI_VMCCR_VMT0_Pos (0U)
8762 #define DSI_VMCCR_VMT0_Msk (0x1U << DSI_VMCCR_VMT0_Pos) /*!< 0x00000001 */
8763 #define DSI_VMCCR_VMT0 DSI_VMCCR_VMT0_Msk
8764 #define DSI_VMCCR_VMT1_Pos (1U)
8765 #define DSI_VMCCR_VMT1_Msk (0x1U << DSI_VMCCR_VMT1_Pos) /*!< 0x00000002 */
8766 #define DSI_VMCCR_VMT1 DSI_VMCCR_VMT1_Msk
8767
8768 #define DSI_VMCCR_LPVSAE_Pos (8U)
8769 #define DSI_VMCCR_LPVSAE_Msk (0x1U << DSI_VMCCR_LPVSAE_Pos) /*!< 0x00000100 */
8770 #define DSI_VMCCR_LPVSAE DSI_VMCCR_LPVSAE_Msk /*!< Low-power Vertical Sync time Enable */
8771 #define DSI_VMCCR_LPVBPE_Pos (9U)
8772 #define DSI_VMCCR_LPVBPE_Msk (0x1U << DSI_VMCCR_LPVBPE_Pos) /*!< 0x00000200 */
8773 #define DSI_VMCCR_LPVBPE DSI_VMCCR_LPVBPE_Msk /*!< Low-power Vertical Back-porch Enable */
8774 #define DSI_VMCCR_LPVFPE_Pos (10U)
8775 #define DSI_VMCCR_LPVFPE_Msk (0x1U << DSI_VMCCR_LPVFPE_Pos) /*!< 0x00000400 */
8776 #define DSI_VMCCR_LPVFPE DSI_VMCCR_LPVFPE_Msk /*!< Low-power Vertical Front-porch Enable */
8777 #define DSI_VMCCR_LPVAE_Pos (11U)
8778 #define DSI_VMCCR_LPVAE_Msk (0x1U << DSI_VMCCR_LPVAE_Pos) /*!< 0x00000800 */
8779 #define DSI_VMCCR_LPVAE DSI_VMCCR_LPVAE_Msk /*!< Low-power Vertical Active Enable */
8780 #define DSI_VMCCR_LPHBPE_Pos (12U)
8781 #define DSI_VMCCR_LPHBPE_Msk (0x1U << DSI_VMCCR_LPHBPE_Pos) /*!< 0x00001000 */
8782 #define DSI_VMCCR_LPHBPE DSI_VMCCR_LPHBPE_Msk /*!< Low-power Horizontal Back-porch Enable */
8783 #define DSI_VMCCR_LPHFE_Pos (13U)
8784 #define DSI_VMCCR_LPHFE_Msk (0x1U << DSI_VMCCR_LPHFE_Pos) /*!< 0x00002000 */
8785 #define DSI_VMCCR_LPHFE DSI_VMCCR_LPHFE_Msk /*!< Low-power Horizontal Front-porch Enable */
8786 #define DSI_VMCCR_FBTAAE_Pos (14U)
8787 #define DSI_VMCCR_FBTAAE_Msk (0x1U << DSI_VMCCR_FBTAAE_Pos) /*!< 0x00004000 */
8788 #define DSI_VMCCR_FBTAAE DSI_VMCCR_FBTAAE_Msk /*!< Frame BTA Acknowledge Enable */
8789 #define DSI_VMCCR_LPCE_Pos (15U)
8790 #define DSI_VMCCR_LPCE_Msk (0x1U << DSI_VMCCR_LPCE_Pos) /*!< 0x00008000 */
8791 #define DSI_VMCCR_LPCE DSI_VMCCR_LPCE_Msk /*!< Low-power Command Enable */
8792
8793 /******************* Bit definition for DSI_VPCCR register **************/
8794 #define DSI_VPCCR_VPSIZE_Pos (0U)
8795 #define DSI_VPCCR_VPSIZE_Msk (0x3FFFU << DSI_VPCCR_VPSIZE_Pos) /*!< 0x00003FFF */
8796 #define DSI_VPCCR_VPSIZE DSI_VPCCR_VPSIZE_Msk /*!< Video Packet Size */
8797 #define DSI_VPCCR_VPSIZE0_Pos (0U)
8798 #define DSI_VPCCR_VPSIZE0_Msk (0x1U << DSI_VPCCR_VPSIZE0_Pos) /*!< 0x00000001 */
8799 #define DSI_VPCCR_VPSIZE0 DSI_VPCCR_VPSIZE0_Msk
8800 #define DSI_VPCCR_VPSIZE1_Pos (1U)
8801 #define DSI_VPCCR_VPSIZE1_Msk (0x1U << DSI_VPCCR_VPSIZE1_Pos) /*!< 0x00000002 */
8802 #define DSI_VPCCR_VPSIZE1 DSI_VPCCR_VPSIZE1_Msk
8803 #define DSI_VPCCR_VPSIZE2_Pos (2U)
8804 #define DSI_VPCCR_VPSIZE2_Msk (0x1U << DSI_VPCCR_VPSIZE2_Pos) /*!< 0x00000004 */
8805 #define DSI_VPCCR_VPSIZE2 DSI_VPCCR_VPSIZE2_Msk
8806 #define DSI_VPCCR_VPSIZE3_Pos (3U)
8807 #define DSI_VPCCR_VPSIZE3_Msk (0x1U << DSI_VPCCR_VPSIZE3_Pos) /*!< 0x00000008 */
8808 #define DSI_VPCCR_VPSIZE3 DSI_VPCCR_VPSIZE3_Msk
8809 #define DSI_VPCCR_VPSIZE4_Pos (4U)
8810 #define DSI_VPCCR_VPSIZE4_Msk (0x1U << DSI_VPCCR_VPSIZE4_Pos) /*!< 0x00000010 */
8811 #define DSI_VPCCR_VPSIZE4 DSI_VPCCR_VPSIZE4_Msk
8812 #define DSI_VPCCR_VPSIZE5_Pos (5U)
8813 #define DSI_VPCCR_VPSIZE5_Msk (0x1U << DSI_VPCCR_VPSIZE5_Pos) /*!< 0x00000020 */
8814 #define DSI_VPCCR_VPSIZE5 DSI_VPCCR_VPSIZE5_Msk
8815 #define DSI_VPCCR_VPSIZE6_Pos (6U)
8816 #define DSI_VPCCR_VPSIZE6_Msk (0x1U << DSI_VPCCR_VPSIZE6_Pos) /*!< 0x00000040 */
8817 #define DSI_VPCCR_VPSIZE6 DSI_VPCCR_VPSIZE6_Msk
8818 #define DSI_VPCCR_VPSIZE7_Pos (7U)
8819 #define DSI_VPCCR_VPSIZE7_Msk (0x1U << DSI_VPCCR_VPSIZE7_Pos) /*!< 0x00000080 */
8820 #define DSI_VPCCR_VPSIZE7 DSI_VPCCR_VPSIZE7_Msk
8821 #define DSI_VPCCR_VPSIZE8_Pos (8U)
8822 #define DSI_VPCCR_VPSIZE8_Msk (0x1U << DSI_VPCCR_VPSIZE8_Pos) /*!< 0x00000100 */
8823 #define DSI_VPCCR_VPSIZE8 DSI_VPCCR_VPSIZE8_Msk
8824 #define DSI_VPCCR_VPSIZE9_Pos (9U)
8825 #define DSI_VPCCR_VPSIZE9_Msk (0x1U << DSI_VPCCR_VPSIZE9_Pos) /*!< 0x00000200 */
8826 #define DSI_VPCCR_VPSIZE9 DSI_VPCCR_VPSIZE9_Msk
8827 #define DSI_VPCCR_VPSIZE10_Pos (10U)
8828 #define DSI_VPCCR_VPSIZE10_Msk (0x1U << DSI_VPCCR_VPSIZE10_Pos) /*!< 0x00000400 */
8829 #define DSI_VPCCR_VPSIZE10 DSI_VPCCR_VPSIZE10_Msk
8830 #define DSI_VPCCR_VPSIZE11_Pos (11U)
8831 #define DSI_VPCCR_VPSIZE11_Msk (0x1U << DSI_VPCCR_VPSIZE11_Pos) /*!< 0x00000800 */
8832 #define DSI_VPCCR_VPSIZE11 DSI_VPCCR_VPSIZE11_Msk
8833 #define DSI_VPCCR_VPSIZE12_Pos (12U)
8834 #define DSI_VPCCR_VPSIZE12_Msk (0x1U << DSI_VPCCR_VPSIZE12_Pos) /*!< 0x00001000 */
8835 #define DSI_VPCCR_VPSIZE12 DSI_VPCCR_VPSIZE12_Msk
8836 #define DSI_VPCCR_VPSIZE13_Pos (13U)
8837 #define DSI_VPCCR_VPSIZE13_Msk (0x1U << DSI_VPCCR_VPSIZE13_Pos) /*!< 0x00002000 */
8838 #define DSI_VPCCR_VPSIZE13 DSI_VPCCR_VPSIZE13_Msk
8839
8840 /******************* Bit definition for DSI_VCCCR register **************/
8841 #define DSI_VCCCR_NUMC_Pos (0U)
8842 #define DSI_VCCCR_NUMC_Msk (0x1FFFU << DSI_VCCCR_NUMC_Pos) /*!< 0x00001FFF */
8843 #define DSI_VCCCR_NUMC DSI_VCCCR_NUMC_Msk /*!< Number of Chunks */
8844 #define DSI_VCCCR_NUMC0_Pos (0U)
8845 #define DSI_VCCCR_NUMC0_Msk (0x1U << DSI_VCCCR_NUMC0_Pos) /*!< 0x00000001 */
8846 #define DSI_VCCCR_NUMC0 DSI_VCCCR_NUMC0_Msk
8847 #define DSI_VCCCR_NUMC1_Pos (1U)
8848 #define DSI_VCCCR_NUMC1_Msk (0x1U << DSI_VCCCR_NUMC1_Pos) /*!< 0x00000002 */
8849 #define DSI_VCCCR_NUMC1 DSI_VCCCR_NUMC1_Msk
8850 #define DSI_VCCCR_NUMC2_Pos (2U)
8851 #define DSI_VCCCR_NUMC2_Msk (0x1U << DSI_VCCCR_NUMC2_Pos) /*!< 0x00000004 */
8852 #define DSI_VCCCR_NUMC2 DSI_VCCCR_NUMC2_Msk
8853 #define DSI_VCCCR_NUMC3_Pos (3U)
8854 #define DSI_VCCCR_NUMC3_Msk (0x1U << DSI_VCCCR_NUMC3_Pos) /*!< 0x00000008 */
8855 #define DSI_VCCCR_NUMC3 DSI_VCCCR_NUMC3_Msk
8856 #define DSI_VCCCR_NUMC4_Pos (4U)
8857 #define DSI_VCCCR_NUMC4_Msk (0x1U << DSI_VCCCR_NUMC4_Pos) /*!< 0x00000010 */
8858 #define DSI_VCCCR_NUMC4 DSI_VCCCR_NUMC4_Msk
8859 #define DSI_VCCCR_NUMC5_Pos (5U)
8860 #define DSI_VCCCR_NUMC5_Msk (0x1U << DSI_VCCCR_NUMC5_Pos) /*!< 0x00000020 */
8861 #define DSI_VCCCR_NUMC5 DSI_VCCCR_NUMC5_Msk
8862 #define DSI_VCCCR_NUMC6_Pos (6U)
8863 #define DSI_VCCCR_NUMC6_Msk (0x1U << DSI_VCCCR_NUMC6_Pos) /*!< 0x00000040 */
8864 #define DSI_VCCCR_NUMC6 DSI_VCCCR_NUMC6_Msk
8865 #define DSI_VCCCR_NUMC7_Pos (7U)
8866 #define DSI_VCCCR_NUMC7_Msk (0x1U << DSI_VCCCR_NUMC7_Pos) /*!< 0x00000080 */
8867 #define DSI_VCCCR_NUMC7 DSI_VCCCR_NUMC7_Msk
8868 #define DSI_VCCCR_NUMC8_Pos (8U)
8869 #define DSI_VCCCR_NUMC8_Msk (0x1U << DSI_VCCCR_NUMC8_Pos) /*!< 0x00000100 */
8870 #define DSI_VCCCR_NUMC8 DSI_VCCCR_NUMC8_Msk
8871 #define DSI_VCCCR_NUMC9_Pos (9U)
8872 #define DSI_VCCCR_NUMC9_Msk (0x1U << DSI_VCCCR_NUMC9_Pos) /*!< 0x00000200 */
8873 #define DSI_VCCCR_NUMC9 DSI_VCCCR_NUMC9_Msk
8874 #define DSI_VCCCR_NUMC10_Pos (10U)
8875 #define DSI_VCCCR_NUMC10_Msk (0x1U << DSI_VCCCR_NUMC10_Pos) /*!< 0x00000400 */
8876 #define DSI_VCCCR_NUMC10 DSI_VCCCR_NUMC10_Msk
8877 #define DSI_VCCCR_NUMC11_Pos (11U)
8878 #define DSI_VCCCR_NUMC11_Msk (0x1U << DSI_VCCCR_NUMC11_Pos) /*!< 0x00000800 */
8879 #define DSI_VCCCR_NUMC11 DSI_VCCCR_NUMC11_Msk
8880 #define DSI_VCCCR_NUMC12_Pos (12U)
8881 #define DSI_VCCCR_NUMC12_Msk (0x1U << DSI_VCCCR_NUMC12_Pos) /*!< 0x00001000 */
8882 #define DSI_VCCCR_NUMC12 DSI_VCCCR_NUMC12_Msk
8883
8884 /******************* Bit definition for DSI_VNPCCR register *************/
8885 #define DSI_VNPCCR_NPSIZE_Pos (0U)
8886 #define DSI_VNPCCR_NPSIZE_Msk (0x1FFFU << DSI_VNPCCR_NPSIZE_Pos) /*!< 0x00001FFF */
8887 #define DSI_VNPCCR_NPSIZE DSI_VNPCCR_NPSIZE_Msk /*!< Number of Chunks */
8888 #define DSI_VNPCCR_NPSIZE0_Pos (0U)
8889 #define DSI_VNPCCR_NPSIZE0_Msk (0x1U << DSI_VNPCCR_NPSIZE0_Pos) /*!< 0x00000001 */
8890 #define DSI_VNPCCR_NPSIZE0 DSI_VNPCCR_NPSIZE0_Msk
8891 #define DSI_VNPCCR_NPSIZE1_Pos (1U)
8892 #define DSI_VNPCCR_NPSIZE1_Msk (0x1U << DSI_VNPCCR_NPSIZE1_Pos) /*!< 0x00000002 */
8893 #define DSI_VNPCCR_NPSIZE1 DSI_VNPCCR_NPSIZE1_Msk
8894 #define DSI_VNPCCR_NPSIZE2_Pos (2U)
8895 #define DSI_VNPCCR_NPSIZE2_Msk (0x1U << DSI_VNPCCR_NPSIZE2_Pos) /*!< 0x00000004 */
8896 #define DSI_VNPCCR_NPSIZE2 DSI_VNPCCR_NPSIZE2_Msk
8897 #define DSI_VNPCCR_NPSIZE3_Pos (3U)
8898 #define DSI_VNPCCR_NPSIZE3_Msk (0x1U << DSI_VNPCCR_NPSIZE3_Pos) /*!< 0x00000008 */
8899 #define DSI_VNPCCR_NPSIZE3 DSI_VNPCCR_NPSIZE3_Msk
8900 #define DSI_VNPCCR_NPSIZE4_Pos (4U)
8901 #define DSI_VNPCCR_NPSIZE4_Msk (0x1U << DSI_VNPCCR_NPSIZE4_Pos) /*!< 0x00000010 */
8902 #define DSI_VNPCCR_NPSIZE4 DSI_VNPCCR_NPSIZE4_Msk
8903 #define DSI_VNPCCR_NPSIZE5_Pos (5U)
8904 #define DSI_VNPCCR_NPSIZE5_Msk (0x1U << DSI_VNPCCR_NPSIZE5_Pos) /*!< 0x00000020 */
8905 #define DSI_VNPCCR_NPSIZE5 DSI_VNPCCR_NPSIZE5_Msk
8906 #define DSI_VNPCCR_NPSIZE6_Pos (6U)
8907 #define DSI_VNPCCR_NPSIZE6_Msk (0x1U << DSI_VNPCCR_NPSIZE6_Pos) /*!< 0x00000040 */
8908 #define DSI_VNPCCR_NPSIZE6 DSI_VNPCCR_NPSIZE6_Msk
8909 #define DSI_VNPCCR_NPSIZE7_Pos (7U)
8910 #define DSI_VNPCCR_NPSIZE7_Msk (0x1U << DSI_VNPCCR_NPSIZE7_Pos) /*!< 0x00000080 */
8911 #define DSI_VNPCCR_NPSIZE7 DSI_VNPCCR_NPSIZE7_Msk
8912 #define DSI_VNPCCR_NPSIZE8_Pos (8U)
8913 #define DSI_VNPCCR_NPSIZE8_Msk (0x1U << DSI_VNPCCR_NPSIZE8_Pos) /*!< 0x00000100 */
8914 #define DSI_VNPCCR_NPSIZE8 DSI_VNPCCR_NPSIZE8_Msk
8915 #define DSI_VNPCCR_NPSIZE9_Pos (9U)
8916 #define DSI_VNPCCR_NPSIZE9_Msk (0x1U << DSI_VNPCCR_NPSIZE9_Pos) /*!< 0x00000200 */
8917 #define DSI_VNPCCR_NPSIZE9 DSI_VNPCCR_NPSIZE9_Msk
8918 #define DSI_VNPCCR_NPSIZE10_Pos (10U)
8919 #define DSI_VNPCCR_NPSIZE10_Msk (0x1U << DSI_VNPCCR_NPSIZE10_Pos) /*!< 0x00000400 */
8920 #define DSI_VNPCCR_NPSIZE10 DSI_VNPCCR_NPSIZE10_Msk
8921 #define DSI_VNPCCR_NPSIZE11_Pos (11U)
8922 #define DSI_VNPCCR_NPSIZE11_Msk (0x1U << DSI_VNPCCR_NPSIZE11_Pos) /*!< 0x00000800 */
8923 #define DSI_VNPCCR_NPSIZE11 DSI_VNPCCR_NPSIZE11_Msk
8924 #define DSI_VNPCCR_NPSIZE12_Pos (12U)
8925 #define DSI_VNPCCR_NPSIZE12_Msk (0x1U << DSI_VNPCCR_NPSIZE12_Pos) /*!< 0x00001000 */
8926 #define DSI_VNPCCR_NPSIZE12 DSI_VNPCCR_NPSIZE12_Msk
8927
8928 /******************* Bit definition for DSI_VHSACCR register ************/
8929 #define DSI_VHSACCR_HSA_Pos (0U)
8930 #define DSI_VHSACCR_HSA_Msk (0xFFFU << DSI_VHSACCR_HSA_Pos) /*!< 0x00000FFF */
8931 #define DSI_VHSACCR_HSA DSI_VHSACCR_HSA_Msk /*!< Horizontal Synchronism Active duration */
8932 #define DSI_VHSACCR_HSA0_Pos (0U)
8933 #define DSI_VHSACCR_HSA0_Msk (0x1U << DSI_VHSACCR_HSA0_Pos) /*!< 0x00000001 */
8934 #define DSI_VHSACCR_HSA0 DSI_VHSACCR_HSA0_Msk
8935 #define DSI_VHSACCR_HSA1_Pos (1U)
8936 #define DSI_VHSACCR_HSA1_Msk (0x1U << DSI_VHSACCR_HSA1_Pos) /*!< 0x00000002 */
8937 #define DSI_VHSACCR_HSA1 DSI_VHSACCR_HSA1_Msk
8938 #define DSI_VHSACCR_HSA2_Pos (2U)
8939 #define DSI_VHSACCR_HSA2_Msk (0x1U << DSI_VHSACCR_HSA2_Pos) /*!< 0x00000004 */
8940 #define DSI_VHSACCR_HSA2 DSI_VHSACCR_HSA2_Msk
8941 #define DSI_VHSACCR_HSA3_Pos (3U)
8942 #define DSI_VHSACCR_HSA3_Msk (0x1U << DSI_VHSACCR_HSA3_Pos) /*!< 0x00000008 */
8943 #define DSI_VHSACCR_HSA3 DSI_VHSACCR_HSA3_Msk
8944 #define DSI_VHSACCR_HSA4_Pos (4U)
8945 #define DSI_VHSACCR_HSA4_Msk (0x1U << DSI_VHSACCR_HSA4_Pos) /*!< 0x00000010 */
8946 #define DSI_VHSACCR_HSA4 DSI_VHSACCR_HSA4_Msk
8947 #define DSI_VHSACCR_HSA5_Pos (5U)
8948 #define DSI_VHSACCR_HSA5_Msk (0x1U << DSI_VHSACCR_HSA5_Pos) /*!< 0x00000020 */
8949 #define DSI_VHSACCR_HSA5 DSI_VHSACCR_HSA5_Msk
8950 #define DSI_VHSACCR_HSA6_Pos (6U)
8951 #define DSI_VHSACCR_HSA6_Msk (0x1U << DSI_VHSACCR_HSA6_Pos) /*!< 0x00000040 */
8952 #define DSI_VHSACCR_HSA6 DSI_VHSACCR_HSA6_Msk
8953 #define DSI_VHSACCR_HSA7_Pos (7U)
8954 #define DSI_VHSACCR_HSA7_Msk (0x1U << DSI_VHSACCR_HSA7_Pos) /*!< 0x00000080 */
8955 #define DSI_VHSACCR_HSA7 DSI_VHSACCR_HSA7_Msk
8956 #define DSI_VHSACCR_HSA8_Pos (8U)
8957 #define DSI_VHSACCR_HSA8_Msk (0x1U << DSI_VHSACCR_HSA8_Pos) /*!< 0x00000100 */
8958 #define DSI_VHSACCR_HSA8 DSI_VHSACCR_HSA8_Msk
8959 #define DSI_VHSACCR_HSA9_Pos (9U)
8960 #define DSI_VHSACCR_HSA9_Msk (0x1U << DSI_VHSACCR_HSA9_Pos) /*!< 0x00000200 */
8961 #define DSI_VHSACCR_HSA9 DSI_VHSACCR_HSA9_Msk
8962 #define DSI_VHSACCR_HSA10_Pos (10U)
8963 #define DSI_VHSACCR_HSA10_Msk (0x1U << DSI_VHSACCR_HSA10_Pos) /*!< 0x00000400 */
8964 #define DSI_VHSACCR_HSA10 DSI_VHSACCR_HSA10_Msk
8965 #define DSI_VHSACCR_HSA11_Pos (11U)
8966 #define DSI_VHSACCR_HSA11_Msk (0x1U << DSI_VHSACCR_HSA11_Pos) /*!< 0x00000800 */
8967 #define DSI_VHSACCR_HSA11 DSI_VHSACCR_HSA11_Msk
8968
8969 /******************* Bit definition for DSI_VHBPCCR register ************/
8970 #define DSI_VHBPCCR_HBP_Pos (0U)
8971 #define DSI_VHBPCCR_HBP_Msk (0xFFFU << DSI_VHBPCCR_HBP_Pos) /*!< 0x00000FFF */
8972 #define DSI_VHBPCCR_HBP DSI_VHBPCCR_HBP_Msk /*!< Horizontal Back-Porch duration */
8973 #define DSI_VHBPCCR_HBP0_Pos (0U)
8974 #define DSI_VHBPCCR_HBP0_Msk (0x1U << DSI_VHBPCCR_HBP0_Pos) /*!< 0x00000001 */
8975 #define DSI_VHBPCCR_HBP0 DSI_VHBPCCR_HBP0_Msk
8976 #define DSI_VHBPCCR_HBP1_Pos (1U)
8977 #define DSI_VHBPCCR_HBP1_Msk (0x1U << DSI_VHBPCCR_HBP1_Pos) /*!< 0x00000002 */
8978 #define DSI_VHBPCCR_HBP1 DSI_VHBPCCR_HBP1_Msk
8979 #define DSI_VHBPCCR_HBP2_Pos (2U)
8980 #define DSI_VHBPCCR_HBP2_Msk (0x1U << DSI_VHBPCCR_HBP2_Pos) /*!< 0x00000004 */
8981 #define DSI_VHBPCCR_HBP2 DSI_VHBPCCR_HBP2_Msk
8982 #define DSI_VHBPCCR_HBP3_Pos (3U)
8983 #define DSI_VHBPCCR_HBP3_Msk (0x1U << DSI_VHBPCCR_HBP3_Pos) /*!< 0x00000008 */
8984 #define DSI_VHBPCCR_HBP3 DSI_VHBPCCR_HBP3_Msk
8985 #define DSI_VHBPCCR_HBP4_Pos (4U)
8986 #define DSI_VHBPCCR_HBP4_Msk (0x1U << DSI_VHBPCCR_HBP4_Pos) /*!< 0x00000010 */
8987 #define DSI_VHBPCCR_HBP4 DSI_VHBPCCR_HBP4_Msk
8988 #define DSI_VHBPCCR_HBP5_Pos (5U)
8989 #define DSI_VHBPCCR_HBP5_Msk (0x1U << DSI_VHBPCCR_HBP5_Pos) /*!< 0x00000020 */
8990 #define DSI_VHBPCCR_HBP5 DSI_VHBPCCR_HBP5_Msk
8991 #define DSI_VHBPCCR_HBP6_Pos (6U)
8992 #define DSI_VHBPCCR_HBP6_Msk (0x1U << DSI_VHBPCCR_HBP6_Pos) /*!< 0x00000040 */
8993 #define DSI_VHBPCCR_HBP6 DSI_VHBPCCR_HBP6_Msk
8994 #define DSI_VHBPCCR_HBP7_Pos (7U)
8995 #define DSI_VHBPCCR_HBP7_Msk (0x1U << DSI_VHBPCCR_HBP7_Pos) /*!< 0x00000080 */
8996 #define DSI_VHBPCCR_HBP7 DSI_VHBPCCR_HBP7_Msk
8997 #define DSI_VHBPCCR_HBP8_Pos (8U)
8998 #define DSI_VHBPCCR_HBP8_Msk (0x1U << DSI_VHBPCCR_HBP8_Pos) /*!< 0x00000100 */
8999 #define DSI_VHBPCCR_HBP8 DSI_VHBPCCR_HBP8_Msk
9000 #define DSI_VHBPCCR_HBP9_Pos (9U)
9001 #define DSI_VHBPCCR_HBP9_Msk (0x1U << DSI_VHBPCCR_HBP9_Pos) /*!< 0x00000200 */
9002 #define DSI_VHBPCCR_HBP9 DSI_VHBPCCR_HBP9_Msk
9003 #define DSI_VHBPCCR_HBP10_Pos (10U)
9004 #define DSI_VHBPCCR_HBP10_Msk (0x1U << DSI_VHBPCCR_HBP10_Pos) /*!< 0x00000400 */
9005 #define DSI_VHBPCCR_HBP10 DSI_VHBPCCR_HBP10_Msk
9006 #define DSI_VHBPCCR_HBP11_Pos (11U)
9007 #define DSI_VHBPCCR_HBP11_Msk (0x1U << DSI_VHBPCCR_HBP11_Pos) /*!< 0x00000800 */
9008 #define DSI_VHBPCCR_HBP11 DSI_VHBPCCR_HBP11_Msk
9009
9010 /******************* Bit definition for DSI_VLCCR register **************/
9011 #define DSI_VLCCR_HLINE_Pos (0U)
9012 #define DSI_VLCCR_HLINE_Msk (0x7FFFU << DSI_VLCCR_HLINE_Pos) /*!< 0x00007FFF */
9013 #define DSI_VLCCR_HLINE DSI_VLCCR_HLINE_Msk /*!< Horizontal Line duration */
9014 #define DSI_VLCCR_HLINE0_Pos (0U)
9015 #define DSI_VLCCR_HLINE0_Msk (0x1U << DSI_VLCCR_HLINE0_Pos) /*!< 0x00000001 */
9016 #define DSI_VLCCR_HLINE0 DSI_VLCCR_HLINE0_Msk
9017 #define DSI_VLCCR_HLINE1_Pos (1U)
9018 #define DSI_VLCCR_HLINE1_Msk (0x1U << DSI_VLCCR_HLINE1_Pos) /*!< 0x00000002 */
9019 #define DSI_VLCCR_HLINE1 DSI_VLCCR_HLINE1_Msk
9020 #define DSI_VLCCR_HLINE2_Pos (2U)
9021 #define DSI_VLCCR_HLINE2_Msk (0x1U << DSI_VLCCR_HLINE2_Pos) /*!< 0x00000004 */
9022 #define DSI_VLCCR_HLINE2 DSI_VLCCR_HLINE2_Msk
9023 #define DSI_VLCCR_HLINE3_Pos (3U)
9024 #define DSI_VLCCR_HLINE3_Msk (0x1U << DSI_VLCCR_HLINE3_Pos) /*!< 0x00000008 */
9025 #define DSI_VLCCR_HLINE3 DSI_VLCCR_HLINE3_Msk
9026 #define DSI_VLCCR_HLINE4_Pos (4U)
9027 #define DSI_VLCCR_HLINE4_Msk (0x1U << DSI_VLCCR_HLINE4_Pos) /*!< 0x00000010 */
9028 #define DSI_VLCCR_HLINE4 DSI_VLCCR_HLINE4_Msk
9029 #define DSI_VLCCR_HLINE5_Pos (5U)
9030 #define DSI_VLCCR_HLINE5_Msk (0x1U << DSI_VLCCR_HLINE5_Pos) /*!< 0x00000020 */
9031 #define DSI_VLCCR_HLINE5 DSI_VLCCR_HLINE5_Msk
9032 #define DSI_VLCCR_HLINE6_Pos (6U)
9033 #define DSI_VLCCR_HLINE6_Msk (0x1U << DSI_VLCCR_HLINE6_Pos) /*!< 0x00000040 */
9034 #define DSI_VLCCR_HLINE6 DSI_VLCCR_HLINE6_Msk
9035 #define DSI_VLCCR_HLINE7_Pos (7U)
9036 #define DSI_VLCCR_HLINE7_Msk (0x1U << DSI_VLCCR_HLINE7_Pos) /*!< 0x00000080 */
9037 #define DSI_VLCCR_HLINE7 DSI_VLCCR_HLINE7_Msk
9038 #define DSI_VLCCR_HLINE8_Pos (8U)
9039 #define DSI_VLCCR_HLINE8_Msk (0x1U << DSI_VLCCR_HLINE8_Pos) /*!< 0x00000100 */
9040 #define DSI_VLCCR_HLINE8 DSI_VLCCR_HLINE8_Msk
9041 #define DSI_VLCCR_HLINE9_Pos (9U)
9042 #define DSI_VLCCR_HLINE9_Msk (0x1U << DSI_VLCCR_HLINE9_Pos) /*!< 0x00000200 */
9043 #define DSI_VLCCR_HLINE9 DSI_VLCCR_HLINE9_Msk
9044 #define DSI_VLCCR_HLINE10_Pos (10U)
9045 #define DSI_VLCCR_HLINE10_Msk (0x1U << DSI_VLCCR_HLINE10_Pos) /*!< 0x00000400 */
9046 #define DSI_VLCCR_HLINE10 DSI_VLCCR_HLINE10_Msk
9047 #define DSI_VLCCR_HLINE11_Pos (11U)
9048 #define DSI_VLCCR_HLINE11_Msk (0x1U << DSI_VLCCR_HLINE11_Pos) /*!< 0x00000800 */
9049 #define DSI_VLCCR_HLINE11 DSI_VLCCR_HLINE11_Msk
9050 #define DSI_VLCCR_HLINE12_Pos (12U)
9051 #define DSI_VLCCR_HLINE12_Msk (0x1U << DSI_VLCCR_HLINE12_Pos) /*!< 0x00001000 */
9052 #define DSI_VLCCR_HLINE12 DSI_VLCCR_HLINE12_Msk
9053 #define DSI_VLCCR_HLINE13_Pos (13U)
9054 #define DSI_VLCCR_HLINE13_Msk (0x1U << DSI_VLCCR_HLINE13_Pos) /*!< 0x00002000 */
9055 #define DSI_VLCCR_HLINE13 DSI_VLCCR_HLINE13_Msk
9056 #define DSI_VLCCR_HLINE14_Pos (14U)
9057 #define DSI_VLCCR_HLINE14_Msk (0x1U << DSI_VLCCR_HLINE14_Pos) /*!< 0x00004000 */
9058 #define DSI_VLCCR_HLINE14 DSI_VLCCR_HLINE14_Msk
9059
9060 /******************* Bit definition for DSI_VVSACCR register ***************/
9061 #define DSI_VVSACCR_VSA_Pos (0U)
9062 #define DSI_VVSACCR_VSA_Msk (0x3FFU << DSI_VVSACCR_VSA_Pos) /*!< 0x000003FF */
9063 #define DSI_VVSACCR_VSA DSI_VVSACCR_VSA_Msk /*!< Vertical Synchronism Active duration */
9064 #define DSI_VVSACCR_VSA0_Pos (0U)
9065 #define DSI_VVSACCR_VSA0_Msk (0x1U << DSI_VVSACCR_VSA0_Pos) /*!< 0x00000001 */
9066 #define DSI_VVSACCR_VSA0 DSI_VVSACCR_VSA0_Msk
9067 #define DSI_VVSACCR_VSA1_Pos (1U)
9068 #define DSI_VVSACCR_VSA1_Msk (0x1U << DSI_VVSACCR_VSA1_Pos) /*!< 0x00000002 */
9069 #define DSI_VVSACCR_VSA1 DSI_VVSACCR_VSA1_Msk
9070 #define DSI_VVSACCR_VSA2_Pos (2U)
9071 #define DSI_VVSACCR_VSA2_Msk (0x1U << DSI_VVSACCR_VSA2_Pos) /*!< 0x00000004 */
9072 #define DSI_VVSACCR_VSA2 DSI_VVSACCR_VSA2_Msk
9073 #define DSI_VVSACCR_VSA3_Pos (3U)
9074 #define DSI_VVSACCR_VSA3_Msk (0x1U << DSI_VVSACCR_VSA3_Pos) /*!< 0x00000008 */
9075 #define DSI_VVSACCR_VSA3 DSI_VVSACCR_VSA3_Msk
9076 #define DSI_VVSACCR_VSA4_Pos (4U)
9077 #define DSI_VVSACCR_VSA4_Msk (0x1U << DSI_VVSACCR_VSA4_Pos) /*!< 0x00000010 */
9078 #define DSI_VVSACCR_VSA4 DSI_VVSACCR_VSA4_Msk
9079 #define DSI_VVSACCR_VSA5_Pos (5U)
9080 #define DSI_VVSACCR_VSA5_Msk (0x1U << DSI_VVSACCR_VSA5_Pos) /*!< 0x00000020 */
9081 #define DSI_VVSACCR_VSA5 DSI_VVSACCR_VSA5_Msk
9082 #define DSI_VVSACCR_VSA6_Pos (6U)
9083 #define DSI_VVSACCR_VSA6_Msk (0x1U << DSI_VVSACCR_VSA6_Pos) /*!< 0x00000040 */
9084 #define DSI_VVSACCR_VSA6 DSI_VVSACCR_VSA6_Msk
9085 #define DSI_VVSACCR_VSA7_Pos (7U)
9086 #define DSI_VVSACCR_VSA7_Msk (0x1U << DSI_VVSACCR_VSA7_Pos) /*!< 0x00000080 */
9087 #define DSI_VVSACCR_VSA7 DSI_VVSACCR_VSA7_Msk
9088 #define DSI_VVSACCR_VSA8_Pos (8U)
9089 #define DSI_VVSACCR_VSA8_Msk (0x1U << DSI_VVSACCR_VSA8_Pos) /*!< 0x00000100 */
9090 #define DSI_VVSACCR_VSA8 DSI_VVSACCR_VSA8_Msk
9091 #define DSI_VVSACCR_VSA9_Pos (9U)
9092 #define DSI_VVSACCR_VSA9_Msk (0x1U << DSI_VVSACCR_VSA9_Pos) /*!< 0x00000200 */
9093 #define DSI_VVSACCR_VSA9 DSI_VVSACCR_VSA9_Msk
9094
9095 /******************* Bit definition for DSI_VVBPCCR register ************/
9096 #define DSI_VVBPCCR_VBP_Pos (0U)
9097 #define DSI_VVBPCCR_VBP_Msk (0x3FFU << DSI_VVBPCCR_VBP_Pos) /*!< 0x000003FF */
9098 #define DSI_VVBPCCR_VBP DSI_VVBPCCR_VBP_Msk /*!< Vertical Back-Porch duration */
9099 #define DSI_VVBPCCR_VBP0_Pos (0U)
9100 #define DSI_VVBPCCR_VBP0_Msk (0x1U << DSI_VVBPCCR_VBP0_Pos) /*!< 0x00000001 */
9101 #define DSI_VVBPCCR_VBP0 DSI_VVBPCCR_VBP0_Msk
9102 #define DSI_VVBPCCR_VBP1_Pos (1U)
9103 #define DSI_VVBPCCR_VBP1_Msk (0x1U << DSI_VVBPCCR_VBP1_Pos) /*!< 0x00000002 */
9104 #define DSI_VVBPCCR_VBP1 DSI_VVBPCCR_VBP1_Msk
9105 #define DSI_VVBPCCR_VBP2_Pos (2U)
9106 #define DSI_VVBPCCR_VBP2_Msk (0x1U << DSI_VVBPCCR_VBP2_Pos) /*!< 0x00000004 */
9107 #define DSI_VVBPCCR_VBP2 DSI_VVBPCCR_VBP2_Msk
9108 #define DSI_VVBPCCR_VBP3_Pos (3U)
9109 #define DSI_VVBPCCR_VBP3_Msk (0x1U << DSI_VVBPCCR_VBP3_Pos) /*!< 0x00000008 */
9110 #define DSI_VVBPCCR_VBP3 DSI_VVBPCCR_VBP3_Msk
9111 #define DSI_VVBPCCR_VBP4_Pos (4U)
9112 #define DSI_VVBPCCR_VBP4_Msk (0x1U << DSI_VVBPCCR_VBP4_Pos) /*!< 0x00000010 */
9113 #define DSI_VVBPCCR_VBP4 DSI_VVBPCCR_VBP4_Msk
9114 #define DSI_VVBPCCR_VBP5_Pos (5U)
9115 #define DSI_VVBPCCR_VBP5_Msk (0x1U << DSI_VVBPCCR_VBP5_Pos) /*!< 0x00000020 */
9116 #define DSI_VVBPCCR_VBP5 DSI_VVBPCCR_VBP5_Msk
9117 #define DSI_VVBPCCR_VBP6_Pos (6U)
9118 #define DSI_VVBPCCR_VBP6_Msk (0x1U << DSI_VVBPCCR_VBP6_Pos) /*!< 0x00000040 */
9119 #define DSI_VVBPCCR_VBP6 DSI_VVBPCCR_VBP6_Msk
9120 #define DSI_VVBPCCR_VBP7_Pos (7U)
9121 #define DSI_VVBPCCR_VBP7_Msk (0x1U << DSI_VVBPCCR_VBP7_Pos) /*!< 0x00000080 */
9122 #define DSI_VVBPCCR_VBP7 DSI_VVBPCCR_VBP7_Msk
9123 #define DSI_VVBPCCR_VBP8_Pos (8U)
9124 #define DSI_VVBPCCR_VBP8_Msk (0x1U << DSI_VVBPCCR_VBP8_Pos) /*!< 0x00000100 */
9125 #define DSI_VVBPCCR_VBP8 DSI_VVBPCCR_VBP8_Msk
9126 #define DSI_VVBPCCR_VBP9_Pos (9U)
9127 #define DSI_VVBPCCR_VBP9_Msk (0x1U << DSI_VVBPCCR_VBP9_Pos) /*!< 0x00000200 */
9128 #define DSI_VVBPCCR_VBP9 DSI_VVBPCCR_VBP9_Msk
9129
9130 /******************* Bit definition for DSI_VVFPCCR register ************/
9131 #define DSI_VVFPCCR_VFP_Pos (0U)
9132 #define DSI_VVFPCCR_VFP_Msk (0x3FFU << DSI_VVFPCCR_VFP_Pos) /*!< 0x000003FF */
9133 #define DSI_VVFPCCR_VFP DSI_VVFPCCR_VFP_Msk /*!< Vertical Front-Porch duration */
9134 #define DSI_VVFPCCR_VFP0_Pos (0U)
9135 #define DSI_VVFPCCR_VFP0_Msk (0x1U << DSI_VVFPCCR_VFP0_Pos) /*!< 0x00000001 */
9136 #define DSI_VVFPCCR_VFP0 DSI_VVFPCCR_VFP0_Msk
9137 #define DSI_VVFPCCR_VFP1_Pos (1U)
9138 #define DSI_VVFPCCR_VFP1_Msk (0x1U << DSI_VVFPCCR_VFP1_Pos) /*!< 0x00000002 */
9139 #define DSI_VVFPCCR_VFP1 DSI_VVFPCCR_VFP1_Msk
9140 #define DSI_VVFPCCR_VFP2_Pos (2U)
9141 #define DSI_VVFPCCR_VFP2_Msk (0x1U << DSI_VVFPCCR_VFP2_Pos) /*!< 0x00000004 */
9142 #define DSI_VVFPCCR_VFP2 DSI_VVFPCCR_VFP2_Msk
9143 #define DSI_VVFPCCR_VFP3_Pos (3U)
9144 #define DSI_VVFPCCR_VFP3_Msk (0x1U << DSI_VVFPCCR_VFP3_Pos) /*!< 0x00000008 */
9145 #define DSI_VVFPCCR_VFP3 DSI_VVFPCCR_VFP3_Msk
9146 #define DSI_VVFPCCR_VFP4_Pos (4U)
9147 #define DSI_VVFPCCR_VFP4_Msk (0x1U << DSI_VVFPCCR_VFP4_Pos) /*!< 0x00000010 */
9148 #define DSI_VVFPCCR_VFP4 DSI_VVFPCCR_VFP4_Msk
9149 #define DSI_VVFPCCR_VFP5_Pos (5U)
9150 #define DSI_VVFPCCR_VFP5_Msk (0x1U << DSI_VVFPCCR_VFP5_Pos) /*!< 0x00000020 */
9151 #define DSI_VVFPCCR_VFP5 DSI_VVFPCCR_VFP5_Msk
9152 #define DSI_VVFPCCR_VFP6_Pos (6U)
9153 #define DSI_VVFPCCR_VFP6_Msk (0x1U << DSI_VVFPCCR_VFP6_Pos) /*!< 0x00000040 */
9154 #define DSI_VVFPCCR_VFP6 DSI_VVFPCCR_VFP6_Msk
9155 #define DSI_VVFPCCR_VFP7_Pos (7U)
9156 #define DSI_VVFPCCR_VFP7_Msk (0x1U << DSI_VVFPCCR_VFP7_Pos) /*!< 0x00000080 */
9157 #define DSI_VVFPCCR_VFP7 DSI_VVFPCCR_VFP7_Msk
9158 #define DSI_VVFPCCR_VFP8_Pos (8U)
9159 #define DSI_VVFPCCR_VFP8_Msk (0x1U << DSI_VVFPCCR_VFP8_Pos) /*!< 0x00000100 */
9160 #define DSI_VVFPCCR_VFP8 DSI_VVFPCCR_VFP8_Msk
9161 #define DSI_VVFPCCR_VFP9_Pos (9U)
9162 #define DSI_VVFPCCR_VFP9_Msk (0x1U << DSI_VVFPCCR_VFP9_Pos) /*!< 0x00000200 */
9163 #define DSI_VVFPCCR_VFP9 DSI_VVFPCCR_VFP9_Msk
9164
9165 /******************* Bit definition for DSI_VVACCR register *************/
9166 #define DSI_VVACCR_VA_Pos (0U)
9167 #define DSI_VVACCR_VA_Msk (0x3FFFU << DSI_VVACCR_VA_Pos) /*!< 0x00003FFF */
9168 #define DSI_VVACCR_VA DSI_VVACCR_VA_Msk /*!< Vertical Active duration */
9169 #define DSI_VVACCR_VA0_Pos (0U)
9170 #define DSI_VVACCR_VA0_Msk (0x1U << DSI_VVACCR_VA0_Pos) /*!< 0x00000001 */
9171 #define DSI_VVACCR_VA0 DSI_VVACCR_VA0_Msk
9172 #define DSI_VVACCR_VA1_Pos (1U)
9173 #define DSI_VVACCR_VA1_Msk (0x1U << DSI_VVACCR_VA1_Pos) /*!< 0x00000002 */
9174 #define DSI_VVACCR_VA1 DSI_VVACCR_VA1_Msk
9175 #define DSI_VVACCR_VA2_Pos (2U)
9176 #define DSI_VVACCR_VA2_Msk (0x1U << DSI_VVACCR_VA2_Pos) /*!< 0x00000004 */
9177 #define DSI_VVACCR_VA2 DSI_VVACCR_VA2_Msk
9178 #define DSI_VVACCR_VA3_Pos (3U)
9179 #define DSI_VVACCR_VA3_Msk (0x1U << DSI_VVACCR_VA3_Pos) /*!< 0x00000008 */
9180 #define DSI_VVACCR_VA3 DSI_VVACCR_VA3_Msk
9181 #define DSI_VVACCR_VA4_Pos (4U)
9182 #define DSI_VVACCR_VA4_Msk (0x1U << DSI_VVACCR_VA4_Pos) /*!< 0x00000010 */
9183 #define DSI_VVACCR_VA4 DSI_VVACCR_VA4_Msk
9184 #define DSI_VVACCR_VA5_Pos (5U)
9185 #define DSI_VVACCR_VA5_Msk (0x1U << DSI_VVACCR_VA5_Pos) /*!< 0x00000020 */
9186 #define DSI_VVACCR_VA5 DSI_VVACCR_VA5_Msk
9187 #define DSI_VVACCR_VA6_Pos (6U)
9188 #define DSI_VVACCR_VA6_Msk (0x1U << DSI_VVACCR_VA6_Pos) /*!< 0x00000040 */
9189 #define DSI_VVACCR_VA6 DSI_VVACCR_VA6_Msk
9190 #define DSI_VVACCR_VA7_Pos (7U)
9191 #define DSI_VVACCR_VA7_Msk (0x1U << DSI_VVACCR_VA7_Pos) /*!< 0x00000080 */
9192 #define DSI_VVACCR_VA7 DSI_VVACCR_VA7_Msk
9193 #define DSI_VVACCR_VA8_Pos (8U)
9194 #define DSI_VVACCR_VA8_Msk (0x1U << DSI_VVACCR_VA8_Pos) /*!< 0x00000100 */
9195 #define DSI_VVACCR_VA8 DSI_VVACCR_VA8_Msk
9196 #define DSI_VVACCR_VA9_Pos (9U)
9197 #define DSI_VVACCR_VA9_Msk (0x1U << DSI_VVACCR_VA9_Pos) /*!< 0x00000200 */
9198 #define DSI_VVACCR_VA9 DSI_VVACCR_VA9_Msk
9199 #define DSI_VVACCR_VA10_Pos (10U)
9200 #define DSI_VVACCR_VA10_Msk (0x1U << DSI_VVACCR_VA10_Pos) /*!< 0x00000400 */
9201 #define DSI_VVACCR_VA10 DSI_VVACCR_VA10_Msk
9202 #define DSI_VVACCR_VA11_Pos (11U)
9203 #define DSI_VVACCR_VA11_Msk (0x1U << DSI_VVACCR_VA11_Pos) /*!< 0x00000800 */
9204 #define DSI_VVACCR_VA11 DSI_VVACCR_VA11_Msk
9205 #define DSI_VVACCR_VA12_Pos (12U)
9206 #define DSI_VVACCR_VA12_Msk (0x1U << DSI_VVACCR_VA12_Pos) /*!< 0x00001000 */
9207 #define DSI_VVACCR_VA12 DSI_VVACCR_VA12_Msk
9208 #define DSI_VVACCR_VA13_Pos (13U)
9209 #define DSI_VVACCR_VA13_Msk (0x1U << DSI_VVACCR_VA13_Pos) /*!< 0x00002000 */
9210 #define DSI_VVACCR_VA13 DSI_VVACCR_VA13_Msk
9211
9212 /******************* Bit definition for DSI_TDCCR register **************/
9213 #define DSI_TDCCR_3DM 0x00000003U /*!< 3D Mode */
9214 #define DSI_TDCCR_3DM0 0x00000001U
9215 #define DSI_TDCCR_3DM1 0x00000002U
9216
9217 #define DSI_TDCCR_3DF 0x0000000CU /*!< 3D Format */
9218 #define DSI_TDCCR_3DF0 0x00000004U
9219 #define DSI_TDCCR_3DF1 0x00000008U
9220
9221 #define DSI_TDCCR_SVS_Pos (4U)
9222 #define DSI_TDCCR_SVS_Msk (0x1U << DSI_TDCCR_SVS_Pos) /*!< 0x00000010 */
9223 #define DSI_TDCCR_SVS DSI_TDCCR_SVS_Msk /*!< Second VSYNC */
9224 #define DSI_TDCCR_RF_Pos (5U)
9225 #define DSI_TDCCR_RF_Msk (0x1U << DSI_TDCCR_RF_Pos) /*!< 0x00000020 */
9226 #define DSI_TDCCR_RF DSI_TDCCR_RF_Msk /*!< Right First */
9227 #define DSI_TDCCR_S3DC_Pos (16U)
9228 #define DSI_TDCCR_S3DC_Msk (0x1U << DSI_TDCCR_S3DC_Pos) /*!< 0x00010000 */
9229 #define DSI_TDCCR_S3DC DSI_TDCCR_S3DC_Msk /*!< Send 3D Control */
9230
9231 /******************* Bit definition for DSI_WCFGR register ***************/
9232 #define DSI_WCFGR_DSIM_Pos (0U)
9233 #define DSI_WCFGR_DSIM_Msk (0x1U << DSI_WCFGR_DSIM_Pos) /*!< 0x00000001 */
9234 #define DSI_WCFGR_DSIM DSI_WCFGR_DSIM_Msk /*!< DSI Mode */
9235 #define DSI_WCFGR_COLMUX_Pos (1U)
9236 #define DSI_WCFGR_COLMUX_Msk (0x7U << DSI_WCFGR_COLMUX_Pos) /*!< 0x0000000E */
9237 #define DSI_WCFGR_COLMUX DSI_WCFGR_COLMUX_Msk /*!< Color Multiplexing */
9238 #define DSI_WCFGR_COLMUX0_Pos (1U)
9239 #define DSI_WCFGR_COLMUX0_Msk (0x1U << DSI_WCFGR_COLMUX0_Pos) /*!< 0x00000002 */
9240 #define DSI_WCFGR_COLMUX0 DSI_WCFGR_COLMUX0_Msk
9241 #define DSI_WCFGR_COLMUX1_Pos (2U)
9242 #define DSI_WCFGR_COLMUX1_Msk (0x1U << DSI_WCFGR_COLMUX1_Pos) /*!< 0x00000004 */
9243 #define DSI_WCFGR_COLMUX1 DSI_WCFGR_COLMUX1_Msk
9244 #define DSI_WCFGR_COLMUX2_Pos (3U)
9245 #define DSI_WCFGR_COLMUX2_Msk (0x1U << DSI_WCFGR_COLMUX2_Pos) /*!< 0x00000008 */
9246 #define DSI_WCFGR_COLMUX2 DSI_WCFGR_COLMUX2_Msk
9247
9248 #define DSI_WCFGR_TESRC_Pos (4U)
9249 #define DSI_WCFGR_TESRC_Msk (0x1U << DSI_WCFGR_TESRC_Pos) /*!< 0x00000010 */
9250 #define DSI_WCFGR_TESRC DSI_WCFGR_TESRC_Msk /*!< Tearing Effect Source */
9251 #define DSI_WCFGR_TEPOL_Pos (5U)
9252 #define DSI_WCFGR_TEPOL_Msk (0x1U << DSI_WCFGR_TEPOL_Pos) /*!< 0x00000020 */
9253 #define DSI_WCFGR_TEPOL DSI_WCFGR_TEPOL_Msk /*!< Tearing Effect Polarity */
9254 #define DSI_WCFGR_AR_Pos (6U)
9255 #define DSI_WCFGR_AR_Msk (0x1U << DSI_WCFGR_AR_Pos) /*!< 0x00000040 */
9256 #define DSI_WCFGR_AR DSI_WCFGR_AR_Msk /*!< Automatic Refresh */
9257 #define DSI_WCFGR_VSPOL_Pos (7U)
9258 #define DSI_WCFGR_VSPOL_Msk (0x1U << DSI_WCFGR_VSPOL_Pos) /*!< 0x00000080 */
9259 #define DSI_WCFGR_VSPOL DSI_WCFGR_VSPOL_Msk /*!< VSync Polarity */
9260
9261 /******************* Bit definition for DSI_WCR register *****************/
9262 #define DSI_WCR_COLM_Pos (0U)
9263 #define DSI_WCR_COLM_Msk (0x1U << DSI_WCR_COLM_Pos) /*!< 0x00000001 */
9264 #define DSI_WCR_COLM DSI_WCR_COLM_Msk /*!< Color Mode */
9265 #define DSI_WCR_SHTDN_Pos (1U)
9266 #define DSI_WCR_SHTDN_Msk (0x1U << DSI_WCR_SHTDN_Pos) /*!< 0x00000002 */
9267 #define DSI_WCR_SHTDN DSI_WCR_SHTDN_Msk /*!< Shutdown */
9268 #define DSI_WCR_LTDCEN_Pos (2U)
9269 #define DSI_WCR_LTDCEN_Msk (0x1U << DSI_WCR_LTDCEN_Pos) /*!< 0x00000004 */
9270 #define DSI_WCR_LTDCEN DSI_WCR_LTDCEN_Msk /*!< LTDC Enable */
9271 #define DSI_WCR_DSIEN_Pos (3U)
9272 #define DSI_WCR_DSIEN_Msk (0x1U << DSI_WCR_DSIEN_Pos) /*!< 0x00000008 */
9273 #define DSI_WCR_DSIEN DSI_WCR_DSIEN_Msk /*!< DSI Enable */
9274
9275 /******************* Bit definition for DSI_WIER register ****************/
9276 #define DSI_WIER_TEIE_Pos (0U)
9277 #define DSI_WIER_TEIE_Msk (0x1U << DSI_WIER_TEIE_Pos) /*!< 0x00000001 */
9278 #define DSI_WIER_TEIE DSI_WIER_TEIE_Msk /*!< Tearing Effect Interrupt Enable */
9279 #define DSI_WIER_ERIE_Pos (1U)
9280 #define DSI_WIER_ERIE_Msk (0x1U << DSI_WIER_ERIE_Pos) /*!< 0x00000002 */
9281 #define DSI_WIER_ERIE DSI_WIER_ERIE_Msk /*!< End of Refresh Interrupt Enable */
9282 #define DSI_WIER_PLLLIE_Pos (9U)
9283 #define DSI_WIER_PLLLIE_Msk (0x1U << DSI_WIER_PLLLIE_Pos) /*!< 0x00000200 */
9284 #define DSI_WIER_PLLLIE DSI_WIER_PLLLIE_Msk /*!< PLL Lock Interrupt Enable */
9285 #define DSI_WIER_PLLUIE_Pos (10U)
9286 #define DSI_WIER_PLLUIE_Msk (0x1U << DSI_WIER_PLLUIE_Pos) /*!< 0x00000400 */
9287 #define DSI_WIER_PLLUIE DSI_WIER_PLLUIE_Msk /*!< PLL Unlock Interrupt Enable */
9288 #define DSI_WIER_RRIE_Pos (13U)
9289 #define DSI_WIER_RRIE_Msk (0x1U << DSI_WIER_RRIE_Pos) /*!< 0x00002000 */
9290 #define DSI_WIER_RRIE DSI_WIER_RRIE_Msk /*!< Regulator Ready Interrupt Enable */
9291
9292 /******************* Bit definition for DSI_WISR register ****************/
9293 #define DSI_WISR_TEIF_Pos (0U)
9294 #define DSI_WISR_TEIF_Msk (0x1U << DSI_WISR_TEIF_Pos) /*!< 0x00000001 */
9295 #define DSI_WISR_TEIF DSI_WISR_TEIF_Msk /*!< Tearing Effect Interrupt Flag */
9296 #define DSI_WISR_ERIF_Pos (1U)
9297 #define DSI_WISR_ERIF_Msk (0x1U << DSI_WISR_ERIF_Pos) /*!< 0x00000002 */
9298 #define DSI_WISR_ERIF DSI_WISR_ERIF_Msk /*!< End of Refresh Interrupt Flag */
9299 #define DSI_WISR_BUSY_Pos (2U)
9300 #define DSI_WISR_BUSY_Msk (0x1U << DSI_WISR_BUSY_Pos) /*!< 0x00000004 */
9301 #define DSI_WISR_BUSY DSI_WISR_BUSY_Msk /*!< Busy Flag */
9302 #define DSI_WISR_PLLLS_Pos (8U)
9303 #define DSI_WISR_PLLLS_Msk (0x1U << DSI_WISR_PLLLS_Pos) /*!< 0x00000100 */
9304 #define DSI_WISR_PLLLS DSI_WISR_PLLLS_Msk /*!< PLL Lock Status */
9305 #define DSI_WISR_PLLLIF_Pos (9U)
9306 #define DSI_WISR_PLLLIF_Msk (0x1U << DSI_WISR_PLLLIF_Pos) /*!< 0x00000200 */
9307 #define DSI_WISR_PLLLIF DSI_WISR_PLLLIF_Msk /*!< PLL Lock Interrupt Flag */
9308 #define DSI_WISR_PLLUIF_Pos (10U)
9309 #define DSI_WISR_PLLUIF_Msk (0x1U << DSI_WISR_PLLUIF_Pos) /*!< 0x00000400 */
9310 #define DSI_WISR_PLLUIF DSI_WISR_PLLUIF_Msk /*!< PLL Unlock Interrupt Flag */
9311 #define DSI_WISR_RRS_Pos (12U)
9312 #define DSI_WISR_RRS_Msk (0x1U << DSI_WISR_RRS_Pos) /*!< 0x00001000 */
9313 #define DSI_WISR_RRS DSI_WISR_RRS_Msk /*!< Regulator Ready Flag */
9314 #define DSI_WISR_RRIF_Pos (13U)
9315 #define DSI_WISR_RRIF_Msk (0x1U << DSI_WISR_RRIF_Pos) /*!< 0x00002000 */
9316 #define DSI_WISR_RRIF DSI_WISR_RRIF_Msk /*!< Regulator Ready Interrupt Flag */
9317
9318 /******************* Bit definition for DSI_WIFCR register ***************/
9319 #define DSI_WIFCR_CTEIF_Pos (0U)
9320 #define DSI_WIFCR_CTEIF_Msk (0x1U << DSI_WIFCR_CTEIF_Pos) /*!< 0x00000001 */
9321 #define DSI_WIFCR_CTEIF DSI_WIFCR_CTEIF_Msk /*!< Clear Tearing Effect Interrupt Flag */
9322 #define DSI_WIFCR_CERIF_Pos (1U)
9323 #define DSI_WIFCR_CERIF_Msk (0x1U << DSI_WIFCR_CERIF_Pos) /*!< 0x00000002 */
9324 #define DSI_WIFCR_CERIF DSI_WIFCR_CERIF_Msk /*!< Clear End of Refresh Interrupt Flag */
9325 #define DSI_WIFCR_CPLLLIF_Pos (9U)
9326 #define DSI_WIFCR_CPLLLIF_Msk (0x1U << DSI_WIFCR_CPLLLIF_Pos) /*!< 0x00000200 */
9327 #define DSI_WIFCR_CPLLLIF DSI_WIFCR_CPLLLIF_Msk /*!< Clear PLL Lock Interrupt Flag */
9328 #define DSI_WIFCR_CPLLUIF_Pos (10U)
9329 #define DSI_WIFCR_CPLLUIF_Msk (0x1U << DSI_WIFCR_CPLLUIF_Pos) /*!< 0x00000400 */
9330 #define DSI_WIFCR_CPLLUIF DSI_WIFCR_CPLLUIF_Msk /*!< Clear PLL Unlock Interrupt Flag */
9331 #define DSI_WIFCR_CRRIF_Pos (13U)
9332 #define DSI_WIFCR_CRRIF_Msk (0x1U << DSI_WIFCR_CRRIF_Pos) /*!< 0x00002000 */
9333 #define DSI_WIFCR_CRRIF DSI_WIFCR_CRRIF_Msk /*!< Clear Regulator Ready Interrupt Flag */
9334
9335 /******************* Bit definition for DSI_WPCR0 register ***************/
9336 #define DSI_WPCR0_UIX4_Pos (0U)
9337 #define DSI_WPCR0_UIX4_Msk (0x3FU << DSI_WPCR0_UIX4_Pos) /*!< 0x0000003F */
9338 #define DSI_WPCR0_UIX4 DSI_WPCR0_UIX4_Msk /*!< Unit Interval multiplied by 4 */
9339 #define DSI_WPCR0_UIX4_0 (0x01U << DSI_WPCR0_UIX4_Pos) /*!< 0x00000001 */
9340 #define DSI_WPCR0_UIX4_1 (0x02U << DSI_WPCR0_UIX4_Pos) /*!< 0x00000002 */
9341 #define DSI_WPCR0_UIX4_2 (0x04U << DSI_WPCR0_UIX4_Pos) /*!< 0x00000004 */
9342 #define DSI_WPCR0_UIX4_3 (0x08U << DSI_WPCR0_UIX4_Pos) /*!< 0x00000008 */
9343 #define DSI_WPCR0_UIX4_4 (0x10U << DSI_WPCR0_UIX4_Pos) /*!< 0x00000010 */
9344 #define DSI_WPCR0_UIX4_5 (0x20U << DSI_WPCR0_UIX4_Pos) /*!< 0x00000020 */
9345
9346 #define DSI_WPCR0_SWCL_Pos (6U)
9347 #define DSI_WPCR0_SWCL_Msk (0x1U << DSI_WPCR0_SWCL_Pos) /*!< 0x00000040 */
9348 #define DSI_WPCR0_SWCL DSI_WPCR0_SWCL_Msk /*!< Swap pins on clock lane */
9349 #define DSI_WPCR0_SWDL0_Pos (7U)
9350 #define DSI_WPCR0_SWDL0_Msk (0x1U << DSI_WPCR0_SWDL0_Pos) /*!< 0x00000080 */
9351 #define DSI_WPCR0_SWDL0 DSI_WPCR0_SWDL0_Msk /*!< Swap pins on data lane 1 */
9352 #define DSI_WPCR0_SWDL1_Pos (8U)
9353 #define DSI_WPCR0_SWDL1_Msk (0x1U << DSI_WPCR0_SWDL1_Pos) /*!< 0x00000100 */
9354 #define DSI_WPCR0_SWDL1 DSI_WPCR0_SWDL1_Msk /*!< Swap pins on data lane 2 */
9355 #define DSI_WPCR0_HSICL_Pos (9U)
9356 #define DSI_WPCR0_HSICL_Msk (0x1U << DSI_WPCR0_HSICL_Pos) /*!< 0x00000200 */
9357 #define DSI_WPCR0_HSICL DSI_WPCR0_HSICL_Msk /*!< Invert the high-speed data signal on clock lane */
9358 #define DSI_WPCR0_HSIDL0_Pos (10U)
9359 #define DSI_WPCR0_HSIDL0_Msk (0x1U << DSI_WPCR0_HSIDL0_Pos) /*!< 0x00000400 */
9360 #define DSI_WPCR0_HSIDL0 DSI_WPCR0_HSIDL0_Msk /*!< Invert the high-speed data signal on lane 1 */
9361 #define DSI_WPCR0_HSIDL1_Pos (11U)
9362 #define DSI_WPCR0_HSIDL1_Msk (0x1U << DSI_WPCR0_HSIDL1_Pos) /*!< 0x00000800 */
9363 #define DSI_WPCR0_HSIDL1 DSI_WPCR0_HSIDL1_Msk /*!< Invert the high-speed data signal on lane 2 */
9364 #define DSI_WPCR0_FTXSMCL_Pos (12U)
9365 #define DSI_WPCR0_FTXSMCL_Msk (0x1U << DSI_WPCR0_FTXSMCL_Pos) /*!< 0x00001000 */
9366 #define DSI_WPCR0_FTXSMCL DSI_WPCR0_FTXSMCL_Msk /*!< Force clock lane in TX stop mode */
9367 #define DSI_WPCR0_FTXSMDL_Pos (13U)
9368 #define DSI_WPCR0_FTXSMDL_Msk (0x1U << DSI_WPCR0_FTXSMDL_Pos) /*!< 0x00002000 */
9369 #define DSI_WPCR0_FTXSMDL DSI_WPCR0_FTXSMDL_Msk /*!< Force data lanes in TX stop mode */
9370 #define DSI_WPCR0_CDOFFDL_Pos (14U)
9371 #define DSI_WPCR0_CDOFFDL_Msk (0x1U << DSI_WPCR0_CDOFFDL_Pos) /*!< 0x00004000 */
9372 #define DSI_WPCR0_CDOFFDL DSI_WPCR0_CDOFFDL_Msk /*!< Contention detection OFF */
9373 #define DSI_WPCR0_TDDL_Pos (16U)
9374 #define DSI_WPCR0_TDDL_Msk (0x1U << DSI_WPCR0_TDDL_Pos) /*!< 0x00010000 */
9375 #define DSI_WPCR0_TDDL DSI_WPCR0_TDDL_Msk /*!< Turn Disable Data Lanes */
9376 #define DSI_WPCR0_PDEN_Pos (18U)
9377 #define DSI_WPCR0_PDEN_Msk (0x1U << DSI_WPCR0_PDEN_Pos) /*!< 0x00040000 */
9378 #define DSI_WPCR0_PDEN DSI_WPCR0_PDEN_Msk /*!< Pull-Down Enable */
9379 #define DSI_WPCR0_TCLKPREPEN_Pos (19U)
9380 #define DSI_WPCR0_TCLKPREPEN_Msk (0x1U << DSI_WPCR0_TCLKPREPEN_Pos) /*!< 0x00080000 */
9381 #define DSI_WPCR0_TCLKPREPEN DSI_WPCR0_TCLKPREPEN_Msk /*!< Timer for t-CLKPREP Enable */
9382 #define DSI_WPCR0_TCLKZEROEN_Pos (20U)
9383 #define DSI_WPCR0_TCLKZEROEN_Msk (0x1U << DSI_WPCR0_TCLKZEROEN_Pos) /*!< 0x00100000 */
9384 #define DSI_WPCR0_TCLKZEROEN DSI_WPCR0_TCLKZEROEN_Msk /*!< Timer for t-CLKZERO Enable */
9385 #define DSI_WPCR0_THSPREPEN_Pos (21U)
9386 #define DSI_WPCR0_THSPREPEN_Msk (0x1U << DSI_WPCR0_THSPREPEN_Pos) /*!< 0x00200000 */
9387 #define DSI_WPCR0_THSPREPEN DSI_WPCR0_THSPREPEN_Msk /*!< Timer for t-HSPREP Enable */
9388 #define DSI_WPCR0_THSTRAILEN_Pos (22U)
9389 #define DSI_WPCR0_THSTRAILEN_Msk (0x1U << DSI_WPCR0_THSTRAILEN_Pos) /*!< 0x00400000 */
9390 #define DSI_WPCR0_THSTRAILEN DSI_WPCR0_THSTRAILEN_Msk /*!< Timer for t-HSTRAIL Enable */
9391 #define DSI_WPCR0_THSZEROEN_Pos (23U)
9392 #define DSI_WPCR0_THSZEROEN_Msk (0x1U << DSI_WPCR0_THSZEROEN_Pos) /*!< 0x00800000 */
9393 #define DSI_WPCR0_THSZEROEN DSI_WPCR0_THSZEROEN_Msk /*!< Timer for t-HSZERO Enable */
9394 #define DSI_WPCR0_TLPXDEN_Pos (24U)
9395 #define DSI_WPCR0_TLPXDEN_Msk (0x1U << DSI_WPCR0_TLPXDEN_Pos) /*!< 0x01000000 */
9396 #define DSI_WPCR0_TLPXDEN DSI_WPCR0_TLPXDEN_Msk /*!< Timer for t-LPXD Enable */
9397 #define DSI_WPCR0_THSEXITEN_Pos (25U)
9398 #define DSI_WPCR0_THSEXITEN_Msk (0x1U << DSI_WPCR0_THSEXITEN_Pos) /*!< 0x02000000 */
9399 #define DSI_WPCR0_THSEXITEN DSI_WPCR0_THSEXITEN_Msk /*!< Timer for t-HSEXIT Enable */
9400 #define DSI_WPCR0_TLPXCEN_Pos (26U)
9401 #define DSI_WPCR0_TLPXCEN_Msk (0x1U << DSI_WPCR0_TLPXCEN_Pos) /*!< 0x04000000 */
9402 #define DSI_WPCR0_TLPXCEN DSI_WPCR0_TLPXCEN_Msk /*!< Timer for t-LPXC Enable */
9403 #define DSI_WPCR0_TCLKPOSTEN_Pos (27U)
9404 #define DSI_WPCR0_TCLKPOSTEN_Msk (0x1U << DSI_WPCR0_TCLKPOSTEN_Pos) /*!< 0x08000000 */
9405 #define DSI_WPCR0_TCLKPOSTEN DSI_WPCR0_TCLKPOSTEN_Msk /*!< Timer for t-CLKPOST Enable */
9406
9407 /******************* Bit definition for DSI_WPCR1 register ***************/
9408 #define DSI_WPCR1_HSTXDCL_Pos (0U)
9409 #define DSI_WPCR1_HSTXDCL_Msk (0x3U << DSI_WPCR1_HSTXDCL_Pos) /*!< 0x00000003 */
9410 #define DSI_WPCR1_HSTXDCL DSI_WPCR1_HSTXDCL_Msk /*!< High-Speed Transmission Delay on Clock Lane */
9411 #define DSI_WPCR1_HSTXDCL0_Pos (0U)
9412 #define DSI_WPCR1_HSTXDCL0_Msk (0x1U << DSI_WPCR1_HSTXDCL0_Pos) /*!< 0x00000001 */
9413 #define DSI_WPCR1_HSTXDCL0 DSI_WPCR1_HSTXDCL0_Msk
9414 #define DSI_WPCR1_HSTXDCL1_Pos (1U)
9415 #define DSI_WPCR1_HSTXDCL1_Msk (0x1U << DSI_WPCR1_HSTXDCL1_Pos) /*!< 0x00000002 */
9416 #define DSI_WPCR1_HSTXDCL1 DSI_WPCR1_HSTXDCL1_Msk
9417
9418 #define DSI_WPCR1_HSTXDDL_Pos (2U)
9419 #define DSI_WPCR1_HSTXDDL_Msk (0x3U << DSI_WPCR1_HSTXDDL_Pos) /*!< 0x0000000C */
9420 #define DSI_WPCR1_HSTXDDL DSI_WPCR1_HSTXDDL_Msk /*!< High-Speed Transmission Delay on Data Lane */
9421 #define DSI_WPCR1_HSTXDDL0_Pos (2U)
9422 #define DSI_WPCR1_HSTXDDL0_Msk (0x1U << DSI_WPCR1_HSTXDDL0_Pos) /*!< 0x00000004 */
9423 #define DSI_WPCR1_HSTXDDL0 DSI_WPCR1_HSTXDDL0_Msk
9424 #define DSI_WPCR1_HSTXDDL1_Pos (3U)
9425 #define DSI_WPCR1_HSTXDDL1_Msk (0x1U << DSI_WPCR1_HSTXDDL1_Pos) /*!< 0x00000008 */
9426 #define DSI_WPCR1_HSTXDDL1 DSI_WPCR1_HSTXDDL1_Msk
9427
9428 #define DSI_WPCR1_LPSRCCL_Pos (6U)
9429 #define DSI_WPCR1_LPSRCCL_Msk (0x3U << DSI_WPCR1_LPSRCCL_Pos) /*!< 0x000000C0 */
9430 #define DSI_WPCR1_LPSRCCL DSI_WPCR1_LPSRCCL_Msk /*!< Low-Power transmission Slew Rate Compensation on Clock Lane */
9431 #define DSI_WPCR1_LPSRCCL0_Pos (6U)
9432 #define DSI_WPCR1_LPSRCCL0_Msk (0x1U << DSI_WPCR1_LPSRCCL0_Pos) /*!< 0x00000040 */
9433 #define DSI_WPCR1_LPSRCCL0 DSI_WPCR1_LPSRCCL0_Msk
9434 #define DSI_WPCR1_LPSRCCL1_Pos (7U)
9435 #define DSI_WPCR1_LPSRCCL1_Msk (0x1U << DSI_WPCR1_LPSRCCL1_Pos) /*!< 0x00000080 */
9436 #define DSI_WPCR1_LPSRCCL1 DSI_WPCR1_LPSRCCL1_Msk
9437
9438 #define DSI_WPCR1_LPSRCDL_Pos (8U)
9439 #define DSI_WPCR1_LPSRCDL_Msk (0x3U << DSI_WPCR1_LPSRCDL_Pos) /*!< 0x00000300 */
9440 #define DSI_WPCR1_LPSRCDL DSI_WPCR1_LPSRCDL_Msk /*!< Low-Power transmission Slew Rate Compensation on Data Lane */
9441 #define DSI_WPCR1_LPSRCDL0_Pos (8U)
9442 #define DSI_WPCR1_LPSRCDL0_Msk (0x1U << DSI_WPCR1_LPSRCDL0_Pos) /*!< 0x00000100 */
9443 #define DSI_WPCR1_LPSRCDL0 DSI_WPCR1_LPSRCDL0_Msk
9444 #define DSI_WPCR1_LPSRCDL1_Pos (9U)
9445 #define DSI_WPCR1_LPSRCDL1_Msk (0x1U << DSI_WPCR1_LPSRCDL1_Pos) /*!< 0x00000200 */
9446 #define DSI_WPCR1_LPSRCDL1 DSI_WPCR1_LPSRCDL1_Msk
9447
9448 #define DSI_WPCR1_SDDC_Pos (12U)
9449 #define DSI_WPCR1_SDDC_Msk (0x1U << DSI_WPCR1_SDDC_Pos) /*!< 0x00001000 */
9450 #define DSI_WPCR1_SDDC DSI_WPCR1_SDDC_Msk /*!< SDD Control */
9451
9452 #define DSI_WPCR1_LPRXVCDL_Pos (14U)
9453 #define DSI_WPCR1_LPRXVCDL_Msk (0x3U << DSI_WPCR1_LPRXVCDL_Pos) /*!< 0x0000C000 */
9454 #define DSI_WPCR1_LPRXVCDL DSI_WPCR1_LPRXVCDL_Msk /*!< Low-Power Reception V-IL Compensation on Data Lanes */
9455 #define DSI_WPCR1_LPRXVCDL0_Pos (14U)
9456 #define DSI_WPCR1_LPRXVCDL0_Msk (0x1U << DSI_WPCR1_LPRXVCDL0_Pos) /*!< 0x00004000 */
9457 #define DSI_WPCR1_LPRXVCDL0 DSI_WPCR1_LPRXVCDL0_Msk
9458 #define DSI_WPCR1_LPRXVCDL1_Pos (15U)
9459 #define DSI_WPCR1_LPRXVCDL1_Msk (0x1U << DSI_WPCR1_LPRXVCDL1_Pos) /*!< 0x00008000 */
9460 #define DSI_WPCR1_LPRXVCDL1 DSI_WPCR1_LPRXVCDL1_Msk
9461
9462 #define DSI_WPCR1_HSTXSRCCL_Pos (16U)
9463 #define DSI_WPCR1_HSTXSRCCL_Msk (0x3U << DSI_WPCR1_HSTXSRCCL_Pos) /*!< 0x00030000 */
9464 #define DSI_WPCR1_HSTXSRCCL DSI_WPCR1_HSTXSRCCL_Msk /*!< High-Speed Transmission Delay on Clock Lane */
9465 #define DSI_WPCR1_HSTXSRCCL0_Pos (16U)
9466 #define DSI_WPCR1_HSTXSRCCL0_Msk (0x1U << DSI_WPCR1_HSTXSRCCL0_Pos) /*!< 0x00010000 */
9467 #define DSI_WPCR1_HSTXSRCCL0 DSI_WPCR1_HSTXSRCCL0_Msk
9468 #define DSI_WPCR1_HSTXSRCCL1_Pos (17U)
9469 #define DSI_WPCR1_HSTXSRCCL1_Msk (0x1U << DSI_WPCR1_HSTXSRCCL1_Pos) /*!< 0x00020000 */
9470 #define DSI_WPCR1_HSTXSRCCL1 DSI_WPCR1_HSTXSRCCL1_Msk
9471
9472 #define DSI_WPCR1_HSTXSRCDL_Pos (18U)
9473 #define DSI_WPCR1_HSTXSRCDL_Msk (0x3U << DSI_WPCR1_HSTXSRCDL_Pos) /*!< 0x000C0000 */
9474 #define DSI_WPCR1_HSTXSRCDL DSI_WPCR1_HSTXSRCDL_Msk /*!< High-Speed Transmission Delay on Data Lane */
9475 #define DSI_WPCR1_HSTXSRCDL0_Pos (18U)
9476 #define DSI_WPCR1_HSTXSRCDL0_Msk (0x1U << DSI_WPCR1_HSTXSRCDL0_Pos) /*!< 0x00040000 */
9477 #define DSI_WPCR1_HSTXSRCDL0 DSI_WPCR1_HSTXSRCDL0_Msk
9478 #define DSI_WPCR1_HSTXSRCDL1_Pos (19U)
9479 #define DSI_WPCR1_HSTXSRCDL1_Msk (0x1U << DSI_WPCR1_HSTXSRCDL1_Pos) /*!< 0x00080000 */
9480 #define DSI_WPCR1_HSTXSRCDL1 DSI_WPCR1_HSTXSRCDL1_Msk
9481
9482 #define DSI_WPCR1_FLPRXLPM_Pos (22U)
9483 #define DSI_WPCR1_FLPRXLPM_Msk (0x1U << DSI_WPCR1_FLPRXLPM_Pos) /*!< 0x00400000 */
9484 #define DSI_WPCR1_FLPRXLPM DSI_WPCR1_FLPRXLPM_Msk /*!< Forces LP Receiver in Low-Power Mode */
9485
9486 #define DSI_WPCR1_LPRXFT_Pos (25U)
9487 #define DSI_WPCR1_LPRXFT_Msk (0x3U << DSI_WPCR1_LPRXFT_Pos) /*!< 0x06000000 */
9488 #define DSI_WPCR1_LPRXFT DSI_WPCR1_LPRXFT_Msk /*!< Low-Power RX low-pass Filtering Tuning */
9489 #define DSI_WPCR1_LPRXFT0_Pos (25U)
9490 #define DSI_WPCR1_LPRXFT0_Msk (0x1U << DSI_WPCR1_LPRXFT0_Pos) /*!< 0x02000000 */
9491 #define DSI_WPCR1_LPRXFT0 DSI_WPCR1_LPRXFT0_Msk
9492 #define DSI_WPCR1_LPRXFT1_Pos (26U)
9493 #define DSI_WPCR1_LPRXFT1_Msk (0x1U << DSI_WPCR1_LPRXFT1_Pos) /*!< 0x04000000 */
9494 #define DSI_WPCR1_LPRXFT1 DSI_WPCR1_LPRXFT1_Msk
9495
9496 /******************* Bit definition for DSI_WPCR2 register ***************/
9497 #define DSI_WPCR2_TCLKPREP_Pos (0U)
9498 #define DSI_WPCR2_TCLKPREP_Msk (0xFFU << DSI_WPCR2_TCLKPREP_Pos) /*!< 0x000000FF */
9499 #define DSI_WPCR2_TCLKPREP DSI_WPCR2_TCLKPREP_Msk /*!< t-CLKPREP */
9500 #define DSI_WPCR2_TCLKPREP0_Pos (0U)
9501 #define DSI_WPCR2_TCLKPREP0_Msk (0x1U << DSI_WPCR2_TCLKPREP0_Pos) /*!< 0x00000001 */
9502 #define DSI_WPCR2_TCLKPREP0 DSI_WPCR2_TCLKPREP0_Msk
9503 #define DSI_WPCR2_TCLKPREP1_Pos (1U)
9504 #define DSI_WPCR2_TCLKPREP1_Msk (0x1U << DSI_WPCR2_TCLKPREP1_Pos) /*!< 0x00000002 */
9505 #define DSI_WPCR2_TCLKPREP1 DSI_WPCR2_TCLKPREP1_Msk
9506 #define DSI_WPCR2_TCLKPREP2_Pos (2U)
9507 #define DSI_WPCR2_TCLKPREP2_Msk (0x1U << DSI_WPCR2_TCLKPREP2_Pos) /*!< 0x00000004 */
9508 #define DSI_WPCR2_TCLKPREP2 DSI_WPCR2_TCLKPREP2_Msk
9509 #define DSI_WPCR2_TCLKPREP3_Pos (3U)
9510 #define DSI_WPCR2_TCLKPREP3_Msk (0x1U << DSI_WPCR2_TCLKPREP3_Pos) /*!< 0x00000008 */
9511 #define DSI_WPCR2_TCLKPREP3 DSI_WPCR2_TCLKPREP3_Msk
9512 #define DSI_WPCR2_TCLKPREP4_Pos (4U)
9513 #define DSI_WPCR2_TCLKPREP4_Msk (0x1U << DSI_WPCR2_TCLKPREP4_Pos) /*!< 0x00000010 */
9514 #define DSI_WPCR2_TCLKPREP4 DSI_WPCR2_TCLKPREP4_Msk
9515 #define DSI_WPCR2_TCLKPREP5_Pos (5U)
9516 #define DSI_WPCR2_TCLKPREP5_Msk (0x1U << DSI_WPCR2_TCLKPREP5_Pos) /*!< 0x00000020 */
9517 #define DSI_WPCR2_TCLKPREP5 DSI_WPCR2_TCLKPREP5_Msk
9518 #define DSI_WPCR2_TCLKPREP6_Pos (6U)
9519 #define DSI_WPCR2_TCLKPREP6_Msk (0x1U << DSI_WPCR2_TCLKPREP6_Pos) /*!< 0x00000040 */
9520 #define DSI_WPCR2_TCLKPREP6 DSI_WPCR2_TCLKPREP6_Msk
9521 #define DSI_WPCR2_TCLKPREP7_Pos (7U)
9522 #define DSI_WPCR2_TCLKPREP7_Msk (0x1U << DSI_WPCR2_TCLKPREP7_Pos) /*!< 0x00000080 */
9523 #define DSI_WPCR2_TCLKPREP7 DSI_WPCR2_TCLKPREP7_Msk
9524
9525 #define DSI_WPCR2_TCLKZERO_Pos (8U)
9526 #define DSI_WPCR2_TCLKZERO_Msk (0xFFU << DSI_WPCR2_TCLKZERO_Pos) /*!< 0x0000FF00 */
9527 #define DSI_WPCR2_TCLKZERO DSI_WPCR2_TCLKZERO_Msk /*!< t-CLKZERO */
9528 #define DSI_WPCR2_TCLKZERO0_Pos (8U)
9529 #define DSI_WPCR2_TCLKZERO0_Msk (0x1U << DSI_WPCR2_TCLKZERO0_Pos) /*!< 0x00000100 */
9530 #define DSI_WPCR2_TCLKZERO0 DSI_WPCR2_TCLKZERO0_Msk
9531 #define DSI_WPCR2_TCLKZERO1_Pos (9U)
9532 #define DSI_WPCR2_TCLKZERO1_Msk (0x1U << DSI_WPCR2_TCLKZERO1_Pos) /*!< 0x00000200 */
9533 #define DSI_WPCR2_TCLKZERO1 DSI_WPCR2_TCLKZERO1_Msk
9534 #define DSI_WPCR2_TCLKZERO2_Pos (10U)
9535 #define DSI_WPCR2_TCLKZERO2_Msk (0x1U << DSI_WPCR2_TCLKZERO2_Pos) /*!< 0x00000400 */
9536 #define DSI_WPCR2_TCLKZERO2 DSI_WPCR2_TCLKZERO2_Msk
9537 #define DSI_WPCR2_TCLKZERO3_Pos (11U)
9538 #define DSI_WPCR2_TCLKZERO3_Msk (0x1U << DSI_WPCR2_TCLKZERO3_Pos) /*!< 0x00000800 */
9539 #define DSI_WPCR2_TCLKZERO3 DSI_WPCR2_TCLKZERO3_Msk
9540 #define DSI_WPCR2_TCLKZERO4_Pos (12U)
9541 #define DSI_WPCR2_TCLKZERO4_Msk (0x1U << DSI_WPCR2_TCLKZERO4_Pos) /*!< 0x00001000 */
9542 #define DSI_WPCR2_TCLKZERO4 DSI_WPCR2_TCLKZERO4_Msk
9543 #define DSI_WPCR2_TCLKZERO5_Pos (13U)
9544 #define DSI_WPCR2_TCLKZERO5_Msk (0x1U << DSI_WPCR2_TCLKZERO5_Pos) /*!< 0x00002000 */
9545 #define DSI_WPCR2_TCLKZERO5 DSI_WPCR2_TCLKZERO5_Msk
9546 #define DSI_WPCR2_TCLKZERO6_Pos (14U)
9547 #define DSI_WPCR2_TCLKZERO6_Msk (0x1U << DSI_WPCR2_TCLKZERO6_Pos) /*!< 0x00004000 */
9548 #define DSI_WPCR2_TCLKZERO6 DSI_WPCR2_TCLKZERO6_Msk
9549 #define DSI_WPCR2_TCLKZERO7_Pos (15U)
9550 #define DSI_WPCR2_TCLKZERO7_Msk (0x1U << DSI_WPCR2_TCLKZERO7_Pos) /*!< 0x00008000 */
9551 #define DSI_WPCR2_TCLKZERO7 DSI_WPCR2_TCLKZERO7_Msk
9552
9553 #define DSI_WPCR2_THSPREP_Pos (16U)
9554 #define DSI_WPCR2_THSPREP_Msk (0xFFU << DSI_WPCR2_THSPREP_Pos) /*!< 0x00FF0000 */
9555 #define DSI_WPCR2_THSPREP DSI_WPCR2_THSPREP_Msk /*!< t-HSPREP */
9556 #define DSI_WPCR2_THSPREP0_Pos (16U)
9557 #define DSI_WPCR2_THSPREP0_Msk (0x1U << DSI_WPCR2_THSPREP0_Pos) /*!< 0x00010000 */
9558 #define DSI_WPCR2_THSPREP0 DSI_WPCR2_THSPREP0_Msk
9559 #define DSI_WPCR2_THSPREP1_Pos (17U)
9560 #define DSI_WPCR2_THSPREP1_Msk (0x1U << DSI_WPCR2_THSPREP1_Pos) /*!< 0x00020000 */
9561 #define DSI_WPCR2_THSPREP1 DSI_WPCR2_THSPREP1_Msk
9562 #define DSI_WPCR2_THSPREP2_Pos (18U)
9563 #define DSI_WPCR2_THSPREP2_Msk (0x1U << DSI_WPCR2_THSPREP2_Pos) /*!< 0x00040000 */
9564 #define DSI_WPCR2_THSPREP2 DSI_WPCR2_THSPREP2_Msk
9565 #define DSI_WPCR2_THSPREP3_Pos (19U)
9566 #define DSI_WPCR2_THSPREP3_Msk (0x1U << DSI_WPCR2_THSPREP3_Pos) /*!< 0x00080000 */
9567 #define DSI_WPCR2_THSPREP3 DSI_WPCR2_THSPREP3_Msk
9568 #define DSI_WPCR2_THSPREP4_Pos (20U)
9569 #define DSI_WPCR2_THSPREP4_Msk (0x1U << DSI_WPCR2_THSPREP4_Pos) /*!< 0x00100000 */
9570 #define DSI_WPCR2_THSPREP4 DSI_WPCR2_THSPREP4_Msk
9571 #define DSI_WPCR2_THSPREP5_Pos (21U)
9572 #define DSI_WPCR2_THSPREP5_Msk (0x1U << DSI_WPCR2_THSPREP5_Pos) /*!< 0x00200000 */
9573 #define DSI_WPCR2_THSPREP5 DSI_WPCR2_THSPREP5_Msk
9574 #define DSI_WPCR2_THSPREP6_Pos (22U)
9575 #define DSI_WPCR2_THSPREP6_Msk (0x1U << DSI_WPCR2_THSPREP6_Pos) /*!< 0x00400000 */
9576 #define DSI_WPCR2_THSPREP6 DSI_WPCR2_THSPREP6_Msk
9577 #define DSI_WPCR2_THSPREP7_Pos (23U)
9578 #define DSI_WPCR2_THSPREP7_Msk (0x1U << DSI_WPCR2_THSPREP7_Pos) /*!< 0x00800000 */
9579 #define DSI_WPCR2_THSPREP7 DSI_WPCR2_THSPREP7_Msk
9580
9581 #define DSI_WPCR2_THSTRAIL_Pos (24U)
9582 #define DSI_WPCR2_THSTRAIL_Msk (0xFFU << DSI_WPCR2_THSTRAIL_Pos) /*!< 0xFF000000 */
9583 #define DSI_WPCR2_THSTRAIL DSI_WPCR2_THSTRAIL_Msk /*!< t-HSTRAIL */
9584 #define DSI_WPCR2_THSTRAIL0_Pos (24U)
9585 #define DSI_WPCR2_THSTRAIL0_Msk (0x1U << DSI_WPCR2_THSTRAIL0_Pos) /*!< 0x01000000 */
9586 #define DSI_WPCR2_THSTRAIL0 DSI_WPCR2_THSTRAIL0_Msk
9587 #define DSI_WPCR2_THSTRAIL1_Pos (25U)
9588 #define DSI_WPCR2_THSTRAIL1_Msk (0x1U << DSI_WPCR2_THSTRAIL1_Pos) /*!< 0x02000000 */
9589 #define DSI_WPCR2_THSTRAIL1 DSI_WPCR2_THSTRAIL1_Msk
9590 #define DSI_WPCR2_THSTRAIL2_Pos (26U)
9591 #define DSI_WPCR2_THSTRAIL2_Msk (0x1U << DSI_WPCR2_THSTRAIL2_Pos) /*!< 0x04000000 */
9592 #define DSI_WPCR2_THSTRAIL2 DSI_WPCR2_THSTRAIL2_Msk
9593 #define DSI_WPCR2_THSTRAIL3_Pos (27U)
9594 #define DSI_WPCR2_THSTRAIL3_Msk (0x1U << DSI_WPCR2_THSTRAIL3_Pos) /*!< 0x08000000 */
9595 #define DSI_WPCR2_THSTRAIL3 DSI_WPCR2_THSTRAIL3_Msk
9596 #define DSI_WPCR2_THSTRAIL4_Pos (28U)
9597 #define DSI_WPCR2_THSTRAIL4_Msk (0x1U << DSI_WPCR2_THSTRAIL4_Pos) /*!< 0x10000000 */
9598 #define DSI_WPCR2_THSTRAIL4 DSI_WPCR2_THSTRAIL4_Msk
9599 #define DSI_WPCR2_THSTRAIL5_Pos (29U)
9600 #define DSI_WPCR2_THSTRAIL5_Msk (0x1U << DSI_WPCR2_THSTRAIL5_Pos) /*!< 0x20000000 */
9601 #define DSI_WPCR2_THSTRAIL5 DSI_WPCR2_THSTRAIL5_Msk
9602 #define DSI_WPCR2_THSTRAIL6_Pos (30U)
9603 #define DSI_WPCR2_THSTRAIL6_Msk (0x1U << DSI_WPCR2_THSTRAIL6_Pos) /*!< 0x40000000 */
9604 #define DSI_WPCR2_THSTRAIL6 DSI_WPCR2_THSTRAIL6_Msk
9605 #define DSI_WPCR2_THSTRAIL7_Pos (31U)
9606 #define DSI_WPCR2_THSTRAIL7_Msk (0x1U << DSI_WPCR2_THSTRAIL7_Pos) /*!< 0x80000000 */
9607 #define DSI_WPCR2_THSTRAIL7 DSI_WPCR2_THSTRAIL7_Msk
9608
9609 /******************* Bit definition for DSI_WPCR3 register ***************/
9610 #define DSI_WPCR3_THSZERO_Pos (0U)
9611 #define DSI_WPCR3_THSZERO_Msk (0xFFU << DSI_WPCR3_THSZERO_Pos) /*!< 0x000000FF */
9612 #define DSI_WPCR3_THSZERO DSI_WPCR3_THSZERO_Msk /*!< t-HSZERO */
9613 #define DSI_WPCR3_THSZERO0_Pos (0U)
9614 #define DSI_WPCR3_THSZERO0_Msk (0x1U << DSI_WPCR3_THSZERO0_Pos) /*!< 0x00000001 */
9615 #define DSI_WPCR3_THSZERO0 DSI_WPCR3_THSZERO0_Msk
9616 #define DSI_WPCR3_THSZERO1_Pos (1U)
9617 #define DSI_WPCR3_THSZERO1_Msk (0x1U << DSI_WPCR3_THSZERO1_Pos) /*!< 0x00000002 */
9618 #define DSI_WPCR3_THSZERO1 DSI_WPCR3_THSZERO1_Msk
9619 #define DSI_WPCR3_THSZERO2_Pos (2U)
9620 #define DSI_WPCR3_THSZERO2_Msk (0x1U << DSI_WPCR3_THSZERO2_Pos) /*!< 0x00000004 */
9621 #define DSI_WPCR3_THSZERO2 DSI_WPCR3_THSZERO2_Msk
9622 #define DSI_WPCR3_THSZERO3_Pos (3U)
9623 #define DSI_WPCR3_THSZERO3_Msk (0x1U << DSI_WPCR3_THSZERO3_Pos) /*!< 0x00000008 */
9624 #define DSI_WPCR3_THSZERO3 DSI_WPCR3_THSZERO3_Msk
9625 #define DSI_WPCR3_THSZERO4_Pos (4U)
9626 #define DSI_WPCR3_THSZERO4_Msk (0x1U << DSI_WPCR3_THSZERO4_Pos) /*!< 0x00000010 */
9627 #define DSI_WPCR3_THSZERO4 DSI_WPCR3_THSZERO4_Msk
9628 #define DSI_WPCR3_THSZERO5_Pos (5U)
9629 #define DSI_WPCR3_THSZERO5_Msk (0x1U << DSI_WPCR3_THSZERO5_Pos) /*!< 0x00000020 */
9630 #define DSI_WPCR3_THSZERO5 DSI_WPCR3_THSZERO5_Msk
9631 #define DSI_WPCR3_THSZERO6_Pos (6U)
9632 #define DSI_WPCR3_THSZERO6_Msk (0x1U << DSI_WPCR3_THSZERO6_Pos) /*!< 0x00000040 */
9633 #define DSI_WPCR3_THSZERO6 DSI_WPCR3_THSZERO6_Msk
9634 #define DSI_WPCR3_THSZERO7_Pos (7U)
9635 #define DSI_WPCR3_THSZERO7_Msk (0x1U << DSI_WPCR3_THSZERO7_Pos) /*!< 0x00000080 */
9636 #define DSI_WPCR3_THSZERO7 DSI_WPCR3_THSZERO7_Msk
9637
9638 #define DSI_WPCR3_TLPXD_Pos (8U)
9639 #define DSI_WPCR3_TLPXD_Msk (0xFFU << DSI_WPCR3_TLPXD_Pos) /*!< 0x0000FF00 */
9640 #define DSI_WPCR3_TLPXD DSI_WPCR3_TLPXD_Msk /*!< t-LPXD */
9641 #define DSI_WPCR3_TLPXD0_Pos (8U)
9642 #define DSI_WPCR3_TLPXD0_Msk (0x1U << DSI_WPCR3_TLPXD0_Pos) /*!< 0x00000100 */
9643 #define DSI_WPCR3_TLPXD0 DSI_WPCR3_TLPXD0_Msk
9644 #define DSI_WPCR3_TLPXD1_Pos (9U)
9645 #define DSI_WPCR3_TLPXD1_Msk (0x1U << DSI_WPCR3_TLPXD1_Pos) /*!< 0x00000200 */
9646 #define DSI_WPCR3_TLPXD1 DSI_WPCR3_TLPXD1_Msk
9647 #define DSI_WPCR3_TLPXD2_Pos (10U)
9648 #define DSI_WPCR3_TLPXD2_Msk (0x1U << DSI_WPCR3_TLPXD2_Pos) /*!< 0x00000400 */
9649 #define DSI_WPCR3_TLPXD2 DSI_WPCR3_TLPXD2_Msk
9650 #define DSI_WPCR3_TLPXD3_Pos (11U)
9651 #define DSI_WPCR3_TLPXD3_Msk (0x1U << DSI_WPCR3_TLPXD3_Pos) /*!< 0x00000800 */
9652 #define DSI_WPCR3_TLPXD3 DSI_WPCR3_TLPXD3_Msk
9653 #define DSI_WPCR3_TLPXD4_Pos (12U)
9654 #define DSI_WPCR3_TLPXD4_Msk (0x1U << DSI_WPCR3_TLPXD4_Pos) /*!< 0x00001000 */
9655 #define DSI_WPCR3_TLPXD4 DSI_WPCR3_TLPXD4_Msk
9656 #define DSI_WPCR3_TLPXD5_Pos (13U)
9657 #define DSI_WPCR3_TLPXD5_Msk (0x1U << DSI_WPCR3_TLPXD5_Pos) /*!< 0x00002000 */
9658 #define DSI_WPCR3_TLPXD5 DSI_WPCR3_TLPXD5_Msk
9659 #define DSI_WPCR3_TLPXD6_Pos (14U)
9660 #define DSI_WPCR3_TLPXD6_Msk (0x1U << DSI_WPCR3_TLPXD6_Pos) /*!< 0x00004000 */
9661 #define DSI_WPCR3_TLPXD6 DSI_WPCR3_TLPXD6_Msk
9662 #define DSI_WPCR3_TLPXD7_Pos (15U)
9663 #define DSI_WPCR3_TLPXD7_Msk (0x1U << DSI_WPCR3_TLPXD7_Pos) /*!< 0x00008000 */
9664 #define DSI_WPCR3_TLPXD7 DSI_WPCR3_TLPXD7_Msk
9665
9666 #define DSI_WPCR3_THSEXIT_Pos (16U)
9667 #define DSI_WPCR3_THSEXIT_Msk (0xFFU << DSI_WPCR3_THSEXIT_Pos) /*!< 0x00FF0000 */
9668 #define DSI_WPCR3_THSEXIT DSI_WPCR3_THSEXIT_Msk /*!< t-HSEXIT */
9669 #define DSI_WPCR3_THSEXIT0_Pos (16U)
9670 #define DSI_WPCR3_THSEXIT0_Msk (0x1U << DSI_WPCR3_THSEXIT0_Pos) /*!< 0x00010000 */
9671 #define DSI_WPCR3_THSEXIT0 DSI_WPCR3_THSEXIT0_Msk
9672 #define DSI_WPCR3_THSEXIT1_Pos (17U)
9673 #define DSI_WPCR3_THSEXIT1_Msk (0x1U << DSI_WPCR3_THSEXIT1_Pos) /*!< 0x00020000 */
9674 #define DSI_WPCR3_THSEXIT1 DSI_WPCR3_THSEXIT1_Msk
9675 #define DSI_WPCR3_THSEXIT2_Pos (18U)
9676 #define DSI_WPCR3_THSEXIT2_Msk (0x1U << DSI_WPCR3_THSEXIT2_Pos) /*!< 0x00040000 */
9677 #define DSI_WPCR3_THSEXIT2 DSI_WPCR3_THSEXIT2_Msk
9678 #define DSI_WPCR3_THSEXIT3_Pos (19U)
9679 #define DSI_WPCR3_THSEXIT3_Msk (0x1U << DSI_WPCR3_THSEXIT3_Pos) /*!< 0x00080000 */
9680 #define DSI_WPCR3_THSEXIT3 DSI_WPCR3_THSEXIT3_Msk
9681 #define DSI_WPCR3_THSEXIT4_Pos (20U)
9682 #define DSI_WPCR3_THSEXIT4_Msk (0x1U << DSI_WPCR3_THSEXIT4_Pos) /*!< 0x00100000 */
9683 #define DSI_WPCR3_THSEXIT4 DSI_WPCR3_THSEXIT4_Msk
9684 #define DSI_WPCR3_THSEXIT5_Pos (21U)
9685 #define DSI_WPCR3_THSEXIT5_Msk (0x1U << DSI_WPCR3_THSEXIT5_Pos) /*!< 0x00200000 */
9686 #define DSI_WPCR3_THSEXIT5 DSI_WPCR3_THSEXIT5_Msk
9687 #define DSI_WPCR3_THSEXIT6_Pos (22U)
9688 #define DSI_WPCR3_THSEXIT6_Msk (0x1U << DSI_WPCR3_THSEXIT6_Pos) /*!< 0x00400000 */
9689 #define DSI_WPCR3_THSEXIT6 DSI_WPCR3_THSEXIT6_Msk
9690 #define DSI_WPCR3_THSEXIT7_Pos (23U)
9691 #define DSI_WPCR3_THSEXIT7_Msk (0x1U << DSI_WPCR3_THSEXIT7_Pos) /*!< 0x00800000 */
9692 #define DSI_WPCR3_THSEXIT7 DSI_WPCR3_THSEXIT7_Msk
9693
9694 #define DSI_WPCR3_TLPXC_Pos (24U)
9695 #define DSI_WPCR3_TLPXC_Msk (0xFFU << DSI_WPCR3_TLPXC_Pos) /*!< 0xFF000000 */
9696 #define DSI_WPCR3_TLPXC DSI_WPCR3_TLPXC_Msk /*!< t-LPXC */
9697 #define DSI_WPCR3_TLPXC0_Pos (24U)
9698 #define DSI_WPCR3_TLPXC0_Msk (0x1U << DSI_WPCR3_TLPXC0_Pos) /*!< 0x01000000 */
9699 #define DSI_WPCR3_TLPXC0 DSI_WPCR3_TLPXC0_Msk
9700 #define DSI_WPCR3_TLPXC1_Pos (25U)
9701 #define DSI_WPCR3_TLPXC1_Msk (0x1U << DSI_WPCR3_TLPXC1_Pos) /*!< 0x02000000 */
9702 #define DSI_WPCR3_TLPXC1 DSI_WPCR3_TLPXC1_Msk
9703 #define DSI_WPCR3_TLPXC2_Pos (26U)
9704 #define DSI_WPCR3_TLPXC2_Msk (0x1U << DSI_WPCR3_TLPXC2_Pos) /*!< 0x04000000 */
9705 #define DSI_WPCR3_TLPXC2 DSI_WPCR3_TLPXC2_Msk
9706 #define DSI_WPCR3_TLPXC3_Pos (27U)
9707 #define DSI_WPCR3_TLPXC3_Msk (0x1U << DSI_WPCR3_TLPXC3_Pos) /*!< 0x08000000 */
9708 #define DSI_WPCR3_TLPXC3 DSI_WPCR3_TLPXC3_Msk
9709 #define DSI_WPCR3_TLPXC4_Pos (28U)
9710 #define DSI_WPCR3_TLPXC4_Msk (0x1U << DSI_WPCR3_TLPXC4_Pos) /*!< 0x10000000 */
9711 #define DSI_WPCR3_TLPXC4 DSI_WPCR3_TLPXC4_Msk
9712 #define DSI_WPCR3_TLPXC5_Pos (29U)
9713 #define DSI_WPCR3_TLPXC5_Msk (0x1U << DSI_WPCR3_TLPXC5_Pos) /*!< 0x20000000 */
9714 #define DSI_WPCR3_TLPXC5 DSI_WPCR3_TLPXC5_Msk
9715 #define DSI_WPCR3_TLPXC6_Pos (30U)
9716 #define DSI_WPCR3_TLPXC6_Msk (0x1U << DSI_WPCR3_TLPXC6_Pos) /*!< 0x40000000 */
9717 #define DSI_WPCR3_TLPXC6 DSI_WPCR3_TLPXC6_Msk
9718 #define DSI_WPCR3_TLPXC7_Pos (31U)
9719 #define DSI_WPCR3_TLPXC7_Msk (0x1U << DSI_WPCR3_TLPXC7_Pos) /*!< 0x80000000 */
9720 #define DSI_WPCR3_TLPXC7 DSI_WPCR3_TLPXC7_Msk
9721
9722 /******************* Bit definition for DSI_WPCR4 register ***************/
9723 #define DSI_WPCR4_TCLKPOST_Pos (0U)
9724 #define DSI_WPCR4_TCLKPOST_Msk (0xFFU << DSI_WPCR4_TCLKPOST_Pos) /*!< 0x000000FF */
9725 #define DSI_WPCR4_TCLKPOST DSI_WPCR4_TCLKPOST_Msk /*!< t-CLKPOST */
9726 #define DSI_WPCR4_TCLKPOST0_Pos (0U)
9727 #define DSI_WPCR4_TCLKPOST0_Msk (0x1U << DSI_WPCR4_TCLKPOST0_Pos) /*!< 0x00000001 */
9728 #define DSI_WPCR4_TCLKPOST0 DSI_WPCR4_TCLKPOST0_Msk
9729 #define DSI_WPCR4_TCLKPOST1_Pos (1U)
9730 #define DSI_WPCR4_TCLKPOST1_Msk (0x1U << DSI_WPCR4_TCLKPOST1_Pos) /*!< 0x00000002 */
9731 #define DSI_WPCR4_TCLKPOST1 DSI_WPCR4_TCLKPOST1_Msk
9732 #define DSI_WPCR4_TCLKPOST2_Pos (2U)
9733 #define DSI_WPCR4_TCLKPOST2_Msk (0x1U << DSI_WPCR4_TCLKPOST2_Pos) /*!< 0x00000004 */
9734 #define DSI_WPCR4_TCLKPOST2 DSI_WPCR4_TCLKPOST2_Msk
9735 #define DSI_WPCR4_TCLKPOST3_Pos (3U)
9736 #define DSI_WPCR4_TCLKPOST3_Msk (0x1U << DSI_WPCR4_TCLKPOST3_Pos) /*!< 0x00000008 */
9737 #define DSI_WPCR4_TCLKPOST3 DSI_WPCR4_TCLKPOST3_Msk
9738 #define DSI_WPCR4_TCLKPOST4_Pos (4U)
9739 #define DSI_WPCR4_TCLKPOST4_Msk (0x1U << DSI_WPCR4_TCLKPOST4_Pos) /*!< 0x00000010 */
9740 #define DSI_WPCR4_TCLKPOST4 DSI_WPCR4_TCLKPOST4_Msk
9741 #define DSI_WPCR4_TCLKPOST5_Pos (5U)
9742 #define DSI_WPCR4_TCLKPOST5_Msk (0x1U << DSI_WPCR4_TCLKPOST5_Pos) /*!< 0x00000020 */
9743 #define DSI_WPCR4_TCLKPOST5 DSI_WPCR4_TCLKPOST5_Msk
9744 #define DSI_WPCR4_TCLKPOST6_Pos (6U)
9745 #define DSI_WPCR4_TCLKPOST6_Msk (0x1U << DSI_WPCR4_TCLKPOST6_Pos) /*!< 0x00000040 */
9746 #define DSI_WPCR4_TCLKPOST6 DSI_WPCR4_TCLKPOST6_Msk
9747 #define DSI_WPCR4_TCLKPOST7_Pos (7U)
9748 #define DSI_WPCR4_TCLKPOST7_Msk (0x1U << DSI_WPCR4_TCLKPOST7_Pos) /*!< 0x00000080 */
9749 #define DSI_WPCR4_TCLKPOST7 DSI_WPCR4_TCLKPOST7_Msk
9750
9751 /******************* Bit definition for DSI_WRPCR register ***************/
9752 #define DSI_WRPCR_PLLEN_Pos (0U)
9753 #define DSI_WRPCR_PLLEN_Msk (0x1U << DSI_WRPCR_PLLEN_Pos) /*!< 0x00000001 */
9754 #define DSI_WRPCR_PLLEN DSI_WRPCR_PLLEN_Msk /*!< PLL Enable */
9755 #define DSI_WRPCR_PLL_NDIV_Pos (2U)
9756 #define DSI_WRPCR_PLL_NDIV_Msk (0x7FU << DSI_WRPCR_PLL_NDIV_Pos) /*!< 0x000001FC */
9757 #define DSI_WRPCR_PLL_NDIV DSI_WRPCR_PLL_NDIV_Msk /*!< PLL Loop Division Factor */
9758 #define DSI_WRPCR_PLL_NDIV0_Pos (2U)
9759 #define DSI_WRPCR_PLL_NDIV0_Msk (0x1U << DSI_WRPCR_PLL_NDIV0_Pos) /*!< 0x00000004 */
9760 #define DSI_WRPCR_PLL_NDIV0 DSI_WRPCR_PLL_NDIV0_Msk
9761 #define DSI_WRPCR_PLL_NDIV1_Pos (3U)
9762 #define DSI_WRPCR_PLL_NDIV1_Msk (0x1U << DSI_WRPCR_PLL_NDIV1_Pos) /*!< 0x00000008 */
9763 #define DSI_WRPCR_PLL_NDIV1 DSI_WRPCR_PLL_NDIV1_Msk
9764 #define DSI_WRPCR_PLL_NDIV2_Pos (4U)
9765 #define DSI_WRPCR_PLL_NDIV2_Msk (0x1U << DSI_WRPCR_PLL_NDIV2_Pos) /*!< 0x00000010 */
9766 #define DSI_WRPCR_PLL_NDIV2 DSI_WRPCR_PLL_NDIV2_Msk
9767 #define DSI_WRPCR_PLL_NDIV3_Pos (5U)
9768 #define DSI_WRPCR_PLL_NDIV3_Msk (0x1U << DSI_WRPCR_PLL_NDIV3_Pos) /*!< 0x00000020 */
9769 #define DSI_WRPCR_PLL_NDIV3 DSI_WRPCR_PLL_NDIV3_Msk
9770 #define DSI_WRPCR_PLL_NDIV4_Pos (6U)
9771 #define DSI_WRPCR_PLL_NDIV4_Msk (0x1U << DSI_WRPCR_PLL_NDIV4_Pos) /*!< 0x00000040 */
9772 #define DSI_WRPCR_PLL_NDIV4 DSI_WRPCR_PLL_NDIV4_Msk
9773 #define DSI_WRPCR_PLL_NDIV5_Pos (7U)
9774 #define DSI_WRPCR_PLL_NDIV5_Msk (0x1U << DSI_WRPCR_PLL_NDIV5_Pos) /*!< 0x00000080 */
9775 #define DSI_WRPCR_PLL_NDIV5 DSI_WRPCR_PLL_NDIV5_Msk
9776 #define DSI_WRPCR_PLL_NDIV6_Pos (8U)
9777 #define DSI_WRPCR_PLL_NDIV6_Msk (0x1U << DSI_WRPCR_PLL_NDIV6_Pos) /*!< 0x00000100 */
9778 #define DSI_WRPCR_PLL_NDIV6 DSI_WRPCR_PLL_NDIV6_Msk
9779
9780 #define DSI_WRPCR_PLL_IDF_Pos (11U)
9781 #define DSI_WRPCR_PLL_IDF_Msk (0xFU << DSI_WRPCR_PLL_IDF_Pos) /*!< 0x00007800 */
9782 #define DSI_WRPCR_PLL_IDF DSI_WRPCR_PLL_IDF_Msk /*!< PLL Input Division Factor */
9783 #define DSI_WRPCR_PLL_IDF0_Pos (11U)
9784 #define DSI_WRPCR_PLL_IDF0_Msk (0x1U << DSI_WRPCR_PLL_IDF0_Pos) /*!< 0x00000800 */
9785 #define DSI_WRPCR_PLL_IDF0 DSI_WRPCR_PLL_IDF0_Msk
9786 #define DSI_WRPCR_PLL_IDF1_Pos (12U)
9787 #define DSI_WRPCR_PLL_IDF1_Msk (0x1U << DSI_WRPCR_PLL_IDF1_Pos) /*!< 0x00001000 */
9788 #define DSI_WRPCR_PLL_IDF1 DSI_WRPCR_PLL_IDF1_Msk
9789 #define DSI_WRPCR_PLL_IDF2_Pos (13U)
9790 #define DSI_WRPCR_PLL_IDF2_Msk (0x1U << DSI_WRPCR_PLL_IDF2_Pos) /*!< 0x00002000 */
9791 #define DSI_WRPCR_PLL_IDF2 DSI_WRPCR_PLL_IDF2_Msk
9792 #define DSI_WRPCR_PLL_IDF3_Pos (14U)
9793 #define DSI_WRPCR_PLL_IDF3_Msk (0x1U << DSI_WRPCR_PLL_IDF3_Pos) /*!< 0x00004000 */
9794 #define DSI_WRPCR_PLL_IDF3 DSI_WRPCR_PLL_IDF3_Msk
9795
9796 #define DSI_WRPCR_PLL_ODF_Pos (16U)
9797 #define DSI_WRPCR_PLL_ODF_Msk (0x3U << DSI_WRPCR_PLL_ODF_Pos) /*!< 0x00030000 */
9798 #define DSI_WRPCR_PLL_ODF DSI_WRPCR_PLL_ODF_Msk /*!< PLL Output Division Factor */
9799 #define DSI_WRPCR_PLL_ODF0_Pos (16U)
9800 #define DSI_WRPCR_PLL_ODF0_Msk (0x1U << DSI_WRPCR_PLL_ODF0_Pos) /*!< 0x00010000 */
9801 #define DSI_WRPCR_PLL_ODF0 DSI_WRPCR_PLL_ODF0_Msk
9802 #define DSI_WRPCR_PLL_ODF1_Pos (17U)
9803 #define DSI_WRPCR_PLL_ODF1_Msk (0x1U << DSI_WRPCR_PLL_ODF1_Pos) /*!< 0x00020000 */
9804 #define DSI_WRPCR_PLL_ODF1 DSI_WRPCR_PLL_ODF1_Msk
9805
9806 #define DSI_WRPCR_REGEN_Pos (24U)
9807 #define DSI_WRPCR_REGEN_Msk (0x1U << DSI_WRPCR_REGEN_Pos) /*!< 0x01000000 */
9808 #define DSI_WRPCR_REGEN DSI_WRPCR_REGEN_Msk /*!< Regulator Enable */
9809
9810 /******************************************************************************/
9811 /* */
9812 /* External Interrupt/Event Controller */
9813 /* */
9814 /******************************************************************************/
9815 /******************* Bit definition for EXTI_IMR register *******************/
9816 #define EXTI_IMR_MR0_Pos (0U)
9817 #define EXTI_IMR_MR0_Msk (0x1U << EXTI_IMR_MR0_Pos) /*!< 0x00000001 */
9818 #define EXTI_IMR_MR0 EXTI_IMR_MR0_Msk /*!< Interrupt Mask on line 0 */
9819 #define EXTI_IMR_MR1_Pos (1U)
9820 #define EXTI_IMR_MR1_Msk (0x1U << EXTI_IMR_MR1_Pos) /*!< 0x00000002 */
9821 #define EXTI_IMR_MR1 EXTI_IMR_MR1_Msk /*!< Interrupt Mask on line 1 */
9822 #define EXTI_IMR_MR2_Pos (2U)
9823 #define EXTI_IMR_MR2_Msk (0x1U << EXTI_IMR_MR2_Pos) /*!< 0x00000004 */
9824 #define EXTI_IMR_MR2 EXTI_IMR_MR2_Msk /*!< Interrupt Mask on line 2 */
9825 #define EXTI_IMR_MR3_Pos (3U)
9826 #define EXTI_IMR_MR3_Msk (0x1U << EXTI_IMR_MR3_Pos) /*!< 0x00000008 */
9827 #define EXTI_IMR_MR3 EXTI_IMR_MR3_Msk /*!< Interrupt Mask on line 3 */
9828 #define EXTI_IMR_MR4_Pos (4U)
9829 #define EXTI_IMR_MR4_Msk (0x1U << EXTI_IMR_MR4_Pos) /*!< 0x00000010 */
9830 #define EXTI_IMR_MR4 EXTI_IMR_MR4_Msk /*!< Interrupt Mask on line 4 */
9831 #define EXTI_IMR_MR5_Pos (5U)
9832 #define EXTI_IMR_MR5_Msk (0x1U << EXTI_IMR_MR5_Pos) /*!< 0x00000020 */
9833 #define EXTI_IMR_MR5 EXTI_IMR_MR5_Msk /*!< Interrupt Mask on line 5 */
9834 #define EXTI_IMR_MR6_Pos (6U)
9835 #define EXTI_IMR_MR6_Msk (0x1U << EXTI_IMR_MR6_Pos) /*!< 0x00000040 */
9836 #define EXTI_IMR_MR6 EXTI_IMR_MR6_Msk /*!< Interrupt Mask on line 6 */
9837 #define EXTI_IMR_MR7_Pos (7U)
9838 #define EXTI_IMR_MR7_Msk (0x1U << EXTI_IMR_MR7_Pos) /*!< 0x00000080 */
9839 #define EXTI_IMR_MR7 EXTI_IMR_MR7_Msk /*!< Interrupt Mask on line 7 */
9840 #define EXTI_IMR_MR8_Pos (8U)
9841 #define EXTI_IMR_MR8_Msk (0x1U << EXTI_IMR_MR8_Pos) /*!< 0x00000100 */
9842 #define EXTI_IMR_MR8 EXTI_IMR_MR8_Msk /*!< Interrupt Mask on line 8 */
9843 #define EXTI_IMR_MR9_Pos (9U)
9844 #define EXTI_IMR_MR9_Msk (0x1U << EXTI_IMR_MR9_Pos) /*!< 0x00000200 */
9845 #define EXTI_IMR_MR9 EXTI_IMR_MR9_Msk /*!< Interrupt Mask on line 9 */
9846 #define EXTI_IMR_MR10_Pos (10U)
9847 #define EXTI_IMR_MR10_Msk (0x1U << EXTI_IMR_MR10_Pos) /*!< 0x00000400 */
9848 #define EXTI_IMR_MR10 EXTI_IMR_MR10_Msk /*!< Interrupt Mask on line 10 */
9849 #define EXTI_IMR_MR11_Pos (11U)
9850 #define EXTI_IMR_MR11_Msk (0x1U << EXTI_IMR_MR11_Pos) /*!< 0x00000800 */
9851 #define EXTI_IMR_MR11 EXTI_IMR_MR11_Msk /*!< Interrupt Mask on line 11 */
9852 #define EXTI_IMR_MR12_Pos (12U)
9853 #define EXTI_IMR_MR12_Msk (0x1U << EXTI_IMR_MR12_Pos) /*!< 0x00001000 */
9854 #define EXTI_IMR_MR12 EXTI_IMR_MR12_Msk /*!< Interrupt Mask on line 12 */
9855 #define EXTI_IMR_MR13_Pos (13U)
9856 #define EXTI_IMR_MR13_Msk (0x1U << EXTI_IMR_MR13_Pos) /*!< 0x00002000 */
9857 #define EXTI_IMR_MR13 EXTI_IMR_MR13_Msk /*!< Interrupt Mask on line 13 */
9858 #define EXTI_IMR_MR14_Pos (14U)
9859 #define EXTI_IMR_MR14_Msk (0x1U << EXTI_IMR_MR14_Pos) /*!< 0x00004000 */
9860 #define EXTI_IMR_MR14 EXTI_IMR_MR14_Msk /*!< Interrupt Mask on line 14 */
9861 #define EXTI_IMR_MR15_Pos (15U)
9862 #define EXTI_IMR_MR15_Msk (0x1U << EXTI_IMR_MR15_Pos) /*!< 0x00008000 */
9863 #define EXTI_IMR_MR15 EXTI_IMR_MR15_Msk /*!< Interrupt Mask on line 15 */
9864 #define EXTI_IMR_MR16_Pos (16U)
9865 #define EXTI_IMR_MR16_Msk (0x1U << EXTI_IMR_MR16_Pos) /*!< 0x00010000 */
9866 #define EXTI_IMR_MR16 EXTI_IMR_MR16_Msk /*!< Interrupt Mask on line 16 */
9867 #define EXTI_IMR_MR17_Pos (17U)
9868 #define EXTI_IMR_MR17_Msk (0x1U << EXTI_IMR_MR17_Pos) /*!< 0x00020000 */
9869 #define EXTI_IMR_MR17 EXTI_IMR_MR17_Msk /*!< Interrupt Mask on line 17 */
9870 #define EXTI_IMR_MR18_Pos (18U)
9871 #define EXTI_IMR_MR18_Msk (0x1U << EXTI_IMR_MR18_Pos) /*!< 0x00040000 */
9872 #define EXTI_IMR_MR18 EXTI_IMR_MR18_Msk /*!< Interrupt Mask on line 18 */
9873 #define EXTI_IMR_MR19_Pos (19U)
9874 #define EXTI_IMR_MR19_Msk (0x1U << EXTI_IMR_MR19_Pos) /*!< 0x00080000 */
9875 #define EXTI_IMR_MR19 EXTI_IMR_MR19_Msk /*!< Interrupt Mask on line 19 */
9876 #define EXTI_IMR_MR20_Pos (20U)
9877 #define EXTI_IMR_MR20_Msk (0x1U << EXTI_IMR_MR20_Pos) /*!< 0x00100000 */
9878 #define EXTI_IMR_MR20 EXTI_IMR_MR20_Msk /*!< Interrupt Mask on line 20 */
9879 #define EXTI_IMR_MR21_Pos (21U)
9880 #define EXTI_IMR_MR21_Msk (0x1U << EXTI_IMR_MR21_Pos) /*!< 0x00200000 */
9881 #define EXTI_IMR_MR21 EXTI_IMR_MR21_Msk /*!< Interrupt Mask on line 21 */
9882 #define EXTI_IMR_MR22_Pos (22U)
9883 #define EXTI_IMR_MR22_Msk (0x1U << EXTI_IMR_MR22_Pos) /*!< 0x00400000 */
9884 #define EXTI_IMR_MR22 EXTI_IMR_MR22_Msk /*!< Interrupt Mask on line 22 */
9885
9886 /* Reference Defines */
9887 #define EXTI_IMR_IM0 EXTI_IMR_MR0
9888 #define EXTI_IMR_IM1 EXTI_IMR_MR1
9889 #define EXTI_IMR_IM2 EXTI_IMR_MR2
9890 #define EXTI_IMR_IM3 EXTI_IMR_MR3
9891 #define EXTI_IMR_IM4 EXTI_IMR_MR4
9892 #define EXTI_IMR_IM5 EXTI_IMR_MR5
9893 #define EXTI_IMR_IM6 EXTI_IMR_MR6
9894 #define EXTI_IMR_IM7 EXTI_IMR_MR7
9895 #define EXTI_IMR_IM8 EXTI_IMR_MR8
9896 #define EXTI_IMR_IM9 EXTI_IMR_MR9
9897 #define EXTI_IMR_IM10 EXTI_IMR_MR10
9898 #define EXTI_IMR_IM11 EXTI_IMR_MR11
9899 #define EXTI_IMR_IM12 EXTI_IMR_MR12
9900 #define EXTI_IMR_IM13 EXTI_IMR_MR13
9901 #define EXTI_IMR_IM14 EXTI_IMR_MR14
9902 #define EXTI_IMR_IM15 EXTI_IMR_MR15
9903 #define EXTI_IMR_IM16 EXTI_IMR_MR16
9904 #define EXTI_IMR_IM17 EXTI_IMR_MR17
9905 #define EXTI_IMR_IM18 EXTI_IMR_MR18
9906 #define EXTI_IMR_IM19 EXTI_IMR_MR19
9907 #define EXTI_IMR_IM20 EXTI_IMR_MR20
9908 #define EXTI_IMR_IM21 EXTI_IMR_MR21
9909 #define EXTI_IMR_IM22 EXTI_IMR_MR22
9910 #define EXTI_IMR_IM_Pos (0U)
9911 #define EXTI_IMR_IM_Msk (0x7FFFFFU << EXTI_IMR_IM_Pos) /*!< 0x007FFFFF */
9912 #define EXTI_IMR_IM EXTI_IMR_IM_Msk /*!< Interrupt Mask All */
9913
9914 /******************* Bit definition for EXTI_EMR register *******************/
9915 #define EXTI_EMR_MR0_Pos (0U)
9916 #define EXTI_EMR_MR0_Msk (0x1U << EXTI_EMR_MR0_Pos) /*!< 0x00000001 */
9917 #define EXTI_EMR_MR0 EXTI_EMR_MR0_Msk /*!< Event Mask on line 0 */
9918 #define EXTI_EMR_MR1_Pos (1U)
9919 #define EXTI_EMR_MR1_Msk (0x1U << EXTI_EMR_MR1_Pos) /*!< 0x00000002 */
9920 #define EXTI_EMR_MR1 EXTI_EMR_MR1_Msk /*!< Event Mask on line 1 */
9921 #define EXTI_EMR_MR2_Pos (2U)
9922 #define EXTI_EMR_MR2_Msk (0x1U << EXTI_EMR_MR2_Pos) /*!< 0x00000004 */
9923 #define EXTI_EMR_MR2 EXTI_EMR_MR2_Msk /*!< Event Mask on line 2 */
9924 #define EXTI_EMR_MR3_Pos (3U)
9925 #define EXTI_EMR_MR3_Msk (0x1U << EXTI_EMR_MR3_Pos) /*!< 0x00000008 */
9926 #define EXTI_EMR_MR3 EXTI_EMR_MR3_Msk /*!< Event Mask on line 3 */
9927 #define EXTI_EMR_MR4_Pos (4U)
9928 #define EXTI_EMR_MR4_Msk (0x1U << EXTI_EMR_MR4_Pos) /*!< 0x00000010 */
9929 #define EXTI_EMR_MR4 EXTI_EMR_MR4_Msk /*!< Event Mask on line 4 */
9930 #define EXTI_EMR_MR5_Pos (5U)
9931 #define EXTI_EMR_MR5_Msk (0x1U << EXTI_EMR_MR5_Pos) /*!< 0x00000020 */
9932 #define EXTI_EMR_MR5 EXTI_EMR_MR5_Msk /*!< Event Mask on line 5 */
9933 #define EXTI_EMR_MR6_Pos (6U)
9934 #define EXTI_EMR_MR6_Msk (0x1U << EXTI_EMR_MR6_Pos) /*!< 0x00000040 */
9935 #define EXTI_EMR_MR6 EXTI_EMR_MR6_Msk /*!< Event Mask on line 6 */
9936 #define EXTI_EMR_MR7_Pos (7U)
9937 #define EXTI_EMR_MR7_Msk (0x1U << EXTI_EMR_MR7_Pos) /*!< 0x00000080 */
9938 #define EXTI_EMR_MR7 EXTI_EMR_MR7_Msk /*!< Event Mask on line 7 */
9939 #define EXTI_EMR_MR8_Pos (8U)
9940 #define EXTI_EMR_MR8_Msk (0x1U << EXTI_EMR_MR8_Pos) /*!< 0x00000100 */
9941 #define EXTI_EMR_MR8 EXTI_EMR_MR8_Msk /*!< Event Mask on line 8 */
9942 #define EXTI_EMR_MR9_Pos (9U)
9943 #define EXTI_EMR_MR9_Msk (0x1U << EXTI_EMR_MR9_Pos) /*!< 0x00000200 */
9944 #define EXTI_EMR_MR9 EXTI_EMR_MR9_Msk /*!< Event Mask on line 9 */
9945 #define EXTI_EMR_MR10_Pos (10U)
9946 #define EXTI_EMR_MR10_Msk (0x1U << EXTI_EMR_MR10_Pos) /*!< 0x00000400 */
9947 #define EXTI_EMR_MR10 EXTI_EMR_MR10_Msk /*!< Event Mask on line 10 */
9948 #define EXTI_EMR_MR11_Pos (11U)
9949 #define EXTI_EMR_MR11_Msk (0x1U << EXTI_EMR_MR11_Pos) /*!< 0x00000800 */
9950 #define EXTI_EMR_MR11 EXTI_EMR_MR11_Msk /*!< Event Mask on line 11 */
9951 #define EXTI_EMR_MR12_Pos (12U)
9952 #define EXTI_EMR_MR12_Msk (0x1U << EXTI_EMR_MR12_Pos) /*!< 0x00001000 */
9953 #define EXTI_EMR_MR12 EXTI_EMR_MR12_Msk /*!< Event Mask on line 12 */
9954 #define EXTI_EMR_MR13_Pos (13U)
9955 #define EXTI_EMR_MR13_Msk (0x1U << EXTI_EMR_MR13_Pos) /*!< 0x00002000 */
9956 #define EXTI_EMR_MR13 EXTI_EMR_MR13_Msk /*!< Event Mask on line 13 */
9957 #define EXTI_EMR_MR14_Pos (14U)
9958 #define EXTI_EMR_MR14_Msk (0x1U << EXTI_EMR_MR14_Pos) /*!< 0x00004000 */
9959 #define EXTI_EMR_MR14 EXTI_EMR_MR14_Msk /*!< Event Mask on line 14 */
9960 #define EXTI_EMR_MR15_Pos (15U)
9961 #define EXTI_EMR_MR15_Msk (0x1U << EXTI_EMR_MR15_Pos) /*!< 0x00008000 */
9962 #define EXTI_EMR_MR15 EXTI_EMR_MR15_Msk /*!< Event Mask on line 15 */
9963 #define EXTI_EMR_MR16_Pos (16U)
9964 #define EXTI_EMR_MR16_Msk (0x1U << EXTI_EMR_MR16_Pos) /*!< 0x00010000 */
9965 #define EXTI_EMR_MR16 EXTI_EMR_MR16_Msk /*!< Event Mask on line 16 */
9966 #define EXTI_EMR_MR17_Pos (17U)
9967 #define EXTI_EMR_MR17_Msk (0x1U << EXTI_EMR_MR17_Pos) /*!< 0x00020000 */
9968 #define EXTI_EMR_MR17 EXTI_EMR_MR17_Msk /*!< Event Mask on line 17 */
9969 #define EXTI_EMR_MR18_Pos (18U)
9970 #define EXTI_EMR_MR18_Msk (0x1U << EXTI_EMR_MR18_Pos) /*!< 0x00040000 */
9971 #define EXTI_EMR_MR18 EXTI_EMR_MR18_Msk /*!< Event Mask on line 18 */
9972 #define EXTI_EMR_MR19_Pos (19U)
9973 #define EXTI_EMR_MR19_Msk (0x1U << EXTI_EMR_MR19_Pos) /*!< 0x00080000 */
9974 #define EXTI_EMR_MR19 EXTI_EMR_MR19_Msk /*!< Event Mask on line 19 */
9975 #define EXTI_EMR_MR20_Pos (20U)
9976 #define EXTI_EMR_MR20_Msk (0x1U << EXTI_EMR_MR20_Pos) /*!< 0x00100000 */
9977 #define EXTI_EMR_MR20 EXTI_EMR_MR20_Msk /*!< Event Mask on line 20 */
9978 #define EXTI_EMR_MR21_Pos (21U)
9979 #define EXTI_EMR_MR21_Msk (0x1U << EXTI_EMR_MR21_Pos) /*!< 0x00200000 */
9980 #define EXTI_EMR_MR21 EXTI_EMR_MR21_Msk /*!< Event Mask on line 21 */
9981 #define EXTI_EMR_MR22_Pos (22U)
9982 #define EXTI_EMR_MR22_Msk (0x1U << EXTI_EMR_MR22_Pos) /*!< 0x00400000 */
9983 #define EXTI_EMR_MR22 EXTI_EMR_MR22_Msk /*!< Event Mask on line 22 */
9984
9985 /* Reference Defines */
9986 #define EXTI_EMR_EM0 EXTI_EMR_MR0
9987 #define EXTI_EMR_EM1 EXTI_EMR_MR1
9988 #define EXTI_EMR_EM2 EXTI_EMR_MR2
9989 #define EXTI_EMR_EM3 EXTI_EMR_MR3
9990 #define EXTI_EMR_EM4 EXTI_EMR_MR4
9991 #define EXTI_EMR_EM5 EXTI_EMR_MR5
9992 #define EXTI_EMR_EM6 EXTI_EMR_MR6
9993 #define EXTI_EMR_EM7 EXTI_EMR_MR7
9994 #define EXTI_EMR_EM8 EXTI_EMR_MR8
9995 #define EXTI_EMR_EM9 EXTI_EMR_MR9
9996 #define EXTI_EMR_EM10 EXTI_EMR_MR10
9997 #define EXTI_EMR_EM11 EXTI_EMR_MR11
9998 #define EXTI_EMR_EM12 EXTI_EMR_MR12
9999 #define EXTI_EMR_EM13 EXTI_EMR_MR13
10000 #define EXTI_EMR_EM14 EXTI_EMR_MR14
10001 #define EXTI_EMR_EM15 EXTI_EMR_MR15
10002 #define EXTI_EMR_EM16 EXTI_EMR_MR16
10003 #define EXTI_EMR_EM17 EXTI_EMR_MR17
10004 #define EXTI_EMR_EM18 EXTI_EMR_MR18
10005 #define EXTI_EMR_EM19 EXTI_EMR_MR19
10006 #define EXTI_EMR_EM20 EXTI_EMR_MR20
10007 #define EXTI_EMR_EM21 EXTI_EMR_MR21
10008 #define EXTI_EMR_EM22 EXTI_EMR_MR22
10009
10010 /****************** Bit definition for EXTI_RTSR register *******************/
10011 #define EXTI_RTSR_TR0_Pos (0U)
10012 #define EXTI_RTSR_TR0_Msk (0x1U << EXTI_RTSR_TR0_Pos) /*!< 0x00000001 */
10013 #define EXTI_RTSR_TR0 EXTI_RTSR_TR0_Msk /*!< Rising trigger event configuration bit of line 0 */
10014 #define EXTI_RTSR_TR1_Pos (1U)
10015 #define EXTI_RTSR_TR1_Msk (0x1U << EXTI_RTSR_TR1_Pos) /*!< 0x00000002 */
10016 #define EXTI_RTSR_TR1 EXTI_RTSR_TR1_Msk /*!< Rising trigger event configuration bit of line 1 */
10017 #define EXTI_RTSR_TR2_Pos (2U)
10018 #define EXTI_RTSR_TR2_Msk (0x1U << EXTI_RTSR_TR2_Pos) /*!< 0x00000004 */
10019 #define EXTI_RTSR_TR2 EXTI_RTSR_TR2_Msk /*!< Rising trigger event configuration bit of line 2 */
10020 #define EXTI_RTSR_TR3_Pos (3U)
10021 #define EXTI_RTSR_TR3_Msk (0x1U << EXTI_RTSR_TR3_Pos) /*!< 0x00000008 */
10022 #define EXTI_RTSR_TR3 EXTI_RTSR_TR3_Msk /*!< Rising trigger event configuration bit of line 3 */
10023 #define EXTI_RTSR_TR4_Pos (4U)
10024 #define EXTI_RTSR_TR4_Msk (0x1U << EXTI_RTSR_TR4_Pos) /*!< 0x00000010 */
10025 #define EXTI_RTSR_TR4 EXTI_RTSR_TR4_Msk /*!< Rising trigger event configuration bit of line 4 */
10026 #define EXTI_RTSR_TR5_Pos (5U)
10027 #define EXTI_RTSR_TR5_Msk (0x1U << EXTI_RTSR_TR5_Pos) /*!< 0x00000020 */
10028 #define EXTI_RTSR_TR5 EXTI_RTSR_TR5_Msk /*!< Rising trigger event configuration bit of line 5 */
10029 #define EXTI_RTSR_TR6_Pos (6U)
10030 #define EXTI_RTSR_TR6_Msk (0x1U << EXTI_RTSR_TR6_Pos) /*!< 0x00000040 */
10031 #define EXTI_RTSR_TR6 EXTI_RTSR_TR6_Msk /*!< Rising trigger event configuration bit of line 6 */
10032 #define EXTI_RTSR_TR7_Pos (7U)
10033 #define EXTI_RTSR_TR7_Msk (0x1U << EXTI_RTSR_TR7_Pos) /*!< 0x00000080 */
10034 #define EXTI_RTSR_TR7 EXTI_RTSR_TR7_Msk /*!< Rising trigger event configuration bit of line 7 */
10035 #define EXTI_RTSR_TR8_Pos (8U)
10036 #define EXTI_RTSR_TR8_Msk (0x1U << EXTI_RTSR_TR8_Pos) /*!< 0x00000100 */
10037 #define EXTI_RTSR_TR8 EXTI_RTSR_TR8_Msk /*!< Rising trigger event configuration bit of line 8 */
10038 #define EXTI_RTSR_TR9_Pos (9U)
10039 #define EXTI_RTSR_TR9_Msk (0x1U << EXTI_RTSR_TR9_Pos) /*!< 0x00000200 */
10040 #define EXTI_RTSR_TR9 EXTI_RTSR_TR9_Msk /*!< Rising trigger event configuration bit of line 9 */
10041 #define EXTI_RTSR_TR10_Pos (10U)
10042 #define EXTI_RTSR_TR10_Msk (0x1U << EXTI_RTSR_TR10_Pos) /*!< 0x00000400 */
10043 #define EXTI_RTSR_TR10 EXTI_RTSR_TR10_Msk /*!< Rising trigger event configuration bit of line 10 */
10044 #define EXTI_RTSR_TR11_Pos (11U)
10045 #define EXTI_RTSR_TR11_Msk (0x1U << EXTI_RTSR_TR11_Pos) /*!< 0x00000800 */
10046 #define EXTI_RTSR_TR11 EXTI_RTSR_TR11_Msk /*!< Rising trigger event configuration bit of line 11 */
10047 #define EXTI_RTSR_TR12_Pos (12U)
10048 #define EXTI_RTSR_TR12_Msk (0x1U << EXTI_RTSR_TR12_Pos) /*!< 0x00001000 */
10049 #define EXTI_RTSR_TR12 EXTI_RTSR_TR12_Msk /*!< Rising trigger event configuration bit of line 12 */
10050 #define EXTI_RTSR_TR13_Pos (13U)
10051 #define EXTI_RTSR_TR13_Msk (0x1U << EXTI_RTSR_TR13_Pos) /*!< 0x00002000 */
10052 #define EXTI_RTSR_TR13 EXTI_RTSR_TR13_Msk /*!< Rising trigger event configuration bit of line 13 */
10053 #define EXTI_RTSR_TR14_Pos (14U)
10054 #define EXTI_RTSR_TR14_Msk (0x1U << EXTI_RTSR_TR14_Pos) /*!< 0x00004000 */
10055 #define EXTI_RTSR_TR14 EXTI_RTSR_TR14_Msk /*!< Rising trigger event configuration bit of line 14 */
10056 #define EXTI_RTSR_TR15_Pos (15U)
10057 #define EXTI_RTSR_TR15_Msk (0x1U << EXTI_RTSR_TR15_Pos) /*!< 0x00008000 */
10058 #define EXTI_RTSR_TR15 EXTI_RTSR_TR15_Msk /*!< Rising trigger event configuration bit of line 15 */
10059 #define EXTI_RTSR_TR16_Pos (16U)
10060 #define EXTI_RTSR_TR16_Msk (0x1U << EXTI_RTSR_TR16_Pos) /*!< 0x00010000 */
10061 #define EXTI_RTSR_TR16 EXTI_RTSR_TR16_Msk /*!< Rising trigger event configuration bit of line 16 */
10062 #define EXTI_RTSR_TR17_Pos (17U)
10063 #define EXTI_RTSR_TR17_Msk (0x1U << EXTI_RTSR_TR17_Pos) /*!< 0x00020000 */
10064 #define EXTI_RTSR_TR17 EXTI_RTSR_TR17_Msk /*!< Rising trigger event configuration bit of line 17 */
10065 #define EXTI_RTSR_TR18_Pos (18U)
10066 #define EXTI_RTSR_TR18_Msk (0x1U << EXTI_RTSR_TR18_Pos) /*!< 0x00040000 */
10067 #define EXTI_RTSR_TR18 EXTI_RTSR_TR18_Msk /*!< Rising trigger event configuration bit of line 18 */
10068 #define EXTI_RTSR_TR19_Pos (19U)
10069 #define EXTI_RTSR_TR19_Msk (0x1U << EXTI_RTSR_TR19_Pos) /*!< 0x00080000 */
10070 #define EXTI_RTSR_TR19 EXTI_RTSR_TR19_Msk /*!< Rising trigger event configuration bit of line 19 */
10071 #define EXTI_RTSR_TR20_Pos (20U)
10072 #define EXTI_RTSR_TR20_Msk (0x1U << EXTI_RTSR_TR20_Pos) /*!< 0x00100000 */
10073 #define EXTI_RTSR_TR20 EXTI_RTSR_TR20_Msk /*!< Rising trigger event configuration bit of line 20 */
10074 #define EXTI_RTSR_TR21_Pos (21U)
10075 #define EXTI_RTSR_TR21_Msk (0x1U << EXTI_RTSR_TR21_Pos) /*!< 0x00200000 */
10076 #define EXTI_RTSR_TR21 EXTI_RTSR_TR21_Msk /*!< Rising trigger event configuration bit of line 21 */
10077 #define EXTI_RTSR_TR22_Pos (22U)
10078 #define EXTI_RTSR_TR22_Msk (0x1U << EXTI_RTSR_TR22_Pos) /*!< 0x00400000 */
10079 #define EXTI_RTSR_TR22 EXTI_RTSR_TR22_Msk /*!< Rising trigger event configuration bit of line 22 */
10080
10081 /****************** Bit definition for EXTI_FTSR register *******************/
10082 #define EXTI_FTSR_TR0_Pos (0U)
10083 #define EXTI_FTSR_TR0_Msk (0x1U << EXTI_FTSR_TR0_Pos) /*!< 0x00000001 */
10084 #define EXTI_FTSR_TR0 EXTI_FTSR_TR0_Msk /*!< Falling trigger event configuration bit of line 0 */
10085 #define EXTI_FTSR_TR1_Pos (1U)
10086 #define EXTI_FTSR_TR1_Msk (0x1U << EXTI_FTSR_TR1_Pos) /*!< 0x00000002 */
10087 #define EXTI_FTSR_TR1 EXTI_FTSR_TR1_Msk /*!< Falling trigger event configuration bit of line 1 */
10088 #define EXTI_FTSR_TR2_Pos (2U)
10089 #define EXTI_FTSR_TR2_Msk (0x1U << EXTI_FTSR_TR2_Pos) /*!< 0x00000004 */
10090 #define EXTI_FTSR_TR2 EXTI_FTSR_TR2_Msk /*!< Falling trigger event configuration bit of line 2 */
10091 #define EXTI_FTSR_TR3_Pos (3U)
10092 #define EXTI_FTSR_TR3_Msk (0x1U << EXTI_FTSR_TR3_Pos) /*!< 0x00000008 */
10093 #define EXTI_FTSR_TR3 EXTI_FTSR_TR3_Msk /*!< Falling trigger event configuration bit of line 3 */
10094 #define EXTI_FTSR_TR4_Pos (4U)
10095 #define EXTI_FTSR_TR4_Msk (0x1U << EXTI_FTSR_TR4_Pos) /*!< 0x00000010 */
10096 #define EXTI_FTSR_TR4 EXTI_FTSR_TR4_Msk /*!< Falling trigger event configuration bit of line 4 */
10097 #define EXTI_FTSR_TR5_Pos (5U)
10098 #define EXTI_FTSR_TR5_Msk (0x1U << EXTI_FTSR_TR5_Pos) /*!< 0x00000020 */
10099 #define EXTI_FTSR_TR5 EXTI_FTSR_TR5_Msk /*!< Falling trigger event configuration bit of line 5 */
10100 #define EXTI_FTSR_TR6_Pos (6U)
10101 #define EXTI_FTSR_TR6_Msk (0x1U << EXTI_FTSR_TR6_Pos) /*!< 0x00000040 */
10102 #define EXTI_FTSR_TR6 EXTI_FTSR_TR6_Msk /*!< Falling trigger event configuration bit of line 6 */
10103 #define EXTI_FTSR_TR7_Pos (7U)
10104 #define EXTI_FTSR_TR7_Msk (0x1U << EXTI_FTSR_TR7_Pos) /*!< 0x00000080 */
10105 #define EXTI_FTSR_TR7 EXTI_FTSR_TR7_Msk /*!< Falling trigger event configuration bit of line 7 */
10106 #define EXTI_FTSR_TR8_Pos (8U)
10107 #define EXTI_FTSR_TR8_Msk (0x1U << EXTI_FTSR_TR8_Pos) /*!< 0x00000100 */
10108 #define EXTI_FTSR_TR8 EXTI_FTSR_TR8_Msk /*!< Falling trigger event configuration bit of line 8 */
10109 #define EXTI_FTSR_TR9_Pos (9U)
10110 #define EXTI_FTSR_TR9_Msk (0x1U << EXTI_FTSR_TR9_Pos) /*!< 0x00000200 */
10111 #define EXTI_FTSR_TR9 EXTI_FTSR_TR9_Msk /*!< Falling trigger event configuration bit of line 9 */
10112 #define EXTI_FTSR_TR10_Pos (10U)
10113 #define EXTI_FTSR_TR10_Msk (0x1U << EXTI_FTSR_TR10_Pos) /*!< 0x00000400 */
10114 #define EXTI_FTSR_TR10 EXTI_FTSR_TR10_Msk /*!< Falling trigger event configuration bit of line 10 */
10115 #define EXTI_FTSR_TR11_Pos (11U)
10116 #define EXTI_FTSR_TR11_Msk (0x1U << EXTI_FTSR_TR11_Pos) /*!< 0x00000800 */
10117 #define EXTI_FTSR_TR11 EXTI_FTSR_TR11_Msk /*!< Falling trigger event configuration bit of line 11 */
10118 #define EXTI_FTSR_TR12_Pos (12U)
10119 #define EXTI_FTSR_TR12_Msk (0x1U << EXTI_FTSR_TR12_Pos) /*!< 0x00001000 */
10120 #define EXTI_FTSR_TR12 EXTI_FTSR_TR12_Msk /*!< Falling trigger event configuration bit of line 12 */
10121 #define EXTI_FTSR_TR13_Pos (13U)
10122 #define EXTI_FTSR_TR13_Msk (0x1U << EXTI_FTSR_TR13_Pos) /*!< 0x00002000 */
10123 #define EXTI_FTSR_TR13 EXTI_FTSR_TR13_Msk /*!< Falling trigger event configuration bit of line 13 */
10124 #define EXTI_FTSR_TR14_Pos (14U)
10125 #define EXTI_FTSR_TR14_Msk (0x1U << EXTI_FTSR_TR14_Pos) /*!< 0x00004000 */
10126 #define EXTI_FTSR_TR14 EXTI_FTSR_TR14_Msk /*!< Falling trigger event configuration bit of line 14 */
10127 #define EXTI_FTSR_TR15_Pos (15U)
10128 #define EXTI_FTSR_TR15_Msk (0x1U << EXTI_FTSR_TR15_Pos) /*!< 0x00008000 */
10129 #define EXTI_FTSR_TR15 EXTI_FTSR_TR15_Msk /*!< Falling trigger event configuration bit of line 15 */
10130 #define EXTI_FTSR_TR16_Pos (16U)
10131 #define EXTI_FTSR_TR16_Msk (0x1U << EXTI_FTSR_TR16_Pos) /*!< 0x00010000 */
10132 #define EXTI_FTSR_TR16 EXTI_FTSR_TR16_Msk /*!< Falling trigger event configuration bit of line 16 */
10133 #define EXTI_FTSR_TR17_Pos (17U)
10134 #define EXTI_FTSR_TR17_Msk (0x1U << EXTI_FTSR_TR17_Pos) /*!< 0x00020000 */
10135 #define EXTI_FTSR_TR17 EXTI_FTSR_TR17_Msk /*!< Falling trigger event configuration bit of line 17 */
10136 #define EXTI_FTSR_TR18_Pos (18U)
10137 #define EXTI_FTSR_TR18_Msk (0x1U << EXTI_FTSR_TR18_Pos) /*!< 0x00040000 */
10138 #define EXTI_FTSR_TR18 EXTI_FTSR_TR18_Msk /*!< Falling trigger event configuration bit of line 18 */
10139 #define EXTI_FTSR_TR19_Pos (19U)
10140 #define EXTI_FTSR_TR19_Msk (0x1U << EXTI_FTSR_TR19_Pos) /*!< 0x00080000 */
10141 #define EXTI_FTSR_TR19 EXTI_FTSR_TR19_Msk /*!< Falling trigger event configuration bit of line 19 */
10142 #define EXTI_FTSR_TR20_Pos (20U)
10143 #define EXTI_FTSR_TR20_Msk (0x1U << EXTI_FTSR_TR20_Pos) /*!< 0x00100000 */
10144 #define EXTI_FTSR_TR20 EXTI_FTSR_TR20_Msk /*!< Falling trigger event configuration bit of line 20 */
10145 #define EXTI_FTSR_TR21_Pos (21U)
10146 #define EXTI_FTSR_TR21_Msk (0x1U << EXTI_FTSR_TR21_Pos) /*!< 0x00200000 */
10147 #define EXTI_FTSR_TR21 EXTI_FTSR_TR21_Msk /*!< Falling trigger event configuration bit of line 21 */
10148 #define EXTI_FTSR_TR22_Pos (22U)
10149 #define EXTI_FTSR_TR22_Msk (0x1U << EXTI_FTSR_TR22_Pos) /*!< 0x00400000 */
10150 #define EXTI_FTSR_TR22 EXTI_FTSR_TR22_Msk /*!< Falling trigger event configuration bit of line 22 */
10151
10152 /****************** Bit definition for EXTI_SWIER register ******************/
10153 #define EXTI_SWIER_SWIER0_Pos (0U)
10154 #define EXTI_SWIER_SWIER0_Msk (0x1U << EXTI_SWIER_SWIER0_Pos) /*!< 0x00000001 */
10155 #define EXTI_SWIER_SWIER0 EXTI_SWIER_SWIER0_Msk /*!< Software Interrupt on line 0 */
10156 #define EXTI_SWIER_SWIER1_Pos (1U)
10157 #define EXTI_SWIER_SWIER1_Msk (0x1U << EXTI_SWIER_SWIER1_Pos) /*!< 0x00000002 */
10158 #define EXTI_SWIER_SWIER1 EXTI_SWIER_SWIER1_Msk /*!< Software Interrupt on line 1 */
10159 #define EXTI_SWIER_SWIER2_Pos (2U)
10160 #define EXTI_SWIER_SWIER2_Msk (0x1U << EXTI_SWIER_SWIER2_Pos) /*!< 0x00000004 */
10161 #define EXTI_SWIER_SWIER2 EXTI_SWIER_SWIER2_Msk /*!< Software Interrupt on line 2 */
10162 #define EXTI_SWIER_SWIER3_Pos (3U)
10163 #define EXTI_SWIER_SWIER3_Msk (0x1U << EXTI_SWIER_SWIER3_Pos) /*!< 0x00000008 */
10164 #define EXTI_SWIER_SWIER3 EXTI_SWIER_SWIER3_Msk /*!< Software Interrupt on line 3 */
10165 #define EXTI_SWIER_SWIER4_Pos (4U)
10166 #define EXTI_SWIER_SWIER4_Msk (0x1U << EXTI_SWIER_SWIER4_Pos) /*!< 0x00000010 */
10167 #define EXTI_SWIER_SWIER4 EXTI_SWIER_SWIER4_Msk /*!< Software Interrupt on line 4 */
10168 #define EXTI_SWIER_SWIER5_Pos (5U)
10169 #define EXTI_SWIER_SWIER5_Msk (0x1U << EXTI_SWIER_SWIER5_Pos) /*!< 0x00000020 */
10170 #define EXTI_SWIER_SWIER5 EXTI_SWIER_SWIER5_Msk /*!< Software Interrupt on line 5 */
10171 #define EXTI_SWIER_SWIER6_Pos (6U)
10172 #define EXTI_SWIER_SWIER6_Msk (0x1U << EXTI_SWIER_SWIER6_Pos) /*!< 0x00000040 */
10173 #define EXTI_SWIER_SWIER6 EXTI_SWIER_SWIER6_Msk /*!< Software Interrupt on line 6 */
10174 #define EXTI_SWIER_SWIER7_Pos (7U)
10175 #define EXTI_SWIER_SWIER7_Msk (0x1U << EXTI_SWIER_SWIER7_Pos) /*!< 0x00000080 */
10176 #define EXTI_SWIER_SWIER7 EXTI_SWIER_SWIER7_Msk /*!< Software Interrupt on line 7 */
10177 #define EXTI_SWIER_SWIER8_Pos (8U)
10178 #define EXTI_SWIER_SWIER8_Msk (0x1U << EXTI_SWIER_SWIER8_Pos) /*!< 0x00000100 */
10179 #define EXTI_SWIER_SWIER8 EXTI_SWIER_SWIER8_Msk /*!< Software Interrupt on line 8 */
10180 #define EXTI_SWIER_SWIER9_Pos (9U)
10181 #define EXTI_SWIER_SWIER9_Msk (0x1U << EXTI_SWIER_SWIER9_Pos) /*!< 0x00000200 */
10182 #define EXTI_SWIER_SWIER9 EXTI_SWIER_SWIER9_Msk /*!< Software Interrupt on line 9 */
10183 #define EXTI_SWIER_SWIER10_Pos (10U)
10184 #define EXTI_SWIER_SWIER10_Msk (0x1U << EXTI_SWIER_SWIER10_Pos) /*!< 0x00000400 */
10185 #define EXTI_SWIER_SWIER10 EXTI_SWIER_SWIER10_Msk /*!< Software Interrupt on line 10 */
10186 #define EXTI_SWIER_SWIER11_Pos (11U)
10187 #define EXTI_SWIER_SWIER11_Msk (0x1U << EXTI_SWIER_SWIER11_Pos) /*!< 0x00000800 */
10188 #define EXTI_SWIER_SWIER11 EXTI_SWIER_SWIER11_Msk /*!< Software Interrupt on line 11 */
10189 #define EXTI_SWIER_SWIER12_Pos (12U)
10190 #define EXTI_SWIER_SWIER12_Msk (0x1U << EXTI_SWIER_SWIER12_Pos) /*!< 0x00001000 */
10191 #define EXTI_SWIER_SWIER12 EXTI_SWIER_SWIER12_Msk /*!< Software Interrupt on line 12 */
10192 #define EXTI_SWIER_SWIER13_Pos (13U)
10193 #define EXTI_SWIER_SWIER13_Msk (0x1U << EXTI_SWIER_SWIER13_Pos) /*!< 0x00002000 */
10194 #define EXTI_SWIER_SWIER13 EXTI_SWIER_SWIER13_Msk /*!< Software Interrupt on line 13 */
10195 #define EXTI_SWIER_SWIER14_Pos (14U)
10196 #define EXTI_SWIER_SWIER14_Msk (0x1U << EXTI_SWIER_SWIER14_Pos) /*!< 0x00004000 */
10197 #define EXTI_SWIER_SWIER14 EXTI_SWIER_SWIER14_Msk /*!< Software Interrupt on line 14 */
10198 #define EXTI_SWIER_SWIER15_Pos (15U)
10199 #define EXTI_SWIER_SWIER15_Msk (0x1U << EXTI_SWIER_SWIER15_Pos) /*!< 0x00008000 */
10200 #define EXTI_SWIER_SWIER15 EXTI_SWIER_SWIER15_Msk /*!< Software Interrupt on line 15 */
10201 #define EXTI_SWIER_SWIER16_Pos (16U)
10202 #define EXTI_SWIER_SWIER16_Msk (0x1U << EXTI_SWIER_SWIER16_Pos) /*!< 0x00010000 */
10203 #define EXTI_SWIER_SWIER16 EXTI_SWIER_SWIER16_Msk /*!< Software Interrupt on line 16 */
10204 #define EXTI_SWIER_SWIER17_Pos (17U)
10205 #define EXTI_SWIER_SWIER17_Msk (0x1U << EXTI_SWIER_SWIER17_Pos) /*!< 0x00020000 */
10206 #define EXTI_SWIER_SWIER17 EXTI_SWIER_SWIER17_Msk /*!< Software Interrupt on line 17 */
10207 #define EXTI_SWIER_SWIER18_Pos (18U)
10208 #define EXTI_SWIER_SWIER18_Msk (0x1U << EXTI_SWIER_SWIER18_Pos) /*!< 0x00040000 */
10209 #define EXTI_SWIER_SWIER18 EXTI_SWIER_SWIER18_Msk /*!< Software Interrupt on line 18 */
10210 #define EXTI_SWIER_SWIER19_Pos (19U)
10211 #define EXTI_SWIER_SWIER19_Msk (0x1U << EXTI_SWIER_SWIER19_Pos) /*!< 0x00080000 */
10212 #define EXTI_SWIER_SWIER19 EXTI_SWIER_SWIER19_Msk /*!< Software Interrupt on line 19 */
10213 #define EXTI_SWIER_SWIER20_Pos (20U)
10214 #define EXTI_SWIER_SWIER20_Msk (0x1U << EXTI_SWIER_SWIER20_Pos) /*!< 0x00100000 */
10215 #define EXTI_SWIER_SWIER20 EXTI_SWIER_SWIER20_Msk /*!< Software Interrupt on line 20 */
10216 #define EXTI_SWIER_SWIER21_Pos (21U)
10217 #define EXTI_SWIER_SWIER21_Msk (0x1U << EXTI_SWIER_SWIER21_Pos) /*!< 0x00200000 */
10218 #define EXTI_SWIER_SWIER21 EXTI_SWIER_SWIER21_Msk /*!< Software Interrupt on line 21 */
10219 #define EXTI_SWIER_SWIER22_Pos (22U)
10220 #define EXTI_SWIER_SWIER22_Msk (0x1U << EXTI_SWIER_SWIER22_Pos) /*!< 0x00400000 */
10221 #define EXTI_SWIER_SWIER22 EXTI_SWIER_SWIER22_Msk /*!< Software Interrupt on line 22 */
10222
10223 /******************* Bit definition for EXTI_PR register ********************/
10224 #define EXTI_PR_PR0_Pos (0U)
10225 #define EXTI_PR_PR0_Msk (0x1U << EXTI_PR_PR0_Pos) /*!< 0x00000001 */
10226 #define EXTI_PR_PR0 EXTI_PR_PR0_Msk /*!< Pending bit for line 0 */
10227 #define EXTI_PR_PR1_Pos (1U)
10228 #define EXTI_PR_PR1_Msk (0x1U << EXTI_PR_PR1_Pos) /*!< 0x00000002 */
10229 #define EXTI_PR_PR1 EXTI_PR_PR1_Msk /*!< Pending bit for line 1 */
10230 #define EXTI_PR_PR2_Pos (2U)
10231 #define EXTI_PR_PR2_Msk (0x1U << EXTI_PR_PR2_Pos) /*!< 0x00000004 */
10232 #define EXTI_PR_PR2 EXTI_PR_PR2_Msk /*!< Pending bit for line 2 */
10233 #define EXTI_PR_PR3_Pos (3U)
10234 #define EXTI_PR_PR3_Msk (0x1U << EXTI_PR_PR3_Pos) /*!< 0x00000008 */
10235 #define EXTI_PR_PR3 EXTI_PR_PR3_Msk /*!< Pending bit for line 3 */
10236 #define EXTI_PR_PR4_Pos (4U)
10237 #define EXTI_PR_PR4_Msk (0x1U << EXTI_PR_PR4_Pos) /*!< 0x00000010 */
10238 #define EXTI_PR_PR4 EXTI_PR_PR4_Msk /*!< Pending bit for line 4 */
10239 #define EXTI_PR_PR5_Pos (5U)
10240 #define EXTI_PR_PR5_Msk (0x1U << EXTI_PR_PR5_Pos) /*!< 0x00000020 */
10241 #define EXTI_PR_PR5 EXTI_PR_PR5_Msk /*!< Pending bit for line 5 */
10242 #define EXTI_PR_PR6_Pos (6U)
10243 #define EXTI_PR_PR6_Msk (0x1U << EXTI_PR_PR6_Pos) /*!< 0x00000040 */
10244 #define EXTI_PR_PR6 EXTI_PR_PR6_Msk /*!< Pending bit for line 6 */
10245 #define EXTI_PR_PR7_Pos (7U)
10246 #define EXTI_PR_PR7_Msk (0x1U << EXTI_PR_PR7_Pos) /*!< 0x00000080 */
10247 #define EXTI_PR_PR7 EXTI_PR_PR7_Msk /*!< Pending bit for line 7 */
10248 #define EXTI_PR_PR8_Pos (8U)
10249 #define EXTI_PR_PR8_Msk (0x1U << EXTI_PR_PR8_Pos) /*!< 0x00000100 */
10250 #define EXTI_PR_PR8 EXTI_PR_PR8_Msk /*!< Pending bit for line 8 */
10251 #define EXTI_PR_PR9_Pos (9U)
10252 #define EXTI_PR_PR9_Msk (0x1U << EXTI_PR_PR9_Pos) /*!< 0x00000200 */
10253 #define EXTI_PR_PR9 EXTI_PR_PR9_Msk /*!< Pending bit for line 9 */
10254 #define EXTI_PR_PR10_Pos (10U)
10255 #define EXTI_PR_PR10_Msk (0x1U << EXTI_PR_PR10_Pos) /*!< 0x00000400 */
10256 #define EXTI_PR_PR10 EXTI_PR_PR10_Msk /*!< Pending bit for line 10 */
10257 #define EXTI_PR_PR11_Pos (11U)
10258 #define EXTI_PR_PR11_Msk (0x1U << EXTI_PR_PR11_Pos) /*!< 0x00000800 */
10259 #define EXTI_PR_PR11 EXTI_PR_PR11_Msk /*!< Pending bit for line 11 */
10260 #define EXTI_PR_PR12_Pos (12U)
10261 #define EXTI_PR_PR12_Msk (0x1U << EXTI_PR_PR12_Pos) /*!< 0x00001000 */
10262 #define EXTI_PR_PR12 EXTI_PR_PR12_Msk /*!< Pending bit for line 12 */
10263 #define EXTI_PR_PR13_Pos (13U)
10264 #define EXTI_PR_PR13_Msk (0x1U << EXTI_PR_PR13_Pos) /*!< 0x00002000 */
10265 #define EXTI_PR_PR13 EXTI_PR_PR13_Msk /*!< Pending bit for line 13 */
10266 #define EXTI_PR_PR14_Pos (14U)
10267 #define EXTI_PR_PR14_Msk (0x1U << EXTI_PR_PR14_Pos) /*!< 0x00004000 */
10268 #define EXTI_PR_PR14 EXTI_PR_PR14_Msk /*!< Pending bit for line 14 */
10269 #define EXTI_PR_PR15_Pos (15U)
10270 #define EXTI_PR_PR15_Msk (0x1U << EXTI_PR_PR15_Pos) /*!< 0x00008000 */
10271 #define EXTI_PR_PR15 EXTI_PR_PR15_Msk /*!< Pending bit for line 15 */
10272 #define EXTI_PR_PR16_Pos (16U)
10273 #define EXTI_PR_PR16_Msk (0x1U << EXTI_PR_PR16_Pos) /*!< 0x00010000 */
10274 #define EXTI_PR_PR16 EXTI_PR_PR16_Msk /*!< Pending bit for line 16 */
10275 #define EXTI_PR_PR17_Pos (17U)
10276 #define EXTI_PR_PR17_Msk (0x1U << EXTI_PR_PR17_Pos) /*!< 0x00020000 */
10277 #define EXTI_PR_PR17 EXTI_PR_PR17_Msk /*!< Pending bit for line 17 */
10278 #define EXTI_PR_PR18_Pos (18U)
10279 #define EXTI_PR_PR18_Msk (0x1U << EXTI_PR_PR18_Pos) /*!< 0x00040000 */
10280 #define EXTI_PR_PR18 EXTI_PR_PR18_Msk /*!< Pending bit for line 18 */
10281 #define EXTI_PR_PR19_Pos (19U)
10282 #define EXTI_PR_PR19_Msk (0x1U << EXTI_PR_PR19_Pos) /*!< 0x00080000 */
10283 #define EXTI_PR_PR19 EXTI_PR_PR19_Msk /*!< Pending bit for line 19 */
10284 #define EXTI_PR_PR20_Pos (20U)
10285 #define EXTI_PR_PR20_Msk (0x1U << EXTI_PR_PR20_Pos) /*!< 0x00100000 */
10286 #define EXTI_PR_PR20 EXTI_PR_PR20_Msk /*!< Pending bit for line 20 */
10287 #define EXTI_PR_PR21_Pos (21U)
10288 #define EXTI_PR_PR21_Msk (0x1U << EXTI_PR_PR21_Pos) /*!< 0x00200000 */
10289 #define EXTI_PR_PR21 EXTI_PR_PR21_Msk /*!< Pending bit for line 21 */
10290 #define EXTI_PR_PR22_Pos (22U)
10291 #define EXTI_PR_PR22_Msk (0x1U << EXTI_PR_PR22_Pos) /*!< 0x00400000 */
10292 #define EXTI_PR_PR22 EXTI_PR_PR22_Msk /*!< Pending bit for line 22 */
10293
10294 /******************************************************************************/
10295 /* */
10296 /* FLASH */
10297 /* */
10298 /******************************************************************************/
10299 /******************* Bits definition for FLASH_ACR register *****************/
10300 #define FLASH_ACR_LATENCY_Pos (0U)
10301 #define FLASH_ACR_LATENCY_Msk (0xFU << FLASH_ACR_LATENCY_Pos) /*!< 0x0000000F */
10302 #define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk
10303 #define FLASH_ACR_LATENCY_0WS 0x00000000U
10304 #define FLASH_ACR_LATENCY_1WS 0x00000001U
10305 #define FLASH_ACR_LATENCY_2WS 0x00000002U
10306 #define FLASH_ACR_LATENCY_3WS 0x00000003U
10307 #define FLASH_ACR_LATENCY_4WS 0x00000004U
10308 #define FLASH_ACR_LATENCY_5WS 0x00000005U
10309 #define FLASH_ACR_LATENCY_6WS 0x00000006U
10310 #define FLASH_ACR_LATENCY_7WS 0x00000007U
10311
10312 #define FLASH_ACR_LATENCY_8WS 0x00000008U
10313 #define FLASH_ACR_LATENCY_9WS 0x00000009U
10314 #define FLASH_ACR_LATENCY_10WS 0x0000000AU
10315 #define FLASH_ACR_LATENCY_11WS 0x0000000BU
10316 #define FLASH_ACR_LATENCY_12WS 0x0000000CU
10317 #define FLASH_ACR_LATENCY_13WS 0x0000000DU
10318 #define FLASH_ACR_LATENCY_14WS 0x0000000EU
10319 #define FLASH_ACR_LATENCY_15WS 0x0000000FU
10320 #define FLASH_ACR_PRFTEN_Pos (8U)
10321 #define FLASH_ACR_PRFTEN_Msk (0x1U << FLASH_ACR_PRFTEN_Pos) /*!< 0x00000100 */
10322 #define FLASH_ACR_PRFTEN FLASH_ACR_PRFTEN_Msk
10323 #define FLASH_ACR_ICEN_Pos (9U)
10324 #define FLASH_ACR_ICEN_Msk (0x1U << FLASH_ACR_ICEN_Pos) /*!< 0x00000200 */
10325 #define FLASH_ACR_ICEN FLASH_ACR_ICEN_Msk
10326 #define FLASH_ACR_DCEN_Pos (10U)
10327 #define FLASH_ACR_DCEN_Msk (0x1U << FLASH_ACR_DCEN_Pos) /*!< 0x00000400 */
10328 #define FLASH_ACR_DCEN FLASH_ACR_DCEN_Msk
10329 #define FLASH_ACR_ICRST_Pos (11U)
10330 #define FLASH_ACR_ICRST_Msk (0x1U << FLASH_ACR_ICRST_Pos) /*!< 0x00000800 */
10331 #define FLASH_ACR_ICRST FLASH_ACR_ICRST_Msk
10332 #define FLASH_ACR_DCRST_Pos (12U)
10333 #define FLASH_ACR_DCRST_Msk (0x1U << FLASH_ACR_DCRST_Pos) /*!< 0x00001000 */
10334 #define FLASH_ACR_DCRST FLASH_ACR_DCRST_Msk
10335 #define FLASH_ACR_BYTE0_ADDRESS_Pos (10U)
10336 #define FLASH_ACR_BYTE0_ADDRESS_Msk (0x10008FU << FLASH_ACR_BYTE0_ADDRESS_Pos) /*!< 0x40023C00 */
10337 #define FLASH_ACR_BYTE0_ADDRESS FLASH_ACR_BYTE0_ADDRESS_Msk
10338 #define FLASH_ACR_BYTE2_ADDRESS_Pos (0U)
10339 #define FLASH_ACR_BYTE2_ADDRESS_Msk (0x40023C03U << FLASH_ACR_BYTE2_ADDRESS_Pos) /*!< 0x40023C03 */
10340 #define FLASH_ACR_BYTE2_ADDRESS FLASH_ACR_BYTE2_ADDRESS_Msk
10341
10342 /******************* Bits definition for FLASH_SR register ******************/
10343 #define FLASH_SR_EOP_Pos (0U)
10344 #define FLASH_SR_EOP_Msk (0x1U << FLASH_SR_EOP_Pos) /*!< 0x00000001 */
10345 #define FLASH_SR_EOP FLASH_SR_EOP_Msk
10346 #define FLASH_SR_SOP_Pos (1U)
10347 #define FLASH_SR_SOP_Msk (0x1U << FLASH_SR_SOP_Pos) /*!< 0x00000002 */
10348 #define FLASH_SR_SOP FLASH_SR_SOP_Msk
10349 #define FLASH_SR_WRPERR_Pos (4U)
10350 #define FLASH_SR_WRPERR_Msk (0x1U << FLASH_SR_WRPERR_Pos) /*!< 0x00000010 */
10351 #define FLASH_SR_WRPERR FLASH_SR_WRPERR_Msk
10352 #define FLASH_SR_PGAERR_Pos (5U)
10353 #define FLASH_SR_PGAERR_Msk (0x1U << FLASH_SR_PGAERR_Pos) /*!< 0x00000020 */
10354 #define FLASH_SR_PGAERR FLASH_SR_PGAERR_Msk
10355 #define FLASH_SR_PGPERR_Pos (6U)
10356 #define FLASH_SR_PGPERR_Msk (0x1U << FLASH_SR_PGPERR_Pos) /*!< 0x00000040 */
10357 #define FLASH_SR_PGPERR FLASH_SR_PGPERR_Msk
10358 #define FLASH_SR_PGSERR_Pos (7U)
10359 #define FLASH_SR_PGSERR_Msk (0x1U << FLASH_SR_PGSERR_Pos) /*!< 0x00000080 */
10360 #define FLASH_SR_PGSERR FLASH_SR_PGSERR_Msk
10361 #define FLASH_SR_RDERR_Pos (8U)
10362 #define FLASH_SR_RDERR_Msk (0x1U << FLASH_SR_RDERR_Pos) /*!< 0x00000100 */
10363 #define FLASH_SR_RDERR FLASH_SR_RDERR_Msk
10364 #define FLASH_SR_BSY_Pos (16U)
10365 #define FLASH_SR_BSY_Msk (0x1U << FLASH_SR_BSY_Pos) /*!< 0x00010000 */
10366 #define FLASH_SR_BSY FLASH_SR_BSY_Msk
10367
10368 /******************* Bits definition for FLASH_CR register ******************/
10369 #define FLASH_CR_PG_Pos (0U)
10370 #define FLASH_CR_PG_Msk (0x1U << FLASH_CR_PG_Pos) /*!< 0x00000001 */
10371 #define FLASH_CR_PG FLASH_CR_PG_Msk
10372 #define FLASH_CR_SER_Pos (1U)
10373 #define FLASH_CR_SER_Msk (0x1U << FLASH_CR_SER_Pos) /*!< 0x00000002 */
10374 #define FLASH_CR_SER FLASH_CR_SER_Msk
10375 #define FLASH_CR_MER_Pos (2U)
10376 #define FLASH_CR_MER_Msk (0x1U << FLASH_CR_MER_Pos) /*!< 0x00000004 */
10377 #define FLASH_CR_MER FLASH_CR_MER_Msk
10378 #define FLASH_CR_MER1 FLASH_CR_MER
10379 #define FLASH_CR_SNB_Pos (3U)
10380 #define FLASH_CR_SNB_Msk (0x1FU << FLASH_CR_SNB_Pos) /*!< 0x000000F8 */
10381 #define FLASH_CR_SNB FLASH_CR_SNB_Msk
10382 #define FLASH_CR_SNB_0 (0x01U << FLASH_CR_SNB_Pos) /*!< 0x00000008 */
10383 #define FLASH_CR_SNB_1 (0x02U << FLASH_CR_SNB_Pos) /*!< 0x00000010 */
10384 #define FLASH_CR_SNB_2 (0x04U << FLASH_CR_SNB_Pos) /*!< 0x00000020 */
10385 #define FLASH_CR_SNB_3 (0x08U << FLASH_CR_SNB_Pos) /*!< 0x00000040 */
10386 #define FLASH_CR_SNB_4 (0x10U << FLASH_CR_SNB_Pos) /*!< 0x00000080 */
10387 #define FLASH_CR_PSIZE_Pos (8U)
10388 #define FLASH_CR_PSIZE_Msk (0x3U << FLASH_CR_PSIZE_Pos) /*!< 0x00000300 */
10389 #define FLASH_CR_PSIZE FLASH_CR_PSIZE_Msk
10390 #define FLASH_CR_PSIZE_0 (0x1U << FLASH_CR_PSIZE_Pos) /*!< 0x00000100 */
10391 #define FLASH_CR_PSIZE_1 (0x2U << FLASH_CR_PSIZE_Pos) /*!< 0x00000200 */
10392 #define FLASH_CR_MER2_Pos (15U)
10393 #define FLASH_CR_MER2_Msk (0x1U << FLASH_CR_MER2_Pos) /*!< 0x00008000 */
10394 #define FLASH_CR_MER2 FLASH_CR_MER2_Msk
10395 #define FLASH_CR_STRT_Pos (16U)
10396 #define FLASH_CR_STRT_Msk (0x1U << FLASH_CR_STRT_Pos) /*!< 0x00010000 */
10397 #define FLASH_CR_STRT FLASH_CR_STRT_Msk
10398 #define FLASH_CR_EOPIE_Pos (24U)
10399 #define FLASH_CR_EOPIE_Msk (0x1U << FLASH_CR_EOPIE_Pos) /*!< 0x01000000 */
10400 #define FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk
10401 #define FLASH_CR_LOCK_Pos (31U)
10402 #define FLASH_CR_LOCK_Msk (0x1U << FLASH_CR_LOCK_Pos) /*!< 0x80000000 */
10403 #define FLASH_CR_LOCK FLASH_CR_LOCK_Msk
10404
10405 /******************* Bits definition for FLASH_OPTCR register ***************/
10406 #define FLASH_OPTCR_OPTLOCK_Pos (0U)
10407 #define FLASH_OPTCR_OPTLOCK_Msk (0x1U << FLASH_OPTCR_OPTLOCK_Pos) /*!< 0x00000001 */
10408 #define FLASH_OPTCR_OPTLOCK FLASH_OPTCR_OPTLOCK_Msk
10409 #define FLASH_OPTCR_OPTSTRT_Pos (1U)
10410 #define FLASH_OPTCR_OPTSTRT_Msk (0x1U << FLASH_OPTCR_OPTSTRT_Pos) /*!< 0x00000002 */
10411 #define FLASH_OPTCR_OPTSTRT FLASH_OPTCR_OPTSTRT_Msk
10412
10413 #define FLASH_OPTCR_BOR_LEV_0 0x00000004U
10414 #define FLASH_OPTCR_BOR_LEV_1 0x00000008U
10415 #define FLASH_OPTCR_BOR_LEV_Pos (2U)
10416 #define FLASH_OPTCR_BOR_LEV_Msk (0x3U << FLASH_OPTCR_BOR_LEV_Pos) /*!< 0x0000000C */
10417 #define FLASH_OPTCR_BOR_LEV FLASH_OPTCR_BOR_LEV_Msk
10418 #define FLASH_OPTCR_BFB2_Pos (4U)
10419 #define FLASH_OPTCR_BFB2_Msk (0x1U << FLASH_OPTCR_BFB2_Pos) /*!< 0x00000010 */
10420 #define FLASH_OPTCR_BFB2 FLASH_OPTCR_BFB2_Msk
10421 #define FLASH_OPTCR_WDG_SW_Pos (5U)
10422 #define FLASH_OPTCR_WDG_SW_Msk (0x1U << FLASH_OPTCR_WDG_SW_Pos) /*!< 0x00000020 */
10423 #define FLASH_OPTCR_WDG_SW FLASH_OPTCR_WDG_SW_Msk
10424 #define FLASH_OPTCR_nRST_STOP_Pos (6U)
10425 #define FLASH_OPTCR_nRST_STOP_Msk (0x1U << FLASH_OPTCR_nRST_STOP_Pos) /*!< 0x00000040 */
10426 #define FLASH_OPTCR_nRST_STOP FLASH_OPTCR_nRST_STOP_Msk
10427 #define FLASH_OPTCR_nRST_STDBY_Pos (7U)
10428 #define FLASH_OPTCR_nRST_STDBY_Msk (0x1U << FLASH_OPTCR_nRST_STDBY_Pos) /*!< 0x00000080 */
10429 #define FLASH_OPTCR_nRST_STDBY FLASH_OPTCR_nRST_STDBY_Msk
10430 #define FLASH_OPTCR_RDP_Pos (8U)
10431 #define FLASH_OPTCR_RDP_Msk (0xFFU << FLASH_OPTCR_RDP_Pos) /*!< 0x0000FF00 */
10432 #define FLASH_OPTCR_RDP FLASH_OPTCR_RDP_Msk
10433 #define FLASH_OPTCR_RDP_0 (0x01U << FLASH_OPTCR_RDP_Pos) /*!< 0x00000100 */
10434 #define FLASH_OPTCR_RDP_1 (0x02U << FLASH_OPTCR_RDP_Pos) /*!< 0x00000200 */
10435 #define FLASH_OPTCR_RDP_2 (0x04U << FLASH_OPTCR_RDP_Pos) /*!< 0x00000400 */
10436 #define FLASH_OPTCR_RDP_3 (0x08U << FLASH_OPTCR_RDP_Pos) /*!< 0x00000800 */
10437 #define FLASH_OPTCR_RDP_4 (0x10U << FLASH_OPTCR_RDP_Pos) /*!< 0x00001000 */
10438 #define FLASH_OPTCR_RDP_5 (0x20U << FLASH_OPTCR_RDP_Pos) /*!< 0x00002000 */
10439 #define FLASH_OPTCR_RDP_6 (0x40U << FLASH_OPTCR_RDP_Pos) /*!< 0x00004000 */
10440 #define FLASH_OPTCR_RDP_7 (0x80U << FLASH_OPTCR_RDP_Pos) /*!< 0x00008000 */
10441 #define FLASH_OPTCR_nWRP_Pos (16U)
10442 #define FLASH_OPTCR_nWRP_Msk (0xFFFU << FLASH_OPTCR_nWRP_Pos) /*!< 0x0FFF0000 */
10443 #define FLASH_OPTCR_nWRP FLASH_OPTCR_nWRP_Msk
10444 #define FLASH_OPTCR_nWRP_0 0x00010000U
10445 #define FLASH_OPTCR_nWRP_1 0x00020000U
10446 #define FLASH_OPTCR_nWRP_2 0x00040000U
10447 #define FLASH_OPTCR_nWRP_3 0x00080000U
10448 #define FLASH_OPTCR_nWRP_4 0x00100000U
10449 #define FLASH_OPTCR_nWRP_5 0x00200000U
10450 #define FLASH_OPTCR_nWRP_6 0x00400000U
10451 #define FLASH_OPTCR_nWRP_7 0x00800000U
10452 #define FLASH_OPTCR_nWRP_8 0x01000000U
10453 #define FLASH_OPTCR_nWRP_9 0x02000000U
10454 #define FLASH_OPTCR_nWRP_10 0x04000000U
10455 #define FLASH_OPTCR_nWRP_11 0x08000000U
10456 #define FLASH_OPTCR_DB1M_Pos (30U)
10457 #define FLASH_OPTCR_DB1M_Msk (0x1U << FLASH_OPTCR_DB1M_Pos) /*!< 0x40000000 */
10458 #define FLASH_OPTCR_DB1M FLASH_OPTCR_DB1M_Msk
10459 #define FLASH_OPTCR_SPRMOD_Pos (31U)
10460 #define FLASH_OPTCR_SPRMOD_Msk (0x1U << FLASH_OPTCR_SPRMOD_Pos) /*!< 0x80000000 */
10461 #define FLASH_OPTCR_SPRMOD FLASH_OPTCR_SPRMOD_Msk
10462
10463 /****************** Bits definition for FLASH_OPTCR1 register ***************/
10464 #define FLASH_OPTCR1_nWRP_Pos (16U)
10465 #define FLASH_OPTCR1_nWRP_Msk (0xFFFU << FLASH_OPTCR1_nWRP_Pos) /*!< 0x0FFF0000 */
10466 #define FLASH_OPTCR1_nWRP FLASH_OPTCR1_nWRP_Msk
10467 #define FLASH_OPTCR1_nWRP_0 (0x001U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00010000 */
10468 #define FLASH_OPTCR1_nWRP_1 (0x002U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00020000 */
10469 #define FLASH_OPTCR1_nWRP_2 (0x004U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00040000 */
10470 #define FLASH_OPTCR1_nWRP_3 (0x008U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00080000 */
10471 #define FLASH_OPTCR1_nWRP_4 (0x010U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00100000 */
10472 #define FLASH_OPTCR1_nWRP_5 (0x020U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00200000 */
10473 #define FLASH_OPTCR1_nWRP_6 (0x040U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00400000 */
10474 #define FLASH_OPTCR1_nWRP_7 (0x080U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x00800000 */
10475 #define FLASH_OPTCR1_nWRP_8 (0x100U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x01000000 */
10476 #define FLASH_OPTCR1_nWRP_9 (0x200U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x02000000 */
10477 #define FLASH_OPTCR1_nWRP_10 (0x400U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x04000000 */
10478 #define FLASH_OPTCR1_nWRP_11 (0x800U << FLASH_OPTCR1_nWRP_Pos) /*!< 0x08000000 */
10479
10480 /******************************************************************************/
10481 /* */
10482 /* Flexible Memory Controller */
10483 /* */
10484 /******************************************************************************/
10485 /****************** Bit definition for FMC_BCR1 register *******************/
10486 #define FMC_BCR1_MBKEN_Pos (0U)
10487 #define FMC_BCR1_MBKEN_Msk (0x1U << FMC_BCR1_MBKEN_Pos) /*!< 0x00000001 */
10488 #define FMC_BCR1_MBKEN FMC_BCR1_MBKEN_Msk /*!<Memory bank enable bit */
10489 #define FMC_BCR1_MUXEN_Pos (1U)
10490 #define FMC_BCR1_MUXEN_Msk (0x1U << FMC_BCR1_MUXEN_Pos) /*!< 0x00000002 */
10491 #define FMC_BCR1_MUXEN FMC_BCR1_MUXEN_Msk /*!<Address/data multiplexing enable bit */
10492
10493 #define FMC_BCR1_MTYP_Pos (2U)
10494 #define FMC_BCR1_MTYP_Msk (0x3U << FMC_BCR1_MTYP_Pos) /*!< 0x0000000C */
10495 #define FMC_BCR1_MTYP FMC_BCR1_MTYP_Msk /*!<MTYP[1:0] bits (Memory type) */
10496 #define FMC_BCR1_MTYP_0 (0x1U << FMC_BCR1_MTYP_Pos) /*!< 0x00000004 */
10497 #define FMC_BCR1_MTYP_1 (0x2U << FMC_BCR1_MTYP_Pos) /*!< 0x00000008 */
10498
10499 #define FMC_BCR1_MWID_Pos (4U)
10500 #define FMC_BCR1_MWID_Msk (0x3U << FMC_BCR1_MWID_Pos) /*!< 0x00000030 */
10501 #define FMC_BCR1_MWID FMC_BCR1_MWID_Msk /*!<MWID[1:0] bits (Memory data bus width) */
10502 #define FMC_BCR1_MWID_0 (0x1U << FMC_BCR1_MWID_Pos) /*!< 0x00000010 */
10503 #define FMC_BCR1_MWID_1 (0x2U << FMC_BCR1_MWID_Pos) /*!< 0x00000020 */
10504
10505 #define FMC_BCR1_FACCEN_Pos (6U)
10506 #define FMC_BCR1_FACCEN_Msk (0x1U << FMC_BCR1_FACCEN_Pos) /*!< 0x00000040 */
10507 #define FMC_BCR1_FACCEN FMC_BCR1_FACCEN_Msk /*!<Flash access enable */
10508 #define FMC_BCR1_BURSTEN_Pos (8U)
10509 #define FMC_BCR1_BURSTEN_Msk (0x1U << FMC_BCR1_BURSTEN_Pos) /*!< 0x00000100 */
10510 #define FMC_BCR1_BURSTEN FMC_BCR1_BURSTEN_Msk /*!<Burst enable bit */
10511 #define FMC_BCR1_WAITPOL_Pos (9U)
10512 #define FMC_BCR1_WAITPOL_Msk (0x1U << FMC_BCR1_WAITPOL_Pos) /*!< 0x00000200 */
10513 #define FMC_BCR1_WAITPOL FMC_BCR1_WAITPOL_Msk /*!<Wait signal polarity bit */
10514 #define FMC_BCR1_WAITCFG_Pos (11U)
10515 #define FMC_BCR1_WAITCFG_Msk (0x1U << FMC_BCR1_WAITCFG_Pos) /*!< 0x00000800 */
10516 #define FMC_BCR1_WAITCFG FMC_BCR1_WAITCFG_Msk /*!<Wait timing configuration */
10517 #define FMC_BCR1_WREN_Pos (12U)
10518 #define FMC_BCR1_WREN_Msk (0x1U << FMC_BCR1_WREN_Pos) /*!< 0x00001000 */
10519 #define FMC_BCR1_WREN FMC_BCR1_WREN_Msk /*!<Write enable bit */
10520 #define FMC_BCR1_WAITEN_Pos (13U)
10521 #define FMC_BCR1_WAITEN_Msk (0x1U << FMC_BCR1_WAITEN_Pos) /*!< 0x00002000 */
10522 #define FMC_BCR1_WAITEN FMC_BCR1_WAITEN_Msk /*!<Wait enable bit */
10523 #define FMC_BCR1_EXTMOD_Pos (14U)
10524 #define FMC_BCR1_EXTMOD_Msk (0x1U << FMC_BCR1_EXTMOD_Pos) /*!< 0x00004000 */
10525 #define FMC_BCR1_EXTMOD FMC_BCR1_EXTMOD_Msk /*!<Extended mode enable */
10526 #define FMC_BCR1_ASYNCWAIT_Pos (15U)
10527 #define FMC_BCR1_ASYNCWAIT_Msk (0x1U << FMC_BCR1_ASYNCWAIT_Pos) /*!< 0x00008000 */
10528 #define FMC_BCR1_ASYNCWAIT FMC_BCR1_ASYNCWAIT_Msk /*!<Asynchronous wait */
10529 #define FMC_BCR1_CPSIZE_Pos (16U)
10530 #define FMC_BCR1_CPSIZE_Msk (0x7U << FMC_BCR1_CPSIZE_Pos) /*!< 0x00070000 */
10531 #define FMC_BCR1_CPSIZE FMC_BCR1_CPSIZE_Msk /*!<CRAM page size */
10532 #define FMC_BCR1_CPSIZE_0 (0x1U << FMC_BCR1_CPSIZE_Pos) /*!< 0x00010000 */
10533 #define FMC_BCR1_CPSIZE_1 (0x2U << FMC_BCR1_CPSIZE_Pos) /*!< 0x00020000 */
10534 #define FMC_BCR1_CPSIZE_2 (0x4U << FMC_BCR1_CPSIZE_Pos) /*!< 0x00040000 */
10535 #define FMC_BCR1_CBURSTRW_Pos (19U)
10536 #define FMC_BCR1_CBURSTRW_Msk (0x1U << FMC_BCR1_CBURSTRW_Pos) /*!< 0x00080000 */
10537 #define FMC_BCR1_CBURSTRW FMC_BCR1_CBURSTRW_Msk /*!<Write burst enable */
10538 #define FMC_BCR1_CCLKEN_Pos (20U)
10539 #define FMC_BCR1_CCLKEN_Msk (0x1U << FMC_BCR1_CCLKEN_Pos) /*!< 0x00100000 */
10540 #define FMC_BCR1_CCLKEN FMC_BCR1_CCLKEN_Msk /*!<Continous clock enable */
10541 #define FMC_BCR1_WFDIS_Pos (21U)
10542 #define FMC_BCR1_WFDIS_Msk (0x1U << FMC_BCR1_WFDIS_Pos) /*!< 0x00200000 */
10543 #define FMC_BCR1_WFDIS FMC_BCR1_WFDIS_Msk /*!<Write FIFO Disable */
10544
10545 /****************** Bit definition for FMC_BCR2 register *******************/
10546 #define FMC_BCR2_MBKEN_Pos (0U)
10547 #define FMC_BCR2_MBKEN_Msk (0x1U << FMC_BCR2_MBKEN_Pos) /*!< 0x00000001 */
10548 #define FMC_BCR2_MBKEN FMC_BCR2_MBKEN_Msk /*!<Memory bank enable bit */
10549 #define FMC_BCR2_MUXEN_Pos (1U)
10550 #define FMC_BCR2_MUXEN_Msk (0x1U << FMC_BCR2_MUXEN_Pos) /*!< 0x00000002 */
10551 #define FMC_BCR2_MUXEN FMC_BCR2_MUXEN_Msk /*!<Address/data multiplexing enable bit */
10552
10553 #define FMC_BCR2_MTYP_Pos (2U)
10554 #define FMC_BCR2_MTYP_Msk (0x3U << FMC_BCR2_MTYP_Pos) /*!< 0x0000000C */
10555 #define FMC_BCR2_MTYP FMC_BCR2_MTYP_Msk /*!<MTYP[1:0] bits (Memory type) */
10556 #define FMC_BCR2_MTYP_0 (0x1U << FMC_BCR2_MTYP_Pos) /*!< 0x00000004 */
10557 #define FMC_BCR2_MTYP_1 (0x2U << FMC_BCR2_MTYP_Pos) /*!< 0x00000008 */
10558
10559 #define FMC_BCR2_MWID_Pos (4U)
10560 #define FMC_BCR2_MWID_Msk (0x3U << FMC_BCR2_MWID_Pos) /*!< 0x00000030 */
10561 #define FMC_BCR2_MWID FMC_BCR2_MWID_Msk /*!<MWID[1:0] bits (Memory data bus width) */
10562 #define FMC_BCR2_MWID_0 (0x1U << FMC_BCR2_MWID_Pos) /*!< 0x00000010 */
10563 #define FMC_BCR2_MWID_1 (0x2U << FMC_BCR2_MWID_Pos) /*!< 0x00000020 */
10564
10565 #define FMC_BCR2_FACCEN_Pos (6U)
10566 #define FMC_BCR2_FACCEN_Msk (0x1U << FMC_BCR2_FACCEN_Pos) /*!< 0x00000040 */
10567 #define FMC_BCR2_FACCEN FMC_BCR2_FACCEN_Msk /*!<Flash access enable */
10568 #define FMC_BCR2_BURSTEN_Pos (8U)
10569 #define FMC_BCR2_BURSTEN_Msk (0x1U << FMC_BCR2_BURSTEN_Pos) /*!< 0x00000100 */
10570 #define FMC_BCR2_BURSTEN FMC_BCR2_BURSTEN_Msk /*!<Burst enable bit */
10571 #define FMC_BCR2_WAITPOL_Pos (9U)
10572 #define FMC_BCR2_WAITPOL_Msk (0x1U << FMC_BCR2_WAITPOL_Pos) /*!< 0x00000200 */
10573 #define FMC_BCR2_WAITPOL FMC_BCR2_WAITPOL_Msk /*!<Wait signal polarity bit */
10574 #define FMC_BCR2_WAITCFG_Pos (11U)
10575 #define FMC_BCR2_WAITCFG_Msk (0x1U << FMC_BCR2_WAITCFG_Pos) /*!< 0x00000800 */
10576 #define FMC_BCR2_WAITCFG FMC_BCR2_WAITCFG_Msk /*!<Wait timing configuration */
10577 #define FMC_BCR2_WREN_Pos (12U)
10578 #define FMC_BCR2_WREN_Msk (0x1U << FMC_BCR2_WREN_Pos) /*!< 0x00001000 */
10579 #define FMC_BCR2_WREN FMC_BCR2_WREN_Msk /*!<Write enable bit */
10580 #define FMC_BCR2_WAITEN_Pos (13U)
10581 #define FMC_BCR2_WAITEN_Msk (0x1U << FMC_BCR2_WAITEN_Pos) /*!< 0x00002000 */
10582 #define FMC_BCR2_WAITEN FMC_BCR2_WAITEN_Msk /*!<Wait enable bit */
10583 #define FMC_BCR2_EXTMOD_Pos (14U)
10584 #define FMC_BCR2_EXTMOD_Msk (0x1U << FMC_BCR2_EXTMOD_Pos) /*!< 0x00004000 */
10585 #define FMC_BCR2_EXTMOD FMC_BCR2_EXTMOD_Msk /*!<Extended mode enable */
10586 #define FMC_BCR2_ASYNCWAIT_Pos (15U)
10587 #define FMC_BCR2_ASYNCWAIT_Msk (0x1U << FMC_BCR2_ASYNCWAIT_Pos) /*!< 0x00008000 */
10588 #define FMC_BCR2_ASYNCWAIT FMC_BCR2_ASYNCWAIT_Msk /*!<Asynchronous wait */
10589 #define FMC_BCR2_CBURSTRW_Pos (19U)
10590 #define FMC_BCR2_CBURSTRW_Msk (0x1U << FMC_BCR2_CBURSTRW_Pos) /*!< 0x00080000 */
10591 #define FMC_BCR2_CBURSTRW FMC_BCR2_CBURSTRW_Msk /*!<Write burst enable */
10592
10593 /****************** Bit definition for FMC_BCR3 register *******************/
10594 #define FMC_BCR3_MBKEN_Pos (0U)
10595 #define FMC_BCR3_MBKEN_Msk (0x1U << FMC_BCR3_MBKEN_Pos) /*!< 0x00000001 */
10596 #define FMC_BCR3_MBKEN FMC_BCR3_MBKEN_Msk /*!<Memory bank enable bit */
10597 #define FMC_BCR3_MUXEN_Pos (1U)
10598 #define FMC_BCR3_MUXEN_Msk (0x1U << FMC_BCR3_MUXEN_Pos) /*!< 0x00000002 */
10599 #define FMC_BCR3_MUXEN FMC_BCR3_MUXEN_Msk /*!<Address/data multiplexing enable bit */
10600
10601 #define FMC_BCR3_MTYP_Pos (2U)
10602 #define FMC_BCR3_MTYP_Msk (0x3U << FMC_BCR3_MTYP_Pos) /*!< 0x0000000C */
10603 #define FMC_BCR3_MTYP FMC_BCR3_MTYP_Msk /*!<MTYP[1:0] bits (Memory type) */
10604 #define FMC_BCR3_MTYP_0 (0x1U << FMC_BCR3_MTYP_Pos) /*!< 0x00000004 */
10605 #define FMC_BCR3_MTYP_1 (0x2U << FMC_BCR3_MTYP_Pos) /*!< 0x00000008 */
10606
10607 #define FMC_BCR3_MWID_Pos (4U)
10608 #define FMC_BCR3_MWID_Msk (0x3U << FMC_BCR3_MWID_Pos) /*!< 0x00000030 */
10609 #define FMC_BCR3_MWID FMC_BCR3_MWID_Msk /*!<MWID[1:0] bits (Memory data bus width) */
10610 #define FMC_BCR3_MWID_0 (0x1U << FMC_BCR3_MWID_Pos) /*!< 0x00000010 */
10611 #define FMC_BCR3_MWID_1 (0x2U << FMC_BCR3_MWID_Pos) /*!< 0x00000020 */
10612
10613 #define FMC_BCR3_FACCEN_Pos (6U)
10614 #define FMC_BCR3_FACCEN_Msk (0x1U << FMC_BCR3_FACCEN_Pos) /*!< 0x00000040 */
10615 #define FMC_BCR3_FACCEN FMC_BCR3_FACCEN_Msk /*!<Flash access enable */
10616 #define FMC_BCR3_BURSTEN_Pos (8U)
10617 #define FMC_BCR3_BURSTEN_Msk (0x1U << FMC_BCR3_BURSTEN_Pos) /*!< 0x00000100 */
10618 #define FMC_BCR3_BURSTEN FMC_BCR3_BURSTEN_Msk /*!<Burst enable bit */
10619 #define FMC_BCR3_WAITPOL_Pos (9U)
10620 #define FMC_BCR3_WAITPOL_Msk (0x1U << FMC_BCR3_WAITPOL_Pos) /*!< 0x00000200 */
10621 #define FMC_BCR3_WAITPOL FMC_BCR3_WAITPOL_Msk /*!<Wait signal polarity bit */
10622 #define FMC_BCR3_WAITCFG_Pos (11U)
10623 #define FMC_BCR3_WAITCFG_Msk (0x1U << FMC_BCR3_WAITCFG_Pos) /*!< 0x00000800 */
10624 #define FMC_BCR3_WAITCFG FMC_BCR3_WAITCFG_Msk /*!<Wait timing configuration */
10625 #define FMC_BCR3_WREN_Pos (12U)
10626 #define FMC_BCR3_WREN_Msk (0x1U << FMC_BCR3_WREN_Pos) /*!< 0x00001000 */
10627 #define FMC_BCR3_WREN FMC_BCR3_WREN_Msk /*!<Write enable bit */
10628 #define FMC_BCR3_WAITEN_Pos (13U)
10629 #define FMC_BCR3_WAITEN_Msk (0x1U << FMC_BCR3_WAITEN_Pos) /*!< 0x00002000 */
10630 #define FMC_BCR3_WAITEN FMC_BCR3_WAITEN_Msk /*!<Wait enable bit */
10631 #define FMC_BCR3_EXTMOD_Pos (14U)
10632 #define FMC_BCR3_EXTMOD_Msk (0x1U << FMC_BCR3_EXTMOD_Pos) /*!< 0x00004000 */
10633 #define FMC_BCR3_EXTMOD FMC_BCR3_EXTMOD_Msk /*!<Extended mode enable */
10634 #define FMC_BCR3_ASYNCWAIT_Pos (15U)
10635 #define FMC_BCR3_ASYNCWAIT_Msk (0x1U << FMC_BCR3_ASYNCWAIT_Pos) /*!< 0x00008000 */
10636 #define FMC_BCR3_ASYNCWAIT FMC_BCR3_ASYNCWAIT_Msk /*!<Asynchronous wait */
10637 #define FMC_BCR3_CBURSTRW_Pos (19U)
10638 #define FMC_BCR3_CBURSTRW_Msk (0x1U << FMC_BCR3_CBURSTRW_Pos) /*!< 0x00080000 */
10639 #define FMC_BCR3_CBURSTRW FMC_BCR3_CBURSTRW_Msk /*!<Write burst enable */
10640
10641 /****************** Bit definition for FMC_BCR4 register *******************/
10642 #define FMC_BCR4_MBKEN_Pos (0U)
10643 #define FMC_BCR4_MBKEN_Msk (0x1U << FMC_BCR4_MBKEN_Pos) /*!< 0x00000001 */
10644 #define FMC_BCR4_MBKEN FMC_BCR4_MBKEN_Msk /*!<Memory bank enable bit */
10645 #define FMC_BCR4_MUXEN_Pos (1U)
10646 #define FMC_BCR4_MUXEN_Msk (0x1U << FMC_BCR4_MUXEN_Pos) /*!< 0x00000002 */
10647 #define FMC_BCR4_MUXEN FMC_BCR4_MUXEN_Msk /*!<Address/data multiplexing enable bit */
10648
10649 #define FMC_BCR4_MTYP_Pos (2U)
10650 #define FMC_BCR4_MTYP_Msk (0x3U << FMC_BCR4_MTYP_Pos) /*!< 0x0000000C */
10651 #define FMC_BCR4_MTYP FMC_BCR4_MTYP_Msk /*!<MTYP[1:0] bits (Memory type) */
10652 #define FMC_BCR4_MTYP_0 (0x1U << FMC_BCR4_MTYP_Pos) /*!< 0x00000004 */
10653 #define FMC_BCR4_MTYP_1 (0x2U << FMC_BCR4_MTYP_Pos) /*!< 0x00000008 */
10654
10655 #define FMC_BCR4_MWID_Pos (4U)
10656 #define FMC_BCR4_MWID_Msk (0x3U << FMC_BCR4_MWID_Pos) /*!< 0x00000030 */
10657 #define FMC_BCR4_MWID FMC_BCR4_MWID_Msk /*!<MWID[1:0] bits (Memory data bus width) */
10658 #define FMC_BCR4_MWID_0 (0x1U << FMC_BCR4_MWID_Pos) /*!< 0x00000010 */
10659 #define FMC_BCR4_MWID_1 (0x2U << FMC_BCR4_MWID_Pos) /*!< 0x00000020 */
10660
10661 #define FMC_BCR4_FACCEN_Pos (6U)
10662 #define FMC_BCR4_FACCEN_Msk (0x1U << FMC_BCR4_FACCEN_Pos) /*!< 0x00000040 */
10663 #define FMC_BCR4_FACCEN FMC_BCR4_FACCEN_Msk /*!<Flash access enable */
10664 #define FMC_BCR4_BURSTEN_Pos (8U)
10665 #define FMC_BCR4_BURSTEN_Msk (0x1U << FMC_BCR4_BURSTEN_Pos) /*!< 0x00000100 */
10666 #define FMC_BCR4_BURSTEN FMC_BCR4_BURSTEN_Msk /*!<Burst enable bit */
10667 #define FMC_BCR4_WAITPOL_Pos (9U)
10668 #define FMC_BCR4_WAITPOL_Msk (0x1U << FMC_BCR4_WAITPOL_Pos) /*!< 0x00000200 */
10669 #define FMC_BCR4_WAITPOL FMC_BCR4_WAITPOL_Msk /*!<Wait signal polarity bit */
10670 #define FMC_BCR4_WAITCFG_Pos (11U)
10671 #define FMC_BCR4_WAITCFG_Msk (0x1U << FMC_BCR4_WAITCFG_Pos) /*!< 0x00000800 */
10672 #define FMC_BCR4_WAITCFG FMC_BCR4_WAITCFG_Msk /*!<Wait timing configuration */
10673 #define FMC_BCR4_WREN_Pos (12U)
10674 #define FMC_BCR4_WREN_Msk (0x1U << FMC_BCR4_WREN_Pos) /*!< 0x00001000 */
10675 #define FMC_BCR4_WREN FMC_BCR4_WREN_Msk /*!<Write enable bit */
10676 #define FMC_BCR4_WAITEN_Pos (13U)
10677 #define FMC_BCR4_WAITEN_Msk (0x1U << FMC_BCR4_WAITEN_Pos) /*!< 0x00002000 */
10678 #define FMC_BCR4_WAITEN FMC_BCR4_WAITEN_Msk /*!<Wait enable bit */
10679 #define FMC_BCR4_EXTMOD_Pos (14U)
10680 #define FMC_BCR4_EXTMOD_Msk (0x1U << FMC_BCR4_EXTMOD_Pos) /*!< 0x00004000 */
10681 #define FMC_BCR4_EXTMOD FMC_BCR4_EXTMOD_Msk /*!<Extended mode enable */
10682 #define FMC_BCR4_ASYNCWAIT_Pos (15U)
10683 #define FMC_BCR4_ASYNCWAIT_Msk (0x1U << FMC_BCR4_ASYNCWAIT_Pos) /*!< 0x00008000 */
10684 #define FMC_BCR4_ASYNCWAIT FMC_BCR4_ASYNCWAIT_Msk /*!<Asynchronous wait */
10685 #define FMC_BCR4_CBURSTRW_Pos (19U)
10686 #define FMC_BCR4_CBURSTRW_Msk (0x1U << FMC_BCR4_CBURSTRW_Pos) /*!< 0x00080000 */
10687 #define FMC_BCR4_CBURSTRW FMC_BCR4_CBURSTRW_Msk /*!<Write burst enable */
10688
10689 /****************** Bit definition for FMC_BTR1 register ******************/
10690 #define FMC_BTR1_ADDSET_Pos (0U)
10691 #define FMC_BTR1_ADDSET_Msk (0xFU << FMC_BTR1_ADDSET_Pos) /*!< 0x0000000F */
10692 #define FMC_BTR1_ADDSET FMC_BTR1_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
10693 #define FMC_BTR1_ADDSET_0 (0x1U << FMC_BTR1_ADDSET_Pos) /*!< 0x00000001 */
10694 #define FMC_BTR1_ADDSET_1 (0x2U << FMC_BTR1_ADDSET_Pos) /*!< 0x00000002 */
10695 #define FMC_BTR1_ADDSET_2 (0x4U << FMC_BTR1_ADDSET_Pos) /*!< 0x00000004 */
10696 #define FMC_BTR1_ADDSET_3 (0x8U << FMC_BTR1_ADDSET_Pos) /*!< 0x00000008 */
10697
10698 #define FMC_BTR1_ADDHLD_Pos (4U)
10699 #define FMC_BTR1_ADDHLD_Msk (0xFU << FMC_BTR1_ADDHLD_Pos) /*!< 0x000000F0 */
10700 #define FMC_BTR1_ADDHLD FMC_BTR1_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
10701 #define FMC_BTR1_ADDHLD_0 (0x1U << FMC_BTR1_ADDHLD_Pos) /*!< 0x00000010 */
10702 #define FMC_BTR1_ADDHLD_1 (0x2U << FMC_BTR1_ADDHLD_Pos) /*!< 0x00000020 */
10703 #define FMC_BTR1_ADDHLD_2 (0x4U << FMC_BTR1_ADDHLD_Pos) /*!< 0x00000040 */
10704 #define FMC_BTR1_ADDHLD_3 (0x8U << FMC_BTR1_ADDHLD_Pos) /*!< 0x00000080 */
10705
10706 #define FMC_BTR1_DATAST_Pos (8U)
10707 #define FMC_BTR1_DATAST_Msk (0xFFU << FMC_BTR1_DATAST_Pos) /*!< 0x0000FF00 */
10708 #define FMC_BTR1_DATAST FMC_BTR1_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */
10709 #define FMC_BTR1_DATAST_0 (0x01U << FMC_BTR1_DATAST_Pos) /*!< 0x00000100 */
10710 #define FMC_BTR1_DATAST_1 (0x02U << FMC_BTR1_DATAST_Pos) /*!< 0x00000200 */
10711 #define FMC_BTR1_DATAST_2 (0x04U << FMC_BTR1_DATAST_Pos) /*!< 0x00000400 */
10712 #define FMC_BTR1_DATAST_3 (0x08U << FMC_BTR1_DATAST_Pos) /*!< 0x00000800 */
10713 #define FMC_BTR1_DATAST_4 (0x10U << FMC_BTR1_DATAST_Pos) /*!< 0x00001000 */
10714 #define FMC_BTR1_DATAST_5 (0x20U << FMC_BTR1_DATAST_Pos) /*!< 0x00002000 */
10715 #define FMC_BTR1_DATAST_6 (0x40U << FMC_BTR1_DATAST_Pos) /*!< 0x00004000 */
10716 #define FMC_BTR1_DATAST_7 (0x80U << FMC_BTR1_DATAST_Pos) /*!< 0x00008000 */
10717
10718 #define FMC_BTR1_BUSTURN_Pos (16U)
10719 #define FMC_BTR1_BUSTURN_Msk (0xFU << FMC_BTR1_BUSTURN_Pos) /*!< 0x000F0000 */
10720 #define FMC_BTR1_BUSTURN FMC_BTR1_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
10721 #define FMC_BTR1_BUSTURN_0 (0x1U << FMC_BTR1_BUSTURN_Pos) /*!< 0x00010000 */
10722 #define FMC_BTR1_BUSTURN_1 (0x2U << FMC_BTR1_BUSTURN_Pos) /*!< 0x00020000 */
10723 #define FMC_BTR1_BUSTURN_2 (0x4U << FMC_BTR1_BUSTURN_Pos) /*!< 0x00040000 */
10724 #define FMC_BTR1_BUSTURN_3 (0x8U << FMC_BTR1_BUSTURN_Pos) /*!< 0x00080000 */
10725
10726 #define FMC_BTR1_CLKDIV_Pos (20U)
10727 #define FMC_BTR1_CLKDIV_Msk (0xFU << FMC_BTR1_CLKDIV_Pos) /*!< 0x00F00000 */
10728 #define FMC_BTR1_CLKDIV FMC_BTR1_CLKDIV_Msk /*!<CLKDIV[3:0] bits (Clock divide ratio) */
10729 #define FMC_BTR1_CLKDIV_0 (0x1U << FMC_BTR1_CLKDIV_Pos) /*!< 0x00100000 */
10730 #define FMC_BTR1_CLKDIV_1 (0x2U << FMC_BTR1_CLKDIV_Pos) /*!< 0x00200000 */
10731 #define FMC_BTR1_CLKDIV_2 (0x4U << FMC_BTR1_CLKDIV_Pos) /*!< 0x00400000 */
10732 #define FMC_BTR1_CLKDIV_3 (0x8U << FMC_BTR1_CLKDIV_Pos) /*!< 0x00800000 */
10733
10734 #define FMC_BTR1_DATLAT_Pos (24U)
10735 #define FMC_BTR1_DATLAT_Msk (0xFU << FMC_BTR1_DATLAT_Pos) /*!< 0x0F000000 */
10736 #define FMC_BTR1_DATLAT FMC_BTR1_DATLAT_Msk /*!<DATLA[3:0] bits (Data latency) */
10737 #define FMC_BTR1_DATLAT_0 (0x1U << FMC_BTR1_DATLAT_Pos) /*!< 0x01000000 */
10738 #define FMC_BTR1_DATLAT_1 (0x2U << FMC_BTR1_DATLAT_Pos) /*!< 0x02000000 */
10739 #define FMC_BTR1_DATLAT_2 (0x4U << FMC_BTR1_DATLAT_Pos) /*!< 0x04000000 */
10740 #define FMC_BTR1_DATLAT_3 (0x8U << FMC_BTR1_DATLAT_Pos) /*!< 0x08000000 */
10741
10742 #define FMC_BTR1_ACCMOD_Pos (28U)
10743 #define FMC_BTR1_ACCMOD_Msk (0x3U << FMC_BTR1_ACCMOD_Pos) /*!< 0x30000000 */
10744 #define FMC_BTR1_ACCMOD FMC_BTR1_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
10745 #define FMC_BTR1_ACCMOD_0 (0x1U << FMC_BTR1_ACCMOD_Pos) /*!< 0x10000000 */
10746 #define FMC_BTR1_ACCMOD_1 (0x2U << FMC_BTR1_ACCMOD_Pos) /*!< 0x20000000 */
10747
10748 /****************** Bit definition for FMC_BTR2 register *******************/
10749 #define FMC_BTR2_ADDSET_Pos (0U)
10750 #define FMC_BTR2_ADDSET_Msk (0xFU << FMC_BTR2_ADDSET_Pos) /*!< 0x0000000F */
10751 #define FMC_BTR2_ADDSET FMC_BTR2_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
10752 #define FMC_BTR2_ADDSET_0 (0x1U << FMC_BTR2_ADDSET_Pos) /*!< 0x00000001 */
10753 #define FMC_BTR2_ADDSET_1 (0x2U << FMC_BTR2_ADDSET_Pos) /*!< 0x00000002 */
10754 #define FMC_BTR2_ADDSET_2 (0x4U << FMC_BTR2_ADDSET_Pos) /*!< 0x00000004 */
10755 #define FMC_BTR2_ADDSET_3 (0x8U << FMC_BTR2_ADDSET_Pos) /*!< 0x00000008 */
10756
10757 #define FMC_BTR2_ADDHLD_Pos (4U)
10758 #define FMC_BTR2_ADDHLD_Msk (0xFU << FMC_BTR2_ADDHLD_Pos) /*!< 0x000000F0 */
10759 #define FMC_BTR2_ADDHLD FMC_BTR2_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
10760 #define FMC_BTR2_ADDHLD_0 (0x1U << FMC_BTR2_ADDHLD_Pos) /*!< 0x00000010 */
10761 #define FMC_BTR2_ADDHLD_1 (0x2U << FMC_BTR2_ADDHLD_Pos) /*!< 0x00000020 */
10762 #define FMC_BTR2_ADDHLD_2 (0x4U << FMC_BTR2_ADDHLD_Pos) /*!< 0x00000040 */
10763 #define FMC_BTR2_ADDHLD_3 (0x8U << FMC_BTR2_ADDHLD_Pos) /*!< 0x00000080 */
10764
10765 #define FMC_BTR2_DATAST_Pos (8U)
10766 #define FMC_BTR2_DATAST_Msk (0xFFU << FMC_BTR2_DATAST_Pos) /*!< 0x0000FF00 */
10767 #define FMC_BTR2_DATAST FMC_BTR2_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */
10768 #define FMC_BTR2_DATAST_0 (0x01U << FMC_BTR2_DATAST_Pos) /*!< 0x00000100 */
10769 #define FMC_BTR2_DATAST_1 (0x02U << FMC_BTR2_DATAST_Pos) /*!< 0x00000200 */
10770 #define FMC_BTR2_DATAST_2 (0x04U << FMC_BTR2_DATAST_Pos) /*!< 0x00000400 */
10771 #define FMC_BTR2_DATAST_3 (0x08U << FMC_BTR2_DATAST_Pos) /*!< 0x00000800 */
10772 #define FMC_BTR2_DATAST_4 (0x10U << FMC_BTR2_DATAST_Pos) /*!< 0x00001000 */
10773 #define FMC_BTR2_DATAST_5 (0x20U << FMC_BTR2_DATAST_Pos) /*!< 0x00002000 */
10774 #define FMC_BTR2_DATAST_6 (0x40U << FMC_BTR2_DATAST_Pos) /*!< 0x00004000 */
10775 #define FMC_BTR2_DATAST_7 (0x80U << FMC_BTR2_DATAST_Pos) /*!< 0x00008000 */
10776
10777 #define FMC_BTR2_BUSTURN_Pos (16U)
10778 #define FMC_BTR2_BUSTURN_Msk (0xFU << FMC_BTR2_BUSTURN_Pos) /*!< 0x000F0000 */
10779 #define FMC_BTR2_BUSTURN FMC_BTR2_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
10780 #define FMC_BTR2_BUSTURN_0 (0x1U << FMC_BTR2_BUSTURN_Pos) /*!< 0x00010000 */
10781 #define FMC_BTR2_BUSTURN_1 (0x2U << FMC_BTR2_BUSTURN_Pos) /*!< 0x00020000 */
10782 #define FMC_BTR2_BUSTURN_2 (0x4U << FMC_BTR2_BUSTURN_Pos) /*!< 0x00040000 */
10783 #define FMC_BTR2_BUSTURN_3 (0x8U << FMC_BTR2_BUSTURN_Pos) /*!< 0x00080000 */
10784
10785 #define FMC_BTR2_CLKDIV_Pos (20U)
10786 #define FMC_BTR2_CLKDIV_Msk (0xFU << FMC_BTR2_CLKDIV_Pos) /*!< 0x00F00000 */
10787 #define FMC_BTR2_CLKDIV FMC_BTR2_CLKDIV_Msk /*!<CLKDIV[3:0] bits (Clock divide ratio) */
10788 #define FMC_BTR2_CLKDIV_0 (0x1U << FMC_BTR2_CLKDIV_Pos) /*!< 0x00100000 */
10789 #define FMC_BTR2_CLKDIV_1 (0x2U << FMC_BTR2_CLKDIV_Pos) /*!< 0x00200000 */
10790 #define FMC_BTR2_CLKDIV_2 (0x4U << FMC_BTR2_CLKDIV_Pos) /*!< 0x00400000 */
10791 #define FMC_BTR2_CLKDIV_3 (0x8U << FMC_BTR2_CLKDIV_Pos) /*!< 0x00800000 */
10792
10793 #define FMC_BTR2_DATLAT_Pos (24U)
10794 #define FMC_BTR2_DATLAT_Msk (0xFU << FMC_BTR2_DATLAT_Pos) /*!< 0x0F000000 */
10795 #define FMC_BTR2_DATLAT FMC_BTR2_DATLAT_Msk /*!<DATLA[3:0] bits (Data latency) */
10796 #define FMC_BTR2_DATLAT_0 (0x1U << FMC_BTR2_DATLAT_Pos) /*!< 0x01000000 */
10797 #define FMC_BTR2_DATLAT_1 (0x2U << FMC_BTR2_DATLAT_Pos) /*!< 0x02000000 */
10798 #define FMC_BTR2_DATLAT_2 (0x4U << FMC_BTR2_DATLAT_Pos) /*!< 0x04000000 */
10799 #define FMC_BTR2_DATLAT_3 (0x8U << FMC_BTR2_DATLAT_Pos) /*!< 0x08000000 */
10800
10801 #define FMC_BTR2_ACCMOD_Pos (28U)
10802 #define FMC_BTR2_ACCMOD_Msk (0x3U << FMC_BTR2_ACCMOD_Pos) /*!< 0x30000000 */
10803 #define FMC_BTR2_ACCMOD FMC_BTR2_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
10804 #define FMC_BTR2_ACCMOD_0 (0x1U << FMC_BTR2_ACCMOD_Pos) /*!< 0x10000000 */
10805 #define FMC_BTR2_ACCMOD_1 (0x2U << FMC_BTR2_ACCMOD_Pos) /*!< 0x20000000 */
10806
10807 /******************* Bit definition for FMC_BTR3 register *******************/
10808 #define FMC_BTR3_ADDSET_Pos (0U)
10809 #define FMC_BTR3_ADDSET_Msk (0xFU << FMC_BTR3_ADDSET_Pos) /*!< 0x0000000F */
10810 #define FMC_BTR3_ADDSET FMC_BTR3_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
10811 #define FMC_BTR3_ADDSET_0 (0x1U << FMC_BTR3_ADDSET_Pos) /*!< 0x00000001 */
10812 #define FMC_BTR3_ADDSET_1 (0x2U << FMC_BTR3_ADDSET_Pos) /*!< 0x00000002 */
10813 #define FMC_BTR3_ADDSET_2 (0x4U << FMC_BTR3_ADDSET_Pos) /*!< 0x00000004 */
10814 #define FMC_BTR3_ADDSET_3 (0x8U << FMC_BTR3_ADDSET_Pos) /*!< 0x00000008 */
10815
10816 #define FMC_BTR3_ADDHLD_Pos (4U)
10817 #define FMC_BTR3_ADDHLD_Msk (0xFU << FMC_BTR3_ADDHLD_Pos) /*!< 0x000000F0 */
10818 #define FMC_BTR3_ADDHLD FMC_BTR3_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
10819 #define FMC_BTR3_ADDHLD_0 (0x1U << FMC_BTR3_ADDHLD_Pos) /*!< 0x00000010 */
10820 #define FMC_BTR3_ADDHLD_1 (0x2U << FMC_BTR3_ADDHLD_Pos) /*!< 0x00000020 */
10821 #define FMC_BTR3_ADDHLD_2 (0x4U << FMC_BTR3_ADDHLD_Pos) /*!< 0x00000040 */
10822 #define FMC_BTR3_ADDHLD_3 (0x8U << FMC_BTR3_ADDHLD_Pos) /*!< 0x00000080 */
10823
10824 #define FMC_BTR3_DATAST_Pos (8U)
10825 #define FMC_BTR3_DATAST_Msk (0xFFU << FMC_BTR3_DATAST_Pos) /*!< 0x0000FF00 */
10826 #define FMC_BTR3_DATAST FMC_BTR3_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */
10827 #define FMC_BTR3_DATAST_0 (0x01U << FMC_BTR3_DATAST_Pos) /*!< 0x00000100 */
10828 #define FMC_BTR3_DATAST_1 (0x02U << FMC_BTR3_DATAST_Pos) /*!< 0x00000200 */
10829 #define FMC_BTR3_DATAST_2 (0x04U << FMC_BTR3_DATAST_Pos) /*!< 0x00000400 */
10830 #define FMC_BTR3_DATAST_3 (0x08U << FMC_BTR3_DATAST_Pos) /*!< 0x00000800 */
10831 #define FMC_BTR3_DATAST_4 (0x10U << FMC_BTR3_DATAST_Pos) /*!< 0x00001000 */
10832 #define FMC_BTR3_DATAST_5 (0x20U << FMC_BTR3_DATAST_Pos) /*!< 0x00002000 */
10833 #define FMC_BTR3_DATAST_6 (0x40U << FMC_BTR3_DATAST_Pos) /*!< 0x00004000 */
10834 #define FMC_BTR3_DATAST_7 (0x80U << FMC_BTR3_DATAST_Pos) /*!< 0x00008000 */
10835
10836 #define FMC_BTR3_BUSTURN_Pos (16U)
10837 #define FMC_BTR3_BUSTURN_Msk (0xFU << FMC_BTR3_BUSTURN_Pos) /*!< 0x000F0000 */
10838 #define FMC_BTR3_BUSTURN FMC_BTR3_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
10839 #define FMC_BTR3_BUSTURN_0 (0x1U << FMC_BTR3_BUSTURN_Pos) /*!< 0x00010000 */
10840 #define FMC_BTR3_BUSTURN_1 (0x2U << FMC_BTR3_BUSTURN_Pos) /*!< 0x00020000 */
10841 #define FMC_BTR3_BUSTURN_2 (0x4U << FMC_BTR3_BUSTURN_Pos) /*!< 0x00040000 */
10842 #define FMC_BTR3_BUSTURN_3 (0x8U << FMC_BTR3_BUSTURN_Pos) /*!< 0x00080000 */
10843
10844 #define FMC_BTR3_CLKDIV_Pos (20U)
10845 #define FMC_BTR3_CLKDIV_Msk (0xFU << FMC_BTR3_CLKDIV_Pos) /*!< 0x00F00000 */
10846 #define FMC_BTR3_CLKDIV FMC_BTR3_CLKDIV_Msk /*!<CLKDIV[3:0] bits (Clock divide ratio) */
10847 #define FMC_BTR3_CLKDIV_0 (0x1U << FMC_BTR3_CLKDIV_Pos) /*!< 0x00100000 */
10848 #define FMC_BTR3_CLKDIV_1 (0x2U << FMC_BTR3_CLKDIV_Pos) /*!< 0x00200000 */
10849 #define FMC_BTR3_CLKDIV_2 (0x4U << FMC_BTR3_CLKDIV_Pos) /*!< 0x00400000 */
10850 #define FMC_BTR3_CLKDIV_3 (0x8U << FMC_BTR3_CLKDIV_Pos) /*!< 0x00800000 */
10851
10852 #define FMC_BTR3_DATLAT_Pos (24U)
10853 #define FMC_BTR3_DATLAT_Msk (0xFU << FMC_BTR3_DATLAT_Pos) /*!< 0x0F000000 */
10854 #define FMC_BTR3_DATLAT FMC_BTR3_DATLAT_Msk /*!<DATLA[3:0] bits (Data latency) */
10855 #define FMC_BTR3_DATLAT_0 (0x1U << FMC_BTR3_DATLAT_Pos) /*!< 0x01000000 */
10856 #define FMC_BTR3_DATLAT_1 (0x2U << FMC_BTR3_DATLAT_Pos) /*!< 0x02000000 */
10857 #define FMC_BTR3_DATLAT_2 (0x4U << FMC_BTR3_DATLAT_Pos) /*!< 0x04000000 */
10858 #define FMC_BTR3_DATLAT_3 (0x8U << FMC_BTR3_DATLAT_Pos) /*!< 0x08000000 */
10859
10860 #define FMC_BTR3_ACCMOD_Pos (28U)
10861 #define FMC_BTR3_ACCMOD_Msk (0x3U << FMC_BTR3_ACCMOD_Pos) /*!< 0x30000000 */
10862 #define FMC_BTR3_ACCMOD FMC_BTR3_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
10863 #define FMC_BTR3_ACCMOD_0 (0x1U << FMC_BTR3_ACCMOD_Pos) /*!< 0x10000000 */
10864 #define FMC_BTR3_ACCMOD_1 (0x2U << FMC_BTR3_ACCMOD_Pos) /*!< 0x20000000 */
10865
10866 /****************** Bit definition for FMC_BTR4 register *******************/
10867 #define FMC_BTR4_ADDSET_Pos (0U)
10868 #define FMC_BTR4_ADDSET_Msk (0xFU << FMC_BTR4_ADDSET_Pos) /*!< 0x0000000F */
10869 #define FMC_BTR4_ADDSET FMC_BTR4_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
10870 #define FMC_BTR4_ADDSET_0 (0x1U << FMC_BTR4_ADDSET_Pos) /*!< 0x00000001 */
10871 #define FMC_BTR4_ADDSET_1 (0x2U << FMC_BTR4_ADDSET_Pos) /*!< 0x00000002 */
10872 #define FMC_BTR4_ADDSET_2 (0x4U << FMC_BTR4_ADDSET_Pos) /*!< 0x00000004 */
10873 #define FMC_BTR4_ADDSET_3 (0x8U << FMC_BTR4_ADDSET_Pos) /*!< 0x00000008 */
10874
10875 #define FMC_BTR4_ADDHLD_Pos (4U)
10876 #define FMC_BTR4_ADDHLD_Msk (0xFU << FMC_BTR4_ADDHLD_Pos) /*!< 0x000000F0 */
10877 #define FMC_BTR4_ADDHLD FMC_BTR4_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
10878 #define FMC_BTR4_ADDHLD_0 (0x1U << FMC_BTR4_ADDHLD_Pos) /*!< 0x00000010 */
10879 #define FMC_BTR4_ADDHLD_1 (0x2U << FMC_BTR4_ADDHLD_Pos) /*!< 0x00000020 */
10880 #define FMC_BTR4_ADDHLD_2 (0x4U << FMC_BTR4_ADDHLD_Pos) /*!< 0x00000040 */
10881 #define FMC_BTR4_ADDHLD_3 (0x8U << FMC_BTR4_ADDHLD_Pos) /*!< 0x00000080 */
10882
10883 #define FMC_BTR4_DATAST_Pos (8U)
10884 #define FMC_BTR4_DATAST_Msk (0xFFU << FMC_BTR4_DATAST_Pos) /*!< 0x0000FF00 */
10885 #define FMC_BTR4_DATAST FMC_BTR4_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */
10886 #define FMC_BTR4_DATAST_0 (0x01U << FMC_BTR4_DATAST_Pos) /*!< 0x00000100 */
10887 #define FMC_BTR4_DATAST_1 (0x02U << FMC_BTR4_DATAST_Pos) /*!< 0x00000200 */
10888 #define FMC_BTR4_DATAST_2 (0x04U << FMC_BTR4_DATAST_Pos) /*!< 0x00000400 */
10889 #define FMC_BTR4_DATAST_3 (0x08U << FMC_BTR4_DATAST_Pos) /*!< 0x00000800 */
10890 #define FMC_BTR4_DATAST_4 (0x10U << FMC_BTR4_DATAST_Pos) /*!< 0x00001000 */
10891 #define FMC_BTR4_DATAST_5 (0x20U << FMC_BTR4_DATAST_Pos) /*!< 0x00002000 */
10892 #define FMC_BTR4_DATAST_6 (0x40U << FMC_BTR4_DATAST_Pos) /*!< 0x00004000 */
10893 #define FMC_BTR4_DATAST_7 (0x80U << FMC_BTR4_DATAST_Pos) /*!< 0x00008000 */
10894
10895 #define FMC_BTR4_BUSTURN_Pos (16U)
10896 #define FMC_BTR4_BUSTURN_Msk (0xFU << FMC_BTR4_BUSTURN_Pos) /*!< 0x000F0000 */
10897 #define FMC_BTR4_BUSTURN FMC_BTR4_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
10898 #define FMC_BTR4_BUSTURN_0 (0x1U << FMC_BTR4_BUSTURN_Pos) /*!< 0x00010000 */
10899 #define FMC_BTR4_BUSTURN_1 (0x2U << FMC_BTR4_BUSTURN_Pos) /*!< 0x00020000 */
10900 #define FMC_BTR4_BUSTURN_2 (0x4U << FMC_BTR4_BUSTURN_Pos) /*!< 0x00040000 */
10901 #define FMC_BTR4_BUSTURN_3 (0x8U << FMC_BTR4_BUSTURN_Pos) /*!< 0x00080000 */
10902
10903 #define FMC_BTR4_CLKDIV_Pos (20U)
10904 #define FMC_BTR4_CLKDIV_Msk (0xFU << FMC_BTR4_CLKDIV_Pos) /*!< 0x00F00000 */
10905 #define FMC_BTR4_CLKDIV FMC_BTR4_CLKDIV_Msk /*!<CLKDIV[3:0] bits (Clock divide ratio) */
10906 #define FMC_BTR4_CLKDIV_0 (0x1U << FMC_BTR4_CLKDIV_Pos) /*!< 0x00100000 */
10907 #define FMC_BTR4_CLKDIV_1 (0x2U << FMC_BTR4_CLKDIV_Pos) /*!< 0x00200000 */
10908 #define FMC_BTR4_CLKDIV_2 (0x4U << FMC_BTR4_CLKDIV_Pos) /*!< 0x00400000 */
10909 #define FMC_BTR4_CLKDIV_3 (0x8U << FMC_BTR4_CLKDIV_Pos) /*!< 0x00800000 */
10910
10911 #define FMC_BTR4_DATLAT_Pos (24U)
10912 #define FMC_BTR4_DATLAT_Msk (0xFU << FMC_BTR4_DATLAT_Pos) /*!< 0x0F000000 */
10913 #define FMC_BTR4_DATLAT FMC_BTR4_DATLAT_Msk /*!<DATLA[3:0] bits (Data latency) */
10914 #define FMC_BTR4_DATLAT_0 (0x1U << FMC_BTR4_DATLAT_Pos) /*!< 0x01000000 */
10915 #define FMC_BTR4_DATLAT_1 (0x2U << FMC_BTR4_DATLAT_Pos) /*!< 0x02000000 */
10916 #define FMC_BTR4_DATLAT_2 (0x4U << FMC_BTR4_DATLAT_Pos) /*!< 0x04000000 */
10917 #define FMC_BTR4_DATLAT_3 (0x8U << FMC_BTR4_DATLAT_Pos) /*!< 0x08000000 */
10918
10919 #define FMC_BTR4_ACCMOD_Pos (28U)
10920 #define FMC_BTR4_ACCMOD_Msk (0x3U << FMC_BTR4_ACCMOD_Pos) /*!< 0x30000000 */
10921 #define FMC_BTR4_ACCMOD FMC_BTR4_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
10922 #define FMC_BTR4_ACCMOD_0 (0x1U << FMC_BTR4_ACCMOD_Pos) /*!< 0x10000000 */
10923 #define FMC_BTR4_ACCMOD_1 (0x2U << FMC_BTR4_ACCMOD_Pos) /*!< 0x20000000 */
10924
10925 /****************** Bit definition for FMC_BWTR1 register ******************/
10926 #define FMC_BWTR1_ADDSET_Pos (0U)
10927 #define FMC_BWTR1_ADDSET_Msk (0xFU << FMC_BWTR1_ADDSET_Pos) /*!< 0x0000000F */
10928 #define FMC_BWTR1_ADDSET FMC_BWTR1_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
10929 #define FMC_BWTR1_ADDSET_0 (0x1U << FMC_BWTR1_ADDSET_Pos) /*!< 0x00000001 */
10930 #define FMC_BWTR1_ADDSET_1 (0x2U << FMC_BWTR1_ADDSET_Pos) /*!< 0x00000002 */
10931 #define FMC_BWTR1_ADDSET_2 (0x4U << FMC_BWTR1_ADDSET_Pos) /*!< 0x00000004 */
10932 #define FMC_BWTR1_ADDSET_3 (0x8U << FMC_BWTR1_ADDSET_Pos) /*!< 0x00000008 */
10933
10934 #define FMC_BWTR1_ADDHLD_Pos (4U)
10935 #define FMC_BWTR1_ADDHLD_Msk (0xFU << FMC_BWTR1_ADDHLD_Pos) /*!< 0x000000F0 */
10936 #define FMC_BWTR1_ADDHLD FMC_BWTR1_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
10937 #define FMC_BWTR1_ADDHLD_0 (0x1U << FMC_BWTR1_ADDHLD_Pos) /*!< 0x00000010 */
10938 #define FMC_BWTR1_ADDHLD_1 (0x2U << FMC_BWTR1_ADDHLD_Pos) /*!< 0x00000020 */
10939 #define FMC_BWTR1_ADDHLD_2 (0x4U << FMC_BWTR1_ADDHLD_Pos) /*!< 0x00000040 */
10940 #define FMC_BWTR1_ADDHLD_3 (0x8U << FMC_BWTR1_ADDHLD_Pos) /*!< 0x00000080 */
10941
10942 #define FMC_BWTR1_DATAST_Pos (8U)
10943 #define FMC_BWTR1_DATAST_Msk (0xFFU << FMC_BWTR1_DATAST_Pos) /*!< 0x0000FF00 */
10944 #define FMC_BWTR1_DATAST FMC_BWTR1_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */
10945 #define FMC_BWTR1_DATAST_0 (0x01U << FMC_BWTR1_DATAST_Pos) /*!< 0x00000100 */
10946 #define FMC_BWTR1_DATAST_1 (0x02U << FMC_BWTR1_DATAST_Pos) /*!< 0x00000200 */
10947 #define FMC_BWTR1_DATAST_2 (0x04U << FMC_BWTR1_DATAST_Pos) /*!< 0x00000400 */
10948 #define FMC_BWTR1_DATAST_3 (0x08U << FMC_BWTR1_DATAST_Pos) /*!< 0x00000800 */
10949 #define FMC_BWTR1_DATAST_4 (0x10U << FMC_BWTR1_DATAST_Pos) /*!< 0x00001000 */
10950 #define FMC_BWTR1_DATAST_5 (0x20U << FMC_BWTR1_DATAST_Pos) /*!< 0x00002000 */
10951 #define FMC_BWTR1_DATAST_6 (0x40U << FMC_BWTR1_DATAST_Pos) /*!< 0x00004000 */
10952 #define FMC_BWTR1_DATAST_7 (0x80U << FMC_BWTR1_DATAST_Pos) /*!< 0x00008000 */
10953
10954 #define FMC_BWTR1_BUSTURN_Pos (16U)
10955 #define FMC_BWTR1_BUSTURN_Msk (0xFU << FMC_BWTR1_BUSTURN_Pos) /*!< 0x000F0000 */
10956 #define FMC_BWTR1_BUSTURN FMC_BWTR1_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
10957 #define FMC_BWTR1_BUSTURN_0 (0x1U << FMC_BWTR1_BUSTURN_Pos) /*!< 0x00010000 */
10958 #define FMC_BWTR1_BUSTURN_1 (0x2U << FMC_BWTR1_BUSTURN_Pos) /*!< 0x00020000 */
10959 #define FMC_BWTR1_BUSTURN_2 (0x4U << FMC_BWTR1_BUSTURN_Pos) /*!< 0x00040000 */
10960 #define FMC_BWTR1_BUSTURN_3 (0x8U << FMC_BWTR1_BUSTURN_Pos) /*!< 0x00080000 */
10961
10962 #define FMC_BWTR1_ACCMOD_Pos (28U)
10963 #define FMC_BWTR1_ACCMOD_Msk (0x3U << FMC_BWTR1_ACCMOD_Pos) /*!< 0x30000000 */
10964 #define FMC_BWTR1_ACCMOD FMC_BWTR1_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
10965 #define FMC_BWTR1_ACCMOD_0 (0x1U << FMC_BWTR1_ACCMOD_Pos) /*!< 0x10000000 */
10966 #define FMC_BWTR1_ACCMOD_1 (0x2U << FMC_BWTR1_ACCMOD_Pos) /*!< 0x20000000 */
10967
10968 /****************** Bit definition for FMC_BWTR2 register ******************/
10969 #define FMC_BWTR2_ADDSET_Pos (0U)
10970 #define FMC_BWTR2_ADDSET_Msk (0xFU << FMC_BWTR2_ADDSET_Pos) /*!< 0x0000000F */
10971 #define FMC_BWTR2_ADDSET FMC_BWTR2_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
10972 #define FMC_BWTR2_ADDSET_0 (0x1U << FMC_BWTR2_ADDSET_Pos) /*!< 0x00000001 */
10973 #define FMC_BWTR2_ADDSET_1 (0x2U << FMC_BWTR2_ADDSET_Pos) /*!< 0x00000002 */
10974 #define FMC_BWTR2_ADDSET_2 (0x4U << FMC_BWTR2_ADDSET_Pos) /*!< 0x00000004 */
10975 #define FMC_BWTR2_ADDSET_3 (0x8U << FMC_BWTR2_ADDSET_Pos) /*!< 0x00000008 */
10976
10977 #define FMC_BWTR2_ADDHLD_Pos (4U)
10978 #define FMC_BWTR2_ADDHLD_Msk (0xFU << FMC_BWTR2_ADDHLD_Pos) /*!< 0x000000F0 */
10979 #define FMC_BWTR2_ADDHLD FMC_BWTR2_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
10980 #define FMC_BWTR2_ADDHLD_0 (0x1U << FMC_BWTR2_ADDHLD_Pos) /*!< 0x00000010 */
10981 #define FMC_BWTR2_ADDHLD_1 (0x2U << FMC_BWTR2_ADDHLD_Pos) /*!< 0x00000020 */
10982 #define FMC_BWTR2_ADDHLD_2 (0x4U << FMC_BWTR2_ADDHLD_Pos) /*!< 0x00000040 */
10983 #define FMC_BWTR2_ADDHLD_3 (0x8U << FMC_BWTR2_ADDHLD_Pos) /*!< 0x00000080 */
10984
10985 #define FMC_BWTR2_DATAST_Pos (8U)
10986 #define FMC_BWTR2_DATAST_Msk (0xFFU << FMC_BWTR2_DATAST_Pos) /*!< 0x0000FF00 */
10987 #define FMC_BWTR2_DATAST FMC_BWTR2_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */
10988 #define FMC_BWTR2_DATAST_0 (0x01U << FMC_BWTR2_DATAST_Pos) /*!< 0x00000100 */
10989 #define FMC_BWTR2_DATAST_1 (0x02U << FMC_BWTR2_DATAST_Pos) /*!< 0x00000200 */
10990 #define FMC_BWTR2_DATAST_2 (0x04U << FMC_BWTR2_DATAST_Pos) /*!< 0x00000400 */
10991 #define FMC_BWTR2_DATAST_3 (0x08U << FMC_BWTR2_DATAST_Pos) /*!< 0x00000800 */
10992 #define FMC_BWTR2_DATAST_4 (0x10U << FMC_BWTR2_DATAST_Pos) /*!< 0x00001000 */
10993 #define FMC_BWTR2_DATAST_5 (0x20U << FMC_BWTR2_DATAST_Pos) /*!< 0x00002000 */
10994 #define FMC_BWTR2_DATAST_6 (0x40U << FMC_BWTR2_DATAST_Pos) /*!< 0x00004000 */
10995 #define FMC_BWTR2_DATAST_7 (0x80U << FMC_BWTR2_DATAST_Pos) /*!< 0x00008000 */
10996
10997 #define FMC_BWTR2_BUSTURN_Pos (16U)
10998 #define FMC_BWTR2_BUSTURN_Msk (0xFU << FMC_BWTR2_BUSTURN_Pos) /*!< 0x000F0000 */
10999 #define FMC_BWTR2_BUSTURN FMC_BWTR2_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
11000 #define FMC_BWTR2_BUSTURN_0 (0x1U << FMC_BWTR2_BUSTURN_Pos) /*!< 0x00010000 */
11001 #define FMC_BWTR2_BUSTURN_1 (0x2U << FMC_BWTR2_BUSTURN_Pos) /*!< 0x00020000 */
11002 #define FMC_BWTR2_BUSTURN_2 (0x4U << FMC_BWTR2_BUSTURN_Pos) /*!< 0x00040000 */
11003 #define FMC_BWTR2_BUSTURN_3 (0x8U << FMC_BWTR2_BUSTURN_Pos) /*!< 0x00080000 */
11004
11005 #define FMC_BWTR2_ACCMOD_Pos (28U)
11006 #define FMC_BWTR2_ACCMOD_Msk (0x3U << FMC_BWTR2_ACCMOD_Pos) /*!< 0x30000000 */
11007 #define FMC_BWTR2_ACCMOD FMC_BWTR2_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
11008 #define FMC_BWTR2_ACCMOD_0 (0x1U << FMC_BWTR2_ACCMOD_Pos) /*!< 0x10000000 */
11009 #define FMC_BWTR2_ACCMOD_1 (0x2U << FMC_BWTR2_ACCMOD_Pos) /*!< 0x20000000 */
11010
11011 /****************** Bit definition for FMC_BWTR3 register ******************/
11012 #define FMC_BWTR3_ADDSET_Pos (0U)
11013 #define FMC_BWTR3_ADDSET_Msk (0xFU << FMC_BWTR3_ADDSET_Pos) /*!< 0x0000000F */
11014 #define FMC_BWTR3_ADDSET FMC_BWTR3_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
11015 #define FMC_BWTR3_ADDSET_0 (0x1U << FMC_BWTR3_ADDSET_Pos) /*!< 0x00000001 */
11016 #define FMC_BWTR3_ADDSET_1 (0x2U << FMC_BWTR3_ADDSET_Pos) /*!< 0x00000002 */
11017 #define FMC_BWTR3_ADDSET_2 (0x4U << FMC_BWTR3_ADDSET_Pos) /*!< 0x00000004 */
11018 #define FMC_BWTR3_ADDSET_3 (0x8U << FMC_BWTR3_ADDSET_Pos) /*!< 0x00000008 */
11019
11020 #define FMC_BWTR3_ADDHLD_Pos (4U)
11021 #define FMC_BWTR3_ADDHLD_Msk (0xFU << FMC_BWTR3_ADDHLD_Pos) /*!< 0x000000F0 */
11022 #define FMC_BWTR3_ADDHLD FMC_BWTR3_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
11023 #define FMC_BWTR3_ADDHLD_0 (0x1U << FMC_BWTR3_ADDHLD_Pos) /*!< 0x00000010 */
11024 #define FMC_BWTR3_ADDHLD_1 (0x2U << FMC_BWTR3_ADDHLD_Pos) /*!< 0x00000020 */
11025 #define FMC_BWTR3_ADDHLD_2 (0x4U << FMC_BWTR3_ADDHLD_Pos) /*!< 0x00000040 */
11026 #define FMC_BWTR3_ADDHLD_3 (0x8U << FMC_BWTR3_ADDHLD_Pos) /*!< 0x00000080 */
11027
11028 #define FMC_BWTR3_DATAST_Pos (8U)
11029 #define FMC_BWTR3_DATAST_Msk (0xFFU << FMC_BWTR3_DATAST_Pos) /*!< 0x0000FF00 */
11030 #define FMC_BWTR3_DATAST FMC_BWTR3_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */
11031 #define FMC_BWTR3_DATAST_0 (0x01U << FMC_BWTR3_DATAST_Pos) /*!< 0x00000100 */
11032 #define FMC_BWTR3_DATAST_1 (0x02U << FMC_BWTR3_DATAST_Pos) /*!< 0x00000200 */
11033 #define FMC_BWTR3_DATAST_2 (0x04U << FMC_BWTR3_DATAST_Pos) /*!< 0x00000400 */
11034 #define FMC_BWTR3_DATAST_3 (0x08U << FMC_BWTR3_DATAST_Pos) /*!< 0x00000800 */
11035 #define FMC_BWTR3_DATAST_4 (0x10U << FMC_BWTR3_DATAST_Pos) /*!< 0x00001000 */
11036 #define FMC_BWTR3_DATAST_5 (0x20U << FMC_BWTR3_DATAST_Pos) /*!< 0x00002000 */
11037 #define FMC_BWTR3_DATAST_6 (0x40U << FMC_BWTR3_DATAST_Pos) /*!< 0x00004000 */
11038 #define FMC_BWTR3_DATAST_7 (0x80U << FMC_BWTR3_DATAST_Pos) /*!< 0x00008000 */
11039
11040 #define FMC_BWTR3_BUSTURN_Pos (16U)
11041 #define FMC_BWTR3_BUSTURN_Msk (0xFU << FMC_BWTR3_BUSTURN_Pos) /*!< 0x000F0000 */
11042 #define FMC_BWTR3_BUSTURN FMC_BWTR3_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
11043 #define FMC_BWTR3_BUSTURN_0 (0x1U << FMC_BWTR3_BUSTURN_Pos) /*!< 0x00010000 */
11044 #define FMC_BWTR3_BUSTURN_1 (0x2U << FMC_BWTR3_BUSTURN_Pos) /*!< 0x00020000 */
11045 #define FMC_BWTR3_BUSTURN_2 (0x4U << FMC_BWTR3_BUSTURN_Pos) /*!< 0x00040000 */
11046 #define FMC_BWTR3_BUSTURN_3 (0x8U << FMC_BWTR3_BUSTURN_Pos) /*!< 0x00080000 */
11047
11048 #define FMC_BWTR3_ACCMOD_Pos (28U)
11049 #define FMC_BWTR3_ACCMOD_Msk (0x3U << FMC_BWTR3_ACCMOD_Pos) /*!< 0x30000000 */
11050 #define FMC_BWTR3_ACCMOD FMC_BWTR3_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
11051 #define FMC_BWTR3_ACCMOD_0 (0x1U << FMC_BWTR3_ACCMOD_Pos) /*!< 0x10000000 */
11052 #define FMC_BWTR3_ACCMOD_1 (0x2U << FMC_BWTR3_ACCMOD_Pos) /*!< 0x20000000 */
11053
11054 /****************** Bit definition for FMC_BWTR4 register ******************/
11055 #define FMC_BWTR4_ADDSET_Pos (0U)
11056 #define FMC_BWTR4_ADDSET_Msk (0xFU << FMC_BWTR4_ADDSET_Pos) /*!< 0x0000000F */
11057 #define FMC_BWTR4_ADDSET FMC_BWTR4_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
11058 #define FMC_BWTR4_ADDSET_0 (0x1U << FMC_BWTR4_ADDSET_Pos) /*!< 0x00000001 */
11059 #define FMC_BWTR4_ADDSET_1 (0x2U << FMC_BWTR4_ADDSET_Pos) /*!< 0x00000002 */
11060 #define FMC_BWTR4_ADDSET_2 (0x4U << FMC_BWTR4_ADDSET_Pos) /*!< 0x00000004 */
11061 #define FMC_BWTR4_ADDSET_3 (0x8U << FMC_BWTR4_ADDSET_Pos) /*!< 0x00000008 */
11062
11063 #define FMC_BWTR4_ADDHLD_Pos (4U)
11064 #define FMC_BWTR4_ADDHLD_Msk (0xFU << FMC_BWTR4_ADDHLD_Pos) /*!< 0x000000F0 */
11065 #define FMC_BWTR4_ADDHLD FMC_BWTR4_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
11066 #define FMC_BWTR4_ADDHLD_0 (0x1U << FMC_BWTR4_ADDHLD_Pos) /*!< 0x00000010 */
11067 #define FMC_BWTR4_ADDHLD_1 (0x2U << FMC_BWTR4_ADDHLD_Pos) /*!< 0x00000020 */
11068 #define FMC_BWTR4_ADDHLD_2 (0x4U << FMC_BWTR4_ADDHLD_Pos) /*!< 0x00000040 */
11069 #define FMC_BWTR4_ADDHLD_3 (0x8U << FMC_BWTR4_ADDHLD_Pos) /*!< 0x00000080 */
11070
11071 #define FMC_BWTR4_DATAST_Pos (8U)
11072 #define FMC_BWTR4_DATAST_Msk (0xFFU << FMC_BWTR4_DATAST_Pos) /*!< 0x0000FF00 */
11073 #define FMC_BWTR4_DATAST FMC_BWTR4_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */
11074 #define FMC_BWTR4_DATAST_0 (0x01U << FMC_BWTR4_DATAST_Pos) /*!< 0x00000100 */
11075 #define FMC_BWTR4_DATAST_1 (0x02U << FMC_BWTR4_DATAST_Pos) /*!< 0x00000200 */
11076 #define FMC_BWTR4_DATAST_2 (0x04U << FMC_BWTR4_DATAST_Pos) /*!< 0x00000400 */
11077 #define FMC_BWTR4_DATAST_3 (0x08U << FMC_BWTR4_DATAST_Pos) /*!< 0x00000800 */
11078 #define FMC_BWTR4_DATAST_4 (0x10U << FMC_BWTR4_DATAST_Pos) /*!< 0x00001000 */
11079 #define FMC_BWTR4_DATAST_5 (0x20U << FMC_BWTR4_DATAST_Pos) /*!< 0x00002000 */
11080 #define FMC_BWTR4_DATAST_6 (0x40U << FMC_BWTR4_DATAST_Pos) /*!< 0x00004000 */
11081 #define FMC_BWTR4_DATAST_7 (0x80U << FMC_BWTR4_DATAST_Pos) /*!< 0x00008000 */
11082
11083 #define FMC_BWTR4_BUSTURN_Pos (16U)
11084 #define FMC_BWTR4_BUSTURN_Msk (0xFU << FMC_BWTR4_BUSTURN_Pos) /*!< 0x000F0000 */
11085 #define FMC_BWTR4_BUSTURN FMC_BWTR4_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
11086 #define FMC_BWTR4_BUSTURN_0 (0x1U << FMC_BWTR4_BUSTURN_Pos) /*!< 0x00010000 */
11087 #define FMC_BWTR4_BUSTURN_1 (0x2U << FMC_BWTR4_BUSTURN_Pos) /*!< 0x00020000 */
11088 #define FMC_BWTR4_BUSTURN_2 (0x4U << FMC_BWTR4_BUSTURN_Pos) /*!< 0x00040000 */
11089 #define FMC_BWTR4_BUSTURN_3 (0x8U << FMC_BWTR4_BUSTURN_Pos) /*!< 0x00080000 */
11090
11091 #define FMC_BWTR4_ACCMOD_Pos (28U)
11092 #define FMC_BWTR4_ACCMOD_Msk (0x3U << FMC_BWTR4_ACCMOD_Pos) /*!< 0x30000000 */
11093 #define FMC_BWTR4_ACCMOD FMC_BWTR4_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
11094 #define FMC_BWTR4_ACCMOD_0 (0x1U << FMC_BWTR4_ACCMOD_Pos) /*!< 0x10000000 */
11095 #define FMC_BWTR4_ACCMOD_1 (0x2U << FMC_BWTR4_ACCMOD_Pos) /*!< 0x20000000 */
11096
11097 /****************** Bit definition for FMC_PCR register *******************/
11098 #define FMC_PCR_PWAITEN_Pos (1U)
11099 #define FMC_PCR_PWAITEN_Msk (0x1U << FMC_PCR_PWAITEN_Pos) /*!< 0x00000002 */
11100 #define FMC_PCR_PWAITEN FMC_PCR_PWAITEN_Msk /*!<Wait feature enable bit */
11101 #define FMC_PCR_PBKEN_Pos (2U)
11102 #define FMC_PCR_PBKEN_Msk (0x1U << FMC_PCR_PBKEN_Pos) /*!< 0x00000004 */
11103 #define FMC_PCR_PBKEN FMC_PCR_PBKEN_Msk /*!<PC Card/NAND Flash memory bank enable bit */
11104 #define FMC_PCR_PTYP_Pos (3U)
11105 #define FMC_PCR_PTYP_Msk (0x1U << FMC_PCR_PTYP_Pos) /*!< 0x00000008 */
11106 #define FMC_PCR_PTYP FMC_PCR_PTYP_Msk /*!<Memory type */
11107
11108 #define FMC_PCR_PWID_Pos (4U)
11109 #define FMC_PCR_PWID_Msk (0x3U << FMC_PCR_PWID_Pos) /*!< 0x00000030 */
11110 #define FMC_PCR_PWID FMC_PCR_PWID_Msk /*!<PWID[1:0] bits (NAND Flash databus width) */
11111 #define FMC_PCR_PWID_0 (0x1U << FMC_PCR_PWID_Pos) /*!< 0x00000010 */
11112 #define FMC_PCR_PWID_1 (0x2U << FMC_PCR_PWID_Pos) /*!< 0x00000020 */
11113
11114 #define FMC_PCR_ECCEN_Pos (6U)
11115 #define FMC_PCR_ECCEN_Msk (0x1U << FMC_PCR_ECCEN_Pos) /*!< 0x00000040 */
11116 #define FMC_PCR_ECCEN FMC_PCR_ECCEN_Msk /*!<ECC computation logic enable bit */
11117
11118 #define FMC_PCR_TCLR_Pos (9U)
11119 #define FMC_PCR_TCLR_Msk (0xFU << FMC_PCR_TCLR_Pos) /*!< 0x00001E00 */
11120 #define FMC_PCR_TCLR FMC_PCR_TCLR_Msk /*!<TCLR[3:0] bits (CLE to RE delay) */
11121 #define FMC_PCR_TCLR_0 (0x1U << FMC_PCR_TCLR_Pos) /*!< 0x00000200 */
11122 #define FMC_PCR_TCLR_1 (0x2U << FMC_PCR_TCLR_Pos) /*!< 0x00000400 */
11123 #define FMC_PCR_TCLR_2 (0x4U << FMC_PCR_TCLR_Pos) /*!< 0x00000800 */
11124 #define FMC_PCR_TCLR_3 (0x8U << FMC_PCR_TCLR_Pos) /*!< 0x00001000 */
11125
11126 #define FMC_PCR_TAR_Pos (13U)
11127 #define FMC_PCR_TAR_Msk (0xFU << FMC_PCR_TAR_Pos) /*!< 0x0001E000 */
11128 #define FMC_PCR_TAR FMC_PCR_TAR_Msk /*!<TAR[3:0] bits (ALE to RE delay) */
11129 #define FMC_PCR_TAR_0 (0x1U << FMC_PCR_TAR_Pos) /*!< 0x00002000 */
11130 #define FMC_PCR_TAR_1 (0x2U << FMC_PCR_TAR_Pos) /*!< 0x00004000 */
11131 #define FMC_PCR_TAR_2 (0x4U << FMC_PCR_TAR_Pos) /*!< 0x00008000 */
11132 #define FMC_PCR_TAR_3 (0x8U << FMC_PCR_TAR_Pos) /*!< 0x00010000 */
11133
11134 #define FMC_PCR_ECCPS_Pos (17U)
11135 #define FMC_PCR_ECCPS_Msk (0x7U << FMC_PCR_ECCPS_Pos) /*!< 0x000E0000 */
11136 #define FMC_PCR_ECCPS FMC_PCR_ECCPS_Msk /*!<ECCPS[1:0] bits (ECC page size) */
11137 #define FMC_PCR_ECCPS_0 (0x1U << FMC_PCR_ECCPS_Pos) /*!< 0x00020000 */
11138 #define FMC_PCR_ECCPS_1 (0x2U << FMC_PCR_ECCPS_Pos) /*!< 0x00040000 */
11139 #define FMC_PCR_ECCPS_2 (0x4U << FMC_PCR_ECCPS_Pos) /*!< 0x00080000 */
11140
11141 /******************* Bit definition for FMC_SR register *******************/
11142 #define FMC_SR_IRS_Pos (0U)
11143 #define FMC_SR_IRS_Msk (0x1U << FMC_SR_IRS_Pos) /*!< 0x00000001 */
11144 #define FMC_SR_IRS FMC_SR_IRS_Msk /*!<Interrupt Rising Edge status */
11145 #define FMC_SR_ILS_Pos (1U)
11146 #define FMC_SR_ILS_Msk (0x1U << FMC_SR_ILS_Pos) /*!< 0x00000002 */
11147 #define FMC_SR_ILS FMC_SR_ILS_Msk /*!<Interrupt Level status */
11148 #define FMC_SR_IFS_Pos (2U)
11149 #define FMC_SR_IFS_Msk (0x1U << FMC_SR_IFS_Pos) /*!< 0x00000004 */
11150 #define FMC_SR_IFS FMC_SR_IFS_Msk /*!<Interrupt Falling Edge status */
11151 #define FMC_SR_IREN_Pos (3U)
11152 #define FMC_SR_IREN_Msk (0x1U << FMC_SR_IREN_Pos) /*!< 0x00000008 */
11153 #define FMC_SR_IREN FMC_SR_IREN_Msk /*!<Interrupt Rising Edge detection Enable bit */
11154 #define FMC_SR_ILEN_Pos (4U)
11155 #define FMC_SR_ILEN_Msk (0x1U << FMC_SR_ILEN_Pos) /*!< 0x00000010 */
11156 #define FMC_SR_ILEN FMC_SR_ILEN_Msk /*!<Interrupt Level detection Enable bit */
11157 #define FMC_SR_IFEN_Pos (5U)
11158 #define FMC_SR_IFEN_Msk (0x1U << FMC_SR_IFEN_Pos) /*!< 0x00000020 */
11159 #define FMC_SR_IFEN FMC_SR_IFEN_Msk /*!<Interrupt Falling Edge detection Enable bit */
11160 #define FMC_SR_FEMPT_Pos (6U)
11161 #define FMC_SR_FEMPT_Msk (0x1U << FMC_SR_FEMPT_Pos) /*!< 0x00000040 */
11162 #define FMC_SR_FEMPT FMC_SR_FEMPT_Msk /*!<FIFO empty */
11163
11164 /****************** Bit definition for FMC_PMEM register ******************/
11165 #define FMC_PMEM_MEMSET2_Pos (0U)
11166 #define FMC_PMEM_MEMSET2_Msk (0xFFU << FMC_PMEM_MEMSET2_Pos) /*!< 0x000000FF */
11167 #define FMC_PMEM_MEMSET2 FMC_PMEM_MEMSET2_Msk /*!<MEMSET2[7:0] bits (Common memory 2 setup time) */
11168 #define FMC_PMEM_MEMSET2_0 (0x01U << FMC_PMEM_MEMSET2_Pos) /*!< 0x00000001 */
11169 #define FMC_PMEM_MEMSET2_1 (0x02U << FMC_PMEM_MEMSET2_Pos) /*!< 0x00000002 */
11170 #define FMC_PMEM_MEMSET2_2 (0x04U << FMC_PMEM_MEMSET2_Pos) /*!< 0x00000004 */
11171 #define FMC_PMEM_MEMSET2_3 (0x08U << FMC_PMEM_MEMSET2_Pos) /*!< 0x00000008 */
11172 #define FMC_PMEM_MEMSET2_4 (0x10U << FMC_PMEM_MEMSET2_Pos) /*!< 0x00000010 */
11173 #define FMC_PMEM_MEMSET2_5 (0x20U << FMC_PMEM_MEMSET2_Pos) /*!< 0x00000020 */
11174 #define FMC_PMEM_MEMSET2_6 (0x40U << FMC_PMEM_MEMSET2_Pos) /*!< 0x00000040 */
11175 #define FMC_PMEM_MEMSET2_7 (0x80U << FMC_PMEM_MEMSET2_Pos) /*!< 0x00000080 */
11176
11177 #define FMC_PMEM_MEMWAIT2_Pos (8U)
11178 #define FMC_PMEM_MEMWAIT2_Msk (0xFFU << FMC_PMEM_MEMWAIT2_Pos) /*!< 0x0000FF00 */
11179 #define FMC_PMEM_MEMWAIT2 FMC_PMEM_MEMWAIT2_Msk /*!<MEMWAIT2[7:0] bits (Common memory 2 wait time) */
11180 #define FMC_PMEM_MEMWAIT2_0 (0x01U << FMC_PMEM_MEMWAIT2_Pos) /*!< 0x00000100 */
11181 #define FMC_PMEM_MEMWAIT2_1 (0x02U << FMC_PMEM_MEMWAIT2_Pos) /*!< 0x00000200 */
11182 #define FMC_PMEM_MEMWAIT2_2 (0x04U << FMC_PMEM_MEMWAIT2_Pos) /*!< 0x00000400 */
11183 #define FMC_PMEM_MEMWAIT2_3 (0x08U << FMC_PMEM_MEMWAIT2_Pos) /*!< 0x00000800 */
11184 #define FMC_PMEM_MEMWAIT2_4 (0x10U << FMC_PMEM_MEMWAIT2_Pos) /*!< 0x00001000 */
11185 #define FMC_PMEM_MEMWAIT2_5 (0x20U << FMC_PMEM_MEMWAIT2_Pos) /*!< 0x00002000 */
11186 #define FMC_PMEM_MEMWAIT2_6 (0x40U << FMC_PMEM_MEMWAIT2_Pos) /*!< 0x00004000 */
11187 #define FMC_PMEM_MEMWAIT2_7 (0x80U << FMC_PMEM_MEMWAIT2_Pos) /*!< 0x00008000 */
11188
11189 #define FMC_PMEM_MEMHOLD2_Pos (16U)
11190 #define FMC_PMEM_MEMHOLD2_Msk (0xFFU << FMC_PMEM_MEMHOLD2_Pos) /*!< 0x00FF0000 */
11191 #define FMC_PMEM_MEMHOLD2 FMC_PMEM_MEMHOLD2_Msk /*!<MEMHOLD2[7:0] bits (Common memory 2 hold time) */
11192 #define FMC_PMEM_MEMHOLD2_0 (0x01U << FMC_PMEM_MEMHOLD2_Pos) /*!< 0x00010000 */
11193 #define FMC_PMEM_MEMHOLD2_1 (0x02U << FMC_PMEM_MEMHOLD2_Pos) /*!< 0x00020000 */
11194 #define FMC_PMEM_MEMHOLD2_2 (0x04U << FMC_PMEM_MEMHOLD2_Pos) /*!< 0x00040000 */
11195 #define FMC_PMEM_MEMHOLD2_3 (0x08U << FMC_PMEM_MEMHOLD2_Pos) /*!< 0x00080000 */
11196 #define FMC_PMEM_MEMHOLD2_4 (0x10U << FMC_PMEM_MEMHOLD2_Pos) /*!< 0x00100000 */
11197 #define FMC_PMEM_MEMHOLD2_5 (0x20U << FMC_PMEM_MEMHOLD2_Pos) /*!< 0x00200000 */
11198 #define FMC_PMEM_MEMHOLD2_6 (0x40U << FMC_PMEM_MEMHOLD2_Pos) /*!< 0x00400000 */
11199 #define FMC_PMEM_MEMHOLD2_7 (0x80U << FMC_PMEM_MEMHOLD2_Pos) /*!< 0x00800000 */
11200
11201 #define FMC_PMEM_MEMHIZ2_Pos (24U)
11202 #define FMC_PMEM_MEMHIZ2_Msk (0xFFU << FMC_PMEM_MEMHIZ2_Pos) /*!< 0xFF000000 */
11203 #define FMC_PMEM_MEMHIZ2 FMC_PMEM_MEMHIZ2_Msk /*!<MEMHIZ2[7:0] bits (Common memory 2 databus HiZ time) */
11204 #define FMC_PMEM_MEMHIZ2_0 (0x01U << FMC_PMEM_MEMHIZ2_Pos) /*!< 0x01000000 */
11205 #define FMC_PMEM_MEMHIZ2_1 (0x02U << FMC_PMEM_MEMHIZ2_Pos) /*!< 0x02000000 */
11206 #define FMC_PMEM_MEMHIZ2_2 (0x04U << FMC_PMEM_MEMHIZ2_Pos) /*!< 0x04000000 */
11207 #define FMC_PMEM_MEMHIZ2_3 (0x08U << FMC_PMEM_MEMHIZ2_Pos) /*!< 0x08000000 */
11208 #define FMC_PMEM_MEMHIZ2_4 (0x10U << FMC_PMEM_MEMHIZ2_Pos) /*!< 0x10000000 */
11209 #define FMC_PMEM_MEMHIZ2_5 (0x20U << FMC_PMEM_MEMHIZ2_Pos) /*!< 0x20000000 */
11210 #define FMC_PMEM_MEMHIZ2_6 (0x40U << FMC_PMEM_MEMHIZ2_Pos) /*!< 0x40000000 */
11211 #define FMC_PMEM_MEMHIZ2_7 (0x80U << FMC_PMEM_MEMHIZ2_Pos) /*!< 0x80000000 */
11212
11213 /****************** Bit definition for FMC_PATT register ******************/
11214 #define FMC_PATT_ATTSET2_Pos (0U)
11215 #define FMC_PATT_ATTSET2_Msk (0xFFU << FMC_PATT_ATTSET2_Pos) /*!< 0x000000FF */
11216 #define FMC_PATT_ATTSET2 FMC_PATT_ATTSET2_Msk /*!<ATTSET2[7:0] bits (Attribute memory 2 setup time) */
11217 #define FMC_PATT_ATTSET2_0 (0x01U << FMC_PATT_ATTSET2_Pos) /*!< 0x00000001 */
11218 #define FMC_PATT_ATTSET2_1 (0x02U << FMC_PATT_ATTSET2_Pos) /*!< 0x00000002 */
11219 #define FMC_PATT_ATTSET2_2 (0x04U << FMC_PATT_ATTSET2_Pos) /*!< 0x00000004 */
11220 #define FMC_PATT_ATTSET2_3 (0x08U << FMC_PATT_ATTSET2_Pos) /*!< 0x00000008 */
11221 #define FMC_PATT_ATTSET2_4 (0x10U << FMC_PATT_ATTSET2_Pos) /*!< 0x00000010 */
11222 #define FMC_PATT_ATTSET2_5 (0x20U << FMC_PATT_ATTSET2_Pos) /*!< 0x00000020 */
11223 #define FMC_PATT_ATTSET2_6 (0x40U << FMC_PATT_ATTSET2_Pos) /*!< 0x00000040 */
11224 #define FMC_PATT_ATTSET2_7 (0x80U << FMC_PATT_ATTSET2_Pos) /*!< 0x00000080 */
11225
11226 #define FMC_PATT_ATTWAIT2_Pos (8U)
11227 #define FMC_PATT_ATTWAIT2_Msk (0xFFU << FMC_PATT_ATTWAIT2_Pos) /*!< 0x0000FF00 */
11228 #define FMC_PATT_ATTWAIT2 FMC_PATT_ATTWAIT2_Msk /*!<ATTWAIT2[7:0] bits (Attribute memory 2 wait time) */
11229 #define FMC_PATT_ATTWAIT2_0 (0x01U << FMC_PATT_ATTWAIT2_Pos) /*!< 0x00000100 */
11230 #define FMC_PATT_ATTWAIT2_1 (0x02U << FMC_PATT_ATTWAIT2_Pos) /*!< 0x00000200 */
11231 #define FMC_PATT_ATTWAIT2_2 (0x04U << FMC_PATT_ATTWAIT2_Pos) /*!< 0x00000400 */
11232 #define FMC_PATT_ATTWAIT2_3 (0x08U << FMC_PATT_ATTWAIT2_Pos) /*!< 0x00000800 */
11233 #define FMC_PATT_ATTWAIT2_4 (0x10U << FMC_PATT_ATTWAIT2_Pos) /*!< 0x00001000 */
11234 #define FMC_PATT_ATTWAIT2_5 (0x20U << FMC_PATT_ATTWAIT2_Pos) /*!< 0x00002000 */
11235 #define FMC_PATT_ATTWAIT2_6 (0x40U << FMC_PATT_ATTWAIT2_Pos) /*!< 0x00004000 */
11236 #define FMC_PATT_ATTWAIT2_7 (0x80U << FMC_PATT_ATTWAIT2_Pos) /*!< 0x00008000 */
11237
11238 #define FMC_PATT_ATTHOLD2_Pos (16U)
11239 #define FMC_PATT_ATTHOLD2_Msk (0xFFU << FMC_PATT_ATTHOLD2_Pos) /*!< 0x00FF0000 */
11240 #define FMC_PATT_ATTHOLD2 FMC_PATT_ATTHOLD2_Msk /*!<ATTHOLD2[7:0] bits (Attribute memory 2 hold time) */
11241 #define FMC_PATT_ATTHOLD2_0 (0x01U << FMC_PATT_ATTHOLD2_Pos) /*!< 0x00010000 */
11242 #define FMC_PATT_ATTHOLD2_1 (0x02U << FMC_PATT_ATTHOLD2_Pos) /*!< 0x00020000 */
11243 #define FMC_PATT_ATTHOLD2_2 (0x04U << FMC_PATT_ATTHOLD2_Pos) /*!< 0x00040000 */
11244 #define FMC_PATT_ATTHOLD2_3 (0x08U << FMC_PATT_ATTHOLD2_Pos) /*!< 0x00080000 */
11245 #define FMC_PATT_ATTHOLD2_4 (0x10U << FMC_PATT_ATTHOLD2_Pos) /*!< 0x00100000 */
11246 #define FMC_PATT_ATTHOLD2_5 (0x20U << FMC_PATT_ATTHOLD2_Pos) /*!< 0x00200000 */
11247 #define FMC_PATT_ATTHOLD2_6 (0x40U << FMC_PATT_ATTHOLD2_Pos) /*!< 0x00400000 */
11248 #define FMC_PATT_ATTHOLD2_7 (0x80U << FMC_PATT_ATTHOLD2_Pos) /*!< 0x00800000 */
11249
11250 #define FMC_PATT_ATTHIZ2_Pos (24U)
11251 #define FMC_PATT_ATTHIZ2_Msk (0xFFU << FMC_PATT_ATTHIZ2_Pos) /*!< 0xFF000000 */
11252 #define FMC_PATT_ATTHIZ2 FMC_PATT_ATTHIZ2_Msk /*!<ATTHIZ2[7:0] bits (Attribute memory 2 databus HiZ time) */
11253 #define FMC_PATT_ATTHIZ2_0 (0x01U << FMC_PATT_ATTHIZ2_Pos) /*!< 0x01000000 */
11254 #define FMC_PATT_ATTHIZ2_1 (0x02U << FMC_PATT_ATTHIZ2_Pos) /*!< 0x02000000 */
11255 #define FMC_PATT_ATTHIZ2_2 (0x04U << FMC_PATT_ATTHIZ2_Pos) /*!< 0x04000000 */
11256 #define FMC_PATT_ATTHIZ2_3 (0x08U << FMC_PATT_ATTHIZ2_Pos) /*!< 0x08000000 */
11257 #define FMC_PATT_ATTHIZ2_4 (0x10U << FMC_PATT_ATTHIZ2_Pos) /*!< 0x10000000 */
11258 #define FMC_PATT_ATTHIZ2_5 (0x20U << FMC_PATT_ATTHIZ2_Pos) /*!< 0x20000000 */
11259 #define FMC_PATT_ATTHIZ2_6 (0x40U << FMC_PATT_ATTHIZ2_Pos) /*!< 0x40000000 */
11260 #define FMC_PATT_ATTHIZ2_7 (0x80U << FMC_PATT_ATTHIZ2_Pos) /*!< 0x80000000 */
11261
11262 /****************** Bit definition for FMC_ECCR register ******************/
11263 #define FMC_ECCR_ECC2_Pos (0U)
11264 #define FMC_ECCR_ECC2_Msk (0xFFFFFFFFU << FMC_ECCR_ECC2_Pos) /*!< 0xFFFFFFFF */
11265 #define FMC_ECCR_ECC2 FMC_ECCR_ECC2_Msk /*!<ECC result */
11266
11267 /****************** Bit definition for FMC_SDCR1 register ******************/
11268 #define FMC_SDCR1_NC_Pos (0U)
11269 #define FMC_SDCR1_NC_Msk (0x3U << FMC_SDCR1_NC_Pos) /*!< 0x00000003 */
11270 #define FMC_SDCR1_NC FMC_SDCR1_NC_Msk /*!<NC[1:0] bits (Number of column bits) */
11271 #define FMC_SDCR1_NC_0 (0x1U << FMC_SDCR1_NC_Pos) /*!< 0x00000001 */
11272 #define FMC_SDCR1_NC_1 (0x2U << FMC_SDCR1_NC_Pos) /*!< 0x00000002 */
11273
11274 #define FMC_SDCR1_NR_Pos (2U)
11275 #define FMC_SDCR1_NR_Msk (0x3U << FMC_SDCR1_NR_Pos) /*!< 0x0000000C */
11276 #define FMC_SDCR1_NR FMC_SDCR1_NR_Msk /*!<NR[1:0] bits (Number of row bits) */
11277 #define FMC_SDCR1_NR_0 (0x1U << FMC_SDCR1_NR_Pos) /*!< 0x00000004 */
11278 #define FMC_SDCR1_NR_1 (0x2U << FMC_SDCR1_NR_Pos) /*!< 0x00000008 */
11279
11280 #define FMC_SDCR1_MWID_Pos (4U)
11281 #define FMC_SDCR1_MWID_Msk (0x3U << FMC_SDCR1_MWID_Pos) /*!< 0x00000030 */
11282 #define FMC_SDCR1_MWID FMC_SDCR1_MWID_Msk /*!<NR[1:0] bits (Number of row bits) */
11283 #define FMC_SDCR1_MWID_0 (0x1U << FMC_SDCR1_MWID_Pos) /*!< 0x00000010 */
11284 #define FMC_SDCR1_MWID_1 (0x2U << FMC_SDCR1_MWID_Pos) /*!< 0x00000020 */
11285
11286 #define FMC_SDCR1_NB_Pos (6U)
11287 #define FMC_SDCR1_NB_Msk (0x1U << FMC_SDCR1_NB_Pos) /*!< 0x00000040 */
11288 #define FMC_SDCR1_NB FMC_SDCR1_NB_Msk /*!<Number of internal bank */
11289
11290 #define FMC_SDCR1_CAS_Pos (7U)
11291 #define FMC_SDCR1_CAS_Msk (0x3U << FMC_SDCR1_CAS_Pos) /*!< 0x00000180 */
11292 #define FMC_SDCR1_CAS FMC_SDCR1_CAS_Msk /*!<CAS[1:0] bits (CAS latency) */
11293 #define FMC_SDCR1_CAS_0 (0x1U << FMC_SDCR1_CAS_Pos) /*!< 0x00000080 */
11294 #define FMC_SDCR1_CAS_1 (0x2U << FMC_SDCR1_CAS_Pos) /*!< 0x00000100 */
11295
11296 #define FMC_SDCR1_WP_Pos (9U)
11297 #define FMC_SDCR1_WP_Msk (0x1U << FMC_SDCR1_WP_Pos) /*!< 0x00000200 */
11298 #define FMC_SDCR1_WP FMC_SDCR1_WP_Msk /*!<Write protection */
11299
11300 #define FMC_SDCR1_SDCLK_Pos (10U)
11301 #define FMC_SDCR1_SDCLK_Msk (0x3U << FMC_SDCR1_SDCLK_Pos) /*!< 0x00000C00 */
11302 #define FMC_SDCR1_SDCLK FMC_SDCR1_SDCLK_Msk /*!<SDRAM clock configuration */
11303 #define FMC_SDCR1_SDCLK_0 (0x1U << FMC_SDCR1_SDCLK_Pos) /*!< 0x00000400 */
11304 #define FMC_SDCR1_SDCLK_1 (0x2U << FMC_SDCR1_SDCLK_Pos) /*!< 0x00000800 */
11305
11306 #define FMC_SDCR1_RBURST_Pos (12U)
11307 #define FMC_SDCR1_RBURST_Msk (0x1U << FMC_SDCR1_RBURST_Pos) /*!< 0x00001000 */
11308 #define FMC_SDCR1_RBURST FMC_SDCR1_RBURST_Msk /*!<Read burst */
11309
11310 #define FMC_SDCR1_RPIPE_Pos (13U)
11311 #define FMC_SDCR1_RPIPE_Msk (0x3U << FMC_SDCR1_RPIPE_Pos) /*!< 0x00006000 */
11312 #define FMC_SDCR1_RPIPE FMC_SDCR1_RPIPE_Msk /*!<Write protection */
11313 #define FMC_SDCR1_RPIPE_0 (0x1U << FMC_SDCR1_RPIPE_Pos) /*!< 0x00002000 */
11314 #define FMC_SDCR1_RPIPE_1 (0x2U << FMC_SDCR1_RPIPE_Pos) /*!< 0x00004000 */
11315
11316 /****************** Bit definition for FMC_SDCR2 register ******************/
11317 #define FMC_SDCR2_NC_Pos (0U)
11318 #define FMC_SDCR2_NC_Msk (0x3U << FMC_SDCR2_NC_Pos) /*!< 0x00000003 */
11319 #define FMC_SDCR2_NC FMC_SDCR2_NC_Msk /*!<NC[1:0] bits (Number of column bits) */
11320 #define FMC_SDCR2_NC_0 (0x1U << FMC_SDCR2_NC_Pos) /*!< 0x00000001 */
11321 #define FMC_SDCR2_NC_1 (0x2U << FMC_SDCR2_NC_Pos) /*!< 0x00000002 */
11322
11323 #define FMC_SDCR2_NR_Pos (2U)
11324 #define FMC_SDCR2_NR_Msk (0x3U << FMC_SDCR2_NR_Pos) /*!< 0x0000000C */
11325 #define FMC_SDCR2_NR FMC_SDCR2_NR_Msk /*!<NR[1:0] bits (Number of row bits) */
11326 #define FMC_SDCR2_NR_0 (0x1U << FMC_SDCR2_NR_Pos) /*!< 0x00000004 */
11327 #define FMC_SDCR2_NR_1 (0x2U << FMC_SDCR2_NR_Pos) /*!< 0x00000008 */
11328
11329 #define FMC_SDCR2_MWID_Pos (4U)
11330 #define FMC_SDCR2_MWID_Msk (0x3U << FMC_SDCR2_MWID_Pos) /*!< 0x00000030 */
11331 #define FMC_SDCR2_MWID FMC_SDCR2_MWID_Msk /*!<NR[1:0] bits (Number of row bits) */
11332 #define FMC_SDCR2_MWID_0 (0x1U << FMC_SDCR2_MWID_Pos) /*!< 0x00000010 */
11333 #define FMC_SDCR2_MWID_1 (0x2U << FMC_SDCR2_MWID_Pos) /*!< 0x00000020 */
11334
11335 #define FMC_SDCR2_NB_Pos (6U)
11336 #define FMC_SDCR2_NB_Msk (0x1U << FMC_SDCR2_NB_Pos) /*!< 0x00000040 */
11337 #define FMC_SDCR2_NB FMC_SDCR2_NB_Msk /*!<Number of internal bank */
11338
11339 #define FMC_SDCR2_CAS_Pos (7U)
11340 #define FMC_SDCR2_CAS_Msk (0x3U << FMC_SDCR2_CAS_Pos) /*!< 0x00000180 */
11341 #define FMC_SDCR2_CAS FMC_SDCR2_CAS_Msk /*!<CAS[1:0] bits (CAS latency) */
11342 #define FMC_SDCR2_CAS_0 (0x1U << FMC_SDCR2_CAS_Pos) /*!< 0x00000080 */
11343 #define FMC_SDCR2_CAS_1 (0x2U << FMC_SDCR2_CAS_Pos) /*!< 0x00000100 */
11344
11345 #define FMC_SDCR2_WP_Pos (9U)
11346 #define FMC_SDCR2_WP_Msk (0x1U << FMC_SDCR2_WP_Pos) /*!< 0x00000200 */
11347 #define FMC_SDCR2_WP FMC_SDCR2_WP_Msk /*!<Write protection */
11348
11349 #define FMC_SDCR2_SDCLK_Pos (10U)
11350 #define FMC_SDCR2_SDCLK_Msk (0x3U << FMC_SDCR2_SDCLK_Pos) /*!< 0x00000C00 */
11351 #define FMC_SDCR2_SDCLK FMC_SDCR2_SDCLK_Msk /*!<SDCLK[1:0] (SDRAM clock configuration) */
11352 #define FMC_SDCR2_SDCLK_0 (0x1U << FMC_SDCR2_SDCLK_Pos) /*!< 0x00000400 */
11353 #define FMC_SDCR2_SDCLK_1 (0x2U << FMC_SDCR2_SDCLK_Pos) /*!< 0x00000800 */
11354
11355 #define FMC_SDCR2_RBURST_Pos (12U)
11356 #define FMC_SDCR2_RBURST_Msk (0x1U << FMC_SDCR2_RBURST_Pos) /*!< 0x00001000 */
11357 #define FMC_SDCR2_RBURST FMC_SDCR2_RBURST_Msk /*!<Read burst */
11358
11359 #define FMC_SDCR2_RPIPE_Pos (13U)
11360 #define FMC_SDCR2_RPIPE_Msk (0x3U << FMC_SDCR2_RPIPE_Pos) /*!< 0x00006000 */
11361 #define FMC_SDCR2_RPIPE FMC_SDCR2_RPIPE_Msk /*!<RPIPE[1:0](Read pipe) */
11362 #define FMC_SDCR2_RPIPE_0 (0x1U << FMC_SDCR2_RPIPE_Pos) /*!< 0x00002000 */
11363 #define FMC_SDCR2_RPIPE_1 (0x2U << FMC_SDCR2_RPIPE_Pos) /*!< 0x00004000 */
11364
11365 /****************** Bit definition for FMC_SDTR1 register ******************/
11366 #define FMC_SDTR1_TMRD_Pos (0U)
11367 #define FMC_SDTR1_TMRD_Msk (0xFU << FMC_SDTR1_TMRD_Pos) /*!< 0x0000000F */
11368 #define FMC_SDTR1_TMRD FMC_SDTR1_TMRD_Msk /*!<TMRD[3:0] bits (Load mode register to active) */
11369 #define FMC_SDTR1_TMRD_0 (0x1U << FMC_SDTR1_TMRD_Pos) /*!< 0x00000001 */
11370 #define FMC_SDTR1_TMRD_1 (0x2U << FMC_SDTR1_TMRD_Pos) /*!< 0x00000002 */
11371 #define FMC_SDTR1_TMRD_2 (0x4U << FMC_SDTR1_TMRD_Pos) /*!< 0x00000004 */
11372 #define FMC_SDTR1_TMRD_3 (0x8U << FMC_SDTR1_TMRD_Pos) /*!< 0x00000008 */
11373
11374 #define FMC_SDTR1_TXSR_Pos (4U)
11375 #define FMC_SDTR1_TXSR_Msk (0xFU << FMC_SDTR1_TXSR_Pos) /*!< 0x000000F0 */
11376 #define FMC_SDTR1_TXSR FMC_SDTR1_TXSR_Msk /*!<TXSR[3:0] bits (Exit self refresh) */
11377 #define FMC_SDTR1_TXSR_0 (0x1U << FMC_SDTR1_TXSR_Pos) /*!< 0x00000010 */
11378 #define FMC_SDTR1_TXSR_1 (0x2U << FMC_SDTR1_TXSR_Pos) /*!< 0x00000020 */
11379 #define FMC_SDTR1_TXSR_2 (0x4U << FMC_SDTR1_TXSR_Pos) /*!< 0x00000040 */
11380 #define FMC_SDTR1_TXSR_3 (0x8U << FMC_SDTR1_TXSR_Pos) /*!< 0x00000080 */
11381
11382 #define FMC_SDTR1_TRAS_Pos (8U)
11383 #define FMC_SDTR1_TRAS_Msk (0xFU << FMC_SDTR1_TRAS_Pos) /*!< 0x00000F00 */
11384 #define FMC_SDTR1_TRAS FMC_SDTR1_TRAS_Msk /*!<TRAS[3:0] bits (Self refresh time) */
11385 #define FMC_SDTR1_TRAS_0 (0x1U << FMC_SDTR1_TRAS_Pos) /*!< 0x00000100 */
11386 #define FMC_SDTR1_TRAS_1 (0x2U << FMC_SDTR1_TRAS_Pos) /*!< 0x00000200 */
11387 #define FMC_SDTR1_TRAS_2 (0x4U << FMC_SDTR1_TRAS_Pos) /*!< 0x00000400 */
11388 #define FMC_SDTR1_TRAS_3 (0x8U << FMC_SDTR1_TRAS_Pos) /*!< 0x00000800 */
11389
11390 #define FMC_SDTR1_TRC_Pos (12U)
11391 #define FMC_SDTR1_TRC_Msk (0xFU << FMC_SDTR1_TRC_Pos) /*!< 0x0000F000 */
11392 #define FMC_SDTR1_TRC FMC_SDTR1_TRC_Msk /*!<TRC[2:0] bits (Row cycle delay) */
11393 #define FMC_SDTR1_TRC_0 (0x1U << FMC_SDTR1_TRC_Pos) /*!< 0x00001000 */
11394 #define FMC_SDTR1_TRC_1 (0x2U << FMC_SDTR1_TRC_Pos) /*!< 0x00002000 */
11395 #define FMC_SDTR1_TRC_2 (0x4U << FMC_SDTR1_TRC_Pos) /*!< 0x00004000 */
11396
11397 #define FMC_SDTR1_TWR_Pos (16U)
11398 #define FMC_SDTR1_TWR_Msk (0xFU << FMC_SDTR1_TWR_Pos) /*!< 0x000F0000 */
11399 #define FMC_SDTR1_TWR FMC_SDTR1_TWR_Msk /*!<TRC[2:0] bits (Write recovery delay) */
11400 #define FMC_SDTR1_TWR_0 (0x1U << FMC_SDTR1_TWR_Pos) /*!< 0x00010000 */
11401 #define FMC_SDTR1_TWR_1 (0x2U << FMC_SDTR1_TWR_Pos) /*!< 0x00020000 */
11402 #define FMC_SDTR1_TWR_2 (0x4U << FMC_SDTR1_TWR_Pos) /*!< 0x00040000 */
11403
11404 #define FMC_SDTR1_TRP_Pos (20U)
11405 #define FMC_SDTR1_TRP_Msk (0xFU << FMC_SDTR1_TRP_Pos) /*!< 0x00F00000 */
11406 #define FMC_SDTR1_TRP FMC_SDTR1_TRP_Msk /*!<TRP[2:0] bits (Row precharge delay) */
11407 #define FMC_SDTR1_TRP_0 (0x1U << FMC_SDTR1_TRP_Pos) /*!< 0x00100000 */
11408 #define FMC_SDTR1_TRP_1 (0x2U << FMC_SDTR1_TRP_Pos) /*!< 0x00200000 */
11409 #define FMC_SDTR1_TRP_2 (0x4U << FMC_SDTR1_TRP_Pos) /*!< 0x00400000 */
11410
11411 #define FMC_SDTR1_TRCD_Pos (24U)
11412 #define FMC_SDTR1_TRCD_Msk (0xFU << FMC_SDTR1_TRCD_Pos) /*!< 0x0F000000 */
11413 #define FMC_SDTR1_TRCD FMC_SDTR1_TRCD_Msk /*!<TRP[2:0] bits (Row to column delay) */
11414 #define FMC_SDTR1_TRCD_0 (0x1U << FMC_SDTR1_TRCD_Pos) /*!< 0x01000000 */
11415 #define FMC_SDTR1_TRCD_1 (0x2U << FMC_SDTR1_TRCD_Pos) /*!< 0x02000000 */
11416 #define FMC_SDTR1_TRCD_2 (0x4U << FMC_SDTR1_TRCD_Pos) /*!< 0x04000000 */
11417
11418 /****************** Bit definition for FMC_SDTR2 register ******************/
11419 #define FMC_SDTR2_TMRD_Pos (0U)
11420 #define FMC_SDTR2_TMRD_Msk (0xFU << FMC_SDTR2_TMRD_Pos) /*!< 0x0000000F */
11421 #define FMC_SDTR2_TMRD FMC_SDTR2_TMRD_Msk /*!<TMRD[3:0] bits (Load mode register to active) */
11422 #define FMC_SDTR2_TMRD_0 (0x1U << FMC_SDTR2_TMRD_Pos) /*!< 0x00000001 */
11423 #define FMC_SDTR2_TMRD_1 (0x2U << FMC_SDTR2_TMRD_Pos) /*!< 0x00000002 */
11424 #define FMC_SDTR2_TMRD_2 (0x4U << FMC_SDTR2_TMRD_Pos) /*!< 0x00000004 */
11425 #define FMC_SDTR2_TMRD_3 (0x8U << FMC_SDTR2_TMRD_Pos) /*!< 0x00000008 */
11426
11427 #define FMC_SDTR2_TXSR_Pos (4U)
11428 #define FMC_SDTR2_TXSR_Msk (0xFU << FMC_SDTR2_TXSR_Pos) /*!< 0x000000F0 */
11429 #define FMC_SDTR2_TXSR FMC_SDTR2_TXSR_Msk /*!<TXSR[3:0] bits (Exit self refresh) */
11430 #define FMC_SDTR2_TXSR_0 (0x1U << FMC_SDTR2_TXSR_Pos) /*!< 0x00000010 */
11431 #define FMC_SDTR2_TXSR_1 (0x2U << FMC_SDTR2_TXSR_Pos) /*!< 0x00000020 */
11432 #define FMC_SDTR2_TXSR_2 (0x4U << FMC_SDTR2_TXSR_Pos) /*!< 0x00000040 */
11433 #define FMC_SDTR2_TXSR_3 (0x8U << FMC_SDTR2_TXSR_Pos) /*!< 0x00000080 */
11434
11435 #define FMC_SDTR2_TRAS_Pos (8U)
11436 #define FMC_SDTR2_TRAS_Msk (0xFU << FMC_SDTR2_TRAS_Pos) /*!< 0x00000F00 */
11437 #define FMC_SDTR2_TRAS FMC_SDTR2_TRAS_Msk /*!<TRAS[3:0] bits (Self refresh time) */
11438 #define FMC_SDTR2_TRAS_0 (0x1U << FMC_SDTR2_TRAS_Pos) /*!< 0x00000100 */
11439 #define FMC_SDTR2_TRAS_1 (0x2U << FMC_SDTR2_TRAS_Pos) /*!< 0x00000200 */
11440 #define FMC_SDTR2_TRAS_2 (0x4U << FMC_SDTR2_TRAS_Pos) /*!< 0x00000400 */
11441 #define FMC_SDTR2_TRAS_3 (0x8U << FMC_SDTR2_TRAS_Pos) /*!< 0x00000800 */
11442
11443 #define FMC_SDTR2_TRC_Pos (12U)
11444 #define FMC_SDTR2_TRC_Msk (0xFU << FMC_SDTR2_TRC_Pos) /*!< 0x0000F000 */
11445 #define FMC_SDTR2_TRC FMC_SDTR2_TRC_Msk /*!<TRC[2:0] bits (Row cycle delay) */
11446 #define FMC_SDTR2_TRC_0 (0x1U << FMC_SDTR2_TRC_Pos) /*!< 0x00001000 */
11447 #define FMC_SDTR2_TRC_1 (0x2U << FMC_SDTR2_TRC_Pos) /*!< 0x00002000 */
11448 #define FMC_SDTR2_TRC_2 (0x4U << FMC_SDTR2_TRC_Pos) /*!< 0x00004000 */
11449
11450 #define FMC_SDTR2_TWR_Pos (16U)
11451 #define FMC_SDTR2_TWR_Msk (0xFU << FMC_SDTR2_TWR_Pos) /*!< 0x000F0000 */
11452 #define FMC_SDTR2_TWR FMC_SDTR2_TWR_Msk /*!<TRC[2:0] bits (Write recovery delay) */
11453 #define FMC_SDTR2_TWR_0 (0x1U << FMC_SDTR2_TWR_Pos) /*!< 0x00010000 */
11454 #define FMC_SDTR2_TWR_1 (0x2U << FMC_SDTR2_TWR_Pos) /*!< 0x00020000 */
11455 #define FMC_SDTR2_TWR_2 (0x4U << FMC_SDTR2_TWR_Pos) /*!< 0x00040000 */
11456
11457 #define FMC_SDTR2_TRP_Pos (20U)
11458 #define FMC_SDTR2_TRP_Msk (0xFU << FMC_SDTR2_TRP_Pos) /*!< 0x00F00000 */
11459 #define FMC_SDTR2_TRP FMC_SDTR2_TRP_Msk /*!<TRP[2:0] bits (Row precharge delay) */
11460 #define FMC_SDTR2_TRP_0 (0x1U << FMC_SDTR2_TRP_Pos) /*!< 0x00100000 */
11461 #define FMC_SDTR2_TRP_1 (0x2U << FMC_SDTR2_TRP_Pos) /*!< 0x00200000 */
11462 #define FMC_SDTR2_TRP_2 (0x4U << FMC_SDTR2_TRP_Pos) /*!< 0x00400000 */
11463
11464 #define FMC_SDTR2_TRCD_Pos (24U)
11465 #define FMC_SDTR2_TRCD_Msk (0xFU << FMC_SDTR2_TRCD_Pos) /*!< 0x0F000000 */
11466 #define FMC_SDTR2_TRCD FMC_SDTR2_TRCD_Msk /*!<TRP[2:0] bits (Row to column delay) */
11467 #define FMC_SDTR2_TRCD_0 (0x1U << FMC_SDTR2_TRCD_Pos) /*!< 0x01000000 */
11468 #define FMC_SDTR2_TRCD_1 (0x2U << FMC_SDTR2_TRCD_Pos) /*!< 0x02000000 */
11469 #define FMC_SDTR2_TRCD_2 (0x4U << FMC_SDTR2_TRCD_Pos) /*!< 0x04000000 */
11470
11471 /****************** Bit definition for FMC_SDCMR register ******************/
11472 #define FMC_SDCMR_MODE_Pos (0U)
11473 #define FMC_SDCMR_MODE_Msk (0x7U << FMC_SDCMR_MODE_Pos) /*!< 0x00000007 */
11474 #define FMC_SDCMR_MODE FMC_SDCMR_MODE_Msk /*!<MODE[2:0] bits (Command mode) */
11475 #define FMC_SDCMR_MODE_0 (0x1U << FMC_SDCMR_MODE_Pos) /*!< 0x00000001 */
11476 #define FMC_SDCMR_MODE_1 (0x2U << FMC_SDCMR_MODE_Pos) /*!< 0x00000002 */
11477 #define FMC_SDCMR_MODE_2 (0x4U << FMC_SDCMR_MODE_Pos) /*!< 0x00000004 */
11478
11479 #define FMC_SDCMR_CTB2_Pos (3U)
11480 #define FMC_SDCMR_CTB2_Msk (0x1U << FMC_SDCMR_CTB2_Pos) /*!< 0x00000008 */
11481 #define FMC_SDCMR_CTB2 FMC_SDCMR_CTB2_Msk /*!<Command target 2 */
11482
11483 #define FMC_SDCMR_CTB1_Pos (4U)
11484 #define FMC_SDCMR_CTB1_Msk (0x1U << FMC_SDCMR_CTB1_Pos) /*!< 0x00000010 */
11485 #define FMC_SDCMR_CTB1 FMC_SDCMR_CTB1_Msk /*!<Command target 1 */
11486
11487 #define FMC_SDCMR_NRFS_Pos (5U)
11488 #define FMC_SDCMR_NRFS_Msk (0xFU << FMC_SDCMR_NRFS_Pos) /*!< 0x000001E0 */
11489 #define FMC_SDCMR_NRFS FMC_SDCMR_NRFS_Msk /*!<NRFS[3:0] bits (Number of auto-refresh) */
11490 #define FMC_SDCMR_NRFS_0 (0x1U << FMC_SDCMR_NRFS_Pos) /*!< 0x00000020 */
11491 #define FMC_SDCMR_NRFS_1 (0x2U << FMC_SDCMR_NRFS_Pos) /*!< 0x00000040 */
11492 #define FMC_SDCMR_NRFS_2 (0x4U << FMC_SDCMR_NRFS_Pos) /*!< 0x00000080 */
11493 #define FMC_SDCMR_NRFS_3 (0x8U << FMC_SDCMR_NRFS_Pos) /*!< 0x00000100 */
11494
11495 #define FMC_SDCMR_MRD_Pos (9U)
11496 #define FMC_SDCMR_MRD_Msk (0x1FFFU << FMC_SDCMR_MRD_Pos) /*!< 0x003FFE00 */
11497 #define FMC_SDCMR_MRD FMC_SDCMR_MRD_Msk /*!<MRD[12:0] bits (Mode register definition) */
11498
11499 /****************** Bit definition for FMC_SDRTR register ******************/
11500 #define FMC_SDRTR_CRE_Pos (0U)
11501 #define FMC_SDRTR_CRE_Msk (0x1U << FMC_SDRTR_CRE_Pos) /*!< 0x00000001 */
11502 #define FMC_SDRTR_CRE FMC_SDRTR_CRE_Msk /*!<Clear refresh error flag */
11503
11504 #define FMC_SDRTR_COUNT_Pos (1U)
11505 #define FMC_SDRTR_COUNT_Msk (0x1FFFU << FMC_SDRTR_COUNT_Pos) /*!< 0x00003FFE */
11506 #define FMC_SDRTR_COUNT FMC_SDRTR_COUNT_Msk /*!<COUNT[12:0] bits (Refresh timer count) */
11507
11508 #define FMC_SDRTR_REIE_Pos (14U)
11509 #define FMC_SDRTR_REIE_Msk (0x1U << FMC_SDRTR_REIE_Pos) /*!< 0x00004000 */
11510 #define FMC_SDRTR_REIE FMC_SDRTR_REIE_Msk /*!<RES interupt enable */
11511
11512 /****************** Bit definition for FMC_SDSR register ******************/
11513 #define FMC_SDSR_RE_Pos (0U)
11514 #define FMC_SDSR_RE_Msk (0x1U << FMC_SDSR_RE_Pos) /*!< 0x00000001 */
11515 #define FMC_SDSR_RE FMC_SDSR_RE_Msk /*!<Refresh error flag */
11516
11517 #define FMC_SDSR_MODES1_Pos (1U)
11518 #define FMC_SDSR_MODES1_Msk (0x3U << FMC_SDSR_MODES1_Pos) /*!< 0x00000006 */
11519 #define FMC_SDSR_MODES1 FMC_SDSR_MODES1_Msk /*!<MODES1[1:0]bits (Status mode for bank 1) */
11520 #define FMC_SDSR_MODES1_0 (0x1U << FMC_SDSR_MODES1_Pos) /*!< 0x00000002 */
11521 #define FMC_SDSR_MODES1_1 (0x2U << FMC_SDSR_MODES1_Pos) /*!< 0x00000004 */
11522
11523 #define FMC_SDSR_MODES2_Pos (3U)
11524 #define FMC_SDSR_MODES2_Msk (0x3U << FMC_SDSR_MODES2_Pos) /*!< 0x00000018 */
11525 #define FMC_SDSR_MODES2 FMC_SDSR_MODES2_Msk /*!<MODES2[1:0]bits (Status mode for bank 2) */
11526 #define FMC_SDSR_MODES2_0 (0x1U << FMC_SDSR_MODES2_Pos) /*!< 0x00000008 */
11527 #define FMC_SDSR_MODES2_1 (0x2U << FMC_SDSR_MODES2_Pos) /*!< 0x00000010 */
11528 #define FMC_SDSR_BUSY_Pos (5U)
11529 #define FMC_SDSR_BUSY_Msk (0x1U << FMC_SDSR_BUSY_Pos) /*!< 0x00000020 */
11530 #define FMC_SDSR_BUSY FMC_SDSR_BUSY_Msk /*!<Busy status */
11531
11532 /******************************************************************************/
11533 /* */
11534 /* General Purpose I/O */
11535 /* */
11536 /******************************************************************************/
11537 /****************** Bits definition for GPIO_MODER register *****************/
11538 #define GPIO_MODER_MODE0_Pos (0U)
11539 #define GPIO_MODER_MODE0_Msk (0x3U << GPIO_MODER_MODE0_Pos) /*!< 0x00000003 */
11540 #define GPIO_MODER_MODE0 GPIO_MODER_MODE0_Msk
11541 #define GPIO_MODER_MODE0_0 (0x1U << GPIO_MODER_MODE0_Pos) /*!< 0x00000001 */
11542 #define GPIO_MODER_MODE0_1 (0x2U << GPIO_MODER_MODE0_Pos) /*!< 0x00000002 */
11543 #define GPIO_MODER_MODE1_Pos (2U)
11544 #define GPIO_MODER_MODE1_Msk (0x3U << GPIO_MODER_MODE1_Pos) /*!< 0x0000000C */
11545 #define GPIO_MODER_MODE1 GPIO_MODER_MODE1_Msk
11546 #define GPIO_MODER_MODE1_0 (0x1U << GPIO_MODER_MODE1_Pos) /*!< 0x00000004 */
11547 #define GPIO_MODER_MODE1_1 (0x2U << GPIO_MODER_MODE1_Pos) /*!< 0x00000008 */
11548 #define GPIO_MODER_MODE2_Pos (4U)
11549 #define GPIO_MODER_MODE2_Msk (0x3U << GPIO_MODER_MODE2_Pos) /*!< 0x00000030 */
11550 #define GPIO_MODER_MODE2 GPIO_MODER_MODE2_Msk
11551 #define GPIO_MODER_MODE2_0 (0x1U << GPIO_MODER_MODE2_Pos) /*!< 0x00000010 */
11552 #define GPIO_MODER_MODE2_1 (0x2U << GPIO_MODER_MODE2_Pos) /*!< 0x00000020 */
11553 #define GPIO_MODER_MODE3_Pos (6U)
11554 #define GPIO_MODER_MODE3_Msk (0x3U << GPIO_MODER_MODE3_Pos) /*!< 0x000000C0 */
11555 #define GPIO_MODER_MODE3 GPIO_MODER_MODE3_Msk
11556 #define GPIO_MODER_MODE3_0 (0x1U << GPIO_MODER_MODE3_Pos) /*!< 0x00000040 */
11557 #define GPIO_MODER_MODE3_1 (0x2U << GPIO_MODER_MODE3_Pos) /*!< 0x00000080 */
11558 #define GPIO_MODER_MODE4_Pos (8U)
11559 #define GPIO_MODER_MODE4_Msk (0x3U << GPIO_MODER_MODE4_Pos) /*!< 0x00000300 */
11560 #define GPIO_MODER_MODE4 GPIO_MODER_MODE4_Msk
11561 #define GPIO_MODER_MODE4_0 (0x1U << GPIO_MODER_MODE4_Pos) /*!< 0x00000100 */
11562 #define GPIO_MODER_MODE4_1 (0x2U << GPIO_MODER_MODE4_Pos) /*!< 0x00000200 */
11563 #define GPIO_MODER_MODE5_Pos (10U)
11564 #define GPIO_MODER_MODE5_Msk (0x3U << GPIO_MODER_MODE5_Pos) /*!< 0x00000C00 */
11565 #define GPIO_MODER_MODE5 GPIO_MODER_MODE5_Msk
11566 #define GPIO_MODER_MODE5_0 (0x1U << GPIO_MODER_MODE5_Pos) /*!< 0x00000400 */
11567 #define GPIO_MODER_MODE5_1 (0x2U << GPIO_MODER_MODE5_Pos) /*!< 0x00000800 */
11568 #define GPIO_MODER_MODE6_Pos (12U)
11569 #define GPIO_MODER_MODE6_Msk (0x3U << GPIO_MODER_MODE6_Pos) /*!< 0x00003000 */
11570 #define GPIO_MODER_MODE6 GPIO_MODER_MODE6_Msk
11571 #define GPIO_MODER_MODE6_0 (0x1U << GPIO_MODER_MODE6_Pos) /*!< 0x00001000 */
11572 #define GPIO_MODER_MODE6_1 (0x2U << GPIO_MODER_MODE6_Pos) /*!< 0x00002000 */
11573 #define GPIO_MODER_MODE7_Pos (14U)
11574 #define GPIO_MODER_MODE7_Msk (0x3U << GPIO_MODER_MODE7_Pos) /*!< 0x0000C000 */
11575 #define GPIO_MODER_MODE7 GPIO_MODER_MODE7_Msk
11576 #define GPIO_MODER_MODE7_0 (0x1U << GPIO_MODER_MODE7_Pos) /*!< 0x00004000 */
11577 #define GPIO_MODER_MODE7_1 (0x2U << GPIO_MODER_MODE7_Pos) /*!< 0x00008000 */
11578 #define GPIO_MODER_MODE8_Pos (16U)
11579 #define GPIO_MODER_MODE8_Msk (0x3U << GPIO_MODER_MODE8_Pos) /*!< 0x00030000 */
11580 #define GPIO_MODER_MODE8 GPIO_MODER_MODE8_Msk
11581 #define GPIO_MODER_MODE8_0 (0x1U << GPIO_MODER_MODE8_Pos) /*!< 0x00010000 */
11582 #define GPIO_MODER_MODE8_1 (0x2U << GPIO_MODER_MODE8_Pos) /*!< 0x00020000 */
11583 #define GPIO_MODER_MODE9_Pos (18U)
11584 #define GPIO_MODER_MODE9_Msk (0x3U << GPIO_MODER_MODE9_Pos) /*!< 0x000C0000 */
11585 #define GPIO_MODER_MODE9 GPIO_MODER_MODE9_Msk
11586 #define GPIO_MODER_MODE9_0 (0x1U << GPIO_MODER_MODE9_Pos) /*!< 0x00040000 */
11587 #define GPIO_MODER_MODE9_1 (0x2U << GPIO_MODER_MODE9_Pos) /*!< 0x00080000 */
11588 #define GPIO_MODER_MODE10_Pos (20U)
11589 #define GPIO_MODER_MODE10_Msk (0x3U << GPIO_MODER_MODE10_Pos) /*!< 0x00300000 */
11590 #define GPIO_MODER_MODE10 GPIO_MODER_MODE10_Msk
11591 #define GPIO_MODER_MODE10_0 (0x1U << GPIO_MODER_MODE10_Pos) /*!< 0x00100000 */
11592 #define GPIO_MODER_MODE10_1 (0x2U << GPIO_MODER_MODE10_Pos) /*!< 0x00200000 */
11593 #define GPIO_MODER_MODE11_Pos (22U)
11594 #define GPIO_MODER_MODE11_Msk (0x3U << GPIO_MODER_MODE11_Pos) /*!< 0x00C00000 */
11595 #define GPIO_MODER_MODE11 GPIO_MODER_MODE11_Msk
11596 #define GPIO_MODER_MODE11_0 (0x1U << GPIO_MODER_MODE11_Pos) /*!< 0x00400000 */
11597 #define GPIO_MODER_MODE11_1 (0x2U << GPIO_MODER_MODE11_Pos) /*!< 0x00800000 */
11598 #define GPIO_MODER_MODE12_Pos (24U)
11599 #define GPIO_MODER_MODE12_Msk (0x3U << GPIO_MODER_MODE12_Pos) /*!< 0x03000000 */
11600 #define GPIO_MODER_MODE12 GPIO_MODER_MODE12_Msk
11601 #define GPIO_MODER_MODE12_0 (0x1U << GPIO_MODER_MODE12_Pos) /*!< 0x01000000 */
11602 #define GPIO_MODER_MODE12_1 (0x2U << GPIO_MODER_MODE12_Pos) /*!< 0x02000000 */
11603 #define GPIO_MODER_MODE13_Pos (26U)
11604 #define GPIO_MODER_MODE13_Msk (0x3U << GPIO_MODER_MODE13_Pos) /*!< 0x0C000000 */
11605 #define GPIO_MODER_MODE13 GPIO_MODER_MODE13_Msk
11606 #define GPIO_MODER_MODE13_0 (0x1U << GPIO_MODER_MODE13_Pos) /*!< 0x04000000 */
11607 #define GPIO_MODER_MODE13_1 (0x2U << GPIO_MODER_MODE13_Pos) /*!< 0x08000000 */
11608 #define GPIO_MODER_MODE14_Pos (28U)
11609 #define GPIO_MODER_MODE14_Msk (0x3U << GPIO_MODER_MODE14_Pos) /*!< 0x30000000 */
11610 #define GPIO_MODER_MODE14 GPIO_MODER_MODE14_Msk
11611 #define GPIO_MODER_MODE14_0 (0x1U << GPIO_MODER_MODE14_Pos) /*!< 0x10000000 */
11612 #define GPIO_MODER_MODE14_1 (0x2U << GPIO_MODER_MODE14_Pos) /*!< 0x20000000 */
11613 #define GPIO_MODER_MODE15_Pos (30U)
11614 #define GPIO_MODER_MODE15_Msk (0x3U << GPIO_MODER_MODE15_Pos) /*!< 0xC0000000 */
11615 #define GPIO_MODER_MODE15 GPIO_MODER_MODE15_Msk
11616 #define GPIO_MODER_MODE15_0 (0x1U << GPIO_MODER_MODE15_Pos) /*!< 0x40000000 */
11617 #define GPIO_MODER_MODE15_1 (0x2U << GPIO_MODER_MODE15_Pos) /*!< 0x80000000 */
11618
11619 /* Legacy defines */
11620 #define GPIO_MODER_MODER0_Pos (0U)
11621 #define GPIO_MODER_MODER0_Msk (0x3U << GPIO_MODER_MODER0_Pos) /*!< 0x00000003 */
11622 #define GPIO_MODER_MODER0 GPIO_MODER_MODER0_Msk
11623 #define GPIO_MODER_MODER0_0 (0x1U << GPIO_MODER_MODER0_Pos) /*!< 0x00000001 */
11624 #define GPIO_MODER_MODER0_1 (0x2U << GPIO_MODER_MODER0_Pos) /*!< 0x00000002 */
11625 #define GPIO_MODER_MODER1_Pos (2U)
11626 #define GPIO_MODER_MODER1_Msk (0x3U << GPIO_MODER_MODER1_Pos) /*!< 0x0000000C */
11627 #define GPIO_MODER_MODER1 GPIO_MODER_MODER1_Msk
11628 #define GPIO_MODER_MODER1_0 (0x1U << GPIO_MODER_MODER1_Pos) /*!< 0x00000004 */
11629 #define GPIO_MODER_MODER1_1 (0x2U << GPIO_MODER_MODER1_Pos) /*!< 0x00000008 */
11630 #define GPIO_MODER_MODER2_Pos (4U)
11631 #define GPIO_MODER_MODER2_Msk (0x3U << GPIO_MODER_MODER2_Pos) /*!< 0x00000030 */
11632 #define GPIO_MODER_MODER2 GPIO_MODER_MODER2_Msk
11633 #define GPIO_MODER_MODER2_0 (0x1U << GPIO_MODER_MODER2_Pos) /*!< 0x00000010 */
11634 #define GPIO_MODER_MODER2_1 (0x2U << GPIO_MODER_MODER2_Pos) /*!< 0x00000020 */
11635 #define GPIO_MODER_MODER3_Pos (6U)
11636 #define GPIO_MODER_MODER3_Msk (0x3U << GPIO_MODER_MODER3_Pos) /*!< 0x000000C0 */
11637 #define GPIO_MODER_MODER3 GPIO_MODER_MODER3_Msk
11638 #define GPIO_MODER_MODER3_0 (0x1U << GPIO_MODER_MODER3_Pos) /*!< 0x00000040 */
11639 #define GPIO_MODER_MODER3_1 (0x2U << GPIO_MODER_MODER3_Pos) /*!< 0x00000080 */
11640 #define GPIO_MODER_MODER4_Pos (8U)
11641 #define GPIO_MODER_MODER4_Msk (0x3U << GPIO_MODER_MODER4_Pos) /*!< 0x00000300 */
11642 #define GPIO_MODER_MODER4 GPIO_MODER_MODER4_Msk
11643 #define GPIO_MODER_MODER4_0 (0x1U << GPIO_MODER_MODER4_Pos) /*!< 0x00000100 */
11644 #define GPIO_MODER_MODER4_1 (0x2U << GPIO_MODER_MODER4_Pos) /*!< 0x00000200 */
11645 #define GPIO_MODER_MODER5_Pos (10U)
11646 #define GPIO_MODER_MODER5_Msk (0x3U << GPIO_MODER_MODER5_Pos) /*!< 0x00000C00 */
11647 #define GPIO_MODER_MODER5 GPIO_MODER_MODER5_Msk
11648 #define GPIO_MODER_MODER5_0 (0x1U << GPIO_MODER_MODER5_Pos) /*!< 0x00000400 */
11649 #define GPIO_MODER_MODER5_1 (0x2U << GPIO_MODER_MODER5_Pos) /*!< 0x00000800 */
11650 #define GPIO_MODER_MODER6_Pos (12U)
11651 #define GPIO_MODER_MODER6_Msk (0x3U << GPIO_MODER_MODER6_Pos) /*!< 0x00003000 */
11652 #define GPIO_MODER_MODER6 GPIO_MODER_MODER6_Msk
11653 #define GPIO_MODER_MODER6_0 (0x1U << GPIO_MODER_MODER6_Pos) /*!< 0x00001000 */
11654 #define GPIO_MODER_MODER6_1 (0x2U << GPIO_MODER_MODER6_Pos) /*!< 0x00002000 */
11655 #define GPIO_MODER_MODER7_Pos (14U)
11656 #define GPIO_MODER_MODER7_Msk (0x3U << GPIO_MODER_MODER7_Pos) /*!< 0x0000C000 */
11657 #define GPIO_MODER_MODER7 GPIO_MODER_MODER7_Msk
11658 #define GPIO_MODER_MODER7_0 (0x1U << GPIO_MODER_MODER7_Pos) /*!< 0x00004000 */
11659 #define GPIO_MODER_MODER7_1 (0x2U << GPIO_MODER_MODER7_Pos) /*!< 0x00008000 */
11660 #define GPIO_MODER_MODER8_Pos (16U)
11661 #define GPIO_MODER_MODER8_Msk (0x3U << GPIO_MODER_MODER8_Pos) /*!< 0x00030000 */
11662 #define GPIO_MODER_MODER8 GPIO_MODER_MODER8_Msk
11663 #define GPIO_MODER_MODER8_0 (0x1U << GPIO_MODER_MODER8_Pos) /*!< 0x00010000 */
11664 #define GPIO_MODER_MODER8_1 (0x2U << GPIO_MODER_MODER8_Pos) /*!< 0x00020000 */
11665 #define GPIO_MODER_MODER9_Pos (18U)
11666 #define GPIO_MODER_MODER9_Msk (0x3U << GPIO_MODER_MODER9_Pos) /*!< 0x000C0000 */
11667 #define GPIO_MODER_MODER9 GPIO_MODER_MODER9_Msk
11668 #define GPIO_MODER_MODER9_0 (0x1U << GPIO_MODER_MODER9_Pos) /*!< 0x00040000 */
11669 #define GPIO_MODER_MODER9_1 (0x2U << GPIO_MODER_MODER9_Pos) /*!< 0x00080000 */
11670 #define GPIO_MODER_MODER10_Pos (20U)
11671 #define GPIO_MODER_MODER10_Msk (0x3U << GPIO_MODER_MODER10_Pos) /*!< 0x00300000 */
11672 #define GPIO_MODER_MODER10 GPIO_MODER_MODER10_Msk
11673 #define GPIO_MODER_MODER10_0 (0x1U << GPIO_MODER_MODER10_Pos) /*!< 0x00100000 */
11674 #define GPIO_MODER_MODER10_1 (0x2U << GPIO_MODER_MODER10_Pos) /*!< 0x00200000 */
11675 #define GPIO_MODER_MODER11_Pos (22U)
11676 #define GPIO_MODER_MODER11_Msk (0x3U << GPIO_MODER_MODER11_Pos) /*!< 0x00C00000 */
11677 #define GPIO_MODER_MODER11 GPIO_MODER_MODER11_Msk
11678 #define GPIO_MODER_MODER11_0 (0x1U << GPIO_MODER_MODER11_Pos) /*!< 0x00400000 */
11679 #define GPIO_MODER_MODER11_1 (0x2U << GPIO_MODER_MODER11_Pos) /*!< 0x00800000 */
11680 #define GPIO_MODER_MODER12_Pos (24U)
11681 #define GPIO_MODER_MODER12_Msk (0x3U << GPIO_MODER_MODER12_Pos) /*!< 0x03000000 */
11682 #define GPIO_MODER_MODER12 GPIO_MODER_MODER12_Msk
11683 #define GPIO_MODER_MODER12_0 (0x1U << GPIO_MODER_MODER12_Pos) /*!< 0x01000000 */
11684 #define GPIO_MODER_MODER12_1 (0x2U << GPIO_MODER_MODER12_Pos) /*!< 0x02000000 */
11685 #define GPIO_MODER_MODER13_Pos (26U)
11686 #define GPIO_MODER_MODER13_Msk (0x3U << GPIO_MODER_MODER13_Pos) /*!< 0x0C000000 */
11687 #define GPIO_MODER_MODER13 GPIO_MODER_MODER13_Msk
11688 #define GPIO_MODER_MODER13_0 (0x1U << GPIO_MODER_MODER13_Pos) /*!< 0x04000000 */
11689 #define GPIO_MODER_MODER13_1 (0x2U << GPIO_MODER_MODER13_Pos) /*!< 0x08000000 */
11690 #define GPIO_MODER_MODER14_Pos (28U)
11691 #define GPIO_MODER_MODER14_Msk (0x3U << GPIO_MODER_MODER14_Pos) /*!< 0x30000000 */
11692 #define GPIO_MODER_MODER14 GPIO_MODER_MODER14_Msk
11693 #define GPIO_MODER_MODER14_0 (0x1U << GPIO_MODER_MODER14_Pos) /*!< 0x10000000 */
11694 #define GPIO_MODER_MODER14_1 (0x2U << GPIO_MODER_MODER14_Pos) /*!< 0x20000000 */
11695 #define GPIO_MODER_MODER15_Pos (30U)
11696 #define GPIO_MODER_MODER15_Msk (0x3U << GPIO_MODER_MODER15_Pos) /*!< 0xC0000000 */
11697 #define GPIO_MODER_MODER15 GPIO_MODER_MODER15_Msk
11698 #define GPIO_MODER_MODER15_0 (0x1U << GPIO_MODER_MODER15_Pos) /*!< 0x40000000 */
11699 #define GPIO_MODER_MODER15_1 (0x2U << GPIO_MODER_MODER15_Pos) /*!< 0x80000000 */
11700
11701 /****************** Bits definition for GPIO_OTYPER register ****************/
11702 #define GPIO_OTYPER_OT0_Pos (0U)
11703 #define GPIO_OTYPER_OT0_Msk (0x1U << GPIO_OTYPER_OT0_Pos) /*!< 0x00000001 */
11704 #define GPIO_OTYPER_OT0 GPIO_OTYPER_OT0_Msk
11705 #define GPIO_OTYPER_OT1_Pos (1U)
11706 #define GPIO_OTYPER_OT1_Msk (0x1U << GPIO_OTYPER_OT1_Pos) /*!< 0x00000002 */
11707 #define GPIO_OTYPER_OT1 GPIO_OTYPER_OT1_Msk
11708 #define GPIO_OTYPER_OT2_Pos (2U)
11709 #define GPIO_OTYPER_OT2_Msk (0x1U << GPIO_OTYPER_OT2_Pos) /*!< 0x00000004 */
11710 #define GPIO_OTYPER_OT2 GPIO_OTYPER_OT2_Msk
11711 #define GPIO_OTYPER_OT3_Pos (3U)
11712 #define GPIO_OTYPER_OT3_Msk (0x1U << GPIO_OTYPER_OT3_Pos) /*!< 0x00000008 */
11713 #define GPIO_OTYPER_OT3 GPIO_OTYPER_OT3_Msk
11714 #define GPIO_OTYPER_OT4_Pos (4U)
11715 #define GPIO_OTYPER_OT4_Msk (0x1U << GPIO_OTYPER_OT4_Pos) /*!< 0x00000010 */
11716 #define GPIO_OTYPER_OT4 GPIO_OTYPER_OT4_Msk
11717 #define GPIO_OTYPER_OT5_Pos (5U)
11718 #define GPIO_OTYPER_OT5_Msk (0x1U << GPIO_OTYPER_OT5_Pos) /*!< 0x00000020 */
11719 #define GPIO_OTYPER_OT5 GPIO_OTYPER_OT5_Msk
11720 #define GPIO_OTYPER_OT6_Pos (6U)
11721 #define GPIO_OTYPER_OT6_Msk (0x1U << GPIO_OTYPER_OT6_Pos) /*!< 0x00000040 */
11722 #define GPIO_OTYPER_OT6 GPIO_OTYPER_OT6_Msk
11723 #define GPIO_OTYPER_OT7_Pos (7U)
11724 #define GPIO_OTYPER_OT7_Msk (0x1U << GPIO_OTYPER_OT7_Pos) /*!< 0x00000080 */
11725 #define GPIO_OTYPER_OT7 GPIO_OTYPER_OT7_Msk
11726 #define GPIO_OTYPER_OT8_Pos (8U)
11727 #define GPIO_OTYPER_OT8_Msk (0x1U << GPIO_OTYPER_OT8_Pos) /*!< 0x00000100 */
11728 #define GPIO_OTYPER_OT8 GPIO_OTYPER_OT8_Msk
11729 #define GPIO_OTYPER_OT9_Pos (9U)
11730 #define GPIO_OTYPER_OT9_Msk (0x1U << GPIO_OTYPER_OT9_Pos) /*!< 0x00000200 */
11731 #define GPIO_OTYPER_OT9 GPIO_OTYPER_OT9_Msk
11732 #define GPIO_OTYPER_OT10_Pos (10U)
11733 #define GPIO_OTYPER_OT10_Msk (0x1U << GPIO_OTYPER_OT10_Pos) /*!< 0x00000400 */
11734 #define GPIO_OTYPER_OT10 GPIO_OTYPER_OT10_Msk
11735 #define GPIO_OTYPER_OT11_Pos (11U)
11736 #define GPIO_OTYPER_OT11_Msk (0x1U << GPIO_OTYPER_OT11_Pos) /*!< 0x00000800 */
11737 #define GPIO_OTYPER_OT11 GPIO_OTYPER_OT11_Msk
11738 #define GPIO_OTYPER_OT12_Pos (12U)
11739 #define GPIO_OTYPER_OT12_Msk (0x1U << GPIO_OTYPER_OT12_Pos) /*!< 0x00001000 */
11740 #define GPIO_OTYPER_OT12 GPIO_OTYPER_OT12_Msk
11741 #define GPIO_OTYPER_OT13_Pos (13U)
11742 #define GPIO_OTYPER_OT13_Msk (0x1U << GPIO_OTYPER_OT13_Pos) /*!< 0x00002000 */
11743 #define GPIO_OTYPER_OT13 GPIO_OTYPER_OT13_Msk
11744 #define GPIO_OTYPER_OT14_Pos (14U)
11745 #define GPIO_OTYPER_OT14_Msk (0x1U << GPIO_OTYPER_OT14_Pos) /*!< 0x00004000 */
11746 #define GPIO_OTYPER_OT14 GPIO_OTYPER_OT14_Msk
11747 #define GPIO_OTYPER_OT15_Pos (15U)
11748 #define GPIO_OTYPER_OT15_Msk (0x1U << GPIO_OTYPER_OT15_Pos) /*!< 0x00008000 */
11749 #define GPIO_OTYPER_OT15 GPIO_OTYPER_OT15_Msk
11750
11751 /* Legacy defines */
11752 #define GPIO_OTYPER_OT_0 GPIO_OTYPER_OT0
11753 #define GPIO_OTYPER_OT_1 GPIO_OTYPER_OT1
11754 #define GPIO_OTYPER_OT_2 GPIO_OTYPER_OT2
11755 #define GPIO_OTYPER_OT_3 GPIO_OTYPER_OT3
11756 #define GPIO_OTYPER_OT_4 GPIO_OTYPER_OT4
11757 #define GPIO_OTYPER_OT_5 GPIO_OTYPER_OT5
11758 #define GPIO_OTYPER_OT_6 GPIO_OTYPER_OT6
11759 #define GPIO_OTYPER_OT_7 GPIO_OTYPER_OT7
11760 #define GPIO_OTYPER_OT_8 GPIO_OTYPER_OT8
11761 #define GPIO_OTYPER_OT_9 GPIO_OTYPER_OT9
11762 #define GPIO_OTYPER_OT_10 GPIO_OTYPER_OT10
11763 #define GPIO_OTYPER_OT_11 GPIO_OTYPER_OT11
11764 #define GPIO_OTYPER_OT_12 GPIO_OTYPER_OT12
11765 #define GPIO_OTYPER_OT_13 GPIO_OTYPER_OT13
11766 #define GPIO_OTYPER_OT_14 GPIO_OTYPER_OT14
11767 #define GPIO_OTYPER_OT_15 GPIO_OTYPER_OT15
11768
11769 /****************** Bits definition for GPIO_OSPEEDR register ***************/
11770 #define GPIO_OSPEEDR_OSPEED0_Pos (0U)
11771 #define GPIO_OSPEEDR_OSPEED0_Msk (0x3U << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000003 */
11772 #define GPIO_OSPEEDR_OSPEED0 GPIO_OSPEEDR_OSPEED0_Msk
11773 #define GPIO_OSPEEDR_OSPEED0_0 (0x1U << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000001 */
11774 #define GPIO_OSPEEDR_OSPEED0_1 (0x2U << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000002 */
11775 #define GPIO_OSPEEDR_OSPEED1_Pos (2U)
11776 #define GPIO_OSPEEDR_OSPEED1_Msk (0x3U << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x0000000C */
11777 #define GPIO_OSPEEDR_OSPEED1 GPIO_OSPEEDR_OSPEED1_Msk
11778 #define GPIO_OSPEEDR_OSPEED1_0 (0x1U << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x00000004 */
11779 #define GPIO_OSPEEDR_OSPEED1_1 (0x2U << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x00000008 */
11780 #define GPIO_OSPEEDR_OSPEED2_Pos (4U)
11781 #define GPIO_OSPEEDR_OSPEED2_Msk (0x3U << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000030 */
11782 #define GPIO_OSPEEDR_OSPEED2 GPIO_OSPEEDR_OSPEED2_Msk
11783 #define GPIO_OSPEEDR_OSPEED2_0 (0x1U << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000010 */
11784 #define GPIO_OSPEEDR_OSPEED2_1 (0x2U << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000020 */
11785 #define GPIO_OSPEEDR_OSPEED3_Pos (6U)
11786 #define GPIO_OSPEEDR_OSPEED3_Msk (0x3U << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x000000C0 */
11787 #define GPIO_OSPEEDR_OSPEED3 GPIO_OSPEEDR_OSPEED3_Msk
11788 #define GPIO_OSPEEDR_OSPEED3_0 (0x1U << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x00000040 */
11789 #define GPIO_OSPEEDR_OSPEED3_1 (0x2U << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x00000080 */
11790 #define GPIO_OSPEEDR_OSPEED4_Pos (8U)
11791 #define GPIO_OSPEEDR_OSPEED4_Msk (0x3U << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000300 */
11792 #define GPIO_OSPEEDR_OSPEED4 GPIO_OSPEEDR_OSPEED4_Msk
11793 #define GPIO_OSPEEDR_OSPEED4_0 (0x1U << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000100 */
11794 #define GPIO_OSPEEDR_OSPEED4_1 (0x2U << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000200 */
11795 #define GPIO_OSPEEDR_OSPEED5_Pos (10U)
11796 #define GPIO_OSPEEDR_OSPEED5_Msk (0x3U << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000C00 */
11797 #define GPIO_OSPEEDR_OSPEED5 GPIO_OSPEEDR_OSPEED5_Msk
11798 #define GPIO_OSPEEDR_OSPEED5_0 (0x1U << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000400 */
11799 #define GPIO_OSPEEDR_OSPEED5_1 (0x2U << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000800 */
11800 #define GPIO_OSPEEDR_OSPEED6_Pos (12U)
11801 #define GPIO_OSPEEDR_OSPEED6_Msk (0x3U << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00003000 */
11802 #define GPIO_OSPEEDR_OSPEED6 GPIO_OSPEEDR_OSPEED6_Msk
11803 #define GPIO_OSPEEDR_OSPEED6_0 (0x1U << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00001000 */
11804 #define GPIO_OSPEEDR_OSPEED6_1 (0x2U << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00002000 */
11805 #define GPIO_OSPEEDR_OSPEED7_Pos (14U)
11806 #define GPIO_OSPEEDR_OSPEED7_Msk (0x3U << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x0000C000 */
11807 #define GPIO_OSPEEDR_OSPEED7 GPIO_OSPEEDR_OSPEED7_Msk
11808 #define GPIO_OSPEEDR_OSPEED7_0 (0x1U << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x00004000 */
11809 #define GPIO_OSPEEDR_OSPEED7_1 (0x2U << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x00008000 */
11810 #define GPIO_OSPEEDR_OSPEED8_Pos (16U)
11811 #define GPIO_OSPEEDR_OSPEED8_Msk (0x3U << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00030000 */
11812 #define GPIO_OSPEEDR_OSPEED8 GPIO_OSPEEDR_OSPEED8_Msk
11813 #define GPIO_OSPEEDR_OSPEED8_0 (0x1U << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00010000 */
11814 #define GPIO_OSPEEDR_OSPEED8_1 (0x2U << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00020000 */
11815 #define GPIO_OSPEEDR_OSPEED9_Pos (18U)
11816 #define GPIO_OSPEEDR_OSPEED9_Msk (0x3U << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x000C0000 */
11817 #define GPIO_OSPEEDR_OSPEED9 GPIO_OSPEEDR_OSPEED9_Msk
11818 #define GPIO_OSPEEDR_OSPEED9_0 (0x1U << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x00040000 */
11819 #define GPIO_OSPEEDR_OSPEED9_1 (0x2U << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x00080000 */
11820 #define GPIO_OSPEEDR_OSPEED10_Pos (20U)
11821 #define GPIO_OSPEEDR_OSPEED10_Msk (0x3U << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00300000 */
11822 #define GPIO_OSPEEDR_OSPEED10 GPIO_OSPEEDR_OSPEED10_Msk
11823 #define GPIO_OSPEEDR_OSPEED10_0 (0x1U << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00100000 */
11824 #define GPIO_OSPEEDR_OSPEED10_1 (0x2U << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00200000 */
11825 #define GPIO_OSPEEDR_OSPEED11_Pos (22U)
11826 #define GPIO_OSPEEDR_OSPEED11_Msk (0x3U << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00C00000 */
11827 #define GPIO_OSPEEDR_OSPEED11 GPIO_OSPEEDR_OSPEED11_Msk
11828 #define GPIO_OSPEEDR_OSPEED11_0 (0x1U << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00400000 */
11829 #define GPIO_OSPEEDR_OSPEED11_1 (0x2U << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00800000 */
11830 #define GPIO_OSPEEDR_OSPEED12_Pos (24U)
11831 #define GPIO_OSPEEDR_OSPEED12_Msk (0x3U << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x03000000 */
11832 #define GPIO_OSPEEDR_OSPEED12 GPIO_OSPEEDR_OSPEED12_Msk
11833 #define GPIO_OSPEEDR_OSPEED12_0 (0x1U << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x01000000 */
11834 #define GPIO_OSPEEDR_OSPEED12_1 (0x2U << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x02000000 */
11835 #define GPIO_OSPEEDR_OSPEED13_Pos (26U)
11836 #define GPIO_OSPEEDR_OSPEED13_Msk (0x3U << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x0C000000 */
11837 #define GPIO_OSPEEDR_OSPEED13 GPIO_OSPEEDR_OSPEED13_Msk
11838 #define GPIO_OSPEEDR_OSPEED13_0 (0x1U << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x04000000 */
11839 #define GPIO_OSPEEDR_OSPEED13_1 (0x2U << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x08000000 */
11840 #define GPIO_OSPEEDR_OSPEED14_Pos (28U)
11841 #define GPIO_OSPEEDR_OSPEED14_Msk (0x3U << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x30000000 */
11842 #define GPIO_OSPEEDR_OSPEED14 GPIO_OSPEEDR_OSPEED14_Msk
11843 #define GPIO_OSPEEDR_OSPEED14_0 (0x1U << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x10000000 */
11844 #define GPIO_OSPEEDR_OSPEED14_1 (0x2U << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x20000000 */
11845 #define GPIO_OSPEEDR_OSPEED15_Pos (30U)
11846 #define GPIO_OSPEEDR_OSPEED15_Msk (0x3U << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0xC0000000 */
11847 #define GPIO_OSPEEDR_OSPEED15 GPIO_OSPEEDR_OSPEED15_Msk
11848 #define GPIO_OSPEEDR_OSPEED15_0 (0x1U << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0x40000000 */
11849 #define GPIO_OSPEEDR_OSPEED15_1 (0x2U << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0x80000000 */
11850
11851 /* Legacy defines */
11852 #define GPIO_OSPEEDER_OSPEEDR0 GPIO_OSPEEDR_OSPEED0
11853 #define GPIO_OSPEEDER_OSPEEDR0_0 GPIO_OSPEEDR_OSPEED0_0
11854 #define GPIO_OSPEEDER_OSPEEDR0_1 GPIO_OSPEEDR_OSPEED0_1
11855 #define GPIO_OSPEEDER_OSPEEDR1 GPIO_OSPEEDR_OSPEED1
11856 #define GPIO_OSPEEDER_OSPEEDR1_0 GPIO_OSPEEDR_OSPEED1_0
11857 #define GPIO_OSPEEDER_OSPEEDR1_1 GPIO_OSPEEDR_OSPEED1_1
11858 #define GPIO_OSPEEDER_OSPEEDR2 GPIO_OSPEEDR_OSPEED2
11859 #define GPIO_OSPEEDER_OSPEEDR2_0 GPIO_OSPEEDR_OSPEED2_0
11860 #define GPIO_OSPEEDER_OSPEEDR2_1 GPIO_OSPEEDR_OSPEED2_1
11861 #define GPIO_OSPEEDER_OSPEEDR3 GPIO_OSPEEDR_OSPEED3
11862 #define GPIO_OSPEEDER_OSPEEDR3_0 GPIO_OSPEEDR_OSPEED3_0
11863 #define GPIO_OSPEEDER_OSPEEDR3_1 GPIO_OSPEEDR_OSPEED3_1
11864 #define GPIO_OSPEEDER_OSPEEDR4 GPIO_OSPEEDR_OSPEED4
11865 #define GPIO_OSPEEDER_OSPEEDR4_0 GPIO_OSPEEDR_OSPEED4_0
11866 #define GPIO_OSPEEDER_OSPEEDR4_1 GPIO_OSPEEDR_OSPEED4_1
11867 #define GPIO_OSPEEDER_OSPEEDR5 GPIO_OSPEEDR_OSPEED5
11868 #define GPIO_OSPEEDER_OSPEEDR5_0 GPIO_OSPEEDR_OSPEED5_0
11869 #define GPIO_OSPEEDER_OSPEEDR5_1 GPIO_OSPEEDR_OSPEED5_1
11870 #define GPIO_OSPEEDER_OSPEEDR6 GPIO_OSPEEDR_OSPEED6
11871 #define GPIO_OSPEEDER_OSPEEDR6_0 GPIO_OSPEEDR_OSPEED6_0
11872 #define GPIO_OSPEEDER_OSPEEDR6_1 GPIO_OSPEEDR_OSPEED6_1
11873 #define GPIO_OSPEEDER_OSPEEDR7 GPIO_OSPEEDR_OSPEED7
11874 #define GPIO_OSPEEDER_OSPEEDR7_0 GPIO_OSPEEDR_OSPEED7_0
11875 #define GPIO_OSPEEDER_OSPEEDR7_1 GPIO_OSPEEDR_OSPEED7_1
11876 #define GPIO_OSPEEDER_OSPEEDR8 GPIO_OSPEEDR_OSPEED8
11877 #define GPIO_OSPEEDER_OSPEEDR8_0 GPIO_OSPEEDR_OSPEED8_0
11878 #define GPIO_OSPEEDER_OSPEEDR8_1 GPIO_OSPEEDR_OSPEED8_1
11879 #define GPIO_OSPEEDER_OSPEEDR9 GPIO_OSPEEDR_OSPEED9
11880 #define GPIO_OSPEEDER_OSPEEDR9_0 GPIO_OSPEEDR_OSPEED9_0
11881 #define GPIO_OSPEEDER_OSPEEDR9_1 GPIO_OSPEEDR_OSPEED9_1
11882 #define GPIO_OSPEEDER_OSPEEDR10 GPIO_OSPEEDR_OSPEED10
11883 #define GPIO_OSPEEDER_OSPEEDR10_0 GPIO_OSPEEDR_OSPEED10_0
11884 #define GPIO_OSPEEDER_OSPEEDR10_1 GPIO_OSPEEDR_OSPEED10_1
11885 #define GPIO_OSPEEDER_OSPEEDR11 GPIO_OSPEEDR_OSPEED11
11886 #define GPIO_OSPEEDER_OSPEEDR11_0 GPIO_OSPEEDR_OSPEED11_0
11887 #define GPIO_OSPEEDER_OSPEEDR11_1 GPIO_OSPEEDR_OSPEED11_1
11888 #define GPIO_OSPEEDER_OSPEEDR12 GPIO_OSPEEDR_OSPEED12
11889 #define GPIO_OSPEEDER_OSPEEDR12_0 GPIO_OSPEEDR_OSPEED12_0
11890 #define GPIO_OSPEEDER_OSPEEDR12_1 GPIO_OSPEEDR_OSPEED12_1
11891 #define GPIO_OSPEEDER_OSPEEDR13 GPIO_OSPEEDR_OSPEED13
11892 #define GPIO_OSPEEDER_OSPEEDR13_0 GPIO_OSPEEDR_OSPEED13_0
11893 #define GPIO_OSPEEDER_OSPEEDR13_1 GPIO_OSPEEDR_OSPEED13_1
11894 #define GPIO_OSPEEDER_OSPEEDR14 GPIO_OSPEEDR_OSPEED14
11895 #define GPIO_OSPEEDER_OSPEEDR14_0 GPIO_OSPEEDR_OSPEED14_0
11896 #define GPIO_OSPEEDER_OSPEEDR14_1 GPIO_OSPEEDR_OSPEED14_1
11897 #define GPIO_OSPEEDER_OSPEEDR15 GPIO_OSPEEDR_OSPEED15
11898 #define GPIO_OSPEEDER_OSPEEDR15_0 GPIO_OSPEEDR_OSPEED15_0
11899 #define GPIO_OSPEEDER_OSPEEDR15_1 GPIO_OSPEEDR_OSPEED15_1
11900
11901 /****************** Bits definition for GPIO_PUPDR register *****************/
11902 #define GPIO_PUPDR_PUPD0_Pos (0U)
11903 #define GPIO_PUPDR_PUPD0_Msk (0x3U << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000003 */
11904 #define GPIO_PUPDR_PUPD0 GPIO_PUPDR_PUPD0_Msk
11905 #define GPIO_PUPDR_PUPD0_0 (0x1U << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000001 */
11906 #define GPIO_PUPDR_PUPD0_1 (0x2U << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000002 */
11907 #define GPIO_PUPDR_PUPD1_Pos (2U)
11908 #define GPIO_PUPDR_PUPD1_Msk (0x3U << GPIO_PUPDR_PUPD1_Pos) /*!< 0x0000000C */
11909 #define GPIO_PUPDR_PUPD1 GPIO_PUPDR_PUPD1_Msk
11910 #define GPIO_PUPDR_PUPD1_0 (0x1U << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000004 */
11911 #define GPIO_PUPDR_PUPD1_1 (0x2U << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000008 */
11912 #define GPIO_PUPDR_PUPD2_Pos (4U)
11913 #define GPIO_PUPDR_PUPD2_Msk (0x3U << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000030 */
11914 #define GPIO_PUPDR_PUPD2 GPIO_PUPDR_PUPD2_Msk
11915 #define GPIO_PUPDR_PUPD2_0 (0x1U << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000010 */
11916 #define GPIO_PUPDR_PUPD2_1 (0x2U << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000020 */
11917 #define GPIO_PUPDR_PUPD3_Pos (6U)
11918 #define GPIO_PUPDR_PUPD3_Msk (0x3U << GPIO_PUPDR_PUPD3_Pos) /*!< 0x000000C0 */
11919 #define GPIO_PUPDR_PUPD3 GPIO_PUPDR_PUPD3_Msk
11920 #define GPIO_PUPDR_PUPD3_0 (0x1U << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000040 */
11921 #define GPIO_PUPDR_PUPD3_1 (0x2U << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000080 */
11922 #define GPIO_PUPDR_PUPD4_Pos (8U)
11923 #define GPIO_PUPDR_PUPD4_Msk (0x3U << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000300 */
11924 #define GPIO_PUPDR_PUPD4 GPIO_PUPDR_PUPD4_Msk
11925 #define GPIO_PUPDR_PUPD4_0 (0x1U << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000100 */
11926 #define GPIO_PUPDR_PUPD4_1 (0x2U << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000200 */
11927 #define GPIO_PUPDR_PUPD5_Pos (10U)
11928 #define GPIO_PUPDR_PUPD5_Msk (0x3U << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000C00 */
11929 #define GPIO_PUPDR_PUPD5 GPIO_PUPDR_PUPD5_Msk
11930 #define GPIO_PUPDR_PUPD5_0 (0x1U << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000400 */
11931 #define GPIO_PUPDR_PUPD5_1 (0x2U << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000800 */
11932 #define GPIO_PUPDR_PUPD6_Pos (12U)
11933 #define GPIO_PUPDR_PUPD6_Msk (0x3U << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00003000 */
11934 #define GPIO_PUPDR_PUPD6 GPIO_PUPDR_PUPD6_Msk
11935 #define GPIO_PUPDR_PUPD6_0 (0x1U << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00001000 */
11936 #define GPIO_PUPDR_PUPD6_1 (0x2U << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00002000 */
11937 #define GPIO_PUPDR_PUPD7_Pos (14U)
11938 #define GPIO_PUPDR_PUPD7_Msk (0x3U << GPIO_PUPDR_PUPD7_Pos) /*!< 0x0000C000 */
11939 #define GPIO_PUPDR_PUPD7 GPIO_PUPDR_PUPD7_Msk
11940 #define GPIO_PUPDR_PUPD7_0 (0x1U << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00004000 */
11941 #define GPIO_PUPDR_PUPD7_1 (0x2U << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00008000 */
11942 #define GPIO_PUPDR_PUPD8_Pos (16U)
11943 #define GPIO_PUPDR_PUPD8_Msk (0x3U << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00030000 */
11944 #define GPIO_PUPDR_PUPD8 GPIO_PUPDR_PUPD8_Msk
11945 #define GPIO_PUPDR_PUPD8_0 (0x1U << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00010000 */
11946 #define GPIO_PUPDR_PUPD8_1 (0x2U << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00020000 */
11947 #define GPIO_PUPDR_PUPD9_Pos (18U)
11948 #define GPIO_PUPDR_PUPD9_Msk (0x3U << GPIO_PUPDR_PUPD9_Pos) /*!< 0x000C0000 */
11949 #define GPIO_PUPDR_PUPD9 GPIO_PUPDR_PUPD9_Msk
11950 #define GPIO_PUPDR_PUPD9_0 (0x1U << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00040000 */
11951 #define GPIO_PUPDR_PUPD9_1 (0x2U << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00080000 */
11952 #define GPIO_PUPDR_PUPD10_Pos (20U)
11953 #define GPIO_PUPDR_PUPD10_Msk (0x3U << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00300000 */
11954 #define GPIO_PUPDR_PUPD10 GPIO_PUPDR_PUPD10_Msk
11955 #define GPIO_PUPDR_PUPD10_0 (0x1U << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00100000 */
11956 #define GPIO_PUPDR_PUPD10_1 (0x2U << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00200000 */
11957 #define GPIO_PUPDR_PUPD11_Pos (22U)
11958 #define GPIO_PUPDR_PUPD11_Msk (0x3U << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00C00000 */
11959 #define GPIO_PUPDR_PUPD11 GPIO_PUPDR_PUPD11_Msk
11960 #define GPIO_PUPDR_PUPD11_0 (0x1U << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00400000 */
11961 #define GPIO_PUPDR_PUPD11_1 (0x2U << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00800000 */
11962 #define GPIO_PUPDR_PUPD12_Pos (24U)
11963 #define GPIO_PUPDR_PUPD12_Msk (0x3U << GPIO_PUPDR_PUPD12_Pos) /*!< 0x03000000 */
11964 #define GPIO_PUPDR_PUPD12 GPIO_PUPDR_PUPD12_Msk
11965 #define GPIO_PUPDR_PUPD12_0 (0x1U << GPIO_PUPDR_PUPD12_Pos) /*!< 0x01000000 */
11966 #define GPIO_PUPDR_PUPD12_1 (0x2U << GPIO_PUPDR_PUPD12_Pos) /*!< 0x02000000 */
11967 #define GPIO_PUPDR_PUPD13_Pos (26U)
11968 #define GPIO_PUPDR_PUPD13_Msk (0x3U << GPIO_PUPDR_PUPD13_Pos) /*!< 0x0C000000 */
11969 #define GPIO_PUPDR_PUPD13 GPIO_PUPDR_PUPD13_Msk
11970 #define GPIO_PUPDR_PUPD13_0 (0x1U << GPIO_PUPDR_PUPD13_Pos) /*!< 0x04000000 */
11971 #define GPIO_PUPDR_PUPD13_1 (0x2U << GPIO_PUPDR_PUPD13_Pos) /*!< 0x08000000 */
11972 #define GPIO_PUPDR_PUPD14_Pos (28U)
11973 #define GPIO_PUPDR_PUPD14_Msk (0x3U << GPIO_PUPDR_PUPD14_Pos) /*!< 0x30000000 */
11974 #define GPIO_PUPDR_PUPD14 GPIO_PUPDR_PUPD14_Msk
11975 #define GPIO_PUPDR_PUPD14_0 (0x1U << GPIO_PUPDR_PUPD14_Pos) /*!< 0x10000000 */
11976 #define GPIO_PUPDR_PUPD14_1 (0x2U << GPIO_PUPDR_PUPD14_Pos) /*!< 0x20000000 */
11977 #define GPIO_PUPDR_PUPD15_Pos (30U)
11978 #define GPIO_PUPDR_PUPD15_Msk (0x3U << GPIO_PUPDR_PUPD15_Pos) /*!< 0xC0000000 */
11979 #define GPIO_PUPDR_PUPD15 GPIO_PUPDR_PUPD15_Msk
11980 #define GPIO_PUPDR_PUPD15_0 (0x1U << GPIO_PUPDR_PUPD15_Pos) /*!< 0x40000000 */
11981 #define GPIO_PUPDR_PUPD15_1 (0x2U << GPIO_PUPDR_PUPD15_Pos) /*!< 0x80000000 */
11982
11983 /* Legacy defines */
11984 #define GPIO_PUPDR_PUPDR0 GPIO_PUPDR_PUPD0
11985 #define GPIO_PUPDR_PUPDR0_0 GPIO_PUPDR_PUPD0_0
11986 #define GPIO_PUPDR_PUPDR0_1 GPIO_PUPDR_PUPD0_1
11987 #define GPIO_PUPDR_PUPDR1 GPIO_PUPDR_PUPD1
11988 #define GPIO_PUPDR_PUPDR1_0 GPIO_PUPDR_PUPD1_0
11989 #define GPIO_PUPDR_PUPDR1_1 GPIO_PUPDR_PUPD1_1
11990 #define GPIO_PUPDR_PUPDR2 GPIO_PUPDR_PUPD2
11991 #define GPIO_PUPDR_PUPDR2_0 GPIO_PUPDR_PUPD2_0
11992 #define GPIO_PUPDR_PUPDR2_1 GPIO_PUPDR_PUPD2_1
11993 #define GPIO_PUPDR_PUPDR3 GPIO_PUPDR_PUPD3
11994 #define GPIO_PUPDR_PUPDR3_0 GPIO_PUPDR_PUPD3_0
11995 #define GPIO_PUPDR_PUPDR3_1 GPIO_PUPDR_PUPD3_1
11996 #define GPIO_PUPDR_PUPDR4 GPIO_PUPDR_PUPD4
11997 #define GPIO_PUPDR_PUPDR4_0 GPIO_PUPDR_PUPD4_0
11998 #define GPIO_PUPDR_PUPDR4_1 GPIO_PUPDR_PUPD4_1
11999 #define GPIO_PUPDR_PUPDR5 GPIO_PUPDR_PUPD5
12000 #define GPIO_PUPDR_PUPDR5_0 GPIO_PUPDR_PUPD5_0
12001 #define GPIO_PUPDR_PUPDR5_1 GPIO_PUPDR_PUPD5_1
12002 #define GPIO_PUPDR_PUPDR6 GPIO_PUPDR_PUPD6
12003 #define GPIO_PUPDR_PUPDR6_0 GPIO_PUPDR_PUPD6_0
12004 #define GPIO_PUPDR_PUPDR6_1 GPIO_PUPDR_PUPD6_1
12005 #define GPIO_PUPDR_PUPDR7 GPIO_PUPDR_PUPD7
12006 #define GPIO_PUPDR_PUPDR7_0 GPIO_PUPDR_PUPD7_0
12007 #define GPIO_PUPDR_PUPDR7_1 GPIO_PUPDR_PUPD7_1
12008 #define GPIO_PUPDR_PUPDR8 GPIO_PUPDR_PUPD8
12009 #define GPIO_PUPDR_PUPDR8_0 GPIO_PUPDR_PUPD8_0
12010 #define GPIO_PUPDR_PUPDR8_1 GPIO_PUPDR_PUPD8_1
12011 #define GPIO_PUPDR_PUPDR9 GPIO_PUPDR_PUPD9
12012 #define GPIO_PUPDR_PUPDR9_0 GPIO_PUPDR_PUPD9_0
12013 #define GPIO_PUPDR_PUPDR9_1 GPIO_PUPDR_PUPD9_1
12014 #define GPIO_PUPDR_PUPDR10 GPIO_PUPDR_PUPD10
12015 #define GPIO_PUPDR_PUPDR10_0 GPIO_PUPDR_PUPD10_0
12016 #define GPIO_PUPDR_PUPDR10_1 GPIO_PUPDR_PUPD10_1
12017 #define GPIO_PUPDR_PUPDR11 GPIO_PUPDR_PUPD11
12018 #define GPIO_PUPDR_PUPDR11_0 GPIO_PUPDR_PUPD11_0
12019 #define GPIO_PUPDR_PUPDR11_1 GPIO_PUPDR_PUPD11_1
12020 #define GPIO_PUPDR_PUPDR12 GPIO_PUPDR_PUPD12
12021 #define GPIO_PUPDR_PUPDR12_0 GPIO_PUPDR_PUPD12_0
12022 #define GPIO_PUPDR_PUPDR12_1 GPIO_PUPDR_PUPD12_1
12023 #define GPIO_PUPDR_PUPDR13 GPIO_PUPDR_PUPD13
12024 #define GPIO_PUPDR_PUPDR13_0 GPIO_PUPDR_PUPD13_0
12025 #define GPIO_PUPDR_PUPDR13_1 GPIO_PUPDR_PUPD13_1
12026 #define GPIO_PUPDR_PUPDR14 GPIO_PUPDR_PUPD14
12027 #define GPIO_PUPDR_PUPDR14_0 GPIO_PUPDR_PUPD14_0
12028 #define GPIO_PUPDR_PUPDR14_1 GPIO_PUPDR_PUPD14_1
12029 #define GPIO_PUPDR_PUPDR15 GPIO_PUPDR_PUPD15
12030 #define GPIO_PUPDR_PUPDR15_0 GPIO_PUPDR_PUPD15_0
12031 #define GPIO_PUPDR_PUPDR15_1 GPIO_PUPDR_PUPD15_1
12032
12033 /****************** Bits definition for GPIO_IDR register *******************/
12034 #define GPIO_IDR_ID0_Pos (0U)
12035 #define GPIO_IDR_ID0_Msk (0x1U << GPIO_IDR_ID0_Pos) /*!< 0x00000001 */
12036 #define GPIO_IDR_ID0 GPIO_IDR_ID0_Msk
12037 #define GPIO_IDR_ID1_Pos (1U)
12038 #define GPIO_IDR_ID1_Msk (0x1U << GPIO_IDR_ID1_Pos) /*!< 0x00000002 */
12039 #define GPIO_IDR_ID1 GPIO_IDR_ID1_Msk
12040 #define GPIO_IDR_ID2_Pos (2U)
12041 #define GPIO_IDR_ID2_Msk (0x1U << GPIO_IDR_ID2_Pos) /*!< 0x00000004 */
12042 #define GPIO_IDR_ID2 GPIO_IDR_ID2_Msk
12043 #define GPIO_IDR_ID3_Pos (3U)
12044 #define GPIO_IDR_ID3_Msk (0x1U << GPIO_IDR_ID3_Pos) /*!< 0x00000008 */
12045 #define GPIO_IDR_ID3 GPIO_IDR_ID3_Msk
12046 #define GPIO_IDR_ID4_Pos (4U)
12047 #define GPIO_IDR_ID4_Msk (0x1U << GPIO_IDR_ID4_Pos) /*!< 0x00000010 */
12048 #define GPIO_IDR_ID4 GPIO_IDR_ID4_Msk
12049 #define GPIO_IDR_ID5_Pos (5U)
12050 #define GPIO_IDR_ID5_Msk (0x1U << GPIO_IDR_ID5_Pos) /*!< 0x00000020 */
12051 #define GPIO_IDR_ID5 GPIO_IDR_ID5_Msk
12052 #define GPIO_IDR_ID6_Pos (6U)
12053 #define GPIO_IDR_ID6_Msk (0x1U << GPIO_IDR_ID6_Pos) /*!< 0x00000040 */
12054 #define GPIO_IDR_ID6 GPIO_IDR_ID6_Msk
12055 #define GPIO_IDR_ID7_Pos (7U)
12056 #define GPIO_IDR_ID7_Msk (0x1U << GPIO_IDR_ID7_Pos) /*!< 0x00000080 */
12057 #define GPIO_IDR_ID7 GPIO_IDR_ID7_Msk
12058 #define GPIO_IDR_ID8_Pos (8U)
12059 #define GPIO_IDR_ID8_Msk (0x1U << GPIO_IDR_ID8_Pos) /*!< 0x00000100 */
12060 #define GPIO_IDR_ID8 GPIO_IDR_ID8_Msk
12061 #define GPIO_IDR_ID9_Pos (9U)
12062 #define GPIO_IDR_ID9_Msk (0x1U << GPIO_IDR_ID9_Pos) /*!< 0x00000200 */
12063 #define GPIO_IDR_ID9 GPIO_IDR_ID9_Msk
12064 #define GPIO_IDR_ID10_Pos (10U)
12065 #define GPIO_IDR_ID10_Msk (0x1U << GPIO_IDR_ID10_Pos) /*!< 0x00000400 */
12066 #define GPIO_IDR_ID10 GPIO_IDR_ID10_Msk
12067 #define GPIO_IDR_ID11_Pos (11U)
12068 #define GPIO_IDR_ID11_Msk (0x1U << GPIO_IDR_ID11_Pos) /*!< 0x00000800 */
12069 #define GPIO_IDR_ID11 GPIO_IDR_ID11_Msk
12070 #define GPIO_IDR_ID12_Pos (12U)
12071 #define GPIO_IDR_ID12_Msk (0x1U << GPIO_IDR_ID12_Pos) /*!< 0x00001000 */
12072 #define GPIO_IDR_ID12 GPIO_IDR_ID12_Msk
12073 #define GPIO_IDR_ID13_Pos (13U)
12074 #define GPIO_IDR_ID13_Msk (0x1U << GPIO_IDR_ID13_Pos) /*!< 0x00002000 */
12075 #define GPIO_IDR_ID13 GPIO_IDR_ID13_Msk
12076 #define GPIO_IDR_ID14_Pos (14U)
12077 #define GPIO_IDR_ID14_Msk (0x1U << GPIO_IDR_ID14_Pos) /*!< 0x00004000 */
12078 #define GPIO_IDR_ID14 GPIO_IDR_ID14_Msk
12079 #define GPIO_IDR_ID15_Pos (15U)
12080 #define GPIO_IDR_ID15_Msk (0x1U << GPIO_IDR_ID15_Pos) /*!< 0x00008000 */
12081 #define GPIO_IDR_ID15 GPIO_IDR_ID15_Msk
12082
12083 /* Legacy defines */
12084 #define GPIO_IDR_IDR_0 GPIO_IDR_ID0
12085 #define GPIO_IDR_IDR_1 GPIO_IDR_ID1
12086 #define GPIO_IDR_IDR_2 GPIO_IDR_ID2
12087 #define GPIO_IDR_IDR_3 GPIO_IDR_ID3
12088 #define GPIO_IDR_IDR_4 GPIO_IDR_ID4
12089 #define GPIO_IDR_IDR_5 GPIO_IDR_ID5
12090 #define GPIO_IDR_IDR_6 GPIO_IDR_ID6
12091 #define GPIO_IDR_IDR_7 GPIO_IDR_ID7
12092 #define GPIO_IDR_IDR_8 GPIO_IDR_ID8
12093 #define GPIO_IDR_IDR_9 GPIO_IDR_ID9
12094 #define GPIO_IDR_IDR_10 GPIO_IDR_ID10
12095 #define GPIO_IDR_IDR_11 GPIO_IDR_ID11
12096 #define GPIO_IDR_IDR_12 GPIO_IDR_ID12
12097 #define GPIO_IDR_IDR_13 GPIO_IDR_ID13
12098 #define GPIO_IDR_IDR_14 GPIO_IDR_ID14
12099 #define GPIO_IDR_IDR_15 GPIO_IDR_ID15
12100
12101 /****************** Bits definition for GPIO_ODR register *******************/
12102 #define GPIO_ODR_OD0_Pos (0U)
12103 #define GPIO_ODR_OD0_Msk (0x1U << GPIO_ODR_OD0_Pos) /*!< 0x00000001 */
12104 #define GPIO_ODR_OD0 GPIO_ODR_OD0_Msk
12105 #define GPIO_ODR_OD1_Pos (1U)
12106 #define GPIO_ODR_OD1_Msk (0x1U << GPIO_ODR_OD1_Pos) /*!< 0x00000002 */
12107 #define GPIO_ODR_OD1 GPIO_ODR_OD1_Msk
12108 #define GPIO_ODR_OD2_Pos (2U)
12109 #define GPIO_ODR_OD2_Msk (0x1U << GPIO_ODR_OD2_Pos) /*!< 0x00000004 */
12110 #define GPIO_ODR_OD2 GPIO_ODR_OD2_Msk
12111 #define GPIO_ODR_OD3_Pos (3U)
12112 #define GPIO_ODR_OD3_Msk (0x1U << GPIO_ODR_OD3_Pos) /*!< 0x00000008 */
12113 #define GPIO_ODR_OD3 GPIO_ODR_OD3_Msk
12114 #define GPIO_ODR_OD4_Pos (4U)
12115 #define GPIO_ODR_OD4_Msk (0x1U << GPIO_ODR_OD4_Pos) /*!< 0x00000010 */
12116 #define GPIO_ODR_OD4 GPIO_ODR_OD4_Msk
12117 #define GPIO_ODR_OD5_Pos (5U)
12118 #define GPIO_ODR_OD5_Msk (0x1U << GPIO_ODR_OD5_Pos) /*!< 0x00000020 */
12119 #define GPIO_ODR_OD5 GPIO_ODR_OD5_Msk
12120 #define GPIO_ODR_OD6_Pos (6U)
12121 #define GPIO_ODR_OD6_Msk (0x1U << GPIO_ODR_OD6_Pos) /*!< 0x00000040 */
12122 #define GPIO_ODR_OD6 GPIO_ODR_OD6_Msk
12123 #define GPIO_ODR_OD7_Pos (7U)
12124 #define GPIO_ODR_OD7_Msk (0x1U << GPIO_ODR_OD7_Pos) /*!< 0x00000080 */
12125 #define GPIO_ODR_OD7 GPIO_ODR_OD7_Msk
12126 #define GPIO_ODR_OD8_Pos (8U)
12127 #define GPIO_ODR_OD8_Msk (0x1U << GPIO_ODR_OD8_Pos) /*!< 0x00000100 */
12128 #define GPIO_ODR_OD8 GPIO_ODR_OD8_Msk
12129 #define GPIO_ODR_OD9_Pos (9U)
12130 #define GPIO_ODR_OD9_Msk (0x1U << GPIO_ODR_OD9_Pos) /*!< 0x00000200 */
12131 #define GPIO_ODR_OD9 GPIO_ODR_OD9_Msk
12132 #define GPIO_ODR_OD10_Pos (10U)
12133 #define GPIO_ODR_OD10_Msk (0x1U << GPIO_ODR_OD10_Pos) /*!< 0x00000400 */
12134 #define GPIO_ODR_OD10 GPIO_ODR_OD10_Msk
12135 #define GPIO_ODR_OD11_Pos (11U)
12136 #define GPIO_ODR_OD11_Msk (0x1U << GPIO_ODR_OD11_Pos) /*!< 0x00000800 */
12137 #define GPIO_ODR_OD11 GPIO_ODR_OD11_Msk
12138 #define GPIO_ODR_OD12_Pos (12U)
12139 #define GPIO_ODR_OD12_Msk (0x1U << GPIO_ODR_OD12_Pos) /*!< 0x00001000 */
12140 #define GPIO_ODR_OD12 GPIO_ODR_OD12_Msk
12141 #define GPIO_ODR_OD13_Pos (13U)
12142 #define GPIO_ODR_OD13_Msk (0x1U << GPIO_ODR_OD13_Pos) /*!< 0x00002000 */
12143 #define GPIO_ODR_OD13 GPIO_ODR_OD13_Msk
12144 #define GPIO_ODR_OD14_Pos (14U)
12145 #define GPIO_ODR_OD14_Msk (0x1U << GPIO_ODR_OD14_Pos) /*!< 0x00004000 */
12146 #define GPIO_ODR_OD14 GPIO_ODR_OD14_Msk
12147 #define GPIO_ODR_OD15_Pos (15U)
12148 #define GPIO_ODR_OD15_Msk (0x1U << GPIO_ODR_OD15_Pos) /*!< 0x00008000 */
12149 #define GPIO_ODR_OD15 GPIO_ODR_OD15_Msk
12150 /* Legacy defines */
12151 #define GPIO_ODR_ODR_0 GPIO_ODR_OD0
12152 #define GPIO_ODR_ODR_1 GPIO_ODR_OD1
12153 #define GPIO_ODR_ODR_2 GPIO_ODR_OD2
12154 #define GPIO_ODR_ODR_3 GPIO_ODR_OD3
12155 #define GPIO_ODR_ODR_4 GPIO_ODR_OD4
12156 #define GPIO_ODR_ODR_5 GPIO_ODR_OD5
12157 #define GPIO_ODR_ODR_6 GPIO_ODR_OD6
12158 #define GPIO_ODR_ODR_7 GPIO_ODR_OD7
12159 #define GPIO_ODR_ODR_8 GPIO_ODR_OD8
12160 #define GPIO_ODR_ODR_9 GPIO_ODR_OD9
12161 #define GPIO_ODR_ODR_10 GPIO_ODR_OD10
12162 #define GPIO_ODR_ODR_11 GPIO_ODR_OD11
12163 #define GPIO_ODR_ODR_12 GPIO_ODR_OD12
12164 #define GPIO_ODR_ODR_13 GPIO_ODR_OD13
12165 #define GPIO_ODR_ODR_14 GPIO_ODR_OD14
12166 #define GPIO_ODR_ODR_15 GPIO_ODR_OD15
12167
12168 /****************** Bits definition for GPIO_BSRR register ******************/
12169 #define GPIO_BSRR_BS0_Pos (0U)
12170 #define GPIO_BSRR_BS0_Msk (0x1U << GPIO_BSRR_BS0_Pos) /*!< 0x00000001 */
12171 #define GPIO_BSRR_BS0 GPIO_BSRR_BS0_Msk
12172 #define GPIO_BSRR_BS1_Pos (1U)
12173 #define GPIO_BSRR_BS1_Msk (0x1U << GPIO_BSRR_BS1_Pos) /*!< 0x00000002 */
12174 #define GPIO_BSRR_BS1 GPIO_BSRR_BS1_Msk
12175 #define GPIO_BSRR_BS2_Pos (2U)
12176 #define GPIO_BSRR_BS2_Msk (0x1U << GPIO_BSRR_BS2_Pos) /*!< 0x00000004 */
12177 #define GPIO_BSRR_BS2 GPIO_BSRR_BS2_Msk
12178 #define GPIO_BSRR_BS3_Pos (3U)
12179 #define GPIO_BSRR_BS3_Msk (0x1U << GPIO_BSRR_BS3_Pos) /*!< 0x00000008 */
12180 #define GPIO_BSRR_BS3 GPIO_BSRR_BS3_Msk
12181 #define GPIO_BSRR_BS4_Pos (4U)
12182 #define GPIO_BSRR_BS4_Msk (0x1U << GPIO_BSRR_BS4_Pos) /*!< 0x00000010 */
12183 #define GPIO_BSRR_BS4 GPIO_BSRR_BS4_Msk
12184 #define GPIO_BSRR_BS5_Pos (5U)
12185 #define GPIO_BSRR_BS5_Msk (0x1U << GPIO_BSRR_BS5_Pos) /*!< 0x00000020 */
12186 #define GPIO_BSRR_BS5 GPIO_BSRR_BS5_Msk
12187 #define GPIO_BSRR_BS6_Pos (6U)
12188 #define GPIO_BSRR_BS6_Msk (0x1U << GPIO_BSRR_BS6_Pos) /*!< 0x00000040 */
12189 #define GPIO_BSRR_BS6 GPIO_BSRR_BS6_Msk
12190 #define GPIO_BSRR_BS7_Pos (7U)
12191 #define GPIO_BSRR_BS7_Msk (0x1U << GPIO_BSRR_BS7_Pos) /*!< 0x00000080 */
12192 #define GPIO_BSRR_BS7 GPIO_BSRR_BS7_Msk
12193 #define GPIO_BSRR_BS8_Pos (8U)
12194 #define GPIO_BSRR_BS8_Msk (0x1U << GPIO_BSRR_BS8_Pos) /*!< 0x00000100 */
12195 #define GPIO_BSRR_BS8 GPIO_BSRR_BS8_Msk
12196 #define GPIO_BSRR_BS9_Pos (9U)
12197 #define GPIO_BSRR_BS9_Msk (0x1U << GPIO_BSRR_BS9_Pos) /*!< 0x00000200 */
12198 #define GPIO_BSRR_BS9 GPIO_BSRR_BS9_Msk
12199 #define GPIO_BSRR_BS10_Pos (10U)
12200 #define GPIO_BSRR_BS10_Msk (0x1U << GPIO_BSRR_BS10_Pos) /*!< 0x00000400 */
12201 #define GPIO_BSRR_BS10 GPIO_BSRR_BS10_Msk
12202 #define GPIO_BSRR_BS11_Pos (11U)
12203 #define GPIO_BSRR_BS11_Msk (0x1U << GPIO_BSRR_BS11_Pos) /*!< 0x00000800 */
12204 #define GPIO_BSRR_BS11 GPIO_BSRR_BS11_Msk
12205 #define GPIO_BSRR_BS12_Pos (12U)
12206 #define GPIO_BSRR_BS12_Msk (0x1U << GPIO_BSRR_BS12_Pos) /*!< 0x00001000 */
12207 #define GPIO_BSRR_BS12 GPIO_BSRR_BS12_Msk
12208 #define GPIO_BSRR_BS13_Pos (13U)
12209 #define GPIO_BSRR_BS13_Msk (0x1U << GPIO_BSRR_BS13_Pos) /*!< 0x00002000 */
12210 #define GPIO_BSRR_BS13 GPIO_BSRR_BS13_Msk
12211 #define GPIO_BSRR_BS14_Pos (14U)
12212 #define GPIO_BSRR_BS14_Msk (0x1U << GPIO_BSRR_BS14_Pos) /*!< 0x00004000 */
12213 #define GPIO_BSRR_BS14 GPIO_BSRR_BS14_Msk
12214 #define GPIO_BSRR_BS15_Pos (15U)
12215 #define GPIO_BSRR_BS15_Msk (0x1U << GPIO_BSRR_BS15_Pos) /*!< 0x00008000 */
12216 #define GPIO_BSRR_BS15 GPIO_BSRR_BS15_Msk
12217 #define GPIO_BSRR_BR0_Pos (16U)
12218 #define GPIO_BSRR_BR0_Msk (0x1U << GPIO_BSRR_BR0_Pos) /*!< 0x00010000 */
12219 #define GPIO_BSRR_BR0 GPIO_BSRR_BR0_Msk
12220 #define GPIO_BSRR_BR1_Pos (17U)
12221 #define GPIO_BSRR_BR1_Msk (0x1U << GPIO_BSRR_BR1_Pos) /*!< 0x00020000 */
12222 #define GPIO_BSRR_BR1 GPIO_BSRR_BR1_Msk
12223 #define GPIO_BSRR_BR2_Pos (18U)
12224 #define GPIO_BSRR_BR2_Msk (0x1U << GPIO_BSRR_BR2_Pos) /*!< 0x00040000 */
12225 #define GPIO_BSRR_BR2 GPIO_BSRR_BR2_Msk
12226 #define GPIO_BSRR_BR3_Pos (19U)
12227 #define GPIO_BSRR_BR3_Msk (0x1U << GPIO_BSRR_BR3_Pos) /*!< 0x00080000 */
12228 #define GPIO_BSRR_BR3 GPIO_BSRR_BR3_Msk
12229 #define GPIO_BSRR_BR4_Pos (20U)
12230 #define GPIO_BSRR_BR4_Msk (0x1U << GPIO_BSRR_BR4_Pos) /*!< 0x00100000 */
12231 #define GPIO_BSRR_BR4 GPIO_BSRR_BR4_Msk
12232 #define GPIO_BSRR_BR5_Pos (21U)
12233 #define GPIO_BSRR_BR5_Msk (0x1U << GPIO_BSRR_BR5_Pos) /*!< 0x00200000 */
12234 #define GPIO_BSRR_BR5 GPIO_BSRR_BR5_Msk
12235 #define GPIO_BSRR_BR6_Pos (22U)
12236 #define GPIO_BSRR_BR6_Msk (0x1U << GPIO_BSRR_BR6_Pos) /*!< 0x00400000 */
12237 #define GPIO_BSRR_BR6 GPIO_BSRR_BR6_Msk
12238 #define GPIO_BSRR_BR7_Pos (23U)
12239 #define GPIO_BSRR_BR7_Msk (0x1U << GPIO_BSRR_BR7_Pos) /*!< 0x00800000 */
12240 #define GPIO_BSRR_BR7 GPIO_BSRR_BR7_Msk
12241 #define GPIO_BSRR_BR8_Pos (24U)
12242 #define GPIO_BSRR_BR8_Msk (0x1U << GPIO_BSRR_BR8_Pos) /*!< 0x01000000 */
12243 #define GPIO_BSRR_BR8 GPIO_BSRR_BR8_Msk
12244 #define GPIO_BSRR_BR9_Pos (25U)
12245 #define GPIO_BSRR_BR9_Msk (0x1U << GPIO_BSRR_BR9_Pos) /*!< 0x02000000 */
12246 #define GPIO_BSRR_BR9 GPIO_BSRR_BR9_Msk
12247 #define GPIO_BSRR_BR10_Pos (26U)
12248 #define GPIO_BSRR_BR10_Msk (0x1U << GPIO_BSRR_BR10_Pos) /*!< 0x04000000 */
12249 #define GPIO_BSRR_BR10 GPIO_BSRR_BR10_Msk
12250 #define GPIO_BSRR_BR11_Pos (27U)
12251 #define GPIO_BSRR_BR11_Msk (0x1U << GPIO_BSRR_BR11_Pos) /*!< 0x08000000 */
12252 #define GPIO_BSRR_BR11 GPIO_BSRR_BR11_Msk
12253 #define GPIO_BSRR_BR12_Pos (28U)
12254 #define GPIO_BSRR_BR12_Msk (0x1U << GPIO_BSRR_BR12_Pos) /*!< 0x10000000 */
12255 #define GPIO_BSRR_BR12 GPIO_BSRR_BR12_Msk
12256 #define GPIO_BSRR_BR13_Pos (29U)
12257 #define GPIO_BSRR_BR13_Msk (0x1U << GPIO_BSRR_BR13_Pos) /*!< 0x20000000 */
12258 #define GPIO_BSRR_BR13 GPIO_BSRR_BR13_Msk
12259 #define GPIO_BSRR_BR14_Pos (30U)
12260 #define GPIO_BSRR_BR14_Msk (0x1U << GPIO_BSRR_BR14_Pos) /*!< 0x40000000 */
12261 #define GPIO_BSRR_BR14 GPIO_BSRR_BR14_Msk
12262 #define GPIO_BSRR_BR15_Pos (31U)
12263 #define GPIO_BSRR_BR15_Msk (0x1U << GPIO_BSRR_BR15_Pos) /*!< 0x80000000 */
12264 #define GPIO_BSRR_BR15 GPIO_BSRR_BR15_Msk
12265
12266 /* Legacy defines */
12267 #define GPIO_BSRR_BS_0 GPIO_BSRR_BS0
12268 #define GPIO_BSRR_BS_1 GPIO_BSRR_BS1
12269 #define GPIO_BSRR_BS_2 GPIO_BSRR_BS2
12270 #define GPIO_BSRR_BS_3 GPIO_BSRR_BS3
12271 #define GPIO_BSRR_BS_4 GPIO_BSRR_BS4
12272 #define GPIO_BSRR_BS_5 GPIO_BSRR_BS5
12273 #define GPIO_BSRR_BS_6 GPIO_BSRR_BS6
12274 #define GPIO_BSRR_BS_7 GPIO_BSRR_BS7
12275 #define GPIO_BSRR_BS_8 GPIO_BSRR_BS8
12276 #define GPIO_BSRR_BS_9 GPIO_BSRR_BS9
12277 #define GPIO_BSRR_BS_10 GPIO_BSRR_BS10
12278 #define GPIO_BSRR_BS_11 GPIO_BSRR_BS11
12279 #define GPIO_BSRR_BS_12 GPIO_BSRR_BS12
12280 #define GPIO_BSRR_BS_13 GPIO_BSRR_BS13
12281 #define GPIO_BSRR_BS_14 GPIO_BSRR_BS14
12282 #define GPIO_BSRR_BS_15 GPIO_BSRR_BS15
12283 #define GPIO_BSRR_BR_0 GPIO_BSRR_BR0
12284 #define GPIO_BSRR_BR_1 GPIO_BSRR_BR1
12285 #define GPIO_BSRR_BR_2 GPIO_BSRR_BR2
12286 #define GPIO_BSRR_BR_3 GPIO_BSRR_BR3
12287 #define GPIO_BSRR_BR_4 GPIO_BSRR_BR4
12288 #define GPIO_BSRR_BR_5 GPIO_BSRR_BR5
12289 #define GPIO_BSRR_BR_6 GPIO_BSRR_BR6
12290 #define GPIO_BSRR_BR_7 GPIO_BSRR_BR7
12291 #define GPIO_BSRR_BR_8 GPIO_BSRR_BR8
12292 #define GPIO_BSRR_BR_9 GPIO_BSRR_BR9
12293 #define GPIO_BSRR_BR_10 GPIO_BSRR_BR10
12294 #define GPIO_BSRR_BR_11 GPIO_BSRR_BR11
12295 #define GPIO_BSRR_BR_12 GPIO_BSRR_BR12
12296 #define GPIO_BSRR_BR_13 GPIO_BSRR_BR13
12297 #define GPIO_BSRR_BR_14 GPIO_BSRR_BR14
12298 #define GPIO_BSRR_BR_15 GPIO_BSRR_BR15
12299 /****************** Bit definition for GPIO_LCKR register *********************/
12300 #define GPIO_LCKR_LCK0_Pos (0U)
12301 #define GPIO_LCKR_LCK0_Msk (0x1U << GPIO_LCKR_LCK0_Pos) /*!< 0x00000001 */
12302 #define GPIO_LCKR_LCK0 GPIO_LCKR_LCK0_Msk
12303 #define GPIO_LCKR_LCK1_Pos (1U)
12304 #define GPIO_LCKR_LCK1_Msk (0x1U << GPIO_LCKR_LCK1_Pos) /*!< 0x00000002 */
12305 #define GPIO_LCKR_LCK1 GPIO_LCKR_LCK1_Msk
12306 #define GPIO_LCKR_LCK2_Pos (2U)
12307 #define GPIO_LCKR_LCK2_Msk (0x1U << GPIO_LCKR_LCK2_Pos) /*!< 0x00000004 */
12308 #define GPIO_LCKR_LCK2 GPIO_LCKR_LCK2_Msk
12309 #define GPIO_LCKR_LCK3_Pos (3U)
12310 #define GPIO_LCKR_LCK3_Msk (0x1U << GPIO_LCKR_LCK3_Pos) /*!< 0x00000008 */
12311 #define GPIO_LCKR_LCK3 GPIO_LCKR_LCK3_Msk
12312 #define GPIO_LCKR_LCK4_Pos (4U)
12313 #define GPIO_LCKR_LCK4_Msk (0x1U << GPIO_LCKR_LCK4_Pos) /*!< 0x00000010 */
12314 #define GPIO_LCKR_LCK4 GPIO_LCKR_LCK4_Msk
12315 #define GPIO_LCKR_LCK5_Pos (5U)
12316 #define GPIO_LCKR_LCK5_Msk (0x1U << GPIO_LCKR_LCK5_Pos) /*!< 0x00000020 */
12317 #define GPIO_LCKR_LCK5 GPIO_LCKR_LCK5_Msk
12318 #define GPIO_LCKR_LCK6_Pos (6U)
12319 #define GPIO_LCKR_LCK6_Msk (0x1U << GPIO_LCKR_LCK6_Pos) /*!< 0x00000040 */
12320 #define GPIO_LCKR_LCK6 GPIO_LCKR_LCK6_Msk
12321 #define GPIO_LCKR_LCK7_Pos (7U)
12322 #define GPIO_LCKR_LCK7_Msk (0x1U << GPIO_LCKR_LCK7_Pos) /*!< 0x00000080 */
12323 #define GPIO_LCKR_LCK7 GPIO_LCKR_LCK7_Msk
12324 #define GPIO_LCKR_LCK8_Pos (8U)
12325 #define GPIO_LCKR_LCK8_Msk (0x1U << GPIO_LCKR_LCK8_Pos) /*!< 0x00000100 */
12326 #define GPIO_LCKR_LCK8 GPIO_LCKR_LCK8_Msk
12327 #define GPIO_LCKR_LCK9_Pos (9U)
12328 #define GPIO_LCKR_LCK9_Msk (0x1U << GPIO_LCKR_LCK9_Pos) /*!< 0x00000200 */
12329 #define GPIO_LCKR_LCK9 GPIO_LCKR_LCK9_Msk
12330 #define GPIO_LCKR_LCK10_Pos (10U)
12331 #define GPIO_LCKR_LCK10_Msk (0x1U << GPIO_LCKR_LCK10_Pos) /*!< 0x00000400 */
12332 #define GPIO_LCKR_LCK10 GPIO_LCKR_LCK10_Msk
12333 #define GPIO_LCKR_LCK11_Pos (11U)
12334 #define GPIO_LCKR_LCK11_Msk (0x1U << GPIO_LCKR_LCK11_Pos) /*!< 0x00000800 */
12335 #define GPIO_LCKR_LCK11 GPIO_LCKR_LCK11_Msk
12336 #define GPIO_LCKR_LCK12_Pos (12U)
12337 #define GPIO_LCKR_LCK12_Msk (0x1U << GPIO_LCKR_LCK12_Pos) /*!< 0x00001000 */
12338 #define GPIO_LCKR_LCK12 GPIO_LCKR_LCK12_Msk
12339 #define GPIO_LCKR_LCK13_Pos (13U)
12340 #define GPIO_LCKR_LCK13_Msk (0x1U << GPIO_LCKR_LCK13_Pos) /*!< 0x00002000 */
12341 #define GPIO_LCKR_LCK13 GPIO_LCKR_LCK13_Msk
12342 #define GPIO_LCKR_LCK14_Pos (14U)
12343 #define GPIO_LCKR_LCK14_Msk (0x1U << GPIO_LCKR_LCK14_Pos) /*!< 0x00004000 */
12344 #define GPIO_LCKR_LCK14 GPIO_LCKR_LCK14_Msk
12345 #define GPIO_LCKR_LCK15_Pos (15U)
12346 #define GPIO_LCKR_LCK15_Msk (0x1U << GPIO_LCKR_LCK15_Pos) /*!< 0x00008000 */
12347 #define GPIO_LCKR_LCK15 GPIO_LCKR_LCK15_Msk
12348 #define GPIO_LCKR_LCKK_Pos (16U)
12349 #define GPIO_LCKR_LCKK_Msk (0x1U << GPIO_LCKR_LCKK_Pos) /*!< 0x00010000 */
12350 #define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk
12351 /****************** Bit definition for GPIO_AFRL register *********************/
12352 #define GPIO_AFRL_AFSEL0_Pos (0U)
12353 #define GPIO_AFRL_AFSEL0_Msk (0xFU << GPIO_AFRL_AFSEL0_Pos) /*!< 0x0000000F */
12354 #define GPIO_AFRL_AFSEL0 GPIO_AFRL_AFSEL0_Msk
12355 #define GPIO_AFRL_AFSEL0_0 (0x1U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000001 */
12356 #define GPIO_AFRL_AFSEL0_1 (0x2U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000002 */
12357 #define GPIO_AFRL_AFSEL0_2 (0x4U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000004 */
12358 #define GPIO_AFRL_AFSEL0_3 (0x8U << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000008 */
12359 #define GPIO_AFRL_AFSEL1_Pos (4U)
12360 #define GPIO_AFRL_AFSEL1_Msk (0xFU << GPIO_AFRL_AFSEL1_Pos) /*!< 0x000000F0 */
12361 #define GPIO_AFRL_AFSEL1 GPIO_AFRL_AFSEL1_Msk
12362 #define GPIO_AFRL_AFSEL1_0 (0x1U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000010 */
12363 #define GPIO_AFRL_AFSEL1_1 (0x2U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000020 */
12364 #define GPIO_AFRL_AFSEL1_2 (0x4U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000040 */
12365 #define GPIO_AFRL_AFSEL1_3 (0x8U << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000080 */
12366 #define GPIO_AFRL_AFSEL2_Pos (8U)
12367 #define GPIO_AFRL_AFSEL2_Msk (0xFU << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000F00 */
12368 #define GPIO_AFRL_AFSEL2 GPIO_AFRL_AFSEL2_Msk
12369 #define GPIO_AFRL_AFSEL2_0 (0x1U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000100 */
12370 #define GPIO_AFRL_AFSEL2_1 (0x2U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000200 */
12371 #define GPIO_AFRL_AFSEL2_2 (0x4U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000400 */
12372 #define GPIO_AFRL_AFSEL2_3 (0x8U << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000800 */
12373 #define GPIO_AFRL_AFSEL3_Pos (12U)
12374 #define GPIO_AFRL_AFSEL3_Msk (0xFU << GPIO_AFRL_AFSEL3_Pos) /*!< 0x0000F000 */
12375 #define GPIO_AFRL_AFSEL3 GPIO_AFRL_AFSEL3_Msk
12376 #define GPIO_AFRL_AFSEL3_0 (0x1U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00001000 */
12377 #define GPIO_AFRL_AFSEL3_1 (0x2U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00002000 */
12378 #define GPIO_AFRL_AFSEL3_2 (0x4U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00004000 */
12379 #define GPIO_AFRL_AFSEL3_3 (0x8U << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00008000 */
12380 #define GPIO_AFRL_AFSEL4_Pos (16U)
12381 #define GPIO_AFRL_AFSEL4_Msk (0xFU << GPIO_AFRL_AFSEL4_Pos) /*!< 0x000F0000 */
12382 #define GPIO_AFRL_AFSEL4 GPIO_AFRL_AFSEL4_Msk
12383 #define GPIO_AFRL_AFSEL4_0 (0x1U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00010000 */
12384 #define GPIO_AFRL_AFSEL4_1 (0x2U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00020000 */
12385 #define GPIO_AFRL_AFSEL4_2 (0x4U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00040000 */
12386 #define GPIO_AFRL_AFSEL4_3 (0x8U << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00080000 */
12387 #define GPIO_AFRL_AFSEL5_Pos (20U)
12388 #define GPIO_AFRL_AFSEL5_Msk (0xFU << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00F00000 */
12389 #define GPIO_AFRL_AFSEL5 GPIO_AFRL_AFSEL5_Msk
12390 #define GPIO_AFRL_AFSEL5_0 (0x1U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00100000 */
12391 #define GPIO_AFRL_AFSEL5_1 (0x2U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00200000 */
12392 #define GPIO_AFRL_AFSEL5_2 (0x4U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00400000 */
12393 #define GPIO_AFRL_AFSEL5_3 (0x8U << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00800000 */
12394 #define GPIO_AFRL_AFSEL6_Pos (24U)
12395 #define GPIO_AFRL_AFSEL6_Msk (0xFU << GPIO_AFRL_AFSEL6_Pos) /*!< 0x0F000000 */
12396 #define GPIO_AFRL_AFSEL6 GPIO_AFRL_AFSEL6_Msk
12397 #define GPIO_AFRL_AFSEL6_0 (0x1U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x01000000 */
12398 #define GPIO_AFRL_AFSEL6_1 (0x2U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x02000000 */
12399 #define GPIO_AFRL_AFSEL6_2 (0x4U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x04000000 */
12400 #define GPIO_AFRL_AFSEL6_3 (0x8U << GPIO_AFRL_AFSEL6_Pos) /*!< 0x08000000 */
12401 #define GPIO_AFRL_AFSEL7_Pos (28U)
12402 #define GPIO_AFRL_AFSEL7_Msk (0xFU << GPIO_AFRL_AFSEL7_Pos) /*!< 0xF0000000 */
12403 #define GPIO_AFRL_AFSEL7 GPIO_AFRL_AFSEL7_Msk
12404 #define GPIO_AFRL_AFSEL7_0 (0x1U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x10000000 */
12405 #define GPIO_AFRL_AFSEL7_1 (0x2U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x20000000 */
12406 #define GPIO_AFRL_AFSEL7_2 (0x4U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x40000000 */
12407 #define GPIO_AFRL_AFSEL7_3 (0x8U << GPIO_AFRL_AFSEL7_Pos) /*!< 0x80000000 */
12408
12409 /* Legacy defines */
12410 #define GPIO_AFRL_AFRL0 GPIO_AFRL_AFSEL0
12411 #define GPIO_AFRL_AFRL0_0 GPIO_AFRL_AFSEL0_0
12412 #define GPIO_AFRL_AFRL0_1 GPIO_AFRL_AFSEL0_1
12413 #define GPIO_AFRL_AFRL0_2 GPIO_AFRL_AFSEL0_2
12414 #define GPIO_AFRL_AFRL0_3 GPIO_AFRL_AFSEL0_3
12415 #define GPIO_AFRL_AFRL1 GPIO_AFRL_AFSEL1
12416 #define GPIO_AFRL_AFRL1_0 GPIO_AFRL_AFSEL1_0
12417 #define GPIO_AFRL_AFRL1_1 GPIO_AFRL_AFSEL1_1
12418 #define GPIO_AFRL_AFRL1_2 GPIO_AFRL_AFSEL1_2
12419 #define GPIO_AFRL_AFRL1_3 GPIO_AFRL_AFSEL1_3
12420 #define GPIO_AFRL_AFRL2 GPIO_AFRL_AFSEL2
12421 #define GPIO_AFRL_AFRL2_0 GPIO_AFRL_AFSEL2_0
12422 #define GPIO_AFRL_AFRL2_1 GPIO_AFRL_AFSEL2_1
12423 #define GPIO_AFRL_AFRL2_2 GPIO_AFRL_AFSEL2_2
12424 #define GPIO_AFRL_AFRL2_3 GPIO_AFRL_AFSEL2_3
12425 #define GPIO_AFRL_AFRL3 GPIO_AFRL_AFSEL3
12426 #define GPIO_AFRL_AFRL3_0 GPIO_AFRL_AFSEL3_0
12427 #define GPIO_AFRL_AFRL3_1 GPIO_AFRL_AFSEL3_1
12428 #define GPIO_AFRL_AFRL3_2 GPIO_AFRL_AFSEL3_2
12429 #define GPIO_AFRL_AFRL3_3 GPIO_AFRL_AFSEL3_3
12430 #define GPIO_AFRL_AFRL4 GPIO_AFRL_AFSEL4
12431 #define GPIO_AFRL_AFRL4_0 GPIO_AFRL_AFSEL4_0
12432 #define GPIO_AFRL_AFRL4_1 GPIO_AFRL_AFSEL4_1
12433 #define GPIO_AFRL_AFRL4_2 GPIO_AFRL_AFSEL4_2
12434 #define GPIO_AFRL_AFRL4_3 GPIO_AFRL_AFSEL4_3
12435 #define GPIO_AFRL_AFRL5 GPIO_AFRL_AFSEL5
12436 #define GPIO_AFRL_AFRL5_0 GPIO_AFRL_AFSEL5_0
12437 #define GPIO_AFRL_AFRL5_1 GPIO_AFRL_AFSEL5_1
12438 #define GPIO_AFRL_AFRL5_2 GPIO_AFRL_AFSEL5_2
12439 #define GPIO_AFRL_AFRL5_3 GPIO_AFRL_AFSEL5_3
12440 #define GPIO_AFRL_AFRL6 GPIO_AFRL_AFSEL6
12441 #define GPIO_AFRL_AFRL6_0 GPIO_AFRL_AFSEL6_0
12442 #define GPIO_AFRL_AFRL6_1 GPIO_AFRL_AFSEL6_1
12443 #define GPIO_AFRL_AFRL6_2 GPIO_AFRL_AFSEL6_2
12444 #define GPIO_AFRL_AFRL6_3 GPIO_AFRL_AFSEL6_3
12445 #define GPIO_AFRL_AFRL7 GPIO_AFRL_AFSEL7
12446 #define GPIO_AFRL_AFRL7_0 GPIO_AFRL_AFSEL7_0
12447 #define GPIO_AFRL_AFRL7_1 GPIO_AFRL_AFSEL7_1
12448 #define GPIO_AFRL_AFRL7_2 GPIO_AFRL_AFSEL7_2
12449 #define GPIO_AFRL_AFRL7_3 GPIO_AFRL_AFSEL7_3
12450
12451 /****************** Bit definition for GPIO_AFRH register *********************/
12452 #define GPIO_AFRH_AFSEL8_Pos (0U)
12453 #define GPIO_AFRH_AFSEL8_Msk (0xFU << GPIO_AFRH_AFSEL8_Pos) /*!< 0x0000000F */
12454 #define GPIO_AFRH_AFSEL8 GPIO_AFRH_AFSEL8_Msk
12455 #define GPIO_AFRH_AFSEL8_0 (0x1U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000001 */
12456 #define GPIO_AFRH_AFSEL8_1 (0x2U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000002 */
12457 #define GPIO_AFRH_AFSEL8_2 (0x4U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000004 */
12458 #define GPIO_AFRH_AFSEL8_3 (0x8U << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000008 */
12459 #define GPIO_AFRH_AFSEL9_Pos (4U)
12460 #define GPIO_AFRH_AFSEL9_Msk (0xFU << GPIO_AFRH_AFSEL9_Pos) /*!< 0x000000F0 */
12461 #define GPIO_AFRH_AFSEL9 GPIO_AFRH_AFSEL9_Msk
12462 #define GPIO_AFRH_AFSEL9_0 (0x1U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000010 */
12463 #define GPIO_AFRH_AFSEL9_1 (0x2U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000020 */
12464 #define GPIO_AFRH_AFSEL9_2 (0x4U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000040 */
12465 #define GPIO_AFRH_AFSEL9_3 (0x8U << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000080 */
12466 #define GPIO_AFRH_AFSEL10_Pos (8U)
12467 #define GPIO_AFRH_AFSEL10_Msk (0xFU << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000F00 */
12468 #define GPIO_AFRH_AFSEL10 GPIO_AFRH_AFSEL10_Msk
12469 #define GPIO_AFRH_AFSEL10_0 (0x1U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000100 */
12470 #define GPIO_AFRH_AFSEL10_1 (0x2U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000200 */
12471 #define GPIO_AFRH_AFSEL10_2 (0x4U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000400 */
12472 #define GPIO_AFRH_AFSEL10_3 (0x8U << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000800 */
12473 #define GPIO_AFRH_AFSEL11_Pos (12U)
12474 #define GPIO_AFRH_AFSEL11_Msk (0xFU << GPIO_AFRH_AFSEL11_Pos) /*!< 0x0000F000 */
12475 #define GPIO_AFRH_AFSEL11 GPIO_AFRH_AFSEL11_Msk
12476 #define GPIO_AFRH_AFSEL11_0 (0x1U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00001000 */
12477 #define GPIO_AFRH_AFSEL11_1 (0x2U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00002000 */
12478 #define GPIO_AFRH_AFSEL11_2 (0x4U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00004000 */
12479 #define GPIO_AFRH_AFSEL11_3 (0x8U << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00008000 */
12480 #define GPIO_AFRH_AFSEL12_Pos (16U)
12481 #define GPIO_AFRH_AFSEL12_Msk (0xFU << GPIO_AFRH_AFSEL12_Pos) /*!< 0x000F0000 */
12482 #define GPIO_AFRH_AFSEL12 GPIO_AFRH_AFSEL12_Msk
12483 #define GPIO_AFRH_AFSEL12_0 (0x1U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00010000 */
12484 #define GPIO_AFRH_AFSEL12_1 (0x2U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00020000 */
12485 #define GPIO_AFRH_AFSEL12_2 (0x4U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00040000 */
12486 #define GPIO_AFRH_AFSEL12_3 (0x8U << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00080000 */
12487 #define GPIO_AFRH_AFSEL13_Pos (20U)
12488 #define GPIO_AFRH_AFSEL13_Msk (0xFU << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00F00000 */
12489 #define GPIO_AFRH_AFSEL13 GPIO_AFRH_AFSEL13_Msk
12490 #define GPIO_AFRH_AFSEL13_0 (0x1U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00100000 */
12491 #define GPIO_AFRH_AFSEL13_1 (0x2U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00200000 */
12492 #define GPIO_AFRH_AFSEL13_2 (0x4U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00400000 */
12493 #define GPIO_AFRH_AFSEL13_3 (0x8U << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00800000 */
12494 #define GPIO_AFRH_AFSEL14_Pos (24U)
12495 #define GPIO_AFRH_AFSEL14_Msk (0xFU << GPIO_AFRH_AFSEL14_Pos) /*!< 0x0F000000 */
12496 #define GPIO_AFRH_AFSEL14 GPIO_AFRH_AFSEL14_Msk
12497 #define GPIO_AFRH_AFSEL14_0 (0x1U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x01000000 */
12498 #define GPIO_AFRH_AFSEL14_1 (0x2U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x02000000 */
12499 #define GPIO_AFRH_AFSEL14_2 (0x4U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x04000000 */
12500 #define GPIO_AFRH_AFSEL14_3 (0x8U << GPIO_AFRH_AFSEL14_Pos) /*!< 0x08000000 */
12501 #define GPIO_AFRH_AFSEL15_Pos (28U)
12502 #define GPIO_AFRH_AFSEL15_Msk (0xFU << GPIO_AFRH_AFSEL15_Pos) /*!< 0xF0000000 */
12503 #define GPIO_AFRH_AFSEL15 GPIO_AFRH_AFSEL15_Msk
12504 #define GPIO_AFRH_AFSEL15_0 (0x1U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x10000000 */
12505 #define GPIO_AFRH_AFSEL15_1 (0x2U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x20000000 */
12506 #define GPIO_AFRH_AFSEL15_2 (0x4U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x40000000 */
12507 #define GPIO_AFRH_AFSEL15_3 (0x8U << GPIO_AFRH_AFSEL15_Pos) /*!< 0x80000000 */
12508
12509 /* Legacy defines */
12510 #define GPIO_AFRH_AFRH0 GPIO_AFRH_AFSEL8
12511 #define GPIO_AFRH_AFRH0_0 GPIO_AFRH_AFSEL8_0
12512 #define GPIO_AFRH_AFRH0_1 GPIO_AFRH_AFSEL8_1
12513 #define GPIO_AFRH_AFRH0_2 GPIO_AFRH_AFSEL8_2
12514 #define GPIO_AFRH_AFRH0_3 GPIO_AFRH_AFSEL8_3
12515 #define GPIO_AFRH_AFRH1 GPIO_AFRH_AFSEL9
12516 #define GPIO_AFRH_AFRH1_0 GPIO_AFRH_AFSEL9_0
12517 #define GPIO_AFRH_AFRH1_1 GPIO_AFRH_AFSEL9_1
12518 #define GPIO_AFRH_AFRH1_2 GPIO_AFRH_AFSEL9_2
12519 #define GPIO_AFRH_AFRH1_3 GPIO_AFRH_AFSEL9_3
12520 #define GPIO_AFRH_AFRH2 GPIO_AFRH_AFSEL10
12521 #define GPIO_AFRH_AFRH2_0 GPIO_AFRH_AFSEL10_0
12522 #define GPIO_AFRH_AFRH2_1 GPIO_AFRH_AFSEL10_1
12523 #define GPIO_AFRH_AFRH2_2 GPIO_AFRH_AFSEL10_2
12524 #define GPIO_AFRH_AFRH2_3 GPIO_AFRH_AFSEL10_3
12525 #define GPIO_AFRH_AFRH3 GPIO_AFRH_AFSEL11
12526 #define GPIO_AFRH_AFRH3_0 GPIO_AFRH_AFSEL11_0
12527 #define GPIO_AFRH_AFRH3_1 GPIO_AFRH_AFSEL11_1
12528 #define GPIO_AFRH_AFRH3_2 GPIO_AFRH_AFSEL11_2
12529 #define GPIO_AFRH_AFRH3_3 GPIO_AFRH_AFSEL11_3
12530 #define GPIO_AFRH_AFRH4 GPIO_AFRH_AFSEL12
12531 #define GPIO_AFRH_AFRH4_0 GPIO_AFRH_AFSEL12_0
12532 #define GPIO_AFRH_AFRH4_1 GPIO_AFRH_AFSEL12_1
12533 #define GPIO_AFRH_AFRH4_2 GPIO_AFRH_AFSEL12_2
12534 #define GPIO_AFRH_AFRH4_3 GPIO_AFRH_AFSEL12_3
12535 #define GPIO_AFRH_AFRH5 GPIO_AFRH_AFSEL13
12536 #define GPIO_AFRH_AFRH5_0 GPIO_AFRH_AFSEL13_0
12537 #define GPIO_AFRH_AFRH5_1 GPIO_AFRH_AFSEL13_1
12538 #define GPIO_AFRH_AFRH5_2 GPIO_AFRH_AFSEL13_2
12539 #define GPIO_AFRH_AFRH5_3 GPIO_AFRH_AFSEL13_3
12540 #define GPIO_AFRH_AFRH6 GPIO_AFRH_AFSEL14
12541 #define GPIO_AFRH_AFRH6_0 GPIO_AFRH_AFSEL14_0
12542 #define GPIO_AFRH_AFRH6_1 GPIO_AFRH_AFSEL14_1
12543 #define GPIO_AFRH_AFRH6_2 GPIO_AFRH_AFSEL14_2
12544 #define GPIO_AFRH_AFRH6_3 GPIO_AFRH_AFSEL14_3
12545 #define GPIO_AFRH_AFRH7 GPIO_AFRH_AFSEL15
12546 #define GPIO_AFRH_AFRH7_0 GPIO_AFRH_AFSEL15_0
12547 #define GPIO_AFRH_AFRH7_1 GPIO_AFRH_AFSEL15_1
12548 #define GPIO_AFRH_AFRH7_2 GPIO_AFRH_AFSEL15_2
12549 #define GPIO_AFRH_AFRH7_3 GPIO_AFRH_AFSEL15_3
12550
12551 /****************** Bits definition for GPIO_BRR register ******************/
12552 #define GPIO_BRR_BR0_Pos (0U)
12553 #define GPIO_BRR_BR0_Msk (0x1U << GPIO_BRR_BR0_Pos) /*!< 0x00000001 */
12554 #define GPIO_BRR_BR0 GPIO_BRR_BR0_Msk
12555 #define GPIO_BRR_BR1_Pos (1U)
12556 #define GPIO_BRR_BR1_Msk (0x1U << GPIO_BRR_BR1_Pos) /*!< 0x00000002 */
12557 #define GPIO_BRR_BR1 GPIO_BRR_BR1_Msk
12558 #define GPIO_BRR_BR2_Pos (2U)
12559 #define GPIO_BRR_BR2_Msk (0x1U << GPIO_BRR_BR2_Pos) /*!< 0x00000004 */
12560 #define GPIO_BRR_BR2 GPIO_BRR_BR2_Msk
12561 #define GPIO_BRR_BR3_Pos (3U)
12562 #define GPIO_BRR_BR3_Msk (0x1U << GPIO_BRR_BR3_Pos) /*!< 0x00000008 */
12563 #define GPIO_BRR_BR3 GPIO_BRR_BR3_Msk
12564 #define GPIO_BRR_BR4_Pos (4U)
12565 #define GPIO_BRR_BR4_Msk (0x1U << GPIO_BRR_BR4_Pos) /*!< 0x00000010 */
12566 #define GPIO_BRR_BR4 GPIO_BRR_BR4_Msk
12567 #define GPIO_BRR_BR5_Pos (5U)
12568 #define GPIO_BRR_BR5_Msk (0x1U << GPIO_BRR_BR5_Pos) /*!< 0x00000020 */
12569 #define GPIO_BRR_BR5 GPIO_BRR_BR5_Msk
12570 #define GPIO_BRR_BR6_Pos (6U)
12571 #define GPIO_BRR_BR6_Msk (0x1U << GPIO_BRR_BR6_Pos) /*!< 0x00000040 */
12572 #define GPIO_BRR_BR6 GPIO_BRR_BR6_Msk
12573 #define GPIO_BRR_BR7_Pos (7U)
12574 #define GPIO_BRR_BR7_Msk (0x1U << GPIO_BRR_BR7_Pos) /*!< 0x00000080 */
12575 #define GPIO_BRR_BR7 GPIO_BRR_BR7_Msk
12576 #define GPIO_BRR_BR8_Pos (8U)
12577 #define GPIO_BRR_BR8_Msk (0x1U << GPIO_BRR_BR8_Pos) /*!< 0x00000100 */
12578 #define GPIO_BRR_BR8 GPIO_BRR_BR8_Msk
12579 #define GPIO_BRR_BR9_Pos (9U)
12580 #define GPIO_BRR_BR9_Msk (0x1U << GPIO_BRR_BR9_Pos) /*!< 0x00000200 */
12581 #define GPIO_BRR_BR9 GPIO_BRR_BR9_Msk
12582 #define GPIO_BRR_BR10_Pos (10U)
12583 #define GPIO_BRR_BR10_Msk (0x1U << GPIO_BRR_BR10_Pos) /*!< 0x00000400 */
12584 #define GPIO_BRR_BR10 GPIO_BRR_BR10_Msk
12585 #define GPIO_BRR_BR11_Pos (11U)
12586 #define GPIO_BRR_BR11_Msk (0x1U << GPIO_BRR_BR11_Pos) /*!< 0x00000800 */
12587 #define GPIO_BRR_BR11 GPIO_BRR_BR11_Msk
12588 #define GPIO_BRR_BR12_Pos (12U)
12589 #define GPIO_BRR_BR12_Msk (0x1U << GPIO_BRR_BR12_Pos) /*!< 0x00001000 */
12590 #define GPIO_BRR_BR12 GPIO_BRR_BR12_Msk
12591 #define GPIO_BRR_BR13_Pos (13U)
12592 #define GPIO_BRR_BR13_Msk (0x1U << GPIO_BRR_BR13_Pos) /*!< 0x00002000 */
12593 #define GPIO_BRR_BR13 GPIO_BRR_BR13_Msk
12594 #define GPIO_BRR_BR14_Pos (14U)
12595 #define GPIO_BRR_BR14_Msk (0x1U << GPIO_BRR_BR14_Pos) /*!< 0x00004000 */
12596 #define GPIO_BRR_BR14 GPIO_BRR_BR14_Msk
12597 #define GPIO_BRR_BR15_Pos (15U)
12598 #define GPIO_BRR_BR15_Msk (0x1U << GPIO_BRR_BR15_Pos) /*!< 0x00008000 */
12599 #define GPIO_BRR_BR15 GPIO_BRR_BR15_Msk
12600
12601
12602 /******************************************************************************/
12603 /* */
12604 /* Inter-integrated Circuit Interface */
12605 /* */
12606 /******************************************************************************/
12607 /******************* Bit definition for I2C_CR1 register ********************/
12608 #define I2C_CR1_PE_Pos (0U)
12609 #define I2C_CR1_PE_Msk (0x1U << I2C_CR1_PE_Pos) /*!< 0x00000001 */
12610 #define I2C_CR1_PE I2C_CR1_PE_Msk /*!<Peripheral Enable */
12611 #define I2C_CR1_SMBUS_Pos (1U)
12612 #define I2C_CR1_SMBUS_Msk (0x1U << I2C_CR1_SMBUS_Pos) /*!< 0x00000002 */
12613 #define I2C_CR1_SMBUS I2C_CR1_SMBUS_Msk /*!<SMBus Mode */
12614 #define I2C_CR1_SMBTYPE_Pos (3U)
12615 #define I2C_CR1_SMBTYPE_Msk (0x1U << I2C_CR1_SMBTYPE_Pos) /*!< 0x00000008 */
12616 #define I2C_CR1_SMBTYPE I2C_CR1_SMBTYPE_Msk /*!<SMBus Type */
12617 #define I2C_CR1_ENARP_Pos (4U)
12618 #define I2C_CR1_ENARP_Msk (0x1U << I2C_CR1_ENARP_Pos) /*!< 0x00000010 */
12619 #define I2C_CR1_ENARP I2C_CR1_ENARP_Msk /*!<ARP Enable */
12620 #define I2C_CR1_ENPEC_Pos (5U)
12621 #define I2C_CR1_ENPEC_Msk (0x1U << I2C_CR1_ENPEC_Pos) /*!< 0x00000020 */
12622 #define I2C_CR1_ENPEC I2C_CR1_ENPEC_Msk /*!<PEC Enable */
12623 #define I2C_CR1_ENGC_Pos (6U)
12624 #define I2C_CR1_ENGC_Msk (0x1U << I2C_CR1_ENGC_Pos) /*!< 0x00000040 */
12625 #define I2C_CR1_ENGC I2C_CR1_ENGC_Msk /*!<General Call Enable */
12626 #define I2C_CR1_NOSTRETCH_Pos (7U)
12627 #define I2C_CR1_NOSTRETCH_Msk (0x1U << I2C_CR1_NOSTRETCH_Pos) /*!< 0x00000080 */
12628 #define I2C_CR1_NOSTRETCH I2C_CR1_NOSTRETCH_Msk /*!<Clock Stretching Disable (Slave mode) */
12629 #define I2C_CR1_START_Pos (8U)
12630 #define I2C_CR1_START_Msk (0x1U << I2C_CR1_START_Pos) /*!< 0x00000100 */
12631 #define I2C_CR1_START I2C_CR1_START_Msk /*!<Start Generation */
12632 #define I2C_CR1_STOP_Pos (9U)
12633 #define I2C_CR1_STOP_Msk (0x1U << I2C_CR1_STOP_Pos) /*!< 0x00000200 */
12634 #define I2C_CR1_STOP I2C_CR1_STOP_Msk /*!<Stop Generation */
12635 #define I2C_CR1_ACK_Pos (10U)
12636 #define I2C_CR1_ACK_Msk (0x1U << I2C_CR1_ACK_Pos) /*!< 0x00000400 */
12637 #define I2C_CR1_ACK I2C_CR1_ACK_Msk /*!<Acknowledge Enable */
12638 #define I2C_CR1_POS_Pos (11U)
12639 #define I2C_CR1_POS_Msk (0x1U << I2C_CR1_POS_Pos) /*!< 0x00000800 */
12640 #define I2C_CR1_POS I2C_CR1_POS_Msk /*!<Acknowledge/PEC Position (for data reception) */
12641 #define I2C_CR1_PEC_Pos (12U)
12642 #define I2C_CR1_PEC_Msk (0x1U << I2C_CR1_PEC_Pos) /*!< 0x00001000 */
12643 #define I2C_CR1_PEC I2C_CR1_PEC_Msk /*!<Packet Error Checking */
12644 #define I2C_CR1_ALERT_Pos (13U)
12645 #define I2C_CR1_ALERT_Msk (0x1U << I2C_CR1_ALERT_Pos) /*!< 0x00002000 */
12646 #define I2C_CR1_ALERT I2C_CR1_ALERT_Msk /*!<SMBus Alert */
12647 #define I2C_CR1_SWRST_Pos (15U)
12648 #define I2C_CR1_SWRST_Msk (0x1U << I2C_CR1_SWRST_Pos) /*!< 0x00008000 */
12649 #define I2C_CR1_SWRST I2C_CR1_SWRST_Msk /*!<Software Reset */
12650
12651 /******************* Bit definition for I2C_CR2 register ********************/
12652 #define I2C_CR2_FREQ_Pos (0U)
12653 #define I2C_CR2_FREQ_Msk (0x3FU << I2C_CR2_FREQ_Pos) /*!< 0x0000003F */
12654 #define I2C_CR2_FREQ I2C_CR2_FREQ_Msk /*!<FREQ[5:0] bits (Peripheral Clock Frequency) */
12655 #define I2C_CR2_FREQ_0 (0x01U << I2C_CR2_FREQ_Pos) /*!< 0x00000001 */
12656 #define I2C_CR2_FREQ_1 (0x02U << I2C_CR2_FREQ_Pos) /*!< 0x00000002 */
12657 #define I2C_CR2_FREQ_2 (0x04U << I2C_CR2_FREQ_Pos) /*!< 0x00000004 */
12658 #define I2C_CR2_FREQ_3 (0x08U << I2C_CR2_FREQ_Pos) /*!< 0x00000008 */
12659 #define I2C_CR2_FREQ_4 (0x10U << I2C_CR2_FREQ_Pos) /*!< 0x00000010 */
12660 #define I2C_CR2_FREQ_5 (0x20U << I2C_CR2_FREQ_Pos) /*!< 0x00000020 */
12661
12662 #define I2C_CR2_ITERREN_Pos (8U)
12663 #define I2C_CR2_ITERREN_Msk (0x1U << I2C_CR2_ITERREN_Pos) /*!< 0x00000100 */
12664 #define I2C_CR2_ITERREN I2C_CR2_ITERREN_Msk /*!<Error Interrupt Enable */
12665 #define I2C_CR2_ITEVTEN_Pos (9U)
12666 #define I2C_CR2_ITEVTEN_Msk (0x1U << I2C_CR2_ITEVTEN_Pos) /*!< 0x00000200 */
12667 #define I2C_CR2_ITEVTEN I2C_CR2_ITEVTEN_Msk /*!<Event Interrupt Enable */
12668 #define I2C_CR2_ITBUFEN_Pos (10U)
12669 #define I2C_CR2_ITBUFEN_Msk (0x1U << I2C_CR2_ITBUFEN_Pos) /*!< 0x00000400 */
12670 #define I2C_CR2_ITBUFEN I2C_CR2_ITBUFEN_Msk /*!<Buffer Interrupt Enable */
12671 #define I2C_CR2_DMAEN_Pos (11U)
12672 #define I2C_CR2_DMAEN_Msk (0x1U << I2C_CR2_DMAEN_Pos) /*!< 0x00000800 */
12673 #define I2C_CR2_DMAEN I2C_CR2_DMAEN_Msk /*!<DMA Requests Enable */
12674 #define I2C_CR2_LAST_Pos (12U)
12675 #define I2C_CR2_LAST_Msk (0x1U << I2C_CR2_LAST_Pos) /*!< 0x00001000 */
12676 #define I2C_CR2_LAST I2C_CR2_LAST_Msk /*!<DMA Last Transfer */
12677
12678 /******************* Bit definition for I2C_OAR1 register *******************/
12679 #define I2C_OAR1_ADD1_7 0x000000FEU /*!<Interface Address */
12680 #define I2C_OAR1_ADD8_9 0x00000300U /*!<Interface Address */
12681
12682 #define I2C_OAR1_ADD0_Pos (0U)
12683 #define I2C_OAR1_ADD0_Msk (0x1U << I2C_OAR1_ADD0_Pos) /*!< 0x00000001 */
12684 #define I2C_OAR1_ADD0 I2C_OAR1_ADD0_Msk /*!<Bit 0 */
12685 #define I2C_OAR1_ADD1_Pos (1U)
12686 #define I2C_OAR1_ADD1_Msk (0x1U << I2C_OAR1_ADD1_Pos) /*!< 0x00000002 */
12687 #define I2C_OAR1_ADD1 I2C_OAR1_ADD1_Msk /*!<Bit 1 */
12688 #define I2C_OAR1_ADD2_Pos (2U)
12689 #define I2C_OAR1_ADD2_Msk (0x1U << I2C_OAR1_ADD2_Pos) /*!< 0x00000004 */
12690 #define I2C_OAR1_ADD2 I2C_OAR1_ADD2_Msk /*!<Bit 2 */
12691 #define I2C_OAR1_ADD3_Pos (3U)
12692 #define I2C_OAR1_ADD3_Msk (0x1U << I2C_OAR1_ADD3_Pos) /*!< 0x00000008 */
12693 #define I2C_OAR1_ADD3 I2C_OAR1_ADD3_Msk /*!<Bit 3 */
12694 #define I2C_OAR1_ADD4_Pos (4U)
12695 #define I2C_OAR1_ADD4_Msk (0x1U << I2C_OAR1_ADD4_Pos) /*!< 0x00000010 */
12696 #define I2C_OAR1_ADD4 I2C_OAR1_ADD4_Msk /*!<Bit 4 */
12697 #define I2C_OAR1_ADD5_Pos (5U)
12698 #define I2C_OAR1_ADD5_Msk (0x1U << I2C_OAR1_ADD5_Pos) /*!< 0x00000020 */
12699 #define I2C_OAR1_ADD5 I2C_OAR1_ADD5_Msk /*!<Bit 5 */
12700 #define I2C_OAR1_ADD6_Pos (6U)
12701 #define I2C_OAR1_ADD6_Msk (0x1U << I2C_OAR1_ADD6_Pos) /*!< 0x00000040 */
12702 #define I2C_OAR1_ADD6 I2C_OAR1_ADD6_Msk /*!<Bit 6 */
12703 #define I2C_OAR1_ADD7_Pos (7U)
12704 #define I2C_OAR1_ADD7_Msk (0x1U << I2C_OAR1_ADD7_Pos) /*!< 0x00000080 */
12705 #define I2C_OAR1_ADD7 I2C_OAR1_ADD7_Msk /*!<Bit 7 */
12706 #define I2C_OAR1_ADD8_Pos (8U)
12707 #define I2C_OAR1_ADD8_Msk (0x1U << I2C_OAR1_ADD8_Pos) /*!< 0x00000100 */
12708 #define I2C_OAR1_ADD8 I2C_OAR1_ADD8_Msk /*!<Bit 8 */
12709 #define I2C_OAR1_ADD9_Pos (9U)
12710 #define I2C_OAR1_ADD9_Msk (0x1U << I2C_OAR1_ADD9_Pos) /*!< 0x00000200 */
12711 #define I2C_OAR1_ADD9 I2C_OAR1_ADD9_Msk /*!<Bit 9 */
12712
12713 #define I2C_OAR1_ADDMODE_Pos (15U)
12714 #define I2C_OAR1_ADDMODE_Msk (0x1U << I2C_OAR1_ADDMODE_Pos) /*!< 0x00008000 */
12715 #define I2C_OAR1_ADDMODE I2C_OAR1_ADDMODE_Msk /*!<Addressing Mode (Slave mode) */
12716
12717 /******************* Bit definition for I2C_OAR2 register *******************/
12718 #define I2C_OAR2_ENDUAL_Pos (0U)
12719 #define I2C_OAR2_ENDUAL_Msk (0x1U << I2C_OAR2_ENDUAL_Pos) /*!< 0x00000001 */
12720 #define I2C_OAR2_ENDUAL I2C_OAR2_ENDUAL_Msk /*!<Dual addressing mode enable */
12721 #define I2C_OAR2_ADD2_Pos (1U)
12722 #define I2C_OAR2_ADD2_Msk (0x7FU << I2C_OAR2_ADD2_Pos) /*!< 0x000000FE */
12723 #define I2C_OAR2_ADD2 I2C_OAR2_ADD2_Msk /*!<Interface address */
12724
12725 /******************** Bit definition for I2C_DR register ********************/
12726 #define I2C_DR_DR_Pos (0U)
12727 #define I2C_DR_DR_Msk (0xFFU << I2C_DR_DR_Pos) /*!< 0x000000FF */
12728 #define I2C_DR_DR I2C_DR_DR_Msk /*!<8-bit Data Register */
12729
12730 /******************* Bit definition for I2C_SR1 register ********************/
12731 #define I2C_SR1_SB_Pos (0U)
12732 #define I2C_SR1_SB_Msk (0x1U << I2C_SR1_SB_Pos) /*!< 0x00000001 */
12733 #define I2C_SR1_SB I2C_SR1_SB_Msk /*!<Start Bit (Master mode) */
12734 #define I2C_SR1_ADDR_Pos (1U)
12735 #define I2C_SR1_ADDR_Msk (0x1U << I2C_SR1_ADDR_Pos) /*!< 0x00000002 */
12736 #define I2C_SR1_ADDR I2C_SR1_ADDR_Msk /*!<Address sent (master mode)/matched (slave mode) */
12737 #define I2C_SR1_BTF_Pos (2U)
12738 #define I2C_SR1_BTF_Msk (0x1U << I2C_SR1_BTF_Pos) /*!< 0x00000004 */
12739 #define I2C_SR1_BTF I2C_SR1_BTF_Msk /*!<Byte Transfer Finished */
12740 #define I2C_SR1_ADD10_Pos (3U)
12741 #define I2C_SR1_ADD10_Msk (0x1U << I2C_SR1_ADD10_Pos) /*!< 0x00000008 */
12742 #define I2C_SR1_ADD10 I2C_SR1_ADD10_Msk /*!<10-bit header sent (Master mode) */
12743 #define I2C_SR1_STOPF_Pos (4U)
12744 #define I2C_SR1_STOPF_Msk (0x1U << I2C_SR1_STOPF_Pos) /*!< 0x00000010 */
12745 #define I2C_SR1_STOPF I2C_SR1_STOPF_Msk /*!<Stop detection (Slave mode) */
12746 #define I2C_SR1_RXNE_Pos (6U)
12747 #define I2C_SR1_RXNE_Msk (0x1U << I2C_SR1_RXNE_Pos) /*!< 0x00000040 */
12748 #define I2C_SR1_RXNE I2C_SR1_RXNE_Msk /*!<Data Register not Empty (receivers) */
12749 #define I2C_SR1_TXE_Pos (7U)
12750 #define I2C_SR1_TXE_Msk (0x1U << I2C_SR1_TXE_Pos) /*!< 0x00000080 */
12751 #define I2C_SR1_TXE I2C_SR1_TXE_Msk /*!<Data Register Empty (transmitters) */
12752 #define I2C_SR1_BERR_Pos (8U)
12753 #define I2C_SR1_BERR_Msk (0x1U << I2C_SR1_BERR_Pos) /*!< 0x00000100 */
12754 #define I2C_SR1_BERR I2C_SR1_BERR_Msk /*!<Bus Error */
12755 #define I2C_SR1_ARLO_Pos (9U)
12756 #define I2C_SR1_ARLO_Msk (0x1U << I2C_SR1_ARLO_Pos) /*!< 0x00000200 */
12757 #define I2C_SR1_ARLO I2C_SR1_ARLO_Msk /*!<Arbitration Lost (master mode) */
12758 #define I2C_SR1_AF_Pos (10U)
12759 #define I2C_SR1_AF_Msk (0x1U << I2C_SR1_AF_Pos) /*!< 0x00000400 */
12760 #define I2C_SR1_AF I2C_SR1_AF_Msk /*!<Acknowledge Failure */
12761 #define I2C_SR1_OVR_Pos (11U)
12762 #define I2C_SR1_OVR_Msk (0x1U << I2C_SR1_OVR_Pos) /*!< 0x00000800 */
12763 #define I2C_SR1_OVR I2C_SR1_OVR_Msk /*!<Overrun/Underrun */
12764 #define I2C_SR1_PECERR_Pos (12U)
12765 #define I2C_SR1_PECERR_Msk (0x1U << I2C_SR1_PECERR_Pos) /*!< 0x00001000 */
12766 #define I2C_SR1_PECERR I2C_SR1_PECERR_Msk /*!<PEC Error in reception */
12767 #define I2C_SR1_TIMEOUT_Pos (14U)
12768 #define I2C_SR1_TIMEOUT_Msk (0x1U << I2C_SR1_TIMEOUT_Pos) /*!< 0x00004000 */
12769 #define I2C_SR1_TIMEOUT I2C_SR1_TIMEOUT_Msk /*!<Timeout or Tlow Error */
12770 #define I2C_SR1_SMBALERT_Pos (15U)
12771 #define I2C_SR1_SMBALERT_Msk (0x1U << I2C_SR1_SMBALERT_Pos) /*!< 0x00008000 */
12772 #define I2C_SR1_SMBALERT I2C_SR1_SMBALERT_Msk /*!<SMBus Alert */
12773
12774 /******************* Bit definition for I2C_SR2 register ********************/
12775 #define I2C_SR2_MSL_Pos (0U)
12776 #define I2C_SR2_MSL_Msk (0x1U << I2C_SR2_MSL_Pos) /*!< 0x00000001 */
12777 #define I2C_SR2_MSL I2C_SR2_MSL_Msk /*!<Master/Slave */
12778 #define I2C_SR2_BUSY_Pos (1U)
12779 #define I2C_SR2_BUSY_Msk (0x1U << I2C_SR2_BUSY_Pos) /*!< 0x00000002 */
12780 #define I2C_SR2_BUSY I2C_SR2_BUSY_Msk /*!<Bus Busy */
12781 #define I2C_SR2_TRA_Pos (2U)
12782 #define I2C_SR2_TRA_Msk (0x1U << I2C_SR2_TRA_Pos) /*!< 0x00000004 */
12783 #define I2C_SR2_TRA I2C_SR2_TRA_Msk /*!<Transmitter/Receiver */
12784 #define I2C_SR2_GENCALL_Pos (4U)
12785 #define I2C_SR2_GENCALL_Msk (0x1U << I2C_SR2_GENCALL_Pos) /*!< 0x00000010 */
12786 #define I2C_SR2_GENCALL I2C_SR2_GENCALL_Msk /*!<General Call Address (Slave mode) */
12787 #define I2C_SR2_SMBDEFAULT_Pos (5U)
12788 #define I2C_SR2_SMBDEFAULT_Msk (0x1U << I2C_SR2_SMBDEFAULT_Pos) /*!< 0x00000020 */
12789 #define I2C_SR2_SMBDEFAULT I2C_SR2_SMBDEFAULT_Msk /*!<SMBus Device Default Address (Slave mode) */
12790 #define I2C_SR2_SMBHOST_Pos (6U)
12791 #define I2C_SR2_SMBHOST_Msk (0x1U << I2C_SR2_SMBHOST_Pos) /*!< 0x00000040 */
12792 #define I2C_SR2_SMBHOST I2C_SR2_SMBHOST_Msk /*!<SMBus Host Header (Slave mode) */
12793 #define I2C_SR2_DUALF_Pos (7U)
12794 #define I2C_SR2_DUALF_Msk (0x1U << I2C_SR2_DUALF_Pos) /*!< 0x00000080 */
12795 #define I2C_SR2_DUALF I2C_SR2_DUALF_Msk /*!<Dual Flag (Slave mode) */
12796 #define I2C_SR2_PEC_Pos (8U)
12797 #define I2C_SR2_PEC_Msk (0xFFU << I2C_SR2_PEC_Pos) /*!< 0x0000FF00 */
12798 #define I2C_SR2_PEC I2C_SR2_PEC_Msk /*!<Packet Error Checking Register */
12799
12800 /******************* Bit definition for I2C_CCR register ********************/
12801 #define I2C_CCR_CCR_Pos (0U)
12802 #define I2C_CCR_CCR_Msk (0xFFFU << I2C_CCR_CCR_Pos) /*!< 0x00000FFF */
12803 #define I2C_CCR_CCR I2C_CCR_CCR_Msk /*!<Clock Control Register in Fast/Standard mode (Master mode) */
12804 #define I2C_CCR_DUTY_Pos (14U)
12805 #define I2C_CCR_DUTY_Msk (0x1U << I2C_CCR_DUTY_Pos) /*!< 0x00004000 */
12806 #define I2C_CCR_DUTY I2C_CCR_DUTY_Msk /*!<Fast Mode Duty Cycle */
12807 #define I2C_CCR_FS_Pos (15U)
12808 #define I2C_CCR_FS_Msk (0x1U << I2C_CCR_FS_Pos) /*!< 0x00008000 */
12809 #define I2C_CCR_FS I2C_CCR_FS_Msk /*!<I2C Master Mode Selection */
12810
12811 /****************** Bit definition for I2C_TRISE register *******************/
12812 #define I2C_TRISE_TRISE_Pos (0U)
12813 #define I2C_TRISE_TRISE_Msk (0x3FU << I2C_TRISE_TRISE_Pos) /*!< 0x0000003F */
12814 #define I2C_TRISE_TRISE I2C_TRISE_TRISE_Msk /*!<Maximum Rise Time in Fast/Standard mode (Master mode) */
12815
12816 /****************** Bit definition for I2C_FLTR register *******************/
12817 #define I2C_FLTR_DNF_Pos (0U)
12818 #define I2C_FLTR_DNF_Msk (0xFU << I2C_FLTR_DNF_Pos) /*!< 0x0000000F */
12819 #define I2C_FLTR_DNF I2C_FLTR_DNF_Msk /*!<Digital Noise Filter */
12820 #define I2C_FLTR_ANOFF_Pos (4U)
12821 #define I2C_FLTR_ANOFF_Msk (0x1U << I2C_FLTR_ANOFF_Pos) /*!< 0x00000010 */
12822 #define I2C_FLTR_ANOFF I2C_FLTR_ANOFF_Msk /*!<Analog Noise Filter OFF */
12823
12824 /******************************************************************************/
12825 /* */
12826 /* Independent WATCHDOG */
12827 /* */
12828 /******************************************************************************/
12829 /******************* Bit definition for IWDG_KR register ********************/
12830 #define IWDG_KR_KEY_Pos (0U)
12831 #define IWDG_KR_KEY_Msk (0xFFFFU << IWDG_KR_KEY_Pos) /*!< 0x0000FFFF */
12832 #define IWDG_KR_KEY IWDG_KR_KEY_Msk /*!<Key value (write only, read 0000h) */
12833
12834 /******************* Bit definition for IWDG_PR register ********************/
12835 #define IWDG_PR_PR_Pos (0U)
12836 #define IWDG_PR_PR_Msk (0x7U << IWDG_PR_PR_Pos) /*!< 0x00000007 */
12837 #define IWDG_PR_PR IWDG_PR_PR_Msk /*!<PR[2:0] (Prescaler divider) */
12838 #define IWDG_PR_PR_0 (0x1U << IWDG_PR_PR_Pos) /*!< 0x01 */
12839 #define IWDG_PR_PR_1 (0x2U << IWDG_PR_PR_Pos) /*!< 0x02 */
12840 #define IWDG_PR_PR_2 (0x4U << IWDG_PR_PR_Pos) /*!< 0x04 */
12841
12842 /******************* Bit definition for IWDG_RLR register *******************/
12843 #define IWDG_RLR_RL_Pos (0U)
12844 #define IWDG_RLR_RL_Msk (0xFFFU << IWDG_RLR_RL_Pos) /*!< 0x00000FFF */
12845 #define IWDG_RLR_RL IWDG_RLR_RL_Msk /*!<Watchdog counter reload value */
12846
12847 /******************* Bit definition for IWDG_SR register ********************/
12848 #define IWDG_SR_PVU_Pos (0U)
12849 #define IWDG_SR_PVU_Msk (0x1U << IWDG_SR_PVU_Pos) /*!< 0x00000001 */
12850 #define IWDG_SR_PVU IWDG_SR_PVU_Msk /*!<Watchdog prescaler value update */
12851 #define IWDG_SR_RVU_Pos (1U)
12852 #define IWDG_SR_RVU_Msk (0x1U << IWDG_SR_RVU_Pos) /*!< 0x00000002 */
12853 #define IWDG_SR_RVU IWDG_SR_RVU_Msk /*!<Watchdog counter reload value update */
12854
12855
12856 /******************************************************************************/
12857 /* */
12858 /* LCD-TFT Display Controller (LTDC) */
12859 /* */
12860 /******************************************************************************/
12861
12862 /******************** Bit definition for LTDC_SSCR register *****************/
12863
12864 #define LTDC_SSCR_VSH_Pos (0U)
12865 #define LTDC_SSCR_VSH_Msk (0x7FFU << LTDC_SSCR_VSH_Pos) /*!< 0x000007FF */
12866 #define LTDC_SSCR_VSH LTDC_SSCR_VSH_Msk /*!< Vertical Synchronization Height */
12867 #define LTDC_SSCR_HSW_Pos (16U)
12868 #define LTDC_SSCR_HSW_Msk (0xFFFU << LTDC_SSCR_HSW_Pos) /*!< 0x0FFF0000 */
12869 #define LTDC_SSCR_HSW LTDC_SSCR_HSW_Msk /*!< Horizontal Synchronization Width */
12870
12871 /******************** Bit definition for LTDC_BPCR register *****************/
12872
12873 #define LTDC_BPCR_AVBP_Pos (0U)
12874 #define LTDC_BPCR_AVBP_Msk (0x7FFU << LTDC_BPCR_AVBP_Pos) /*!< 0x000007FF */
12875 #define LTDC_BPCR_AVBP LTDC_BPCR_AVBP_Msk /*!< Accumulated Vertical Back Porch */
12876 #define LTDC_BPCR_AHBP_Pos (16U)
12877 #define LTDC_BPCR_AHBP_Msk (0xFFFU << LTDC_BPCR_AHBP_Pos) /*!< 0x0FFF0000 */
12878 #define LTDC_BPCR_AHBP LTDC_BPCR_AHBP_Msk /*!< Accumulated Horizontal Back Porch */
12879
12880 /******************** Bit definition for LTDC_AWCR register *****************/
12881
12882 #define LTDC_AWCR_AAH_Pos (0U)
12883 #define LTDC_AWCR_AAH_Msk (0x7FFU << LTDC_AWCR_AAH_Pos) /*!< 0x000007FF */
12884 #define LTDC_AWCR_AAH LTDC_AWCR_AAH_Msk /*!< Accumulated Active heigh */
12885 #define LTDC_AWCR_AAW_Pos (16U)
12886 #define LTDC_AWCR_AAW_Msk (0xFFFU << LTDC_AWCR_AAW_Pos) /*!< 0x0FFF0000 */
12887 #define LTDC_AWCR_AAW LTDC_AWCR_AAW_Msk /*!< Accumulated Active Width */
12888
12889 /******************** Bit definition for LTDC_TWCR register *****************/
12890
12891 #define LTDC_TWCR_TOTALH_Pos (0U)
12892 #define LTDC_TWCR_TOTALH_Msk (0x7FFU << LTDC_TWCR_TOTALH_Pos) /*!< 0x000007FF */
12893 #define LTDC_TWCR_TOTALH LTDC_TWCR_TOTALH_Msk /*!< Total Heigh */
12894 #define LTDC_TWCR_TOTALW_Pos (16U)
12895 #define LTDC_TWCR_TOTALW_Msk (0xFFFU << LTDC_TWCR_TOTALW_Pos) /*!< 0x0FFF0000 */
12896 #define LTDC_TWCR_TOTALW LTDC_TWCR_TOTALW_Msk /*!< Total Width */
12897
12898 /******************** Bit definition for LTDC_GCR register ******************/
12899
12900 #define LTDC_GCR_LTDCEN_Pos (0U)
12901 #define LTDC_GCR_LTDCEN_Msk (0x1U << LTDC_GCR_LTDCEN_Pos) /*!< 0x00000001 */
12902 #define LTDC_GCR_LTDCEN LTDC_GCR_LTDCEN_Msk /*!< LCD-TFT controller enable bit */
12903 #define LTDC_GCR_DBW_Pos (4U)
12904 #define LTDC_GCR_DBW_Msk (0x7U << LTDC_GCR_DBW_Pos) /*!< 0x00000070 */
12905 #define LTDC_GCR_DBW LTDC_GCR_DBW_Msk /*!< Dither Blue Width */
12906 #define LTDC_GCR_DGW_Pos (8U)
12907 #define LTDC_GCR_DGW_Msk (0x7U << LTDC_GCR_DGW_Pos) /*!< 0x00000700 */
12908 #define LTDC_GCR_DGW LTDC_GCR_DGW_Msk /*!< Dither Green Width */
12909 #define LTDC_GCR_DRW_Pos (12U)
12910 #define LTDC_GCR_DRW_Msk (0x7U << LTDC_GCR_DRW_Pos) /*!< 0x00007000 */
12911 #define LTDC_GCR_DRW LTDC_GCR_DRW_Msk /*!< Dither Red Width */
12912 #define LTDC_GCR_DEN_Pos (16U)
12913 #define LTDC_GCR_DEN_Msk (0x1U << LTDC_GCR_DEN_Pos) /*!< 0x00010000 */
12914 #define LTDC_GCR_DEN LTDC_GCR_DEN_Msk /*!< Dither Enable */
12915 #define LTDC_GCR_PCPOL_Pos (28U)
12916 #define LTDC_GCR_PCPOL_Msk (0x1U << LTDC_GCR_PCPOL_Pos) /*!< 0x10000000 */
12917 #define LTDC_GCR_PCPOL LTDC_GCR_PCPOL_Msk /*!< Pixel Clock Polarity */
12918 #define LTDC_GCR_DEPOL_Pos (29U)
12919 #define LTDC_GCR_DEPOL_Msk (0x1U << LTDC_GCR_DEPOL_Pos) /*!< 0x20000000 */
12920 #define LTDC_GCR_DEPOL LTDC_GCR_DEPOL_Msk /*!< Data Enable Polarity */
12921 #define LTDC_GCR_VSPOL_Pos (30U)
12922 #define LTDC_GCR_VSPOL_Msk (0x1U << LTDC_GCR_VSPOL_Pos) /*!< 0x40000000 */
12923 #define LTDC_GCR_VSPOL LTDC_GCR_VSPOL_Msk /*!< Vertical Synchronization Polarity */
12924 #define LTDC_GCR_HSPOL_Pos (31U)
12925 #define LTDC_GCR_HSPOL_Msk (0x1U << LTDC_GCR_HSPOL_Pos) /*!< 0x80000000 */
12926 #define LTDC_GCR_HSPOL LTDC_GCR_HSPOL_Msk /*!< Horizontal Synchronization Polarity */
12927
12928 /* Legacy defines */
12929 #define LTDC_GCR_DTEN LTDC_GCR_DEN
12930
12931 /******************** Bit definition for LTDC_SRCR register *****************/
12932
12933 #define LTDC_SRCR_IMR_Pos (0U)
12934 #define LTDC_SRCR_IMR_Msk (0x1U << LTDC_SRCR_IMR_Pos) /*!< 0x00000001 */
12935 #define LTDC_SRCR_IMR LTDC_SRCR_IMR_Msk /*!< Immediate Reload */
12936 #define LTDC_SRCR_VBR_Pos (1U)
12937 #define LTDC_SRCR_VBR_Msk (0x1U << LTDC_SRCR_VBR_Pos) /*!< 0x00000002 */
12938 #define LTDC_SRCR_VBR LTDC_SRCR_VBR_Msk /*!< Vertical Blanking Reload */
12939
12940 /******************** Bit definition for LTDC_BCCR register *****************/
12941
12942 #define LTDC_BCCR_BCBLUE_Pos (0U)
12943 #define LTDC_BCCR_BCBLUE_Msk (0xFFU << LTDC_BCCR_BCBLUE_Pos) /*!< 0x000000FF */
12944 #define LTDC_BCCR_BCBLUE LTDC_BCCR_BCBLUE_Msk /*!< Background Blue value */
12945 #define LTDC_BCCR_BCGREEN_Pos (8U)
12946 #define LTDC_BCCR_BCGREEN_Msk (0xFFU << LTDC_BCCR_BCGREEN_Pos) /*!< 0x0000FF00 */
12947 #define LTDC_BCCR_BCGREEN LTDC_BCCR_BCGREEN_Msk /*!< Background Green value */
12948 #define LTDC_BCCR_BCRED_Pos (16U)
12949 #define LTDC_BCCR_BCRED_Msk (0xFFU << LTDC_BCCR_BCRED_Pos) /*!< 0x00FF0000 */
12950 #define LTDC_BCCR_BCRED LTDC_BCCR_BCRED_Msk /*!< Background Red value */
12951
12952 /******************** Bit definition for LTDC_IER register ******************/
12953
12954 #define LTDC_IER_LIE_Pos (0U)
12955 #define LTDC_IER_LIE_Msk (0x1U << LTDC_IER_LIE_Pos) /*!< 0x00000001 */
12956 #define LTDC_IER_LIE LTDC_IER_LIE_Msk /*!< Line Interrupt Enable */
12957 #define LTDC_IER_FUIE_Pos (1U)
12958 #define LTDC_IER_FUIE_Msk (0x1U << LTDC_IER_FUIE_Pos) /*!< 0x00000002 */
12959 #define LTDC_IER_FUIE LTDC_IER_FUIE_Msk /*!< FIFO Underrun Interrupt Enable */
12960 #define LTDC_IER_TERRIE_Pos (2U)
12961 #define LTDC_IER_TERRIE_Msk (0x1U << LTDC_IER_TERRIE_Pos) /*!< 0x00000004 */
12962 #define LTDC_IER_TERRIE LTDC_IER_TERRIE_Msk /*!< Transfer Error Interrupt Enable */
12963 #define LTDC_IER_RRIE_Pos (3U)
12964 #define LTDC_IER_RRIE_Msk (0x1U << LTDC_IER_RRIE_Pos) /*!< 0x00000008 */
12965 #define LTDC_IER_RRIE LTDC_IER_RRIE_Msk /*!< Register Reload interrupt enable */
12966
12967 /******************** Bit definition for LTDC_ISR register ******************/
12968
12969 #define LTDC_ISR_LIF_Pos (0U)
12970 #define LTDC_ISR_LIF_Msk (0x1U << LTDC_ISR_LIF_Pos) /*!< 0x00000001 */
12971 #define LTDC_ISR_LIF LTDC_ISR_LIF_Msk /*!< Line Interrupt Flag */
12972 #define LTDC_ISR_FUIF_Pos (1U)
12973 #define LTDC_ISR_FUIF_Msk (0x1U << LTDC_ISR_FUIF_Pos) /*!< 0x00000002 */
12974 #define LTDC_ISR_FUIF LTDC_ISR_FUIF_Msk /*!< FIFO Underrun Interrupt Flag */
12975 #define LTDC_ISR_TERRIF_Pos (2U)
12976 #define LTDC_ISR_TERRIF_Msk (0x1U << LTDC_ISR_TERRIF_Pos) /*!< 0x00000004 */
12977 #define LTDC_ISR_TERRIF LTDC_ISR_TERRIF_Msk /*!< Transfer Error Interrupt Flag */
12978 #define LTDC_ISR_RRIF_Pos (3U)
12979 #define LTDC_ISR_RRIF_Msk (0x1U << LTDC_ISR_RRIF_Pos) /*!< 0x00000008 */
12980 #define LTDC_ISR_RRIF LTDC_ISR_RRIF_Msk /*!< Register Reload interrupt Flag */
12981
12982 /******************** Bit definition for LTDC_ICR register ******************/
12983
12984 #define LTDC_ICR_CLIF_Pos (0U)
12985 #define LTDC_ICR_CLIF_Msk (0x1U << LTDC_ICR_CLIF_Pos) /*!< 0x00000001 */
12986 #define LTDC_ICR_CLIF LTDC_ICR_CLIF_Msk /*!< Clears the Line Interrupt Flag */
12987 #define LTDC_ICR_CFUIF_Pos (1U)
12988 #define LTDC_ICR_CFUIF_Msk (0x1U << LTDC_ICR_CFUIF_Pos) /*!< 0x00000002 */
12989 #define LTDC_ICR_CFUIF LTDC_ICR_CFUIF_Msk /*!< Clears the FIFO Underrun Interrupt Flag */
12990 #define LTDC_ICR_CTERRIF_Pos (2U)
12991 #define LTDC_ICR_CTERRIF_Msk (0x1U << LTDC_ICR_CTERRIF_Pos) /*!< 0x00000004 */
12992 #define LTDC_ICR_CTERRIF LTDC_ICR_CTERRIF_Msk /*!< Clears the Transfer Error Interrupt Flag */
12993 #define LTDC_ICR_CRRIF_Pos (3U)
12994 #define LTDC_ICR_CRRIF_Msk (0x1U << LTDC_ICR_CRRIF_Pos) /*!< 0x00000008 */
12995 #define LTDC_ICR_CRRIF LTDC_ICR_CRRIF_Msk /*!< Clears Register Reload interrupt Flag */
12996
12997 /******************** Bit definition for LTDC_LIPCR register ****************/
12998
12999 #define LTDC_LIPCR_LIPOS_Pos (0U)
13000 #define LTDC_LIPCR_LIPOS_Msk (0x7FFU << LTDC_LIPCR_LIPOS_Pos) /*!< 0x000007FF */
13001 #define LTDC_LIPCR_LIPOS LTDC_LIPCR_LIPOS_Msk /*!< Line Interrupt Position */
13002
13003 /******************** Bit definition for LTDC_CPSR register *****************/
13004
13005 #define LTDC_CPSR_CYPOS_Pos (0U)
13006 #define LTDC_CPSR_CYPOS_Msk (0xFFFFU << LTDC_CPSR_CYPOS_Pos) /*!< 0x0000FFFF */
13007 #define LTDC_CPSR_CYPOS LTDC_CPSR_CYPOS_Msk /*!< Current Y Position */
13008 #define LTDC_CPSR_CXPOS_Pos (16U)
13009 #define LTDC_CPSR_CXPOS_Msk (0xFFFFU << LTDC_CPSR_CXPOS_Pos) /*!< 0xFFFF0000 */
13010 #define LTDC_CPSR_CXPOS LTDC_CPSR_CXPOS_Msk /*!< Current X Position */
13011
13012 /******************** Bit definition for LTDC_CDSR register *****************/
13013
13014 #define LTDC_CDSR_VDES_Pos (0U)
13015 #define LTDC_CDSR_VDES_Msk (0x1U << LTDC_CDSR_VDES_Pos) /*!< 0x00000001 */
13016 #define LTDC_CDSR_VDES LTDC_CDSR_VDES_Msk /*!< Vertical Data Enable Status */
13017 #define LTDC_CDSR_HDES_Pos (1U)
13018 #define LTDC_CDSR_HDES_Msk (0x1U << LTDC_CDSR_HDES_Pos) /*!< 0x00000002 */
13019 #define LTDC_CDSR_HDES LTDC_CDSR_HDES_Msk /*!< Horizontal Data Enable Status */
13020 #define LTDC_CDSR_VSYNCS_Pos (2U)
13021 #define LTDC_CDSR_VSYNCS_Msk (0x1U << LTDC_CDSR_VSYNCS_Pos) /*!< 0x00000004 */
13022 #define LTDC_CDSR_VSYNCS LTDC_CDSR_VSYNCS_Msk /*!< Vertical Synchronization Status */
13023 #define LTDC_CDSR_HSYNCS_Pos (3U)
13024 #define LTDC_CDSR_HSYNCS_Msk (0x1U << LTDC_CDSR_HSYNCS_Pos) /*!< 0x00000008 */
13025 #define LTDC_CDSR_HSYNCS LTDC_CDSR_HSYNCS_Msk /*!< Horizontal Synchronization Status */
13026
13027 /******************** Bit definition for LTDC_LxCR register *****************/
13028
13029 #define LTDC_LxCR_LEN_Pos (0U)
13030 #define LTDC_LxCR_LEN_Msk (0x1U << LTDC_LxCR_LEN_Pos) /*!< 0x00000001 */
13031 #define LTDC_LxCR_LEN LTDC_LxCR_LEN_Msk /*!< Layer Enable */
13032 #define LTDC_LxCR_COLKEN_Pos (1U)
13033 #define LTDC_LxCR_COLKEN_Msk (0x1U << LTDC_LxCR_COLKEN_Pos) /*!< 0x00000002 */
13034 #define LTDC_LxCR_COLKEN LTDC_LxCR_COLKEN_Msk /*!< Color Keying Enable */
13035 #define LTDC_LxCR_CLUTEN_Pos (4U)
13036 #define LTDC_LxCR_CLUTEN_Msk (0x1U << LTDC_LxCR_CLUTEN_Pos) /*!< 0x00000010 */
13037 #define LTDC_LxCR_CLUTEN LTDC_LxCR_CLUTEN_Msk /*!< Color Lockup Table Enable */
13038
13039 /******************** Bit definition for LTDC_LxWHPCR register **************/
13040
13041 #define LTDC_LxWHPCR_WHSTPOS_Pos (0U)
13042 #define LTDC_LxWHPCR_WHSTPOS_Msk (0xFFFU << LTDC_LxWHPCR_WHSTPOS_Pos) /*!< 0x00000FFF */
13043 #define LTDC_LxWHPCR_WHSTPOS LTDC_LxWHPCR_WHSTPOS_Msk /*!< Window Horizontal Start Position */
13044 #define LTDC_LxWHPCR_WHSPPOS_Pos (16U)
13045 #define LTDC_LxWHPCR_WHSPPOS_Msk (0xFFFFU << LTDC_LxWHPCR_WHSPPOS_Pos) /*!< 0xFFFF0000 */
13046 #define LTDC_LxWHPCR_WHSPPOS LTDC_LxWHPCR_WHSPPOS_Msk /*!< Window Horizontal Stop Position */
13047
13048 /******************** Bit definition for LTDC_LxWVPCR register **************/
13049
13050 #define LTDC_LxWVPCR_WVSTPOS_Pos (0U)
13051 #define LTDC_LxWVPCR_WVSTPOS_Msk (0xFFFU << LTDC_LxWVPCR_WVSTPOS_Pos) /*!< 0x00000FFF */
13052 #define LTDC_LxWVPCR_WVSTPOS LTDC_LxWVPCR_WVSTPOS_Msk /*!< Window Vertical Start Position */
13053 #define LTDC_LxWVPCR_WVSPPOS_Pos (16U)
13054 #define LTDC_LxWVPCR_WVSPPOS_Msk (0xFFFFU << LTDC_LxWVPCR_WVSPPOS_Pos) /*!< 0xFFFF0000 */
13055 #define LTDC_LxWVPCR_WVSPPOS LTDC_LxWVPCR_WVSPPOS_Msk /*!< Window Vertical Stop Position */
13056
13057 /******************** Bit definition for LTDC_LxCKCR register ***************/
13058
13059 #define LTDC_LxCKCR_CKBLUE_Pos (0U)
13060 #define LTDC_LxCKCR_CKBLUE_Msk (0xFFU << LTDC_LxCKCR_CKBLUE_Pos) /*!< 0x000000FF */
13061 #define LTDC_LxCKCR_CKBLUE LTDC_LxCKCR_CKBLUE_Msk /*!< Color Key Blue value */
13062 #define LTDC_LxCKCR_CKGREEN_Pos (8U)
13063 #define LTDC_LxCKCR_CKGREEN_Msk (0xFFU << LTDC_LxCKCR_CKGREEN_Pos) /*!< 0x0000FF00 */
13064 #define LTDC_LxCKCR_CKGREEN LTDC_LxCKCR_CKGREEN_Msk /*!< Color Key Green value */
13065 #define LTDC_LxCKCR_CKRED_Pos (16U)
13066 #define LTDC_LxCKCR_CKRED_Msk (0xFFU << LTDC_LxCKCR_CKRED_Pos) /*!< 0x00FF0000 */
13067 #define LTDC_LxCKCR_CKRED LTDC_LxCKCR_CKRED_Msk /*!< Color Key Red value */
13068
13069 /******************** Bit definition for LTDC_LxPFCR register ***************/
13070
13071 #define LTDC_LxPFCR_PF_Pos (0U)
13072 #define LTDC_LxPFCR_PF_Msk (0x7U << LTDC_LxPFCR_PF_Pos) /*!< 0x00000007 */
13073 #define LTDC_LxPFCR_PF LTDC_LxPFCR_PF_Msk /*!< Pixel Format */
13074
13075 /******************** Bit definition for LTDC_LxCACR register ***************/
13076
13077 #define LTDC_LxCACR_CONSTA_Pos (0U)
13078 #define LTDC_LxCACR_CONSTA_Msk (0xFFU << LTDC_LxCACR_CONSTA_Pos) /*!< 0x000000FF */
13079 #define LTDC_LxCACR_CONSTA LTDC_LxCACR_CONSTA_Msk /*!< Constant Alpha */
13080
13081 /******************** Bit definition for LTDC_LxDCCR register ***************/
13082
13083 #define LTDC_LxDCCR_DCBLUE_Pos (0U)
13084 #define LTDC_LxDCCR_DCBLUE_Msk (0xFFU << LTDC_LxDCCR_DCBLUE_Pos) /*!< 0x000000FF */
13085 #define LTDC_LxDCCR_DCBLUE LTDC_LxDCCR_DCBLUE_Msk /*!< Default Color Blue */
13086 #define LTDC_LxDCCR_DCGREEN_Pos (8U)
13087 #define LTDC_LxDCCR_DCGREEN_Msk (0xFFU << LTDC_LxDCCR_DCGREEN_Pos) /*!< 0x0000FF00 */
13088 #define LTDC_LxDCCR_DCGREEN LTDC_LxDCCR_DCGREEN_Msk /*!< Default Color Green */
13089 #define LTDC_LxDCCR_DCRED_Pos (16U)
13090 #define LTDC_LxDCCR_DCRED_Msk (0xFFU << LTDC_LxDCCR_DCRED_Pos) /*!< 0x00FF0000 */
13091 #define LTDC_LxDCCR_DCRED LTDC_LxDCCR_DCRED_Msk /*!< Default Color Red */
13092 #define LTDC_LxDCCR_DCALPHA_Pos (24U)
13093 #define LTDC_LxDCCR_DCALPHA_Msk (0xFFU << LTDC_LxDCCR_DCALPHA_Pos) /*!< 0xFF000000 */
13094 #define LTDC_LxDCCR_DCALPHA LTDC_LxDCCR_DCALPHA_Msk /*!< Default Color Alpha */
13095
13096 /******************** Bit definition for LTDC_LxBFCR register ***************/
13097
13098 #define LTDC_LxBFCR_BF2_Pos (0U)
13099 #define LTDC_LxBFCR_BF2_Msk (0x7U << LTDC_LxBFCR_BF2_Pos) /*!< 0x00000007 */
13100 #define LTDC_LxBFCR_BF2 LTDC_LxBFCR_BF2_Msk /*!< Blending Factor 2 */
13101 #define LTDC_LxBFCR_BF1_Pos (8U)
13102 #define LTDC_LxBFCR_BF1_Msk (0x7U << LTDC_LxBFCR_BF1_Pos) /*!< 0x00000700 */
13103 #define LTDC_LxBFCR_BF1 LTDC_LxBFCR_BF1_Msk /*!< Blending Factor 1 */
13104
13105 /******************** Bit definition for LTDC_LxCFBAR register **************/
13106
13107 #define LTDC_LxCFBAR_CFBADD_Pos (0U)
13108 #define LTDC_LxCFBAR_CFBADD_Msk (0xFFFFFFFFU << LTDC_LxCFBAR_CFBADD_Pos) /*!< 0xFFFFFFFF */
13109 #define LTDC_LxCFBAR_CFBADD LTDC_LxCFBAR_CFBADD_Msk /*!< Color Frame Buffer Start Address */
13110
13111 /******************** Bit definition for LTDC_LxCFBLR register **************/
13112
13113 #define LTDC_LxCFBLR_CFBLL_Pos (0U)
13114 #define LTDC_LxCFBLR_CFBLL_Msk (0x1FFFU << LTDC_LxCFBLR_CFBLL_Pos) /*!< 0x00001FFF */
13115 #define LTDC_LxCFBLR_CFBLL LTDC_LxCFBLR_CFBLL_Msk /*!< Color Frame Buffer Line Length */
13116 #define LTDC_LxCFBLR_CFBP_Pos (16U)
13117 #define LTDC_LxCFBLR_CFBP_Msk (0x1FFFU << LTDC_LxCFBLR_CFBP_Pos) /*!< 0x1FFF0000 */
13118 #define LTDC_LxCFBLR_CFBP LTDC_LxCFBLR_CFBP_Msk /*!< Color Frame Buffer Pitch in bytes */
13119
13120 /******************** Bit definition for LTDC_LxCFBLNR register *************/
13121
13122 #define LTDC_LxCFBLNR_CFBLNBR_Pos (0U)
13123 #define LTDC_LxCFBLNR_CFBLNBR_Msk (0x7FFU << LTDC_LxCFBLNR_CFBLNBR_Pos) /*!< 0x000007FF */
13124 #define LTDC_LxCFBLNR_CFBLNBR LTDC_LxCFBLNR_CFBLNBR_Msk /*!< Frame Buffer Line Number */
13125
13126 /******************** Bit definition for LTDC_LxCLUTWR register *************/
13127
13128 #define LTDC_LxCLUTWR_BLUE_Pos (0U)
13129 #define LTDC_LxCLUTWR_BLUE_Msk (0xFFU << LTDC_LxCLUTWR_BLUE_Pos) /*!< 0x000000FF */
13130 #define LTDC_LxCLUTWR_BLUE LTDC_LxCLUTWR_BLUE_Msk /*!< Blue value */
13131 #define LTDC_LxCLUTWR_GREEN_Pos (8U)
13132 #define LTDC_LxCLUTWR_GREEN_Msk (0xFFU << LTDC_LxCLUTWR_GREEN_Pos) /*!< 0x0000FF00 */
13133 #define LTDC_LxCLUTWR_GREEN LTDC_LxCLUTWR_GREEN_Msk /*!< Green value */
13134 #define LTDC_LxCLUTWR_RED_Pos (16U)
13135 #define LTDC_LxCLUTWR_RED_Msk (0xFFU << LTDC_LxCLUTWR_RED_Pos) /*!< 0x00FF0000 */
13136 #define LTDC_LxCLUTWR_RED LTDC_LxCLUTWR_RED_Msk /*!< Red value */
13137 #define LTDC_LxCLUTWR_CLUTADD_Pos (24U)
13138 #define LTDC_LxCLUTWR_CLUTADD_Msk (0xFFU << LTDC_LxCLUTWR_CLUTADD_Pos) /*!< 0xFF000000 */
13139 #define LTDC_LxCLUTWR_CLUTADD LTDC_LxCLUTWR_CLUTADD_Msk /*!< CLUT address */
13140
13141
13142 /******************************************************************************/
13143 /* */
13144 /* Power Control */
13145 /* */
13146 /******************************************************************************/
13147 /******************** Bit definition for PWR_CR register ********************/
13148 #define PWR_CR_LPDS_Pos (0U)
13149 #define PWR_CR_LPDS_Msk (0x1U << PWR_CR_LPDS_Pos) /*!< 0x00000001 */
13150 #define PWR_CR_LPDS PWR_CR_LPDS_Msk /*!< Low-Power Deepsleep */
13151 #define PWR_CR_PDDS_Pos (1U)
13152 #define PWR_CR_PDDS_Msk (0x1U << PWR_CR_PDDS_Pos) /*!< 0x00000002 */
13153 #define PWR_CR_PDDS PWR_CR_PDDS_Msk /*!< Power Down Deepsleep */
13154 #define PWR_CR_CWUF_Pos (2U)
13155 #define PWR_CR_CWUF_Msk (0x1U << PWR_CR_CWUF_Pos) /*!< 0x00000004 */
13156 #define PWR_CR_CWUF PWR_CR_CWUF_Msk /*!< Clear Wakeup Flag */
13157 #define PWR_CR_CSBF_Pos (3U)
13158 #define PWR_CR_CSBF_Msk (0x1U << PWR_CR_CSBF_Pos) /*!< 0x00000008 */
13159 #define PWR_CR_CSBF PWR_CR_CSBF_Msk /*!< Clear Standby Flag */
13160 #define PWR_CR_PVDE_Pos (4U)
13161 #define PWR_CR_PVDE_Msk (0x1U << PWR_CR_PVDE_Pos) /*!< 0x00000010 */
13162 #define PWR_CR_PVDE PWR_CR_PVDE_Msk /*!< Power Voltage Detector Enable */
13163
13164 #define PWR_CR_PLS_Pos (5U)
13165 #define PWR_CR_PLS_Msk (0x7U << PWR_CR_PLS_Pos) /*!< 0x000000E0 */
13166 #define PWR_CR_PLS PWR_CR_PLS_Msk /*!< PLS[2:0] bits (PVD Level Selection) */
13167 #define PWR_CR_PLS_0 (0x1U << PWR_CR_PLS_Pos) /*!< 0x00000020 */
13168 #define PWR_CR_PLS_1 (0x2U << PWR_CR_PLS_Pos) /*!< 0x00000040 */
13169 #define PWR_CR_PLS_2 (0x4U << PWR_CR_PLS_Pos) /*!< 0x00000080 */
13170
13171 /*!< PVD level configuration */
13172 #define PWR_CR_PLS_LEV0 0x00000000U /*!< PVD level 0 */
13173 #define PWR_CR_PLS_LEV1 0x00000020U /*!< PVD level 1 */
13174 #define PWR_CR_PLS_LEV2 0x00000040U /*!< PVD level 2 */
13175 #define PWR_CR_PLS_LEV3 0x00000060U /*!< PVD level 3 */
13176 #define PWR_CR_PLS_LEV4 0x00000080U /*!< PVD level 4 */
13177 #define PWR_CR_PLS_LEV5 0x000000A0U /*!< PVD level 5 */
13178 #define PWR_CR_PLS_LEV6 0x000000C0U /*!< PVD level 6 */
13179 #define PWR_CR_PLS_LEV7 0x000000E0U /*!< PVD level 7 */
13180 #define PWR_CR_DBP_Pos (8U)
13181 #define PWR_CR_DBP_Msk (0x1U << PWR_CR_DBP_Pos) /*!< 0x00000100 */
13182 #define PWR_CR_DBP PWR_CR_DBP_Msk /*!< Disable Backup Domain write protection */
13183 #define PWR_CR_FPDS_Pos (9U)
13184 #define PWR_CR_FPDS_Msk (0x1U << PWR_CR_FPDS_Pos) /*!< 0x00000200 */
13185 #define PWR_CR_FPDS PWR_CR_FPDS_Msk /*!< Flash power down in Stop mode */
13186 #define PWR_CR_LPLVDS_Pos (10U)
13187 #define PWR_CR_LPLVDS_Msk (0x1U << PWR_CR_LPLVDS_Pos) /*!< 0x00000400 */
13188 #define PWR_CR_LPLVDS PWR_CR_LPLVDS_Msk /*!< Low-Power Regulator Low Voltage Scaling in Stop mode */
13189 #define PWR_CR_MRLVDS_Pos (11U)
13190 #define PWR_CR_MRLVDS_Msk (0x1U << PWR_CR_MRLVDS_Pos) /*!< 0x00000800 */
13191 #define PWR_CR_MRLVDS PWR_CR_MRLVDS_Msk /*!< Main regulator Low Voltage Scaling in Stop mode */
13192 #define PWR_CR_ADCDC1_Pos (13U)
13193 #define PWR_CR_ADCDC1_Msk (0x1U << PWR_CR_ADCDC1_Pos) /*!< 0x00002000 */
13194 #define PWR_CR_ADCDC1 PWR_CR_ADCDC1_Msk /*!< Refer to AN4073 on how to use this bit */
13195 #define PWR_CR_VOS_Pos (14U)
13196 #define PWR_CR_VOS_Msk (0x3U << PWR_CR_VOS_Pos) /*!< 0x0000C000 */
13197 #define PWR_CR_VOS PWR_CR_VOS_Msk /*!< VOS[1:0] bits (Regulator voltage scaling output selection) */
13198 #define PWR_CR_VOS_0 0x00004000U /*!< Bit 0 */
13199 #define PWR_CR_VOS_1 0x00008000U /*!< Bit 1 */
13200 #define PWR_CR_ODEN_Pos (16U)
13201 #define PWR_CR_ODEN_Msk (0x1U << PWR_CR_ODEN_Pos) /*!< 0x00010000 */
13202 #define PWR_CR_ODEN PWR_CR_ODEN_Msk /*!< Over Drive enable */
13203 #define PWR_CR_ODSWEN_Pos (17U)
13204 #define PWR_CR_ODSWEN_Msk (0x1U << PWR_CR_ODSWEN_Pos) /*!< 0x00020000 */
13205 #define PWR_CR_ODSWEN PWR_CR_ODSWEN_Msk /*!< Over Drive switch enabled */
13206 #define PWR_CR_UDEN_Pos (18U)
13207 #define PWR_CR_UDEN_Msk (0x3U << PWR_CR_UDEN_Pos) /*!< 0x000C0000 */
13208 #define PWR_CR_UDEN PWR_CR_UDEN_Msk /*!< Under Drive enable in stop mode */
13209 #define PWR_CR_UDEN_0 (0x1U << PWR_CR_UDEN_Pos) /*!< 0x00040000 */
13210 #define PWR_CR_UDEN_1 (0x2U << PWR_CR_UDEN_Pos) /*!< 0x00080000 */
13211
13212 /* Legacy define */
13213 #define PWR_CR_PMODE PWR_CR_VOS
13214 #define PWR_CR_LPUDS PWR_CR_LPLVDS /*!< Low-Power Regulator in deepsleep under-drive mode */
13215 #define PWR_CR_MRUDS PWR_CR_MRLVDS /*!< Main regulator in deepsleep under-drive mode */
13216
13217 /******************* Bit definition for PWR_CSR register ********************/
13218 #define PWR_CSR_WUF_Pos (0U)
13219 #define PWR_CSR_WUF_Msk (0x1U << PWR_CSR_WUF_Pos) /*!< 0x00000001 */
13220 #define PWR_CSR_WUF PWR_CSR_WUF_Msk /*!< Wakeup Flag */
13221 #define PWR_CSR_SBF_Pos (1U)
13222 #define PWR_CSR_SBF_Msk (0x1U << PWR_CSR_SBF_Pos) /*!< 0x00000002 */
13223 #define PWR_CSR_SBF PWR_CSR_SBF_Msk /*!< Standby Flag */
13224 #define PWR_CSR_PVDO_Pos (2U)
13225 #define PWR_CSR_PVDO_Msk (0x1U << PWR_CSR_PVDO_Pos) /*!< 0x00000004 */
13226 #define PWR_CSR_PVDO PWR_CSR_PVDO_Msk /*!< PVD Output */
13227 #define PWR_CSR_BRR_Pos (3U)
13228 #define PWR_CSR_BRR_Msk (0x1U << PWR_CSR_BRR_Pos) /*!< 0x00000008 */
13229 #define PWR_CSR_BRR PWR_CSR_BRR_Msk /*!< Backup regulator ready */
13230 #define PWR_CSR_WUPP_Pos (7U)
13231 #define PWR_CSR_WUPP_Msk (0x1U << PWR_CSR_WUPP_Pos) /*!< 0x00000080 */
13232 #define PWR_CSR_WUPP PWR_CSR_WUPP_Msk /*!< WKUP pin Polarity */
13233 #define PWR_CSR_EWUP_Pos (8U)
13234 #define PWR_CSR_EWUP_Msk (0x1U << PWR_CSR_EWUP_Pos) /*!< 0x00000100 */
13235 #define PWR_CSR_EWUP PWR_CSR_EWUP_Msk /*!< Enable WKUP pin */
13236 #define PWR_CSR_BRE_Pos (9U)
13237 #define PWR_CSR_BRE_Msk (0x1U << PWR_CSR_BRE_Pos) /*!< 0x00000200 */
13238 #define PWR_CSR_BRE PWR_CSR_BRE_Msk /*!< Backup regulator enable */
13239 #define PWR_CSR_VOSRDY_Pos (14U)
13240 #define PWR_CSR_VOSRDY_Msk (0x1U << PWR_CSR_VOSRDY_Pos) /*!< 0x00004000 */
13241 #define PWR_CSR_VOSRDY PWR_CSR_VOSRDY_Msk /*!< Regulator voltage scaling output selection ready */
13242 #define PWR_CSR_ODRDY_Pos (16U)
13243 #define PWR_CSR_ODRDY_Msk (0x1U << PWR_CSR_ODRDY_Pos) /*!< 0x00010000 */
13244 #define PWR_CSR_ODRDY PWR_CSR_ODRDY_Msk /*!< Over Drive generator ready */
13245 #define PWR_CSR_ODSWRDY_Pos (17U)
13246 #define PWR_CSR_ODSWRDY_Msk (0x1U << PWR_CSR_ODSWRDY_Pos) /*!< 0x00020000 */
13247 #define PWR_CSR_ODSWRDY PWR_CSR_ODSWRDY_Msk /*!< Over Drive Switch ready */
13248 #define PWR_CSR_UDRDY_Pos (18U)
13249 #define PWR_CSR_UDRDY_Msk (0x3U << PWR_CSR_UDRDY_Pos) /*!< 0x000C0000 */
13250 #define PWR_CSR_UDRDY PWR_CSR_UDRDY_Msk /*!< Under Drive ready */
13251 /* Legacy define */
13252 #define PWR_CSR_UDSWRDY PWR_CSR_UDRDY
13253
13254 /* Legacy define */
13255 #define PWR_CSR_REGRDY PWR_CSR_VOSRDY
13256
13257 /******************************************************************************/
13258 /* */
13259 /* QUADSPI */
13260 /* */
13261 /******************************************************************************/
13262 /***************** Bit definition for QUADSPI_CR register *******************/
13263 #define QUADSPI_CR_EN_Pos (0U)
13264 #define QUADSPI_CR_EN_Msk (0x1U << QUADSPI_CR_EN_Pos) /*!< 0x00000001 */
13265 #define QUADSPI_CR_EN QUADSPI_CR_EN_Msk /*!< Enable */
13266 #define QUADSPI_CR_ABORT_Pos (1U)
13267 #define QUADSPI_CR_ABORT_Msk (0x1U << QUADSPI_CR_ABORT_Pos) /*!< 0x00000002 */
13268 #define QUADSPI_CR_ABORT QUADSPI_CR_ABORT_Msk /*!< Abort request */
13269 #define QUADSPI_CR_DMAEN_Pos (2U)
13270 #define QUADSPI_CR_DMAEN_Msk (0x1U << QUADSPI_CR_DMAEN_Pos) /*!< 0x00000004 */
13271 #define QUADSPI_CR_DMAEN QUADSPI_CR_DMAEN_Msk /*!< DMA Enable */
13272 #define QUADSPI_CR_TCEN_Pos (3U)
13273 #define QUADSPI_CR_TCEN_Msk (0x1U << QUADSPI_CR_TCEN_Pos) /*!< 0x00000008 */
13274 #define QUADSPI_CR_TCEN QUADSPI_CR_TCEN_Msk /*!< Timeout Counter Enable */
13275 #define QUADSPI_CR_SSHIFT_Pos (4U)
13276 #define QUADSPI_CR_SSHIFT_Msk (0x1U << QUADSPI_CR_SSHIFT_Pos) /*!< 0x00000010 */
13277 #define QUADSPI_CR_SSHIFT QUADSPI_CR_SSHIFT_Msk /*!< SSHIFT Sample Shift */
13278 #define QUADSPI_CR_DFM_Pos (6U)
13279 #define QUADSPI_CR_DFM_Msk (0x1U << QUADSPI_CR_DFM_Pos) /*!< 0x00000040 */
13280 #define QUADSPI_CR_DFM QUADSPI_CR_DFM_Msk /*!< Dual Flash Mode */
13281 #define QUADSPI_CR_FSEL_Pos (7U)
13282 #define QUADSPI_CR_FSEL_Msk (0x1U << QUADSPI_CR_FSEL_Pos) /*!< 0x00000080 */
13283 #define QUADSPI_CR_FSEL QUADSPI_CR_FSEL_Msk /*!< Flash Select */
13284 #define QUADSPI_CR_FTHRES_Pos (8U)
13285 #define QUADSPI_CR_FTHRES_Msk (0x1FU << QUADSPI_CR_FTHRES_Pos) /*!< 0x00001F00 */
13286 #define QUADSPI_CR_FTHRES QUADSPI_CR_FTHRES_Msk /*!< FTHRES[3:0] FIFO Level */
13287 #define QUADSPI_CR_FTHRES_0 (0x01U << QUADSPI_CR_FTHRES_Pos) /*!< 0x00000100 */
13288 #define QUADSPI_CR_FTHRES_1 (0x02U << QUADSPI_CR_FTHRES_Pos) /*!< 0x00000200 */
13289 #define QUADSPI_CR_FTHRES_2 (0x04U << QUADSPI_CR_FTHRES_Pos) /*!< 0x00000400 */
13290 #define QUADSPI_CR_FTHRES_3 (0x08U << QUADSPI_CR_FTHRES_Pos) /*!< 0x00000800 */
13291 #define QUADSPI_CR_FTHRES_4 (0x10U << QUADSPI_CR_FTHRES_Pos) /*!< 0x00001000 */
13292 #define QUADSPI_CR_TEIE_Pos (16U)
13293 #define QUADSPI_CR_TEIE_Msk (0x1U << QUADSPI_CR_TEIE_Pos) /*!< 0x00010000 */
13294 #define QUADSPI_CR_TEIE QUADSPI_CR_TEIE_Msk /*!< Transfer Error Interrupt Enable */
13295 #define QUADSPI_CR_TCIE_Pos (17U)
13296 #define QUADSPI_CR_TCIE_Msk (0x1U << QUADSPI_CR_TCIE_Pos) /*!< 0x00020000 */
13297 #define QUADSPI_CR_TCIE QUADSPI_CR_TCIE_Msk /*!< Transfer Complete Interrupt Enable */
13298 #define QUADSPI_CR_FTIE_Pos (18U)
13299 #define QUADSPI_CR_FTIE_Msk (0x1U << QUADSPI_CR_FTIE_Pos) /*!< 0x00040000 */
13300 #define QUADSPI_CR_FTIE QUADSPI_CR_FTIE_Msk /*!< FIFO Threshold Interrupt Enable */
13301 #define QUADSPI_CR_SMIE_Pos (19U)
13302 #define QUADSPI_CR_SMIE_Msk (0x1U << QUADSPI_CR_SMIE_Pos) /*!< 0x00080000 */
13303 #define QUADSPI_CR_SMIE QUADSPI_CR_SMIE_Msk /*!< Status Match Interrupt Enable */
13304 #define QUADSPI_CR_TOIE_Pos (20U)
13305 #define QUADSPI_CR_TOIE_Msk (0x1U << QUADSPI_CR_TOIE_Pos) /*!< 0x00100000 */
13306 #define QUADSPI_CR_TOIE QUADSPI_CR_TOIE_Msk /*!< TimeOut Interrupt Enable */
13307 #define QUADSPI_CR_APMS_Pos (22U)
13308 #define QUADSPI_CR_APMS_Msk (0x1U << QUADSPI_CR_APMS_Pos) /*!< 0x00400000 */
13309 #define QUADSPI_CR_APMS QUADSPI_CR_APMS_Msk /*!< Bit 1 */
13310 #define QUADSPI_CR_PMM_Pos (23U)
13311 #define QUADSPI_CR_PMM_Msk (0x1U << QUADSPI_CR_PMM_Pos) /*!< 0x00800000 */
13312 #define QUADSPI_CR_PMM QUADSPI_CR_PMM_Msk /*!< Polling Match Mode */
13313 #define QUADSPI_CR_PRESCALER_Pos (24U)
13314 #define QUADSPI_CR_PRESCALER_Msk (0xFFU << QUADSPI_CR_PRESCALER_Pos) /*!< 0xFF000000 */
13315 #define QUADSPI_CR_PRESCALER QUADSPI_CR_PRESCALER_Msk /*!< PRESCALER[7:0] Clock prescaler */
13316 #define QUADSPI_CR_PRESCALER_0 (0x01U << QUADSPI_CR_PRESCALER_Pos) /*!< 0x01000000 */
13317 #define QUADSPI_CR_PRESCALER_1 (0x02U << QUADSPI_CR_PRESCALER_Pos) /*!< 0x02000000 */
13318 #define QUADSPI_CR_PRESCALER_2 (0x04U << QUADSPI_CR_PRESCALER_Pos) /*!< 0x04000000 */
13319 #define QUADSPI_CR_PRESCALER_3 (0x08U << QUADSPI_CR_PRESCALER_Pos) /*!< 0x08000000 */
13320 #define QUADSPI_CR_PRESCALER_4 (0x10U << QUADSPI_CR_PRESCALER_Pos) /*!< 0x10000000 */
13321 #define QUADSPI_CR_PRESCALER_5 (0x20U << QUADSPI_CR_PRESCALER_Pos) /*!< 0x20000000 */
13322 #define QUADSPI_CR_PRESCALER_6 (0x40U << QUADSPI_CR_PRESCALER_Pos) /*!< 0x40000000 */
13323 #define QUADSPI_CR_PRESCALER_7 (0x80U << QUADSPI_CR_PRESCALER_Pos) /*!< 0x80000000 */
13324
13325 /***************** Bit definition for QUADSPI_DCR register ******************/
13326 #define QUADSPI_DCR_CKMODE_Pos (0U)
13327 #define QUADSPI_DCR_CKMODE_Msk (0x1U << QUADSPI_DCR_CKMODE_Pos) /*!< 0x00000001 */
13328 #define QUADSPI_DCR_CKMODE QUADSPI_DCR_CKMODE_Msk /*!< Mode 0 / Mode 3 */
13329 #define QUADSPI_DCR_CSHT_Pos (8U)
13330 #define QUADSPI_DCR_CSHT_Msk (0x7U << QUADSPI_DCR_CSHT_Pos) /*!< 0x00000700 */
13331 #define QUADSPI_DCR_CSHT QUADSPI_DCR_CSHT_Msk /*!< CSHT[2:0]: ChipSelect High Time */
13332 #define QUADSPI_DCR_CSHT_0 (0x1U << QUADSPI_DCR_CSHT_Pos) /*!< 0x00000100 */
13333 #define QUADSPI_DCR_CSHT_1 (0x2U << QUADSPI_DCR_CSHT_Pos) /*!< 0x00000200 */
13334 #define QUADSPI_DCR_CSHT_2 (0x4U << QUADSPI_DCR_CSHT_Pos) /*!< 0x00000400 */
13335 #define QUADSPI_DCR_FSIZE_Pos (16U)
13336 #define QUADSPI_DCR_FSIZE_Msk (0x1FU << QUADSPI_DCR_FSIZE_Pos) /*!< 0x001F0000 */
13337 #define QUADSPI_DCR_FSIZE QUADSPI_DCR_FSIZE_Msk /*!< FSIZE[4:0]: Flash Size */
13338 #define QUADSPI_DCR_FSIZE_0 (0x01U << QUADSPI_DCR_FSIZE_Pos) /*!< 0x00010000 */
13339 #define QUADSPI_DCR_FSIZE_1 (0x02U << QUADSPI_DCR_FSIZE_Pos) /*!< 0x00020000 */
13340 #define QUADSPI_DCR_FSIZE_2 (0x04U << QUADSPI_DCR_FSIZE_Pos) /*!< 0x00040000 */
13341 #define QUADSPI_DCR_FSIZE_3 (0x08U << QUADSPI_DCR_FSIZE_Pos) /*!< 0x00080000 */
13342 #define QUADSPI_DCR_FSIZE_4 (0x10U << QUADSPI_DCR_FSIZE_Pos) /*!< 0x00100000 */
13343
13344 /****************** Bit definition for QUADSPI_SR register *******************/
13345 #define QUADSPI_SR_TEF_Pos (0U)
13346 #define QUADSPI_SR_TEF_Msk (0x1U << QUADSPI_SR_TEF_Pos) /*!< 0x00000001 */
13347 #define QUADSPI_SR_TEF QUADSPI_SR_TEF_Msk /*!< Transfer Error Flag */
13348 #define QUADSPI_SR_TCF_Pos (1U)
13349 #define QUADSPI_SR_TCF_Msk (0x1U << QUADSPI_SR_TCF_Pos) /*!< 0x00000002 */
13350 #define QUADSPI_SR_TCF QUADSPI_SR_TCF_Msk /*!< Transfer Complete Flag */
13351 #define QUADSPI_SR_FTF_Pos (2U)
13352 #define QUADSPI_SR_FTF_Msk (0x1U << QUADSPI_SR_FTF_Pos) /*!< 0x00000004 */
13353 #define QUADSPI_SR_FTF QUADSPI_SR_FTF_Msk /*!< FIFO Threshlod Flag */
13354 #define QUADSPI_SR_SMF_Pos (3U)
13355 #define QUADSPI_SR_SMF_Msk (0x1U << QUADSPI_SR_SMF_Pos) /*!< 0x00000008 */
13356 #define QUADSPI_SR_SMF QUADSPI_SR_SMF_Msk /*!< Status Match Flag */
13357 #define QUADSPI_SR_TOF_Pos (4U)
13358 #define QUADSPI_SR_TOF_Msk (0x1U << QUADSPI_SR_TOF_Pos) /*!< 0x00000010 */
13359 #define QUADSPI_SR_TOF QUADSPI_SR_TOF_Msk /*!< Timeout Flag */
13360 #define QUADSPI_SR_BUSY_Pos (5U)
13361 #define QUADSPI_SR_BUSY_Msk (0x1U << QUADSPI_SR_BUSY_Pos) /*!< 0x00000020 */
13362 #define QUADSPI_SR_BUSY QUADSPI_SR_BUSY_Msk /*!< Busy */
13363 #define QUADSPI_SR_FLEVEL_Pos (8U)
13364 #define QUADSPI_SR_FLEVEL_Msk (0x3FU << QUADSPI_SR_FLEVEL_Pos) /*!< 0x00003F00 */
13365 #define QUADSPI_SR_FLEVEL QUADSPI_SR_FLEVEL_Msk /*!< FIFO Threshlod Flag */
13366 #define QUADSPI_SR_FLEVEL_0 (0x01U << QUADSPI_SR_FLEVEL_Pos) /*!< 0x00000100 */
13367 #define QUADSPI_SR_FLEVEL_1 (0x02U << QUADSPI_SR_FLEVEL_Pos) /*!< 0x00000200 */
13368 #define QUADSPI_SR_FLEVEL_2 (0x04U << QUADSPI_SR_FLEVEL_Pos) /*!< 0x00000400 */
13369 #define QUADSPI_SR_FLEVEL_3 (0x08U << QUADSPI_SR_FLEVEL_Pos) /*!< 0x00000800 */
13370 #define QUADSPI_SR_FLEVEL_4 (0x10U << QUADSPI_SR_FLEVEL_Pos) /*!< 0x00001000 */
13371 #define QUADSPI_SR_FLEVEL_5 (0x20U << QUADSPI_SR_FLEVEL_Pos) /*!< 0x00002000 */
13372
13373 /****************** Bit definition for QUADSPI_FCR register ******************/
13374 #define QUADSPI_FCR_CTEF_Pos (0U)
13375 #define QUADSPI_FCR_CTEF_Msk (0x1U << QUADSPI_FCR_CTEF_Pos) /*!< 0x00000001 */
13376 #define QUADSPI_FCR_CTEF QUADSPI_FCR_CTEF_Msk /*!< Clear Transfer Error Flag */
13377 #define QUADSPI_FCR_CTCF_Pos (1U)
13378 #define QUADSPI_FCR_CTCF_Msk (0x1U << QUADSPI_FCR_CTCF_Pos) /*!< 0x00000002 */
13379 #define QUADSPI_FCR_CTCF QUADSPI_FCR_CTCF_Msk /*!< Clear Transfer Complete Flag */
13380 #define QUADSPI_FCR_CSMF_Pos (3U)
13381 #define QUADSPI_FCR_CSMF_Msk (0x1U << QUADSPI_FCR_CSMF_Pos) /*!< 0x00000008 */
13382 #define QUADSPI_FCR_CSMF QUADSPI_FCR_CSMF_Msk /*!< Clear Status Match Flag */
13383 #define QUADSPI_FCR_CTOF_Pos (4U)
13384 #define QUADSPI_FCR_CTOF_Msk (0x1U << QUADSPI_FCR_CTOF_Pos) /*!< 0x00000010 */
13385 #define QUADSPI_FCR_CTOF QUADSPI_FCR_CTOF_Msk /*!< Clear Timeout Flag */
13386
13387 /****************** Bit definition for QUADSPI_DLR register ******************/
13388 #define QUADSPI_DLR_DL_Pos (0U)
13389 #define QUADSPI_DLR_DL_Msk (0xFFFFFFFFU << QUADSPI_DLR_DL_Pos) /*!< 0xFFFFFFFF */
13390 #define QUADSPI_DLR_DL QUADSPI_DLR_DL_Msk /*!< DL[31:0]: Data Length */
13391
13392 /****************** Bit definition for QUADSPI_CCR register ******************/
13393 #define QUADSPI_CCR_INSTRUCTION_Pos (0U)
13394 #define QUADSPI_CCR_INSTRUCTION_Msk (0xFFU << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x000000FF */
13395 #define QUADSPI_CCR_INSTRUCTION QUADSPI_CCR_INSTRUCTION_Msk /*!< INSTRUCTION[7:0]: Instruction */
13396 #define QUADSPI_CCR_INSTRUCTION_0 (0x01U << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000001 */
13397 #define QUADSPI_CCR_INSTRUCTION_1 (0x02U << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000002 */
13398 #define QUADSPI_CCR_INSTRUCTION_2 (0x04U << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000004 */
13399 #define QUADSPI_CCR_INSTRUCTION_3 (0x08U << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000008 */
13400 #define QUADSPI_CCR_INSTRUCTION_4 (0x10U << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000010 */
13401 #define QUADSPI_CCR_INSTRUCTION_5 (0x20U << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000020 */
13402 #define QUADSPI_CCR_INSTRUCTION_6 (0x40U << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000040 */
13403 #define QUADSPI_CCR_INSTRUCTION_7 (0x80U << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000080 */
13404 #define QUADSPI_CCR_IMODE_Pos (8U)
13405 #define QUADSPI_CCR_IMODE_Msk (0x3U << QUADSPI_CCR_IMODE_Pos) /*!< 0x00000300 */
13406 #define QUADSPI_CCR_IMODE QUADSPI_CCR_IMODE_Msk /*!< IMODE[1:0]: Instruction Mode */
13407 #define QUADSPI_CCR_IMODE_0 (0x1U << QUADSPI_CCR_IMODE_Pos) /*!< 0x00000100 */
13408 #define QUADSPI_CCR_IMODE_1 (0x2U << QUADSPI_CCR_IMODE_Pos) /*!< 0x00000200 */
13409 #define QUADSPI_CCR_ADMODE_Pos (10U)
13410 #define QUADSPI_CCR_ADMODE_Msk (0x3U << QUADSPI_CCR_ADMODE_Pos) /*!< 0x00000C00 */
13411 #define QUADSPI_CCR_ADMODE QUADSPI_CCR_ADMODE_Msk /*!< ADMODE[1:0]: Address Mode */
13412 #define QUADSPI_CCR_ADMODE_0 (0x1U << QUADSPI_CCR_ADMODE_Pos) /*!< 0x00000400 */
13413 #define QUADSPI_CCR_ADMODE_1 (0x2U << QUADSPI_CCR_ADMODE_Pos) /*!< 0x00000800 */
13414 #define QUADSPI_CCR_ADSIZE_Pos (12U)
13415 #define QUADSPI_CCR_ADSIZE_Msk (0x3U << QUADSPI_CCR_ADSIZE_Pos) /*!< 0x00003000 */
13416 #define QUADSPI_CCR_ADSIZE QUADSPI_CCR_ADSIZE_Msk /*!< ADSIZE[1:0]: Address Size */
13417 #define QUADSPI_CCR_ADSIZE_0 (0x1U << QUADSPI_CCR_ADSIZE_Pos) /*!< 0x00001000 */
13418 #define QUADSPI_CCR_ADSIZE_1 (0x2U << QUADSPI_CCR_ADSIZE_Pos) /*!< 0x00002000 */
13419 #define QUADSPI_CCR_ABMODE_Pos (14U)
13420 #define QUADSPI_CCR_ABMODE_Msk (0x3U << QUADSPI_CCR_ABMODE_Pos) /*!< 0x0000C000 */
13421 #define QUADSPI_CCR_ABMODE QUADSPI_CCR_ABMODE_Msk /*!< ABMODE[1:0]: Alternate Bytes Mode */
13422 #define QUADSPI_CCR_ABMODE_0 (0x1U << QUADSPI_CCR_ABMODE_Pos) /*!< 0x00004000 */
13423 #define QUADSPI_CCR_ABMODE_1 (0x2U << QUADSPI_CCR_ABMODE_Pos) /*!< 0x00008000 */
13424 #define QUADSPI_CCR_ABSIZE_Pos (16U)
13425 #define QUADSPI_CCR_ABSIZE_Msk (0x3U << QUADSPI_CCR_ABSIZE_Pos) /*!< 0x00030000 */
13426 #define QUADSPI_CCR_ABSIZE QUADSPI_CCR_ABSIZE_Msk /*!< ABSIZE[1:0]: Instruction Mode */
13427 #define QUADSPI_CCR_ABSIZE_0 (0x1U << QUADSPI_CCR_ABSIZE_Pos) /*!< 0x00010000 */
13428 #define QUADSPI_CCR_ABSIZE_1 (0x2U << QUADSPI_CCR_ABSIZE_Pos) /*!< 0x00020000 */
13429 #define QUADSPI_CCR_DCYC_Pos (18U)
13430 #define QUADSPI_CCR_DCYC_Msk (0x1FU << QUADSPI_CCR_DCYC_Pos) /*!< 0x007C0000 */
13431 #define QUADSPI_CCR_DCYC QUADSPI_CCR_DCYC_Msk /*!< DCYC[4:0]: Dummy Cycles */
13432 #define QUADSPI_CCR_DCYC_0 (0x01U << QUADSPI_CCR_DCYC_Pos) /*!< 0x00040000 */
13433 #define QUADSPI_CCR_DCYC_1 (0x02U << QUADSPI_CCR_DCYC_Pos) /*!< 0x00080000 */
13434 #define QUADSPI_CCR_DCYC_2 (0x04U << QUADSPI_CCR_DCYC_Pos) /*!< 0x00100000 */
13435 #define QUADSPI_CCR_DCYC_3 (0x08U << QUADSPI_CCR_DCYC_Pos) /*!< 0x00200000 */
13436 #define QUADSPI_CCR_DCYC_4 (0x10U << QUADSPI_CCR_DCYC_Pos) /*!< 0x00400000 */
13437 #define QUADSPI_CCR_DMODE_Pos (24U)
13438 #define QUADSPI_CCR_DMODE_Msk (0x3U << QUADSPI_CCR_DMODE_Pos) /*!< 0x03000000 */
13439 #define QUADSPI_CCR_DMODE QUADSPI_CCR_DMODE_Msk /*!< DMODE[1:0]: Data Mode */
13440 #define QUADSPI_CCR_DMODE_0 (0x1U << QUADSPI_CCR_DMODE_Pos) /*!< 0x01000000 */
13441 #define QUADSPI_CCR_DMODE_1 (0x2U << QUADSPI_CCR_DMODE_Pos) /*!< 0x02000000 */
13442 #define QUADSPI_CCR_FMODE_Pos (26U)
13443 #define QUADSPI_CCR_FMODE_Msk (0x3U << QUADSPI_CCR_FMODE_Pos) /*!< 0x0C000000 */
13444 #define QUADSPI_CCR_FMODE QUADSPI_CCR_FMODE_Msk /*!< FMODE[1:0]: Functional Mode */
13445 #define QUADSPI_CCR_FMODE_0 (0x1U << QUADSPI_CCR_FMODE_Pos) /*!< 0x04000000 */
13446 #define QUADSPI_CCR_FMODE_1 (0x2U << QUADSPI_CCR_FMODE_Pos) /*!< 0x08000000 */
13447 #define QUADSPI_CCR_SIOO_Pos (28U)
13448 #define QUADSPI_CCR_SIOO_Msk (0x1U << QUADSPI_CCR_SIOO_Pos) /*!< 0x10000000 */
13449 #define QUADSPI_CCR_SIOO QUADSPI_CCR_SIOO_Msk /*!< SIOO: Send Instruction Only Once Mode */
13450 #define QUADSPI_CCR_DHHC_Pos (30U)
13451 #define QUADSPI_CCR_DHHC_Msk (0x1U << QUADSPI_CCR_DHHC_Pos) /*!< 0x40000000 */
13452 #define QUADSPI_CCR_DHHC QUADSPI_CCR_DHHC_Msk /*!< DHHC: Delay Half Hclk Cycle */
13453 #define QUADSPI_CCR_DDRM_Pos (31U)
13454 #define QUADSPI_CCR_DDRM_Msk (0x1U << QUADSPI_CCR_DDRM_Pos) /*!< 0x80000000 */
13455 #define QUADSPI_CCR_DDRM QUADSPI_CCR_DDRM_Msk /*!< DDRM: Double Data Rate Mode */
13456 /****************** Bit definition for QUADSPI_AR register *******************/
13457 #define QUADSPI_AR_ADDRESS_Pos (0U)
13458 #define QUADSPI_AR_ADDRESS_Msk (0xFFFFFFFFU << QUADSPI_AR_ADDRESS_Pos) /*!< 0xFFFFFFFF */
13459 #define QUADSPI_AR_ADDRESS QUADSPI_AR_ADDRESS_Msk /*!< ADDRESS[31:0]: Address */
13460
13461 /****************** Bit definition for QUADSPI_ABR register ******************/
13462 #define QUADSPI_ABR_ALTERNATE_Pos (0U)
13463 #define QUADSPI_ABR_ALTERNATE_Msk (0xFFFFFFFFU << QUADSPI_ABR_ALTERNATE_Pos) /*!< 0xFFFFFFFF */
13464 #define QUADSPI_ABR_ALTERNATE QUADSPI_ABR_ALTERNATE_Msk /*!< ALTERNATE[31:0]: Alternate Bytes */
13465
13466 /****************** Bit definition for QUADSPI_DR register *******************/
13467 #define QUADSPI_DR_DATA_Pos (0U)
13468 #define QUADSPI_DR_DATA_Msk (0xFFFFFFFFU << QUADSPI_DR_DATA_Pos) /*!< 0xFFFFFFFF */
13469 #define QUADSPI_DR_DATA QUADSPI_DR_DATA_Msk /*!< DATA[31:0]: Data */
13470
13471 /****************** Bit definition for QUADSPI_PSMKR register ****************/
13472 #define QUADSPI_PSMKR_MASK_Pos (0U)
13473 #define QUADSPI_PSMKR_MASK_Msk (0xFFFFFFFFU << QUADSPI_PSMKR_MASK_Pos) /*!< 0xFFFFFFFF */
13474 #define QUADSPI_PSMKR_MASK QUADSPI_PSMKR_MASK_Msk /*!< MASK[31:0]: Status Mask */
13475
13476 /****************** Bit definition for QUADSPI_PSMAR register ****************/
13477 #define QUADSPI_PSMAR_MATCH_Pos (0U)
13478 #define QUADSPI_PSMAR_MATCH_Msk (0xFFFFFFFFU << QUADSPI_PSMAR_MATCH_Pos) /*!< 0xFFFFFFFF */
13479 #define QUADSPI_PSMAR_MATCH QUADSPI_PSMAR_MATCH_Msk /*!< MATCH[31:0]: Status Match */
13480
13481 /****************** Bit definition for QUADSPI_PIR register *****************/
13482 #define QUADSPI_PIR_INTERVAL_Pos (0U)
13483 #define QUADSPI_PIR_INTERVAL_Msk (0xFFFFU << QUADSPI_PIR_INTERVAL_Pos) /*!< 0x0000FFFF */
13484 #define QUADSPI_PIR_INTERVAL QUADSPI_PIR_INTERVAL_Msk /*!< INTERVAL[15:0]: Polling Interval */
13485
13486 /****************** Bit definition for QUADSPI_LPTR register *****************/
13487 #define QUADSPI_LPTR_TIMEOUT_Pos (0U)
13488 #define QUADSPI_LPTR_TIMEOUT_Msk (0xFFFFU << QUADSPI_LPTR_TIMEOUT_Pos) /*!< 0x0000FFFF */
13489 #define QUADSPI_LPTR_TIMEOUT QUADSPI_LPTR_TIMEOUT_Msk /*!< TIMEOUT[15:0]: Timeout period */
13490
13491 /******************************************************************************/
13492 /* */
13493 /* Reset and Clock Control */
13494 /* */
13495 /******************************************************************************/
13496 /******************** Bit definition for RCC_CR register ********************/
13497 #define RCC_CR_HSION_Pos (0U)
13498 #define RCC_CR_HSION_Msk (0x1U << RCC_CR_HSION_Pos) /*!< 0x00000001 */
13499 #define RCC_CR_HSION RCC_CR_HSION_Msk
13500 #define RCC_CR_HSIRDY_Pos (1U)
13501 #define RCC_CR_HSIRDY_Msk (0x1U << RCC_CR_HSIRDY_Pos) /*!< 0x00000002 */
13502 #define RCC_CR_HSIRDY RCC_CR_HSIRDY_Msk
13503
13504 #define RCC_CR_HSITRIM_Pos (3U)
13505 #define RCC_CR_HSITRIM_Msk (0x1FU << RCC_CR_HSITRIM_Pos) /*!< 0x000000F8 */
13506 #define RCC_CR_HSITRIM RCC_CR_HSITRIM_Msk
13507 #define RCC_CR_HSITRIM_0 (0x01U << RCC_CR_HSITRIM_Pos) /*!< 0x00000008 */
13508 #define RCC_CR_HSITRIM_1 (0x02U << RCC_CR_HSITRIM_Pos) /*!< 0x00000010 */
13509 #define RCC_CR_HSITRIM_2 (0x04U << RCC_CR_HSITRIM_Pos) /*!< 0x00000020 */
13510 #define RCC_CR_HSITRIM_3 (0x08U << RCC_CR_HSITRIM_Pos) /*!< 0x00000040 */
13511 #define RCC_CR_HSITRIM_4 (0x10U << RCC_CR_HSITRIM_Pos) /*!< 0x00000080 */
13512
13513 #define RCC_CR_HSICAL_Pos (8U)
13514 #define RCC_CR_HSICAL_Msk (0xFFU << RCC_CR_HSICAL_Pos) /*!< 0x0000FF00 */
13515 #define RCC_CR_HSICAL RCC_CR_HSICAL_Msk
13516 #define RCC_CR_HSICAL_0 (0x01U << RCC_CR_HSICAL_Pos) /*!< 0x00000100 */
13517 #define RCC_CR_HSICAL_1 (0x02U << RCC_CR_HSICAL_Pos) /*!< 0x00000200 */
13518 #define RCC_CR_HSICAL_2 (0x04U << RCC_CR_HSICAL_Pos) /*!< 0x00000400 */
13519 #define RCC_CR_HSICAL_3 (0x08U << RCC_CR_HSICAL_Pos) /*!< 0x00000800 */
13520 #define RCC_CR_HSICAL_4 (0x10U << RCC_CR_HSICAL_Pos) /*!< 0x00001000 */
13521 #define RCC_CR_HSICAL_5 (0x20U << RCC_CR_HSICAL_Pos) /*!< 0x00002000 */
13522 #define RCC_CR_HSICAL_6 (0x40U << RCC_CR_HSICAL_Pos) /*!< 0x00004000 */
13523 #define RCC_CR_HSICAL_7 (0x80U << RCC_CR_HSICAL_Pos) /*!< 0x00008000 */
13524
13525 #define RCC_CR_HSEON_Pos (16U)
13526 #define RCC_CR_HSEON_Msk (0x1U << RCC_CR_HSEON_Pos) /*!< 0x00010000 */
13527 #define RCC_CR_HSEON RCC_CR_HSEON_Msk
13528 #define RCC_CR_HSERDY_Pos (17U)
13529 #define RCC_CR_HSERDY_Msk (0x1U << RCC_CR_HSERDY_Pos) /*!< 0x00020000 */
13530 #define RCC_CR_HSERDY RCC_CR_HSERDY_Msk
13531 #define RCC_CR_HSEBYP_Pos (18U)
13532 #define RCC_CR_HSEBYP_Msk (0x1U << RCC_CR_HSEBYP_Pos) /*!< 0x00040000 */
13533 #define RCC_CR_HSEBYP RCC_CR_HSEBYP_Msk
13534 #define RCC_CR_CSSON_Pos (19U)
13535 #define RCC_CR_CSSON_Msk (0x1U << RCC_CR_CSSON_Pos) /*!< 0x00080000 */
13536 #define RCC_CR_CSSON RCC_CR_CSSON_Msk
13537 #define RCC_CR_PLLON_Pos (24U)
13538 #define RCC_CR_PLLON_Msk (0x1U << RCC_CR_PLLON_Pos) /*!< 0x01000000 */
13539 #define RCC_CR_PLLON RCC_CR_PLLON_Msk
13540 #define RCC_CR_PLLRDY_Pos (25U)
13541 #define RCC_CR_PLLRDY_Msk (0x1U << RCC_CR_PLLRDY_Pos) /*!< 0x02000000 */
13542 #define RCC_CR_PLLRDY RCC_CR_PLLRDY_Msk
13543 /*
13544 * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
13545 */
13546 #define RCC_PLLI2S_SUPPORT /*!< Support PLLI2S oscillator */
13547
13548 #define RCC_CR_PLLI2SON_Pos (26U)
13549 #define RCC_CR_PLLI2SON_Msk (0x1U << RCC_CR_PLLI2SON_Pos) /*!< 0x04000000 */
13550 #define RCC_CR_PLLI2SON RCC_CR_PLLI2SON_Msk
13551 #define RCC_CR_PLLI2SRDY_Pos (27U)
13552 #define RCC_CR_PLLI2SRDY_Msk (0x1U << RCC_CR_PLLI2SRDY_Pos) /*!< 0x08000000 */
13553 #define RCC_CR_PLLI2SRDY RCC_CR_PLLI2SRDY_Msk
13554 /*
13555 * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
13556 */
13557 #define RCC_PLLSAI_SUPPORT /*!< Support PLLSAI oscillator */
13558
13559 #define RCC_CR_PLLSAION_Pos (28U)
13560 #define RCC_CR_PLLSAION_Msk (0x1U << RCC_CR_PLLSAION_Pos) /*!< 0x10000000 */
13561 #define RCC_CR_PLLSAION RCC_CR_PLLSAION_Msk
13562 #define RCC_CR_PLLSAIRDY_Pos (29U)
13563 #define RCC_CR_PLLSAIRDY_Msk (0x1U << RCC_CR_PLLSAIRDY_Pos) /*!< 0x20000000 */
13564 #define RCC_CR_PLLSAIRDY RCC_CR_PLLSAIRDY_Msk
13565
13566 /******************** Bit definition for RCC_PLLCFGR register ***************/
13567 #define RCC_PLLCFGR_PLLM_Pos (0U)
13568 #define RCC_PLLCFGR_PLLM_Msk (0x3FU << RCC_PLLCFGR_PLLM_Pos) /*!< 0x0000003F */
13569 #define RCC_PLLCFGR_PLLM RCC_PLLCFGR_PLLM_Msk
13570 #define RCC_PLLCFGR_PLLM_0 (0x01U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000001 */
13571 #define RCC_PLLCFGR_PLLM_1 (0x02U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000002 */
13572 #define RCC_PLLCFGR_PLLM_2 (0x04U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000004 */
13573 #define RCC_PLLCFGR_PLLM_3 (0x08U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000008 */
13574 #define RCC_PLLCFGR_PLLM_4 (0x10U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000010 */
13575 #define RCC_PLLCFGR_PLLM_5 (0x20U << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000020 */
13576
13577 #define RCC_PLLCFGR_PLLN_Pos (6U)
13578 #define RCC_PLLCFGR_PLLN_Msk (0x1FFU << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00007FC0 */
13579 #define RCC_PLLCFGR_PLLN RCC_PLLCFGR_PLLN_Msk
13580 #define RCC_PLLCFGR_PLLN_0 (0x001U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000040 */
13581 #define RCC_PLLCFGR_PLLN_1 (0x002U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000080 */
13582 #define RCC_PLLCFGR_PLLN_2 (0x004U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000100 */
13583 #define RCC_PLLCFGR_PLLN_3 (0x008U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000200 */
13584 #define RCC_PLLCFGR_PLLN_4 (0x010U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000400 */
13585 #define RCC_PLLCFGR_PLLN_5 (0x020U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000800 */
13586 #define RCC_PLLCFGR_PLLN_6 (0x040U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00001000 */
13587 #define RCC_PLLCFGR_PLLN_7 (0x080U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00002000 */
13588 #define RCC_PLLCFGR_PLLN_8 (0x100U << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00004000 */
13589
13590 #define RCC_PLLCFGR_PLLP_Pos (16U)
13591 #define RCC_PLLCFGR_PLLP_Msk (0x3U << RCC_PLLCFGR_PLLP_Pos) /*!< 0x00030000 */
13592 #define RCC_PLLCFGR_PLLP RCC_PLLCFGR_PLLP_Msk
13593 #define RCC_PLLCFGR_PLLP_0 (0x1U << RCC_PLLCFGR_PLLP_Pos) /*!< 0x00010000 */
13594 #define RCC_PLLCFGR_PLLP_1 (0x2U << RCC_PLLCFGR_PLLP_Pos) /*!< 0x00020000 */
13595
13596 #define RCC_PLLCFGR_PLLSRC_Pos (22U)
13597 #define RCC_PLLCFGR_PLLSRC_Msk (0x1U << RCC_PLLCFGR_PLLSRC_Pos) /*!< 0x00400000 */
13598 #define RCC_PLLCFGR_PLLSRC RCC_PLLCFGR_PLLSRC_Msk
13599 #define RCC_PLLCFGR_PLLSRC_HSE_Pos (22U)
13600 #define RCC_PLLCFGR_PLLSRC_HSE_Msk (0x1U << RCC_PLLCFGR_PLLSRC_HSE_Pos) /*!< 0x00400000 */
13601 #define RCC_PLLCFGR_PLLSRC_HSE RCC_PLLCFGR_PLLSRC_HSE_Msk
13602 #define RCC_PLLCFGR_PLLSRC_HSI 0x00000000U
13603
13604 #define RCC_PLLCFGR_PLLQ_Pos (24U)
13605 #define RCC_PLLCFGR_PLLQ_Msk (0xFU << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x0F000000 */
13606 #define RCC_PLLCFGR_PLLQ RCC_PLLCFGR_PLLQ_Msk
13607 #define RCC_PLLCFGR_PLLQ_0 (0x1U << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x01000000 */
13608 #define RCC_PLLCFGR_PLLQ_1 (0x2U << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x02000000 */
13609 #define RCC_PLLCFGR_PLLQ_2 (0x4U << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x04000000 */
13610 #define RCC_PLLCFGR_PLLQ_3 (0x8U << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x08000000 */
13611
13612 #define RCC_PLLCFGR_PLLR_Pos (28U)
13613 #define RCC_PLLCFGR_PLLR_Msk (0x7U << RCC_PLLCFGR_PLLR_Pos) /*!< 0x70000000 */
13614 #define RCC_PLLCFGR_PLLR RCC_PLLCFGR_PLLR_Msk
13615 #define RCC_PLLCFGR_PLLR_0 (0x1U << RCC_PLLCFGR_PLLR_Pos) /*!< 0x10000000 */
13616 #define RCC_PLLCFGR_PLLR_1 (0x2U << RCC_PLLCFGR_PLLR_Pos) /*!< 0x20000000 */
13617 #define RCC_PLLCFGR_PLLR_2 (0x4U << RCC_PLLCFGR_PLLR_Pos) /*!< 0x40000000 */
13618
13619 /******************** Bit definition for RCC_CFGR register ******************/
13620 /*!< SW configuration */
13621 #define RCC_CFGR_SW_Pos (0U)
13622 #define RCC_CFGR_SW_Msk (0x3U << RCC_CFGR_SW_Pos) /*!< 0x00000003 */
13623 #define RCC_CFGR_SW RCC_CFGR_SW_Msk /*!< SW[1:0] bits (System clock Switch) */
13624 #define RCC_CFGR_SW_0 (0x1U << RCC_CFGR_SW_Pos) /*!< 0x00000001 */
13625 #define RCC_CFGR_SW_1 (0x2U << RCC_CFGR_SW_Pos) /*!< 0x00000002 */
13626
13627 #define RCC_CFGR_SW_HSI 0x00000000U /*!< HSI selected as system clock */
13628 #define RCC_CFGR_SW_HSE 0x00000001U /*!< HSE selected as system clock */
13629 #define RCC_CFGR_SW_PLL 0x00000002U /*!< PLL selected as system clock */
13630
13631 /*!< SWS configuration */
13632 #define RCC_CFGR_SWS_Pos (2U)
13633 #define RCC_CFGR_SWS_Msk (0x3U << RCC_CFGR_SWS_Pos) /*!< 0x0000000C */
13634 #define RCC_CFGR_SWS RCC_CFGR_SWS_Msk /*!< SWS[1:0] bits (System Clock Switch Status) */
13635 #define RCC_CFGR_SWS_0 (0x1U << RCC_CFGR_SWS_Pos) /*!< 0x00000004 */
13636 #define RCC_CFGR_SWS_1 (0x2U << RCC_CFGR_SWS_Pos) /*!< 0x00000008 */
13637
13638 #define RCC_CFGR_SWS_HSI 0x00000000U /*!< HSI oscillator used as system clock */
13639 #define RCC_CFGR_SWS_HSE 0x00000004U /*!< HSE oscillator used as system clock */
13640 #define RCC_CFGR_SWS_PLL 0x00000008U /*!< PLL used as system clock */
13641
13642 /*!< HPRE configuration */
13643 #define RCC_CFGR_HPRE_Pos (4U)
13644 #define RCC_CFGR_HPRE_Msk (0xFU << RCC_CFGR_HPRE_Pos) /*!< 0x000000F0 */
13645 #define RCC_CFGR_HPRE RCC_CFGR_HPRE_Msk /*!< HPRE[3:0] bits (AHB prescaler) */
13646 #define RCC_CFGR_HPRE_0 (0x1U << RCC_CFGR_HPRE_Pos) /*!< 0x00000010 */
13647 #define RCC_CFGR_HPRE_1 (0x2U << RCC_CFGR_HPRE_Pos) /*!< 0x00000020 */
13648 #define RCC_CFGR_HPRE_2 (0x4U << RCC_CFGR_HPRE_Pos) /*!< 0x00000040 */
13649 #define RCC_CFGR_HPRE_3 (0x8U << RCC_CFGR_HPRE_Pos) /*!< 0x00000080 */
13650
13651 #define RCC_CFGR_HPRE_DIV1 0x00000000U /*!< SYSCLK not divided */
13652 #define RCC_CFGR_HPRE_DIV2 0x00000080U /*!< SYSCLK divided by 2 */
13653 #define RCC_CFGR_HPRE_DIV4 0x00000090U /*!< SYSCLK divided by 4 */
13654 #define RCC_CFGR_HPRE_DIV8 0x000000A0U /*!< SYSCLK divided by 8 */
13655 #define RCC_CFGR_HPRE_DIV16 0x000000B0U /*!< SYSCLK divided by 16 */
13656 #define RCC_CFGR_HPRE_DIV64 0x000000C0U /*!< SYSCLK divided by 64 */
13657 #define RCC_CFGR_HPRE_DIV128 0x000000D0U /*!< SYSCLK divided by 128 */
13658 #define RCC_CFGR_HPRE_DIV256 0x000000E0U /*!< SYSCLK divided by 256 */
13659 #define RCC_CFGR_HPRE_DIV512 0x000000F0U /*!< SYSCLK divided by 512 */
13660
13661 /*!< PPRE1 configuration */
13662 #define RCC_CFGR_PPRE1_Pos (10U)
13663 #define RCC_CFGR_PPRE1_Msk (0x7U << RCC_CFGR_PPRE1_Pos) /*!< 0x00001C00 */
13664 #define RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_Msk /*!< PRE1[2:0] bits (APB1 prescaler) */
13665 #define RCC_CFGR_PPRE1_0 (0x1U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000400 */
13666 #define RCC_CFGR_PPRE1_1 (0x2U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000800 */
13667 #define RCC_CFGR_PPRE1_2 (0x4U << RCC_CFGR_PPRE1_Pos) /*!< 0x00001000 */
13668
13669 #define RCC_CFGR_PPRE1_DIV1 0x00000000U /*!< HCLK not divided */
13670 #define RCC_CFGR_PPRE1_DIV2 0x00001000U /*!< HCLK divided by 2 */
13671 #define RCC_CFGR_PPRE1_DIV4 0x00001400U /*!< HCLK divided by 4 */
13672 #define RCC_CFGR_PPRE1_DIV8 0x00001800U /*!< HCLK divided by 8 */
13673 #define RCC_CFGR_PPRE1_DIV16 0x00001C00U /*!< HCLK divided by 16 */
13674
13675 /*!< PPRE2 configuration */
13676 #define RCC_CFGR_PPRE2_Pos (13U)
13677 #define RCC_CFGR_PPRE2_Msk (0x7U << RCC_CFGR_PPRE2_Pos) /*!< 0x0000E000 */
13678 #define RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_Msk /*!< PRE2[2:0] bits (APB2 prescaler) */
13679 #define RCC_CFGR_PPRE2_0 (0x1U << RCC_CFGR_PPRE2_Pos) /*!< 0x00002000 */
13680 #define RCC_CFGR_PPRE2_1 (0x2U << RCC_CFGR_PPRE2_Pos) /*!< 0x00004000 */
13681 #define RCC_CFGR_PPRE2_2 (0x4U << RCC_CFGR_PPRE2_Pos) /*!< 0x00008000 */
13682
13683 #define RCC_CFGR_PPRE2_DIV1 0x00000000U /*!< HCLK not divided */
13684 #define RCC_CFGR_PPRE2_DIV2 0x00008000U /*!< HCLK divided by 2 */
13685 #define RCC_CFGR_PPRE2_DIV4 0x0000A000U /*!< HCLK divided by 4 */
13686 #define RCC_CFGR_PPRE2_DIV8 0x0000C000U /*!< HCLK divided by 8 */
13687 #define RCC_CFGR_PPRE2_DIV16 0x0000E000U /*!< HCLK divided by 16 */
13688
13689 /*!< RTCPRE configuration */
13690 #define RCC_CFGR_RTCPRE_Pos (16U)
13691 #define RCC_CFGR_RTCPRE_Msk (0x1FU << RCC_CFGR_RTCPRE_Pos) /*!< 0x001F0000 */
13692 #define RCC_CFGR_RTCPRE RCC_CFGR_RTCPRE_Msk
13693 #define RCC_CFGR_RTCPRE_0 (0x01U << RCC_CFGR_RTCPRE_Pos) /*!< 0x00010000 */
13694 #define RCC_CFGR_RTCPRE_1 (0x02U << RCC_CFGR_RTCPRE_Pos) /*!< 0x00020000 */
13695 #define RCC_CFGR_RTCPRE_2 (0x04U << RCC_CFGR_RTCPRE_Pos) /*!< 0x00040000 */
13696 #define RCC_CFGR_RTCPRE_3 (0x08U << RCC_CFGR_RTCPRE_Pos) /*!< 0x00080000 */
13697 #define RCC_CFGR_RTCPRE_4 (0x10U << RCC_CFGR_RTCPRE_Pos) /*!< 0x00100000 */
13698
13699 /*!< MCO1 configuration */
13700 #define RCC_CFGR_MCO1_Pos (21U)
13701 #define RCC_CFGR_MCO1_Msk (0x3U << RCC_CFGR_MCO1_Pos) /*!< 0x00600000 */
13702 #define RCC_CFGR_MCO1 RCC_CFGR_MCO1_Msk
13703 #define RCC_CFGR_MCO1_0 (0x1U << RCC_CFGR_MCO1_Pos) /*!< 0x00200000 */
13704 #define RCC_CFGR_MCO1_1 (0x2U << RCC_CFGR_MCO1_Pos) /*!< 0x00400000 */
13705
13706 #define RCC_CFGR_I2SSRC_Pos (23U)
13707 #define RCC_CFGR_I2SSRC_Msk (0x1U << RCC_CFGR_I2SSRC_Pos) /*!< 0x00800000 */
13708 #define RCC_CFGR_I2SSRC RCC_CFGR_I2SSRC_Msk
13709
13710 #define RCC_CFGR_MCO1PRE_Pos (24U)
13711 #define RCC_CFGR_MCO1PRE_Msk (0x7U << RCC_CFGR_MCO1PRE_Pos) /*!< 0x07000000 */
13712 #define RCC_CFGR_MCO1PRE RCC_CFGR_MCO1PRE_Msk
13713 #define RCC_CFGR_MCO1PRE_0 (0x1U << RCC_CFGR_MCO1PRE_Pos) /*!< 0x01000000 */
13714 #define RCC_CFGR_MCO1PRE_1 (0x2U << RCC_CFGR_MCO1PRE_Pos) /*!< 0x02000000 */
13715 #define RCC_CFGR_MCO1PRE_2 (0x4U << RCC_CFGR_MCO1PRE_Pos) /*!< 0x04000000 */
13716
13717 #define RCC_CFGR_MCO2PRE_Pos (27U)
13718 #define RCC_CFGR_MCO2PRE_Msk (0x7U << RCC_CFGR_MCO2PRE_Pos) /*!< 0x38000000 */
13719 #define RCC_CFGR_MCO2PRE RCC_CFGR_MCO2PRE_Msk
13720 #define RCC_CFGR_MCO2PRE_0 (0x1U << RCC_CFGR_MCO2PRE_Pos) /*!< 0x08000000 */
13721 #define RCC_CFGR_MCO2PRE_1 (0x2U << RCC_CFGR_MCO2PRE_Pos) /*!< 0x10000000 */
13722 #define RCC_CFGR_MCO2PRE_2 (0x4U << RCC_CFGR_MCO2PRE_Pos) /*!< 0x20000000 */
13723
13724 #define RCC_CFGR_MCO2_Pos (30U)
13725 #define RCC_CFGR_MCO2_Msk (0x3U << RCC_CFGR_MCO2_Pos) /*!< 0xC0000000 */
13726 #define RCC_CFGR_MCO2 RCC_CFGR_MCO2_Msk
13727 #define RCC_CFGR_MCO2_0 (0x1U << RCC_CFGR_MCO2_Pos) /*!< 0x40000000 */
13728 #define RCC_CFGR_MCO2_1 (0x2U << RCC_CFGR_MCO2_Pos) /*!< 0x80000000 */
13729
13730 /******************** Bit definition for RCC_CIR register *******************/
13731 #define RCC_CIR_LSIRDYF_Pos (0U)
13732 #define RCC_CIR_LSIRDYF_Msk (0x1U << RCC_CIR_LSIRDYF_Pos) /*!< 0x00000001 */
13733 #define RCC_CIR_LSIRDYF RCC_CIR_LSIRDYF_Msk
13734 #define RCC_CIR_LSERDYF_Pos (1U)
13735 #define RCC_CIR_LSERDYF_Msk (0x1U << RCC_CIR_LSERDYF_Pos) /*!< 0x00000002 */
13736 #define RCC_CIR_LSERDYF RCC_CIR_LSERDYF_Msk
13737 #define RCC_CIR_HSIRDYF_Pos (2U)
13738 #define RCC_CIR_HSIRDYF_Msk (0x1U << RCC_CIR_HSIRDYF_Pos) /*!< 0x00000004 */
13739 #define RCC_CIR_HSIRDYF RCC_CIR_HSIRDYF_Msk
13740 #define RCC_CIR_HSERDYF_Pos (3U)
13741 #define RCC_CIR_HSERDYF_Msk (0x1U << RCC_CIR_HSERDYF_Pos) /*!< 0x00000008 */
13742 #define RCC_CIR_HSERDYF RCC_CIR_HSERDYF_Msk
13743 #define RCC_CIR_PLLRDYF_Pos (4U)
13744 #define RCC_CIR_PLLRDYF_Msk (0x1U << RCC_CIR_PLLRDYF_Pos) /*!< 0x00000010 */
13745 #define RCC_CIR_PLLRDYF RCC_CIR_PLLRDYF_Msk
13746 #define RCC_CIR_PLLI2SRDYF_Pos (5U)
13747 #define RCC_CIR_PLLI2SRDYF_Msk (0x1U << RCC_CIR_PLLI2SRDYF_Pos) /*!< 0x00000020 */
13748 #define RCC_CIR_PLLI2SRDYF RCC_CIR_PLLI2SRDYF_Msk
13749
13750 #define RCC_CIR_PLLSAIRDYF_Pos (6U)
13751 #define RCC_CIR_PLLSAIRDYF_Msk (0x1U << RCC_CIR_PLLSAIRDYF_Pos) /*!< 0x00000040 */
13752 #define RCC_CIR_PLLSAIRDYF RCC_CIR_PLLSAIRDYF_Msk
13753 #define RCC_CIR_CSSF_Pos (7U)
13754 #define RCC_CIR_CSSF_Msk (0x1U << RCC_CIR_CSSF_Pos) /*!< 0x00000080 */
13755 #define RCC_CIR_CSSF RCC_CIR_CSSF_Msk
13756 #define RCC_CIR_LSIRDYIE_Pos (8U)
13757 #define RCC_CIR_LSIRDYIE_Msk (0x1U << RCC_CIR_LSIRDYIE_Pos) /*!< 0x00000100 */
13758 #define RCC_CIR_LSIRDYIE RCC_CIR_LSIRDYIE_Msk
13759 #define RCC_CIR_LSERDYIE_Pos (9U)
13760 #define RCC_CIR_LSERDYIE_Msk (0x1U << RCC_CIR_LSERDYIE_Pos) /*!< 0x00000200 */
13761 #define RCC_CIR_LSERDYIE RCC_CIR_LSERDYIE_Msk
13762 #define RCC_CIR_HSIRDYIE_Pos (10U)
13763 #define RCC_CIR_HSIRDYIE_Msk (0x1U << RCC_CIR_HSIRDYIE_Pos) /*!< 0x00000400 */
13764 #define RCC_CIR_HSIRDYIE RCC_CIR_HSIRDYIE_Msk
13765 #define RCC_CIR_HSERDYIE_Pos (11U)
13766 #define RCC_CIR_HSERDYIE_Msk (0x1U << RCC_CIR_HSERDYIE_Pos) /*!< 0x00000800 */
13767 #define RCC_CIR_HSERDYIE RCC_CIR_HSERDYIE_Msk
13768 #define RCC_CIR_PLLRDYIE_Pos (12U)
13769 #define RCC_CIR_PLLRDYIE_Msk (0x1U << RCC_CIR_PLLRDYIE_Pos) /*!< 0x00001000 */
13770 #define RCC_CIR_PLLRDYIE RCC_CIR_PLLRDYIE_Msk
13771 #define RCC_CIR_PLLI2SRDYIE_Pos (13U)
13772 #define RCC_CIR_PLLI2SRDYIE_Msk (0x1U << RCC_CIR_PLLI2SRDYIE_Pos) /*!< 0x00002000 */
13773 #define RCC_CIR_PLLI2SRDYIE RCC_CIR_PLLI2SRDYIE_Msk
13774
13775 #define RCC_CIR_PLLSAIRDYIE_Pos (14U)
13776 #define RCC_CIR_PLLSAIRDYIE_Msk (0x1U << RCC_CIR_PLLSAIRDYIE_Pos) /*!< 0x00004000 */
13777 #define RCC_CIR_PLLSAIRDYIE RCC_CIR_PLLSAIRDYIE_Msk
13778 #define RCC_CIR_LSIRDYC_Pos (16U)
13779 #define RCC_CIR_LSIRDYC_Msk (0x1U << RCC_CIR_LSIRDYC_Pos) /*!< 0x00010000 */
13780 #define RCC_CIR_LSIRDYC RCC_CIR_LSIRDYC_Msk
13781 #define RCC_CIR_LSERDYC_Pos (17U)
13782 #define RCC_CIR_LSERDYC_Msk (0x1U << RCC_CIR_LSERDYC_Pos) /*!< 0x00020000 */
13783 #define RCC_CIR_LSERDYC RCC_CIR_LSERDYC_Msk
13784 #define RCC_CIR_HSIRDYC_Pos (18U)
13785 #define RCC_CIR_HSIRDYC_Msk (0x1U << RCC_CIR_HSIRDYC_Pos) /*!< 0x00040000 */
13786 #define RCC_CIR_HSIRDYC RCC_CIR_HSIRDYC_Msk
13787 #define RCC_CIR_HSERDYC_Pos (19U)
13788 #define RCC_CIR_HSERDYC_Msk (0x1U << RCC_CIR_HSERDYC_Pos) /*!< 0x00080000 */
13789 #define RCC_CIR_HSERDYC RCC_CIR_HSERDYC_Msk
13790 #define RCC_CIR_PLLRDYC_Pos (20U)
13791 #define RCC_CIR_PLLRDYC_Msk (0x1U << RCC_CIR_PLLRDYC_Pos) /*!< 0x00100000 */
13792 #define RCC_CIR_PLLRDYC RCC_CIR_PLLRDYC_Msk
13793 #define RCC_CIR_PLLI2SRDYC_Pos (21U)
13794 #define RCC_CIR_PLLI2SRDYC_Msk (0x1U << RCC_CIR_PLLI2SRDYC_Pos) /*!< 0x00200000 */
13795 #define RCC_CIR_PLLI2SRDYC RCC_CIR_PLLI2SRDYC_Msk
13796 #define RCC_CIR_PLLSAIRDYC_Pos (22U)
13797 #define RCC_CIR_PLLSAIRDYC_Msk (0x1U << RCC_CIR_PLLSAIRDYC_Pos) /*!< 0x00400000 */
13798 #define RCC_CIR_PLLSAIRDYC RCC_CIR_PLLSAIRDYC_Msk
13799
13800 #define RCC_CIR_CSSC_Pos (23U)
13801 #define RCC_CIR_CSSC_Msk (0x1U << RCC_CIR_CSSC_Pos) /*!< 0x00800000 */
13802 #define RCC_CIR_CSSC RCC_CIR_CSSC_Msk
13803
13804 /******************** Bit definition for RCC_AHB1RSTR register **************/
13805 #define RCC_AHB1RSTR_GPIOARST_Pos (0U)
13806 #define RCC_AHB1RSTR_GPIOARST_Msk (0x1U << RCC_AHB1RSTR_GPIOARST_Pos) /*!< 0x00000001 */
13807 #define RCC_AHB1RSTR_GPIOARST RCC_AHB1RSTR_GPIOARST_Msk
13808 #define RCC_AHB1RSTR_GPIOBRST_Pos (1U)
13809 #define RCC_AHB1RSTR_GPIOBRST_Msk (0x1U << RCC_AHB1RSTR_GPIOBRST_Pos) /*!< 0x00000002 */
13810 #define RCC_AHB1RSTR_GPIOBRST RCC_AHB1RSTR_GPIOBRST_Msk
13811 #define RCC_AHB1RSTR_GPIOCRST_Pos (2U)
13812 #define RCC_AHB1RSTR_GPIOCRST_Msk (0x1U << RCC_AHB1RSTR_GPIOCRST_Pos) /*!< 0x00000004 */
13813 #define RCC_AHB1RSTR_GPIOCRST RCC_AHB1RSTR_GPIOCRST_Msk
13814 #define RCC_AHB1RSTR_GPIODRST_Pos (3U)
13815 #define RCC_AHB1RSTR_GPIODRST_Msk (0x1U << RCC_AHB1RSTR_GPIODRST_Pos) /*!< 0x00000008 */
13816 #define RCC_AHB1RSTR_GPIODRST RCC_AHB1RSTR_GPIODRST_Msk
13817 #define RCC_AHB1RSTR_GPIOERST_Pos (4U)
13818 #define RCC_AHB1RSTR_GPIOERST_Msk (0x1U << RCC_AHB1RSTR_GPIOERST_Pos) /*!< 0x00000010 */
13819 #define RCC_AHB1RSTR_GPIOERST RCC_AHB1RSTR_GPIOERST_Msk
13820 #define RCC_AHB1RSTR_GPIOFRST_Pos (5U)
13821 #define RCC_AHB1RSTR_GPIOFRST_Msk (0x1U << RCC_AHB1RSTR_GPIOFRST_Pos) /*!< 0x00000020 */
13822 #define RCC_AHB1RSTR_GPIOFRST RCC_AHB1RSTR_GPIOFRST_Msk
13823 #define RCC_AHB1RSTR_GPIOGRST_Pos (6U)
13824 #define RCC_AHB1RSTR_GPIOGRST_Msk (0x1U << RCC_AHB1RSTR_GPIOGRST_Pos) /*!< 0x00000040 */
13825 #define RCC_AHB1RSTR_GPIOGRST RCC_AHB1RSTR_GPIOGRST_Msk
13826 #define RCC_AHB1RSTR_GPIOHRST_Pos (7U)
13827 #define RCC_AHB1RSTR_GPIOHRST_Msk (0x1U << RCC_AHB1RSTR_GPIOHRST_Pos) /*!< 0x00000080 */
13828 #define RCC_AHB1RSTR_GPIOHRST RCC_AHB1RSTR_GPIOHRST_Msk
13829 #define RCC_AHB1RSTR_GPIOIRST_Pos (8U)
13830 #define RCC_AHB1RSTR_GPIOIRST_Msk (0x1U << RCC_AHB1RSTR_GPIOIRST_Pos) /*!< 0x00000100 */
13831 #define RCC_AHB1RSTR_GPIOIRST RCC_AHB1RSTR_GPIOIRST_Msk
13832 #define RCC_AHB1RSTR_GPIOJRST_Pos (9U)
13833 #define RCC_AHB1RSTR_GPIOJRST_Msk (0x1U << RCC_AHB1RSTR_GPIOJRST_Pos) /*!< 0x00000200 */
13834 #define RCC_AHB1RSTR_GPIOJRST RCC_AHB1RSTR_GPIOJRST_Msk
13835 #define RCC_AHB1RSTR_GPIOKRST_Pos (10U)
13836 #define RCC_AHB1RSTR_GPIOKRST_Msk (0x1U << RCC_AHB1RSTR_GPIOKRST_Pos) /*!< 0x00000400 */
13837 #define RCC_AHB1RSTR_GPIOKRST RCC_AHB1RSTR_GPIOKRST_Msk
13838 #define RCC_AHB1RSTR_CRCRST_Pos (12U)
13839 #define RCC_AHB1RSTR_CRCRST_Msk (0x1U << RCC_AHB1RSTR_CRCRST_Pos) /*!< 0x00001000 */
13840 #define RCC_AHB1RSTR_CRCRST RCC_AHB1RSTR_CRCRST_Msk
13841 #define RCC_AHB1RSTR_DMA1RST_Pos (21U)
13842 #define RCC_AHB1RSTR_DMA1RST_Msk (0x1U << RCC_AHB1RSTR_DMA1RST_Pos) /*!< 0x00200000 */
13843 #define RCC_AHB1RSTR_DMA1RST RCC_AHB1RSTR_DMA1RST_Msk
13844 #define RCC_AHB1RSTR_DMA2RST_Pos (22U)
13845 #define RCC_AHB1RSTR_DMA2RST_Msk (0x1U << RCC_AHB1RSTR_DMA2RST_Pos) /*!< 0x00400000 */
13846 #define RCC_AHB1RSTR_DMA2RST RCC_AHB1RSTR_DMA2RST_Msk
13847 #define RCC_AHB1RSTR_DMA2DRST_Pos (23U)
13848 #define RCC_AHB1RSTR_DMA2DRST_Msk (0x1U << RCC_AHB1RSTR_DMA2DRST_Pos) /*!< 0x00800000 */
13849 #define RCC_AHB1RSTR_DMA2DRST RCC_AHB1RSTR_DMA2DRST_Msk
13850 #define RCC_AHB1RSTR_ETHMACRST_Pos (25U)
13851 #define RCC_AHB1RSTR_ETHMACRST_Msk (0x1U << RCC_AHB1RSTR_ETHMACRST_Pos) /*!< 0x02000000 */
13852 #define RCC_AHB1RSTR_ETHMACRST RCC_AHB1RSTR_ETHMACRST_Msk
13853 #define RCC_AHB1RSTR_OTGHRST_Pos (29U)
13854 #define RCC_AHB1RSTR_OTGHRST_Msk (0x1U << RCC_AHB1RSTR_OTGHRST_Pos) /*!< 0x20000000 */
13855 #define RCC_AHB1RSTR_OTGHRST RCC_AHB1RSTR_OTGHRST_Msk
13856
13857 /******************** Bit definition for RCC_AHB2RSTR register **************/
13858 #define RCC_AHB2RSTR_DCMIRST_Pos (0U)
13859 #define RCC_AHB2RSTR_DCMIRST_Msk (0x1U << RCC_AHB2RSTR_DCMIRST_Pos) /*!< 0x00000001 */
13860 #define RCC_AHB2RSTR_DCMIRST RCC_AHB2RSTR_DCMIRST_Msk
13861 #define RCC_AHB2RSTR_RNGRST_Pos (6U)
13862 #define RCC_AHB2RSTR_RNGRST_Msk (0x1U << RCC_AHB2RSTR_RNGRST_Pos) /*!< 0x00000040 */
13863 #define RCC_AHB2RSTR_RNGRST RCC_AHB2RSTR_RNGRST_Msk
13864 #define RCC_AHB2RSTR_OTGFSRST_Pos (7U)
13865 #define RCC_AHB2RSTR_OTGFSRST_Msk (0x1U << RCC_AHB2RSTR_OTGFSRST_Pos) /*!< 0x00000080 */
13866 #define RCC_AHB2RSTR_OTGFSRST RCC_AHB2RSTR_OTGFSRST_Msk
13867 /******************** Bit definition for RCC_AHB3RSTR register **************/
13868 #define RCC_AHB3RSTR_FMCRST_Pos (0U)
13869 #define RCC_AHB3RSTR_FMCRST_Msk (0x1U << RCC_AHB3RSTR_FMCRST_Pos) /*!< 0x00000001 */
13870 #define RCC_AHB3RSTR_FMCRST RCC_AHB3RSTR_FMCRST_Msk
13871 #define RCC_AHB3RSTR_QSPIRST_Pos (1U)
13872 #define RCC_AHB3RSTR_QSPIRST_Msk (0x1U << RCC_AHB3RSTR_QSPIRST_Pos) /*!< 0x00000002 */
13873 #define RCC_AHB3RSTR_QSPIRST RCC_AHB3RSTR_QSPIRST_Msk
13874
13875
13876 /******************** Bit definition for RCC_APB1RSTR register **************/
13877 #define RCC_APB1RSTR_TIM2RST_Pos (0U)
13878 #define RCC_APB1RSTR_TIM2RST_Msk (0x1U << RCC_APB1RSTR_TIM2RST_Pos) /*!< 0x00000001 */
13879 #define RCC_APB1RSTR_TIM2RST RCC_APB1RSTR_TIM2RST_Msk
13880 #define RCC_APB1RSTR_TIM3RST_Pos (1U)
13881 #define RCC_APB1RSTR_TIM3RST_Msk (0x1U << RCC_APB1RSTR_TIM3RST_Pos) /*!< 0x00000002 */
13882 #define RCC_APB1RSTR_TIM3RST RCC_APB1RSTR_TIM3RST_Msk
13883 #define RCC_APB1RSTR_TIM4RST_Pos (2U)
13884 #define RCC_APB1RSTR_TIM4RST_Msk (0x1U << RCC_APB1RSTR_TIM4RST_Pos) /*!< 0x00000004 */
13885 #define RCC_APB1RSTR_TIM4RST RCC_APB1RSTR_TIM4RST_Msk
13886 #define RCC_APB1RSTR_TIM5RST_Pos (3U)
13887 #define RCC_APB1RSTR_TIM5RST_Msk (0x1U << RCC_APB1RSTR_TIM5RST_Pos) /*!< 0x00000008 */
13888 #define RCC_APB1RSTR_TIM5RST RCC_APB1RSTR_TIM5RST_Msk
13889 #define RCC_APB1RSTR_TIM6RST_Pos (4U)
13890 #define RCC_APB1RSTR_TIM6RST_Msk (0x1U << RCC_APB1RSTR_TIM6RST_Pos) /*!< 0x00000010 */
13891 #define RCC_APB1RSTR_TIM6RST RCC_APB1RSTR_TIM6RST_Msk
13892 #define RCC_APB1RSTR_TIM7RST_Pos (5U)
13893 #define RCC_APB1RSTR_TIM7RST_Msk (0x1U << RCC_APB1RSTR_TIM7RST_Pos) /*!< 0x00000020 */
13894 #define RCC_APB1RSTR_TIM7RST RCC_APB1RSTR_TIM7RST_Msk
13895 #define RCC_APB1RSTR_TIM12RST_Pos (6U)
13896 #define RCC_APB1RSTR_TIM12RST_Msk (0x1U << RCC_APB1RSTR_TIM12RST_Pos) /*!< 0x00000040 */
13897 #define RCC_APB1RSTR_TIM12RST RCC_APB1RSTR_TIM12RST_Msk
13898 #define RCC_APB1RSTR_TIM13RST_Pos (7U)
13899 #define RCC_APB1RSTR_TIM13RST_Msk (0x1U << RCC_APB1RSTR_TIM13RST_Pos) /*!< 0x00000080 */
13900 #define RCC_APB1RSTR_TIM13RST RCC_APB1RSTR_TIM13RST_Msk
13901 #define RCC_APB1RSTR_TIM14RST_Pos (8U)
13902 #define RCC_APB1RSTR_TIM14RST_Msk (0x1U << RCC_APB1RSTR_TIM14RST_Pos) /*!< 0x00000100 */
13903 #define RCC_APB1RSTR_TIM14RST RCC_APB1RSTR_TIM14RST_Msk
13904 #define RCC_APB1RSTR_WWDGRST_Pos (11U)
13905 #define RCC_APB1RSTR_WWDGRST_Msk (0x1U << RCC_APB1RSTR_WWDGRST_Pos) /*!< 0x00000800 */
13906 #define RCC_APB1RSTR_WWDGRST RCC_APB1RSTR_WWDGRST_Msk
13907 #define RCC_APB1RSTR_SPI2RST_Pos (14U)
13908 #define RCC_APB1RSTR_SPI2RST_Msk (0x1U << RCC_APB1RSTR_SPI2RST_Pos) /*!< 0x00004000 */
13909 #define RCC_APB1RSTR_SPI2RST RCC_APB1RSTR_SPI2RST_Msk
13910 #define RCC_APB1RSTR_SPI3RST_Pos (15U)
13911 #define RCC_APB1RSTR_SPI3RST_Msk (0x1U << RCC_APB1RSTR_SPI3RST_Pos) /*!< 0x00008000 */
13912 #define RCC_APB1RSTR_SPI3RST RCC_APB1RSTR_SPI3RST_Msk
13913 #define RCC_APB1RSTR_USART2RST_Pos (17U)
13914 #define RCC_APB1RSTR_USART2RST_Msk (0x1U << RCC_APB1RSTR_USART2RST_Pos) /*!< 0x00020000 */
13915 #define RCC_APB1RSTR_USART2RST RCC_APB1RSTR_USART2RST_Msk
13916 #define RCC_APB1RSTR_USART3RST_Pos (18U)
13917 #define RCC_APB1RSTR_USART3RST_Msk (0x1U << RCC_APB1RSTR_USART3RST_Pos) /*!< 0x00040000 */
13918 #define RCC_APB1RSTR_USART3RST RCC_APB1RSTR_USART3RST_Msk
13919 #define RCC_APB1RSTR_UART4RST_Pos (19U)
13920 #define RCC_APB1RSTR_UART4RST_Msk (0x1U << RCC_APB1RSTR_UART4RST_Pos) /*!< 0x00080000 */
13921 #define RCC_APB1RSTR_UART4RST RCC_APB1RSTR_UART4RST_Msk
13922 #define RCC_APB1RSTR_UART5RST_Pos (20U)
13923 #define RCC_APB1RSTR_UART5RST_Msk (0x1U << RCC_APB1RSTR_UART5RST_Pos) /*!< 0x00100000 */
13924 #define RCC_APB1RSTR_UART5RST RCC_APB1RSTR_UART5RST_Msk
13925 #define RCC_APB1RSTR_I2C1RST_Pos (21U)
13926 #define RCC_APB1RSTR_I2C1RST_Msk (0x1U << RCC_APB1RSTR_I2C1RST_Pos) /*!< 0x00200000 */
13927 #define RCC_APB1RSTR_I2C1RST RCC_APB1RSTR_I2C1RST_Msk
13928 #define RCC_APB1RSTR_I2C2RST_Pos (22U)
13929 #define RCC_APB1RSTR_I2C2RST_Msk (0x1U << RCC_APB1RSTR_I2C2RST_Pos) /*!< 0x00400000 */
13930 #define RCC_APB1RSTR_I2C2RST RCC_APB1RSTR_I2C2RST_Msk
13931 #define RCC_APB1RSTR_I2C3RST_Pos (23U)
13932 #define RCC_APB1RSTR_I2C3RST_Msk (0x1U << RCC_APB1RSTR_I2C3RST_Pos) /*!< 0x00800000 */
13933 #define RCC_APB1RSTR_I2C3RST RCC_APB1RSTR_I2C3RST_Msk
13934 #define RCC_APB1RSTR_CAN1RST_Pos (25U)
13935 #define RCC_APB1RSTR_CAN1RST_Msk (0x1U << RCC_APB1RSTR_CAN1RST_Pos) /*!< 0x02000000 */
13936 #define RCC_APB1RSTR_CAN1RST RCC_APB1RSTR_CAN1RST_Msk
13937 #define RCC_APB1RSTR_CAN2RST_Pos (26U)
13938 #define RCC_APB1RSTR_CAN2RST_Msk (0x1U << RCC_APB1RSTR_CAN2RST_Pos) /*!< 0x04000000 */
13939 #define RCC_APB1RSTR_CAN2RST RCC_APB1RSTR_CAN2RST_Msk
13940 #define RCC_APB1RSTR_PWRRST_Pos (28U)
13941 #define RCC_APB1RSTR_PWRRST_Msk (0x1U << RCC_APB1RSTR_PWRRST_Pos) /*!< 0x10000000 */
13942 #define RCC_APB1RSTR_PWRRST RCC_APB1RSTR_PWRRST_Msk
13943 #define RCC_APB1RSTR_DACRST_Pos (29U)
13944 #define RCC_APB1RSTR_DACRST_Msk (0x1U << RCC_APB1RSTR_DACRST_Pos) /*!< 0x20000000 */
13945 #define RCC_APB1RSTR_DACRST RCC_APB1RSTR_DACRST_Msk
13946 #define RCC_APB1RSTR_UART7RST_Pos (30U)
13947 #define RCC_APB1RSTR_UART7RST_Msk (0x1U << RCC_APB1RSTR_UART7RST_Pos) /*!< 0x40000000 */
13948 #define RCC_APB1RSTR_UART7RST RCC_APB1RSTR_UART7RST_Msk
13949 #define RCC_APB1RSTR_UART8RST_Pos (31U)
13950 #define RCC_APB1RSTR_UART8RST_Msk (0x1U << RCC_APB1RSTR_UART8RST_Pos) /*!< 0x80000000 */
13951 #define RCC_APB1RSTR_UART8RST RCC_APB1RSTR_UART8RST_Msk
13952
13953 /******************** Bit definition for RCC_APB2RSTR register **************/
13954 #define RCC_APB2RSTR_TIM1RST_Pos (0U)
13955 #define RCC_APB2RSTR_TIM1RST_Msk (0x1U << RCC_APB2RSTR_TIM1RST_Pos) /*!< 0x00000001 */
13956 #define RCC_APB2RSTR_TIM1RST RCC_APB2RSTR_TIM1RST_Msk
13957 #define RCC_APB2RSTR_TIM8RST_Pos (1U)
13958 #define RCC_APB2RSTR_TIM8RST_Msk (0x1U << RCC_APB2RSTR_TIM8RST_Pos) /*!< 0x00000002 */
13959 #define RCC_APB2RSTR_TIM8RST RCC_APB2RSTR_TIM8RST_Msk
13960 #define RCC_APB2RSTR_USART1RST_Pos (4U)
13961 #define RCC_APB2RSTR_USART1RST_Msk (0x1U << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00000010 */
13962 #define RCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_Msk
13963 #define RCC_APB2RSTR_USART6RST_Pos (5U)
13964 #define RCC_APB2RSTR_USART6RST_Msk (0x1U << RCC_APB2RSTR_USART6RST_Pos) /*!< 0x00000020 */
13965 #define RCC_APB2RSTR_USART6RST RCC_APB2RSTR_USART6RST_Msk
13966 #define RCC_APB2RSTR_ADCRST_Pos (8U)
13967 #define RCC_APB2RSTR_ADCRST_Msk (0x1U << RCC_APB2RSTR_ADCRST_Pos) /*!< 0x00000100 */
13968 #define RCC_APB2RSTR_ADCRST RCC_APB2RSTR_ADCRST_Msk
13969 #define RCC_APB2RSTR_SDIORST_Pos (11U)
13970 #define RCC_APB2RSTR_SDIORST_Msk (0x1U << RCC_APB2RSTR_SDIORST_Pos) /*!< 0x00000800 */
13971 #define RCC_APB2RSTR_SDIORST RCC_APB2RSTR_SDIORST_Msk
13972 #define RCC_APB2RSTR_SPI1RST_Pos (12U)
13973 #define RCC_APB2RSTR_SPI1RST_Msk (0x1U << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */
13974 #define RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk
13975 #define RCC_APB2RSTR_SPI4RST_Pos (13U)
13976 #define RCC_APB2RSTR_SPI4RST_Msk (0x1U << RCC_APB2RSTR_SPI4RST_Pos) /*!< 0x00002000 */
13977 #define RCC_APB2RSTR_SPI4RST RCC_APB2RSTR_SPI4RST_Msk
13978 #define RCC_APB2RSTR_SYSCFGRST_Pos (14U)
13979 #define RCC_APB2RSTR_SYSCFGRST_Msk (0x1U << RCC_APB2RSTR_SYSCFGRST_Pos) /*!< 0x00004000 */
13980 #define RCC_APB2RSTR_SYSCFGRST RCC_APB2RSTR_SYSCFGRST_Msk
13981 #define RCC_APB2RSTR_TIM9RST_Pos (16U)
13982 #define RCC_APB2RSTR_TIM9RST_Msk (0x1U << RCC_APB2RSTR_TIM9RST_Pos) /*!< 0x00010000 */
13983 #define RCC_APB2RSTR_TIM9RST RCC_APB2RSTR_TIM9RST_Msk
13984 #define RCC_APB2RSTR_TIM10RST_Pos (17U)
13985 #define RCC_APB2RSTR_TIM10RST_Msk (0x1U << RCC_APB2RSTR_TIM10RST_Pos) /*!< 0x00020000 */
13986 #define RCC_APB2RSTR_TIM10RST RCC_APB2RSTR_TIM10RST_Msk
13987 #define RCC_APB2RSTR_TIM11RST_Pos (18U)
13988 #define RCC_APB2RSTR_TIM11RST_Msk (0x1U << RCC_APB2RSTR_TIM11RST_Pos) /*!< 0x00040000 */
13989 #define RCC_APB2RSTR_TIM11RST RCC_APB2RSTR_TIM11RST_Msk
13990 #define RCC_APB2RSTR_SPI5RST_Pos (20U)
13991 #define RCC_APB2RSTR_SPI5RST_Msk (0x1U << RCC_APB2RSTR_SPI5RST_Pos) /*!< 0x00100000 */
13992 #define RCC_APB2RSTR_SPI5RST RCC_APB2RSTR_SPI5RST_Msk
13993 #define RCC_APB2RSTR_SPI6RST_Pos (21U)
13994 #define RCC_APB2RSTR_SPI6RST_Msk (0x1U << RCC_APB2RSTR_SPI6RST_Pos) /*!< 0x00200000 */
13995 #define RCC_APB2RSTR_SPI6RST RCC_APB2RSTR_SPI6RST_Msk
13996 #define RCC_APB2RSTR_SAI1RST_Pos (22U)
13997 #define RCC_APB2RSTR_SAI1RST_Msk (0x1U << RCC_APB2RSTR_SAI1RST_Pos) /*!< 0x00400000 */
13998 #define RCC_APB2RSTR_SAI1RST RCC_APB2RSTR_SAI1RST_Msk
13999 #define RCC_APB2RSTR_LTDCRST_Pos (26U)
14000 #define RCC_APB2RSTR_LTDCRST_Msk (0x1U << RCC_APB2RSTR_LTDCRST_Pos) /*!< 0x04000000 */
14001 #define RCC_APB2RSTR_LTDCRST RCC_APB2RSTR_LTDCRST_Msk
14002 #define RCC_APB2RSTR_DSIRST_Pos (27U)
14003 #define RCC_APB2RSTR_DSIRST_Msk (0x1U << RCC_APB2RSTR_DSIRST_Pos) /*!< 0x08000000 */
14004 #define RCC_APB2RSTR_DSIRST RCC_APB2RSTR_DSIRST_Msk
14005
14006 /* Old SPI1RST bit definition, maintained for legacy purpose */
14007 #define RCC_APB2RSTR_SPI1 RCC_APB2RSTR_SPI1RST
14008
14009 /******************** Bit definition for RCC_AHB1ENR register ***************/
14010 #define RCC_AHB1ENR_GPIOAEN_Pos (0U)
14011 #define RCC_AHB1ENR_GPIOAEN_Msk (0x1U << RCC_AHB1ENR_GPIOAEN_Pos) /*!< 0x00000001 */
14012 #define RCC_AHB1ENR_GPIOAEN RCC_AHB1ENR_GPIOAEN_Msk
14013 #define RCC_AHB1ENR_GPIOBEN_Pos (1U)
14014 #define RCC_AHB1ENR_GPIOBEN_Msk (0x1U << RCC_AHB1ENR_GPIOBEN_Pos) /*!< 0x00000002 */
14015 #define RCC_AHB1ENR_GPIOBEN RCC_AHB1ENR_GPIOBEN_Msk
14016 #define RCC_AHB1ENR_GPIOCEN_Pos (2U)
14017 #define RCC_AHB1ENR_GPIOCEN_Msk (0x1U << RCC_AHB1ENR_GPIOCEN_Pos) /*!< 0x00000004 */
14018 #define RCC_AHB1ENR_GPIOCEN RCC_AHB1ENR_GPIOCEN_Msk
14019 #define RCC_AHB1ENR_GPIODEN_Pos (3U)
14020 #define RCC_AHB1ENR_GPIODEN_Msk (0x1U << RCC_AHB1ENR_GPIODEN_Pos) /*!< 0x00000008 */
14021 #define RCC_AHB1ENR_GPIODEN RCC_AHB1ENR_GPIODEN_Msk
14022 #define RCC_AHB1ENR_GPIOEEN_Pos (4U)
14023 #define RCC_AHB1ENR_GPIOEEN_Msk (0x1U << RCC_AHB1ENR_GPIOEEN_Pos) /*!< 0x00000010 */
14024 #define RCC_AHB1ENR_GPIOEEN RCC_AHB1ENR_GPIOEEN_Msk
14025 #define RCC_AHB1ENR_GPIOFEN_Pos (5U)
14026 #define RCC_AHB1ENR_GPIOFEN_Msk (0x1U << RCC_AHB1ENR_GPIOFEN_Pos) /*!< 0x00000020 */
14027 #define RCC_AHB1ENR_GPIOFEN RCC_AHB1ENR_GPIOFEN_Msk
14028 #define RCC_AHB1ENR_GPIOGEN_Pos (6U)
14029 #define RCC_AHB1ENR_GPIOGEN_Msk (0x1U << RCC_AHB1ENR_GPIOGEN_Pos) /*!< 0x00000040 */
14030 #define RCC_AHB1ENR_GPIOGEN RCC_AHB1ENR_GPIOGEN_Msk
14031 #define RCC_AHB1ENR_GPIOHEN_Pos (7U)
14032 #define RCC_AHB1ENR_GPIOHEN_Msk (0x1U << RCC_AHB1ENR_GPIOHEN_Pos) /*!< 0x00000080 */
14033 #define RCC_AHB1ENR_GPIOHEN RCC_AHB1ENR_GPIOHEN_Msk
14034 #define RCC_AHB1ENR_GPIOIEN_Pos (8U)
14035 #define RCC_AHB1ENR_GPIOIEN_Msk (0x1U << RCC_AHB1ENR_GPIOIEN_Pos) /*!< 0x00000100 */
14036 #define RCC_AHB1ENR_GPIOIEN RCC_AHB1ENR_GPIOIEN_Msk
14037 #define RCC_AHB1ENR_GPIOJEN_Pos (9U)
14038 #define RCC_AHB1ENR_GPIOJEN_Msk (0x1U << RCC_AHB1ENR_GPIOJEN_Pos) /*!< 0x00000200 */
14039 #define RCC_AHB1ENR_GPIOJEN RCC_AHB1ENR_GPIOJEN_Msk
14040 #define RCC_AHB1ENR_GPIOKEN_Pos (10U)
14041 #define RCC_AHB1ENR_GPIOKEN_Msk (0x1U << RCC_AHB1ENR_GPIOKEN_Pos) /*!< 0x00000400 */
14042 #define RCC_AHB1ENR_GPIOKEN RCC_AHB1ENR_GPIOKEN_Msk
14043 #define RCC_AHB1ENR_CRCEN_Pos (12U)
14044 #define RCC_AHB1ENR_CRCEN_Msk (0x1U << RCC_AHB1ENR_CRCEN_Pos) /*!< 0x00001000 */
14045 #define RCC_AHB1ENR_CRCEN RCC_AHB1ENR_CRCEN_Msk
14046 #define RCC_AHB1ENR_BKPSRAMEN_Pos (18U)
14047 #define RCC_AHB1ENR_BKPSRAMEN_Msk (0x1U << RCC_AHB1ENR_BKPSRAMEN_Pos) /*!< 0x00040000 */
14048 #define RCC_AHB1ENR_BKPSRAMEN RCC_AHB1ENR_BKPSRAMEN_Msk
14049 #define RCC_AHB1ENR_CCMDATARAMEN_Pos (20U)
14050 #define RCC_AHB1ENR_CCMDATARAMEN_Msk (0x1U << RCC_AHB1ENR_CCMDATARAMEN_Pos) /*!< 0x00100000 */
14051 #define RCC_AHB1ENR_CCMDATARAMEN RCC_AHB1ENR_CCMDATARAMEN_Msk
14052 #define RCC_AHB1ENR_DMA1EN_Pos (21U)
14053 #define RCC_AHB1ENR_DMA1EN_Msk (0x1U << RCC_AHB1ENR_DMA1EN_Pos) /*!< 0x00200000 */
14054 #define RCC_AHB1ENR_DMA1EN RCC_AHB1ENR_DMA1EN_Msk
14055 #define RCC_AHB1ENR_DMA2EN_Pos (22U)
14056 #define RCC_AHB1ENR_DMA2EN_Msk (0x1U << RCC_AHB1ENR_DMA2EN_Pos) /*!< 0x00400000 */
14057 #define RCC_AHB1ENR_DMA2EN RCC_AHB1ENR_DMA2EN_Msk
14058 #define RCC_AHB1ENR_DMA2DEN_Pos (23U)
14059 #define RCC_AHB1ENR_DMA2DEN_Msk (0x1U << RCC_AHB1ENR_DMA2DEN_Pos) /*!< 0x00800000 */
14060 #define RCC_AHB1ENR_DMA2DEN RCC_AHB1ENR_DMA2DEN_Msk
14061 #define RCC_AHB1ENR_ETHMACEN_Pos (25U)
14062 #define RCC_AHB1ENR_ETHMACEN_Msk (0x1U << RCC_AHB1ENR_ETHMACEN_Pos) /*!< 0x02000000 */
14063 #define RCC_AHB1ENR_ETHMACEN RCC_AHB1ENR_ETHMACEN_Msk
14064 #define RCC_AHB1ENR_ETHMACTXEN_Pos (26U)
14065 #define RCC_AHB1ENR_ETHMACTXEN_Msk (0x1U << RCC_AHB1ENR_ETHMACTXEN_Pos) /*!< 0x04000000 */
14066 #define RCC_AHB1ENR_ETHMACTXEN RCC_AHB1ENR_ETHMACTXEN_Msk
14067 #define RCC_AHB1ENR_ETHMACRXEN_Pos (27U)
14068 #define RCC_AHB1ENR_ETHMACRXEN_Msk (0x1U << RCC_AHB1ENR_ETHMACRXEN_Pos) /*!< 0x08000000 */
14069 #define RCC_AHB1ENR_ETHMACRXEN RCC_AHB1ENR_ETHMACRXEN_Msk
14070 #define RCC_AHB1ENR_ETHMACPTPEN_Pos (28U)
14071 #define RCC_AHB1ENR_ETHMACPTPEN_Msk (0x1U << RCC_AHB1ENR_ETHMACPTPEN_Pos) /*!< 0x10000000 */
14072 #define RCC_AHB1ENR_ETHMACPTPEN RCC_AHB1ENR_ETHMACPTPEN_Msk
14073 #define RCC_AHB1ENR_OTGHSEN_Pos (29U)
14074 #define RCC_AHB1ENR_OTGHSEN_Msk (0x1U << RCC_AHB1ENR_OTGHSEN_Pos) /*!< 0x20000000 */
14075 #define RCC_AHB1ENR_OTGHSEN RCC_AHB1ENR_OTGHSEN_Msk
14076 #define RCC_AHB1ENR_OTGHSULPIEN_Pos (30U)
14077 #define RCC_AHB1ENR_OTGHSULPIEN_Msk (0x1U << RCC_AHB1ENR_OTGHSULPIEN_Pos) /*!< 0x40000000 */
14078 #define RCC_AHB1ENR_OTGHSULPIEN RCC_AHB1ENR_OTGHSULPIEN_Msk
14079 /******************** Bit definition for RCC_AHB2ENR register ***************/
14080 /*
14081 * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
14082 */
14083 #define RCC_AHB2_SUPPORT /*!< AHB2 Bus is supported */
14084
14085 #define RCC_AHB2ENR_DCMIEN_Pos (0U)
14086 #define RCC_AHB2ENR_DCMIEN_Msk (0x1U << RCC_AHB2ENR_DCMIEN_Pos) /*!< 0x00000001 */
14087 #define RCC_AHB2ENR_DCMIEN RCC_AHB2ENR_DCMIEN_Msk
14088 #define RCC_AHB2ENR_RNGEN_Pos (6U)
14089 #define RCC_AHB2ENR_RNGEN_Msk (0x1U << RCC_AHB2ENR_RNGEN_Pos) /*!< 0x00000040 */
14090 #define RCC_AHB2ENR_RNGEN RCC_AHB2ENR_RNGEN_Msk
14091 #define RCC_AHB2ENR_OTGFSEN_Pos (7U)
14092 #define RCC_AHB2ENR_OTGFSEN_Msk (0x1U << RCC_AHB2ENR_OTGFSEN_Pos) /*!< 0x00000080 */
14093 #define RCC_AHB2ENR_OTGFSEN RCC_AHB2ENR_OTGFSEN_Msk
14094
14095 /******************** Bit definition for RCC_AHB3ENR register ***************/
14096 /*
14097 * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
14098 */
14099 #define RCC_AHB3_SUPPORT /*!< AHB3 Bus is supported */
14100
14101 #define RCC_AHB3ENR_FMCEN_Pos (0U)
14102 #define RCC_AHB3ENR_FMCEN_Msk (0x1U << RCC_AHB3ENR_FMCEN_Pos) /*!< 0x00000001 */
14103 #define RCC_AHB3ENR_FMCEN RCC_AHB3ENR_FMCEN_Msk
14104 #define RCC_AHB3ENR_QSPIEN_Pos (1U)
14105 #define RCC_AHB3ENR_QSPIEN_Msk (0x1U << RCC_AHB3ENR_QSPIEN_Pos) /*!< 0x00000002 */
14106 #define RCC_AHB3ENR_QSPIEN RCC_AHB3ENR_QSPIEN_Msk
14107
14108 /******************** Bit definition for RCC_APB1ENR register ***************/
14109 #define RCC_APB1ENR_TIM2EN_Pos (0U)
14110 #define RCC_APB1ENR_TIM2EN_Msk (0x1U << RCC_APB1ENR_TIM2EN_Pos) /*!< 0x00000001 */
14111 #define RCC_APB1ENR_TIM2EN RCC_APB1ENR_TIM2EN_Msk
14112 #define RCC_APB1ENR_TIM3EN_Pos (1U)
14113 #define RCC_APB1ENR_TIM3EN_Msk (0x1U << RCC_APB1ENR_TIM3EN_Pos) /*!< 0x00000002 */
14114 #define RCC_APB1ENR_TIM3EN RCC_APB1ENR_TIM3EN_Msk
14115 #define RCC_APB1ENR_TIM4EN_Pos (2U)
14116 #define RCC_APB1ENR_TIM4EN_Msk (0x1U << RCC_APB1ENR_TIM4EN_Pos) /*!< 0x00000004 */
14117 #define RCC_APB1ENR_TIM4EN RCC_APB1ENR_TIM4EN_Msk
14118 #define RCC_APB1ENR_TIM5EN_Pos (3U)
14119 #define RCC_APB1ENR_TIM5EN_Msk (0x1U << RCC_APB1ENR_TIM5EN_Pos) /*!< 0x00000008 */
14120 #define RCC_APB1ENR_TIM5EN RCC_APB1ENR_TIM5EN_Msk
14121 #define RCC_APB1ENR_TIM6EN_Pos (4U)
14122 #define RCC_APB1ENR_TIM6EN_Msk (0x1U << RCC_APB1ENR_TIM6EN_Pos) /*!< 0x00000010 */
14123 #define RCC_APB1ENR_TIM6EN RCC_APB1ENR_TIM6EN_Msk
14124 #define RCC_APB1ENR_TIM7EN_Pos (5U)
14125 #define RCC_APB1ENR_TIM7EN_Msk (0x1U << RCC_APB1ENR_TIM7EN_Pos) /*!< 0x00000020 */
14126 #define RCC_APB1ENR_TIM7EN RCC_APB1ENR_TIM7EN_Msk
14127 #define RCC_APB1ENR_TIM12EN_Pos (6U)
14128 #define RCC_APB1ENR_TIM12EN_Msk (0x1U << RCC_APB1ENR_TIM12EN_Pos) /*!< 0x00000040 */
14129 #define RCC_APB1ENR_TIM12EN RCC_APB1ENR_TIM12EN_Msk
14130 #define RCC_APB1ENR_TIM13EN_Pos (7U)
14131 #define RCC_APB1ENR_TIM13EN_Msk (0x1U << RCC_APB1ENR_TIM13EN_Pos) /*!< 0x00000080 */
14132 #define RCC_APB1ENR_TIM13EN RCC_APB1ENR_TIM13EN_Msk
14133 #define RCC_APB1ENR_TIM14EN_Pos (8U)
14134 #define RCC_APB1ENR_TIM14EN_Msk (0x1U << RCC_APB1ENR_TIM14EN_Pos) /*!< 0x00000100 */
14135 #define RCC_APB1ENR_TIM14EN RCC_APB1ENR_TIM14EN_Msk
14136 #define RCC_APB1ENR_WWDGEN_Pos (11U)
14137 #define RCC_APB1ENR_WWDGEN_Msk (0x1U << RCC_APB1ENR_WWDGEN_Pos) /*!< 0x00000800 */
14138 #define RCC_APB1ENR_WWDGEN RCC_APB1ENR_WWDGEN_Msk
14139 #define RCC_APB1ENR_SPI2EN_Pos (14U)
14140 #define RCC_APB1ENR_SPI2EN_Msk (0x1U << RCC_APB1ENR_SPI2EN_Pos) /*!< 0x00004000 */
14141 #define RCC_APB1ENR_SPI2EN RCC_APB1ENR_SPI2EN_Msk
14142 #define RCC_APB1ENR_SPI3EN_Pos (15U)
14143 #define RCC_APB1ENR_SPI3EN_Msk (0x1U << RCC_APB1ENR_SPI3EN_Pos) /*!< 0x00008000 */
14144 #define RCC_APB1ENR_SPI3EN RCC_APB1ENR_SPI3EN_Msk
14145 #define RCC_APB1ENR_USART2EN_Pos (17U)
14146 #define RCC_APB1ENR_USART2EN_Msk (0x1U << RCC_APB1ENR_USART2EN_Pos) /*!< 0x00020000 */
14147 #define RCC_APB1ENR_USART2EN RCC_APB1ENR_USART2EN_Msk
14148 #define RCC_APB1ENR_USART3EN_Pos (18U)
14149 #define RCC_APB1ENR_USART3EN_Msk (0x1U << RCC_APB1ENR_USART3EN_Pos) /*!< 0x00040000 */
14150 #define RCC_APB1ENR_USART3EN RCC_APB1ENR_USART3EN_Msk
14151 #define RCC_APB1ENR_UART4EN_Pos (19U)
14152 #define RCC_APB1ENR_UART4EN_Msk (0x1U << RCC_APB1ENR_UART4EN_Pos) /*!< 0x00080000 */
14153 #define RCC_APB1ENR_UART4EN RCC_APB1ENR_UART4EN_Msk
14154 #define RCC_APB1ENR_UART5EN_Pos (20U)
14155 #define RCC_APB1ENR_UART5EN_Msk (0x1U << RCC_APB1ENR_UART5EN_Pos) /*!< 0x00100000 */
14156 #define RCC_APB1ENR_UART5EN RCC_APB1ENR_UART5EN_Msk
14157 #define RCC_APB1ENR_I2C1EN_Pos (21U)
14158 #define RCC_APB1ENR_I2C1EN_Msk (0x1U << RCC_APB1ENR_I2C1EN_Pos) /*!< 0x00200000 */
14159 #define RCC_APB1ENR_I2C1EN RCC_APB1ENR_I2C1EN_Msk
14160 #define RCC_APB1ENR_I2C2EN_Pos (22U)
14161 #define RCC_APB1ENR_I2C2EN_Msk (0x1U << RCC_APB1ENR_I2C2EN_Pos) /*!< 0x00400000 */
14162 #define RCC_APB1ENR_I2C2EN RCC_APB1ENR_I2C2EN_Msk
14163 #define RCC_APB1ENR_I2C3EN_Pos (23U)
14164 #define RCC_APB1ENR_I2C3EN_Msk (0x1U << RCC_APB1ENR_I2C3EN_Pos) /*!< 0x00800000 */
14165 #define RCC_APB1ENR_I2C3EN RCC_APB1ENR_I2C3EN_Msk
14166 #define RCC_APB1ENR_CAN1EN_Pos (25U)
14167 #define RCC_APB1ENR_CAN1EN_Msk (0x1U << RCC_APB1ENR_CAN1EN_Pos) /*!< 0x02000000 */
14168 #define RCC_APB1ENR_CAN1EN RCC_APB1ENR_CAN1EN_Msk
14169 #define RCC_APB1ENR_CAN2EN_Pos (26U)
14170 #define RCC_APB1ENR_CAN2EN_Msk (0x1U << RCC_APB1ENR_CAN2EN_Pos) /*!< 0x04000000 */
14171 #define RCC_APB1ENR_CAN2EN RCC_APB1ENR_CAN2EN_Msk
14172 #define RCC_APB1ENR_PWREN_Pos (28U)
14173 #define RCC_APB1ENR_PWREN_Msk (0x1U << RCC_APB1ENR_PWREN_Pos) /*!< 0x10000000 */
14174 #define RCC_APB1ENR_PWREN RCC_APB1ENR_PWREN_Msk
14175 #define RCC_APB1ENR_DACEN_Pos (29U)
14176 #define RCC_APB1ENR_DACEN_Msk (0x1U << RCC_APB1ENR_DACEN_Pos) /*!< 0x20000000 */
14177 #define RCC_APB1ENR_DACEN RCC_APB1ENR_DACEN_Msk
14178 #define RCC_APB1ENR_UART7EN_Pos (30U)
14179 #define RCC_APB1ENR_UART7EN_Msk (0x1U << RCC_APB1ENR_UART7EN_Pos) /*!< 0x40000000 */
14180 #define RCC_APB1ENR_UART7EN RCC_APB1ENR_UART7EN_Msk
14181 #define RCC_APB1ENR_UART8EN_Pos (31U)
14182 #define RCC_APB1ENR_UART8EN_Msk (0x1U << RCC_APB1ENR_UART8EN_Pos) /*!< 0x80000000 */
14183 #define RCC_APB1ENR_UART8EN RCC_APB1ENR_UART8EN_Msk
14184
14185 /******************** Bit definition for RCC_APB2ENR register ***************/
14186 #define RCC_APB2ENR_TIM1EN_Pos (0U)
14187 #define RCC_APB2ENR_TIM1EN_Msk (0x1U << RCC_APB2ENR_TIM1EN_Pos) /*!< 0x00000001 */
14188 #define RCC_APB2ENR_TIM1EN RCC_APB2ENR_TIM1EN_Msk
14189 #define RCC_APB2ENR_TIM8EN_Pos (1U)
14190 #define RCC_APB2ENR_TIM8EN_Msk (0x1U << RCC_APB2ENR_TIM8EN_Pos) /*!< 0x00000002 */
14191 #define RCC_APB2ENR_TIM8EN RCC_APB2ENR_TIM8EN_Msk
14192 #define RCC_APB2ENR_USART1EN_Pos (4U)
14193 #define RCC_APB2ENR_USART1EN_Msk (0x1U << RCC_APB2ENR_USART1EN_Pos) /*!< 0x00000010 */
14194 #define RCC_APB2ENR_USART1EN RCC_APB2ENR_USART1EN_Msk
14195 #define RCC_APB2ENR_USART6EN_Pos (5U)
14196 #define RCC_APB2ENR_USART6EN_Msk (0x1U << RCC_APB2ENR_USART6EN_Pos) /*!< 0x00000020 */
14197 #define RCC_APB2ENR_USART6EN RCC_APB2ENR_USART6EN_Msk
14198 #define RCC_APB2ENR_ADC1EN_Pos (8U)
14199 #define RCC_APB2ENR_ADC1EN_Msk (0x1U << RCC_APB2ENR_ADC1EN_Pos) /*!< 0x00000100 */
14200 #define RCC_APB2ENR_ADC1EN RCC_APB2ENR_ADC1EN_Msk
14201 #define RCC_APB2ENR_ADC2EN_Pos (9U)
14202 #define RCC_APB2ENR_ADC2EN_Msk (0x1U << RCC_APB2ENR_ADC2EN_Pos) /*!< 0x00000200 */
14203 #define RCC_APB2ENR_ADC2EN RCC_APB2ENR_ADC2EN_Msk
14204 #define RCC_APB2ENR_ADC3EN_Pos (10U)
14205 #define RCC_APB2ENR_ADC3EN_Msk (0x1U << RCC_APB2ENR_ADC3EN_Pos) /*!< 0x00000400 */
14206 #define RCC_APB2ENR_ADC3EN RCC_APB2ENR_ADC3EN_Msk
14207 #define RCC_APB2ENR_SDIOEN_Pos (11U)
14208 #define RCC_APB2ENR_SDIOEN_Msk (0x1U << RCC_APB2ENR_SDIOEN_Pos) /*!< 0x00000800 */
14209 #define RCC_APB2ENR_SDIOEN RCC_APB2ENR_SDIOEN_Msk
14210 #define RCC_APB2ENR_SPI1EN_Pos (12U)
14211 #define RCC_APB2ENR_SPI1EN_Msk (0x1U << RCC_APB2ENR_SPI1EN_Pos) /*!< 0x00001000 */
14212 #define RCC_APB2ENR_SPI1EN RCC_APB2ENR_SPI1EN_Msk
14213 #define RCC_APB2ENR_SPI4EN_Pos (13U)
14214 #define RCC_APB2ENR_SPI4EN_Msk (0x1U << RCC_APB2ENR_SPI4EN_Pos) /*!< 0x00002000 */
14215 #define RCC_APB2ENR_SPI4EN RCC_APB2ENR_SPI4EN_Msk
14216 #define RCC_APB2ENR_SYSCFGEN_Pos (14U)
14217 #define RCC_APB2ENR_SYSCFGEN_Msk (0x1U << RCC_APB2ENR_SYSCFGEN_Pos) /*!< 0x00004000 */
14218 #define RCC_APB2ENR_SYSCFGEN RCC_APB2ENR_SYSCFGEN_Msk
14219 #define RCC_APB2ENR_TIM9EN_Pos (16U)
14220 #define RCC_APB2ENR_TIM9EN_Msk (0x1U << RCC_APB2ENR_TIM9EN_Pos) /*!< 0x00010000 */
14221 #define RCC_APB2ENR_TIM9EN RCC_APB2ENR_TIM9EN_Msk
14222 #define RCC_APB2ENR_TIM10EN_Pos (17U)
14223 #define RCC_APB2ENR_TIM10EN_Msk (0x1U << RCC_APB2ENR_TIM10EN_Pos) /*!< 0x00020000 */
14224 #define RCC_APB2ENR_TIM10EN RCC_APB2ENR_TIM10EN_Msk
14225 #define RCC_APB2ENR_TIM11EN_Pos (18U)
14226 #define RCC_APB2ENR_TIM11EN_Msk (0x1U << RCC_APB2ENR_TIM11EN_Pos) /*!< 0x00040000 */
14227 #define RCC_APB2ENR_TIM11EN RCC_APB2ENR_TIM11EN_Msk
14228 #define RCC_APB2ENR_SPI5EN_Pos (20U)
14229 #define RCC_APB2ENR_SPI5EN_Msk (0x1U << RCC_APB2ENR_SPI5EN_Pos) /*!< 0x00100000 */
14230 #define RCC_APB2ENR_SPI5EN RCC_APB2ENR_SPI5EN_Msk
14231 #define RCC_APB2ENR_SPI6EN_Pos (21U)
14232 #define RCC_APB2ENR_SPI6EN_Msk (0x1U << RCC_APB2ENR_SPI6EN_Pos) /*!< 0x00200000 */
14233 #define RCC_APB2ENR_SPI6EN RCC_APB2ENR_SPI6EN_Msk
14234 #define RCC_APB2ENR_SAI1EN_Pos (22U)
14235 #define RCC_APB2ENR_SAI1EN_Msk (0x1U << RCC_APB2ENR_SAI1EN_Pos) /*!< 0x00400000 */
14236 #define RCC_APB2ENR_SAI1EN RCC_APB2ENR_SAI1EN_Msk
14237 #define RCC_APB2ENR_LTDCEN_Pos (26U)
14238 #define RCC_APB2ENR_LTDCEN_Msk (0x1U << RCC_APB2ENR_LTDCEN_Pos) /*!< 0x04000000 */
14239 #define RCC_APB2ENR_LTDCEN RCC_APB2ENR_LTDCEN_Msk
14240 #define RCC_APB2ENR_DSIEN_Pos (27U)
14241 #define RCC_APB2ENR_DSIEN_Msk (0x1U << RCC_APB2ENR_DSIEN_Pos) /*!< 0x08000000 */
14242 #define RCC_APB2ENR_DSIEN RCC_APB2ENR_DSIEN_Msk
14243
14244 /******************** Bit definition for RCC_AHB1LPENR register *************/
14245 #define RCC_AHB1LPENR_GPIOALPEN_Pos (0U)
14246 #define RCC_AHB1LPENR_GPIOALPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOALPEN_Pos) /*!< 0x00000001 */
14247 #define RCC_AHB1LPENR_GPIOALPEN RCC_AHB1LPENR_GPIOALPEN_Msk
14248 #define RCC_AHB1LPENR_GPIOBLPEN_Pos (1U)
14249 #define RCC_AHB1LPENR_GPIOBLPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOBLPEN_Pos) /*!< 0x00000002 */
14250 #define RCC_AHB1LPENR_GPIOBLPEN RCC_AHB1LPENR_GPIOBLPEN_Msk
14251 #define RCC_AHB1LPENR_GPIOCLPEN_Pos (2U)
14252 #define RCC_AHB1LPENR_GPIOCLPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOCLPEN_Pos) /*!< 0x00000004 */
14253 #define RCC_AHB1LPENR_GPIOCLPEN RCC_AHB1LPENR_GPIOCLPEN_Msk
14254 #define RCC_AHB1LPENR_GPIODLPEN_Pos (3U)
14255 #define RCC_AHB1LPENR_GPIODLPEN_Msk (0x1U << RCC_AHB1LPENR_GPIODLPEN_Pos) /*!< 0x00000008 */
14256 #define RCC_AHB1LPENR_GPIODLPEN RCC_AHB1LPENR_GPIODLPEN_Msk
14257 #define RCC_AHB1LPENR_GPIOELPEN_Pos (4U)
14258 #define RCC_AHB1LPENR_GPIOELPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOELPEN_Pos) /*!< 0x00000010 */
14259 #define RCC_AHB1LPENR_GPIOELPEN RCC_AHB1LPENR_GPIOELPEN_Msk
14260 #define RCC_AHB1LPENR_GPIOFLPEN_Pos (5U)
14261 #define RCC_AHB1LPENR_GPIOFLPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOFLPEN_Pos) /*!< 0x00000020 */
14262 #define RCC_AHB1LPENR_GPIOFLPEN RCC_AHB1LPENR_GPIOFLPEN_Msk
14263 #define RCC_AHB1LPENR_GPIOGLPEN_Pos (6U)
14264 #define RCC_AHB1LPENR_GPIOGLPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOGLPEN_Pos) /*!< 0x00000040 */
14265 #define RCC_AHB1LPENR_GPIOGLPEN RCC_AHB1LPENR_GPIOGLPEN_Msk
14266 #define RCC_AHB1LPENR_GPIOHLPEN_Pos (7U)
14267 #define RCC_AHB1LPENR_GPIOHLPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOHLPEN_Pos) /*!< 0x00000080 */
14268 #define RCC_AHB1LPENR_GPIOHLPEN RCC_AHB1LPENR_GPIOHLPEN_Msk
14269 #define RCC_AHB1LPENR_GPIOILPEN_Pos (8U)
14270 #define RCC_AHB1LPENR_GPIOILPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOILPEN_Pos) /*!< 0x00000100 */
14271 #define RCC_AHB1LPENR_GPIOILPEN RCC_AHB1LPENR_GPIOILPEN_Msk
14272 #define RCC_AHB1LPENR_GPIOJLPEN_Pos (9U)
14273 #define RCC_AHB1LPENR_GPIOJLPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOJLPEN_Pos) /*!< 0x00000200 */
14274 #define RCC_AHB1LPENR_GPIOJLPEN RCC_AHB1LPENR_GPIOJLPEN_Msk
14275 #define RCC_AHB1LPENR_GPIOKLPEN_Pos (10U)
14276 #define RCC_AHB1LPENR_GPIOKLPEN_Msk (0x1U << RCC_AHB1LPENR_GPIOKLPEN_Pos) /*!< 0x00000400 */
14277 #define RCC_AHB1LPENR_GPIOKLPEN RCC_AHB1LPENR_GPIOKLPEN_Msk
14278 #define RCC_AHB1LPENR_CRCLPEN_Pos (12U)
14279 #define RCC_AHB1LPENR_CRCLPEN_Msk (0x1U << RCC_AHB1LPENR_CRCLPEN_Pos) /*!< 0x00001000 */
14280 #define RCC_AHB1LPENR_CRCLPEN RCC_AHB1LPENR_CRCLPEN_Msk
14281 #define RCC_AHB1LPENR_FLITFLPEN_Pos (15U)
14282 #define RCC_AHB1LPENR_FLITFLPEN_Msk (0x1U << RCC_AHB1LPENR_FLITFLPEN_Pos) /*!< 0x00008000 */
14283 #define RCC_AHB1LPENR_FLITFLPEN RCC_AHB1LPENR_FLITFLPEN_Msk
14284 #define RCC_AHB1LPENR_SRAM1LPEN_Pos (16U)
14285 #define RCC_AHB1LPENR_SRAM1LPEN_Msk (0x1U << RCC_AHB1LPENR_SRAM1LPEN_Pos) /*!< 0x00010000 */
14286 #define RCC_AHB1LPENR_SRAM1LPEN RCC_AHB1LPENR_SRAM1LPEN_Msk
14287 #define RCC_AHB1LPENR_SRAM2LPEN_Pos (17U)
14288 #define RCC_AHB1LPENR_SRAM2LPEN_Msk (0x1U << RCC_AHB1LPENR_SRAM2LPEN_Pos) /*!< 0x00020000 */
14289 #define RCC_AHB1LPENR_SRAM2LPEN RCC_AHB1LPENR_SRAM2LPEN_Msk
14290 #define RCC_AHB1LPENR_BKPSRAMLPEN_Pos (18U)
14291 #define RCC_AHB1LPENR_BKPSRAMLPEN_Msk (0x1U << RCC_AHB1LPENR_BKPSRAMLPEN_Pos) /*!< 0x00040000 */
14292 #define RCC_AHB1LPENR_BKPSRAMLPEN RCC_AHB1LPENR_BKPSRAMLPEN_Msk
14293 #define RCC_AHB1LPENR_SRAM3LPEN_Pos (19U)
14294 #define RCC_AHB1LPENR_SRAM3LPEN_Msk (0x1U << RCC_AHB1LPENR_SRAM3LPEN_Pos) /*!< 0x00080000 */
14295 #define RCC_AHB1LPENR_SRAM3LPEN RCC_AHB1LPENR_SRAM3LPEN_Msk
14296 #define RCC_AHB1LPENR_DMA1LPEN_Pos (21U)
14297 #define RCC_AHB1LPENR_DMA1LPEN_Msk (0x1U << RCC_AHB1LPENR_DMA1LPEN_Pos) /*!< 0x00200000 */
14298 #define RCC_AHB1LPENR_DMA1LPEN RCC_AHB1LPENR_DMA1LPEN_Msk
14299 #define RCC_AHB1LPENR_DMA2LPEN_Pos (22U)
14300 #define RCC_AHB1LPENR_DMA2LPEN_Msk (0x1U << RCC_AHB1LPENR_DMA2LPEN_Pos) /*!< 0x00400000 */
14301 #define RCC_AHB1LPENR_DMA2LPEN RCC_AHB1LPENR_DMA2LPEN_Msk
14302 #define RCC_AHB1LPENR_DMA2DLPEN_Pos (23U)
14303 #define RCC_AHB1LPENR_DMA2DLPEN_Msk (0x1U << RCC_AHB1LPENR_DMA2DLPEN_Pos) /*!< 0x00800000 */
14304 #define RCC_AHB1LPENR_DMA2DLPEN RCC_AHB1LPENR_DMA2DLPEN_Msk
14305
14306 #define RCC_AHB1LPENR_ETHMACLPEN_Pos (25U)
14307 #define RCC_AHB1LPENR_ETHMACLPEN_Msk (0x1U << RCC_AHB1LPENR_ETHMACLPEN_Pos) /*!< 0x02000000 */
14308 #define RCC_AHB1LPENR_ETHMACLPEN RCC_AHB1LPENR_ETHMACLPEN_Msk
14309 #define RCC_AHB1LPENR_ETHMACTXLPEN_Pos (26U)
14310 #define RCC_AHB1LPENR_ETHMACTXLPEN_Msk (0x1U << RCC_AHB1LPENR_ETHMACTXLPEN_Pos) /*!< 0x04000000 */
14311 #define RCC_AHB1LPENR_ETHMACTXLPEN RCC_AHB1LPENR_ETHMACTXLPEN_Msk
14312 #define RCC_AHB1LPENR_ETHMACRXLPEN_Pos (27U)
14313 #define RCC_AHB1LPENR_ETHMACRXLPEN_Msk (0x1U << RCC_AHB1LPENR_ETHMACRXLPEN_Pos) /*!< 0x08000000 */
14314 #define RCC_AHB1LPENR_ETHMACRXLPEN RCC_AHB1LPENR_ETHMACRXLPEN_Msk
14315 #define RCC_AHB1LPENR_ETHMACPTPLPEN_Pos (28U)
14316 #define RCC_AHB1LPENR_ETHMACPTPLPEN_Msk (0x1U << RCC_AHB1LPENR_ETHMACPTPLPEN_Pos) /*!< 0x10000000 */
14317 #define RCC_AHB1LPENR_ETHMACPTPLPEN RCC_AHB1LPENR_ETHMACPTPLPEN_Msk
14318 #define RCC_AHB1LPENR_OTGHSLPEN_Pos (29U)
14319 #define RCC_AHB1LPENR_OTGHSLPEN_Msk (0x1U << RCC_AHB1LPENR_OTGHSLPEN_Pos) /*!< 0x20000000 */
14320 #define RCC_AHB1LPENR_OTGHSLPEN RCC_AHB1LPENR_OTGHSLPEN_Msk
14321 #define RCC_AHB1LPENR_OTGHSULPILPEN_Pos (30U)
14322 #define RCC_AHB1LPENR_OTGHSULPILPEN_Msk (0x1U << RCC_AHB1LPENR_OTGHSULPILPEN_Pos) /*!< 0x40000000 */
14323 #define RCC_AHB1LPENR_OTGHSULPILPEN RCC_AHB1LPENR_OTGHSULPILPEN_Msk
14324
14325 /******************** Bit definition for RCC_AHB2LPENR register *************/
14326 #define RCC_AHB2LPENR_DCMILPEN_Pos (0U)
14327 #define RCC_AHB2LPENR_DCMILPEN_Msk (0x1U << RCC_AHB2LPENR_DCMILPEN_Pos) /*!< 0x00000001 */
14328 #define RCC_AHB2LPENR_DCMILPEN RCC_AHB2LPENR_DCMILPEN_Msk
14329 #define RCC_AHB2LPENR_RNGLPEN_Pos (6U)
14330 #define RCC_AHB2LPENR_RNGLPEN_Msk (0x1U << RCC_AHB2LPENR_RNGLPEN_Pos) /*!< 0x00000040 */
14331 #define RCC_AHB2LPENR_RNGLPEN RCC_AHB2LPENR_RNGLPEN_Msk
14332 #define RCC_AHB2LPENR_OTGFSLPEN_Pos (7U)
14333 #define RCC_AHB2LPENR_OTGFSLPEN_Msk (0x1U << RCC_AHB2LPENR_OTGFSLPEN_Pos) /*!< 0x00000080 */
14334 #define RCC_AHB2LPENR_OTGFSLPEN RCC_AHB2LPENR_OTGFSLPEN_Msk
14335
14336 /******************** Bit definition for RCC_AHB3LPENR register *************/
14337 #define RCC_AHB3LPENR_FMCLPEN_Pos (0U)
14338 #define RCC_AHB3LPENR_FMCLPEN_Msk (0x1U << RCC_AHB3LPENR_FMCLPEN_Pos) /*!< 0x00000001 */
14339 #define RCC_AHB3LPENR_FMCLPEN RCC_AHB3LPENR_FMCLPEN_Msk
14340 #define RCC_AHB3LPENR_QSPILPEN_Pos (1U)
14341 #define RCC_AHB3LPENR_QSPILPEN_Msk (0x1U << RCC_AHB3LPENR_QSPILPEN_Pos) /*!< 0x00000002 */
14342 #define RCC_AHB3LPENR_QSPILPEN RCC_AHB3LPENR_QSPILPEN_Msk
14343
14344 /******************** Bit definition for RCC_APB1LPENR register *************/
14345 #define RCC_APB1LPENR_TIM2LPEN_Pos (0U)
14346 #define RCC_APB1LPENR_TIM2LPEN_Msk (0x1U << RCC_APB1LPENR_TIM2LPEN_Pos) /*!< 0x00000001 */
14347 #define RCC_APB1LPENR_TIM2LPEN RCC_APB1LPENR_TIM2LPEN_Msk
14348 #define RCC_APB1LPENR_TIM3LPEN_Pos (1U)
14349 #define RCC_APB1LPENR_TIM3LPEN_Msk (0x1U << RCC_APB1LPENR_TIM3LPEN_Pos) /*!< 0x00000002 */
14350 #define RCC_APB1LPENR_TIM3LPEN RCC_APB1LPENR_TIM3LPEN_Msk
14351 #define RCC_APB1LPENR_TIM4LPEN_Pos (2U)
14352 #define RCC_APB1LPENR_TIM4LPEN_Msk (0x1U << RCC_APB1LPENR_TIM4LPEN_Pos) /*!< 0x00000004 */
14353 #define RCC_APB1LPENR_TIM4LPEN RCC_APB1LPENR_TIM4LPEN_Msk
14354 #define RCC_APB1LPENR_TIM5LPEN_Pos (3U)
14355 #define RCC_APB1LPENR_TIM5LPEN_Msk (0x1U << RCC_APB1LPENR_TIM5LPEN_Pos) /*!< 0x00000008 */
14356 #define RCC_APB1LPENR_TIM5LPEN RCC_APB1LPENR_TIM5LPEN_Msk
14357 #define RCC_APB1LPENR_TIM6LPEN_Pos (4U)
14358 #define RCC_APB1LPENR_TIM6LPEN_Msk (0x1U << RCC_APB1LPENR_TIM6LPEN_Pos) /*!< 0x00000010 */
14359 #define RCC_APB1LPENR_TIM6LPEN RCC_APB1LPENR_TIM6LPEN_Msk
14360 #define RCC_APB1LPENR_TIM7LPEN_Pos (5U)
14361 #define RCC_APB1LPENR_TIM7LPEN_Msk (0x1U << RCC_APB1LPENR_TIM7LPEN_Pos) /*!< 0x00000020 */
14362 #define RCC_APB1LPENR_TIM7LPEN RCC_APB1LPENR_TIM7LPEN_Msk
14363 #define RCC_APB1LPENR_TIM12LPEN_Pos (6U)
14364 #define RCC_APB1LPENR_TIM12LPEN_Msk (0x1U << RCC_APB1LPENR_TIM12LPEN_Pos) /*!< 0x00000040 */
14365 #define RCC_APB1LPENR_TIM12LPEN RCC_APB1LPENR_TIM12LPEN_Msk
14366 #define RCC_APB1LPENR_TIM13LPEN_Pos (7U)
14367 #define RCC_APB1LPENR_TIM13LPEN_Msk (0x1U << RCC_APB1LPENR_TIM13LPEN_Pos) /*!< 0x00000080 */
14368 #define RCC_APB1LPENR_TIM13LPEN RCC_APB1LPENR_TIM13LPEN_Msk
14369 #define RCC_APB1LPENR_TIM14LPEN_Pos (8U)
14370 #define RCC_APB1LPENR_TIM14LPEN_Msk (0x1U << RCC_APB1LPENR_TIM14LPEN_Pos) /*!< 0x00000100 */
14371 #define RCC_APB1LPENR_TIM14LPEN RCC_APB1LPENR_TIM14LPEN_Msk
14372 #define RCC_APB1LPENR_WWDGLPEN_Pos (11U)
14373 #define RCC_APB1LPENR_WWDGLPEN_Msk (0x1U << RCC_APB1LPENR_WWDGLPEN_Pos) /*!< 0x00000800 */
14374 #define RCC_APB1LPENR_WWDGLPEN RCC_APB1LPENR_WWDGLPEN_Msk
14375 #define RCC_APB1LPENR_SPI2LPEN_Pos (14U)
14376 #define RCC_APB1LPENR_SPI2LPEN_Msk (0x1U << RCC_APB1LPENR_SPI2LPEN_Pos) /*!< 0x00004000 */
14377 #define RCC_APB1LPENR_SPI2LPEN RCC_APB1LPENR_SPI2LPEN_Msk
14378 #define RCC_APB1LPENR_SPI3LPEN_Pos (15U)
14379 #define RCC_APB1LPENR_SPI3LPEN_Msk (0x1U << RCC_APB1LPENR_SPI3LPEN_Pos) /*!< 0x00008000 */
14380 #define RCC_APB1LPENR_SPI3LPEN RCC_APB1LPENR_SPI3LPEN_Msk
14381 #define RCC_APB1LPENR_USART2LPEN_Pos (17U)
14382 #define RCC_APB1LPENR_USART2LPEN_Msk (0x1U << RCC_APB1LPENR_USART2LPEN_Pos) /*!< 0x00020000 */
14383 #define RCC_APB1LPENR_USART2LPEN RCC_APB1LPENR_USART2LPEN_Msk
14384 #define RCC_APB1LPENR_USART3LPEN_Pos (18U)
14385 #define RCC_APB1LPENR_USART3LPEN_Msk (0x1U << RCC_APB1LPENR_USART3LPEN_Pos) /*!< 0x00040000 */
14386 #define RCC_APB1LPENR_USART3LPEN RCC_APB1LPENR_USART3LPEN_Msk
14387 #define RCC_APB1LPENR_UART4LPEN_Pos (19U)
14388 #define RCC_APB1LPENR_UART4LPEN_Msk (0x1U << RCC_APB1LPENR_UART4LPEN_Pos) /*!< 0x00080000 */
14389 #define RCC_APB1LPENR_UART4LPEN RCC_APB1LPENR_UART4LPEN_Msk
14390 #define RCC_APB1LPENR_UART5LPEN_Pos (20U)
14391 #define RCC_APB1LPENR_UART5LPEN_Msk (0x1U << RCC_APB1LPENR_UART5LPEN_Pos) /*!< 0x00100000 */
14392 #define RCC_APB1LPENR_UART5LPEN RCC_APB1LPENR_UART5LPEN_Msk
14393 #define RCC_APB1LPENR_I2C1LPEN_Pos (21U)
14394 #define RCC_APB1LPENR_I2C1LPEN_Msk (0x1U << RCC_APB1LPENR_I2C1LPEN_Pos) /*!< 0x00200000 */
14395 #define RCC_APB1LPENR_I2C1LPEN RCC_APB1LPENR_I2C1LPEN_Msk
14396 #define RCC_APB1LPENR_I2C2LPEN_Pos (22U)
14397 #define RCC_APB1LPENR_I2C2LPEN_Msk (0x1U << RCC_APB1LPENR_I2C2LPEN_Pos) /*!< 0x00400000 */
14398 #define RCC_APB1LPENR_I2C2LPEN RCC_APB1LPENR_I2C2LPEN_Msk
14399 #define RCC_APB1LPENR_I2C3LPEN_Pos (23U)
14400 #define RCC_APB1LPENR_I2C3LPEN_Msk (0x1U << RCC_APB1LPENR_I2C3LPEN_Pos) /*!< 0x00800000 */
14401 #define RCC_APB1LPENR_I2C3LPEN RCC_APB1LPENR_I2C3LPEN_Msk
14402 #define RCC_APB1LPENR_CAN1LPEN_Pos (25U)
14403 #define RCC_APB1LPENR_CAN1LPEN_Msk (0x1U << RCC_APB1LPENR_CAN1LPEN_Pos) /*!< 0x02000000 */
14404 #define RCC_APB1LPENR_CAN1LPEN RCC_APB1LPENR_CAN1LPEN_Msk
14405 #define RCC_APB1LPENR_CAN2LPEN_Pos (26U)
14406 #define RCC_APB1LPENR_CAN2LPEN_Msk (0x1U << RCC_APB1LPENR_CAN2LPEN_Pos) /*!< 0x04000000 */
14407 #define RCC_APB1LPENR_CAN2LPEN RCC_APB1LPENR_CAN2LPEN_Msk
14408 #define RCC_APB1LPENR_PWRLPEN_Pos (28U)
14409 #define RCC_APB1LPENR_PWRLPEN_Msk (0x1U << RCC_APB1LPENR_PWRLPEN_Pos) /*!< 0x10000000 */
14410 #define RCC_APB1LPENR_PWRLPEN RCC_APB1LPENR_PWRLPEN_Msk
14411 #define RCC_APB1LPENR_DACLPEN_Pos (29U)
14412 #define RCC_APB1LPENR_DACLPEN_Msk (0x1U << RCC_APB1LPENR_DACLPEN_Pos) /*!< 0x20000000 */
14413 #define RCC_APB1LPENR_DACLPEN RCC_APB1LPENR_DACLPEN_Msk
14414 #define RCC_APB1LPENR_UART7LPEN_Pos (30U)
14415 #define RCC_APB1LPENR_UART7LPEN_Msk (0x1U << RCC_APB1LPENR_UART7LPEN_Pos) /*!< 0x40000000 */
14416 #define RCC_APB1LPENR_UART7LPEN RCC_APB1LPENR_UART7LPEN_Msk
14417 #define RCC_APB1LPENR_UART8LPEN_Pos (31U)
14418 #define RCC_APB1LPENR_UART8LPEN_Msk (0x1U << RCC_APB1LPENR_UART8LPEN_Pos) /*!< 0x80000000 */
14419 #define RCC_APB1LPENR_UART8LPEN RCC_APB1LPENR_UART8LPEN_Msk
14420
14421 /******************** Bit definition for RCC_APB2LPENR register *************/
14422 #define RCC_APB2LPENR_TIM1LPEN_Pos (0U)
14423 #define RCC_APB2LPENR_TIM1LPEN_Msk (0x1U << RCC_APB2LPENR_TIM1LPEN_Pos) /*!< 0x00000001 */
14424 #define RCC_APB2LPENR_TIM1LPEN RCC_APB2LPENR_TIM1LPEN_Msk
14425 #define RCC_APB2LPENR_TIM8LPEN_Pos (1U)
14426 #define RCC_APB2LPENR_TIM8LPEN_Msk (0x1U << RCC_APB2LPENR_TIM8LPEN_Pos) /*!< 0x00000002 */
14427 #define RCC_APB2LPENR_TIM8LPEN RCC_APB2LPENR_TIM8LPEN_Msk
14428 #define RCC_APB2LPENR_USART1LPEN_Pos (4U)
14429 #define RCC_APB2LPENR_USART1LPEN_Msk (0x1U << RCC_APB2LPENR_USART1LPEN_Pos) /*!< 0x00000010 */
14430 #define RCC_APB2LPENR_USART1LPEN RCC_APB2LPENR_USART1LPEN_Msk
14431 #define RCC_APB2LPENR_USART6LPEN_Pos (5U)
14432 #define RCC_APB2LPENR_USART6LPEN_Msk (0x1U << RCC_APB2LPENR_USART6LPEN_Pos) /*!< 0x00000020 */
14433 #define RCC_APB2LPENR_USART6LPEN RCC_APB2LPENR_USART6LPEN_Msk
14434 #define RCC_APB2LPENR_ADC1LPEN_Pos (8U)
14435 #define RCC_APB2LPENR_ADC1LPEN_Msk (0x1U << RCC_APB2LPENR_ADC1LPEN_Pos) /*!< 0x00000100 */
14436 #define RCC_APB2LPENR_ADC1LPEN RCC_APB2LPENR_ADC1LPEN_Msk
14437 #define RCC_APB2LPENR_ADC2LPEN_Pos (9U)
14438 #define RCC_APB2LPENR_ADC2LPEN_Msk (0x1U << RCC_APB2LPENR_ADC2LPEN_Pos) /*!< 0x00000200 */
14439 #define RCC_APB2LPENR_ADC2LPEN RCC_APB2LPENR_ADC2LPEN_Msk
14440 #define RCC_APB2LPENR_ADC3LPEN_Pos (10U)
14441 #define RCC_APB2LPENR_ADC3LPEN_Msk (0x1U << RCC_APB2LPENR_ADC3LPEN_Pos) /*!< 0x00000400 */
14442 #define RCC_APB2LPENR_ADC3LPEN RCC_APB2LPENR_ADC3LPEN_Msk
14443 #define RCC_APB2LPENR_SDIOLPEN_Pos (11U)
14444 #define RCC_APB2LPENR_SDIOLPEN_Msk (0x1U << RCC_APB2LPENR_SDIOLPEN_Pos) /*!< 0x00000800 */
14445 #define RCC_APB2LPENR_SDIOLPEN RCC_APB2LPENR_SDIOLPEN_Msk
14446 #define RCC_APB2LPENR_SPI1LPEN_Pos (12U)
14447 #define RCC_APB2LPENR_SPI1LPEN_Msk (0x1U << RCC_APB2LPENR_SPI1LPEN_Pos) /*!< 0x00001000 */
14448 #define RCC_APB2LPENR_SPI1LPEN RCC_APB2LPENR_SPI1LPEN_Msk
14449 #define RCC_APB2LPENR_SPI4LPEN_Pos (13U)
14450 #define RCC_APB2LPENR_SPI4LPEN_Msk (0x1U << RCC_APB2LPENR_SPI4LPEN_Pos) /*!< 0x00002000 */
14451 #define RCC_APB2LPENR_SPI4LPEN RCC_APB2LPENR_SPI4LPEN_Msk
14452 #define RCC_APB2LPENR_SYSCFGLPEN_Pos (14U)
14453 #define RCC_APB2LPENR_SYSCFGLPEN_Msk (0x1U << RCC_APB2LPENR_SYSCFGLPEN_Pos) /*!< 0x00004000 */
14454 #define RCC_APB2LPENR_SYSCFGLPEN RCC_APB2LPENR_SYSCFGLPEN_Msk
14455 #define RCC_APB2LPENR_TIM9LPEN_Pos (16U)
14456 #define RCC_APB2LPENR_TIM9LPEN_Msk (0x1U << RCC_APB2LPENR_TIM9LPEN_Pos) /*!< 0x00010000 */
14457 #define RCC_APB2LPENR_TIM9LPEN RCC_APB2LPENR_TIM9LPEN_Msk
14458 #define RCC_APB2LPENR_TIM10LPEN_Pos (17U)
14459 #define RCC_APB2LPENR_TIM10LPEN_Msk (0x1U << RCC_APB2LPENR_TIM10LPEN_Pos) /*!< 0x00020000 */
14460 #define RCC_APB2LPENR_TIM10LPEN RCC_APB2LPENR_TIM10LPEN_Msk
14461 #define RCC_APB2LPENR_TIM11LPEN_Pos (18U)
14462 #define RCC_APB2LPENR_TIM11LPEN_Msk (0x1U << RCC_APB2LPENR_TIM11LPEN_Pos) /*!< 0x00040000 */
14463 #define RCC_APB2LPENR_TIM11LPEN RCC_APB2LPENR_TIM11LPEN_Msk
14464 #define RCC_APB2LPENR_SPI5LPEN_Pos (20U)
14465 #define RCC_APB2LPENR_SPI5LPEN_Msk (0x1U << RCC_APB2LPENR_SPI5LPEN_Pos) /*!< 0x00100000 */
14466 #define RCC_APB2LPENR_SPI5LPEN RCC_APB2LPENR_SPI5LPEN_Msk
14467 #define RCC_APB2LPENR_SPI6LPEN_Pos (21U)
14468 #define RCC_APB2LPENR_SPI6LPEN_Msk (0x1U << RCC_APB2LPENR_SPI6LPEN_Pos) /*!< 0x00200000 */
14469 #define RCC_APB2LPENR_SPI6LPEN RCC_APB2LPENR_SPI6LPEN_Msk
14470 #define RCC_APB2LPENR_SAI1LPEN_Pos (22U)
14471 #define RCC_APB2LPENR_SAI1LPEN_Msk (0x1U << RCC_APB2LPENR_SAI1LPEN_Pos) /*!< 0x00400000 */
14472 #define RCC_APB2LPENR_SAI1LPEN RCC_APB2LPENR_SAI1LPEN_Msk
14473 #define RCC_APB2LPENR_LTDCLPEN_Pos (26U)
14474 #define RCC_APB2LPENR_LTDCLPEN_Msk (0x1U << RCC_APB2LPENR_LTDCLPEN_Pos) /*!< 0x04000000 */
14475 #define RCC_APB2LPENR_LTDCLPEN RCC_APB2LPENR_LTDCLPEN_Msk
14476 #define RCC_APB2LPENR_DSILPEN_Pos (27U)
14477 #define RCC_APB2LPENR_DSILPEN_Msk (0x1U << RCC_APB2LPENR_DSILPEN_Pos) /*!< 0x08000000 */
14478 #define RCC_APB2LPENR_DSILPEN RCC_APB2LPENR_DSILPEN_Msk
14479
14480 /******************** Bit definition for RCC_BDCR register ******************/
14481 #define RCC_BDCR_LSEON_Pos (0U)
14482 #define RCC_BDCR_LSEON_Msk (0x1U << RCC_BDCR_LSEON_Pos) /*!< 0x00000001 */
14483 #define RCC_BDCR_LSEON RCC_BDCR_LSEON_Msk
14484 #define RCC_BDCR_LSERDY_Pos (1U)
14485 #define RCC_BDCR_LSERDY_Msk (0x1U << RCC_BDCR_LSERDY_Pos) /*!< 0x00000002 */
14486 #define RCC_BDCR_LSERDY RCC_BDCR_LSERDY_Msk
14487 #define RCC_BDCR_LSEBYP_Pos (2U)
14488 #define RCC_BDCR_LSEBYP_Msk (0x1U << RCC_BDCR_LSEBYP_Pos) /*!< 0x00000004 */
14489 #define RCC_BDCR_LSEBYP RCC_BDCR_LSEBYP_Msk
14490 #define RCC_BDCR_LSEMOD_Pos (3U)
14491 #define RCC_BDCR_LSEMOD_Msk (0x1U << RCC_BDCR_LSEMOD_Pos) /*!< 0x00000008 */
14492 #define RCC_BDCR_LSEMOD RCC_BDCR_LSEMOD_Msk
14493
14494 #define RCC_BDCR_RTCSEL_Pos (8U)
14495 #define RCC_BDCR_RTCSEL_Msk (0x3U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000300 */
14496 #define RCC_BDCR_RTCSEL RCC_BDCR_RTCSEL_Msk
14497 #define RCC_BDCR_RTCSEL_0 (0x1U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000100 */
14498 #define RCC_BDCR_RTCSEL_1 (0x2U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000200 */
14499
14500 #define RCC_BDCR_RTCEN_Pos (15U)
14501 #define RCC_BDCR_RTCEN_Msk (0x1U << RCC_BDCR_RTCEN_Pos) /*!< 0x00008000 */
14502 #define RCC_BDCR_RTCEN RCC_BDCR_RTCEN_Msk
14503 #define RCC_BDCR_BDRST_Pos (16U)
14504 #define RCC_BDCR_BDRST_Msk (0x1U << RCC_BDCR_BDRST_Pos) /*!< 0x00010000 */
14505 #define RCC_BDCR_BDRST RCC_BDCR_BDRST_Msk
14506
14507 /******************** Bit definition for RCC_CSR register *******************/
14508 #define RCC_CSR_LSION_Pos (0U)
14509 #define RCC_CSR_LSION_Msk (0x1U << RCC_CSR_LSION_Pos) /*!< 0x00000001 */
14510 #define RCC_CSR_LSION RCC_CSR_LSION_Msk
14511 #define RCC_CSR_LSIRDY_Pos (1U)
14512 #define RCC_CSR_LSIRDY_Msk (0x1U << RCC_CSR_LSIRDY_Pos) /*!< 0x00000002 */
14513 #define RCC_CSR_LSIRDY RCC_CSR_LSIRDY_Msk
14514 #define RCC_CSR_RMVF_Pos (24U)
14515 #define RCC_CSR_RMVF_Msk (0x1U << RCC_CSR_RMVF_Pos) /*!< 0x01000000 */
14516 #define RCC_CSR_RMVF RCC_CSR_RMVF_Msk
14517 #define RCC_CSR_BORRSTF_Pos (25U)
14518 #define RCC_CSR_BORRSTF_Msk (0x1U << RCC_CSR_BORRSTF_Pos) /*!< 0x02000000 */
14519 #define RCC_CSR_BORRSTF RCC_CSR_BORRSTF_Msk
14520 #define RCC_CSR_PINRSTF_Pos (26U)
14521 #define RCC_CSR_PINRSTF_Msk (0x1U << RCC_CSR_PINRSTF_Pos) /*!< 0x04000000 */
14522 #define RCC_CSR_PINRSTF RCC_CSR_PINRSTF_Msk
14523 #define RCC_CSR_PORRSTF_Pos (27U)
14524 #define RCC_CSR_PORRSTF_Msk (0x1U << RCC_CSR_PORRSTF_Pos) /*!< 0x08000000 */
14525 #define RCC_CSR_PORRSTF RCC_CSR_PORRSTF_Msk
14526 #define RCC_CSR_SFTRSTF_Pos (28U)
14527 #define RCC_CSR_SFTRSTF_Msk (0x1U << RCC_CSR_SFTRSTF_Pos) /*!< 0x10000000 */
14528 #define RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF_Msk
14529 #define RCC_CSR_IWDGRSTF_Pos (29U)
14530 #define RCC_CSR_IWDGRSTF_Msk (0x1U << RCC_CSR_IWDGRSTF_Pos) /*!< 0x20000000 */
14531 #define RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF_Msk
14532 #define RCC_CSR_WWDGRSTF_Pos (30U)
14533 #define RCC_CSR_WWDGRSTF_Msk (0x1U << RCC_CSR_WWDGRSTF_Pos) /*!< 0x40000000 */
14534 #define RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF_Msk
14535 #define RCC_CSR_LPWRRSTF_Pos (31U)
14536 #define RCC_CSR_LPWRRSTF_Msk (0x1U << RCC_CSR_LPWRRSTF_Pos) /*!< 0x80000000 */
14537 #define RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF_Msk
14538 /* Legacy defines */
14539 #define RCC_CSR_PADRSTF RCC_CSR_PINRSTF
14540 #define RCC_CSR_WDGRSTF RCC_CSR_IWDGRSTF
14541
14542 /******************** Bit definition for RCC_SSCGR register *****************/
14543 #define RCC_SSCGR_MODPER_Pos (0U)
14544 #define RCC_SSCGR_MODPER_Msk (0x1FFFU << RCC_SSCGR_MODPER_Pos) /*!< 0x00001FFF */
14545 #define RCC_SSCGR_MODPER RCC_SSCGR_MODPER_Msk
14546 #define RCC_SSCGR_INCSTEP_Pos (13U)
14547 #define RCC_SSCGR_INCSTEP_Msk (0x7FFFU << RCC_SSCGR_INCSTEP_Pos) /*!< 0x0FFFE000 */
14548 #define RCC_SSCGR_INCSTEP RCC_SSCGR_INCSTEP_Msk
14549 #define RCC_SSCGR_SPREADSEL_Pos (30U)
14550 #define RCC_SSCGR_SPREADSEL_Msk (0x1U << RCC_SSCGR_SPREADSEL_Pos) /*!< 0x40000000 */
14551 #define RCC_SSCGR_SPREADSEL RCC_SSCGR_SPREADSEL_Msk
14552 #define RCC_SSCGR_SSCGEN_Pos (31U)
14553 #define RCC_SSCGR_SSCGEN_Msk (0x1U << RCC_SSCGR_SSCGEN_Pos) /*!< 0x80000000 */
14554 #define RCC_SSCGR_SSCGEN RCC_SSCGR_SSCGEN_Msk
14555
14556 /******************** Bit definition for RCC_PLLI2SCFGR register ************/
14557 #define RCC_PLLI2SCFGR_PLLI2SN_Pos (6U)
14558 #define RCC_PLLI2SCFGR_PLLI2SN_Msk (0x1FFU << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00007FC0 */
14559 #define RCC_PLLI2SCFGR_PLLI2SN RCC_PLLI2SCFGR_PLLI2SN_Msk
14560 #define RCC_PLLI2SCFGR_PLLI2SN_0 (0x001U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000040 */
14561 #define RCC_PLLI2SCFGR_PLLI2SN_1 (0x002U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000080 */
14562 #define RCC_PLLI2SCFGR_PLLI2SN_2 (0x004U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000100 */
14563 #define RCC_PLLI2SCFGR_PLLI2SN_3 (0x008U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000200 */
14564 #define RCC_PLLI2SCFGR_PLLI2SN_4 (0x010U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000400 */
14565 #define RCC_PLLI2SCFGR_PLLI2SN_5 (0x020U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000800 */
14566 #define RCC_PLLI2SCFGR_PLLI2SN_6 (0x040U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00001000 */
14567 #define RCC_PLLI2SCFGR_PLLI2SN_7 (0x080U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00002000 */
14568 #define RCC_PLLI2SCFGR_PLLI2SN_8 (0x100U << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00004000 */
14569
14570 #define RCC_PLLI2SCFGR_PLLI2SQ_Pos (24U)
14571 #define RCC_PLLI2SCFGR_PLLI2SQ_Msk (0xFU << RCC_PLLI2SCFGR_PLLI2SQ_Pos) /*!< 0x0F000000 */
14572 #define RCC_PLLI2SCFGR_PLLI2SQ RCC_PLLI2SCFGR_PLLI2SQ_Msk
14573 #define RCC_PLLI2SCFGR_PLLI2SQ_0 (0x1U << RCC_PLLI2SCFGR_PLLI2SQ_Pos) /*!< 0x01000000 */
14574 #define RCC_PLLI2SCFGR_PLLI2SQ_1 (0x2U << RCC_PLLI2SCFGR_PLLI2SQ_Pos) /*!< 0x02000000 */
14575 #define RCC_PLLI2SCFGR_PLLI2SQ_2 (0x4U << RCC_PLLI2SCFGR_PLLI2SQ_Pos) /*!< 0x04000000 */
14576 #define RCC_PLLI2SCFGR_PLLI2SQ_3 (0x8U << RCC_PLLI2SCFGR_PLLI2SQ_Pos) /*!< 0x08000000 */
14577 #define RCC_PLLI2SCFGR_PLLI2SR_Pos (28U)
14578 #define RCC_PLLI2SCFGR_PLLI2SR_Msk (0x7U << RCC_PLLI2SCFGR_PLLI2SR_Pos) /*!< 0x70000000 */
14579 #define RCC_PLLI2SCFGR_PLLI2SR RCC_PLLI2SCFGR_PLLI2SR_Msk
14580 #define RCC_PLLI2SCFGR_PLLI2SR_0 (0x1U << RCC_PLLI2SCFGR_PLLI2SR_Pos) /*!< 0x10000000 */
14581 #define RCC_PLLI2SCFGR_PLLI2SR_1 (0x2U << RCC_PLLI2SCFGR_PLLI2SR_Pos) /*!< 0x20000000 */
14582 #define RCC_PLLI2SCFGR_PLLI2SR_2 (0x4U << RCC_PLLI2SCFGR_PLLI2SR_Pos) /*!< 0x40000000 */
14583
14584 /******************** Bit definition for RCC_PLLSAICFGR register ************/
14585 #define RCC_PLLSAICFGR_PLLSAIN_Pos (6U)
14586 #define RCC_PLLSAICFGR_PLLSAIN_Msk (0x1FFU << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00007FC0 */
14587 #define RCC_PLLSAICFGR_PLLSAIN RCC_PLLSAICFGR_PLLSAIN_Msk
14588 #define RCC_PLLSAICFGR_PLLSAIN_0 (0x001U << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00000040 */
14589 #define RCC_PLLSAICFGR_PLLSAIN_1 (0x002U << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00000080 */
14590 #define RCC_PLLSAICFGR_PLLSAIN_2 (0x004U << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00000100 */
14591 #define RCC_PLLSAICFGR_PLLSAIN_3 (0x008U << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00000200 */
14592 #define RCC_PLLSAICFGR_PLLSAIN_4 (0x010U << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00000400 */
14593 #define RCC_PLLSAICFGR_PLLSAIN_5 (0x020U << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00000800 */
14594 #define RCC_PLLSAICFGR_PLLSAIN_6 (0x040U << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00001000 */
14595 #define RCC_PLLSAICFGR_PLLSAIN_7 (0x080U << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00002000 */
14596 #define RCC_PLLSAICFGR_PLLSAIN_8 (0x100U << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00004000 */
14597
14598 #define RCC_PLLSAICFGR_PLLSAIP_Pos (16U)
14599 #define RCC_PLLSAICFGR_PLLSAIP_Msk (0x3U << RCC_PLLSAICFGR_PLLSAIP_Pos) /*!< 0x00030000 */
14600 #define RCC_PLLSAICFGR_PLLSAIP RCC_PLLSAICFGR_PLLSAIP_Msk
14601 #define RCC_PLLSAICFGR_PLLSAIP_0 (0x1U << RCC_PLLSAICFGR_PLLSAIP_Pos) /*!< 0x00010000 */
14602 #define RCC_PLLSAICFGR_PLLSAIP_1 (0x2U << RCC_PLLSAICFGR_PLLSAIP_Pos) /*!< 0x00020000 */
14603
14604 #define RCC_PLLSAICFGR_PLLSAIQ_Pos (24U)
14605 #define RCC_PLLSAICFGR_PLLSAIQ_Msk (0xFU << RCC_PLLSAICFGR_PLLSAIQ_Pos) /*!< 0x0F000000 */
14606 #define RCC_PLLSAICFGR_PLLSAIQ RCC_PLLSAICFGR_PLLSAIQ_Msk
14607 #define RCC_PLLSAICFGR_PLLSAIQ_0 (0x1U << RCC_PLLSAICFGR_PLLSAIQ_Pos) /*!< 0x01000000 */
14608 #define RCC_PLLSAICFGR_PLLSAIQ_1 (0x2U << RCC_PLLSAICFGR_PLLSAIQ_Pos) /*!< 0x02000000 */
14609 #define RCC_PLLSAICFGR_PLLSAIQ_2 (0x4U << RCC_PLLSAICFGR_PLLSAIQ_Pos) /*!< 0x04000000 */
14610 #define RCC_PLLSAICFGR_PLLSAIQ_3 (0x8U << RCC_PLLSAICFGR_PLLSAIQ_Pos) /*!< 0x08000000 */
14611
14612 #define RCC_PLLSAICFGR_PLLSAIR_Pos (28U)
14613 #define RCC_PLLSAICFGR_PLLSAIR_Msk (0x7U << RCC_PLLSAICFGR_PLLSAIR_Pos) /*!< 0x70000000 */
14614 #define RCC_PLLSAICFGR_PLLSAIR RCC_PLLSAICFGR_PLLSAIR_Msk
14615 #define RCC_PLLSAICFGR_PLLSAIR_0 (0x1U << RCC_PLLSAICFGR_PLLSAIR_Pos) /*!< 0x10000000 */
14616 #define RCC_PLLSAICFGR_PLLSAIR_1 (0x2U << RCC_PLLSAICFGR_PLLSAIR_Pos) /*!< 0x20000000 */
14617 #define RCC_PLLSAICFGR_PLLSAIR_2 (0x4U << RCC_PLLSAICFGR_PLLSAIR_Pos) /*!< 0x40000000 */
14618
14619 /******************** Bit definition for RCC_DCKCFGR register ***************/
14620 #define RCC_DCKCFGR_PLLI2SDIVQ_Pos (0U)
14621 #define RCC_DCKCFGR_PLLI2SDIVQ_Msk (0x1FU << RCC_DCKCFGR_PLLI2SDIVQ_Pos) /*!< 0x0000001F */
14622 #define RCC_DCKCFGR_PLLI2SDIVQ RCC_DCKCFGR_PLLI2SDIVQ_Msk
14623 #define RCC_DCKCFGR_PLLI2SDIVQ_0 (0x01U << RCC_DCKCFGR_PLLI2SDIVQ_Pos) /*!< 0x00000001 */
14624 #define RCC_DCKCFGR_PLLI2SDIVQ_1 (0x02U << RCC_DCKCFGR_PLLI2SDIVQ_Pos) /*!< 0x00000002 */
14625 #define RCC_DCKCFGR_PLLI2SDIVQ_2 (0x04U << RCC_DCKCFGR_PLLI2SDIVQ_Pos) /*!< 0x00000004 */
14626 #define RCC_DCKCFGR_PLLI2SDIVQ_3 (0x08U << RCC_DCKCFGR_PLLI2SDIVQ_Pos) /*!< 0x00000008 */
14627 #define RCC_DCKCFGR_PLLI2SDIVQ_4 (0x10U << RCC_DCKCFGR_PLLI2SDIVQ_Pos) /*!< 0x00000010 */
14628
14629 #define RCC_DCKCFGR_PLLSAIDIVQ_Pos (8U)
14630 #define RCC_DCKCFGR_PLLSAIDIVQ_Msk (0x1FU << RCC_DCKCFGR_PLLSAIDIVQ_Pos) /*!< 0x00001F00 */
14631 #define RCC_DCKCFGR_PLLSAIDIVQ RCC_DCKCFGR_PLLSAIDIVQ_Msk
14632 #define RCC_DCKCFGR_PLLSAIDIVQ_0 (0x01U << RCC_DCKCFGR_PLLSAIDIVQ_Pos) /*!< 0x00000100 */
14633 #define RCC_DCKCFGR_PLLSAIDIVQ_1 (0x02U << RCC_DCKCFGR_PLLSAIDIVQ_Pos) /*!< 0x00000200 */
14634 #define RCC_DCKCFGR_PLLSAIDIVQ_2 (0x04U << RCC_DCKCFGR_PLLSAIDIVQ_Pos) /*!< 0x00000400 */
14635 #define RCC_DCKCFGR_PLLSAIDIVQ_3 (0x08U << RCC_DCKCFGR_PLLSAIDIVQ_Pos) /*!< 0x00000800 */
14636 #define RCC_DCKCFGR_PLLSAIDIVQ_4 (0x10U << RCC_DCKCFGR_PLLSAIDIVQ_Pos) /*!< 0x00001000 */
14637 #define RCC_DCKCFGR_PLLSAIDIVR_Pos (16U)
14638 #define RCC_DCKCFGR_PLLSAIDIVR_Msk (0x3U << RCC_DCKCFGR_PLLSAIDIVR_Pos) /*!< 0x00030000 */
14639 #define RCC_DCKCFGR_PLLSAIDIVR RCC_DCKCFGR_PLLSAIDIVR_Msk
14640 #define RCC_DCKCFGR_PLLSAIDIVR_0 (0x1U << RCC_DCKCFGR_PLLSAIDIVR_Pos) /*!< 0x00010000 */
14641 #define RCC_DCKCFGR_PLLSAIDIVR_1 (0x2U << RCC_DCKCFGR_PLLSAIDIVR_Pos) /*!< 0x00020000 */
14642
14643 #define RCC_DCKCFGR_SAI1ASRC_Pos (20U)
14644 #define RCC_DCKCFGR_SAI1ASRC_Msk (0x3U << RCC_DCKCFGR_SAI1ASRC_Pos) /*!< 0x00300000 */
14645 #define RCC_DCKCFGR_SAI1ASRC RCC_DCKCFGR_SAI1ASRC_Msk
14646 #define RCC_DCKCFGR_SAI1ASRC_0 (0x1U << RCC_DCKCFGR_SAI1ASRC_Pos) /*!< 0x00100000 */
14647 #define RCC_DCKCFGR_SAI1ASRC_1 (0x2U << RCC_DCKCFGR_SAI1ASRC_Pos) /*!< 0x00200000 */
14648 #define RCC_DCKCFGR_SAI1BSRC_Pos (22U)
14649 #define RCC_DCKCFGR_SAI1BSRC_Msk (0x3U << RCC_DCKCFGR_SAI1BSRC_Pos) /*!< 0x00C00000 */
14650 #define RCC_DCKCFGR_SAI1BSRC RCC_DCKCFGR_SAI1BSRC_Msk
14651 #define RCC_DCKCFGR_SAI1BSRC_0 (0x1U << RCC_DCKCFGR_SAI1BSRC_Pos) /*!< 0x00400000 */
14652 #define RCC_DCKCFGR_SAI1BSRC_1 (0x2U << RCC_DCKCFGR_SAI1BSRC_Pos) /*!< 0x00800000 */
14653 #define RCC_DCKCFGR_TIMPRE_Pos (24U)
14654 #define RCC_DCKCFGR_TIMPRE_Msk (0x1U << RCC_DCKCFGR_TIMPRE_Pos) /*!< 0x01000000 */
14655 #define RCC_DCKCFGR_TIMPRE RCC_DCKCFGR_TIMPRE_Msk
14656 #define RCC_DCKCFGR_CK48MSEL_Pos (27U)
14657 #define RCC_DCKCFGR_CK48MSEL_Msk (0x1U << RCC_DCKCFGR_CK48MSEL_Pos) /*!< 0x08000000 */
14658 #define RCC_DCKCFGR_CK48MSEL RCC_DCKCFGR_CK48MSEL_Msk
14659 #define RCC_DCKCFGR_SDIOSEL_Pos (28U)
14660 #define RCC_DCKCFGR_SDIOSEL_Msk (0x1U << RCC_DCKCFGR_SDIOSEL_Pos) /*!< 0x10000000 */
14661 #define RCC_DCKCFGR_SDIOSEL RCC_DCKCFGR_SDIOSEL_Msk
14662 #define RCC_DCKCFGR_DSISEL_Pos (29U)
14663 #define RCC_DCKCFGR_DSISEL_Msk (0x1U << RCC_DCKCFGR_DSISEL_Pos) /*!< 0x20000000 */
14664 #define RCC_DCKCFGR_DSISEL RCC_DCKCFGR_DSISEL_Msk
14665
14666
14667 /******************************************************************************/
14668 /* */
14669 /* RNG */
14670 /* */
14671 /******************************************************************************/
14672 /******************** Bits definition for RNG_CR register *******************/
14673 #define RNG_CR_RNGEN_Pos (2U)
14674 #define RNG_CR_RNGEN_Msk (0x1U << RNG_CR_RNGEN_Pos) /*!< 0x00000004 */
14675 #define RNG_CR_RNGEN RNG_CR_RNGEN_Msk
14676 #define RNG_CR_IE_Pos (3U)
14677 #define RNG_CR_IE_Msk (0x1U << RNG_CR_IE_Pos) /*!< 0x00000008 */
14678 #define RNG_CR_IE RNG_CR_IE_Msk
14679
14680 /******************** Bits definition for RNG_SR register *******************/
14681 #define RNG_SR_DRDY_Pos (0U)
14682 #define RNG_SR_DRDY_Msk (0x1U << RNG_SR_DRDY_Pos) /*!< 0x00000001 */
14683 #define RNG_SR_DRDY RNG_SR_DRDY_Msk
14684 #define RNG_SR_CECS_Pos (1U)
14685 #define RNG_SR_CECS_Msk (0x1U << RNG_SR_CECS_Pos) /*!< 0x00000002 */
14686 #define RNG_SR_CECS RNG_SR_CECS_Msk
14687 #define RNG_SR_SECS_Pos (2U)
14688 #define RNG_SR_SECS_Msk (0x1U << RNG_SR_SECS_Pos) /*!< 0x00000004 */
14689 #define RNG_SR_SECS RNG_SR_SECS_Msk
14690 #define RNG_SR_CEIS_Pos (5U)
14691 #define RNG_SR_CEIS_Msk (0x1U << RNG_SR_CEIS_Pos) /*!< 0x00000020 */
14692 #define RNG_SR_CEIS RNG_SR_CEIS_Msk
14693 #define RNG_SR_SEIS_Pos (6U)
14694 #define RNG_SR_SEIS_Msk (0x1U << RNG_SR_SEIS_Pos) /*!< 0x00000040 */
14695 #define RNG_SR_SEIS RNG_SR_SEIS_Msk
14696
14697 /******************************************************************************/
14698 /* */
14699 /* Real-Time Clock (RTC) */
14700 /* */
14701 /******************************************************************************/
14702 /*
14703 * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
14704 */
14705 #define RTC_TAMPER2_SUPPORT /*!< TAMPER 2 feature support */
14706 #define RTC_AF2_SUPPORT /*!< RTC Alternate Function 2 mapping support */
14707 /******************** Bits definition for RTC_TR register *******************/
14708 #define RTC_TR_PM_Pos (22U)
14709 #define RTC_TR_PM_Msk (0x1U << RTC_TR_PM_Pos) /*!< 0x00400000 */
14710 #define RTC_TR_PM RTC_TR_PM_Msk
14711 #define RTC_TR_HT_Pos (20U)
14712 #define RTC_TR_HT_Msk (0x3U << RTC_TR_HT_Pos) /*!< 0x00300000 */
14713 #define RTC_TR_HT RTC_TR_HT_Msk
14714 #define RTC_TR_HT_0 (0x1U << RTC_TR_HT_Pos) /*!< 0x00100000 */
14715 #define RTC_TR_HT_1 (0x2U << RTC_TR_HT_Pos) /*!< 0x00200000 */
14716 #define RTC_TR_HU_Pos (16U)
14717 #define RTC_TR_HU_Msk (0xFU << RTC_TR_HU_Pos) /*!< 0x000F0000 */
14718 #define RTC_TR_HU RTC_TR_HU_Msk
14719 #define RTC_TR_HU_0 (0x1U << RTC_TR_HU_Pos) /*!< 0x00010000 */
14720 #define RTC_TR_HU_1 (0x2U << RTC_TR_HU_Pos) /*!< 0x00020000 */
14721 #define RTC_TR_HU_2 (0x4U << RTC_TR_HU_Pos) /*!< 0x00040000 */
14722 #define RTC_TR_HU_3 (0x8U << RTC_TR_HU_Pos) /*!< 0x00080000 */
14723 #define RTC_TR_MNT_Pos (12U)
14724 #define RTC_TR_MNT_Msk (0x7U << RTC_TR_MNT_Pos) /*!< 0x00007000 */
14725 #define RTC_TR_MNT RTC_TR_MNT_Msk
14726 #define RTC_TR_MNT_0 (0x1U << RTC_TR_MNT_Pos) /*!< 0x00001000 */
14727 #define RTC_TR_MNT_1 (0x2U << RTC_TR_MNT_Pos) /*!< 0x00002000 */
14728 #define RTC_TR_MNT_2 (0x4U << RTC_TR_MNT_Pos) /*!< 0x00004000 */
14729 #define RTC_TR_MNU_Pos (8U)
14730 #define RTC_TR_MNU_Msk (0xFU << RTC_TR_MNU_Pos) /*!< 0x00000F00 */
14731 #define RTC_TR_MNU RTC_TR_MNU_Msk
14732 #define RTC_TR_MNU_0 (0x1U << RTC_TR_MNU_Pos) /*!< 0x00000100 */
14733 #define RTC_TR_MNU_1 (0x2U << RTC_TR_MNU_Pos) /*!< 0x00000200 */
14734 #define RTC_TR_MNU_2 (0x4U << RTC_TR_MNU_Pos) /*!< 0x00000400 */
14735 #define RTC_TR_MNU_3 (0x8U << RTC_TR_MNU_Pos) /*!< 0x00000800 */
14736 #define RTC_TR_ST_Pos (4U)
14737 #define RTC_TR_ST_Msk (0x7U << RTC_TR_ST_Pos) /*!< 0x00000070 */
14738 #define RTC_TR_ST RTC_TR_ST_Msk
14739 #define RTC_TR_ST_0 (0x1U << RTC_TR_ST_Pos) /*!< 0x00000010 */
14740 #define RTC_TR_ST_1 (0x2U << RTC_TR_ST_Pos) /*!< 0x00000020 */
14741 #define RTC_TR_ST_2 (0x4U << RTC_TR_ST_Pos) /*!< 0x00000040 */
14742 #define RTC_TR_SU_Pos (0U)
14743 #define RTC_TR_SU_Msk (0xFU << RTC_TR_SU_Pos) /*!< 0x0000000F */
14744 #define RTC_TR_SU RTC_TR_SU_Msk
14745 #define RTC_TR_SU_0 (0x1U << RTC_TR_SU_Pos) /*!< 0x00000001 */
14746 #define RTC_TR_SU_1 (0x2U << RTC_TR_SU_Pos) /*!< 0x00000002 */
14747 #define RTC_TR_SU_2 (0x4U << RTC_TR_SU_Pos) /*!< 0x00000004 */
14748 #define RTC_TR_SU_3 (0x8U << RTC_TR_SU_Pos) /*!< 0x00000008 */
14749
14750 /******************** Bits definition for RTC_DR register *******************/
14751 #define RTC_DR_YT_Pos (20U)
14752 #define RTC_DR_YT_Msk (0xFU << RTC_DR_YT_Pos) /*!< 0x00F00000 */
14753 #define RTC_DR_YT RTC_DR_YT_Msk
14754 #define RTC_DR_YT_0 (0x1U << RTC_DR_YT_Pos) /*!< 0x00100000 */
14755 #define RTC_DR_YT_1 (0x2U << RTC_DR_YT_Pos) /*!< 0x00200000 */
14756 #define RTC_DR_YT_2 (0x4U << RTC_DR_YT_Pos) /*!< 0x00400000 */
14757 #define RTC_DR_YT_3 (0x8U << RTC_DR_YT_Pos) /*!< 0x00800000 */
14758 #define RTC_DR_YU_Pos (16U)
14759 #define RTC_DR_YU_Msk (0xFU << RTC_DR_YU_Pos) /*!< 0x000F0000 */
14760 #define RTC_DR_YU RTC_DR_YU_Msk
14761 #define RTC_DR_YU_0 (0x1U << RTC_DR_YU_Pos) /*!< 0x00010000 */
14762 #define RTC_DR_YU_1 (0x2U << RTC_DR_YU_Pos) /*!< 0x00020000 */
14763 #define RTC_DR_YU_2 (0x4U << RTC_DR_YU_Pos) /*!< 0x00040000 */
14764 #define RTC_DR_YU_3 (0x8U << RTC_DR_YU_Pos) /*!< 0x00080000 */
14765 #define RTC_DR_WDU_Pos (13U)
14766 #define RTC_DR_WDU_Msk (0x7U << RTC_DR_WDU_Pos) /*!< 0x0000E000 */
14767 #define RTC_DR_WDU RTC_DR_WDU_Msk
14768 #define RTC_DR_WDU_0 (0x1U << RTC_DR_WDU_Pos) /*!< 0x00002000 */
14769 #define RTC_DR_WDU_1 (0x2U << RTC_DR_WDU_Pos) /*!< 0x00004000 */
14770 #define RTC_DR_WDU_2 (0x4U << RTC_DR_WDU_Pos) /*!< 0x00008000 */
14771 #define RTC_DR_MT_Pos (12U)
14772 #define RTC_DR_MT_Msk (0x1U << RTC_DR_MT_Pos) /*!< 0x00001000 */
14773 #define RTC_DR_MT RTC_DR_MT_Msk
14774 #define RTC_DR_MU_Pos (8U)
14775 #define RTC_DR_MU_Msk (0xFU << RTC_DR_MU_Pos) /*!< 0x00000F00 */
14776 #define RTC_DR_MU RTC_DR_MU_Msk
14777 #define RTC_DR_MU_0 (0x1U << RTC_DR_MU_Pos) /*!< 0x00000100 */
14778 #define RTC_DR_MU_1 (0x2U << RTC_DR_MU_Pos) /*!< 0x00000200 */
14779 #define RTC_DR_MU_2 (0x4U << RTC_DR_MU_Pos) /*!< 0x00000400 */
14780 #define RTC_DR_MU_3 (0x8U << RTC_DR_MU_Pos) /*!< 0x00000800 */
14781 #define RTC_DR_DT_Pos (4U)
14782 #define RTC_DR_DT_Msk (0x3U << RTC_DR_DT_Pos) /*!< 0x00000030 */
14783 #define RTC_DR_DT RTC_DR_DT_Msk
14784 #define RTC_DR_DT_0 (0x1U << RTC_DR_DT_Pos) /*!< 0x00000010 */
14785 #define RTC_DR_DT_1 (0x2U << RTC_DR_DT_Pos) /*!< 0x00000020 */
14786 #define RTC_DR_DU_Pos (0U)
14787 #define RTC_DR_DU_Msk (0xFU << RTC_DR_DU_Pos) /*!< 0x0000000F */
14788 #define RTC_DR_DU RTC_DR_DU_Msk
14789 #define RTC_DR_DU_0 (0x1U << RTC_DR_DU_Pos) /*!< 0x00000001 */
14790 #define RTC_DR_DU_1 (0x2U << RTC_DR_DU_Pos) /*!< 0x00000002 */
14791 #define RTC_DR_DU_2 (0x4U << RTC_DR_DU_Pos) /*!< 0x00000004 */
14792 #define RTC_DR_DU_3 (0x8U << RTC_DR_DU_Pos) /*!< 0x00000008 */
14793
14794 /******************** Bits definition for RTC_CR register *******************/
14795 #define RTC_CR_COE_Pos (23U)
14796 #define RTC_CR_COE_Msk (0x1U << RTC_CR_COE_Pos) /*!< 0x00800000 */
14797 #define RTC_CR_COE RTC_CR_COE_Msk
14798 #define RTC_CR_OSEL_Pos (21U)
14799 #define RTC_CR_OSEL_Msk (0x3U << RTC_CR_OSEL_Pos) /*!< 0x00600000 */
14800 #define RTC_CR_OSEL RTC_CR_OSEL_Msk
14801 #define RTC_CR_OSEL_0 (0x1U << RTC_CR_OSEL_Pos) /*!< 0x00200000 */
14802 #define RTC_CR_OSEL_1 (0x2U << RTC_CR_OSEL_Pos) /*!< 0x00400000 */
14803 #define RTC_CR_POL_Pos (20U)
14804 #define RTC_CR_POL_Msk (0x1U << RTC_CR_POL_Pos) /*!< 0x00100000 */
14805 #define RTC_CR_POL RTC_CR_POL_Msk
14806 #define RTC_CR_COSEL_Pos (19U)
14807 #define RTC_CR_COSEL_Msk (0x1U << RTC_CR_COSEL_Pos) /*!< 0x00080000 */
14808 #define RTC_CR_COSEL RTC_CR_COSEL_Msk
14809 #define RTC_CR_BKP_Pos (18U)
14810 #define RTC_CR_BKP_Msk (0x1U << RTC_CR_BKP_Pos) /*!< 0x00040000 */
14811 #define RTC_CR_BKP RTC_CR_BKP_Msk
14812 #define RTC_CR_SUB1H_Pos (17U)
14813 #define RTC_CR_SUB1H_Msk (0x1U << RTC_CR_SUB1H_Pos) /*!< 0x00020000 */
14814 #define RTC_CR_SUB1H RTC_CR_SUB1H_Msk
14815 #define RTC_CR_ADD1H_Pos (16U)
14816 #define RTC_CR_ADD1H_Msk (0x1U << RTC_CR_ADD1H_Pos) /*!< 0x00010000 */
14817 #define RTC_CR_ADD1H RTC_CR_ADD1H_Msk
14818 #define RTC_CR_TSIE_Pos (15U)
14819 #define RTC_CR_TSIE_Msk (0x1U << RTC_CR_TSIE_Pos) /*!< 0x00008000 */
14820 #define RTC_CR_TSIE RTC_CR_TSIE_Msk
14821 #define RTC_CR_WUTIE_Pos (14U)
14822 #define RTC_CR_WUTIE_Msk (0x1U << RTC_CR_WUTIE_Pos) /*!< 0x00004000 */
14823 #define RTC_CR_WUTIE RTC_CR_WUTIE_Msk
14824 #define RTC_CR_ALRBIE_Pos (13U)
14825 #define RTC_CR_ALRBIE_Msk (0x1U << RTC_CR_ALRBIE_Pos) /*!< 0x00002000 */
14826 #define RTC_CR_ALRBIE RTC_CR_ALRBIE_Msk
14827 #define RTC_CR_ALRAIE_Pos (12U)
14828 #define RTC_CR_ALRAIE_Msk (0x1U << RTC_CR_ALRAIE_Pos) /*!< 0x00001000 */
14829 #define RTC_CR_ALRAIE RTC_CR_ALRAIE_Msk
14830 #define RTC_CR_TSE_Pos (11U)
14831 #define RTC_CR_TSE_Msk (0x1U << RTC_CR_TSE_Pos) /*!< 0x00000800 */
14832 #define RTC_CR_TSE RTC_CR_TSE_Msk
14833 #define RTC_CR_WUTE_Pos (10U)
14834 #define RTC_CR_WUTE_Msk (0x1U << RTC_CR_WUTE_Pos) /*!< 0x00000400 */
14835 #define RTC_CR_WUTE RTC_CR_WUTE_Msk
14836 #define RTC_CR_ALRBE_Pos (9U)
14837 #define RTC_CR_ALRBE_Msk (0x1U << RTC_CR_ALRBE_Pos) /*!< 0x00000200 */
14838 #define RTC_CR_ALRBE RTC_CR_ALRBE_Msk
14839 #define RTC_CR_ALRAE_Pos (8U)
14840 #define RTC_CR_ALRAE_Msk (0x1U << RTC_CR_ALRAE_Pos) /*!< 0x00000100 */
14841 #define RTC_CR_ALRAE RTC_CR_ALRAE_Msk
14842 #define RTC_CR_DCE_Pos (7U)
14843 #define RTC_CR_DCE_Msk (0x1U << RTC_CR_DCE_Pos) /*!< 0x00000080 */
14844 #define RTC_CR_DCE RTC_CR_DCE_Msk
14845 #define RTC_CR_FMT_Pos (6U)
14846 #define RTC_CR_FMT_Msk (0x1U << RTC_CR_FMT_Pos) /*!< 0x00000040 */
14847 #define RTC_CR_FMT RTC_CR_FMT_Msk
14848 #define RTC_CR_BYPSHAD_Pos (5U)
14849 #define RTC_CR_BYPSHAD_Msk (0x1U << RTC_CR_BYPSHAD_Pos) /*!< 0x00000020 */
14850 #define RTC_CR_BYPSHAD RTC_CR_BYPSHAD_Msk
14851 #define RTC_CR_REFCKON_Pos (4U)
14852 #define RTC_CR_REFCKON_Msk (0x1U << RTC_CR_REFCKON_Pos) /*!< 0x00000010 */
14853 #define RTC_CR_REFCKON RTC_CR_REFCKON_Msk
14854 #define RTC_CR_TSEDGE_Pos (3U)
14855 #define RTC_CR_TSEDGE_Msk (0x1U << RTC_CR_TSEDGE_Pos) /*!< 0x00000008 */
14856 #define RTC_CR_TSEDGE RTC_CR_TSEDGE_Msk
14857 #define RTC_CR_WUCKSEL_Pos (0U)
14858 #define RTC_CR_WUCKSEL_Msk (0x7U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000007 */
14859 #define RTC_CR_WUCKSEL RTC_CR_WUCKSEL_Msk
14860 #define RTC_CR_WUCKSEL_0 (0x1U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000001 */
14861 #define RTC_CR_WUCKSEL_1 (0x2U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000002 */
14862 #define RTC_CR_WUCKSEL_2 (0x4U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000004 */
14863
14864 /* Legacy defines */
14865 #define RTC_CR_BCK RTC_CR_BKP
14866
14867 /******************** Bits definition for RTC_ISR register ******************/
14868 #define RTC_ISR_RECALPF_Pos (16U)
14869 #define RTC_ISR_RECALPF_Msk (0x1U << RTC_ISR_RECALPF_Pos) /*!< 0x00010000 */
14870 #define RTC_ISR_RECALPF RTC_ISR_RECALPF_Msk
14871 #define RTC_ISR_TAMP1F_Pos (13U)
14872 #define RTC_ISR_TAMP1F_Msk (0x1U << RTC_ISR_TAMP1F_Pos) /*!< 0x00002000 */
14873 #define RTC_ISR_TAMP1F RTC_ISR_TAMP1F_Msk
14874 #define RTC_ISR_TAMP2F_Pos (14U)
14875 #define RTC_ISR_TAMP2F_Msk (0x1U << RTC_ISR_TAMP2F_Pos) /*!< 0x00004000 */
14876 #define RTC_ISR_TAMP2F RTC_ISR_TAMP2F_Msk
14877 #define RTC_ISR_TSOVF_Pos (12U)
14878 #define RTC_ISR_TSOVF_Msk (0x1U << RTC_ISR_TSOVF_Pos) /*!< 0x00001000 */
14879 #define RTC_ISR_TSOVF RTC_ISR_TSOVF_Msk
14880 #define RTC_ISR_TSF_Pos (11U)
14881 #define RTC_ISR_TSF_Msk (0x1U << RTC_ISR_TSF_Pos) /*!< 0x00000800 */
14882 #define RTC_ISR_TSF RTC_ISR_TSF_Msk
14883 #define RTC_ISR_WUTF_Pos (10U)
14884 #define RTC_ISR_WUTF_Msk (0x1U << RTC_ISR_WUTF_Pos) /*!< 0x00000400 */
14885 #define RTC_ISR_WUTF RTC_ISR_WUTF_Msk
14886 #define RTC_ISR_ALRBF_Pos (9U)
14887 #define RTC_ISR_ALRBF_Msk (0x1U << RTC_ISR_ALRBF_Pos) /*!< 0x00000200 */
14888 #define RTC_ISR_ALRBF RTC_ISR_ALRBF_Msk
14889 #define RTC_ISR_ALRAF_Pos (8U)
14890 #define RTC_ISR_ALRAF_Msk (0x1U << RTC_ISR_ALRAF_Pos) /*!< 0x00000100 */
14891 #define RTC_ISR_ALRAF RTC_ISR_ALRAF_Msk
14892 #define RTC_ISR_INIT_Pos (7U)
14893 #define RTC_ISR_INIT_Msk (0x1U << RTC_ISR_INIT_Pos) /*!< 0x00000080 */
14894 #define RTC_ISR_INIT RTC_ISR_INIT_Msk
14895 #define RTC_ISR_INITF_Pos (6U)
14896 #define RTC_ISR_INITF_Msk (0x1U << RTC_ISR_INITF_Pos) /*!< 0x00000040 */
14897 #define RTC_ISR_INITF RTC_ISR_INITF_Msk
14898 #define RTC_ISR_RSF_Pos (5U)
14899 #define RTC_ISR_RSF_Msk (0x1U << RTC_ISR_RSF_Pos) /*!< 0x00000020 */
14900 #define RTC_ISR_RSF RTC_ISR_RSF_Msk
14901 #define RTC_ISR_INITS_Pos (4U)
14902 #define RTC_ISR_INITS_Msk (0x1U << RTC_ISR_INITS_Pos) /*!< 0x00000010 */
14903 #define RTC_ISR_INITS RTC_ISR_INITS_Msk
14904 #define RTC_ISR_SHPF_Pos (3U)
14905 #define RTC_ISR_SHPF_Msk (0x1U << RTC_ISR_SHPF_Pos) /*!< 0x00000008 */
14906 #define RTC_ISR_SHPF RTC_ISR_SHPF_Msk
14907 #define RTC_ISR_WUTWF_Pos (2U)
14908 #define RTC_ISR_WUTWF_Msk (0x1U << RTC_ISR_WUTWF_Pos) /*!< 0x00000004 */
14909 #define RTC_ISR_WUTWF RTC_ISR_WUTWF_Msk
14910 #define RTC_ISR_ALRBWF_Pos (1U)
14911 #define RTC_ISR_ALRBWF_Msk (0x1U << RTC_ISR_ALRBWF_Pos) /*!< 0x00000002 */
14912 #define RTC_ISR_ALRBWF RTC_ISR_ALRBWF_Msk
14913 #define RTC_ISR_ALRAWF_Pos (0U)
14914 #define RTC_ISR_ALRAWF_Msk (0x1U << RTC_ISR_ALRAWF_Pos) /*!< 0x00000001 */
14915 #define RTC_ISR_ALRAWF RTC_ISR_ALRAWF_Msk
14916
14917 /******************** Bits definition for RTC_PRER register *****************/
14918 #define RTC_PRER_PREDIV_A_Pos (16U)
14919 #define RTC_PRER_PREDIV_A_Msk (0x7FU << RTC_PRER_PREDIV_A_Pos) /*!< 0x007F0000 */
14920 #define RTC_PRER_PREDIV_A RTC_PRER_PREDIV_A_Msk
14921 #define RTC_PRER_PREDIV_S_Pos (0U)
14922 #define RTC_PRER_PREDIV_S_Msk (0x7FFFU << RTC_PRER_PREDIV_S_Pos) /*!< 0x00007FFF */
14923 #define RTC_PRER_PREDIV_S RTC_PRER_PREDIV_S_Msk
14924
14925 /******************** Bits definition for RTC_WUTR register *****************/
14926 #define RTC_WUTR_WUT_Pos (0U)
14927 #define RTC_WUTR_WUT_Msk (0xFFFFU << RTC_WUTR_WUT_Pos) /*!< 0x0000FFFF */
14928 #define RTC_WUTR_WUT RTC_WUTR_WUT_Msk
14929
14930 /******************** Bits definition for RTC_CALIBR register ***************/
14931 #define RTC_CALIBR_DCS_Pos (7U)
14932 #define RTC_CALIBR_DCS_Msk (0x1U << RTC_CALIBR_DCS_Pos) /*!< 0x00000080 */
14933 #define RTC_CALIBR_DCS RTC_CALIBR_DCS_Msk
14934 #define RTC_CALIBR_DC_Pos (0U)
14935 #define RTC_CALIBR_DC_Msk (0x1FU << RTC_CALIBR_DC_Pos) /*!< 0x0000001F */
14936 #define RTC_CALIBR_DC RTC_CALIBR_DC_Msk
14937
14938 /******************** Bits definition for RTC_ALRMAR register ***************/
14939 #define RTC_ALRMAR_MSK4_Pos (31U)
14940 #define RTC_ALRMAR_MSK4_Msk (0x1U << RTC_ALRMAR_MSK4_Pos) /*!< 0x80000000 */
14941 #define RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk
14942 #define RTC_ALRMAR_WDSEL_Pos (30U)
14943 #define RTC_ALRMAR_WDSEL_Msk (0x1U << RTC_ALRMAR_WDSEL_Pos) /*!< 0x40000000 */
14944 #define RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk
14945 #define RTC_ALRMAR_DT_Pos (28U)
14946 #define RTC_ALRMAR_DT_Msk (0x3U << RTC_ALRMAR_DT_Pos) /*!< 0x30000000 */
14947 #define RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk
14948 #define RTC_ALRMAR_DT_0 (0x1U << RTC_ALRMAR_DT_Pos) /*!< 0x10000000 */
14949 #define RTC_ALRMAR_DT_1 (0x2U << RTC_ALRMAR_DT_Pos) /*!< 0x20000000 */
14950 #define RTC_ALRMAR_DU_Pos (24U)
14951 #define RTC_ALRMAR_DU_Msk (0xFU << RTC_ALRMAR_DU_Pos) /*!< 0x0F000000 */
14952 #define RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk
14953 #define RTC_ALRMAR_DU_0 (0x1U << RTC_ALRMAR_DU_Pos) /*!< 0x01000000 */
14954 #define RTC_ALRMAR_DU_1 (0x2U << RTC_ALRMAR_DU_Pos) /*!< 0x02000000 */
14955 #define RTC_ALRMAR_DU_2 (0x4U << RTC_ALRMAR_DU_Pos) /*!< 0x04000000 */
14956 #define RTC_ALRMAR_DU_3 (0x8U << RTC_ALRMAR_DU_Pos) /*!< 0x08000000 */
14957 #define RTC_ALRMAR_MSK3_Pos (23U)
14958 #define RTC_ALRMAR_MSK3_Msk (0x1U << RTC_ALRMAR_MSK3_Pos) /*!< 0x00800000 */
14959 #define RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk
14960 #define RTC_ALRMAR_PM_Pos (22U)
14961 #define RTC_ALRMAR_PM_Msk (0x1U << RTC_ALRMAR_PM_Pos) /*!< 0x00400000 */
14962 #define RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk
14963 #define RTC_ALRMAR_HT_Pos (20U)
14964 #define RTC_ALRMAR_HT_Msk (0x3U << RTC_ALRMAR_HT_Pos) /*!< 0x00300000 */
14965 #define RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk
14966 #define RTC_ALRMAR_HT_0 (0x1U << RTC_ALRMAR_HT_Pos) /*!< 0x00100000 */
14967 #define RTC_ALRMAR_HT_1 (0x2U << RTC_ALRMAR_HT_Pos) /*!< 0x00200000 */
14968 #define RTC_ALRMAR_HU_Pos (16U)
14969 #define RTC_ALRMAR_HU_Msk (0xFU << RTC_ALRMAR_HU_Pos) /*!< 0x000F0000 */
14970 #define RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk
14971 #define RTC_ALRMAR_HU_0 (0x1U << RTC_ALRMAR_HU_Pos) /*!< 0x00010000 */
14972 #define RTC_ALRMAR_HU_1 (0x2U << RTC_ALRMAR_HU_Pos) /*!< 0x00020000 */
14973 #define RTC_ALRMAR_HU_2 (0x4U << RTC_ALRMAR_HU_Pos) /*!< 0x00040000 */
14974 #define RTC_ALRMAR_HU_3 (0x8U << RTC_ALRMAR_HU_Pos) /*!< 0x00080000 */
14975 #define RTC_ALRMAR_MSK2_Pos (15U)
14976 #define RTC_ALRMAR_MSK2_Msk (0x1U << RTC_ALRMAR_MSK2_Pos) /*!< 0x00008000 */
14977 #define RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk
14978 #define RTC_ALRMAR_MNT_Pos (12U)
14979 #define RTC_ALRMAR_MNT_Msk (0x7U << RTC_ALRMAR_MNT_Pos) /*!< 0x00007000 */
14980 #define RTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk
14981 #define RTC_ALRMAR_MNT_0 (0x1U << RTC_ALRMAR_MNT_Pos) /*!< 0x00001000 */
14982 #define RTC_ALRMAR_MNT_1 (0x2U << RTC_ALRMAR_MNT_Pos) /*!< 0x00002000 */
14983 #define RTC_ALRMAR_MNT_2 (0x4U << RTC_ALRMAR_MNT_Pos) /*!< 0x00004000 */
14984 #define RTC_ALRMAR_MNU_Pos (8U)
14985 #define RTC_ALRMAR_MNU_Msk (0xFU << RTC_ALRMAR_MNU_Pos) /*!< 0x00000F00 */
14986 #define RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk
14987 #define RTC_ALRMAR_MNU_0 (0x1U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000100 */
14988 #define RTC_ALRMAR_MNU_1 (0x2U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000200 */
14989 #define RTC_ALRMAR_MNU_2 (0x4U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000400 */
14990 #define RTC_ALRMAR_MNU_3 (0x8U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000800 */
14991 #define RTC_ALRMAR_MSK1_Pos (7U)
14992 #define RTC_ALRMAR_MSK1_Msk (0x1U << RTC_ALRMAR_MSK1_Pos) /*!< 0x00000080 */
14993 #define RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_Msk
14994 #define RTC_ALRMAR_ST_Pos (4U)
14995 #define RTC_ALRMAR_ST_Msk (0x7U << RTC_ALRMAR_ST_Pos) /*!< 0x00000070 */
14996 #define RTC_ALRMAR_ST RTC_ALRMAR_ST_Msk
14997 #define RTC_ALRMAR_ST_0 (0x1U << RTC_ALRMAR_ST_Pos) /*!< 0x00000010 */
14998 #define RTC_ALRMAR_ST_1 (0x2U << RTC_ALRMAR_ST_Pos) /*!< 0x00000020 */
14999 #define RTC_ALRMAR_ST_2 (0x4U << RTC_ALRMAR_ST_Pos) /*!< 0x00000040 */
15000 #define RTC_ALRMAR_SU_Pos (0U)
15001 #define RTC_ALRMAR_SU_Msk (0xFU << RTC_ALRMAR_SU_Pos) /*!< 0x0000000F */
15002 #define RTC_ALRMAR_SU RTC_ALRMAR_SU_Msk
15003 #define RTC_ALRMAR_SU_0 (0x1U << RTC_ALRMAR_SU_Pos) /*!< 0x00000001 */
15004 #define RTC_ALRMAR_SU_1 (0x2U << RTC_ALRMAR_SU_Pos) /*!< 0x00000002 */
15005 #define RTC_ALRMAR_SU_2 (0x4U << RTC_ALRMAR_SU_Pos) /*!< 0x00000004 */
15006 #define RTC_ALRMAR_SU_3 (0x8U << RTC_ALRMAR_SU_Pos) /*!< 0x00000008 */
15007
15008 /******************** Bits definition for RTC_ALRMBR register ***************/
15009 #define RTC_ALRMBR_MSK4_Pos (31U)
15010 #define RTC_ALRMBR_MSK4_Msk (0x1U << RTC_ALRMBR_MSK4_Pos) /*!< 0x80000000 */
15011 #define RTC_ALRMBR_MSK4 RTC_ALRMBR_MSK4_Msk
15012 #define RTC_ALRMBR_WDSEL_Pos (30U)
15013 #define RTC_ALRMBR_WDSEL_Msk (0x1U << RTC_ALRMBR_WDSEL_Pos) /*!< 0x40000000 */
15014 #define RTC_ALRMBR_WDSEL RTC_ALRMBR_WDSEL_Msk
15015 #define RTC_ALRMBR_DT_Pos (28U)
15016 #define RTC_ALRMBR_DT_Msk (0x3U << RTC_ALRMBR_DT_Pos) /*!< 0x30000000 */
15017 #define RTC_ALRMBR_DT RTC_ALRMBR_DT_Msk
15018 #define RTC_ALRMBR_DT_0 (0x1U << RTC_ALRMBR_DT_Pos) /*!< 0x10000000 */
15019 #define RTC_ALRMBR_DT_1 (0x2U << RTC_ALRMBR_DT_Pos) /*!< 0x20000000 */
15020 #define RTC_ALRMBR_DU_Pos (24U)
15021 #define RTC_ALRMBR_DU_Msk (0xFU << RTC_ALRMBR_DU_Pos) /*!< 0x0F000000 */
15022 #define RTC_ALRMBR_DU RTC_ALRMBR_DU_Msk
15023 #define RTC_ALRMBR_DU_0 (0x1U << RTC_ALRMBR_DU_Pos) /*!< 0x01000000 */
15024 #define RTC_ALRMBR_DU_1 (0x2U << RTC_ALRMBR_DU_Pos) /*!< 0x02000000 */
15025 #define RTC_ALRMBR_DU_2 (0x4U << RTC_ALRMBR_DU_Pos) /*!< 0x04000000 */
15026 #define RTC_ALRMBR_DU_3 (0x8U << RTC_ALRMBR_DU_Pos) /*!< 0x08000000 */
15027 #define RTC_ALRMBR_MSK3_Pos (23U)
15028 #define RTC_ALRMBR_MSK3_Msk (0x1U << RTC_ALRMBR_MSK3_Pos) /*!< 0x00800000 */
15029 #define RTC_ALRMBR_MSK3 RTC_ALRMBR_MSK3_Msk
15030 #define RTC_ALRMBR_PM_Pos (22U)
15031 #define RTC_ALRMBR_PM_Msk (0x1U << RTC_ALRMBR_PM_Pos) /*!< 0x00400000 */
15032 #define RTC_ALRMBR_PM RTC_ALRMBR_PM_Msk
15033 #define RTC_ALRMBR_HT_Pos (20U)
15034 #define RTC_ALRMBR_HT_Msk (0x3U << RTC_ALRMBR_HT_Pos) /*!< 0x00300000 */
15035 #define RTC_ALRMBR_HT RTC_ALRMBR_HT_Msk
15036 #define RTC_ALRMBR_HT_0 (0x1U << RTC_ALRMBR_HT_Pos) /*!< 0x00100000 */
15037 #define RTC_ALRMBR_HT_1 (0x2U << RTC_ALRMBR_HT_Pos) /*!< 0x00200000 */
15038 #define RTC_ALRMBR_HU_Pos (16U)
15039 #define RTC_ALRMBR_HU_Msk (0xFU << RTC_ALRMBR_HU_Pos) /*!< 0x000F0000 */
15040 #define RTC_ALRMBR_HU RTC_ALRMBR_HU_Msk
15041 #define RTC_ALRMBR_HU_0 (0x1U << RTC_ALRMBR_HU_Pos) /*!< 0x00010000 */
15042 #define RTC_ALRMBR_HU_1 (0x2U << RTC_ALRMBR_HU_Pos) /*!< 0x00020000 */
15043 #define RTC_ALRMBR_HU_2 (0x4U << RTC_ALRMBR_HU_Pos) /*!< 0x00040000 */
15044 #define RTC_ALRMBR_HU_3 (0x8U << RTC_ALRMBR_HU_Pos) /*!< 0x00080000 */
15045 #define RTC_ALRMBR_MSK2_Pos (15U)
15046 #define RTC_ALRMBR_MSK2_Msk (0x1U << RTC_ALRMBR_MSK2_Pos) /*!< 0x00008000 */
15047 #define RTC_ALRMBR_MSK2 RTC_ALRMBR_MSK2_Msk
15048 #define RTC_ALRMBR_MNT_Pos (12U)
15049 #define RTC_ALRMBR_MNT_Msk (0x7U << RTC_ALRMBR_MNT_Pos) /*!< 0x00007000 */
15050 #define RTC_ALRMBR_MNT RTC_ALRMBR_MNT_Msk
15051 #define RTC_ALRMBR_MNT_0 (0x1U << RTC_ALRMBR_MNT_Pos) /*!< 0x00001000 */
15052 #define RTC_ALRMBR_MNT_1 (0x2U << RTC_ALRMBR_MNT_Pos) /*!< 0x00002000 */
15053 #define RTC_ALRMBR_MNT_2 (0x4U << RTC_ALRMBR_MNT_Pos) /*!< 0x00004000 */
15054 #define RTC_ALRMBR_MNU_Pos (8U)
15055 #define RTC_ALRMBR_MNU_Msk (0xFU << RTC_ALRMBR_MNU_Pos) /*!< 0x00000F00 */
15056 #define RTC_ALRMBR_MNU RTC_ALRMBR_MNU_Msk
15057 #define RTC_ALRMBR_MNU_0 (0x1U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000100 */
15058 #define RTC_ALRMBR_MNU_1 (0x2U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000200 */
15059 #define RTC_ALRMBR_MNU_2 (0x4U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000400 */
15060 #define RTC_ALRMBR_MNU_3 (0x8U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000800 */
15061 #define RTC_ALRMBR_MSK1_Pos (7U)
15062 #define RTC_ALRMBR_MSK1_Msk (0x1U << RTC_ALRMBR_MSK1_Pos) /*!< 0x00000080 */
15063 #define RTC_ALRMBR_MSK1 RTC_ALRMBR_MSK1_Msk
15064 #define RTC_ALRMBR_ST_Pos (4U)
15065 #define RTC_ALRMBR_ST_Msk (0x7U << RTC_ALRMBR_ST_Pos) /*!< 0x00000070 */
15066 #define RTC_ALRMBR_ST RTC_ALRMBR_ST_Msk
15067 #define RTC_ALRMBR_ST_0 (0x1U << RTC_ALRMBR_ST_Pos) /*!< 0x00000010 */
15068 #define RTC_ALRMBR_ST_1 (0x2U << RTC_ALRMBR_ST_Pos) /*!< 0x00000020 */
15069 #define RTC_ALRMBR_ST_2 (0x4U << RTC_ALRMBR_ST_Pos) /*!< 0x00000040 */
15070 #define RTC_ALRMBR_SU_Pos (0U)
15071 #define RTC_ALRMBR_SU_Msk (0xFU << RTC_ALRMBR_SU_Pos) /*!< 0x0000000F */
15072 #define RTC_ALRMBR_SU RTC_ALRMBR_SU_Msk
15073 #define RTC_ALRMBR_SU_0 (0x1U << RTC_ALRMBR_SU_Pos) /*!< 0x00000001 */
15074 #define RTC_ALRMBR_SU_1 (0x2U << RTC_ALRMBR_SU_Pos) /*!< 0x00000002 */
15075 #define RTC_ALRMBR_SU_2 (0x4U << RTC_ALRMBR_SU_Pos) /*!< 0x00000004 */
15076 #define RTC_ALRMBR_SU_3 (0x8U << RTC_ALRMBR_SU_Pos) /*!< 0x00000008 */
15077
15078 /******************** Bits definition for RTC_WPR register ******************/
15079 #define RTC_WPR_KEY_Pos (0U)
15080 #define RTC_WPR_KEY_Msk (0xFFU << RTC_WPR_KEY_Pos) /*!< 0x000000FF */
15081 #define RTC_WPR_KEY RTC_WPR_KEY_Msk
15082
15083 /******************** Bits definition for RTC_SSR register ******************/
15084 #define RTC_SSR_SS_Pos (0U)
15085 #define RTC_SSR_SS_Msk (0xFFFFU << RTC_SSR_SS_Pos) /*!< 0x0000FFFF */
15086 #define RTC_SSR_SS RTC_SSR_SS_Msk
15087
15088 /******************** Bits definition for RTC_SHIFTR register ***************/
15089 #define RTC_SHIFTR_SUBFS_Pos (0U)
15090 #define RTC_SHIFTR_SUBFS_Msk (0x7FFFU << RTC_SHIFTR_SUBFS_Pos) /*!< 0x00007FFF */
15091 #define RTC_SHIFTR_SUBFS RTC_SHIFTR_SUBFS_Msk
15092 #define RTC_SHIFTR_ADD1S_Pos (31U)
15093 #define RTC_SHIFTR_ADD1S_Msk (0x1U << RTC_SHIFTR_ADD1S_Pos) /*!< 0x80000000 */
15094 #define RTC_SHIFTR_ADD1S RTC_SHIFTR_ADD1S_Msk
15095
15096 /******************** Bits definition for RTC_TSTR register *****************/
15097 #define RTC_TSTR_PM_Pos (22U)
15098 #define RTC_TSTR_PM_Msk (0x1U << RTC_TSTR_PM_Pos) /*!< 0x00400000 */
15099 #define RTC_TSTR_PM RTC_TSTR_PM_Msk
15100 #define RTC_TSTR_HT_Pos (20U)
15101 #define RTC_TSTR_HT_Msk (0x3U << RTC_TSTR_HT_Pos) /*!< 0x00300000 */
15102 #define RTC_TSTR_HT RTC_TSTR_HT_Msk
15103 #define RTC_TSTR_HT_0 (0x1U << RTC_TSTR_HT_Pos) /*!< 0x00100000 */
15104 #define RTC_TSTR_HT_1 (0x2U << RTC_TSTR_HT_Pos) /*!< 0x00200000 */
15105 #define RTC_TSTR_HU_Pos (16U)
15106 #define RTC_TSTR_HU_Msk (0xFU << RTC_TSTR_HU_Pos) /*!< 0x000F0000 */
15107 #define RTC_TSTR_HU RTC_TSTR_HU_Msk
15108 #define RTC_TSTR_HU_0 (0x1U << RTC_TSTR_HU_Pos) /*!< 0x00010000 */
15109 #define RTC_TSTR_HU_1 (0x2U << RTC_TSTR_HU_Pos) /*!< 0x00020000 */
15110 #define RTC_TSTR_HU_2 (0x4U << RTC_TSTR_HU_Pos) /*!< 0x00040000 */
15111 #define RTC_TSTR_HU_3 (0x8U << RTC_TSTR_HU_Pos) /*!< 0x00080000 */
15112 #define RTC_TSTR_MNT_Pos (12U)
15113 #define RTC_TSTR_MNT_Msk (0x7U << RTC_TSTR_MNT_Pos) /*!< 0x00007000 */
15114 #define RTC_TSTR_MNT RTC_TSTR_MNT_Msk
15115 #define RTC_TSTR_MNT_0 (0x1U << RTC_TSTR_MNT_Pos) /*!< 0x00001000 */
15116 #define RTC_TSTR_MNT_1 (0x2U << RTC_TSTR_MNT_Pos) /*!< 0x00002000 */
15117 #define RTC_TSTR_MNT_2 (0x4U << RTC_TSTR_MNT_Pos) /*!< 0x00004000 */
15118 #define RTC_TSTR_MNU_Pos (8U)
15119 #define RTC_TSTR_MNU_Msk (0xFU << RTC_TSTR_MNU_Pos) /*!< 0x00000F00 */
15120 #define RTC_TSTR_MNU RTC_TSTR_MNU_Msk
15121 #define RTC_TSTR_MNU_0 (0x1U << RTC_TSTR_MNU_Pos) /*!< 0x00000100 */
15122 #define RTC_TSTR_MNU_1 (0x2U << RTC_TSTR_MNU_Pos) /*!< 0x00000200 */
15123 #define RTC_TSTR_MNU_2 (0x4U << RTC_TSTR_MNU_Pos) /*!< 0x00000400 */
15124 #define RTC_TSTR_MNU_3 (0x8U << RTC_TSTR_MNU_Pos) /*!< 0x00000800 */
15125 #define RTC_TSTR_ST_Pos (4U)
15126 #define RTC_TSTR_ST_Msk (0x7U << RTC_TSTR_ST_Pos) /*!< 0x00000070 */
15127 #define RTC_TSTR_ST RTC_TSTR_ST_Msk
15128 #define RTC_TSTR_ST_0 (0x1U << RTC_TSTR_ST_Pos) /*!< 0x00000010 */
15129 #define RTC_TSTR_ST_1 (0x2U << RTC_TSTR_ST_Pos) /*!< 0x00000020 */
15130 #define RTC_TSTR_ST_2 (0x4U << RTC_TSTR_ST_Pos) /*!< 0x00000040 */
15131 #define RTC_TSTR_SU_Pos (0U)
15132 #define RTC_TSTR_SU_Msk (0xFU << RTC_TSTR_SU_Pos) /*!< 0x0000000F */
15133 #define RTC_TSTR_SU RTC_TSTR_SU_Msk
15134 #define RTC_TSTR_SU_0 (0x1U << RTC_TSTR_SU_Pos) /*!< 0x00000001 */
15135 #define RTC_TSTR_SU_1 (0x2U << RTC_TSTR_SU_Pos) /*!< 0x00000002 */
15136 #define RTC_TSTR_SU_2 (0x4U << RTC_TSTR_SU_Pos) /*!< 0x00000004 */
15137 #define RTC_TSTR_SU_3 (0x8U << RTC_TSTR_SU_Pos) /*!< 0x00000008 */
15138
15139 /******************** Bits definition for RTC_TSDR register *****************/
15140 #define RTC_TSDR_WDU_Pos (13U)
15141 #define RTC_TSDR_WDU_Msk (0x7U << RTC_TSDR_WDU_Pos) /*!< 0x0000E000 */
15142 #define RTC_TSDR_WDU RTC_TSDR_WDU_Msk
15143 #define RTC_TSDR_WDU_0 (0x1U << RTC_TSDR_WDU_Pos) /*!< 0x00002000 */
15144 #define RTC_TSDR_WDU_1 (0x2U << RTC_TSDR_WDU_Pos) /*!< 0x00004000 */
15145 #define RTC_TSDR_WDU_2 (0x4U << RTC_TSDR_WDU_Pos) /*!< 0x00008000 */
15146 #define RTC_TSDR_MT_Pos (12U)
15147 #define RTC_TSDR_MT_Msk (0x1U << RTC_TSDR_MT_Pos) /*!< 0x00001000 */
15148 #define RTC_TSDR_MT RTC_TSDR_MT_Msk
15149 #define RTC_TSDR_MU_Pos (8U)
15150 #define RTC_TSDR_MU_Msk (0xFU << RTC_TSDR_MU_Pos) /*!< 0x00000F00 */
15151 #define RTC_TSDR_MU RTC_TSDR_MU_Msk
15152 #define RTC_TSDR_MU_0 (0x1U << RTC_TSDR_MU_Pos) /*!< 0x00000100 */
15153 #define RTC_TSDR_MU_1 (0x2U << RTC_TSDR_MU_Pos) /*!< 0x00000200 */
15154 #define RTC_TSDR_MU_2 (0x4U << RTC_TSDR_MU_Pos) /*!< 0x00000400 */
15155 #define RTC_TSDR_MU_3 (0x8U << RTC_TSDR_MU_Pos) /*!< 0x00000800 */
15156 #define RTC_TSDR_DT_Pos (4U)
15157 #define RTC_TSDR_DT_Msk (0x3U << RTC_TSDR_DT_Pos) /*!< 0x00000030 */
15158 #define RTC_TSDR_DT RTC_TSDR_DT_Msk
15159 #define RTC_TSDR_DT_0 (0x1U << RTC_TSDR_DT_Pos) /*!< 0x00000010 */
15160 #define RTC_TSDR_DT_1 (0x2U << RTC_TSDR_DT_Pos) /*!< 0x00000020 */
15161 #define RTC_TSDR_DU_Pos (0U)
15162 #define RTC_TSDR_DU_Msk (0xFU << RTC_TSDR_DU_Pos) /*!< 0x0000000F */
15163 #define RTC_TSDR_DU RTC_TSDR_DU_Msk
15164 #define RTC_TSDR_DU_0 (0x1U << RTC_TSDR_DU_Pos) /*!< 0x00000001 */
15165 #define RTC_TSDR_DU_1 (0x2U << RTC_TSDR_DU_Pos) /*!< 0x00000002 */
15166 #define RTC_TSDR_DU_2 (0x4U << RTC_TSDR_DU_Pos) /*!< 0x00000004 */
15167 #define RTC_TSDR_DU_3 (0x8U << RTC_TSDR_DU_Pos) /*!< 0x00000008 */
15168
15169 /******************** Bits definition for RTC_TSSSR register ****************/
15170 #define RTC_TSSSR_SS_Pos (0U)
15171 #define RTC_TSSSR_SS_Msk (0xFFFFU << RTC_TSSSR_SS_Pos) /*!< 0x0000FFFF */
15172 #define RTC_TSSSR_SS RTC_TSSSR_SS_Msk
15173
15174 /******************** Bits definition for RTC_CAL register *****************/
15175 #define RTC_CALR_CALP_Pos (15U)
15176 #define RTC_CALR_CALP_Msk (0x1U << RTC_CALR_CALP_Pos) /*!< 0x00008000 */
15177 #define RTC_CALR_CALP RTC_CALR_CALP_Msk
15178 #define RTC_CALR_CALW8_Pos (14U)
15179 #define RTC_CALR_CALW8_Msk (0x1U << RTC_CALR_CALW8_Pos) /*!< 0x00004000 */
15180 #define RTC_CALR_CALW8 RTC_CALR_CALW8_Msk
15181 #define RTC_CALR_CALW16_Pos (13U)
15182 #define RTC_CALR_CALW16_Msk (0x1U << RTC_CALR_CALW16_Pos) /*!< 0x00002000 */
15183 #define RTC_CALR_CALW16 RTC_CALR_CALW16_Msk
15184 #define RTC_CALR_CALM_Pos (0U)
15185 #define RTC_CALR_CALM_Msk (0x1FFU << RTC_CALR_CALM_Pos) /*!< 0x000001FF */
15186 #define RTC_CALR_CALM RTC_CALR_CALM_Msk
15187 #define RTC_CALR_CALM_0 (0x001U << RTC_CALR_CALM_Pos) /*!< 0x00000001 */
15188 #define RTC_CALR_CALM_1 (0x002U << RTC_CALR_CALM_Pos) /*!< 0x00000002 */
15189 #define RTC_CALR_CALM_2 (0x004U << RTC_CALR_CALM_Pos) /*!< 0x00000004 */
15190 #define RTC_CALR_CALM_3 (0x008U << RTC_CALR_CALM_Pos) /*!< 0x00000008 */
15191 #define RTC_CALR_CALM_4 (0x010U << RTC_CALR_CALM_Pos) /*!< 0x00000010 */
15192 #define RTC_CALR_CALM_5 (0x020U << RTC_CALR_CALM_Pos) /*!< 0x00000020 */
15193 #define RTC_CALR_CALM_6 (0x040U << RTC_CALR_CALM_Pos) /*!< 0x00000040 */
15194 #define RTC_CALR_CALM_7 (0x080U << RTC_CALR_CALM_Pos) /*!< 0x00000080 */
15195 #define RTC_CALR_CALM_8 (0x100U << RTC_CALR_CALM_Pos) /*!< 0x00000100 */
15196
15197 /******************** Bits definition for RTC_TAFCR register ****************/
15198 #define RTC_TAFCR_ALARMOUTTYPE_Pos (18U)
15199 #define RTC_TAFCR_ALARMOUTTYPE_Msk (0x1U << RTC_TAFCR_ALARMOUTTYPE_Pos) /*!< 0x00040000 */
15200 #define RTC_TAFCR_ALARMOUTTYPE RTC_TAFCR_ALARMOUTTYPE_Msk
15201 #define RTC_TAFCR_TSINSEL_Pos (17U)
15202 #define RTC_TAFCR_TSINSEL_Msk (0x1U << RTC_TAFCR_TSINSEL_Pos) /*!< 0x00020000 */
15203 #define RTC_TAFCR_TSINSEL RTC_TAFCR_TSINSEL_Msk
15204 #define RTC_TAFCR_TAMP1INSEL_Pos (16U)
15205 #define RTC_TAFCR_TAMP1INSEL_Msk (0x1U << RTC_TAFCR_TAMP1INSEL_Pos) /*!< 0x00010000 */
15206 #define RTC_TAFCR_TAMP1INSEL RTC_TAFCR_TAMP1INSEL_Msk
15207 #define RTC_TAFCR_TAMPPUDIS_Pos (15U)
15208 #define RTC_TAFCR_TAMPPUDIS_Msk (0x1U << RTC_TAFCR_TAMPPUDIS_Pos) /*!< 0x00008000 */
15209 #define RTC_TAFCR_TAMPPUDIS RTC_TAFCR_TAMPPUDIS_Msk
15210 #define RTC_TAFCR_TAMPPRCH_Pos (13U)
15211 #define RTC_TAFCR_TAMPPRCH_Msk (0x3U << RTC_TAFCR_TAMPPRCH_Pos) /*!< 0x00006000 */
15212 #define RTC_TAFCR_TAMPPRCH RTC_TAFCR_TAMPPRCH_Msk
15213 #define RTC_TAFCR_TAMPPRCH_0 (0x1U << RTC_TAFCR_TAMPPRCH_Pos) /*!< 0x00002000 */
15214 #define RTC_TAFCR_TAMPPRCH_1 (0x2U << RTC_TAFCR_TAMPPRCH_Pos) /*!< 0x00004000 */
15215 #define RTC_TAFCR_TAMPFLT_Pos (11U)
15216 #define RTC_TAFCR_TAMPFLT_Msk (0x3U << RTC_TAFCR_TAMPFLT_Pos) /*!< 0x00001800 */
15217 #define RTC_TAFCR_TAMPFLT RTC_TAFCR_TAMPFLT_Msk
15218 #define RTC_TAFCR_TAMPFLT_0 (0x1U << RTC_TAFCR_TAMPFLT_Pos) /*!< 0x00000800 */
15219 #define RTC_TAFCR_TAMPFLT_1 (0x2U << RTC_TAFCR_TAMPFLT_Pos) /*!< 0x00001000 */
15220 #define RTC_TAFCR_TAMPFREQ_Pos (8U)
15221 #define RTC_TAFCR_TAMPFREQ_Msk (0x7U << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000700 */
15222 #define RTC_TAFCR_TAMPFREQ RTC_TAFCR_TAMPFREQ_Msk
15223 #define RTC_TAFCR_TAMPFREQ_0 (0x1U << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000100 */
15224 #define RTC_TAFCR_TAMPFREQ_1 (0x2U << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000200 */
15225 #define RTC_TAFCR_TAMPFREQ_2 (0x4U << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000400 */
15226 #define RTC_TAFCR_TAMPTS_Pos (7U)
15227 #define RTC_TAFCR_TAMPTS_Msk (0x1U << RTC_TAFCR_TAMPTS_Pos) /*!< 0x00000080 */
15228 #define RTC_TAFCR_TAMPTS RTC_TAFCR_TAMPTS_Msk
15229 #define RTC_TAFCR_TAMP2TRG_Pos (4U)
15230 #define RTC_TAFCR_TAMP2TRG_Msk (0x1U << RTC_TAFCR_TAMP2TRG_Pos) /*!< 0x00000010 */
15231 #define RTC_TAFCR_TAMP2TRG RTC_TAFCR_TAMP2TRG_Msk
15232 #define RTC_TAFCR_TAMP2E_Pos (3U)
15233 #define RTC_TAFCR_TAMP2E_Msk (0x1U << RTC_TAFCR_TAMP2E_Pos) /*!< 0x00000008 */
15234 #define RTC_TAFCR_TAMP2E RTC_TAFCR_TAMP2E_Msk
15235 #define RTC_TAFCR_TAMPIE_Pos (2U)
15236 #define RTC_TAFCR_TAMPIE_Msk (0x1U << RTC_TAFCR_TAMPIE_Pos) /*!< 0x00000004 */
15237 #define RTC_TAFCR_TAMPIE RTC_TAFCR_TAMPIE_Msk
15238 #define RTC_TAFCR_TAMP1TRG_Pos (1U)
15239 #define RTC_TAFCR_TAMP1TRG_Msk (0x1U << RTC_TAFCR_TAMP1TRG_Pos) /*!< 0x00000002 */
15240 #define RTC_TAFCR_TAMP1TRG RTC_TAFCR_TAMP1TRG_Msk
15241 #define RTC_TAFCR_TAMP1E_Pos (0U)
15242 #define RTC_TAFCR_TAMP1E_Msk (0x1U << RTC_TAFCR_TAMP1E_Pos) /*!< 0x00000001 */
15243 #define RTC_TAFCR_TAMP1E RTC_TAFCR_TAMP1E_Msk
15244
15245 /* Legacy defines */
15246 #define RTC_TAFCR_TAMPINSEL RTC_TAFCR_TAMP1INSEL
15247
15248 /******************** Bits definition for RTC_ALRMASSR register *************/
15249 #define RTC_ALRMASSR_MASKSS_Pos (24U)
15250 #define RTC_ALRMASSR_MASKSS_Msk (0xFU << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x0F000000 */
15251 #define RTC_ALRMASSR_MASKSS RTC_ALRMASSR_MASKSS_Msk
15252 #define RTC_ALRMASSR_MASKSS_0 (0x1U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x01000000 */
15253 #define RTC_ALRMASSR_MASKSS_1 (0x2U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x02000000 */
15254 #define RTC_ALRMASSR_MASKSS_2 (0x4U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x04000000 */
15255 #define RTC_ALRMASSR_MASKSS_3 (0x8U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x08000000 */
15256 #define RTC_ALRMASSR_SS_Pos (0U)
15257 #define RTC_ALRMASSR_SS_Msk (0x7FFFU << RTC_ALRMASSR_SS_Pos) /*!< 0x00007FFF */
15258 #define RTC_ALRMASSR_SS RTC_ALRMASSR_SS_Msk
15259
15260 /******************** Bits definition for RTC_ALRMBSSR register *************/
15261 #define RTC_ALRMBSSR_MASKSS_Pos (24U)
15262 #define RTC_ALRMBSSR_MASKSS_Msk (0xFU << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x0F000000 */
15263 #define RTC_ALRMBSSR_MASKSS RTC_ALRMBSSR_MASKSS_Msk
15264 #define RTC_ALRMBSSR_MASKSS_0 (0x1U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x01000000 */
15265 #define RTC_ALRMBSSR_MASKSS_1 (0x2U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x02000000 */
15266 #define RTC_ALRMBSSR_MASKSS_2 (0x4U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x04000000 */
15267 #define RTC_ALRMBSSR_MASKSS_3 (0x8U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x08000000 */
15268 #define RTC_ALRMBSSR_SS_Pos (0U)
15269 #define RTC_ALRMBSSR_SS_Msk (0x7FFFU << RTC_ALRMBSSR_SS_Pos) /*!< 0x00007FFF */
15270 #define RTC_ALRMBSSR_SS RTC_ALRMBSSR_SS_Msk
15271
15272 /******************** Bits definition for RTC_BKP0R register ****************/
15273 #define RTC_BKP0R_Pos (0U)
15274 #define RTC_BKP0R_Msk (0xFFFFFFFFU << RTC_BKP0R_Pos) /*!< 0xFFFFFFFF */
15275 #define RTC_BKP0R RTC_BKP0R_Msk
15276
15277 /******************** Bits definition for RTC_BKP1R register ****************/
15278 #define RTC_BKP1R_Pos (0U)
15279 #define RTC_BKP1R_Msk (0xFFFFFFFFU << RTC_BKP1R_Pos) /*!< 0xFFFFFFFF */
15280 #define RTC_BKP1R RTC_BKP1R_Msk
15281
15282 /******************** Bits definition for RTC_BKP2R register ****************/
15283 #define RTC_BKP2R_Pos (0U)
15284 #define RTC_BKP2R_Msk (0xFFFFFFFFU << RTC_BKP2R_Pos) /*!< 0xFFFFFFFF */
15285 #define RTC_BKP2R RTC_BKP2R_Msk
15286
15287 /******************** Bits definition for RTC_BKP3R register ****************/
15288 #define RTC_BKP3R_Pos (0U)
15289 #define RTC_BKP3R_Msk (0xFFFFFFFFU << RTC_BKP3R_Pos) /*!< 0xFFFFFFFF */
15290 #define RTC_BKP3R RTC_BKP3R_Msk
15291
15292 /******************** Bits definition for RTC_BKP4R register ****************/
15293 #define RTC_BKP4R_Pos (0U)
15294 #define RTC_BKP4R_Msk (0xFFFFFFFFU << RTC_BKP4R_Pos) /*!< 0xFFFFFFFF */
15295 #define RTC_BKP4R RTC_BKP4R_Msk
15296
15297 /******************** Bits definition for RTC_BKP5R register ****************/
15298 #define RTC_BKP5R_Pos (0U)
15299 #define RTC_BKP5R_Msk (0xFFFFFFFFU << RTC_BKP5R_Pos) /*!< 0xFFFFFFFF */
15300 #define RTC_BKP5R RTC_BKP5R_Msk
15301
15302 /******************** Bits definition for RTC_BKP6R register ****************/
15303 #define RTC_BKP6R_Pos (0U)
15304 #define RTC_BKP6R_Msk (0xFFFFFFFFU << RTC_BKP6R_Pos) /*!< 0xFFFFFFFF */
15305 #define RTC_BKP6R RTC_BKP6R_Msk
15306
15307 /******************** Bits definition for RTC_BKP7R register ****************/
15308 #define RTC_BKP7R_Pos (0U)
15309 #define RTC_BKP7R_Msk (0xFFFFFFFFU << RTC_BKP7R_Pos) /*!< 0xFFFFFFFF */
15310 #define RTC_BKP7R RTC_BKP7R_Msk
15311
15312 /******************** Bits definition for RTC_BKP8R register ****************/
15313 #define RTC_BKP8R_Pos (0U)
15314 #define RTC_BKP8R_Msk (0xFFFFFFFFU << RTC_BKP8R_Pos) /*!< 0xFFFFFFFF */
15315 #define RTC_BKP8R RTC_BKP8R_Msk
15316
15317 /******************** Bits definition for RTC_BKP9R register ****************/
15318 #define RTC_BKP9R_Pos (0U)
15319 #define RTC_BKP9R_Msk (0xFFFFFFFFU << RTC_BKP9R_Pos) /*!< 0xFFFFFFFF */
15320 #define RTC_BKP9R RTC_BKP9R_Msk
15321
15322 /******************** Bits definition for RTC_BKP10R register ***************/
15323 #define RTC_BKP10R_Pos (0U)
15324 #define RTC_BKP10R_Msk (0xFFFFFFFFU << RTC_BKP10R_Pos) /*!< 0xFFFFFFFF */
15325 #define RTC_BKP10R RTC_BKP10R_Msk
15326
15327 /******************** Bits definition for RTC_BKP11R register ***************/
15328 #define RTC_BKP11R_Pos (0U)
15329 #define RTC_BKP11R_Msk (0xFFFFFFFFU << RTC_BKP11R_Pos) /*!< 0xFFFFFFFF */
15330 #define RTC_BKP11R RTC_BKP11R_Msk
15331
15332 /******************** Bits definition for RTC_BKP12R register ***************/
15333 #define RTC_BKP12R_Pos (0U)
15334 #define RTC_BKP12R_Msk (0xFFFFFFFFU << RTC_BKP12R_Pos) /*!< 0xFFFFFFFF */
15335 #define RTC_BKP12R RTC_BKP12R_Msk
15336
15337 /******************** Bits definition for RTC_BKP13R register ***************/
15338 #define RTC_BKP13R_Pos (0U)
15339 #define RTC_BKP13R_Msk (0xFFFFFFFFU << RTC_BKP13R_Pos) /*!< 0xFFFFFFFF */
15340 #define RTC_BKP13R RTC_BKP13R_Msk
15341
15342 /******************** Bits definition for RTC_BKP14R register ***************/
15343 #define RTC_BKP14R_Pos (0U)
15344 #define RTC_BKP14R_Msk (0xFFFFFFFFU << RTC_BKP14R_Pos) /*!< 0xFFFFFFFF */
15345 #define RTC_BKP14R RTC_BKP14R_Msk
15346
15347 /******************** Bits definition for RTC_BKP15R register ***************/
15348 #define RTC_BKP15R_Pos (0U)
15349 #define RTC_BKP15R_Msk (0xFFFFFFFFU << RTC_BKP15R_Pos) /*!< 0xFFFFFFFF */
15350 #define RTC_BKP15R RTC_BKP15R_Msk
15351
15352 /******************** Bits definition for RTC_BKP16R register ***************/
15353 #define RTC_BKP16R_Pos (0U)
15354 #define RTC_BKP16R_Msk (0xFFFFFFFFU << RTC_BKP16R_Pos) /*!< 0xFFFFFFFF */
15355 #define RTC_BKP16R RTC_BKP16R_Msk
15356
15357 /******************** Bits definition for RTC_BKP17R register ***************/
15358 #define RTC_BKP17R_Pos (0U)
15359 #define RTC_BKP17R_Msk (0xFFFFFFFFU << RTC_BKP17R_Pos) /*!< 0xFFFFFFFF */
15360 #define RTC_BKP17R RTC_BKP17R_Msk
15361
15362 /******************** Bits definition for RTC_BKP18R register ***************/
15363 #define RTC_BKP18R_Pos (0U)
15364 #define RTC_BKP18R_Msk (0xFFFFFFFFU << RTC_BKP18R_Pos) /*!< 0xFFFFFFFF */
15365 #define RTC_BKP18R RTC_BKP18R_Msk
15366
15367 /******************** Bits definition for RTC_BKP19R register ***************/
15368 #define RTC_BKP19R_Pos (0U)
15369 #define RTC_BKP19R_Msk (0xFFFFFFFFU << RTC_BKP19R_Pos) /*!< 0xFFFFFFFF */
15370 #define RTC_BKP19R RTC_BKP19R_Msk
15371
15372 /******************** Number of backup registers ******************************/
15373 #define RTC_BKP_NUMBER 0x000000014U
15374
15375 /******************************************************************************/
15376 /* */
15377 /* Serial Audio Interface */
15378 /* */
15379 /******************************************************************************/
15380 /******************** Bit definition for SAI_GCR register *******************/
15381 #define SAI_GCR_SYNCIN_Pos (0U)
15382 #define SAI_GCR_SYNCIN_Msk (0x3U << SAI_GCR_SYNCIN_Pos) /*!< 0x00000003 */
15383 #define SAI_GCR_SYNCIN SAI_GCR_SYNCIN_Msk /*!<SYNCIN[1:0] bits (Synchronization Inputs) */
15384 #define SAI_GCR_SYNCIN_0 (0x1U << SAI_GCR_SYNCIN_Pos) /*!< 0x00000001 */
15385 #define SAI_GCR_SYNCIN_1 (0x2U << SAI_GCR_SYNCIN_Pos) /*!< 0x00000002 */
15386
15387 #define SAI_GCR_SYNCOUT_Pos (4U)
15388 #define SAI_GCR_SYNCOUT_Msk (0x3U << SAI_GCR_SYNCOUT_Pos) /*!< 0x00000030 */
15389 #define SAI_GCR_SYNCOUT SAI_GCR_SYNCOUT_Msk /*!<SYNCOUT[1:0] bits (Synchronization Outputs) */
15390 #define SAI_GCR_SYNCOUT_0 (0x1U << SAI_GCR_SYNCOUT_Pos) /*!< 0x00000010 */
15391 #define SAI_GCR_SYNCOUT_1 (0x2U << SAI_GCR_SYNCOUT_Pos) /*!< 0x00000020 */
15392
15393 /******************* Bit definition for SAI_xCR1 register *******************/
15394 #define SAI_xCR1_MODE_Pos (0U)
15395 #define SAI_xCR1_MODE_Msk (0x3U << SAI_xCR1_MODE_Pos) /*!< 0x00000003 */
15396 #define SAI_xCR1_MODE SAI_xCR1_MODE_Msk /*!<MODE[1:0] bits (Audio Block Mode) */
15397 #define SAI_xCR1_MODE_0 (0x1U << SAI_xCR1_MODE_Pos) /*!< 0x00000001 */
15398 #define SAI_xCR1_MODE_1 (0x2U << SAI_xCR1_MODE_Pos) /*!< 0x00000002 */
15399
15400 #define SAI_xCR1_PRTCFG_Pos (2U)
15401 #define SAI_xCR1_PRTCFG_Msk (0x3U << SAI_xCR1_PRTCFG_Pos) /*!< 0x0000000C */
15402 #define SAI_xCR1_PRTCFG SAI_xCR1_PRTCFG_Msk /*!<PRTCFG[1:0] bits (Protocol Configuration) */
15403 #define SAI_xCR1_PRTCFG_0 (0x1U << SAI_xCR1_PRTCFG_Pos) /*!< 0x00000004 */
15404 #define SAI_xCR1_PRTCFG_1 (0x2U << SAI_xCR1_PRTCFG_Pos) /*!< 0x00000008 */
15405
15406 #define SAI_xCR1_DS_Pos (5U)
15407 #define SAI_xCR1_DS_Msk (0x7U << SAI_xCR1_DS_Pos) /*!< 0x000000E0 */
15408 #define SAI_xCR1_DS SAI_xCR1_DS_Msk /*!<DS[1:0] bits (Data Size) */
15409 #define SAI_xCR1_DS_0 (0x1U << SAI_xCR1_DS_Pos) /*!< 0x00000020 */
15410 #define SAI_xCR1_DS_1 (0x2U << SAI_xCR1_DS_Pos) /*!< 0x00000040 */
15411 #define SAI_xCR1_DS_2 (0x4U << SAI_xCR1_DS_Pos) /*!< 0x00000080 */
15412
15413 #define SAI_xCR1_LSBFIRST_Pos (8U)
15414 #define SAI_xCR1_LSBFIRST_Msk (0x1U << SAI_xCR1_LSBFIRST_Pos) /*!< 0x00000100 */
15415 #define SAI_xCR1_LSBFIRST SAI_xCR1_LSBFIRST_Msk /*!<LSB First Configuration */
15416 #define SAI_xCR1_CKSTR_Pos (9U)
15417 #define SAI_xCR1_CKSTR_Msk (0x1U << SAI_xCR1_CKSTR_Pos) /*!< 0x00000200 */
15418 #define SAI_xCR1_CKSTR SAI_xCR1_CKSTR_Msk /*!<ClocK STRobing edge */
15419
15420 #define SAI_xCR1_SYNCEN_Pos (10U)
15421 #define SAI_xCR1_SYNCEN_Msk (0x3U << SAI_xCR1_SYNCEN_Pos) /*!< 0x00000C00 */
15422 #define SAI_xCR1_SYNCEN SAI_xCR1_SYNCEN_Msk /*!<SYNCEN[1:0](SYNChronization ENable) */
15423 #define SAI_xCR1_SYNCEN_0 (0x1U << SAI_xCR1_SYNCEN_Pos) /*!< 0x00000400 */
15424 #define SAI_xCR1_SYNCEN_1 (0x2U << SAI_xCR1_SYNCEN_Pos) /*!< 0x00000800 */
15425
15426 #define SAI_xCR1_MONO_Pos (12U)
15427 #define SAI_xCR1_MONO_Msk (0x1U << SAI_xCR1_MONO_Pos) /*!< 0x00001000 */
15428 #define SAI_xCR1_MONO SAI_xCR1_MONO_Msk /*!<Mono mode */
15429 #define SAI_xCR1_OUTDRIV_Pos (13U)
15430 #define SAI_xCR1_OUTDRIV_Msk (0x1U << SAI_xCR1_OUTDRIV_Pos) /*!< 0x00002000 */
15431 #define SAI_xCR1_OUTDRIV SAI_xCR1_OUTDRIV_Msk /*!<Output Drive */
15432 #define SAI_xCR1_SAIEN_Pos (16U)
15433 #define SAI_xCR1_SAIEN_Msk (0x1U << SAI_xCR1_SAIEN_Pos) /*!< 0x00010000 */
15434 #define SAI_xCR1_SAIEN SAI_xCR1_SAIEN_Msk /*!<Audio Block enable */
15435 #define SAI_xCR1_DMAEN_Pos (17U)
15436 #define SAI_xCR1_DMAEN_Msk (0x1U << SAI_xCR1_DMAEN_Pos) /*!< 0x00020000 */
15437 #define SAI_xCR1_DMAEN SAI_xCR1_DMAEN_Msk /*!<DMA enable */
15438 #define SAI_xCR1_NODIV_Pos (19U)
15439 #define SAI_xCR1_NODIV_Msk (0x1U << SAI_xCR1_NODIV_Pos) /*!< 0x00080000 */
15440 #define SAI_xCR1_NODIV SAI_xCR1_NODIV_Msk /*!<No Divider Configuration */
15441
15442 #define SAI_xCR1_MCKDIV_Pos (20U)
15443 #define SAI_xCR1_MCKDIV_Msk (0xFU << SAI_xCR1_MCKDIV_Pos) /*!< 0x00F00000 */
15444 #define SAI_xCR1_MCKDIV SAI_xCR1_MCKDIV_Msk /*!<MCKDIV[3:0] (Master ClocK Divider) */
15445 #define SAI_xCR1_MCKDIV_0 (0x1U << SAI_xCR1_MCKDIV_Pos) /*!< 0x00100000 */
15446 #define SAI_xCR1_MCKDIV_1 (0x2U << SAI_xCR1_MCKDIV_Pos) /*!< 0x00200000 */
15447 #define SAI_xCR1_MCKDIV_2 (0x4U << SAI_xCR1_MCKDIV_Pos) /*!< 0x00400000 */
15448 #define SAI_xCR1_MCKDIV_3 (0x8U << SAI_xCR1_MCKDIV_Pos) /*!< 0x00800000 */
15449
15450 /******************* Bit definition for SAI_xCR2 register *******************/
15451 #define SAI_xCR2_FTH_Pos (0U)
15452 #define SAI_xCR2_FTH_Msk (0x7U << SAI_xCR2_FTH_Pos) /*!< 0x00000007 */
15453 #define SAI_xCR2_FTH SAI_xCR2_FTH_Msk /*!<FTH[2:0](Fifo THreshold) */
15454 #define SAI_xCR2_FTH_0 (0x1U << SAI_xCR2_FTH_Pos) /*!< 0x00000001 */
15455 #define SAI_xCR2_FTH_1 (0x2U << SAI_xCR2_FTH_Pos) /*!< 0x00000002 */
15456 #define SAI_xCR2_FTH_2 (0x4U << SAI_xCR2_FTH_Pos) /*!< 0x00000004 */
15457
15458 #define SAI_xCR2_FFLUSH_Pos (3U)
15459 #define SAI_xCR2_FFLUSH_Msk (0x1U << SAI_xCR2_FFLUSH_Pos) /*!< 0x00000008 */
15460 #define SAI_xCR2_FFLUSH SAI_xCR2_FFLUSH_Msk /*!<Fifo FLUSH */
15461 #define SAI_xCR2_TRIS_Pos (4U)
15462 #define SAI_xCR2_TRIS_Msk (0x1U << SAI_xCR2_TRIS_Pos) /*!< 0x00000010 */
15463 #define SAI_xCR2_TRIS SAI_xCR2_TRIS_Msk /*!<TRIState Management on data line */
15464 #define SAI_xCR2_MUTE_Pos (5U)
15465 #define SAI_xCR2_MUTE_Msk (0x1U << SAI_xCR2_MUTE_Pos) /*!< 0x00000020 */
15466 #define SAI_xCR2_MUTE SAI_xCR2_MUTE_Msk /*!<Mute mode */
15467 #define SAI_xCR2_MUTEVAL_Pos (6U)
15468 #define SAI_xCR2_MUTEVAL_Msk (0x1U << SAI_xCR2_MUTEVAL_Pos) /*!< 0x00000040 */
15469 #define SAI_xCR2_MUTEVAL SAI_xCR2_MUTEVAL_Msk /*!<Muate value */
15470
15471 #define SAI_xCR2_MUTECNT_Pos (7U)
15472 #define SAI_xCR2_MUTECNT_Msk (0x3FU << SAI_xCR2_MUTECNT_Pos) /*!< 0x00001F80 */
15473 #define SAI_xCR2_MUTECNT SAI_xCR2_MUTECNT_Msk /*!<MUTECNT[5:0] (MUTE counter) */
15474 #define SAI_xCR2_MUTECNT_0 (0x01U << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000080 */
15475 #define SAI_xCR2_MUTECNT_1 (0x02U << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000100 */
15476 #define SAI_xCR2_MUTECNT_2 (0x04U << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000200 */
15477 #define SAI_xCR2_MUTECNT_3 (0x08U << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000400 */
15478 #define SAI_xCR2_MUTECNT_4 (0x10U << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000800 */
15479 #define SAI_xCR2_MUTECNT_5 (0x20U << SAI_xCR2_MUTECNT_Pos) /*!< 0x00001000 */
15480
15481 #define SAI_xCR2_CPL_Pos (13U)
15482 #define SAI_xCR2_CPL_Msk (0x1U << SAI_xCR2_CPL_Pos) /*!< 0x00002000 */
15483 #define SAI_xCR2_CPL SAI_xCR2_CPL_Msk /*!< Complement Bit */
15484
15485 #define SAI_xCR2_COMP_Pos (14U)
15486 #define SAI_xCR2_COMP_Msk (0x3U << SAI_xCR2_COMP_Pos) /*!< 0x0000C000 */
15487 #define SAI_xCR2_COMP SAI_xCR2_COMP_Msk /*!<COMP[1:0] (Companding mode) */
15488 #define SAI_xCR2_COMP_0 (0x1U << SAI_xCR2_COMP_Pos) /*!< 0x00004000 */
15489 #define SAI_xCR2_COMP_1 (0x2U << SAI_xCR2_COMP_Pos) /*!< 0x00008000 */
15490
15491 /****************** Bit definition for SAI_xFRCR register *******************/
15492 #define SAI_xFRCR_FRL_Pos (0U)
15493 #define SAI_xFRCR_FRL_Msk (0xFFU << SAI_xFRCR_FRL_Pos) /*!< 0x000000FF */
15494 #define SAI_xFRCR_FRL SAI_xFRCR_FRL_Msk /*!<FRL[1:0](Frame length) */
15495 #define SAI_xFRCR_FRL_0 (0x01U << SAI_xFRCR_FRL_Pos) /*!< 0x00000001 */
15496 #define SAI_xFRCR_FRL_1 (0x02U << SAI_xFRCR_FRL_Pos) /*!< 0x00000002 */
15497 #define SAI_xFRCR_FRL_2 (0x04U << SAI_xFRCR_FRL_Pos) /*!< 0x00000004 */
15498 #define SAI_xFRCR_FRL_3 (0x08U << SAI_xFRCR_FRL_Pos) /*!< 0x00000008 */
15499 #define SAI_xFRCR_FRL_4 (0x10U << SAI_xFRCR_FRL_Pos) /*!< 0x00000010 */
15500 #define SAI_xFRCR_FRL_5 (0x20U << SAI_xFRCR_FRL_Pos) /*!< 0x00000020 */
15501 #define SAI_xFRCR_FRL_6 (0x40U << SAI_xFRCR_FRL_Pos) /*!< 0x00000040 */
15502 #define SAI_xFRCR_FRL_7 (0x80U << SAI_xFRCR_FRL_Pos) /*!< 0x00000080 */
15503
15504 #define SAI_xFRCR_FSALL_Pos (8U)
15505 #define SAI_xFRCR_FSALL_Msk (0x7FU << SAI_xFRCR_FSALL_Pos) /*!< 0x00007F00 */
15506 #define SAI_xFRCR_FSALL SAI_xFRCR_FSALL_Msk /*!<FRL[1:0] (Frame synchronization active level length) */
15507 #define SAI_xFRCR_FSALL_0 (0x01U << SAI_xFRCR_FSALL_Pos) /*!< 0x00000100 */
15508 #define SAI_xFRCR_FSALL_1 (0x02U << SAI_xFRCR_FSALL_Pos) /*!< 0x00000200 */
15509 #define SAI_xFRCR_FSALL_2 (0x04U << SAI_xFRCR_FSALL_Pos) /*!< 0x00000400 */
15510 #define SAI_xFRCR_FSALL_3 (0x08U << SAI_xFRCR_FSALL_Pos) /*!< 0x00000800 */
15511 #define SAI_xFRCR_FSALL_4 (0x10U << SAI_xFRCR_FSALL_Pos) /*!< 0x00001000 */
15512 #define SAI_xFRCR_FSALL_5 (0x20U << SAI_xFRCR_FSALL_Pos) /*!< 0x00002000 */
15513 #define SAI_xFRCR_FSALL_6 (0x40U << SAI_xFRCR_FSALL_Pos) /*!< 0x00004000 */
15514
15515 #define SAI_xFRCR_FSDEF_Pos (16U)
15516 #define SAI_xFRCR_FSDEF_Msk (0x1U << SAI_xFRCR_FSDEF_Pos) /*!< 0x00010000 */
15517 #define SAI_xFRCR_FSDEF SAI_xFRCR_FSDEF_Msk /*!< Frame Synchronization Definition */
15518 #define SAI_xFRCR_FSPOL_Pos (17U)
15519 #define SAI_xFRCR_FSPOL_Msk (0x1U << SAI_xFRCR_FSPOL_Pos) /*!< 0x00020000 */
15520 #define SAI_xFRCR_FSPOL SAI_xFRCR_FSPOL_Msk /*!<Frame Synchronization POLarity */
15521 #define SAI_xFRCR_FSOFF_Pos (18U)
15522 #define SAI_xFRCR_FSOFF_Msk (0x1U << SAI_xFRCR_FSOFF_Pos) /*!< 0x00040000 */
15523 #define SAI_xFRCR_FSOFF SAI_xFRCR_FSOFF_Msk /*!<Frame Synchronization OFFset */
15524 /* Legacy defines */
15525 #define SAI_xFRCR_FSPO SAI_xFRCR_FSPOL
15526
15527 /****************** Bit definition for SAI_xSLOTR register *******************/
15528 #define SAI_xSLOTR_FBOFF_Pos (0U)
15529 #define SAI_xSLOTR_FBOFF_Msk (0x1FU << SAI_xSLOTR_FBOFF_Pos) /*!< 0x0000001F */
15530 #define SAI_xSLOTR_FBOFF SAI_xSLOTR_FBOFF_Msk /*!<FRL[4:0](First Bit Offset) */
15531 #define SAI_xSLOTR_FBOFF_0 (0x01U << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000001 */
15532 #define SAI_xSLOTR_FBOFF_1 (0x02U << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000002 */
15533 #define SAI_xSLOTR_FBOFF_2 (0x04U << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000004 */
15534 #define SAI_xSLOTR_FBOFF_3 (0x08U << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000008 */
15535 #define SAI_xSLOTR_FBOFF_4 (0x10U << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000010 */
15536
15537 #define SAI_xSLOTR_SLOTSZ_Pos (6U)
15538 #define SAI_xSLOTR_SLOTSZ_Msk (0x3U << SAI_xSLOTR_SLOTSZ_Pos) /*!< 0x000000C0 */
15539 #define SAI_xSLOTR_SLOTSZ SAI_xSLOTR_SLOTSZ_Msk /*!<SLOTSZ[1:0] (Slot size) */
15540 #define SAI_xSLOTR_SLOTSZ_0 (0x1U << SAI_xSLOTR_SLOTSZ_Pos) /*!< 0x00000040 */
15541 #define SAI_xSLOTR_SLOTSZ_1 (0x2U << SAI_xSLOTR_SLOTSZ_Pos) /*!< 0x00000080 */
15542
15543 #define SAI_xSLOTR_NBSLOT_Pos (8U)
15544 #define SAI_xSLOTR_NBSLOT_Msk (0xFU << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000F00 */
15545 #define SAI_xSLOTR_NBSLOT SAI_xSLOTR_NBSLOT_Msk /*!<NBSLOT[3:0] (Number of Slot in audio Frame) */
15546 #define SAI_xSLOTR_NBSLOT_0 (0x1U << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000100 */
15547 #define SAI_xSLOTR_NBSLOT_1 (0x2U << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000200 */
15548 #define SAI_xSLOTR_NBSLOT_2 (0x4U << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000400 */
15549 #define SAI_xSLOTR_NBSLOT_3 (0x8U << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000800 */
15550
15551 #define SAI_xSLOTR_SLOTEN_Pos (16U)
15552 #define SAI_xSLOTR_SLOTEN_Msk (0xFFFFU << SAI_xSLOTR_SLOTEN_Pos) /*!< 0xFFFF0000 */
15553 #define SAI_xSLOTR_SLOTEN SAI_xSLOTR_SLOTEN_Msk /*!<SLOTEN[15:0] (Slot Enable) */
15554
15555 /******************* Bit definition for SAI_xIMR register *******************/
15556 #define SAI_xIMR_OVRUDRIE_Pos (0U)
15557 #define SAI_xIMR_OVRUDRIE_Msk (0x1U << SAI_xIMR_OVRUDRIE_Pos) /*!< 0x00000001 */
15558 #define SAI_xIMR_OVRUDRIE SAI_xIMR_OVRUDRIE_Msk /*!<Overrun underrun interrupt enable */
15559 #define SAI_xIMR_MUTEDETIE_Pos (1U)
15560 #define SAI_xIMR_MUTEDETIE_Msk (0x1U << SAI_xIMR_MUTEDETIE_Pos) /*!< 0x00000002 */
15561 #define SAI_xIMR_MUTEDETIE SAI_xIMR_MUTEDETIE_Msk /*!<Mute detection interrupt enable */
15562 #define SAI_xIMR_WCKCFGIE_Pos (2U)
15563 #define SAI_xIMR_WCKCFGIE_Msk (0x1U << SAI_xIMR_WCKCFGIE_Pos) /*!< 0x00000004 */
15564 #define SAI_xIMR_WCKCFGIE SAI_xIMR_WCKCFGIE_Msk /*!<Wrong Clock Configuration interrupt enable */
15565 #define SAI_xIMR_FREQIE_Pos (3U)
15566 #define SAI_xIMR_FREQIE_Msk (0x1U << SAI_xIMR_FREQIE_Pos) /*!< 0x00000008 */
15567 #define SAI_xIMR_FREQIE SAI_xIMR_FREQIE_Msk /*!<FIFO request interrupt enable */
15568 #define SAI_xIMR_CNRDYIE_Pos (4U)
15569 #define SAI_xIMR_CNRDYIE_Msk (0x1U << SAI_xIMR_CNRDYIE_Pos) /*!< 0x00000010 */
15570 #define SAI_xIMR_CNRDYIE SAI_xIMR_CNRDYIE_Msk /*!<Codec not ready interrupt enable */
15571 #define SAI_xIMR_AFSDETIE_Pos (5U)
15572 #define SAI_xIMR_AFSDETIE_Msk (0x1U << SAI_xIMR_AFSDETIE_Pos) /*!< 0x00000020 */
15573 #define SAI_xIMR_AFSDETIE SAI_xIMR_AFSDETIE_Msk /*!<Anticipated frame synchronization detection interrupt enable */
15574 #define SAI_xIMR_LFSDETIE_Pos (6U)
15575 #define SAI_xIMR_LFSDETIE_Msk (0x1U << SAI_xIMR_LFSDETIE_Pos) /*!< 0x00000040 */
15576 #define SAI_xIMR_LFSDETIE SAI_xIMR_LFSDETIE_Msk /*!<Late frame synchronization detection interrupt enable */
15577
15578 /******************** Bit definition for SAI_xSR register *******************/
15579 #define SAI_xSR_OVRUDR_Pos (0U)
15580 #define SAI_xSR_OVRUDR_Msk (0x1U << SAI_xSR_OVRUDR_Pos) /*!< 0x00000001 */
15581 #define SAI_xSR_OVRUDR SAI_xSR_OVRUDR_Msk /*!<Overrun underrun */
15582 #define SAI_xSR_MUTEDET_Pos (1U)
15583 #define SAI_xSR_MUTEDET_Msk (0x1U << SAI_xSR_MUTEDET_Pos) /*!< 0x00000002 */
15584 #define SAI_xSR_MUTEDET SAI_xSR_MUTEDET_Msk /*!<Mute detection */
15585 #define SAI_xSR_WCKCFG_Pos (2U)
15586 #define SAI_xSR_WCKCFG_Msk (0x1U << SAI_xSR_WCKCFG_Pos) /*!< 0x00000004 */
15587 #define SAI_xSR_WCKCFG SAI_xSR_WCKCFG_Msk /*!<Wrong Clock Configuration */
15588 #define SAI_xSR_FREQ_Pos (3U)
15589 #define SAI_xSR_FREQ_Msk (0x1U << SAI_xSR_FREQ_Pos) /*!< 0x00000008 */
15590 #define SAI_xSR_FREQ SAI_xSR_FREQ_Msk /*!<FIFO request */
15591 #define SAI_xSR_CNRDY_Pos (4U)
15592 #define SAI_xSR_CNRDY_Msk (0x1U << SAI_xSR_CNRDY_Pos) /*!< 0x00000010 */
15593 #define SAI_xSR_CNRDY SAI_xSR_CNRDY_Msk /*!<Codec not ready */
15594 #define SAI_xSR_AFSDET_Pos (5U)
15595 #define SAI_xSR_AFSDET_Msk (0x1U << SAI_xSR_AFSDET_Pos) /*!< 0x00000020 */
15596 #define SAI_xSR_AFSDET SAI_xSR_AFSDET_Msk /*!<Anticipated frame synchronization detection */
15597 #define SAI_xSR_LFSDET_Pos (6U)
15598 #define SAI_xSR_LFSDET_Msk (0x1U << SAI_xSR_LFSDET_Pos) /*!< 0x00000040 */
15599 #define SAI_xSR_LFSDET SAI_xSR_LFSDET_Msk /*!<Late frame synchronization detection */
15600
15601 #define SAI_xSR_FLVL_Pos (16U)
15602 #define SAI_xSR_FLVL_Msk (0x7U << SAI_xSR_FLVL_Pos) /*!< 0x00070000 */
15603 #define SAI_xSR_FLVL SAI_xSR_FLVL_Msk /*!<FLVL[2:0] (FIFO Level Threshold) */
15604 #define SAI_xSR_FLVL_0 (0x1U << SAI_xSR_FLVL_Pos) /*!< 0x00010000 */
15605 #define SAI_xSR_FLVL_1 (0x2U << SAI_xSR_FLVL_Pos) /*!< 0x00020000 */
15606 #define SAI_xSR_FLVL_2 (0x4U << SAI_xSR_FLVL_Pos) /*!< 0x00040000 */
15607
15608 /****************** Bit definition for SAI_xCLRFR register ******************/
15609 #define SAI_xCLRFR_COVRUDR_Pos (0U)
15610 #define SAI_xCLRFR_COVRUDR_Msk (0x1U << SAI_xCLRFR_COVRUDR_Pos) /*!< 0x00000001 */
15611 #define SAI_xCLRFR_COVRUDR SAI_xCLRFR_COVRUDR_Msk /*!<Clear Overrun underrun */
15612 #define SAI_xCLRFR_CMUTEDET_Pos (1U)
15613 #define SAI_xCLRFR_CMUTEDET_Msk (0x1U << SAI_xCLRFR_CMUTEDET_Pos) /*!< 0x00000002 */
15614 #define SAI_xCLRFR_CMUTEDET SAI_xCLRFR_CMUTEDET_Msk /*!<Clear Mute detection */
15615 #define SAI_xCLRFR_CWCKCFG_Pos (2U)
15616 #define SAI_xCLRFR_CWCKCFG_Msk (0x1U << SAI_xCLRFR_CWCKCFG_Pos) /*!< 0x00000004 */
15617 #define SAI_xCLRFR_CWCKCFG SAI_xCLRFR_CWCKCFG_Msk /*!<Clear Wrong Clock Configuration */
15618 #define SAI_xCLRFR_CFREQ_Pos (3U)
15619 #define SAI_xCLRFR_CFREQ_Msk (0x1U << SAI_xCLRFR_CFREQ_Pos) /*!< 0x00000008 */
15620 #define SAI_xCLRFR_CFREQ SAI_xCLRFR_CFREQ_Msk /*!<Clear FIFO request */
15621 #define SAI_xCLRFR_CCNRDY_Pos (4U)
15622 #define SAI_xCLRFR_CCNRDY_Msk (0x1U << SAI_xCLRFR_CCNRDY_Pos) /*!< 0x00000010 */
15623 #define SAI_xCLRFR_CCNRDY SAI_xCLRFR_CCNRDY_Msk /*!<Clear Codec not ready */
15624 #define SAI_xCLRFR_CAFSDET_Pos (5U)
15625 #define SAI_xCLRFR_CAFSDET_Msk (0x1U << SAI_xCLRFR_CAFSDET_Pos) /*!< 0x00000020 */
15626 #define SAI_xCLRFR_CAFSDET SAI_xCLRFR_CAFSDET_Msk /*!<Clear Anticipated frame synchronization detection */
15627 #define SAI_xCLRFR_CLFSDET_Pos (6U)
15628 #define SAI_xCLRFR_CLFSDET_Msk (0x1U << SAI_xCLRFR_CLFSDET_Pos) /*!< 0x00000040 */
15629 #define SAI_xCLRFR_CLFSDET SAI_xCLRFR_CLFSDET_Msk /*!<Clear Late frame synchronization detection */
15630
15631 /****************** Bit definition for SAI_xDR register ******************/
15632 #define SAI_xDR_DATA_Pos (0U)
15633 #define SAI_xDR_DATA_Msk (0xFFFFFFFFU << SAI_xDR_DATA_Pos) /*!< 0xFFFFFFFF */
15634 #define SAI_xDR_DATA SAI_xDR_DATA_Msk
15635
15636
15637 /******************************************************************************/
15638 /* */
15639 /* SD host Interface */
15640 /* */
15641 /******************************************************************************/
15642 /****************** Bit definition for SDIO_POWER register ******************/
15643 #define SDIO_POWER_PWRCTRL_Pos (0U)
15644 #define SDIO_POWER_PWRCTRL_Msk (0x3U << SDIO_POWER_PWRCTRL_Pos) /*!< 0x00000003 */
15645 #define SDIO_POWER_PWRCTRL SDIO_POWER_PWRCTRL_Msk /*!<PWRCTRL[1:0] bits (Power supply control bits) */
15646 #define SDIO_POWER_PWRCTRL_0 (0x1U << SDIO_POWER_PWRCTRL_Pos) /*!< 0x01 */
15647 #define SDIO_POWER_PWRCTRL_1 (0x2U << SDIO_POWER_PWRCTRL_Pos) /*!< 0x02 */
15648
15649 /****************** Bit definition for SDIO_CLKCR register ******************/
15650 #define SDIO_CLKCR_CLKDIV_Pos (0U)
15651 #define SDIO_CLKCR_CLKDIV_Msk (0xFFU << SDIO_CLKCR_CLKDIV_Pos) /*!< 0x000000FF */
15652 #define SDIO_CLKCR_CLKDIV SDIO_CLKCR_CLKDIV_Msk /*!<Clock divide factor */
15653 #define SDIO_CLKCR_CLKEN_Pos (8U)
15654 #define SDIO_CLKCR_CLKEN_Msk (0x1U << SDIO_CLKCR_CLKEN_Pos) /*!< 0x00000100 */
15655 #define SDIO_CLKCR_CLKEN SDIO_CLKCR_CLKEN_Msk /*!<Clock enable bit */
15656 #define SDIO_CLKCR_PWRSAV_Pos (9U)
15657 #define SDIO_CLKCR_PWRSAV_Msk (0x1U << SDIO_CLKCR_PWRSAV_Pos) /*!< 0x00000200 */
15658 #define SDIO_CLKCR_PWRSAV SDIO_CLKCR_PWRSAV_Msk /*!<Power saving configuration bit */
15659 #define SDIO_CLKCR_BYPASS_Pos (10U)
15660 #define SDIO_CLKCR_BYPASS_Msk (0x1U << SDIO_CLKCR_BYPASS_Pos) /*!< 0x00000400 */
15661 #define SDIO_CLKCR_BYPASS SDIO_CLKCR_BYPASS_Msk /*!<Clock divider bypass enable bit */
15662
15663 #define SDIO_CLKCR_WIDBUS_Pos (11U)
15664 #define SDIO_CLKCR_WIDBUS_Msk (0x3U << SDIO_CLKCR_WIDBUS_Pos) /*!< 0x00001800 */
15665 #define SDIO_CLKCR_WIDBUS SDIO_CLKCR_WIDBUS_Msk /*!<WIDBUS[1:0] bits (Wide bus mode enable bit) */
15666 #define SDIO_CLKCR_WIDBUS_0 (0x1U << SDIO_CLKCR_WIDBUS_Pos) /*!< 0x0800 */
15667 #define SDIO_CLKCR_WIDBUS_1 (0x2U << SDIO_CLKCR_WIDBUS_Pos) /*!< 0x1000 */
15668
15669 #define SDIO_CLKCR_NEGEDGE_Pos (13U)
15670 #define SDIO_CLKCR_NEGEDGE_Msk (0x1U << SDIO_CLKCR_NEGEDGE_Pos) /*!< 0x00002000 */
15671 #define SDIO_CLKCR_NEGEDGE SDIO_CLKCR_NEGEDGE_Msk /*!<SDIO_CK dephasing selection bit */
15672 #define SDIO_CLKCR_HWFC_EN_Pos (14U)
15673 #define SDIO_CLKCR_HWFC_EN_Msk (0x1U << SDIO_CLKCR_HWFC_EN_Pos) /*!< 0x00004000 */
15674 #define SDIO_CLKCR_HWFC_EN SDIO_CLKCR_HWFC_EN_Msk /*!<HW Flow Control enable */
15675
15676 /******************* Bit definition for SDIO_ARG register *******************/
15677 #define SDIO_ARG_CMDARG_Pos (0U)
15678 #define SDIO_ARG_CMDARG_Msk (0xFFFFFFFFU << SDIO_ARG_CMDARG_Pos) /*!< 0xFFFFFFFF */
15679 #define SDIO_ARG_CMDARG SDIO_ARG_CMDARG_Msk /*!<Command argument */
15680
15681 /******************* Bit definition for SDIO_CMD register *******************/
15682 #define SDIO_CMD_CMDINDEX_Pos (0U)
15683 #define SDIO_CMD_CMDINDEX_Msk (0x3FU << SDIO_CMD_CMDINDEX_Pos) /*!< 0x0000003F */
15684 #define SDIO_CMD_CMDINDEX SDIO_CMD_CMDINDEX_Msk /*!<Command Index */
15685
15686 #define SDIO_CMD_WAITRESP_Pos (6U)
15687 #define SDIO_CMD_WAITRESP_Msk (0x3U << SDIO_CMD_WAITRESP_Pos) /*!< 0x000000C0 */
15688 #define SDIO_CMD_WAITRESP SDIO_CMD_WAITRESP_Msk /*!<WAITRESP[1:0] bits (Wait for response bits) */
15689 #define SDIO_CMD_WAITRESP_0 (0x1U << SDIO_CMD_WAITRESP_Pos) /*!< 0x0040 */
15690 #define SDIO_CMD_WAITRESP_1 (0x2U << SDIO_CMD_WAITRESP_Pos) /*!< 0x0080 */
15691
15692 #define SDIO_CMD_WAITINT_Pos (8U)
15693 #define SDIO_CMD_WAITINT_Msk (0x1U << SDIO_CMD_WAITINT_Pos) /*!< 0x00000100 */
15694 #define SDIO_CMD_WAITINT SDIO_CMD_WAITINT_Msk /*!<CPSM Waits for Interrupt Request */
15695 #define SDIO_CMD_WAITPEND_Pos (9U)
15696 #define SDIO_CMD_WAITPEND_Msk (0x1U << SDIO_CMD_WAITPEND_Pos) /*!< 0x00000200 */
15697 #define SDIO_CMD_WAITPEND SDIO_CMD_WAITPEND_Msk /*!<CPSM Waits for ends of data transfer (CmdPend internal signal) */
15698 #define SDIO_CMD_CPSMEN_Pos (10U)
15699 #define SDIO_CMD_CPSMEN_Msk (0x1U << SDIO_CMD_CPSMEN_Pos) /*!< 0x00000400 */
15700 #define SDIO_CMD_CPSMEN SDIO_CMD_CPSMEN_Msk /*!<Command path state machine (CPSM) Enable bit */
15701 #define SDIO_CMD_SDIOSUSPEND_Pos (11U)
15702 #define SDIO_CMD_SDIOSUSPEND_Msk (0x1U << SDIO_CMD_SDIOSUSPEND_Pos) /*!< 0x00000800 */
15703 #define SDIO_CMD_SDIOSUSPEND SDIO_CMD_SDIOSUSPEND_Msk /*!<SD I/O suspend command */
15704
15705 /***************** Bit definition for SDIO_RESPCMD register *****************/
15706 #define SDIO_RESPCMD_RESPCMD_Pos (0U)
15707 #define SDIO_RESPCMD_RESPCMD_Msk (0x3FU << SDIO_RESPCMD_RESPCMD_Pos) /*!< 0x0000003F */
15708 #define SDIO_RESPCMD_RESPCMD SDIO_RESPCMD_RESPCMD_Msk /*!<Response command index */
15709
15710 /****************** Bit definition for SDIO_RESP0 register ******************/
15711 #define SDIO_RESP0_CARDSTATUS0_Pos (0U)
15712 #define SDIO_RESP0_CARDSTATUS0_Msk (0xFFFFFFFFU << SDIO_RESP0_CARDSTATUS0_Pos) /*!< 0xFFFFFFFF */
15713 #define SDIO_RESP0_CARDSTATUS0 SDIO_RESP0_CARDSTATUS0_Msk /*!<Card Status */
15714
15715 /****************** Bit definition for SDIO_RESP1 register ******************/
15716 #define SDIO_RESP1_CARDSTATUS1_Pos (0U)
15717 #define SDIO_RESP1_CARDSTATUS1_Msk (0xFFFFFFFFU << SDIO_RESP1_CARDSTATUS1_Pos) /*!< 0xFFFFFFFF */
15718 #define SDIO_RESP1_CARDSTATUS1 SDIO_RESP1_CARDSTATUS1_Msk /*!<Card Status */
15719
15720 /****************** Bit definition for SDIO_RESP2 register ******************/
15721 #define SDIO_RESP2_CARDSTATUS2_Pos (0U)
15722 #define SDIO_RESP2_CARDSTATUS2_Msk (0xFFFFFFFFU << SDIO_RESP2_CARDSTATUS2_Pos) /*!< 0xFFFFFFFF */
15723 #define SDIO_RESP2_CARDSTATUS2 SDIO_RESP2_CARDSTATUS2_Msk /*!<Card Status */
15724
15725 /****************** Bit definition for SDIO_RESP3 register ******************/
15726 #define SDIO_RESP3_CARDSTATUS3_Pos (0U)
15727 #define SDIO_RESP3_CARDSTATUS3_Msk (0xFFFFFFFFU << SDIO_RESP3_CARDSTATUS3_Pos) /*!< 0xFFFFFFFF */
15728 #define SDIO_RESP3_CARDSTATUS3 SDIO_RESP3_CARDSTATUS3_Msk /*!<Card Status */
15729
15730 /****************** Bit definition for SDIO_RESP4 register ******************/
15731 #define SDIO_RESP4_CARDSTATUS4_Pos (0U)
15732 #define SDIO_RESP4_CARDSTATUS4_Msk (0xFFFFFFFFU << SDIO_RESP4_CARDSTATUS4_Pos) /*!< 0xFFFFFFFF */
15733 #define SDIO_RESP4_CARDSTATUS4 SDIO_RESP4_CARDSTATUS4_Msk /*!<Card Status */
15734
15735 /****************** Bit definition for SDIO_DTIMER register *****************/
15736 #define SDIO_DTIMER_DATATIME_Pos (0U)
15737 #define SDIO_DTIMER_DATATIME_Msk (0xFFFFFFFFU << SDIO_DTIMER_DATATIME_Pos) /*!< 0xFFFFFFFF */
15738 #define SDIO_DTIMER_DATATIME SDIO_DTIMER_DATATIME_Msk /*!<Data timeout period. */
15739
15740 /****************** Bit definition for SDIO_DLEN register *******************/
15741 #define SDIO_DLEN_DATALENGTH_Pos (0U)
15742 #define SDIO_DLEN_DATALENGTH_Msk (0x1FFFFFFU << SDIO_DLEN_DATALENGTH_Pos) /*!< 0x01FFFFFF */
15743 #define SDIO_DLEN_DATALENGTH SDIO_DLEN_DATALENGTH_Msk /*!<Data length value */
15744
15745 /****************** Bit definition for SDIO_DCTRL register ******************/
15746 #define SDIO_DCTRL_DTEN_Pos (0U)
15747 #define SDIO_DCTRL_DTEN_Msk (0x1U << SDIO_DCTRL_DTEN_Pos) /*!< 0x00000001 */
15748 #define SDIO_DCTRL_DTEN SDIO_DCTRL_DTEN_Msk /*!<Data transfer enabled bit */
15749 #define SDIO_DCTRL_DTDIR_Pos (1U)
15750 #define SDIO_DCTRL_DTDIR_Msk (0x1U << SDIO_DCTRL_DTDIR_Pos) /*!< 0x00000002 */
15751 #define SDIO_DCTRL_DTDIR SDIO_DCTRL_DTDIR_Msk /*!<Data transfer direction selection */
15752 #define SDIO_DCTRL_DTMODE_Pos (2U)
15753 #define SDIO_DCTRL_DTMODE_Msk (0x1U << SDIO_DCTRL_DTMODE_Pos) /*!< 0x00000004 */
15754 #define SDIO_DCTRL_DTMODE SDIO_DCTRL_DTMODE_Msk /*!<Data transfer mode selection */
15755 #define SDIO_DCTRL_DMAEN_Pos (3U)
15756 #define SDIO_DCTRL_DMAEN_Msk (0x1U << SDIO_DCTRL_DMAEN_Pos) /*!< 0x00000008 */
15757 #define SDIO_DCTRL_DMAEN SDIO_DCTRL_DMAEN_Msk /*!<DMA enabled bit */
15758
15759 #define SDIO_DCTRL_DBLOCKSIZE_Pos (4U)
15760 #define SDIO_DCTRL_DBLOCKSIZE_Msk (0xFU << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x000000F0 */
15761 #define SDIO_DCTRL_DBLOCKSIZE SDIO_DCTRL_DBLOCKSIZE_Msk /*!<DBLOCKSIZE[3:0] bits (Data block size) */
15762 #define SDIO_DCTRL_DBLOCKSIZE_0 (0x1U << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0010 */
15763 #define SDIO_DCTRL_DBLOCKSIZE_1 (0x2U << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0020 */
15764 #define SDIO_DCTRL_DBLOCKSIZE_2 (0x4U << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0040 */
15765 #define SDIO_DCTRL_DBLOCKSIZE_3 (0x8U << SDIO_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0080 */
15766
15767 #define SDIO_DCTRL_RWSTART_Pos (8U)
15768 #define SDIO_DCTRL_RWSTART_Msk (0x1U << SDIO_DCTRL_RWSTART_Pos) /*!< 0x00000100 */
15769 #define SDIO_DCTRL_RWSTART SDIO_DCTRL_RWSTART_Msk /*!<Read wait start */
15770 #define SDIO_DCTRL_RWSTOP_Pos (9U)
15771 #define SDIO_DCTRL_RWSTOP_Msk (0x1U << SDIO_DCTRL_RWSTOP_Pos) /*!< 0x00000200 */
15772 #define SDIO_DCTRL_RWSTOP SDIO_DCTRL_RWSTOP_Msk /*!<Read wait stop */
15773 #define SDIO_DCTRL_RWMOD_Pos (10U)
15774 #define SDIO_DCTRL_RWMOD_Msk (0x1U << SDIO_DCTRL_RWMOD_Pos) /*!< 0x00000400 */
15775 #define SDIO_DCTRL_RWMOD SDIO_DCTRL_RWMOD_Msk /*!<Read wait mode */
15776 #define SDIO_DCTRL_SDIOEN_Pos (11U)
15777 #define SDIO_DCTRL_SDIOEN_Msk (0x1U << SDIO_DCTRL_SDIOEN_Pos) /*!< 0x00000800 */
15778 #define SDIO_DCTRL_SDIOEN SDIO_DCTRL_SDIOEN_Msk /*!<SD I/O enable functions */
15779
15780 /****************** Bit definition for SDIO_DCOUNT register *****************/
15781 #define SDIO_DCOUNT_DATACOUNT_Pos (0U)
15782 #define SDIO_DCOUNT_DATACOUNT_Msk (0x1FFFFFFU << SDIO_DCOUNT_DATACOUNT_Pos) /*!< 0x01FFFFFF */
15783 #define SDIO_DCOUNT_DATACOUNT SDIO_DCOUNT_DATACOUNT_Msk /*!<Data count value */
15784
15785 /****************** Bit definition for SDIO_STA register ********************/
15786 #define SDIO_STA_CCRCFAIL_Pos (0U)
15787 #define SDIO_STA_CCRCFAIL_Msk (0x1U << SDIO_STA_CCRCFAIL_Pos) /*!< 0x00000001 */
15788 #define SDIO_STA_CCRCFAIL SDIO_STA_CCRCFAIL_Msk /*!<Command response received (CRC check failed) */
15789 #define SDIO_STA_DCRCFAIL_Pos (1U)
15790 #define SDIO_STA_DCRCFAIL_Msk (0x1U << SDIO_STA_DCRCFAIL_Pos) /*!< 0x00000002 */
15791 #define SDIO_STA_DCRCFAIL SDIO_STA_DCRCFAIL_Msk /*!<Data block sent/received (CRC check failed) */
15792 #define SDIO_STA_CTIMEOUT_Pos (2U)
15793 #define SDIO_STA_CTIMEOUT_Msk (0x1U << SDIO_STA_CTIMEOUT_Pos) /*!< 0x00000004 */
15794 #define SDIO_STA_CTIMEOUT SDIO_STA_CTIMEOUT_Msk /*!<Command response timeout */
15795 #define SDIO_STA_DTIMEOUT_Pos (3U)
15796 #define SDIO_STA_DTIMEOUT_Msk (0x1U << SDIO_STA_DTIMEOUT_Pos) /*!< 0x00000008 */
15797 #define SDIO_STA_DTIMEOUT SDIO_STA_DTIMEOUT_Msk /*!<Data timeout */
15798 #define SDIO_STA_TXUNDERR_Pos (4U)
15799 #define SDIO_STA_TXUNDERR_Msk (0x1U << SDIO_STA_TXUNDERR_Pos) /*!< 0x00000010 */
15800 #define SDIO_STA_TXUNDERR SDIO_STA_TXUNDERR_Msk /*!<Transmit FIFO underrun error */
15801 #define SDIO_STA_RXOVERR_Pos (5U)
15802 #define SDIO_STA_RXOVERR_Msk (0x1U << SDIO_STA_RXOVERR_Pos) /*!< 0x00000020 */
15803 #define SDIO_STA_RXOVERR SDIO_STA_RXOVERR_Msk /*!<Received FIFO overrun error */
15804 #define SDIO_STA_CMDREND_Pos (6U)
15805 #define SDIO_STA_CMDREND_Msk (0x1U << SDIO_STA_CMDREND_Pos) /*!< 0x00000040 */
15806 #define SDIO_STA_CMDREND SDIO_STA_CMDREND_Msk /*!<Command response received (CRC check passed) */
15807 #define SDIO_STA_CMDSENT_Pos (7U)
15808 #define SDIO_STA_CMDSENT_Msk (0x1U << SDIO_STA_CMDSENT_Pos) /*!< 0x00000080 */
15809 #define SDIO_STA_CMDSENT SDIO_STA_CMDSENT_Msk /*!<Command sent (no response required) */
15810 #define SDIO_STA_DATAEND_Pos (8U)
15811 #define SDIO_STA_DATAEND_Msk (0x1U << SDIO_STA_DATAEND_Pos) /*!< 0x00000100 */
15812 #define SDIO_STA_DATAEND SDIO_STA_DATAEND_Msk /*!<Data end (data counter, SDIDCOUNT, is zero) */
15813 #define SDIO_STA_DBCKEND_Pos (10U)
15814 #define SDIO_STA_DBCKEND_Msk (0x1U << SDIO_STA_DBCKEND_Pos) /*!< 0x00000400 */
15815 #define SDIO_STA_DBCKEND SDIO_STA_DBCKEND_Msk /*!<Data block sent/received (CRC check passed) */
15816 #define SDIO_STA_CMDACT_Pos (11U)
15817 #define SDIO_STA_CMDACT_Msk (0x1U << SDIO_STA_CMDACT_Pos) /*!< 0x00000800 */
15818 #define SDIO_STA_CMDACT SDIO_STA_CMDACT_Msk /*!<Command transfer in progress */
15819 #define SDIO_STA_TXACT_Pos (12U)
15820 #define SDIO_STA_TXACT_Msk (0x1U << SDIO_STA_TXACT_Pos) /*!< 0x00001000 */
15821 #define SDIO_STA_TXACT SDIO_STA_TXACT_Msk /*!<Data transmit in progress */
15822 #define SDIO_STA_RXACT_Pos (13U)
15823 #define SDIO_STA_RXACT_Msk (0x1U << SDIO_STA_RXACT_Pos) /*!< 0x00002000 */
15824 #define SDIO_STA_RXACT SDIO_STA_RXACT_Msk /*!<Data receive in progress */
15825 #define SDIO_STA_TXFIFOHE_Pos (14U)
15826 #define SDIO_STA_TXFIFOHE_Msk (0x1U << SDIO_STA_TXFIFOHE_Pos) /*!< 0x00004000 */
15827 #define SDIO_STA_TXFIFOHE SDIO_STA_TXFIFOHE_Msk /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
15828 #define SDIO_STA_RXFIFOHF_Pos (15U)
15829 #define SDIO_STA_RXFIFOHF_Msk (0x1U << SDIO_STA_RXFIFOHF_Pos) /*!< 0x00008000 */
15830 #define SDIO_STA_RXFIFOHF SDIO_STA_RXFIFOHF_Msk /*!<Receive FIFO Half Full: there are at least 8 words in the FIFO */
15831 #define SDIO_STA_TXFIFOF_Pos (16U)
15832 #define SDIO_STA_TXFIFOF_Msk (0x1U << SDIO_STA_TXFIFOF_Pos) /*!< 0x00010000 */
15833 #define SDIO_STA_TXFIFOF SDIO_STA_TXFIFOF_Msk /*!<Transmit FIFO full */
15834 #define SDIO_STA_RXFIFOF_Pos (17U)
15835 #define SDIO_STA_RXFIFOF_Msk (0x1U << SDIO_STA_RXFIFOF_Pos) /*!< 0x00020000 */
15836 #define SDIO_STA_RXFIFOF SDIO_STA_RXFIFOF_Msk /*!<Receive FIFO full */
15837 #define SDIO_STA_TXFIFOE_Pos (18U)
15838 #define SDIO_STA_TXFIFOE_Msk (0x1U << SDIO_STA_TXFIFOE_Pos) /*!< 0x00040000 */
15839 #define SDIO_STA_TXFIFOE SDIO_STA_TXFIFOE_Msk /*!<Transmit FIFO empty */
15840 #define SDIO_STA_RXFIFOE_Pos (19U)
15841 #define SDIO_STA_RXFIFOE_Msk (0x1U << SDIO_STA_RXFIFOE_Pos) /*!< 0x00080000 */
15842 #define SDIO_STA_RXFIFOE SDIO_STA_RXFIFOE_Msk /*!<Receive FIFO empty */
15843 #define SDIO_STA_TXDAVL_Pos (20U)
15844 #define SDIO_STA_TXDAVL_Msk (0x1U << SDIO_STA_TXDAVL_Pos) /*!< 0x00100000 */
15845 #define SDIO_STA_TXDAVL SDIO_STA_TXDAVL_Msk /*!<Data available in transmit FIFO */
15846 #define SDIO_STA_RXDAVL_Pos (21U)
15847 #define SDIO_STA_RXDAVL_Msk (0x1U << SDIO_STA_RXDAVL_Pos) /*!< 0x00200000 */
15848 #define SDIO_STA_RXDAVL SDIO_STA_RXDAVL_Msk /*!<Data available in receive FIFO */
15849 #define SDIO_STA_SDIOIT_Pos (22U)
15850 #define SDIO_STA_SDIOIT_Msk (0x1U << SDIO_STA_SDIOIT_Pos) /*!< 0x00400000 */
15851 #define SDIO_STA_SDIOIT SDIO_STA_SDIOIT_Msk /*!<SDIO interrupt received */
15852
15853 /******************* Bit definition for SDIO_ICR register *******************/
15854 #define SDIO_ICR_CCRCFAILC_Pos (0U)
15855 #define SDIO_ICR_CCRCFAILC_Msk (0x1U << SDIO_ICR_CCRCFAILC_Pos) /*!< 0x00000001 */
15856 #define SDIO_ICR_CCRCFAILC SDIO_ICR_CCRCFAILC_Msk /*!<CCRCFAIL flag clear bit */
15857 #define SDIO_ICR_DCRCFAILC_Pos (1U)
15858 #define SDIO_ICR_DCRCFAILC_Msk (0x1U << SDIO_ICR_DCRCFAILC_Pos) /*!< 0x00000002 */
15859 #define SDIO_ICR_DCRCFAILC SDIO_ICR_DCRCFAILC_Msk /*!<DCRCFAIL flag clear bit */
15860 #define SDIO_ICR_CTIMEOUTC_Pos (2U)
15861 #define SDIO_ICR_CTIMEOUTC_Msk (0x1U << SDIO_ICR_CTIMEOUTC_Pos) /*!< 0x00000004 */
15862 #define SDIO_ICR_CTIMEOUTC SDIO_ICR_CTIMEOUTC_Msk /*!<CTIMEOUT flag clear bit */
15863 #define SDIO_ICR_DTIMEOUTC_Pos (3U)
15864 #define SDIO_ICR_DTIMEOUTC_Msk (0x1U << SDIO_ICR_DTIMEOUTC_Pos) /*!< 0x00000008 */
15865 #define SDIO_ICR_DTIMEOUTC SDIO_ICR_DTIMEOUTC_Msk /*!<DTIMEOUT flag clear bit */
15866 #define SDIO_ICR_TXUNDERRC_Pos (4U)
15867 #define SDIO_ICR_TXUNDERRC_Msk (0x1U << SDIO_ICR_TXUNDERRC_Pos) /*!< 0x00000010 */
15868 #define SDIO_ICR_TXUNDERRC SDIO_ICR_TXUNDERRC_Msk /*!<TXUNDERR flag clear bit */
15869 #define SDIO_ICR_RXOVERRC_Pos (5U)
15870 #define SDIO_ICR_RXOVERRC_Msk (0x1U << SDIO_ICR_RXOVERRC_Pos) /*!< 0x00000020 */
15871 #define SDIO_ICR_RXOVERRC SDIO_ICR_RXOVERRC_Msk /*!<RXOVERR flag clear bit */
15872 #define SDIO_ICR_CMDRENDC_Pos (6U)
15873 #define SDIO_ICR_CMDRENDC_Msk (0x1U << SDIO_ICR_CMDRENDC_Pos) /*!< 0x00000040 */
15874 #define SDIO_ICR_CMDRENDC SDIO_ICR_CMDRENDC_Msk /*!<CMDREND flag clear bit */
15875 #define SDIO_ICR_CMDSENTC_Pos (7U)
15876 #define SDIO_ICR_CMDSENTC_Msk (0x1U << SDIO_ICR_CMDSENTC_Pos) /*!< 0x00000080 */
15877 #define SDIO_ICR_CMDSENTC SDIO_ICR_CMDSENTC_Msk /*!<CMDSENT flag clear bit */
15878 #define SDIO_ICR_DATAENDC_Pos (8U)
15879 #define SDIO_ICR_DATAENDC_Msk (0x1U << SDIO_ICR_DATAENDC_Pos) /*!< 0x00000100 */
15880 #define SDIO_ICR_DATAENDC SDIO_ICR_DATAENDC_Msk /*!<DATAEND flag clear bit */
15881 #define SDIO_ICR_DBCKENDC_Pos (10U)
15882 #define SDIO_ICR_DBCKENDC_Msk (0x1U << SDIO_ICR_DBCKENDC_Pos) /*!< 0x00000400 */
15883 #define SDIO_ICR_DBCKENDC SDIO_ICR_DBCKENDC_Msk /*!<DBCKEND flag clear bit */
15884 #define SDIO_ICR_SDIOITC_Pos (22U)
15885 #define SDIO_ICR_SDIOITC_Msk (0x1U << SDIO_ICR_SDIOITC_Pos) /*!< 0x00400000 */
15886 #define SDIO_ICR_SDIOITC SDIO_ICR_SDIOITC_Msk /*!<SDIOIT flag clear bit */
15887
15888 /****************** Bit definition for SDIO_MASK register *******************/
15889 #define SDIO_MASK_CCRCFAILIE_Pos (0U)
15890 #define SDIO_MASK_CCRCFAILIE_Msk (0x1U << SDIO_MASK_CCRCFAILIE_Pos) /*!< 0x00000001 */
15891 #define SDIO_MASK_CCRCFAILIE SDIO_MASK_CCRCFAILIE_Msk /*!<Command CRC Fail Interrupt Enable */
15892 #define SDIO_MASK_DCRCFAILIE_Pos (1U)
15893 #define SDIO_MASK_DCRCFAILIE_Msk (0x1U << SDIO_MASK_DCRCFAILIE_Pos) /*!< 0x00000002 */
15894 #define SDIO_MASK_DCRCFAILIE SDIO_MASK_DCRCFAILIE_Msk /*!<Data CRC Fail Interrupt Enable */
15895 #define SDIO_MASK_CTIMEOUTIE_Pos (2U)
15896 #define SDIO_MASK_CTIMEOUTIE_Msk (0x1U << SDIO_MASK_CTIMEOUTIE_Pos) /*!< 0x00000004 */
15897 #define SDIO_MASK_CTIMEOUTIE SDIO_MASK_CTIMEOUTIE_Msk /*!<Command TimeOut Interrupt Enable */
15898 #define SDIO_MASK_DTIMEOUTIE_Pos (3U)
15899 #define SDIO_MASK_DTIMEOUTIE_Msk (0x1U << SDIO_MASK_DTIMEOUTIE_Pos) /*!< 0x00000008 */
15900 #define SDIO_MASK_DTIMEOUTIE SDIO_MASK_DTIMEOUTIE_Msk /*!<Data TimeOut Interrupt Enable */
15901 #define SDIO_MASK_TXUNDERRIE_Pos (4U)
15902 #define SDIO_MASK_TXUNDERRIE_Msk (0x1U << SDIO_MASK_TXUNDERRIE_Pos) /*!< 0x00000010 */
15903 #define SDIO_MASK_TXUNDERRIE SDIO_MASK_TXUNDERRIE_Msk /*!<Tx FIFO UnderRun Error Interrupt Enable */
15904 #define SDIO_MASK_RXOVERRIE_Pos (5U)
15905 #define SDIO_MASK_RXOVERRIE_Msk (0x1U << SDIO_MASK_RXOVERRIE_Pos) /*!< 0x00000020 */
15906 #define SDIO_MASK_RXOVERRIE SDIO_MASK_RXOVERRIE_Msk /*!<Rx FIFO OverRun Error Interrupt Enable */
15907 #define SDIO_MASK_CMDRENDIE_Pos (6U)
15908 #define SDIO_MASK_CMDRENDIE_Msk (0x1U << SDIO_MASK_CMDRENDIE_Pos) /*!< 0x00000040 */
15909 #define SDIO_MASK_CMDRENDIE SDIO_MASK_CMDRENDIE_Msk /*!<Command Response Received Interrupt Enable */
15910 #define SDIO_MASK_CMDSENTIE_Pos (7U)
15911 #define SDIO_MASK_CMDSENTIE_Msk (0x1U << SDIO_MASK_CMDSENTIE_Pos) /*!< 0x00000080 */
15912 #define SDIO_MASK_CMDSENTIE SDIO_MASK_CMDSENTIE_Msk /*!<Command Sent Interrupt Enable */
15913 #define SDIO_MASK_DATAENDIE_Pos (8U)
15914 #define SDIO_MASK_DATAENDIE_Msk (0x1U << SDIO_MASK_DATAENDIE_Pos) /*!< 0x00000100 */
15915 #define SDIO_MASK_DATAENDIE SDIO_MASK_DATAENDIE_Msk /*!<Data End Interrupt Enable */
15916 #define SDIO_MASK_DBCKENDIE_Pos (10U)
15917 #define SDIO_MASK_DBCKENDIE_Msk (0x1U << SDIO_MASK_DBCKENDIE_Pos) /*!< 0x00000400 */
15918 #define SDIO_MASK_DBCKENDIE SDIO_MASK_DBCKENDIE_Msk /*!<Data Block End Interrupt Enable */
15919 #define SDIO_MASK_CMDACTIE_Pos (11U)
15920 #define SDIO_MASK_CMDACTIE_Msk (0x1U << SDIO_MASK_CMDACTIE_Pos) /*!< 0x00000800 */
15921 #define SDIO_MASK_CMDACTIE SDIO_MASK_CMDACTIE_Msk /*!<CCommand Acting Interrupt Enable */
15922 #define SDIO_MASK_TXACTIE_Pos (12U)
15923 #define SDIO_MASK_TXACTIE_Msk (0x1U << SDIO_MASK_TXACTIE_Pos) /*!< 0x00001000 */
15924 #define SDIO_MASK_TXACTIE SDIO_MASK_TXACTIE_Msk /*!<Data Transmit Acting Interrupt Enable */
15925 #define SDIO_MASK_RXACTIE_Pos (13U)
15926 #define SDIO_MASK_RXACTIE_Msk (0x1U << SDIO_MASK_RXACTIE_Pos) /*!< 0x00002000 */
15927 #define SDIO_MASK_RXACTIE SDIO_MASK_RXACTIE_Msk /*!<Data receive acting interrupt enabled */
15928 #define SDIO_MASK_TXFIFOHEIE_Pos (14U)
15929 #define SDIO_MASK_TXFIFOHEIE_Msk (0x1U << SDIO_MASK_TXFIFOHEIE_Pos) /*!< 0x00004000 */
15930 #define SDIO_MASK_TXFIFOHEIE SDIO_MASK_TXFIFOHEIE_Msk /*!<Tx FIFO Half Empty interrupt Enable */
15931 #define SDIO_MASK_RXFIFOHFIE_Pos (15U)
15932 #define SDIO_MASK_RXFIFOHFIE_Msk (0x1U << SDIO_MASK_RXFIFOHFIE_Pos) /*!< 0x00008000 */
15933 #define SDIO_MASK_RXFIFOHFIE SDIO_MASK_RXFIFOHFIE_Msk /*!<Rx FIFO Half Full interrupt Enable */
15934 #define SDIO_MASK_TXFIFOFIE_Pos (16U)
15935 #define SDIO_MASK_TXFIFOFIE_Msk (0x1U << SDIO_MASK_TXFIFOFIE_Pos) /*!< 0x00010000 */
15936 #define SDIO_MASK_TXFIFOFIE SDIO_MASK_TXFIFOFIE_Msk /*!<Tx FIFO Full interrupt Enable */
15937 #define SDIO_MASK_RXFIFOFIE_Pos (17U)
15938 #define SDIO_MASK_RXFIFOFIE_Msk (0x1U << SDIO_MASK_RXFIFOFIE_Pos) /*!< 0x00020000 */
15939 #define SDIO_MASK_RXFIFOFIE SDIO_MASK_RXFIFOFIE_Msk /*!<Rx FIFO Full interrupt Enable */
15940 #define SDIO_MASK_TXFIFOEIE_Pos (18U)
15941 #define SDIO_MASK_TXFIFOEIE_Msk (0x1U << SDIO_MASK_TXFIFOEIE_Pos) /*!< 0x00040000 */
15942 #define SDIO_MASK_TXFIFOEIE SDIO_MASK_TXFIFOEIE_Msk /*!<Tx FIFO Empty interrupt Enable */
15943 #define SDIO_MASK_RXFIFOEIE_Pos (19U)
15944 #define SDIO_MASK_RXFIFOEIE_Msk (0x1U << SDIO_MASK_RXFIFOEIE_Pos) /*!< 0x00080000 */
15945 #define SDIO_MASK_RXFIFOEIE SDIO_MASK_RXFIFOEIE_Msk /*!<Rx FIFO Empty interrupt Enable */
15946 #define SDIO_MASK_TXDAVLIE_Pos (20U)
15947 #define SDIO_MASK_TXDAVLIE_Msk (0x1U << SDIO_MASK_TXDAVLIE_Pos) /*!< 0x00100000 */
15948 #define SDIO_MASK_TXDAVLIE SDIO_MASK_TXDAVLIE_Msk /*!<Data available in Tx FIFO interrupt Enable */
15949 #define SDIO_MASK_RXDAVLIE_Pos (21U)
15950 #define SDIO_MASK_RXDAVLIE_Msk (0x1U << SDIO_MASK_RXDAVLIE_Pos) /*!< 0x00200000 */
15951 #define SDIO_MASK_RXDAVLIE SDIO_MASK_RXDAVLIE_Msk /*!<Data available in Rx FIFO interrupt Enable */
15952 #define SDIO_MASK_SDIOITIE_Pos (22U)
15953 #define SDIO_MASK_SDIOITIE_Msk (0x1U << SDIO_MASK_SDIOITIE_Pos) /*!< 0x00400000 */
15954 #define SDIO_MASK_SDIOITIE SDIO_MASK_SDIOITIE_Msk /*!<SDIO Mode Interrupt Received interrupt Enable */
15955
15956 /***************** Bit definition for SDIO_FIFOCNT register *****************/
15957 #define SDIO_FIFOCNT_FIFOCOUNT_Pos (0U)
15958 #define SDIO_FIFOCNT_FIFOCOUNT_Msk (0xFFFFFFU << SDIO_FIFOCNT_FIFOCOUNT_Pos) /*!< 0x00FFFFFF */
15959 #define SDIO_FIFOCNT_FIFOCOUNT SDIO_FIFOCNT_FIFOCOUNT_Msk /*!<Remaining number of words to be written to or read from the FIFO */
15960
15961 /****************** Bit definition for SDIO_FIFO register *******************/
15962 #define SDIO_FIFO_FIFODATA_Pos (0U)
15963 #define SDIO_FIFO_FIFODATA_Msk (0xFFFFFFFFU << SDIO_FIFO_FIFODATA_Pos) /*!< 0xFFFFFFFF */
15964 #define SDIO_FIFO_FIFODATA SDIO_FIFO_FIFODATA_Msk /*!<Receive and transmit FIFO data */
15965
15966 /******************************************************************************/
15967 /* */
15968 /* Serial Peripheral Interface */
15969 /* */
15970 /******************************************************************************/
15971 #define SPI_I2S_FULLDUPLEX_SUPPORT /*!< I2S Full-Duplex support */
15972
15973 /******************* Bit definition for SPI_CR1 register ********************/
15974 #define SPI_CR1_CPHA_Pos (0U)
15975 #define SPI_CR1_CPHA_Msk (0x1U << SPI_CR1_CPHA_Pos) /*!< 0x00000001 */
15976 #define SPI_CR1_CPHA SPI_CR1_CPHA_Msk /*!<Clock Phase */
15977 #define SPI_CR1_CPOL_Pos (1U)
15978 #define SPI_CR1_CPOL_Msk (0x1U << SPI_CR1_CPOL_Pos) /*!< 0x00000002 */
15979 #define SPI_CR1_CPOL SPI_CR1_CPOL_Msk /*!<Clock Polarity */
15980 #define SPI_CR1_MSTR_Pos (2U)
15981 #define SPI_CR1_MSTR_Msk (0x1U << SPI_CR1_MSTR_Pos) /*!< 0x00000004 */
15982 #define SPI_CR1_MSTR SPI_CR1_MSTR_Msk /*!<Master Selection */
15983
15984 #define SPI_CR1_BR_Pos (3U)
15985 #define SPI_CR1_BR_Msk (0x7U << SPI_CR1_BR_Pos) /*!< 0x00000038 */
15986 #define SPI_CR1_BR SPI_CR1_BR_Msk /*!<BR[2:0] bits (Baud Rate Control) */
15987 #define SPI_CR1_BR_0 (0x1U << SPI_CR1_BR_Pos) /*!< 0x00000008 */
15988 #define SPI_CR1_BR_1 (0x2U << SPI_CR1_BR_Pos) /*!< 0x00000010 */
15989 #define SPI_CR1_BR_2 (0x4U << SPI_CR1_BR_Pos) /*!< 0x00000020 */
15990
15991 #define SPI_CR1_SPE_Pos (6U)
15992 #define SPI_CR1_SPE_Msk (0x1U << SPI_CR1_SPE_Pos) /*!< 0x00000040 */
15993 #define SPI_CR1_SPE SPI_CR1_SPE_Msk /*!<SPI Enable */
15994 #define SPI_CR1_LSBFIRST_Pos (7U)
15995 #define SPI_CR1_LSBFIRST_Msk (0x1U << SPI_CR1_LSBFIRST_Pos) /*!< 0x00000080 */
15996 #define SPI_CR1_LSBFIRST SPI_CR1_LSBFIRST_Msk /*!<Frame Format */
15997 #define SPI_CR1_SSI_Pos (8U)
15998 #define SPI_CR1_SSI_Msk (0x1U << SPI_CR1_SSI_Pos) /*!< 0x00000100 */
15999 #define SPI_CR1_SSI SPI_CR1_SSI_Msk /*!<Internal slave select */
16000 #define SPI_CR1_SSM_Pos (9U)
16001 #define SPI_CR1_SSM_Msk (0x1U << SPI_CR1_SSM_Pos) /*!< 0x00000200 */
16002 #define SPI_CR1_SSM SPI_CR1_SSM_Msk /*!<Software slave management */
16003 #define SPI_CR1_RXONLY_Pos (10U)
16004 #define SPI_CR1_RXONLY_Msk (0x1U << SPI_CR1_RXONLY_Pos) /*!< 0x00000400 */
16005 #define SPI_CR1_RXONLY SPI_CR1_RXONLY_Msk /*!<Receive only */
16006 #define SPI_CR1_DFF_Pos (11U)
16007 #define SPI_CR1_DFF_Msk (0x1U << SPI_CR1_DFF_Pos) /*!< 0x00000800 */
16008 #define SPI_CR1_DFF SPI_CR1_DFF_Msk /*!<Data Frame Format */
16009 #define SPI_CR1_CRCNEXT_Pos (12U)
16010 #define SPI_CR1_CRCNEXT_Msk (0x1U << SPI_CR1_CRCNEXT_Pos) /*!< 0x00001000 */
16011 #define SPI_CR1_CRCNEXT SPI_CR1_CRCNEXT_Msk /*!<Transmit CRC next */
16012 #define SPI_CR1_CRCEN_Pos (13U)
16013 #define SPI_CR1_CRCEN_Msk (0x1U << SPI_CR1_CRCEN_Pos) /*!< 0x00002000 */
16014 #define SPI_CR1_CRCEN SPI_CR1_CRCEN_Msk /*!<Hardware CRC calculation enable */
16015 #define SPI_CR1_BIDIOE_Pos (14U)
16016 #define SPI_CR1_BIDIOE_Msk (0x1U << SPI_CR1_BIDIOE_Pos) /*!< 0x00004000 */
16017 #define SPI_CR1_BIDIOE SPI_CR1_BIDIOE_Msk /*!<Output enable in bidirectional mode */
16018 #define SPI_CR1_BIDIMODE_Pos (15U)
16019 #define SPI_CR1_BIDIMODE_Msk (0x1U << SPI_CR1_BIDIMODE_Pos) /*!< 0x00008000 */
16020 #define SPI_CR1_BIDIMODE SPI_CR1_BIDIMODE_Msk /*!<Bidirectional data mode enable */
16021
16022 /******************* Bit definition for SPI_CR2 register ********************/
16023 #define SPI_CR2_RXDMAEN_Pos (0U)
16024 #define SPI_CR2_RXDMAEN_Msk (0x1U << SPI_CR2_RXDMAEN_Pos) /*!< 0x00000001 */
16025 #define SPI_CR2_RXDMAEN SPI_CR2_RXDMAEN_Msk /*!<Rx Buffer DMA Enable */
16026 #define SPI_CR2_TXDMAEN_Pos (1U)
16027 #define SPI_CR2_TXDMAEN_Msk (0x1U << SPI_CR2_TXDMAEN_Pos) /*!< 0x00000002 */
16028 #define SPI_CR2_TXDMAEN SPI_CR2_TXDMAEN_Msk /*!<Tx Buffer DMA Enable */
16029 #define SPI_CR2_SSOE_Pos (2U)
16030 #define SPI_CR2_SSOE_Msk (0x1U << SPI_CR2_SSOE_Pos) /*!< 0x00000004 */
16031 #define SPI_CR2_SSOE SPI_CR2_SSOE_Msk /*!<SS Output Enable */
16032 #define SPI_CR2_FRF_Pos (4U)
16033 #define SPI_CR2_FRF_Msk (0x1U << SPI_CR2_FRF_Pos) /*!< 0x00000010 */
16034 #define SPI_CR2_FRF SPI_CR2_FRF_Msk /*!<Frame Format */
16035 #define SPI_CR2_ERRIE_Pos (5U)
16036 #define SPI_CR2_ERRIE_Msk (0x1U << SPI_CR2_ERRIE_Pos) /*!< 0x00000020 */
16037 #define SPI_CR2_ERRIE SPI_CR2_ERRIE_Msk /*!<Error Interrupt Enable */
16038 #define SPI_CR2_RXNEIE_Pos (6U)
16039 #define SPI_CR2_RXNEIE_Msk (0x1U << SPI_CR2_RXNEIE_Pos) /*!< 0x00000040 */
16040 #define SPI_CR2_RXNEIE SPI_CR2_RXNEIE_Msk /*!<RX buffer Not Empty Interrupt Enable */
16041 #define SPI_CR2_TXEIE_Pos (7U)
16042 #define SPI_CR2_TXEIE_Msk (0x1U << SPI_CR2_TXEIE_Pos) /*!< 0x00000080 */
16043 #define SPI_CR2_TXEIE SPI_CR2_TXEIE_Msk /*!<Tx buffer Empty Interrupt Enable */
16044
16045 /******************** Bit definition for SPI_SR register ********************/
16046 #define SPI_SR_RXNE_Pos (0U)
16047 #define SPI_SR_RXNE_Msk (0x1U << SPI_SR_RXNE_Pos) /*!< 0x00000001 */
16048 #define SPI_SR_RXNE SPI_SR_RXNE_Msk /*!<Receive buffer Not Empty */
16049 #define SPI_SR_TXE_Pos (1U)
16050 #define SPI_SR_TXE_Msk (0x1U << SPI_SR_TXE_Pos) /*!< 0x00000002 */
16051 #define SPI_SR_TXE SPI_SR_TXE_Msk /*!<Transmit buffer Empty */
16052 #define SPI_SR_CHSIDE_Pos (2U)
16053 #define SPI_SR_CHSIDE_Msk (0x1U << SPI_SR_CHSIDE_Pos) /*!< 0x00000004 */
16054 #define SPI_SR_CHSIDE SPI_SR_CHSIDE_Msk /*!<Channel side */
16055 #define SPI_SR_UDR_Pos (3U)
16056 #define SPI_SR_UDR_Msk (0x1U << SPI_SR_UDR_Pos) /*!< 0x00000008 */
16057 #define SPI_SR_UDR SPI_SR_UDR_Msk /*!<Underrun flag */
16058 #define SPI_SR_CRCERR_Pos (4U)
16059 #define SPI_SR_CRCERR_Msk (0x1U << SPI_SR_CRCERR_Pos) /*!< 0x00000010 */
16060 #define SPI_SR_CRCERR SPI_SR_CRCERR_Msk /*!<CRC Error flag */
16061 #define SPI_SR_MODF_Pos (5U)
16062 #define SPI_SR_MODF_Msk (0x1U << SPI_SR_MODF_Pos) /*!< 0x00000020 */
16063 #define SPI_SR_MODF SPI_SR_MODF_Msk /*!<Mode fault */
16064 #define SPI_SR_OVR_Pos (6U)
16065 #define SPI_SR_OVR_Msk (0x1U << SPI_SR_OVR_Pos) /*!< 0x00000040 */
16066 #define SPI_SR_OVR SPI_SR_OVR_Msk /*!<Overrun flag */
16067 #define SPI_SR_BSY_Pos (7U)
16068 #define SPI_SR_BSY_Msk (0x1U << SPI_SR_BSY_Pos) /*!< 0x00000080 */
16069 #define SPI_SR_BSY SPI_SR_BSY_Msk /*!<Busy flag */
16070 #define SPI_SR_FRE_Pos (8U)
16071 #define SPI_SR_FRE_Msk (0x1U << SPI_SR_FRE_Pos) /*!< 0x00000100 */
16072 #define SPI_SR_FRE SPI_SR_FRE_Msk /*!<Frame format error flag */
16073
16074 /******************** Bit definition for SPI_DR register ********************/
16075 #define SPI_DR_DR_Pos (0U)
16076 #define SPI_DR_DR_Msk (0xFFFFU << SPI_DR_DR_Pos) /*!< 0x0000FFFF */
16077 #define SPI_DR_DR SPI_DR_DR_Msk /*!<Data Register */
16078
16079 /******************* Bit definition for SPI_CRCPR register ******************/
16080 #define SPI_CRCPR_CRCPOLY_Pos (0U)
16081 #define SPI_CRCPR_CRCPOLY_Msk (0xFFFFU << SPI_CRCPR_CRCPOLY_Pos) /*!< 0x0000FFFF */
16082 #define SPI_CRCPR_CRCPOLY SPI_CRCPR_CRCPOLY_Msk /*!<CRC polynomial register */
16083
16084 /****************** Bit definition for SPI_RXCRCR register ******************/
16085 #define SPI_RXCRCR_RXCRC_Pos (0U)
16086 #define SPI_RXCRCR_RXCRC_Msk (0xFFFFU << SPI_RXCRCR_RXCRC_Pos) /*!< 0x0000FFFF */
16087 #define SPI_RXCRCR_RXCRC SPI_RXCRCR_RXCRC_Msk /*!<Rx CRC Register */
16088
16089 /****************** Bit definition for SPI_TXCRCR register ******************/
16090 #define SPI_TXCRCR_TXCRC_Pos (0U)
16091 #define SPI_TXCRCR_TXCRC_Msk (0xFFFFU << SPI_TXCRCR_TXCRC_Pos) /*!< 0x0000FFFF */
16092 #define SPI_TXCRCR_TXCRC SPI_TXCRCR_TXCRC_Msk /*!<Tx CRC Register */
16093
16094 /****************** Bit definition for SPI_I2SCFGR register *****************/
16095 #define SPI_I2SCFGR_CHLEN_Pos (0U)
16096 #define SPI_I2SCFGR_CHLEN_Msk (0x1U << SPI_I2SCFGR_CHLEN_Pos) /*!< 0x00000001 */
16097 #define SPI_I2SCFGR_CHLEN SPI_I2SCFGR_CHLEN_Msk /*!<Channel length (number of bits per audio channel) */
16098
16099 #define SPI_I2SCFGR_DATLEN_Pos (1U)
16100 #define SPI_I2SCFGR_DATLEN_Msk (0x3U << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000006 */
16101 #define SPI_I2SCFGR_DATLEN SPI_I2SCFGR_DATLEN_Msk /*!<DATLEN[1:0] bits (Data length to be transferred) */
16102 #define SPI_I2SCFGR_DATLEN_0 (0x1U << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000002 */
16103 #define SPI_I2SCFGR_DATLEN_1 (0x2U << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000004 */
16104
16105 #define SPI_I2SCFGR_CKPOL_Pos (3U)
16106 #define SPI_I2SCFGR_CKPOL_Msk (0x1U << SPI_I2SCFGR_CKPOL_Pos) /*!< 0x00000008 */
16107 #define SPI_I2SCFGR_CKPOL SPI_I2SCFGR_CKPOL_Msk /*!<steady state clock polarity */
16108
16109 #define SPI_I2SCFGR_I2SSTD_Pos (4U)
16110 #define SPI_I2SCFGR_I2SSTD_Msk (0x3U << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000030 */
16111 #define SPI_I2SCFGR_I2SSTD SPI_I2SCFGR_I2SSTD_Msk /*!<I2SSTD[1:0] bits (I2S standard selection) */
16112 #define SPI_I2SCFGR_I2SSTD_0 (0x1U << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000010 */
16113 #define SPI_I2SCFGR_I2SSTD_1 (0x2U << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000020 */
16114
16115 #define SPI_I2SCFGR_PCMSYNC_Pos (7U)
16116 #define SPI_I2SCFGR_PCMSYNC_Msk (0x1U << SPI_I2SCFGR_PCMSYNC_Pos) /*!< 0x00000080 */
16117 #define SPI_I2SCFGR_PCMSYNC SPI_I2SCFGR_PCMSYNC_Msk /*!<PCM frame synchronization */
16118
16119 #define SPI_I2SCFGR_I2SCFG_Pos (8U)
16120 #define SPI_I2SCFGR_I2SCFG_Msk (0x3U << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000300 */
16121 #define SPI_I2SCFGR_I2SCFG SPI_I2SCFGR_I2SCFG_Msk /*!<I2SCFG[1:0] bits (I2S configuration mode) */
16122 #define SPI_I2SCFGR_I2SCFG_0 (0x1U << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000100 */
16123 #define SPI_I2SCFGR_I2SCFG_1 (0x2U << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000200 */
16124
16125 #define SPI_I2SCFGR_I2SE_Pos (10U)
16126 #define SPI_I2SCFGR_I2SE_Msk (0x1U << SPI_I2SCFGR_I2SE_Pos) /*!< 0x00000400 */
16127 #define SPI_I2SCFGR_I2SE SPI_I2SCFGR_I2SE_Msk /*!<I2S Enable */
16128 #define SPI_I2SCFGR_I2SMOD_Pos (11U)
16129 #define SPI_I2SCFGR_I2SMOD_Msk (0x1U << SPI_I2SCFGR_I2SMOD_Pos) /*!< 0x00000800 */
16130 #define SPI_I2SCFGR_I2SMOD SPI_I2SCFGR_I2SMOD_Msk /*!<I2S mode selection */
16131 #define SPI_I2SCFGR_ASTRTEN_Pos (12U)
16132 #define SPI_I2SCFGR_ASTRTEN_Msk (0x1U << SPI_I2SCFGR_ASTRTEN_Pos) /*!< 0x00001000 */
16133 #define SPI_I2SCFGR_ASTRTEN SPI_I2SCFGR_ASTRTEN_Msk /*!<Asynchronous start enable */
16134
16135 /****************** Bit definition for SPI_I2SPR register *******************/
16136 #define SPI_I2SPR_I2SDIV_Pos (0U)
16137 #define SPI_I2SPR_I2SDIV_Msk (0xFFU << SPI_I2SPR_I2SDIV_Pos) /*!< 0x000000FF */
16138 #define SPI_I2SPR_I2SDIV SPI_I2SPR_I2SDIV_Msk /*!<I2S Linear prescaler */
16139 #define SPI_I2SPR_ODD_Pos (8U)
16140 #define SPI_I2SPR_ODD_Msk (0x1U << SPI_I2SPR_ODD_Pos) /*!< 0x00000100 */
16141 #define SPI_I2SPR_ODD SPI_I2SPR_ODD_Msk /*!<Odd factor for the prescaler */
16142 #define SPI_I2SPR_MCKOE_Pos (9U)
16143 #define SPI_I2SPR_MCKOE_Msk (0x1U << SPI_I2SPR_MCKOE_Pos) /*!< 0x00000200 */
16144 #define SPI_I2SPR_MCKOE SPI_I2SPR_MCKOE_Msk /*!<Master Clock Output Enable */
16145
16146 /******************************************************************************/
16147 /* */
16148 /* SYSCFG */
16149 /* */
16150 /******************************************************************************/
16151 /****************** Bit definition for SYSCFG_MEMRMP register ***************/
16152 #define SYSCFG_MEMRMP_MEM_MODE_Pos (0U)
16153 #define SYSCFG_MEMRMP_MEM_MODE_Msk (0x7U << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000007 */
16154 #define SYSCFG_MEMRMP_MEM_MODE SYSCFG_MEMRMP_MEM_MODE_Msk /*!< SYSCFG_Memory Remap Config */
16155 #define SYSCFG_MEMRMP_MEM_MODE_0 (0x1U << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000001 */
16156 #define SYSCFG_MEMRMP_MEM_MODE_1 (0x2U << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000002 */
16157 #define SYSCFG_MEMRMP_MEM_MODE_2 (0x4U << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000004 */
16158 #define SYSCFG_MEMRMP_UFB_MODE_Pos (8U)
16159 #define SYSCFG_MEMRMP_UFB_MODE_Msk (0x1U << SYSCFG_MEMRMP_UFB_MODE_Pos) /*!< 0x00000100 */
16160 #define SYSCFG_MEMRMP_UFB_MODE SYSCFG_MEMRMP_UFB_MODE_Msk /*!< User Flash Bank mode */
16161 #define SYSCFG_MEMRMP_SWP_FMC_Pos (10U)
16162 #define SYSCFG_MEMRMP_SWP_FMC_Msk (0x3U << SYSCFG_MEMRMP_SWP_FMC_Pos) /*!< 0x00000C00 */
16163 #define SYSCFG_MEMRMP_SWP_FMC SYSCFG_MEMRMP_SWP_FMC_Msk /*!< FMC memory mapping swap */
16164 #define SYSCFG_MEMRMP_SWP_FMC_0 (0x1U << SYSCFG_MEMRMP_SWP_FMC_Pos) /*!< 0x00000400 */
16165 /* Legacy Defines */
16166 #define SYSCFG_SWP_FMC SYSCFG_MEMRMP_SWP_FMC
16167 /****************** Bit definition for SYSCFG_PMC register ******************/
16168 #define SYSCFG_PMC_ADCxDC2_Pos (16U)
16169 #define SYSCFG_PMC_ADCxDC2_Msk (0x7U << SYSCFG_PMC_ADCxDC2_Pos) /*!< 0x00070000 */
16170 #define SYSCFG_PMC_ADCxDC2 SYSCFG_PMC_ADCxDC2_Msk /*!< Refer to AN4073 on how to use this bit */
16171 #define SYSCFG_PMC_ADC1DC2_Pos (16U)
16172 #define SYSCFG_PMC_ADC1DC2_Msk (0x1U << SYSCFG_PMC_ADC1DC2_Pos) /*!< 0x00010000 */
16173 #define SYSCFG_PMC_ADC1DC2 SYSCFG_PMC_ADC1DC2_Msk /*!< Refer to AN4073 on how to use this bit */
16174 #define SYSCFG_PMC_ADC2DC2_Pos (17U)
16175 #define SYSCFG_PMC_ADC2DC2_Msk (0x1U << SYSCFG_PMC_ADC2DC2_Pos) /*!< 0x00020000 */
16176 #define SYSCFG_PMC_ADC2DC2 SYSCFG_PMC_ADC2DC2_Msk /*!< Refer to AN4073 on how to use this bit */
16177 #define SYSCFG_PMC_ADC3DC2_Pos (18U)
16178 #define SYSCFG_PMC_ADC3DC2_Msk (0x1U << SYSCFG_PMC_ADC3DC2_Pos) /*!< 0x00040000 */
16179 #define SYSCFG_PMC_ADC3DC2 SYSCFG_PMC_ADC3DC2_Msk /*!< Refer to AN4073 on how to use this bit */
16180 #define SYSCFG_PMC_MII_RMII_SEL_Pos (23U)
16181 #define SYSCFG_PMC_MII_RMII_SEL_Msk (0x1U << SYSCFG_PMC_MII_RMII_SEL_Pos) /*!< 0x00800000 */
16182 #define SYSCFG_PMC_MII_RMII_SEL SYSCFG_PMC_MII_RMII_SEL_Msk /*!<Ethernet PHY interface selection */
16183
16184 /***************** Bit definition for SYSCFG_EXTICR1 register ***************/
16185 #define SYSCFG_EXTICR1_EXTI0_Pos (0U)
16186 #define SYSCFG_EXTICR1_EXTI0_Msk (0xFU << SYSCFG_EXTICR1_EXTI0_Pos) /*!< 0x0000000F */
16187 #define SYSCFG_EXTICR1_EXTI0 SYSCFG_EXTICR1_EXTI0_Msk /*!<EXTI 0 configuration */
16188 #define SYSCFG_EXTICR1_EXTI1_Pos (4U)
16189 #define SYSCFG_EXTICR1_EXTI1_Msk (0xFU << SYSCFG_EXTICR1_EXTI1_Pos) /*!< 0x000000F0 */
16190 #define SYSCFG_EXTICR1_EXTI1 SYSCFG_EXTICR1_EXTI1_Msk /*!<EXTI 1 configuration */
16191 #define SYSCFG_EXTICR1_EXTI2_Pos (8U)
16192 #define SYSCFG_EXTICR1_EXTI2_Msk (0xFU << SYSCFG_EXTICR1_EXTI2_Pos) /*!< 0x00000F00 */
16193 #define SYSCFG_EXTICR1_EXTI2 SYSCFG_EXTICR1_EXTI2_Msk /*!<EXTI 2 configuration */
16194 #define SYSCFG_EXTICR1_EXTI3_Pos (12U)
16195 #define SYSCFG_EXTICR1_EXTI3_Msk (0xFU << SYSCFG_EXTICR1_EXTI3_Pos) /*!< 0x0000F000 */
16196 #define SYSCFG_EXTICR1_EXTI3 SYSCFG_EXTICR1_EXTI3_Msk /*!<EXTI 3 configuration */
16197 /**
16198 * @brief EXTI0 configuration
16199 */
16200 #define SYSCFG_EXTICR1_EXTI0_PA 0x0000U /*!<PA[0] pin */
16201 #define SYSCFG_EXTICR1_EXTI0_PB 0x0001U /*!<PB[0] pin */
16202 #define SYSCFG_EXTICR1_EXTI0_PC 0x0002U /*!<PC[0] pin */
16203 #define SYSCFG_EXTICR1_EXTI0_PD 0x0003U /*!<PD[0] pin */
16204 #define SYSCFG_EXTICR1_EXTI0_PE 0x0004U /*!<PE[0] pin */
16205 #define SYSCFG_EXTICR1_EXTI0_PF 0x0005U /*!<PF[0] pin */
16206 #define SYSCFG_EXTICR1_EXTI0_PG 0x0006U /*!<PG[0] pin */
16207 #define SYSCFG_EXTICR1_EXTI0_PH 0x0007U /*!<PH[0] pin */
16208 #define SYSCFG_EXTICR1_EXTI0_PI 0x0008U /*!<PI[0] pin */
16209 #define SYSCFG_EXTICR1_EXTI0_PJ 0x0009U /*!<PJ[0] pin */
16210 #define SYSCFG_EXTICR1_EXTI0_PK 0x000AU /*!<PK[0] pin */
16211
16212 /**
16213 * @brief EXTI1 configuration
16214 */
16215 #define SYSCFG_EXTICR1_EXTI1_PA 0x0000U /*!<PA[1] pin */
16216 #define SYSCFG_EXTICR1_EXTI1_PB 0x0010U /*!<PB[1] pin */
16217 #define SYSCFG_EXTICR1_EXTI1_PC 0x0020U /*!<PC[1] pin */
16218 #define SYSCFG_EXTICR1_EXTI1_PD 0x0030U /*!<PD[1] pin */
16219 #define SYSCFG_EXTICR1_EXTI1_PE 0x0040U /*!<PE[1] pin */
16220 #define SYSCFG_EXTICR1_EXTI1_PF 0x0050U /*!<PF[1] pin */
16221 #define SYSCFG_EXTICR1_EXTI1_PG 0x0060U /*!<PG[1] pin */
16222 #define SYSCFG_EXTICR1_EXTI1_PH 0x0070U /*!<PH[1] pin */
16223 #define SYSCFG_EXTICR1_EXTI1_PI 0x0080U /*!<PI[1] pin */
16224 #define SYSCFG_EXTICR1_EXTI1_PJ 0x0090U /*!<PJ[1] pin */
16225 #define SYSCFG_EXTICR1_EXTI1_PK 0x00A0U /*!<PK[1] pin */
16226
16227 /**
16228 * @brief EXTI2 configuration
16229 */
16230 #define SYSCFG_EXTICR1_EXTI2_PA 0x0000U /*!<PA[2] pin */
16231 #define SYSCFG_EXTICR1_EXTI2_PB 0x0100U /*!<PB[2] pin */
16232 #define SYSCFG_EXTICR1_EXTI2_PC 0x0200U /*!<PC[2] pin */
16233 #define SYSCFG_EXTICR1_EXTI2_PD 0x0300U /*!<PD[2] pin */
16234 #define SYSCFG_EXTICR1_EXTI2_PE 0x0400U /*!<PE[2] pin */
16235 #define SYSCFG_EXTICR1_EXTI2_PF 0x0500U /*!<PF[2] pin */
16236 #define SYSCFG_EXTICR1_EXTI2_PG 0x0600U /*!<PG[2] pin */
16237 #define SYSCFG_EXTICR1_EXTI2_PH 0x0700U /*!<PH[2] pin */
16238 #define SYSCFG_EXTICR1_EXTI2_PI 0x0800U /*!<PI[2] pin */
16239 #define SYSCFG_EXTICR1_EXTI2_PJ 0x0900U /*!<PJ[2] pin */
16240 #define SYSCFG_EXTICR1_EXTI2_PK 0x0A00U /*!<PK[2] pin */
16241
16242 /**
16243 * @brief EXTI3 configuration
16244 */
16245 #define SYSCFG_EXTICR1_EXTI3_PA 0x0000U /*!<PA[3] pin */
16246 #define SYSCFG_EXTICR1_EXTI3_PB 0x1000U /*!<PB[3] pin */
16247 #define SYSCFG_EXTICR1_EXTI3_PC 0x2000U /*!<PC[3] pin */
16248 #define SYSCFG_EXTICR1_EXTI3_PD 0x3000U /*!<PD[3] pin */
16249 #define SYSCFG_EXTICR1_EXTI3_PE 0x4000U /*!<PE[3] pin */
16250 #define SYSCFG_EXTICR1_EXTI3_PF 0x5000U /*!<PF[3] pin */
16251 #define SYSCFG_EXTICR1_EXTI3_PG 0x6000U /*!<PG[3] pin */
16252 #define SYSCFG_EXTICR1_EXTI3_PH 0x7000U /*!<PH[3] pin */
16253 #define SYSCFG_EXTICR1_EXTI3_PI 0x8000U /*!<PI[3] pin */
16254 #define SYSCFG_EXTICR1_EXTI3_PJ 0x9000U /*!<PJ[3] pin */
16255 #define SYSCFG_EXTICR1_EXTI3_PK 0xA000U /*!<PK[3] pin */
16256
16257 /***************** Bit definition for SYSCFG_EXTICR2 register ***************/
16258 #define SYSCFG_EXTICR2_EXTI4_Pos (0U)
16259 #define SYSCFG_EXTICR2_EXTI4_Msk (0xFU << SYSCFG_EXTICR2_EXTI4_Pos) /*!< 0x0000000F */
16260 #define SYSCFG_EXTICR2_EXTI4 SYSCFG_EXTICR2_EXTI4_Msk /*!<EXTI 4 configuration */
16261 #define SYSCFG_EXTICR2_EXTI5_Pos (4U)
16262 #define SYSCFG_EXTICR2_EXTI5_Msk (0xFU << SYSCFG_EXTICR2_EXTI5_Pos) /*!< 0x000000F0 */
16263 #define SYSCFG_EXTICR2_EXTI5 SYSCFG_EXTICR2_EXTI5_Msk /*!<EXTI 5 configuration */
16264 #define SYSCFG_EXTICR2_EXTI6_Pos (8U)
16265 #define SYSCFG_EXTICR2_EXTI6_Msk (0xFU << SYSCFG_EXTICR2_EXTI6_Pos) /*!< 0x00000F00 */
16266 #define SYSCFG_EXTICR2_EXTI6 SYSCFG_EXTICR2_EXTI6_Msk /*!<EXTI 6 configuration */
16267 #define SYSCFG_EXTICR2_EXTI7_Pos (12U)
16268 #define SYSCFG_EXTICR2_EXTI7_Msk (0xFU << SYSCFG_EXTICR2_EXTI7_Pos) /*!< 0x0000F000 */
16269 #define SYSCFG_EXTICR2_EXTI7 SYSCFG_EXTICR2_EXTI7_Msk /*!<EXTI 7 configuration */
16270
16271 /**
16272 * @brief EXTI4 configuration
16273 */
16274 #define SYSCFG_EXTICR2_EXTI4_PA 0x0000U /*!<PA[4] pin */
16275 #define SYSCFG_EXTICR2_EXTI4_PB 0x0001U /*!<PB[4] pin */
16276 #define SYSCFG_EXTICR2_EXTI4_PC 0x0002U /*!<PC[4] pin */
16277 #define SYSCFG_EXTICR2_EXTI4_PD 0x0003U /*!<PD[4] pin */
16278 #define SYSCFG_EXTICR2_EXTI4_PE 0x0004U /*!<PE[4] pin */
16279 #define SYSCFG_EXTICR2_EXTI4_PF 0x0005U /*!<PF[4] pin */
16280 #define SYSCFG_EXTICR2_EXTI4_PG 0x0006U /*!<PG[4] pin */
16281 #define SYSCFG_EXTICR2_EXTI4_PH 0x0007U /*!<PH[4] pin */
16282 #define SYSCFG_EXTICR2_EXTI4_PI 0x0008U /*!<PI[4] pin */
16283 #define SYSCFG_EXTICR2_EXTI4_PJ 0x0009U /*!<PJ[4] pin */
16284 #define SYSCFG_EXTICR2_EXTI4_PK 0x000AU /*!<PK[4] pin */
16285
16286 /**
16287 * @brief EXTI5 configuration
16288 */
16289 #define SYSCFG_EXTICR2_EXTI5_PA 0x0000U /*!<PA[5] pin */
16290 #define SYSCFG_EXTICR2_EXTI5_PB 0x0010U /*!<PB[5] pin */
16291 #define SYSCFG_EXTICR2_EXTI5_PC 0x0020U /*!<PC[5] pin */
16292 #define SYSCFG_EXTICR2_EXTI5_PD 0x0030U /*!<PD[5] pin */
16293 #define SYSCFG_EXTICR2_EXTI5_PE 0x0040U /*!<PE[5] pin */
16294 #define SYSCFG_EXTICR2_EXTI5_PF 0x0050U /*!<PF[5] pin */
16295 #define SYSCFG_EXTICR2_EXTI5_PG 0x0060U /*!<PG[5] pin */
16296 #define SYSCFG_EXTICR2_EXTI5_PH 0x0070U /*!<PH[5] pin */
16297 #define SYSCFG_EXTICR2_EXTI5_PI 0x0080U /*!<PI[5] pin */
16298 #define SYSCFG_EXTICR2_EXTI5_PJ 0x0090U /*!<PJ[5] pin */
16299 #define SYSCFG_EXTICR2_EXTI5_PK 0x00A0U /*!<PK[5] pin */
16300
16301 /**
16302 * @brief EXTI6 configuration
16303 */
16304 #define SYSCFG_EXTICR2_EXTI6_PA 0x0000U /*!<PA[6] pin */
16305 #define SYSCFG_EXTICR2_EXTI6_PB 0x0100U /*!<PB[6] pin */
16306 #define SYSCFG_EXTICR2_EXTI6_PC 0x0200U /*!<PC[6] pin */
16307 #define SYSCFG_EXTICR2_EXTI6_PD 0x0300U /*!<PD[6] pin */
16308 #define SYSCFG_EXTICR2_EXTI6_PE 0x0400U /*!<PE[6] pin */
16309 #define SYSCFG_EXTICR2_EXTI6_PF 0x0500U /*!<PF[6] pin */
16310 #define SYSCFG_EXTICR2_EXTI6_PG 0x0600U /*!<PG[6] pin */
16311 #define SYSCFG_EXTICR2_EXTI6_PH 0x0700U /*!<PH[6] pin */
16312 #define SYSCFG_EXTICR2_EXTI6_PI 0x0800U /*!<PI[6] pin */
16313 #define SYSCFG_EXTICR2_EXTI6_PJ 0x0900U /*!<PJ[6] pin */
16314 #define SYSCFG_EXTICR2_EXTI6_PK 0x0A00U /*!<PK[6] pin */
16315
16316 /**
16317 * @brief EXTI7 configuration
16318 */
16319 #define SYSCFG_EXTICR2_EXTI7_PA 0x0000U /*!<PA[7] pin */
16320 #define SYSCFG_EXTICR2_EXTI7_PB 0x1000U /*!<PB[7] pin */
16321 #define SYSCFG_EXTICR2_EXTI7_PC 0x2000U /*!<PC[7] pin */
16322 #define SYSCFG_EXTICR2_EXTI7_PD 0x3000U /*!<PD[7] pin */
16323 #define SYSCFG_EXTICR2_EXTI7_PE 0x4000U /*!<PE[7] pin */
16324 #define SYSCFG_EXTICR2_EXTI7_PF 0x5000U /*!<PF[7] pin */
16325 #define SYSCFG_EXTICR2_EXTI7_PG 0x6000U /*!<PG[7] pin */
16326 #define SYSCFG_EXTICR2_EXTI7_PH 0x7000U /*!<PH[7] pin */
16327 #define SYSCFG_EXTICR2_EXTI7_PI 0x8000U /*!<PI[7] pin */
16328 #define SYSCFG_EXTICR2_EXTI7_PJ 0x9000U /*!<PJ[7] pin */
16329 #define SYSCFG_EXTICR2_EXTI7_PK 0xA000U /*!<PK[7] pin */
16330
16331 /***************** Bit definition for SYSCFG_EXTICR3 register ***************/
16332 #define SYSCFG_EXTICR3_EXTI8_Pos (0U)
16333 #define SYSCFG_EXTICR3_EXTI8_Msk (0xFU << SYSCFG_EXTICR3_EXTI8_Pos) /*!< 0x0000000F */
16334 #define SYSCFG_EXTICR3_EXTI8 SYSCFG_EXTICR3_EXTI8_Msk /*!<EXTI 8 configuration */
16335 #define SYSCFG_EXTICR3_EXTI9_Pos (4U)
16336 #define SYSCFG_EXTICR3_EXTI9_Msk (0xFU << SYSCFG_EXTICR3_EXTI9_Pos) /*!< 0x000000F0 */
16337 #define SYSCFG_EXTICR3_EXTI9 SYSCFG_EXTICR3_EXTI9_Msk /*!<EXTI 9 configuration */
16338 #define SYSCFG_EXTICR3_EXTI10_Pos (8U)
16339 #define SYSCFG_EXTICR3_EXTI10_Msk (0xFU << SYSCFG_EXTICR3_EXTI10_Pos) /*!< 0x00000F00 */
16340 #define SYSCFG_EXTICR3_EXTI10 SYSCFG_EXTICR3_EXTI10_Msk /*!<EXTI 10 configuration */
16341 #define SYSCFG_EXTICR3_EXTI11_Pos (12U)
16342 #define SYSCFG_EXTICR3_EXTI11_Msk (0xFU << SYSCFG_EXTICR3_EXTI11_Pos) /*!< 0x0000F000 */
16343 #define SYSCFG_EXTICR3_EXTI11 SYSCFG_EXTICR3_EXTI11_Msk /*!<EXTI 11 configuration */
16344
16345 /**
16346 * @brief EXTI8 configuration
16347 */
16348 #define SYSCFG_EXTICR3_EXTI8_PA 0x0000U /*!<PA[8] pin */
16349 #define SYSCFG_EXTICR3_EXTI8_PB 0x0001U /*!<PB[8] pin */
16350 #define SYSCFG_EXTICR3_EXTI8_PC 0x0002U /*!<PC[8] pin */
16351 #define SYSCFG_EXTICR3_EXTI8_PD 0x0003U /*!<PD[8] pin */
16352 #define SYSCFG_EXTICR3_EXTI8_PE 0x0004U /*!<PE[8] pin */
16353 #define SYSCFG_EXTICR3_EXTI8_PF 0x0005U /*!<PF[8] pin */
16354 #define SYSCFG_EXTICR3_EXTI8_PG 0x0006U /*!<PG[8] pin */
16355 #define SYSCFG_EXTICR3_EXTI8_PH 0x0007U /*!<PH[8] pin */
16356 #define SYSCFG_EXTICR3_EXTI8_PI 0x0008U /*!<PI[8] pin */
16357 #define SYSCFG_EXTICR3_EXTI8_PJ 0x0009U /*!<PJ[8] pin */
16358
16359 /**
16360 * @brief EXTI9 configuration
16361 */
16362 #define SYSCFG_EXTICR3_EXTI9_PA 0x0000U /*!<PA[9] pin */
16363 #define SYSCFG_EXTICR3_EXTI9_PB 0x0010U /*!<PB[9] pin */
16364 #define SYSCFG_EXTICR3_EXTI9_PC 0x0020U /*!<PC[9] pin */
16365 #define SYSCFG_EXTICR3_EXTI9_PD 0x0030U /*!<PD[9] pin */
16366 #define SYSCFG_EXTICR3_EXTI9_PE 0x0040U /*!<PE[9] pin */
16367 #define SYSCFG_EXTICR3_EXTI9_PF 0x0050U /*!<PF[9] pin */
16368 #define SYSCFG_EXTICR3_EXTI9_PG 0x0060U /*!<PG[9] pin */
16369 #define SYSCFG_EXTICR3_EXTI9_PH 0x0070U /*!<PH[9] pin */
16370 #define SYSCFG_EXTICR3_EXTI9_PI 0x0080U /*!<PI[9] pin */
16371 #define SYSCFG_EXTICR3_EXTI9_PJ 0x0090U /*!<PJ[9] pin */
16372
16373 /**
16374 * @brief EXTI10 configuration
16375 */
16376 #define SYSCFG_EXTICR3_EXTI10_PA 0x0000U /*!<PA[10] pin */
16377 #define SYSCFG_EXTICR3_EXTI10_PB 0x0100U /*!<PB[10] pin */
16378 #define SYSCFG_EXTICR3_EXTI10_PC 0x0200U /*!<PC[10] pin */
16379 #define SYSCFG_EXTICR3_EXTI10_PD 0x0300U /*!<PD[10] pin */
16380 #define SYSCFG_EXTICR3_EXTI10_PE 0x0400U /*!<PE[10] pin */
16381 #define SYSCFG_EXTICR3_EXTI10_PF 0x0500U /*!<PF[10] pin */
16382 #define SYSCFG_EXTICR3_EXTI10_PG 0x0600U /*!<PG[10] pin */
16383 #define SYSCFG_EXTICR3_EXTI10_PH 0x0700U /*!<PH[10] pin */
16384 #define SYSCFG_EXTICR3_EXTI10_PI 0x0800U /*!<PI[10] pin */
16385 #define SYSCFG_EXTICR3_EXTI10_PJ 0x0900U /*!<PJ[10] pin */
16386
16387 /**
16388 * @brief EXTI11 configuration
16389 */
16390 #define SYSCFG_EXTICR3_EXTI11_PA 0x0000U /*!<PA[11] pin */
16391 #define SYSCFG_EXTICR3_EXTI11_PB 0x1000U /*!<PB[11] pin */
16392 #define SYSCFG_EXTICR3_EXTI11_PC 0x2000U /*!<PC[11] pin */
16393 #define SYSCFG_EXTICR3_EXTI11_PD 0x3000U /*!<PD[11] pin */
16394 #define SYSCFG_EXTICR3_EXTI11_PE 0x4000U /*!<PE[11] pin */
16395 #define SYSCFG_EXTICR3_EXTI11_PF 0x5000U /*!<PF[11] pin */
16396 #define SYSCFG_EXTICR3_EXTI11_PG 0x6000U /*!<PG[11] pin */
16397 #define SYSCFG_EXTICR3_EXTI11_PH 0x7000U /*!<PH[11] pin */
16398 #define SYSCFG_EXTICR3_EXTI11_PI 0x8000U /*!<PI[11] pin */
16399 #define SYSCFG_EXTICR3_EXTI11_PJ 0x9000U /*!<PJ[11] pin */
16400
16401
16402 /***************** Bit definition for SYSCFG_EXTICR4 register ***************/
16403 #define SYSCFG_EXTICR4_EXTI12_Pos (0U)
16404 #define SYSCFG_EXTICR4_EXTI12_Msk (0xFU << SYSCFG_EXTICR4_EXTI12_Pos) /*!< 0x0000000F */
16405 #define SYSCFG_EXTICR4_EXTI12 SYSCFG_EXTICR4_EXTI12_Msk /*!<EXTI 12 configuration */
16406 #define SYSCFG_EXTICR4_EXTI13_Pos (4U)
16407 #define SYSCFG_EXTICR4_EXTI13_Msk (0xFU << SYSCFG_EXTICR4_EXTI13_Pos) /*!< 0x000000F0 */
16408 #define SYSCFG_EXTICR4_EXTI13 SYSCFG_EXTICR4_EXTI13_Msk /*!<EXTI 13 configuration */
16409 #define SYSCFG_EXTICR4_EXTI14_Pos (8U)
16410 #define SYSCFG_EXTICR4_EXTI14_Msk (0xFU << SYSCFG_EXTICR4_EXTI14_Pos) /*!< 0x00000F00 */
16411 #define SYSCFG_EXTICR4_EXTI14 SYSCFG_EXTICR4_EXTI14_Msk /*!<EXTI 14 configuration */
16412 #define SYSCFG_EXTICR4_EXTI15_Pos (12U)
16413 #define SYSCFG_EXTICR4_EXTI15_Msk (0xFU << SYSCFG_EXTICR4_EXTI15_Pos) /*!< 0x0000F000 */
16414 #define SYSCFG_EXTICR4_EXTI15 SYSCFG_EXTICR4_EXTI15_Msk /*!<EXTI 15 configuration */
16415
16416 /**
16417 * @brief EXTI12 configuration
16418 */
16419 #define SYSCFG_EXTICR4_EXTI12_PA 0x0000U /*!<PA[12] pin */
16420 #define SYSCFG_EXTICR4_EXTI12_PB 0x0001U /*!<PB[12] pin */
16421 #define SYSCFG_EXTICR4_EXTI12_PC 0x0002U /*!<PC[12] pin */
16422 #define SYSCFG_EXTICR4_EXTI12_PD 0x0003U /*!<PD[12] pin */
16423 #define SYSCFG_EXTICR4_EXTI12_PE 0x0004U /*!<PE[12] pin */
16424 #define SYSCFG_EXTICR4_EXTI12_PF 0x0005U /*!<PF[12] pin */
16425 #define SYSCFG_EXTICR4_EXTI12_PG 0x0006U /*!<PG[12] pin */
16426 #define SYSCFG_EXTICR4_EXTI12_PH 0x0007U /*!<PH[12] pin */
16427 #define SYSCFG_EXTICR4_EXTI12_PI 0x0008U /*!<PI[12] pin */
16428 #define SYSCFG_EXTICR4_EXTI12_PJ 0x0009U /*!<PJ[12] pin */
16429
16430 /**
16431 * @brief EXTI13 configuration
16432 */
16433 #define SYSCFG_EXTICR4_EXTI13_PA 0x0000U /*!<PA[13] pin */
16434 #define SYSCFG_EXTICR4_EXTI13_PB 0x0010U /*!<PB[13] pin */
16435 #define SYSCFG_EXTICR4_EXTI13_PC 0x0020U /*!<PC[13] pin */
16436 #define SYSCFG_EXTICR4_EXTI13_PD 0x0030U /*!<PD[13] pin */
16437 #define SYSCFG_EXTICR4_EXTI13_PE 0x0040U /*!<PE[13] pin */
16438 #define SYSCFG_EXTICR4_EXTI13_PF 0x0050U /*!<PF[13] pin */
16439 #define SYSCFG_EXTICR4_EXTI13_PG 0x0060U /*!<PG[13] pin */
16440 #define SYSCFG_EXTICR4_EXTI13_PH 0x0070U /*!<PH[13] pin */
16441 #define SYSCFG_EXTICR4_EXTI13_PI 0x0008U /*!<PI[13] pin */
16442 #define SYSCFG_EXTICR4_EXTI13_PJ 0x0009U /*!<PJ[13] pin */
16443
16444 /**
16445 * @brief EXTI14 configuration
16446 */
16447 #define SYSCFG_EXTICR4_EXTI14_PA 0x0000U /*!<PA[14] pin */
16448 #define SYSCFG_EXTICR4_EXTI14_PB 0x0100U /*!<PB[14] pin */
16449 #define SYSCFG_EXTICR4_EXTI14_PC 0x0200U /*!<PC[14] pin */
16450 #define SYSCFG_EXTICR4_EXTI14_PD 0x0300U /*!<PD[14] pin */
16451 #define SYSCFG_EXTICR4_EXTI14_PE 0x0400U /*!<PE[14] pin */
16452 #define SYSCFG_EXTICR4_EXTI14_PF 0x0500U /*!<PF[14] pin */
16453 #define SYSCFG_EXTICR4_EXTI14_PG 0x0600U /*!<PG[14] pin */
16454 #define SYSCFG_EXTICR4_EXTI14_PH 0x0700U /*!<PH[14] pin */
16455 #define SYSCFG_EXTICR4_EXTI14_PI 0x0800U /*!<PI[14] pin */
16456 #define SYSCFG_EXTICR4_EXTI14_PJ 0x0900U /*!<PJ[14] pin */
16457
16458 /**
16459 * @brief EXTI15 configuration
16460 */
16461 #define SYSCFG_EXTICR4_EXTI15_PA 0x0000U /*!<PA[15] pin */
16462 #define SYSCFG_EXTICR4_EXTI15_PB 0x1000U /*!<PB[15] pin */
16463 #define SYSCFG_EXTICR4_EXTI15_PC 0x2000U /*!<PC[15] pin */
16464 #define SYSCFG_EXTICR4_EXTI15_PD 0x3000U /*!<PD[15] pin */
16465 #define SYSCFG_EXTICR4_EXTI15_PE 0x4000U /*!<PE[15] pin */
16466 #define SYSCFG_EXTICR4_EXTI15_PF 0x5000U /*!<PF[15] pin */
16467 #define SYSCFG_EXTICR4_EXTI15_PG 0x6000U /*!<PG[15] pin */
16468 #define SYSCFG_EXTICR4_EXTI15_PH 0x7000U /*!<PH[15] pin */
16469 #define SYSCFG_EXTICR4_EXTI15_PI 0x8000U /*!<PI[15] pin */
16470 #define SYSCFG_EXTICR4_EXTI15_PJ 0x9000U /*!<PJ[15] pin */
16471
16472 /****************** Bit definition for SYSCFG_CMPCR register ****************/
16473 #define SYSCFG_CMPCR_CMP_PD_Pos (0U)
16474 #define SYSCFG_CMPCR_CMP_PD_Msk (0x1U << SYSCFG_CMPCR_CMP_PD_Pos) /*!< 0x00000001 */
16475 #define SYSCFG_CMPCR_CMP_PD SYSCFG_CMPCR_CMP_PD_Msk /*!<Compensation cell ready flag */
16476 #define SYSCFG_CMPCR_READY_Pos (8U)
16477 #define SYSCFG_CMPCR_READY_Msk (0x1U << SYSCFG_CMPCR_READY_Pos) /*!< 0x00000100 */
16478 #define SYSCFG_CMPCR_READY SYSCFG_CMPCR_READY_Msk /*!<Compensation cell power-down */
16479
16480 /******************************************************************************/
16481 /* */
16482 /* TIM */
16483 /* */
16484 /******************************************************************************/
16485 /******************* Bit definition for TIM_CR1 register ********************/
16486 #define TIM_CR1_CEN_Pos (0U)
16487 #define TIM_CR1_CEN_Msk (0x1U << TIM_CR1_CEN_Pos) /*!< 0x00000001 */
16488 #define TIM_CR1_CEN TIM_CR1_CEN_Msk /*!<Counter enable */
16489 #define TIM_CR1_UDIS_Pos (1U)
16490 #define TIM_CR1_UDIS_Msk (0x1U << TIM_CR1_UDIS_Pos) /*!< 0x00000002 */
16491 #define TIM_CR1_UDIS TIM_CR1_UDIS_Msk /*!<Update disable */
16492 #define TIM_CR1_URS_Pos (2U)
16493 #define TIM_CR1_URS_Msk (0x1U << TIM_CR1_URS_Pos) /*!< 0x00000004 */
16494 #define TIM_CR1_URS TIM_CR1_URS_Msk /*!<Update request source */
16495 #define TIM_CR1_OPM_Pos (3U)
16496 #define TIM_CR1_OPM_Msk (0x1U << TIM_CR1_OPM_Pos) /*!< 0x00000008 */
16497 #define TIM_CR1_OPM TIM_CR1_OPM_Msk /*!<One pulse mode */
16498 #define TIM_CR1_DIR_Pos (4U)
16499 #define TIM_CR1_DIR_Msk (0x1U << TIM_CR1_DIR_Pos) /*!< 0x00000010 */
16500 #define TIM_CR1_DIR TIM_CR1_DIR_Msk /*!<Direction */
16501
16502 #define TIM_CR1_CMS_Pos (5U)
16503 #define TIM_CR1_CMS_Msk (0x3U << TIM_CR1_CMS_Pos) /*!< 0x00000060 */
16504 #define TIM_CR1_CMS TIM_CR1_CMS_Msk /*!<CMS[1:0] bits (Center-aligned mode selection) */
16505 #define TIM_CR1_CMS_0 (0x1U << TIM_CR1_CMS_Pos) /*!< 0x0020 */
16506 #define TIM_CR1_CMS_1 (0x2U << TIM_CR1_CMS_Pos) /*!< 0x0040 */
16507
16508 #define TIM_CR1_ARPE_Pos (7U)
16509 #define TIM_CR1_ARPE_Msk (0x1U << TIM_CR1_ARPE_Pos) /*!< 0x00000080 */
16510 #define TIM_CR1_ARPE TIM_CR1_ARPE_Msk /*!<Auto-reload preload enable */
16511
16512 #define TIM_CR1_CKD_Pos (8U)
16513 #define TIM_CR1_CKD_Msk (0x3U << TIM_CR1_CKD_Pos) /*!< 0x00000300 */
16514 #define TIM_CR1_CKD TIM_CR1_CKD_Msk /*!<CKD[1:0] bits (clock division) */
16515 #define TIM_CR1_CKD_0 (0x1U << TIM_CR1_CKD_Pos) /*!< 0x0100 */
16516 #define TIM_CR1_CKD_1 (0x2U << TIM_CR1_CKD_Pos) /*!< 0x0200 */
16517
16518 /******************* Bit definition for TIM_CR2 register ********************/
16519 #define TIM_CR2_CCPC_Pos (0U)
16520 #define TIM_CR2_CCPC_Msk (0x1U << TIM_CR2_CCPC_Pos) /*!< 0x00000001 */
16521 #define TIM_CR2_CCPC TIM_CR2_CCPC_Msk /*!<Capture/Compare Preloaded Control */
16522 #define TIM_CR2_CCUS_Pos (2U)
16523 #define TIM_CR2_CCUS_Msk (0x1U << TIM_CR2_CCUS_Pos) /*!< 0x00000004 */
16524 #define TIM_CR2_CCUS TIM_CR2_CCUS_Msk /*!<Capture/Compare Control Update Selection */
16525 #define TIM_CR2_CCDS_Pos (3U)
16526 #define TIM_CR2_CCDS_Msk (0x1U << TIM_CR2_CCDS_Pos) /*!< 0x00000008 */
16527 #define TIM_CR2_CCDS TIM_CR2_CCDS_Msk /*!<Capture/Compare DMA Selection */
16528
16529 #define TIM_CR2_MMS_Pos (4U)
16530 #define TIM_CR2_MMS_Msk (0x7U << TIM_CR2_MMS_Pos) /*!< 0x00000070 */
16531 #define TIM_CR2_MMS TIM_CR2_MMS_Msk /*!<MMS[2:0] bits (Master Mode Selection) */
16532 #define TIM_CR2_MMS_0 (0x1U << TIM_CR2_MMS_Pos) /*!< 0x0010 */
16533 #define TIM_CR2_MMS_1 (0x2U << TIM_CR2_MMS_Pos) /*!< 0x0020 */
16534 #define TIM_CR2_MMS_2 (0x4U << TIM_CR2_MMS_Pos) /*!< 0x0040 */
16535
16536 #define TIM_CR2_TI1S_Pos (7U)
16537 #define TIM_CR2_TI1S_Msk (0x1U << TIM_CR2_TI1S_Pos) /*!< 0x00000080 */
16538 #define TIM_CR2_TI1S TIM_CR2_TI1S_Msk /*!<TI1 Selection */
16539 #define TIM_CR2_OIS1_Pos (8U)
16540 #define TIM_CR2_OIS1_Msk (0x1U << TIM_CR2_OIS1_Pos) /*!< 0x00000100 */
16541 #define TIM_CR2_OIS1 TIM_CR2_OIS1_Msk /*!<Output Idle state 1 (OC1 output) */
16542 #define TIM_CR2_OIS1N_Pos (9U)
16543 #define TIM_CR2_OIS1N_Msk (0x1U << TIM_CR2_OIS1N_Pos) /*!< 0x00000200 */
16544 #define TIM_CR2_OIS1N TIM_CR2_OIS1N_Msk /*!<Output Idle state 1 (OC1N output) */
16545 #define TIM_CR2_OIS2_Pos (10U)
16546 #define TIM_CR2_OIS2_Msk (0x1U << TIM_CR2_OIS2_Pos) /*!< 0x00000400 */
16547 #define TIM_CR2_OIS2 TIM_CR2_OIS2_Msk /*!<Output Idle state 2 (OC2 output) */
16548 #define TIM_CR2_OIS2N_Pos (11U)
16549 #define TIM_CR2_OIS2N_Msk (0x1U << TIM_CR2_OIS2N_Pos) /*!< 0x00000800 */
16550 #define TIM_CR2_OIS2N TIM_CR2_OIS2N_Msk /*!<Output Idle state 2 (OC2N output) */
16551 #define TIM_CR2_OIS3_Pos (12U)
16552 #define TIM_CR2_OIS3_Msk (0x1U << TIM_CR2_OIS3_Pos) /*!< 0x00001000 */
16553 #define TIM_CR2_OIS3 TIM_CR2_OIS3_Msk /*!<Output Idle state 3 (OC3 output) */
16554 #define TIM_CR2_OIS3N_Pos (13U)
16555 #define TIM_CR2_OIS3N_Msk (0x1U << TIM_CR2_OIS3N_Pos) /*!< 0x00002000 */
16556 #define TIM_CR2_OIS3N TIM_CR2_OIS3N_Msk /*!<Output Idle state 3 (OC3N output) */
16557 #define TIM_CR2_OIS4_Pos (14U)
16558 #define TIM_CR2_OIS4_Msk (0x1U << TIM_CR2_OIS4_Pos) /*!< 0x00004000 */
16559 #define TIM_CR2_OIS4 TIM_CR2_OIS4_Msk /*!<Output Idle state 4 (OC4 output) */
16560
16561 /******************* Bit definition for TIM_SMCR register *******************/
16562 #define TIM_SMCR_SMS_Pos (0U)
16563 #define TIM_SMCR_SMS_Msk (0x7U << TIM_SMCR_SMS_Pos) /*!< 0x00000007 */
16564 #define TIM_SMCR_SMS TIM_SMCR_SMS_Msk /*!<SMS[2:0] bits (Slave mode selection) */
16565 #define TIM_SMCR_SMS_0 (0x1U << TIM_SMCR_SMS_Pos) /*!< 0x0001 */
16566 #define TIM_SMCR_SMS_1 (0x2U << TIM_SMCR_SMS_Pos) /*!< 0x0002 */
16567 #define TIM_SMCR_SMS_2 (0x4U << TIM_SMCR_SMS_Pos) /*!< 0x0004 */
16568
16569 #define TIM_SMCR_TS_Pos (4U)
16570 #define TIM_SMCR_TS_Msk (0x7U << TIM_SMCR_TS_Pos) /*!< 0x00000070 */
16571 #define TIM_SMCR_TS TIM_SMCR_TS_Msk /*!<TS[2:0] bits (Trigger selection) */
16572 #define TIM_SMCR_TS_0 (0x1U << TIM_SMCR_TS_Pos) /*!< 0x0010 */
16573 #define TIM_SMCR_TS_1 (0x2U << TIM_SMCR_TS_Pos) /*!< 0x0020 */
16574 #define TIM_SMCR_TS_2 (0x4U << TIM_SMCR_TS_Pos) /*!< 0x0040 */
16575
16576 #define TIM_SMCR_MSM_Pos (7U)
16577 #define TIM_SMCR_MSM_Msk (0x1U << TIM_SMCR_MSM_Pos) /*!< 0x00000080 */
16578 #define TIM_SMCR_MSM TIM_SMCR_MSM_Msk /*!<Master/slave mode */
16579
16580 #define TIM_SMCR_ETF_Pos (8U)
16581 #define TIM_SMCR_ETF_Msk (0xFU << TIM_SMCR_ETF_Pos) /*!< 0x00000F00 */
16582 #define TIM_SMCR_ETF TIM_SMCR_ETF_Msk /*!<ETF[3:0] bits (External trigger filter) */
16583 #define TIM_SMCR_ETF_0 (0x1U << TIM_SMCR_ETF_Pos) /*!< 0x0100 */
16584 #define TIM_SMCR_ETF_1 (0x2U << TIM_SMCR_ETF_Pos) /*!< 0x0200 */
16585 #define TIM_SMCR_ETF_2 (0x4U << TIM_SMCR_ETF_Pos) /*!< 0x0400 */
16586 #define TIM_SMCR_ETF_3 (0x8U << TIM_SMCR_ETF_Pos) /*!< 0x0800 */
16587
16588 #define TIM_SMCR_ETPS_Pos (12U)
16589 #define TIM_SMCR_ETPS_Msk (0x3U << TIM_SMCR_ETPS_Pos) /*!< 0x00003000 */
16590 #define TIM_SMCR_ETPS TIM_SMCR_ETPS_Msk /*!<ETPS[1:0] bits (External trigger prescaler) */
16591 #define TIM_SMCR_ETPS_0 (0x1U << TIM_SMCR_ETPS_Pos) /*!< 0x1000 */
16592 #define TIM_SMCR_ETPS_1 (0x2U << TIM_SMCR_ETPS_Pos) /*!< 0x2000 */
16593
16594 #define TIM_SMCR_ECE_Pos (14U)
16595 #define TIM_SMCR_ECE_Msk (0x1U << TIM_SMCR_ECE_Pos) /*!< 0x00004000 */
16596 #define TIM_SMCR_ECE TIM_SMCR_ECE_Msk /*!<External clock enable */
16597 #define TIM_SMCR_ETP_Pos (15U)
16598 #define TIM_SMCR_ETP_Msk (0x1U << TIM_SMCR_ETP_Pos) /*!< 0x00008000 */
16599 #define TIM_SMCR_ETP TIM_SMCR_ETP_Msk /*!<External trigger polarity */
16600
16601 /******************* Bit definition for TIM_DIER register *******************/
16602 #define TIM_DIER_UIE_Pos (0U)
16603 #define TIM_DIER_UIE_Msk (0x1U << TIM_DIER_UIE_Pos) /*!< 0x00000001 */
16604 #define TIM_DIER_UIE TIM_DIER_UIE_Msk /*!<Update interrupt enable */
16605 #define TIM_DIER_CC1IE_Pos (1U)
16606 #define TIM_DIER_CC1IE_Msk (0x1U << TIM_DIER_CC1IE_Pos) /*!< 0x00000002 */
16607 #define TIM_DIER_CC1IE TIM_DIER_CC1IE_Msk /*!<Capture/Compare 1 interrupt enable */
16608 #define TIM_DIER_CC2IE_Pos (2U)
16609 #define TIM_DIER_CC2IE_Msk (0x1U << TIM_DIER_CC2IE_Pos) /*!< 0x00000004 */
16610 #define TIM_DIER_CC2IE TIM_DIER_CC2IE_Msk /*!<Capture/Compare 2 interrupt enable */
16611 #define TIM_DIER_CC3IE_Pos (3U)
16612 #define TIM_DIER_CC3IE_Msk (0x1U << TIM_DIER_CC3IE_Pos) /*!< 0x00000008 */
16613 #define TIM_DIER_CC3IE TIM_DIER_CC3IE_Msk /*!<Capture/Compare 3 interrupt enable */
16614 #define TIM_DIER_CC4IE_Pos (4U)
16615 #define TIM_DIER_CC4IE_Msk (0x1U << TIM_DIER_CC4IE_Pos) /*!< 0x00000010 */
16616 #define TIM_DIER_CC4IE TIM_DIER_CC4IE_Msk /*!<Capture/Compare 4 interrupt enable */
16617 #define TIM_DIER_COMIE_Pos (5U)
16618 #define TIM_DIER_COMIE_Msk (0x1U << TIM_DIER_COMIE_Pos) /*!< 0x00000020 */
16619 #define TIM_DIER_COMIE TIM_DIER_COMIE_Msk /*!<COM interrupt enable */
16620 #define TIM_DIER_TIE_Pos (6U)
16621 #define TIM_DIER_TIE_Msk (0x1U << TIM_DIER_TIE_Pos) /*!< 0x00000040 */
16622 #define TIM_DIER_TIE TIM_DIER_TIE_Msk /*!<Trigger interrupt enable */
16623 #define TIM_DIER_BIE_Pos (7U)
16624 #define TIM_DIER_BIE_Msk (0x1U << TIM_DIER_BIE_Pos) /*!< 0x00000080 */
16625 #define TIM_DIER_BIE TIM_DIER_BIE_Msk /*!<Break interrupt enable */
16626 #define TIM_DIER_UDE_Pos (8U)
16627 #define TIM_DIER_UDE_Msk (0x1U << TIM_DIER_UDE_Pos) /*!< 0x00000100 */
16628 #define TIM_DIER_UDE TIM_DIER_UDE_Msk /*!<Update DMA request enable */
16629 #define TIM_DIER_CC1DE_Pos (9U)
16630 #define TIM_DIER_CC1DE_Msk (0x1U << TIM_DIER_CC1DE_Pos) /*!< 0x00000200 */
16631 #define TIM_DIER_CC1DE TIM_DIER_CC1DE_Msk /*!<Capture/Compare 1 DMA request enable */
16632 #define TIM_DIER_CC2DE_Pos (10U)
16633 #define TIM_DIER_CC2DE_Msk (0x1U << TIM_DIER_CC2DE_Pos) /*!< 0x00000400 */
16634 #define TIM_DIER_CC2DE TIM_DIER_CC2DE_Msk /*!<Capture/Compare 2 DMA request enable */
16635 #define TIM_DIER_CC3DE_Pos (11U)
16636 #define TIM_DIER_CC3DE_Msk (0x1U << TIM_DIER_CC3DE_Pos) /*!< 0x00000800 */
16637 #define TIM_DIER_CC3DE TIM_DIER_CC3DE_Msk /*!<Capture/Compare 3 DMA request enable */
16638 #define TIM_DIER_CC4DE_Pos (12U)
16639 #define TIM_DIER_CC4DE_Msk (0x1U << TIM_DIER_CC4DE_Pos) /*!< 0x00001000 */
16640 #define TIM_DIER_CC4DE TIM_DIER_CC4DE_Msk /*!<Capture/Compare 4 DMA request enable */
16641 #define TIM_DIER_COMDE_Pos (13U)
16642 #define TIM_DIER_COMDE_Msk (0x1U << TIM_DIER_COMDE_Pos) /*!< 0x00002000 */
16643 #define TIM_DIER_COMDE TIM_DIER_COMDE_Msk /*!<COM DMA request enable */
16644 #define TIM_DIER_TDE_Pos (14U)
16645 #define TIM_DIER_TDE_Msk (0x1U << TIM_DIER_TDE_Pos) /*!< 0x00004000 */
16646 #define TIM_DIER_TDE TIM_DIER_TDE_Msk /*!<Trigger DMA request enable */
16647
16648 /******************** Bit definition for TIM_SR register ********************/
16649 #define TIM_SR_UIF_Pos (0U)
16650 #define TIM_SR_UIF_Msk (0x1U << TIM_SR_UIF_Pos) /*!< 0x00000001 */
16651 #define TIM_SR_UIF TIM_SR_UIF_Msk /*!<Update interrupt Flag */
16652 #define TIM_SR_CC1IF_Pos (1U)
16653 #define TIM_SR_CC1IF_Msk (0x1U << TIM_SR_CC1IF_Pos) /*!< 0x00000002 */
16654 #define TIM_SR_CC1IF TIM_SR_CC1IF_Msk /*!<Capture/Compare 1 interrupt Flag */
16655 #define TIM_SR_CC2IF_Pos (2U)
16656 #define TIM_SR_CC2IF_Msk (0x1U << TIM_SR_CC2IF_Pos) /*!< 0x00000004 */
16657 #define TIM_SR_CC2IF TIM_SR_CC2IF_Msk /*!<Capture/Compare 2 interrupt Flag */
16658 #define TIM_SR_CC3IF_Pos (3U)
16659 #define TIM_SR_CC3IF_Msk (0x1U << TIM_SR_CC3IF_Pos) /*!< 0x00000008 */
16660 #define TIM_SR_CC3IF TIM_SR_CC3IF_Msk /*!<Capture/Compare 3 interrupt Flag */
16661 #define TIM_SR_CC4IF_Pos (4U)
16662 #define TIM_SR_CC4IF_Msk (0x1U << TIM_SR_CC4IF_Pos) /*!< 0x00000010 */
16663 #define TIM_SR_CC4IF TIM_SR_CC4IF_Msk /*!<Capture/Compare 4 interrupt Flag */
16664 #define TIM_SR_COMIF_Pos (5U)
16665 #define TIM_SR_COMIF_Msk (0x1U << TIM_SR_COMIF_Pos) /*!< 0x00000020 */
16666 #define TIM_SR_COMIF TIM_SR_COMIF_Msk /*!<COM interrupt Flag */
16667 #define TIM_SR_TIF_Pos (6U)
16668 #define TIM_SR_TIF_Msk (0x1U << TIM_SR_TIF_Pos) /*!< 0x00000040 */
16669 #define TIM_SR_TIF TIM_SR_TIF_Msk /*!<Trigger interrupt Flag */
16670 #define TIM_SR_BIF_Pos (7U)
16671 #define TIM_SR_BIF_Msk (0x1U << TIM_SR_BIF_Pos) /*!< 0x00000080 */
16672 #define TIM_SR_BIF TIM_SR_BIF_Msk /*!<Break interrupt Flag */
16673 #define TIM_SR_CC1OF_Pos (9U)
16674 #define TIM_SR_CC1OF_Msk (0x1U << TIM_SR_CC1OF_Pos) /*!< 0x00000200 */
16675 #define TIM_SR_CC1OF TIM_SR_CC1OF_Msk /*!<Capture/Compare 1 Overcapture Flag */
16676 #define TIM_SR_CC2OF_Pos (10U)
16677 #define TIM_SR_CC2OF_Msk (0x1U << TIM_SR_CC2OF_Pos) /*!< 0x00000400 */
16678 #define TIM_SR_CC2OF TIM_SR_CC2OF_Msk /*!<Capture/Compare 2 Overcapture Flag */
16679 #define TIM_SR_CC3OF_Pos (11U)
16680 #define TIM_SR_CC3OF_Msk (0x1U << TIM_SR_CC3OF_Pos) /*!< 0x00000800 */
16681 #define TIM_SR_CC3OF TIM_SR_CC3OF_Msk /*!<Capture/Compare 3 Overcapture Flag */
16682 #define TIM_SR_CC4OF_Pos (12U)
16683 #define TIM_SR_CC4OF_Msk (0x1U << TIM_SR_CC4OF_Pos) /*!< 0x00001000 */
16684 #define TIM_SR_CC4OF TIM_SR_CC4OF_Msk /*!<Capture/Compare 4 Overcapture Flag */
16685
16686 /******************* Bit definition for TIM_EGR register ********************/
16687 #define TIM_EGR_UG_Pos (0U)
16688 #define TIM_EGR_UG_Msk (0x1U << TIM_EGR_UG_Pos) /*!< 0x00000001 */
16689 #define TIM_EGR_UG TIM_EGR_UG_Msk /*!<Update Generation */
16690 #define TIM_EGR_CC1G_Pos (1U)
16691 #define TIM_EGR_CC1G_Msk (0x1U << TIM_EGR_CC1G_Pos) /*!< 0x00000002 */
16692 #define TIM_EGR_CC1G TIM_EGR_CC1G_Msk /*!<Capture/Compare 1 Generation */
16693 #define TIM_EGR_CC2G_Pos (2U)
16694 #define TIM_EGR_CC2G_Msk (0x1U << TIM_EGR_CC2G_Pos) /*!< 0x00000004 */
16695 #define TIM_EGR_CC2G TIM_EGR_CC2G_Msk /*!<Capture/Compare 2 Generation */
16696 #define TIM_EGR_CC3G_Pos (3U)
16697 #define TIM_EGR_CC3G_Msk (0x1U << TIM_EGR_CC3G_Pos) /*!< 0x00000008 */
16698 #define TIM_EGR_CC3G TIM_EGR_CC3G_Msk /*!<Capture/Compare 3 Generation */
16699 #define TIM_EGR_CC4G_Pos (4U)
16700 #define TIM_EGR_CC4G_Msk (0x1U << TIM_EGR_CC4G_Pos) /*!< 0x00000010 */
16701 #define TIM_EGR_CC4G TIM_EGR_CC4G_Msk /*!<Capture/Compare 4 Generation */
16702 #define TIM_EGR_COMG_Pos (5U)
16703 #define TIM_EGR_COMG_Msk (0x1U << TIM_EGR_COMG_Pos) /*!< 0x00000020 */
16704 #define TIM_EGR_COMG TIM_EGR_COMG_Msk /*!<Capture/Compare Control Update Generation */
16705 #define TIM_EGR_TG_Pos (6U)
16706 #define TIM_EGR_TG_Msk (0x1U << TIM_EGR_TG_Pos) /*!< 0x00000040 */
16707 #define TIM_EGR_TG TIM_EGR_TG_Msk /*!<Trigger Generation */
16708 #define TIM_EGR_BG_Pos (7U)
16709 #define TIM_EGR_BG_Msk (0x1U << TIM_EGR_BG_Pos) /*!< 0x00000080 */
16710 #define TIM_EGR_BG TIM_EGR_BG_Msk /*!<Break Generation */
16711
16712 /****************** Bit definition for TIM_CCMR1 register *******************/
16713 #define TIM_CCMR1_CC1S_Pos (0U)
16714 #define TIM_CCMR1_CC1S_Msk (0x3U << TIM_CCMR1_CC1S_Pos) /*!< 0x00000003 */
16715 #define TIM_CCMR1_CC1S TIM_CCMR1_CC1S_Msk /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
16716 #define TIM_CCMR1_CC1S_0 (0x1U << TIM_CCMR1_CC1S_Pos) /*!< 0x0001 */
16717 #define TIM_CCMR1_CC1S_1 (0x2U << TIM_CCMR1_CC1S_Pos) /*!< 0x0002 */
16718
16719 #define TIM_CCMR1_OC1FE_Pos (2U)
16720 #define TIM_CCMR1_OC1FE_Msk (0x1U << TIM_CCMR1_OC1FE_Pos) /*!< 0x00000004 */
16721 #define TIM_CCMR1_OC1FE TIM_CCMR1_OC1FE_Msk /*!<Output Compare 1 Fast enable */
16722 #define TIM_CCMR1_OC1PE_Pos (3U)
16723 #define TIM_CCMR1_OC1PE_Msk (0x1U << TIM_CCMR1_OC1PE_Pos) /*!< 0x00000008 */
16724 #define TIM_CCMR1_OC1PE TIM_CCMR1_OC1PE_Msk /*!<Output Compare 1 Preload enable */
16725
16726 #define TIM_CCMR1_OC1M_Pos (4U)
16727 #define TIM_CCMR1_OC1M_Msk (0x7U << TIM_CCMR1_OC1M_Pos) /*!< 0x00000070 */
16728 #define TIM_CCMR1_OC1M TIM_CCMR1_OC1M_Msk /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
16729 #define TIM_CCMR1_OC1M_0 (0x1U << TIM_CCMR1_OC1M_Pos) /*!< 0x0010 */
16730 #define TIM_CCMR1_OC1M_1 (0x2U << TIM_CCMR1_OC1M_Pos) /*!< 0x0020 */
16731 #define TIM_CCMR1_OC1M_2 (0x4U << TIM_CCMR1_OC1M_Pos) /*!< 0x0040 */
16732
16733 #define TIM_CCMR1_OC1CE_Pos (7U)
16734 #define TIM_CCMR1_OC1CE_Msk (0x1U << TIM_CCMR1_OC1CE_Pos) /*!< 0x00000080 */
16735 #define TIM_CCMR1_OC1CE TIM_CCMR1_OC1CE_Msk /*!<Output Compare 1Clear Enable */
16736
16737 #define TIM_CCMR1_CC2S_Pos (8U)
16738 #define TIM_CCMR1_CC2S_Msk (0x3U << TIM_CCMR1_CC2S_Pos) /*!< 0x00000300 */
16739 #define TIM_CCMR1_CC2S TIM_CCMR1_CC2S_Msk /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
16740 #define TIM_CCMR1_CC2S_0 (0x1U << TIM_CCMR1_CC2S_Pos) /*!< 0x0100 */
16741 #define TIM_CCMR1_CC2S_1 (0x2U << TIM_CCMR1_CC2S_Pos) /*!< 0x0200 */
16742
16743 #define TIM_CCMR1_OC2FE_Pos (10U)
16744 #define TIM_CCMR1_OC2FE_Msk (0x1U << TIM_CCMR1_OC2FE_Pos) /*!< 0x00000400 */
16745 #define TIM_CCMR1_OC2FE TIM_CCMR1_OC2FE_Msk /*!<Output Compare 2 Fast enable */
16746 #define TIM_CCMR1_OC2PE_Pos (11U)
16747 #define TIM_CCMR1_OC2PE_Msk (0x1U << TIM_CCMR1_OC2PE_Pos) /*!< 0x00000800 */
16748 #define TIM_CCMR1_OC2PE TIM_CCMR1_OC2PE_Msk /*!<Output Compare 2 Preload enable */
16749
16750 #define TIM_CCMR1_OC2M_Pos (12U)
16751 #define TIM_CCMR1_OC2M_Msk (0x7U << TIM_CCMR1_OC2M_Pos) /*!< 0x00007000 */
16752 #define TIM_CCMR1_OC2M TIM_CCMR1_OC2M_Msk /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
16753 #define TIM_CCMR1_OC2M_0 (0x1U << TIM_CCMR1_OC2M_Pos) /*!< 0x1000 */
16754 #define TIM_CCMR1_OC2M_1 (0x2U << TIM_CCMR1_OC2M_Pos) /*!< 0x2000 */
16755 #define TIM_CCMR1_OC2M_2 (0x4U << TIM_CCMR1_OC2M_Pos) /*!< 0x4000 */
16756
16757 #define TIM_CCMR1_OC2CE_Pos (15U)
16758 #define TIM_CCMR1_OC2CE_Msk (0x1U << TIM_CCMR1_OC2CE_Pos) /*!< 0x00008000 */
16759 #define TIM_CCMR1_OC2CE TIM_CCMR1_OC2CE_Msk /*!<Output Compare 2 Clear Enable */
16760
16761 /*----------------------------------------------------------------------------*/
16762
16763 #define TIM_CCMR1_IC1PSC_Pos (2U)
16764 #define TIM_CCMR1_IC1PSC_Msk (0x3U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x0000000C */
16765 #define TIM_CCMR1_IC1PSC TIM_CCMR1_IC1PSC_Msk /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
16766 #define TIM_CCMR1_IC1PSC_0 (0x1U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x0004 */
16767 #define TIM_CCMR1_IC1PSC_1 (0x2U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x0008 */
16768
16769 #define TIM_CCMR1_IC1F_Pos (4U)
16770 #define TIM_CCMR1_IC1F_Msk (0xFU << TIM_CCMR1_IC1F_Pos) /*!< 0x000000F0 */
16771 #define TIM_CCMR1_IC1F TIM_CCMR1_IC1F_Msk /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
16772 #define TIM_CCMR1_IC1F_0 (0x1U << TIM_CCMR1_IC1F_Pos) /*!< 0x0010 */
16773 #define TIM_CCMR1_IC1F_1 (0x2U << TIM_CCMR1_IC1F_Pos) /*!< 0x0020 */
16774 #define TIM_CCMR1_IC1F_2 (0x4U << TIM_CCMR1_IC1F_Pos) /*!< 0x0040 */
16775 #define TIM_CCMR1_IC1F_3 (0x8U << TIM_CCMR1_IC1F_Pos) /*!< 0x0080 */
16776
16777 #define TIM_CCMR1_IC2PSC_Pos (10U)
16778 #define TIM_CCMR1_IC2PSC_Msk (0x3U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000C00 */
16779 #define TIM_CCMR1_IC2PSC TIM_CCMR1_IC2PSC_Msk /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
16780 #define TIM_CCMR1_IC2PSC_0 (0x1U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x0400 */
16781 #define TIM_CCMR1_IC2PSC_1 (0x2U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x0800 */
16782
16783 #define TIM_CCMR1_IC2F_Pos (12U)
16784 #define TIM_CCMR1_IC2F_Msk (0xFU << TIM_CCMR1_IC2F_Pos) /*!< 0x0000F000 */
16785 #define TIM_CCMR1_IC2F TIM_CCMR1_IC2F_Msk /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
16786 #define TIM_CCMR1_IC2F_0 (0x1U << TIM_CCMR1_IC2F_Pos) /*!< 0x1000 */
16787 #define TIM_CCMR1_IC2F_1 (0x2U << TIM_CCMR1_IC2F_Pos) /*!< 0x2000 */
16788 #define TIM_CCMR1_IC2F_2 (0x4U << TIM_CCMR1_IC2F_Pos) /*!< 0x4000 */
16789 #define TIM_CCMR1_IC2F_3 (0x8U << TIM_CCMR1_IC2F_Pos) /*!< 0x8000 */
16790
16791 /****************** Bit definition for TIM_CCMR2 register *******************/
16792 #define TIM_CCMR2_CC3S_Pos (0U)
16793 #define TIM_CCMR2_CC3S_Msk (0x3U << TIM_CCMR2_CC3S_Pos) /*!< 0x00000003 */
16794 #define TIM_CCMR2_CC3S TIM_CCMR2_CC3S_Msk /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
16795 #define TIM_CCMR2_CC3S_0 (0x1U << TIM_CCMR2_CC3S_Pos) /*!< 0x0001 */
16796 #define TIM_CCMR2_CC3S_1 (0x2U << TIM_CCMR2_CC3S_Pos) /*!< 0x0002 */
16797
16798 #define TIM_CCMR2_OC3FE_Pos (2U)
16799 #define TIM_CCMR2_OC3FE_Msk (0x1U << TIM_CCMR2_OC3FE_Pos) /*!< 0x00000004 */
16800 #define TIM_CCMR2_OC3FE TIM_CCMR2_OC3FE_Msk /*!<Output Compare 3 Fast enable */
16801 #define TIM_CCMR2_OC3PE_Pos (3U)
16802 #define TIM_CCMR2_OC3PE_Msk (0x1U << TIM_CCMR2_OC3PE_Pos) /*!< 0x00000008 */
16803 #define TIM_CCMR2_OC3PE TIM_CCMR2_OC3PE_Msk /*!<Output Compare 3 Preload enable */
16804
16805 #define TIM_CCMR2_OC3M_Pos (4U)
16806 #define TIM_CCMR2_OC3M_Msk (0x7U << TIM_CCMR2_OC3M_Pos) /*!< 0x00000070 */
16807 #define TIM_CCMR2_OC3M TIM_CCMR2_OC3M_Msk /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
16808 #define TIM_CCMR2_OC3M_0 (0x1U << TIM_CCMR2_OC3M_Pos) /*!< 0x0010 */
16809 #define TIM_CCMR2_OC3M_1 (0x2U << TIM_CCMR2_OC3M_Pos) /*!< 0x0020 */
16810 #define TIM_CCMR2_OC3M_2 (0x4U << TIM_CCMR2_OC3M_Pos) /*!< 0x0040 */
16811
16812 #define TIM_CCMR2_OC3CE_Pos (7U)
16813 #define TIM_CCMR2_OC3CE_Msk (0x1U << TIM_CCMR2_OC3CE_Pos) /*!< 0x00000080 */
16814 #define TIM_CCMR2_OC3CE TIM_CCMR2_OC3CE_Msk /*!<Output Compare 3 Clear Enable */
16815
16816 #define TIM_CCMR2_CC4S_Pos (8U)
16817 #define TIM_CCMR2_CC4S_Msk (0x3U << TIM_CCMR2_CC4S_Pos) /*!< 0x00000300 */
16818 #define TIM_CCMR2_CC4S TIM_CCMR2_CC4S_Msk /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
16819 #define TIM_CCMR2_CC4S_0 (0x1U << TIM_CCMR2_CC4S_Pos) /*!< 0x0100 */
16820 #define TIM_CCMR2_CC4S_1 (0x2U << TIM_CCMR2_CC4S_Pos) /*!< 0x0200 */
16821
16822 #define TIM_CCMR2_OC4FE_Pos (10U)
16823 #define TIM_CCMR2_OC4FE_Msk (0x1U << TIM_CCMR2_OC4FE_Pos) /*!< 0x00000400 */
16824 #define TIM_CCMR2_OC4FE TIM_CCMR2_OC4FE_Msk /*!<Output Compare 4 Fast enable */
16825 #define TIM_CCMR2_OC4PE_Pos (11U)
16826 #define TIM_CCMR2_OC4PE_Msk (0x1U << TIM_CCMR2_OC4PE_Pos) /*!< 0x00000800 */
16827 #define TIM_CCMR2_OC4PE TIM_CCMR2_OC4PE_Msk /*!<Output Compare 4 Preload enable */
16828
16829 #define TIM_CCMR2_OC4M_Pos (12U)
16830 #define TIM_CCMR2_OC4M_Msk (0x7U << TIM_CCMR2_OC4M_Pos) /*!< 0x00007000 */
16831 #define TIM_CCMR2_OC4M TIM_CCMR2_OC4M_Msk /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
16832 #define TIM_CCMR2_OC4M_0 (0x1U << TIM_CCMR2_OC4M_Pos) /*!< 0x1000 */
16833 #define TIM_CCMR2_OC4M_1 (0x2U << TIM_CCMR2_OC4M_Pos) /*!< 0x2000 */
16834 #define TIM_CCMR2_OC4M_2 (0x4U << TIM_CCMR2_OC4M_Pos) /*!< 0x4000 */
16835
16836 #define TIM_CCMR2_OC4CE_Pos (15U)
16837 #define TIM_CCMR2_OC4CE_Msk (0x1U << TIM_CCMR2_OC4CE_Pos) /*!< 0x00008000 */
16838 #define TIM_CCMR2_OC4CE TIM_CCMR2_OC4CE_Msk /*!<Output Compare 4 Clear Enable */
16839
16840 /*----------------------------------------------------------------------------*/
16841
16842 #define TIM_CCMR2_IC3PSC_Pos (2U)
16843 #define TIM_CCMR2_IC3PSC_Msk (0x3U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x0000000C */
16844 #define TIM_CCMR2_IC3PSC TIM_CCMR2_IC3PSC_Msk /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
16845 #define TIM_CCMR2_IC3PSC_0 (0x1U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x0004 */
16846 #define TIM_CCMR2_IC3PSC_1 (0x2U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x0008 */
16847
16848 #define TIM_CCMR2_IC3F_Pos (4U)
16849 #define TIM_CCMR2_IC3F_Msk (0xFU << TIM_CCMR2_IC3F_Pos) /*!< 0x000000F0 */
16850 #define TIM_CCMR2_IC3F TIM_CCMR2_IC3F_Msk /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
16851 #define TIM_CCMR2_IC3F_0 (0x1U << TIM_CCMR2_IC3F_Pos) /*!< 0x0010 */
16852 #define TIM_CCMR2_IC3F_1 (0x2U << TIM_CCMR2_IC3F_Pos) /*!< 0x0020 */
16853 #define TIM_CCMR2_IC3F_2 (0x4U << TIM_CCMR2_IC3F_Pos) /*!< 0x0040 */
16854 #define TIM_CCMR2_IC3F_3 (0x8U << TIM_CCMR2_IC3F_Pos) /*!< 0x0080 */
16855
16856 #define TIM_CCMR2_IC4PSC_Pos (10U)
16857 #define TIM_CCMR2_IC4PSC_Msk (0x3U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000C00 */
16858 #define TIM_CCMR2_IC4PSC TIM_CCMR2_IC4PSC_Msk /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
16859 #define TIM_CCMR2_IC4PSC_0 (0x1U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x0400 */
16860 #define TIM_CCMR2_IC4PSC_1 (0x2U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x0800 */
16861
16862 #define TIM_CCMR2_IC4F_Pos (12U)
16863 #define TIM_CCMR2_IC4F_Msk (0xFU << TIM_CCMR2_IC4F_Pos) /*!< 0x0000F000 */
16864 #define TIM_CCMR2_IC4F TIM_CCMR2_IC4F_Msk /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
16865 #define TIM_CCMR2_IC4F_0 (0x1U << TIM_CCMR2_IC4F_Pos) /*!< 0x1000 */
16866 #define TIM_CCMR2_IC4F_1 (0x2U << TIM_CCMR2_IC4F_Pos) /*!< 0x2000 */
16867 #define TIM_CCMR2_IC4F_2 (0x4U << TIM_CCMR2_IC4F_Pos) /*!< 0x4000 */
16868 #define TIM_CCMR2_IC4F_3 (0x8U << TIM_CCMR2_IC4F_Pos) /*!< 0x8000 */
16869
16870 /******************* Bit definition for TIM_CCER register *******************/
16871 #define TIM_CCER_CC1E_Pos (0U)
16872 #define TIM_CCER_CC1E_Msk (0x1U << TIM_CCER_CC1E_Pos) /*!< 0x00000001 */
16873 #define TIM_CCER_CC1E TIM_CCER_CC1E_Msk /*!<Capture/Compare 1 output enable */
16874 #define TIM_CCER_CC1P_Pos (1U)
16875 #define TIM_CCER_CC1P_Msk (0x1U << TIM_CCER_CC1P_Pos) /*!< 0x00000002 */
16876 #define TIM_CCER_CC1P TIM_CCER_CC1P_Msk /*!<Capture/Compare 1 output Polarity */
16877 #define TIM_CCER_CC1NE_Pos (2U)
16878 #define TIM_CCER_CC1NE_Msk (0x1U << TIM_CCER_CC1NE_Pos) /*!< 0x00000004 */
16879 #define TIM_CCER_CC1NE TIM_CCER_CC1NE_Msk /*!<Capture/Compare 1 Complementary output enable */
16880 #define TIM_CCER_CC1NP_Pos (3U)
16881 #define TIM_CCER_CC1NP_Msk (0x1U << TIM_CCER_CC1NP_Pos) /*!< 0x00000008 */
16882 #define TIM_CCER_CC1NP TIM_CCER_CC1NP_Msk /*!<Capture/Compare 1 Complementary output Polarity */
16883 #define TIM_CCER_CC2E_Pos (4U)
16884 #define TIM_CCER_CC2E_Msk (0x1U << TIM_CCER_CC2E_Pos) /*!< 0x00000010 */
16885 #define TIM_CCER_CC2E TIM_CCER_CC2E_Msk /*!<Capture/Compare 2 output enable */
16886 #define TIM_CCER_CC2P_Pos (5U)
16887 #define TIM_CCER_CC2P_Msk (0x1U << TIM_CCER_CC2P_Pos) /*!< 0x00000020 */
16888 #define TIM_CCER_CC2P TIM_CCER_CC2P_Msk /*!<Capture/Compare 2 output Polarity */
16889 #define TIM_CCER_CC2NE_Pos (6U)
16890 #define TIM_CCER_CC2NE_Msk (0x1U << TIM_CCER_CC2NE_Pos) /*!< 0x00000040 */
16891 #define TIM_CCER_CC2NE TIM_CCER_CC2NE_Msk /*!<Capture/Compare 2 Complementary output enable */
16892 #define TIM_CCER_CC2NP_Pos (7U)
16893 #define TIM_CCER_CC2NP_Msk (0x1U << TIM_CCER_CC2NP_Pos) /*!< 0x00000080 */
16894 #define TIM_CCER_CC2NP TIM_CCER_CC2NP_Msk /*!<Capture/Compare 2 Complementary output Polarity */
16895 #define TIM_CCER_CC3E_Pos (8U)
16896 #define TIM_CCER_CC3E_Msk (0x1U << TIM_CCER_CC3E_Pos) /*!< 0x00000100 */
16897 #define TIM_CCER_CC3E TIM_CCER_CC3E_Msk /*!<Capture/Compare 3 output enable */
16898 #define TIM_CCER_CC3P_Pos (9U)
16899 #define TIM_CCER_CC3P_Msk (0x1U << TIM_CCER_CC3P_Pos) /*!< 0x00000200 */
16900 #define TIM_CCER_CC3P TIM_CCER_CC3P_Msk /*!<Capture/Compare 3 output Polarity */
16901 #define TIM_CCER_CC3NE_Pos (10U)
16902 #define TIM_CCER_CC3NE_Msk (0x1U << TIM_CCER_CC3NE_Pos) /*!< 0x00000400 */
16903 #define TIM_CCER_CC3NE TIM_CCER_CC3NE_Msk /*!<Capture/Compare 3 Complementary output enable */
16904 #define TIM_CCER_CC3NP_Pos (11U)
16905 #define TIM_CCER_CC3NP_Msk (0x1U << TIM_CCER_CC3NP_Pos) /*!< 0x00000800 */
16906 #define TIM_CCER_CC3NP TIM_CCER_CC3NP_Msk /*!<Capture/Compare 3 Complementary output Polarity */
16907 #define TIM_CCER_CC4E_Pos (12U)
16908 #define TIM_CCER_CC4E_Msk (0x1U << TIM_CCER_CC4E_Pos) /*!< 0x00001000 */
16909 #define TIM_CCER_CC4E TIM_CCER_CC4E_Msk /*!<Capture/Compare 4 output enable */
16910 #define TIM_CCER_CC4P_Pos (13U)
16911 #define TIM_CCER_CC4P_Msk (0x1U << TIM_CCER_CC4P_Pos) /*!< 0x00002000 */
16912 #define TIM_CCER_CC4P TIM_CCER_CC4P_Msk /*!<Capture/Compare 4 output Polarity */
16913 #define TIM_CCER_CC4NP_Pos (15U)
16914 #define TIM_CCER_CC4NP_Msk (0x1U << TIM_CCER_CC4NP_Pos) /*!< 0x00008000 */
16915 #define TIM_CCER_CC4NP TIM_CCER_CC4NP_Msk /*!<Capture/Compare 4 Complementary output Polarity */
16916
16917 /******************* Bit definition for TIM_CNT register ********************/
16918 #define TIM_CNT_CNT_Pos (0U)
16919 #define TIM_CNT_CNT_Msk (0xFFFFFFFFU << TIM_CNT_CNT_Pos) /*!< 0xFFFFFFFF */
16920 #define TIM_CNT_CNT TIM_CNT_CNT_Msk /*!<Counter Value */
16921
16922 /******************* Bit definition for TIM_PSC register ********************/
16923 #define TIM_PSC_PSC_Pos (0U)
16924 #define TIM_PSC_PSC_Msk (0xFFFFU << TIM_PSC_PSC_Pos) /*!< 0x0000FFFF */
16925 #define TIM_PSC_PSC TIM_PSC_PSC_Msk /*!<Prescaler Value */
16926
16927 /******************* Bit definition for TIM_ARR register ********************/
16928 #define TIM_ARR_ARR_Pos (0U)
16929 #define TIM_ARR_ARR_Msk (0xFFFFFFFFU << TIM_ARR_ARR_Pos) /*!< 0xFFFFFFFF */
16930 #define TIM_ARR_ARR TIM_ARR_ARR_Msk /*!<actual auto-reload Value */
16931
16932 /******************* Bit definition for TIM_RCR register ********************/
16933 #define TIM_RCR_REP_Pos (0U)
16934 #define TIM_RCR_REP_Msk (0xFFU << TIM_RCR_REP_Pos) /*!< 0x000000FF */
16935 #define TIM_RCR_REP TIM_RCR_REP_Msk /*!<Repetition Counter Value */
16936
16937 /******************* Bit definition for TIM_CCR1 register *******************/
16938 #define TIM_CCR1_CCR1_Pos (0U)
16939 #define TIM_CCR1_CCR1_Msk (0xFFFFU << TIM_CCR1_CCR1_Pos) /*!< 0x0000FFFF */
16940 #define TIM_CCR1_CCR1 TIM_CCR1_CCR1_Msk /*!<Capture/Compare 1 Value */
16941
16942 /******************* Bit definition for TIM_CCR2 register *******************/
16943 #define TIM_CCR2_CCR2_Pos (0U)
16944 #define TIM_CCR2_CCR2_Msk (0xFFFFU << TIM_CCR2_CCR2_Pos) /*!< 0x0000FFFF */
16945 #define TIM_CCR2_CCR2 TIM_CCR2_CCR2_Msk /*!<Capture/Compare 2 Value */
16946
16947 /******************* Bit definition for TIM_CCR3 register *******************/
16948 #define TIM_CCR3_CCR3_Pos (0U)
16949 #define TIM_CCR3_CCR3_Msk (0xFFFFU << TIM_CCR3_CCR3_Pos) /*!< 0x0000FFFF */
16950 #define TIM_CCR3_CCR3 TIM_CCR3_CCR3_Msk /*!<Capture/Compare 3 Value */
16951
16952 /******************* Bit definition for TIM_CCR4 register *******************/
16953 #define TIM_CCR4_CCR4_Pos (0U)
16954 #define TIM_CCR4_CCR4_Msk (0xFFFFU << TIM_CCR4_CCR4_Pos) /*!< 0x0000FFFF */
16955 #define TIM_CCR4_CCR4 TIM_CCR4_CCR4_Msk /*!<Capture/Compare 4 Value */
16956
16957 /******************* Bit definition for TIM_BDTR register *******************/
16958 #define TIM_BDTR_DTG_Pos (0U)
16959 #define TIM_BDTR_DTG_Msk (0xFFU << TIM_BDTR_DTG_Pos) /*!< 0x000000FF */
16960 #define TIM_BDTR_DTG TIM_BDTR_DTG_Msk /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
16961 #define TIM_BDTR_DTG_0 (0x01U << TIM_BDTR_DTG_Pos) /*!< 0x0001 */
16962 #define TIM_BDTR_DTG_1 (0x02U << TIM_BDTR_DTG_Pos) /*!< 0x0002 */
16963 #define TIM_BDTR_DTG_2 (0x04U << TIM_BDTR_DTG_Pos) /*!< 0x0004 */
16964 #define TIM_BDTR_DTG_3 (0x08U << TIM_BDTR_DTG_Pos) /*!< 0x0008 */
16965 #define TIM_BDTR_DTG_4 (0x10U << TIM_BDTR_DTG_Pos) /*!< 0x0010 */
16966 #define TIM_BDTR_DTG_5 (0x20U << TIM_BDTR_DTG_Pos) /*!< 0x0020 */
16967 #define TIM_BDTR_DTG_6 (0x40U << TIM_BDTR_DTG_Pos) /*!< 0x0040 */
16968 #define TIM_BDTR_DTG_7 (0x80U << TIM_BDTR_DTG_Pos) /*!< 0x0080 */
16969
16970 #define TIM_BDTR_LOCK_Pos (8U)
16971 #define TIM_BDTR_LOCK_Msk (0x3U << TIM_BDTR_LOCK_Pos) /*!< 0x00000300 */
16972 #define TIM_BDTR_LOCK TIM_BDTR_LOCK_Msk /*!<LOCK[1:0] bits (Lock Configuration) */
16973 #define TIM_BDTR_LOCK_0 (0x1U << TIM_BDTR_LOCK_Pos) /*!< 0x0100 */
16974 #define TIM_BDTR_LOCK_1 (0x2U << TIM_BDTR_LOCK_Pos) /*!< 0x0200 */
16975
16976 #define TIM_BDTR_OSSI_Pos (10U)
16977 #define TIM_BDTR_OSSI_Msk (0x1U << TIM_BDTR_OSSI_Pos) /*!< 0x00000400 */
16978 #define TIM_BDTR_OSSI TIM_BDTR_OSSI_Msk /*!<Off-State Selection for Idle mode */
16979 #define TIM_BDTR_OSSR_Pos (11U)
16980 #define TIM_BDTR_OSSR_Msk (0x1U << TIM_BDTR_OSSR_Pos) /*!< 0x00000800 */
16981 #define TIM_BDTR_OSSR TIM_BDTR_OSSR_Msk /*!<Off-State Selection for Run mode */
16982 #define TIM_BDTR_BKE_Pos (12U)
16983 #define TIM_BDTR_BKE_Msk (0x1U << TIM_BDTR_BKE_Pos) /*!< 0x00001000 */
16984 #define TIM_BDTR_BKE TIM_BDTR_BKE_Msk /*!<Break enable */
16985 #define TIM_BDTR_BKP_Pos (13U)
16986 #define TIM_BDTR_BKP_Msk (0x1U << TIM_BDTR_BKP_Pos) /*!< 0x00002000 */
16987 #define TIM_BDTR_BKP TIM_BDTR_BKP_Msk /*!<Break Polarity */
16988 #define TIM_BDTR_AOE_Pos (14U)
16989 #define TIM_BDTR_AOE_Msk (0x1U << TIM_BDTR_AOE_Pos) /*!< 0x00004000 */
16990 #define TIM_BDTR_AOE TIM_BDTR_AOE_Msk /*!<Automatic Output enable */
16991 #define TIM_BDTR_MOE_Pos (15U)
16992 #define TIM_BDTR_MOE_Msk (0x1U << TIM_BDTR_MOE_Pos) /*!< 0x00008000 */
16993 #define TIM_BDTR_MOE TIM_BDTR_MOE_Msk /*!<Main Output enable */
16994
16995 /******************* Bit definition for TIM_DCR register ********************/
16996 #define TIM_DCR_DBA_Pos (0U)
16997 #define TIM_DCR_DBA_Msk (0x1FU << TIM_DCR_DBA_Pos) /*!< 0x0000001F */
16998 #define TIM_DCR_DBA TIM_DCR_DBA_Msk /*!<DBA[4:0] bits (DMA Base Address) */
16999 #define TIM_DCR_DBA_0 (0x01U << TIM_DCR_DBA_Pos) /*!< 0x0001 */
17000 #define TIM_DCR_DBA_1 (0x02U << TIM_DCR_DBA_Pos) /*!< 0x0002 */
17001 #define TIM_DCR_DBA_2 (0x04U << TIM_DCR_DBA_Pos) /*!< 0x0004 */
17002 #define TIM_DCR_DBA_3 (0x08U << TIM_DCR_DBA_Pos) /*!< 0x0008 */
17003 #define TIM_DCR_DBA_4 (0x10U << TIM_DCR_DBA_Pos) /*!< 0x0010 */
17004
17005 #define TIM_DCR_DBL_Pos (8U)
17006 #define TIM_DCR_DBL_Msk (0x1FU << TIM_DCR_DBL_Pos) /*!< 0x00001F00 */
17007 #define TIM_DCR_DBL TIM_DCR_DBL_Msk /*!<DBL[4:0] bits (DMA Burst Length) */
17008 #define TIM_DCR_DBL_0 (0x01U << TIM_DCR_DBL_Pos) /*!< 0x0100 */
17009 #define TIM_DCR_DBL_1 (0x02U << TIM_DCR_DBL_Pos) /*!< 0x0200 */
17010 #define TIM_DCR_DBL_2 (0x04U << TIM_DCR_DBL_Pos) /*!< 0x0400 */
17011 #define TIM_DCR_DBL_3 (0x08U << TIM_DCR_DBL_Pos) /*!< 0x0800 */
17012 #define TIM_DCR_DBL_4 (0x10U << TIM_DCR_DBL_Pos) /*!< 0x1000 */
17013
17014 /******************* Bit definition for TIM_DMAR register *******************/
17015 #define TIM_DMAR_DMAB_Pos (0U)
17016 #define TIM_DMAR_DMAB_Msk (0xFFFFU << TIM_DMAR_DMAB_Pos) /*!< 0x0000FFFF */
17017 #define TIM_DMAR_DMAB TIM_DMAR_DMAB_Msk /*!<DMA register for burst accesses */
17018
17019 /******************* Bit definition for TIM_OR register *********************/
17020 #define TIM_OR_TI1_RMP_Pos (0U)
17021 #define TIM_OR_TI1_RMP_Msk (0x3U << TIM_OR_TI1_RMP_Pos) /*!< 0x00000003 */
17022 #define TIM_OR_TI1_RMP TIM_OR_TI1_RMP_Msk /*!< TI1_RMP[1:0] bits (TIM11 Input Capture 1 remap) */
17023 #define TIM_OR_TI1_RMP_0 (0x1U << TIM_OR_TI1_RMP_Pos) /*!< 0x00000001 */
17024 #define TIM_OR_TI1_RMP_1 (0x2U << TIM_OR_TI1_RMP_Pos) /*!< 0x00000002 */
17025
17026 #define TIM_OR_TI4_RMP_Pos (6U)
17027 #define TIM_OR_TI4_RMP_Msk (0x3U << TIM_OR_TI4_RMP_Pos) /*!< 0x000000C0 */
17028 #define TIM_OR_TI4_RMP TIM_OR_TI4_RMP_Msk /*!<TI4_RMP[1:0] bits (TIM5 Input 4 remap) */
17029 #define TIM_OR_TI4_RMP_0 (0x1U << TIM_OR_TI4_RMP_Pos) /*!< 0x0040 */
17030 #define TIM_OR_TI4_RMP_1 (0x2U << TIM_OR_TI4_RMP_Pos) /*!< 0x0080 */
17031 #define TIM_OR_ITR1_RMP_Pos (10U)
17032 #define TIM_OR_ITR1_RMP_Msk (0x3U << TIM_OR_ITR1_RMP_Pos) /*!< 0x00000C00 */
17033 #define TIM_OR_ITR1_RMP TIM_OR_ITR1_RMP_Msk /*!<ITR1_RMP[1:0] bits (TIM2 Internal trigger 1 remap) */
17034 #define TIM_OR_ITR1_RMP_0 (0x1U << TIM_OR_ITR1_RMP_Pos) /*!< 0x0400 */
17035 #define TIM_OR_ITR1_RMP_1 (0x2U << TIM_OR_ITR1_RMP_Pos) /*!< 0x0800 */
17036
17037
17038 /******************************************************************************/
17039 /* */
17040 /* Universal Synchronous Asynchronous Receiver Transmitter */
17041 /* */
17042 /******************************************************************************/
17043 /******************* Bit definition for USART_SR register *******************/
17044 #define USART_SR_PE_Pos (0U)
17045 #define USART_SR_PE_Msk (0x1U << USART_SR_PE_Pos) /*!< 0x00000001 */
17046 #define USART_SR_PE USART_SR_PE_Msk /*!<Parity Error */
17047 #define USART_SR_FE_Pos (1U)
17048 #define USART_SR_FE_Msk (0x1U << USART_SR_FE_Pos) /*!< 0x00000002 */
17049 #define USART_SR_FE USART_SR_FE_Msk /*!<Framing Error */
17050 #define USART_SR_NE_Pos (2U)
17051 #define USART_SR_NE_Msk (0x1U << USART_SR_NE_Pos) /*!< 0x00000004 */
17052 #define USART_SR_NE USART_SR_NE_Msk /*!<Noise Error Flag */
17053 #define USART_SR_ORE_Pos (3U)
17054 #define USART_SR_ORE_Msk (0x1U << USART_SR_ORE_Pos) /*!< 0x00000008 */
17055 #define USART_SR_ORE USART_SR_ORE_Msk /*!<OverRun Error */
17056 #define USART_SR_IDLE_Pos (4U)
17057 #define USART_SR_IDLE_Msk (0x1U << USART_SR_IDLE_Pos) /*!< 0x00000010 */
17058 #define USART_SR_IDLE USART_SR_IDLE_Msk /*!<IDLE line detected */
17059 #define USART_SR_RXNE_Pos (5U)
17060 #define USART_SR_RXNE_Msk (0x1U << USART_SR_RXNE_Pos) /*!< 0x00000020 */
17061 #define USART_SR_RXNE USART_SR_RXNE_Msk /*!<Read Data Register Not Empty */
17062 #define USART_SR_TC_Pos (6U)
17063 #define USART_SR_TC_Msk (0x1U << USART_SR_TC_Pos) /*!< 0x00000040 */
17064 #define USART_SR_TC USART_SR_TC_Msk /*!<Transmission Complete */
17065 #define USART_SR_TXE_Pos (7U)
17066 #define USART_SR_TXE_Msk (0x1U << USART_SR_TXE_Pos) /*!< 0x00000080 */
17067 #define USART_SR_TXE USART_SR_TXE_Msk /*!<Transmit Data Register Empty */
17068 #define USART_SR_LBD_Pos (8U)
17069 #define USART_SR_LBD_Msk (0x1U << USART_SR_LBD_Pos) /*!< 0x00000100 */
17070 #define USART_SR_LBD USART_SR_LBD_Msk /*!<LIN Break Detection Flag */
17071 #define USART_SR_CTS_Pos (9U)
17072 #define USART_SR_CTS_Msk (0x1U << USART_SR_CTS_Pos) /*!< 0x00000200 */
17073 #define USART_SR_CTS USART_SR_CTS_Msk /*!<CTS Flag */
17074
17075 /******************* Bit definition for USART_DR register *******************/
17076 #define USART_DR_DR_Pos (0U)
17077 #define USART_DR_DR_Msk (0x1FFU << USART_DR_DR_Pos) /*!< 0x000001FF */
17078 #define USART_DR_DR USART_DR_DR_Msk /*!<Data value */
17079
17080 /****************** Bit definition for USART_BRR register *******************/
17081 #define USART_BRR_DIV_Fraction_Pos (0U)
17082 #define USART_BRR_DIV_Fraction_Msk (0xFU << USART_BRR_DIV_Fraction_Pos) /*!< 0x0000000F */
17083 #define USART_BRR_DIV_Fraction USART_BRR_DIV_Fraction_Msk /*!<Fraction of USARTDIV */
17084 #define USART_BRR_DIV_Mantissa_Pos (4U)
17085 #define USART_BRR_DIV_Mantissa_Msk (0xFFFU << USART_BRR_DIV_Mantissa_Pos) /*!< 0x0000FFF0 */
17086 #define USART_BRR_DIV_Mantissa USART_BRR_DIV_Mantissa_Msk /*!<Mantissa of USARTDIV */
17087
17088 /****************** Bit definition for USART_CR1 register *******************/
17089 #define USART_CR1_SBK_Pos (0U)
17090 #define USART_CR1_SBK_Msk (0x1U << USART_CR1_SBK_Pos) /*!< 0x00000001 */
17091 #define USART_CR1_SBK USART_CR1_SBK_Msk /*!<Send Break */
17092 #define USART_CR1_RWU_Pos (1U)
17093 #define USART_CR1_RWU_Msk (0x1U << USART_CR1_RWU_Pos) /*!< 0x00000002 */
17094 #define USART_CR1_RWU USART_CR1_RWU_Msk /*!<Receiver wakeup */
17095 #define USART_CR1_RE_Pos (2U)
17096 #define USART_CR1_RE_Msk (0x1U << USART_CR1_RE_Pos) /*!< 0x00000004 */
17097 #define USART_CR1_RE USART_CR1_RE_Msk /*!<Receiver Enable */
17098 #define USART_CR1_TE_Pos (3U)
17099 #define USART_CR1_TE_Msk (0x1U << USART_CR1_TE_Pos) /*!< 0x00000008 */
17100 #define USART_CR1_TE USART_CR1_TE_Msk /*!<Transmitter Enable */
17101 #define USART_CR1_IDLEIE_Pos (4U)
17102 #define USART_CR1_IDLEIE_Msk (0x1U << USART_CR1_IDLEIE_Pos) /*!< 0x00000010 */
17103 #define USART_CR1_IDLEIE USART_CR1_IDLEIE_Msk /*!<IDLE Interrupt Enable */
17104 #define USART_CR1_RXNEIE_Pos (5U)
17105 #define USART_CR1_RXNEIE_Msk (0x1U << USART_CR1_RXNEIE_Pos) /*!< 0x00000020 */
17106 #define USART_CR1_RXNEIE USART_CR1_RXNEIE_Msk /*!<RXNE Interrupt Enable */
17107 #define USART_CR1_TCIE_Pos (6U)
17108 #define USART_CR1_TCIE_Msk (0x1U << USART_CR1_TCIE_Pos) /*!< 0x00000040 */
17109 #define USART_CR1_TCIE USART_CR1_TCIE_Msk /*!<Transmission Complete Interrupt Enable */
17110 #define USART_CR1_TXEIE_Pos (7U)
17111 #define USART_CR1_TXEIE_Msk (0x1U << USART_CR1_TXEIE_Pos) /*!< 0x00000080 */
17112 #define USART_CR1_TXEIE USART_CR1_TXEIE_Msk /*!<TXE Interrupt Enable */
17113 #define USART_CR1_PEIE_Pos (8U)
17114 #define USART_CR1_PEIE_Msk (0x1U << USART_CR1_PEIE_Pos) /*!< 0x00000100 */
17115 #define USART_CR1_PEIE USART_CR1_PEIE_Msk /*!<PE Interrupt Enable */
17116 #define USART_CR1_PS_Pos (9U)
17117 #define USART_CR1_PS_Msk (0x1U << USART_CR1_PS_Pos) /*!< 0x00000200 */
17118 #define USART_CR1_PS USART_CR1_PS_Msk /*!<Parity Selection */
17119 #define USART_CR1_PCE_Pos (10U)
17120 #define USART_CR1_PCE_Msk (0x1U << USART_CR1_PCE_Pos) /*!< 0x00000400 */
17121 #define USART_CR1_PCE USART_CR1_PCE_Msk /*!<Parity Control Enable */
17122 #define USART_CR1_WAKE_Pos (11U)
17123 #define USART_CR1_WAKE_Msk (0x1U << USART_CR1_WAKE_Pos) /*!< 0x00000800 */
17124 #define USART_CR1_WAKE USART_CR1_WAKE_Msk /*!<Wakeup method */
17125 #define USART_CR1_M_Pos (12U)
17126 #define USART_CR1_M_Msk (0x1U << USART_CR1_M_Pos) /*!< 0x00001000 */
17127 #define USART_CR1_M USART_CR1_M_Msk /*!<Word length */
17128 #define USART_CR1_UE_Pos (13U)
17129 #define USART_CR1_UE_Msk (0x1U << USART_CR1_UE_Pos) /*!< 0x00002000 */
17130 #define USART_CR1_UE USART_CR1_UE_Msk /*!<USART Enable */
17131 #define USART_CR1_OVER8_Pos (15U)
17132 #define USART_CR1_OVER8_Msk (0x1U << USART_CR1_OVER8_Pos) /*!< 0x00008000 */
17133 #define USART_CR1_OVER8 USART_CR1_OVER8_Msk /*!<USART Oversampling by 8 enable */
17134
17135 /****************** Bit definition for USART_CR2 register *******************/
17136 #define USART_CR2_ADD_Pos (0U)
17137 #define USART_CR2_ADD_Msk (0xFU << USART_CR2_ADD_Pos) /*!< 0x0000000F */
17138 #define USART_CR2_ADD USART_CR2_ADD_Msk /*!<Address of the USART node */
17139 #define USART_CR2_LBDL_Pos (5U)
17140 #define USART_CR2_LBDL_Msk (0x1U << USART_CR2_LBDL_Pos) /*!< 0x00000020 */
17141 #define USART_CR2_LBDL USART_CR2_LBDL_Msk /*!<LIN Break Detection Length */
17142 #define USART_CR2_LBDIE_Pos (6U)
17143 #define USART_CR2_LBDIE_Msk (0x1U << USART_CR2_LBDIE_Pos) /*!< 0x00000040 */
17144 #define USART_CR2_LBDIE USART_CR2_LBDIE_Msk /*!<LIN Break Detection Interrupt Enable */
17145 #define USART_CR2_LBCL_Pos (8U)
17146 #define USART_CR2_LBCL_Msk (0x1U << USART_CR2_LBCL_Pos) /*!< 0x00000100 */
17147 #define USART_CR2_LBCL USART_CR2_LBCL_Msk /*!<Last Bit Clock pulse */
17148 #define USART_CR2_CPHA_Pos (9U)
17149 #define USART_CR2_CPHA_Msk (0x1U << USART_CR2_CPHA_Pos) /*!< 0x00000200 */
17150 #define USART_CR2_CPHA USART_CR2_CPHA_Msk /*!<Clock Phase */
17151 #define USART_CR2_CPOL_Pos (10U)
17152 #define USART_CR2_CPOL_Msk (0x1U << USART_CR2_CPOL_Pos) /*!< 0x00000400 */
17153 #define USART_CR2_CPOL USART_CR2_CPOL_Msk /*!<Clock Polarity */
17154 #define USART_CR2_CLKEN_Pos (11U)
17155 #define USART_CR2_CLKEN_Msk (0x1U << USART_CR2_CLKEN_Pos) /*!< 0x00000800 */
17156 #define USART_CR2_CLKEN USART_CR2_CLKEN_Msk /*!<Clock Enable */
17157
17158 #define USART_CR2_STOP_Pos (12U)
17159 #define USART_CR2_STOP_Msk (0x3U << USART_CR2_STOP_Pos) /*!< 0x00003000 */
17160 #define USART_CR2_STOP USART_CR2_STOP_Msk /*!<STOP[1:0] bits (STOP bits) */
17161 #define USART_CR2_STOP_0 (0x1U << USART_CR2_STOP_Pos) /*!< 0x1000 */
17162 #define USART_CR2_STOP_1 (0x2U << USART_CR2_STOP_Pos) /*!< 0x2000 */
17163
17164 #define USART_CR2_LINEN_Pos (14U)
17165 #define USART_CR2_LINEN_Msk (0x1U << USART_CR2_LINEN_Pos) /*!< 0x00004000 */
17166 #define USART_CR2_LINEN USART_CR2_LINEN_Msk /*!<LIN mode enable */
17167
17168 /****************** Bit definition for USART_CR3 register *******************/
17169 #define USART_CR3_EIE_Pos (0U)
17170 #define USART_CR3_EIE_Msk (0x1U << USART_CR3_EIE_Pos) /*!< 0x00000001 */
17171 #define USART_CR3_EIE USART_CR3_EIE_Msk /*!<Error Interrupt Enable */
17172 #define USART_CR3_IREN_Pos (1U)
17173 #define USART_CR3_IREN_Msk (0x1U << USART_CR3_IREN_Pos) /*!< 0x00000002 */
17174 #define USART_CR3_IREN USART_CR3_IREN_Msk /*!<IrDA mode Enable */
17175 #define USART_CR3_IRLP_Pos (2U)
17176 #define USART_CR3_IRLP_Msk (0x1U << USART_CR3_IRLP_Pos) /*!< 0x00000004 */
17177 #define USART_CR3_IRLP USART_CR3_IRLP_Msk /*!<IrDA Low-Power */
17178 #define USART_CR3_HDSEL_Pos (3U)
17179 #define USART_CR3_HDSEL_Msk (0x1U << USART_CR3_HDSEL_Pos) /*!< 0x00000008 */
17180 #define USART_CR3_HDSEL USART_CR3_HDSEL_Msk /*!<Half-Duplex Selection */
17181 #define USART_CR3_NACK_Pos (4U)
17182 #define USART_CR3_NACK_Msk (0x1U << USART_CR3_NACK_Pos) /*!< 0x00000010 */
17183 #define USART_CR3_NACK USART_CR3_NACK_Msk /*!<Smartcard NACK enable */
17184 #define USART_CR3_SCEN_Pos (5U)
17185 #define USART_CR3_SCEN_Msk (0x1U << USART_CR3_SCEN_Pos) /*!< 0x00000020 */
17186 #define USART_CR3_SCEN USART_CR3_SCEN_Msk /*!<Smartcard mode enable */
17187 #define USART_CR3_DMAR_Pos (6U)
17188 #define USART_CR3_DMAR_Msk (0x1U << USART_CR3_DMAR_Pos) /*!< 0x00000040 */
17189 #define USART_CR3_DMAR USART_CR3_DMAR_Msk /*!<DMA Enable Receiver */
17190 #define USART_CR3_DMAT_Pos (7U)
17191 #define USART_CR3_DMAT_Msk (0x1U << USART_CR3_DMAT_Pos) /*!< 0x00000080 */
17192 #define USART_CR3_DMAT USART_CR3_DMAT_Msk /*!<DMA Enable Transmitter */
17193 #define USART_CR3_RTSE_Pos (8U)
17194 #define USART_CR3_RTSE_Msk (0x1U << USART_CR3_RTSE_Pos) /*!< 0x00000100 */
17195 #define USART_CR3_RTSE USART_CR3_RTSE_Msk /*!<RTS Enable */
17196 #define USART_CR3_CTSE_Pos (9U)
17197 #define USART_CR3_CTSE_Msk (0x1U << USART_CR3_CTSE_Pos) /*!< 0x00000200 */
17198 #define USART_CR3_CTSE USART_CR3_CTSE_Msk /*!<CTS Enable */
17199 #define USART_CR3_CTSIE_Pos (10U)
17200 #define USART_CR3_CTSIE_Msk (0x1U << USART_CR3_CTSIE_Pos) /*!< 0x00000400 */
17201 #define USART_CR3_CTSIE USART_CR3_CTSIE_Msk /*!<CTS Interrupt Enable */
17202 #define USART_CR3_ONEBIT_Pos (11U)
17203 #define USART_CR3_ONEBIT_Msk (0x1U << USART_CR3_ONEBIT_Pos) /*!< 0x00000800 */
17204 #define USART_CR3_ONEBIT USART_CR3_ONEBIT_Msk /*!<USART One bit method enable */
17205
17206 /****************** Bit definition for USART_GTPR register ******************/
17207 #define USART_GTPR_PSC_Pos (0U)
17208 #define USART_GTPR_PSC_Msk (0xFFU << USART_GTPR_PSC_Pos) /*!< 0x000000FF */
17209 #define USART_GTPR_PSC USART_GTPR_PSC_Msk /*!<PSC[7:0] bits (Prescaler value) */
17210 #define USART_GTPR_PSC_0 (0x01U << USART_GTPR_PSC_Pos) /*!< 0x0001 */
17211 #define USART_GTPR_PSC_1 (0x02U << USART_GTPR_PSC_Pos) /*!< 0x0002 */
17212 #define USART_GTPR_PSC_2 (0x04U << USART_GTPR_PSC_Pos) /*!< 0x0004 */
17213 #define USART_GTPR_PSC_3 (0x08U << USART_GTPR_PSC_Pos) /*!< 0x0008 */
17214 #define USART_GTPR_PSC_4 (0x10U << USART_GTPR_PSC_Pos) /*!< 0x0010 */
17215 #define USART_GTPR_PSC_5 (0x20U << USART_GTPR_PSC_Pos) /*!< 0x0020 */
17216 #define USART_GTPR_PSC_6 (0x40U << USART_GTPR_PSC_Pos) /*!< 0x0040 */
17217 #define USART_GTPR_PSC_7 (0x80U << USART_GTPR_PSC_Pos) /*!< 0x0080 */
17218
17219 #define USART_GTPR_GT_Pos (8U)
17220 #define USART_GTPR_GT_Msk (0xFFU << USART_GTPR_GT_Pos) /*!< 0x0000FF00 */
17221 #define USART_GTPR_GT USART_GTPR_GT_Msk /*!<Guard time value */
17222
17223 /******************************************************************************/
17224 /* */
17225 /* Window WATCHDOG */
17226 /* */
17227 /******************************************************************************/
17228 /******************* Bit definition for WWDG_CR register ********************/
17229 #define WWDG_CR_T_Pos (0U)
17230 #define WWDG_CR_T_Msk (0x7FU << WWDG_CR_T_Pos) /*!< 0x0000007F */
17231 #define WWDG_CR_T WWDG_CR_T_Msk /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
17232 #define WWDG_CR_T_0 (0x01U << WWDG_CR_T_Pos) /*!< 0x01 */
17233 #define WWDG_CR_T_1 (0x02U << WWDG_CR_T_Pos) /*!< 0x02 */
17234 #define WWDG_CR_T_2 (0x04U << WWDG_CR_T_Pos) /*!< 0x04 */
17235 #define WWDG_CR_T_3 (0x08U << WWDG_CR_T_Pos) /*!< 0x08 */
17236 #define WWDG_CR_T_4 (0x10U << WWDG_CR_T_Pos) /*!< 0x10 */
17237 #define WWDG_CR_T_5 (0x20U << WWDG_CR_T_Pos) /*!< 0x20 */
17238 #define WWDG_CR_T_6 (0x40U << WWDG_CR_T_Pos) /*!< 0x40 */
17239 /* Legacy defines */
17240 #define WWDG_CR_T0 WWDG_CR_T_0
17241 #define WWDG_CR_T1 WWDG_CR_T_1
17242 #define WWDG_CR_T2 WWDG_CR_T_2
17243 #define WWDG_CR_T3 WWDG_CR_T_3
17244 #define WWDG_CR_T4 WWDG_CR_T_4
17245 #define WWDG_CR_T5 WWDG_CR_T_5
17246 #define WWDG_CR_T6 WWDG_CR_T_6
17247
17248 #define WWDG_CR_WDGA_Pos (7U)
17249 #define WWDG_CR_WDGA_Msk (0x1U << WWDG_CR_WDGA_Pos) /*!< 0x00000080 */
17250 #define WWDG_CR_WDGA WWDG_CR_WDGA_Msk /*!<Activation bit */
17251
17252 /******************* Bit definition for WWDG_CFR register *******************/
17253 #define WWDG_CFR_W_Pos (0U)
17254 #define WWDG_CFR_W_Msk (0x7FU << WWDG_CFR_W_Pos) /*!< 0x0000007F */
17255 #define WWDG_CFR_W WWDG_CFR_W_Msk /*!<W[6:0] bits (7-bit window value) */
17256 #define WWDG_CFR_W_0 (0x01U << WWDG_CFR_W_Pos) /*!< 0x0001 */
17257 #define WWDG_CFR_W_1 (0x02U << WWDG_CFR_W_Pos) /*!< 0x0002 */
17258 #define WWDG_CFR_W_2 (0x04U << WWDG_CFR_W_Pos) /*!< 0x0004 */
17259 #define WWDG_CFR_W_3 (0x08U << WWDG_CFR_W_Pos) /*!< 0x0008 */
17260 #define WWDG_CFR_W_4 (0x10U << WWDG_CFR_W_Pos) /*!< 0x0010 */
17261 #define WWDG_CFR_W_5 (0x20U << WWDG_CFR_W_Pos) /*!< 0x0020 */
17262 #define WWDG_CFR_W_6 (0x40U << WWDG_CFR_W_Pos) /*!< 0x0040 */
17263 /* Legacy defines */
17264 #define WWDG_CFR_W0 WWDG_CFR_W_0
17265 #define WWDG_CFR_W1 WWDG_CFR_W_1
17266 #define WWDG_CFR_W2 WWDG_CFR_W_2
17267 #define WWDG_CFR_W3 WWDG_CFR_W_3
17268 #define WWDG_CFR_W4 WWDG_CFR_W_4
17269 #define WWDG_CFR_W5 WWDG_CFR_W_5
17270 #define WWDG_CFR_W6 WWDG_CFR_W_6
17271
17272 #define WWDG_CFR_WDGTB_Pos (7U)
17273 #define WWDG_CFR_WDGTB_Msk (0x3U << WWDG_CFR_WDGTB_Pos) /*!< 0x00000180 */
17274 #define WWDG_CFR_WDGTB WWDG_CFR_WDGTB_Msk /*!<WDGTB[1:0] bits (Timer Base) */
17275 #define WWDG_CFR_WDGTB_0 (0x1U << WWDG_CFR_WDGTB_Pos) /*!< 0x0080 */
17276 #define WWDG_CFR_WDGTB_1 (0x2U << WWDG_CFR_WDGTB_Pos) /*!< 0x0100 */
17277 /* Legacy defines */
17278 #define WWDG_CFR_WDGTB0 WWDG_CFR_WDGTB_0
17279 #define WWDG_CFR_WDGTB1 WWDG_CFR_WDGTB_1
17280
17281 #define WWDG_CFR_EWI_Pos (9U)
17282 #define WWDG_CFR_EWI_Msk (0x1U << WWDG_CFR_EWI_Pos) /*!< 0x00000200 */
17283 #define WWDG_CFR_EWI WWDG_CFR_EWI_Msk /*!<Early Wakeup Interrupt */
17284
17285 /******************* Bit definition for WWDG_SR register ********************/
17286 #define WWDG_SR_EWIF_Pos (0U)
17287 #define WWDG_SR_EWIF_Msk (0x1U << WWDG_SR_EWIF_Pos) /*!< 0x00000001 */
17288 #define WWDG_SR_EWIF WWDG_SR_EWIF_Msk /*!<Early Wakeup Interrupt Flag */
17289
17290
17291 /******************************************************************************/
17292 /* */
17293 /* DBG */
17294 /* */
17295 /******************************************************************************/
17296 /******************** Bit definition for DBGMCU_IDCODE register *************/
17297 #define DBGMCU_IDCODE_DEV_ID_Pos (0U)
17298 #define DBGMCU_IDCODE_DEV_ID_Msk (0xFFFU << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */
17299 #define DBGMCU_IDCODE_DEV_ID DBGMCU_IDCODE_DEV_ID_Msk
17300 #define DBGMCU_IDCODE_REV_ID_Pos (16U)
17301 #define DBGMCU_IDCODE_REV_ID_Msk (0xFFFFU << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */
17302 #define DBGMCU_IDCODE_REV_ID DBGMCU_IDCODE_REV_ID_Msk
17303
17304 /******************** Bit definition for DBGMCU_CR register *****************/
17305 #define DBGMCU_CR_DBG_SLEEP_Pos (0U)
17306 #define DBGMCU_CR_DBG_SLEEP_Msk (0x1U << DBGMCU_CR_DBG_SLEEP_Pos) /*!< 0x00000001 */
17307 #define DBGMCU_CR_DBG_SLEEP DBGMCU_CR_DBG_SLEEP_Msk
17308 #define DBGMCU_CR_DBG_STOP_Pos (1U)
17309 #define DBGMCU_CR_DBG_STOP_Msk (0x1U << DBGMCU_CR_DBG_STOP_Pos) /*!< 0x00000002 */
17310 #define DBGMCU_CR_DBG_STOP DBGMCU_CR_DBG_STOP_Msk
17311 #define DBGMCU_CR_DBG_STANDBY_Pos (2U)
17312 #define DBGMCU_CR_DBG_STANDBY_Msk (0x1U << DBGMCU_CR_DBG_STANDBY_Pos) /*!< 0x00000004 */
17313 #define DBGMCU_CR_DBG_STANDBY DBGMCU_CR_DBG_STANDBY_Msk
17314 #define DBGMCU_CR_TRACE_IOEN_Pos (5U)
17315 #define DBGMCU_CR_TRACE_IOEN_Msk (0x1U << DBGMCU_CR_TRACE_IOEN_Pos) /*!< 0x00000020 */
17316 #define DBGMCU_CR_TRACE_IOEN DBGMCU_CR_TRACE_IOEN_Msk
17317
17318 #define DBGMCU_CR_TRACE_MODE_Pos (6U)
17319 #define DBGMCU_CR_TRACE_MODE_Msk (0x3U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x000000C0 */
17320 #define DBGMCU_CR_TRACE_MODE DBGMCU_CR_TRACE_MODE_Msk
17321 #define DBGMCU_CR_TRACE_MODE_0 (0x1U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000040 */
17322 #define DBGMCU_CR_TRACE_MODE_1 (0x2U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000080 */
17323
17324 /******************** Bit definition for DBGMCU_APB1_FZ register ************/
17325 #define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos (0U)
17326 #define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos) /*!< 0x00000001 */
17327 #define DBGMCU_APB1_FZ_DBG_TIM2_STOP DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk
17328 #define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos (1U)
17329 #define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos) /*!< 0x00000002 */
17330 #define DBGMCU_APB1_FZ_DBG_TIM3_STOP DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk
17331 #define DBGMCU_APB1_FZ_DBG_TIM4_STOP_Pos (2U)
17332 #define DBGMCU_APB1_FZ_DBG_TIM4_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM4_STOP_Pos) /*!< 0x00000004 */
17333 #define DBGMCU_APB1_FZ_DBG_TIM4_STOP DBGMCU_APB1_FZ_DBG_TIM4_STOP_Msk
17334 #define DBGMCU_APB1_FZ_DBG_TIM5_STOP_Pos (3U)
17335 #define DBGMCU_APB1_FZ_DBG_TIM5_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM5_STOP_Pos) /*!< 0x00000008 */
17336 #define DBGMCU_APB1_FZ_DBG_TIM5_STOP DBGMCU_APB1_FZ_DBG_TIM5_STOP_Msk
17337 #define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos (4U)
17338 #define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos) /*!< 0x00000010 */
17339 #define DBGMCU_APB1_FZ_DBG_TIM6_STOP DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk
17340 #define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos (5U)
17341 #define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos) /*!< 0x00000020 */
17342 #define DBGMCU_APB1_FZ_DBG_TIM7_STOP DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk
17343 #define DBGMCU_APB1_FZ_DBG_TIM12_STOP_Pos (6U)
17344 #define DBGMCU_APB1_FZ_DBG_TIM12_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM12_STOP_Pos) /*!< 0x00000040 */
17345 #define DBGMCU_APB1_FZ_DBG_TIM12_STOP DBGMCU_APB1_FZ_DBG_TIM12_STOP_Msk
17346 #define DBGMCU_APB1_FZ_DBG_TIM13_STOP_Pos (7U)
17347 #define DBGMCU_APB1_FZ_DBG_TIM13_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM13_STOP_Pos) /*!< 0x00000080 */
17348 #define DBGMCU_APB1_FZ_DBG_TIM13_STOP DBGMCU_APB1_FZ_DBG_TIM13_STOP_Msk
17349 #define DBGMCU_APB1_FZ_DBG_TIM14_STOP_Pos (8U)
17350 #define DBGMCU_APB1_FZ_DBG_TIM14_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM14_STOP_Pos) /*!< 0x00000100 */
17351 #define DBGMCU_APB1_FZ_DBG_TIM14_STOP DBGMCU_APB1_FZ_DBG_TIM14_STOP_Msk
17352 #define DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos (10U)
17353 #define DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos) /*!< 0x00000400 */
17354 #define DBGMCU_APB1_FZ_DBG_RTC_STOP DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk
17355 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos (11U)
17356 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos) /*!< 0x00000800 */
17357 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk
17358 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos (12U)
17359 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos) /*!< 0x00001000 */
17360 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk
17361 #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos (21U)
17362 #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk (0x1U << DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos) /*!< 0x00200000 */
17363 #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk
17364 #define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Pos (22U)
17365 #define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Msk (0x1U << DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Pos) /*!< 0x00400000 */
17366 #define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Msk
17367 #define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Pos (23U)
17368 #define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Msk (0x1U << DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Pos) /*!< 0x00800000 */
17369 #define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Msk
17370 #define DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT_Pos (24U)
17371 #define DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT_Msk (0x1U << DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT_Pos) /*!< 0x01000000 */
17372 #define DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT_Msk
17373 #define DBGMCU_APB1_FZ_DBG_CAN1_STOP_Pos (25U)
17374 #define DBGMCU_APB1_FZ_DBG_CAN1_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_CAN1_STOP_Pos) /*!< 0x02000000 */
17375 #define DBGMCU_APB1_FZ_DBG_CAN1_STOP DBGMCU_APB1_FZ_DBG_CAN1_STOP_Msk
17376 #define DBGMCU_APB1_FZ_DBG_CAN2_STOP_Pos (26U)
17377 #define DBGMCU_APB1_FZ_DBG_CAN2_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_CAN2_STOP_Pos) /*!< 0x04000000 */
17378 #define DBGMCU_APB1_FZ_DBG_CAN2_STOP DBGMCU_APB1_FZ_DBG_CAN2_STOP_Msk
17379 /* Old IWDGSTOP bit definition, maintained for legacy purpose */
17380 #define DBGMCU_APB1_FZ_DBG_IWDEG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP
17381
17382 /******************** Bit definition for DBGMCU_APB2_FZ register ************/
17383 #define DBGMCU_APB2_FZ_DBG_TIM1_STOP_Pos (0U)
17384 #define DBGMCU_APB2_FZ_DBG_TIM1_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM1_STOP_Pos) /*!< 0x00000001 */
17385 #define DBGMCU_APB2_FZ_DBG_TIM1_STOP DBGMCU_APB2_FZ_DBG_TIM1_STOP_Msk
17386 #define DBGMCU_APB2_FZ_DBG_TIM8_STOP_Pos (1U)
17387 #define DBGMCU_APB2_FZ_DBG_TIM8_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM8_STOP_Pos) /*!< 0x00000002 */
17388 #define DBGMCU_APB2_FZ_DBG_TIM8_STOP DBGMCU_APB2_FZ_DBG_TIM8_STOP_Msk
17389 #define DBGMCU_APB2_FZ_DBG_TIM9_STOP_Pos (16U)
17390 #define DBGMCU_APB2_FZ_DBG_TIM9_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM9_STOP_Pos) /*!< 0x00010000 */
17391 #define DBGMCU_APB2_FZ_DBG_TIM9_STOP DBGMCU_APB2_FZ_DBG_TIM9_STOP_Msk
17392 #define DBGMCU_APB2_FZ_DBG_TIM10_STOP_Pos (17U)
17393 #define DBGMCU_APB2_FZ_DBG_TIM10_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM10_STOP_Pos) /*!< 0x00020000 */
17394 #define DBGMCU_APB2_FZ_DBG_TIM10_STOP DBGMCU_APB2_FZ_DBG_TIM10_STOP_Msk
17395 #define DBGMCU_APB2_FZ_DBG_TIM11_STOP_Pos (18U)
17396 #define DBGMCU_APB2_FZ_DBG_TIM11_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM11_STOP_Pos) /*!< 0x00040000 */
17397 #define DBGMCU_APB2_FZ_DBG_TIM11_STOP DBGMCU_APB2_FZ_DBG_TIM11_STOP_Msk
17398
17399 /******************************************************************************/
17400 /* */
17401 /* Ethernet MAC Registers bits definitions */
17402 /* */
17403 /******************************************************************************/
17404 /* Bit definition for Ethernet MAC Control Register register */
17405 #define ETH_MACCR_WD_Pos (23U)
17406 #define ETH_MACCR_WD_Msk (0x1U << ETH_MACCR_WD_Pos) /*!< 0x00800000 */
17407 #define ETH_MACCR_WD ETH_MACCR_WD_Msk /* Watchdog disable */
17408 #define ETH_MACCR_JD_Pos (22U)
17409 #define ETH_MACCR_JD_Msk (0x1U << ETH_MACCR_JD_Pos) /*!< 0x00400000 */
17410 #define ETH_MACCR_JD ETH_MACCR_JD_Msk /* Jabber disable */
17411 #define ETH_MACCR_IFG_Pos (17U)
17412 #define ETH_MACCR_IFG_Msk (0x7U << ETH_MACCR_IFG_Pos) /*!< 0x000E0000 */
17413 #define ETH_MACCR_IFG ETH_MACCR_IFG_Msk /* Inter-frame gap */
17414 #define ETH_MACCR_IFG_96Bit 0x00000000U /* Minimum IFG between frames during transmission is 96Bit */
17415 #define ETH_MACCR_IFG_88Bit 0x00020000U /* Minimum IFG between frames during transmission is 88Bit */
17416 #define ETH_MACCR_IFG_80Bit 0x00040000U /* Minimum IFG between frames during transmission is 80Bit */
17417 #define ETH_MACCR_IFG_72Bit 0x00060000U /* Minimum IFG between frames during transmission is 72Bit */
17418 #define ETH_MACCR_IFG_64Bit 0x00080000U /* Minimum IFG between frames during transmission is 64Bit */
17419 #define ETH_MACCR_IFG_56Bit 0x000A0000U /* Minimum IFG between frames during transmission is 56Bit */
17420 #define ETH_MACCR_IFG_48Bit 0x000C0000U /* Minimum IFG between frames during transmission is 48Bit */
17421 #define ETH_MACCR_IFG_40Bit 0x000E0000U /* Minimum IFG between frames during transmission is 40Bit */
17422 #define ETH_MACCR_CSD_Pos (16U)
17423 #define ETH_MACCR_CSD_Msk (0x1U << ETH_MACCR_CSD_Pos) /*!< 0x00010000 */
17424 #define ETH_MACCR_CSD ETH_MACCR_CSD_Msk /* Carrier sense disable (during transmission) */
17425 #define ETH_MACCR_FES_Pos (14U)
17426 #define ETH_MACCR_FES_Msk (0x1U << ETH_MACCR_FES_Pos) /*!< 0x00004000 */
17427 #define ETH_MACCR_FES ETH_MACCR_FES_Msk /* Fast ethernet speed */
17428 #define ETH_MACCR_ROD_Pos (13U)
17429 #define ETH_MACCR_ROD_Msk (0x1U << ETH_MACCR_ROD_Pos) /*!< 0x00002000 */
17430 #define ETH_MACCR_ROD ETH_MACCR_ROD_Msk /* Receive own disable */
17431 #define ETH_MACCR_LM_Pos (12U)
17432 #define ETH_MACCR_LM_Msk (0x1U << ETH_MACCR_LM_Pos) /*!< 0x00001000 */
17433 #define ETH_MACCR_LM ETH_MACCR_LM_Msk /* loopback mode */
17434 #define ETH_MACCR_DM_Pos (11U)
17435 #define ETH_MACCR_DM_Msk (0x1U << ETH_MACCR_DM_Pos) /*!< 0x00000800 */
17436 #define ETH_MACCR_DM ETH_MACCR_DM_Msk /* Duplex mode */
17437 #define ETH_MACCR_IPCO_Pos (10U)
17438 #define ETH_MACCR_IPCO_Msk (0x1U << ETH_MACCR_IPCO_Pos) /*!< 0x00000400 */
17439 #define ETH_MACCR_IPCO ETH_MACCR_IPCO_Msk /* IP Checksum offload */
17440 #define ETH_MACCR_RD_Pos (9U)
17441 #define ETH_MACCR_RD_Msk (0x1U << ETH_MACCR_RD_Pos) /*!< 0x00000200 */
17442 #define ETH_MACCR_RD ETH_MACCR_RD_Msk /* Retry disable */
17443 #define ETH_MACCR_APCS_Pos (7U)
17444 #define ETH_MACCR_APCS_Msk (0x1U << ETH_MACCR_APCS_Pos) /*!< 0x00000080 */
17445 #define ETH_MACCR_APCS ETH_MACCR_APCS_Msk /* Automatic Pad/CRC stripping */
17446 #define ETH_MACCR_BL_Pos (5U)
17447 #define ETH_MACCR_BL_Msk (0x3U << ETH_MACCR_BL_Pos) /*!< 0x00000060 */
17448 #define ETH_MACCR_BL ETH_MACCR_BL_Msk /* Back-off limit: random integer number (r) of slot time delays before rescheduling
17449 a transmission attempt during retries after a collision: 0 =< r <2^k */
17450 #define ETH_MACCR_BL_10 0x00000000U /* k = min (n, 10) */
17451 #define ETH_MACCR_BL_8 0x00000020U /* k = min (n, 8) */
17452 #define ETH_MACCR_BL_4 0x00000040U /* k = min (n, 4) */
17453 #define ETH_MACCR_BL_1 0x00000060U /* k = min (n, 1) */
17454 #define ETH_MACCR_DC_Pos (4U)
17455 #define ETH_MACCR_DC_Msk (0x1U << ETH_MACCR_DC_Pos) /*!< 0x00000010 */
17456 #define ETH_MACCR_DC ETH_MACCR_DC_Msk /* Defferal check */
17457 #define ETH_MACCR_TE_Pos (3U)
17458 #define ETH_MACCR_TE_Msk (0x1U << ETH_MACCR_TE_Pos) /*!< 0x00000008 */
17459 #define ETH_MACCR_TE ETH_MACCR_TE_Msk /* Transmitter enable */
17460 #define ETH_MACCR_RE_Pos (2U)
17461 #define ETH_MACCR_RE_Msk (0x1U << ETH_MACCR_RE_Pos) /*!< 0x00000004 */
17462 #define ETH_MACCR_RE ETH_MACCR_RE_Msk /* Receiver enable */
17463
17464 /* Bit definition for Ethernet MAC Frame Filter Register */
17465 #define ETH_MACFFR_RA_Pos (31U)
17466 #define ETH_MACFFR_RA_Msk (0x1U << ETH_MACFFR_RA_Pos) /*!< 0x80000000 */
17467 #define ETH_MACFFR_RA ETH_MACFFR_RA_Msk /* Receive all */
17468 #define ETH_MACFFR_HPF_Pos (10U)
17469 #define ETH_MACFFR_HPF_Msk (0x1U << ETH_MACFFR_HPF_Pos) /*!< 0x00000400 */
17470 #define ETH_MACFFR_HPF ETH_MACFFR_HPF_Msk /* Hash or perfect filter */
17471 #define ETH_MACFFR_SAF_Pos (9U)
17472 #define ETH_MACFFR_SAF_Msk (0x1U << ETH_MACFFR_SAF_Pos) /*!< 0x00000200 */
17473 #define ETH_MACFFR_SAF ETH_MACFFR_SAF_Msk /* Source address filter enable */
17474 #define ETH_MACFFR_SAIF_Pos (8U)
17475 #define ETH_MACFFR_SAIF_Msk (0x1U << ETH_MACFFR_SAIF_Pos) /*!< 0x00000100 */
17476 #define ETH_MACFFR_SAIF ETH_MACFFR_SAIF_Msk /* SA inverse filtering */
17477 #define ETH_MACFFR_PCF_Pos (6U)
17478 #define ETH_MACFFR_PCF_Msk (0x3U << ETH_MACFFR_PCF_Pos) /*!< 0x000000C0 */
17479 #define ETH_MACFFR_PCF ETH_MACFFR_PCF_Msk /* Pass control frames: 3 cases */
17480 #define ETH_MACFFR_PCF_BlockAll_Pos (6U)
17481 #define ETH_MACFFR_PCF_BlockAll_Msk (0x1U << ETH_MACFFR_PCF_BlockAll_Pos) /*!< 0x00000040 */
17482 #define ETH_MACFFR_PCF_BlockAll ETH_MACFFR_PCF_BlockAll_Msk /* MAC filters all control frames from reaching the application */
17483 #define ETH_MACFFR_PCF_ForwardAll_Pos (7U)
17484 #define ETH_MACFFR_PCF_ForwardAll_Msk (0x1U << ETH_MACFFR_PCF_ForwardAll_Pos) /*!< 0x00000080 */
17485 #define ETH_MACFFR_PCF_ForwardAll ETH_MACFFR_PCF_ForwardAll_Msk /* MAC forwards all control frames to application even if they fail the Address Filter */
17486 #define ETH_MACFFR_PCF_ForwardPassedAddrFilter_Pos (6U)
17487 #define ETH_MACFFR_PCF_ForwardPassedAddrFilter_Msk (0x3U << ETH_MACFFR_PCF_ForwardPassedAddrFilter_Pos) /*!< 0x000000C0 */
17488 #define ETH_MACFFR_PCF_ForwardPassedAddrFilter ETH_MACFFR_PCF_ForwardPassedAddrFilter_Msk /* MAC forwards control frames that pass the Address Filter. */
17489 #define ETH_MACFFR_BFD_Pos (5U)
17490 #define ETH_MACFFR_BFD_Msk (0x1U << ETH_MACFFR_BFD_Pos) /*!< 0x00000020 */
17491 #define ETH_MACFFR_BFD ETH_MACFFR_BFD_Msk /* Broadcast frame disable */
17492 #define ETH_MACFFR_PAM_Pos (4U)
17493 #define ETH_MACFFR_PAM_Msk (0x1U << ETH_MACFFR_PAM_Pos) /*!< 0x00000010 */
17494 #define ETH_MACFFR_PAM ETH_MACFFR_PAM_Msk /* Pass all mutlicast */
17495 #define ETH_MACFFR_DAIF_Pos (3U)
17496 #define ETH_MACFFR_DAIF_Msk (0x1U << ETH_MACFFR_DAIF_Pos) /*!< 0x00000008 */
17497 #define ETH_MACFFR_DAIF ETH_MACFFR_DAIF_Msk /* DA Inverse filtering */
17498 #define ETH_MACFFR_HM_Pos (2U)
17499 #define ETH_MACFFR_HM_Msk (0x1U << ETH_MACFFR_HM_Pos) /*!< 0x00000004 */
17500 #define ETH_MACFFR_HM ETH_MACFFR_HM_Msk /* Hash multicast */
17501 #define ETH_MACFFR_HU_Pos (1U)
17502 #define ETH_MACFFR_HU_Msk (0x1U << ETH_MACFFR_HU_Pos) /*!< 0x00000002 */
17503 #define ETH_MACFFR_HU ETH_MACFFR_HU_Msk /* Hash unicast */
17504 #define ETH_MACFFR_PM_Pos (0U)
17505 #define ETH_MACFFR_PM_Msk (0x1U << ETH_MACFFR_PM_Pos) /*!< 0x00000001 */
17506 #define ETH_MACFFR_PM ETH_MACFFR_PM_Msk /* Promiscuous mode */
17507
17508 /* Bit definition for Ethernet MAC Hash Table High Register */
17509 #define ETH_MACHTHR_HTH_Pos (0U)
17510 #define ETH_MACHTHR_HTH_Msk (0xFFFFFFFFU << ETH_MACHTHR_HTH_Pos) /*!< 0xFFFFFFFF */
17511 #define ETH_MACHTHR_HTH ETH_MACHTHR_HTH_Msk /* Hash table high */
17512
17513 /* Bit definition for Ethernet MAC Hash Table Low Register */
17514 #define ETH_MACHTLR_HTL_Pos (0U)
17515 #define ETH_MACHTLR_HTL_Msk (0xFFFFFFFFU << ETH_MACHTLR_HTL_Pos) /*!< 0xFFFFFFFF */
17516 #define ETH_MACHTLR_HTL ETH_MACHTLR_HTL_Msk /* Hash table low */
17517
17518 /* Bit definition for Ethernet MAC MII Address Register */
17519 #define ETH_MACMIIAR_PA_Pos (11U)
17520 #define ETH_MACMIIAR_PA_Msk (0x1FU << ETH_MACMIIAR_PA_Pos) /*!< 0x0000F800 */
17521 #define ETH_MACMIIAR_PA ETH_MACMIIAR_PA_Msk /* Physical layer address */
17522 #define ETH_MACMIIAR_MR_Pos (6U)
17523 #define ETH_MACMIIAR_MR_Msk (0x1FU << ETH_MACMIIAR_MR_Pos) /*!< 0x000007C0 */
17524 #define ETH_MACMIIAR_MR ETH_MACMIIAR_MR_Msk /* MII register in the selected PHY */
17525 #define ETH_MACMIIAR_CR_Pos (2U)
17526 #define ETH_MACMIIAR_CR_Msk (0x7U << ETH_MACMIIAR_CR_Pos) /*!< 0x0000001C */
17527 #define ETH_MACMIIAR_CR ETH_MACMIIAR_CR_Msk /* CR clock range: 6 cases */
17528 #define ETH_MACMIIAR_CR_Div42 0x00000000U /* HCLK:60-100 MHz; MDC clock= HCLK/42 */
17529 #define ETH_MACMIIAR_CR_Div62_Pos (2U)
17530 #define ETH_MACMIIAR_CR_Div62_Msk (0x1U << ETH_MACMIIAR_CR_Div62_Pos) /*!< 0x00000004 */
17531 #define ETH_MACMIIAR_CR_Div62 ETH_MACMIIAR_CR_Div62_Msk /* HCLK:100-150 MHz; MDC clock= HCLK/62 */
17532 #define ETH_MACMIIAR_CR_Div16_Pos (3U)
17533 #define ETH_MACMIIAR_CR_Div16_Msk (0x1U << ETH_MACMIIAR_CR_Div16_Pos) /*!< 0x00000008 */
17534 #define ETH_MACMIIAR_CR_Div16 ETH_MACMIIAR_CR_Div16_Msk /* HCLK:20-35 MHz; MDC clock= HCLK/16 */
17535 #define ETH_MACMIIAR_CR_Div26_Pos (2U)
17536 #define ETH_MACMIIAR_CR_Div26_Msk (0x3U << ETH_MACMIIAR_CR_Div26_Pos) /*!< 0x0000000C */
17537 #define ETH_MACMIIAR_CR_Div26 ETH_MACMIIAR_CR_Div26_Msk /* HCLK:35-60 MHz; MDC clock= HCLK/26 */
17538 #define ETH_MACMIIAR_CR_Div102_Pos (4U)
17539 #define ETH_MACMIIAR_CR_Div102_Msk (0x1U << ETH_MACMIIAR_CR_Div102_Pos) /*!< 0x00000010 */
17540 #define ETH_MACMIIAR_CR_Div102 ETH_MACMIIAR_CR_Div102_Msk /* HCLK:150-168 MHz; MDC clock= HCLK/102 */
17541 #define ETH_MACMIIAR_MW_Pos (1U)
17542 #define ETH_MACMIIAR_MW_Msk (0x1U << ETH_MACMIIAR_MW_Pos) /*!< 0x00000002 */
17543 #define ETH_MACMIIAR_MW ETH_MACMIIAR_MW_Msk /* MII write */
17544 #define ETH_MACMIIAR_MB_Pos (0U)
17545 #define ETH_MACMIIAR_MB_Msk (0x1U << ETH_MACMIIAR_MB_Pos) /*!< 0x00000001 */
17546 #define ETH_MACMIIAR_MB ETH_MACMIIAR_MB_Msk /* MII busy */
17547
17548 /* Bit definition for Ethernet MAC MII Data Register */
17549 #define ETH_MACMIIDR_MD_Pos (0U)
17550 #define ETH_MACMIIDR_MD_Msk (0xFFFFU << ETH_MACMIIDR_MD_Pos) /*!< 0x0000FFFF */
17551 #define ETH_MACMIIDR_MD ETH_MACMIIDR_MD_Msk /* MII data: read/write data from/to PHY */
17552
17553 /* Bit definition for Ethernet MAC Flow Control Register */
17554 #define ETH_MACFCR_PT_Pos (16U)
17555 #define ETH_MACFCR_PT_Msk (0xFFFFU << ETH_MACFCR_PT_Pos) /*!< 0xFFFF0000 */
17556 #define ETH_MACFCR_PT ETH_MACFCR_PT_Msk /* Pause time */
17557 #define ETH_MACFCR_ZQPD_Pos (7U)
17558 #define ETH_MACFCR_ZQPD_Msk (0x1U << ETH_MACFCR_ZQPD_Pos) /*!< 0x00000080 */
17559 #define ETH_MACFCR_ZQPD ETH_MACFCR_ZQPD_Msk /* Zero-quanta pause disable */
17560 #define ETH_MACFCR_PLT_Pos (4U)
17561 #define ETH_MACFCR_PLT_Msk (0x3U << ETH_MACFCR_PLT_Pos) /*!< 0x00000030 */
17562 #define ETH_MACFCR_PLT ETH_MACFCR_PLT_Msk /* Pause low threshold: 4 cases */
17563 #define ETH_MACFCR_PLT_Minus4 0x00000000U /* Pause time minus 4 slot times */
17564 #define ETH_MACFCR_PLT_Minus28_Pos (4U)
17565 #define ETH_MACFCR_PLT_Minus28_Msk (0x1U << ETH_MACFCR_PLT_Minus28_Pos) /*!< 0x00000010 */
17566 #define ETH_MACFCR_PLT_Minus28 ETH_MACFCR_PLT_Minus28_Msk /* Pause time minus 28 slot times */
17567 #define ETH_MACFCR_PLT_Minus144_Pos (5U)
17568 #define ETH_MACFCR_PLT_Minus144_Msk (0x1U << ETH_MACFCR_PLT_Minus144_Pos) /*!< 0x00000020 */
17569 #define ETH_MACFCR_PLT_Minus144 ETH_MACFCR_PLT_Minus144_Msk /* Pause time minus 144 slot times */
17570 #define ETH_MACFCR_PLT_Minus256_Pos (4U)
17571 #define ETH_MACFCR_PLT_Minus256_Msk (0x3U << ETH_MACFCR_PLT_Minus256_Pos) /*!< 0x00000030 */
17572 #define ETH_MACFCR_PLT_Minus256 ETH_MACFCR_PLT_Minus256_Msk /* Pause time minus 256 slot times */
17573 #define ETH_MACFCR_UPFD_Pos (3U)
17574 #define ETH_MACFCR_UPFD_Msk (0x1U << ETH_MACFCR_UPFD_Pos) /*!< 0x00000008 */
17575 #define ETH_MACFCR_UPFD ETH_MACFCR_UPFD_Msk /* Unicast pause frame detect */
17576 #define ETH_MACFCR_RFCE_Pos (2U)
17577 #define ETH_MACFCR_RFCE_Msk (0x1U << ETH_MACFCR_RFCE_Pos) /*!< 0x00000004 */
17578 #define ETH_MACFCR_RFCE ETH_MACFCR_RFCE_Msk /* Receive flow control enable */
17579 #define ETH_MACFCR_TFCE_Pos (1U)
17580 #define ETH_MACFCR_TFCE_Msk (0x1U << ETH_MACFCR_TFCE_Pos) /*!< 0x00000002 */
17581 #define ETH_MACFCR_TFCE ETH_MACFCR_TFCE_Msk /* Transmit flow control enable */
17582 #define ETH_MACFCR_FCBBPA_Pos (0U)
17583 #define ETH_MACFCR_FCBBPA_Msk (0x1U << ETH_MACFCR_FCBBPA_Pos) /*!< 0x00000001 */
17584 #define ETH_MACFCR_FCBBPA ETH_MACFCR_FCBBPA_Msk /* Flow control busy/backpressure activate */
17585
17586 /* Bit definition for Ethernet MAC VLAN Tag Register */
17587 #define ETH_MACVLANTR_VLANTC_Pos (16U)
17588 #define ETH_MACVLANTR_VLANTC_Msk (0x1U << ETH_MACVLANTR_VLANTC_Pos) /*!< 0x00010000 */
17589 #define ETH_MACVLANTR_VLANTC ETH_MACVLANTR_VLANTC_Msk /* 12-bit VLAN tag comparison */
17590 #define ETH_MACVLANTR_VLANTI_Pos (0U)
17591 #define ETH_MACVLANTR_VLANTI_Msk (0xFFFFU << ETH_MACVLANTR_VLANTI_Pos) /*!< 0x0000FFFF */
17592 #define ETH_MACVLANTR_VLANTI ETH_MACVLANTR_VLANTI_Msk /* VLAN tag identifier (for receive frames) */
17593
17594 /* Bit definition for Ethernet MAC Remote Wake-UpFrame Filter Register */
17595 #define ETH_MACRWUFFR_D_Pos (0U)
17596 #define ETH_MACRWUFFR_D_Msk (0xFFFFFFFFU << ETH_MACRWUFFR_D_Pos) /*!< 0xFFFFFFFF */
17597 #define ETH_MACRWUFFR_D ETH_MACRWUFFR_D_Msk /* Wake-up frame filter register data */
17598 /* Eight sequential Writes to this address (offset 0x28) will write all Wake-UpFrame Filter Registers.
17599 Eight sequential Reads from this address (offset 0x28) will read all Wake-UpFrame Filter Registers. */
17600 /* Wake-UpFrame Filter Reg0 : Filter 0 Byte Mask
17601 Wake-UpFrame Filter Reg1 : Filter 1 Byte Mask
17602 Wake-UpFrame Filter Reg2 : Filter 2 Byte Mask
17603 Wake-UpFrame Filter Reg3 : Filter 3 Byte Mask
17604 Wake-UpFrame Filter Reg4 : RSVD - Filter3 Command - RSVD - Filter2 Command -
17605 RSVD - Filter1 Command - RSVD - Filter0 Command
17606 Wake-UpFrame Filter Re5 : Filter3 Offset - Filter2 Offset - Filter1 Offset - Filter0 Offset
17607 Wake-UpFrame Filter Re6 : Filter1 CRC16 - Filter0 CRC16
17608 Wake-UpFrame Filter Re7 : Filter3 CRC16 - Filter2 CRC16 */
17609
17610 /* Bit definition for Ethernet MAC PMT Control and Status Register */
17611 #define ETH_MACPMTCSR_WFFRPR_Pos (31U)
17612 #define ETH_MACPMTCSR_WFFRPR_Msk (0x1U << ETH_MACPMTCSR_WFFRPR_Pos) /*!< 0x80000000 */
17613 #define ETH_MACPMTCSR_WFFRPR ETH_MACPMTCSR_WFFRPR_Msk /* Wake-Up Frame Filter Register Pointer Reset */
17614 #define ETH_MACPMTCSR_GU_Pos (9U)
17615 #define ETH_MACPMTCSR_GU_Msk (0x1U << ETH_MACPMTCSR_GU_Pos) /*!< 0x00000200 */
17616 #define ETH_MACPMTCSR_GU ETH_MACPMTCSR_GU_Msk /* Global Unicast */
17617 #define ETH_MACPMTCSR_WFR_Pos (6U)
17618 #define ETH_MACPMTCSR_WFR_Msk (0x1U << ETH_MACPMTCSR_WFR_Pos) /*!< 0x00000040 */
17619 #define ETH_MACPMTCSR_WFR ETH_MACPMTCSR_WFR_Msk /* Wake-Up Frame Received */
17620 #define ETH_MACPMTCSR_MPR_Pos (5U)
17621 #define ETH_MACPMTCSR_MPR_Msk (0x1U << ETH_MACPMTCSR_MPR_Pos) /*!< 0x00000020 */
17622 #define ETH_MACPMTCSR_MPR ETH_MACPMTCSR_MPR_Msk /* Magic Packet Received */
17623 #define ETH_MACPMTCSR_WFE_Pos (2U)
17624 #define ETH_MACPMTCSR_WFE_Msk (0x1U << ETH_MACPMTCSR_WFE_Pos) /*!< 0x00000004 */
17625 #define ETH_MACPMTCSR_WFE ETH_MACPMTCSR_WFE_Msk /* Wake-Up Frame Enable */
17626 #define ETH_MACPMTCSR_MPE_Pos (1U)
17627 #define ETH_MACPMTCSR_MPE_Msk (0x1U << ETH_MACPMTCSR_MPE_Pos) /*!< 0x00000002 */
17628 #define ETH_MACPMTCSR_MPE ETH_MACPMTCSR_MPE_Msk /* Magic Packet Enable */
17629 #define ETH_MACPMTCSR_PD_Pos (0U)
17630 #define ETH_MACPMTCSR_PD_Msk (0x1U << ETH_MACPMTCSR_PD_Pos) /*!< 0x00000001 */
17631 #define ETH_MACPMTCSR_PD ETH_MACPMTCSR_PD_Msk /* Power Down */
17632
17633 /* Bit definition for Ethernet MAC debug Register */
17634 #define ETH_MACDBGR_TFF_Pos (25U)
17635 #define ETH_MACDBGR_TFF_Msk (0x1U << ETH_MACDBGR_TFF_Pos) /*!< 0x02000000 */
17636 #define ETH_MACDBGR_TFF ETH_MACDBGR_TFF_Msk /* Tx FIFO full */
17637 #define ETH_MACDBGR_TFNE_Pos (24U)
17638 #define ETH_MACDBGR_TFNE_Msk (0x1U << ETH_MACDBGR_TFNE_Pos) /*!< 0x01000000 */
17639 #define ETH_MACDBGR_TFNE ETH_MACDBGR_TFNE_Msk /* Tx FIFO not empty */
17640 #define ETH_MACDBGR_TFWA_Pos (22U)
17641 #define ETH_MACDBGR_TFWA_Msk (0x1U << ETH_MACDBGR_TFWA_Pos) /*!< 0x00400000 */
17642 #define ETH_MACDBGR_TFWA ETH_MACDBGR_TFWA_Msk /* Tx FIFO write active */
17643 #define ETH_MACDBGR_TFRS_Pos (20U)
17644 #define ETH_MACDBGR_TFRS_Msk (0x3U << ETH_MACDBGR_TFRS_Pos) /*!< 0x00300000 */
17645 #define ETH_MACDBGR_TFRS ETH_MACDBGR_TFRS_Msk /* Tx FIFO read status mask */
17646 #define ETH_MACDBGR_TFRS_WRITING_Pos (20U)
17647 #define ETH_MACDBGR_TFRS_WRITING_Msk (0x3U << ETH_MACDBGR_TFRS_WRITING_Pos) /*!< 0x00300000 */
17648 #define ETH_MACDBGR_TFRS_WRITING ETH_MACDBGR_TFRS_WRITING_Msk /* Writing the received TxStatus or flushing the TxFIFO */
17649 #define ETH_MACDBGR_TFRS_WAITING_Pos (21U)
17650 #define ETH_MACDBGR_TFRS_WAITING_Msk (0x1U << ETH_MACDBGR_TFRS_WAITING_Pos) /*!< 0x00200000 */
17651 #define ETH_MACDBGR_TFRS_WAITING ETH_MACDBGR_TFRS_WAITING_Msk /* Waiting for TxStatus from MAC transmitter */
17652 #define ETH_MACDBGR_TFRS_READ_Pos (20U)
17653 #define ETH_MACDBGR_TFRS_READ_Msk (0x1U << ETH_MACDBGR_TFRS_READ_Pos) /*!< 0x00100000 */
17654 #define ETH_MACDBGR_TFRS_READ ETH_MACDBGR_TFRS_READ_Msk /* Read state (transferring data to the MAC transmitter) */
17655 #define ETH_MACDBGR_TFRS_IDLE 0x00000000U /* Idle state */
17656 #define ETH_MACDBGR_MTP_Pos (19U)
17657 #define ETH_MACDBGR_MTP_Msk (0x1U << ETH_MACDBGR_MTP_Pos) /*!< 0x00080000 */
17658 #define ETH_MACDBGR_MTP ETH_MACDBGR_MTP_Msk /* MAC transmitter in pause */
17659 #define ETH_MACDBGR_MTFCS_Pos (17U)
17660 #define ETH_MACDBGR_MTFCS_Msk (0x3U << ETH_MACDBGR_MTFCS_Pos) /*!< 0x00060000 */
17661 #define ETH_MACDBGR_MTFCS ETH_MACDBGR_MTFCS_Msk /* MAC transmit frame controller status mask */
17662 #define ETH_MACDBGR_MTFCS_TRANSFERRING_Pos (17U)
17663 #define ETH_MACDBGR_MTFCS_TRANSFERRING_Msk (0x3U << ETH_MACDBGR_MTFCS_TRANSFERRING_Pos) /*!< 0x00060000 */
17664 #define ETH_MACDBGR_MTFCS_TRANSFERRING ETH_MACDBGR_MTFCS_TRANSFERRING_Msk /* Transferring input frame for transmission */
17665 #define ETH_MACDBGR_MTFCS_GENERATINGPCF_Pos (18U)
17666 #define ETH_MACDBGR_MTFCS_GENERATINGPCF_Msk (0x1U << ETH_MACDBGR_MTFCS_GENERATINGPCF_Pos) /*!< 0x00040000 */
17667 #define ETH_MACDBGR_MTFCS_GENERATINGPCF ETH_MACDBGR_MTFCS_GENERATINGPCF_Msk /* Generating and transmitting a Pause control frame (in full duplex mode) */
17668 #define ETH_MACDBGR_MTFCS_WAITING_Pos (17U)
17669 #define ETH_MACDBGR_MTFCS_WAITING_Msk (0x1U << ETH_MACDBGR_MTFCS_WAITING_Pos) /*!< 0x00020000 */
17670 #define ETH_MACDBGR_MTFCS_WAITING ETH_MACDBGR_MTFCS_WAITING_Msk /* Waiting for Status of previous frame or IFG/backoff period to be over */
17671 #define ETH_MACDBGR_MTFCS_IDLE 0x00000000U /* Idle */
17672 #define ETH_MACDBGR_MMTEA_Pos (16U)
17673 #define ETH_MACDBGR_MMTEA_Msk (0x1U << ETH_MACDBGR_MMTEA_Pos) /*!< 0x00010000 */
17674 #define ETH_MACDBGR_MMTEA ETH_MACDBGR_MMTEA_Msk /* MAC MII transmit engine active */
17675 #define ETH_MACDBGR_RFFL_Pos (8U)
17676 #define ETH_MACDBGR_RFFL_Msk (0x3U << ETH_MACDBGR_RFFL_Pos) /*!< 0x00000300 */
17677 #define ETH_MACDBGR_RFFL ETH_MACDBGR_RFFL_Msk /* Rx FIFO fill level mask */
17678 #define ETH_MACDBGR_RFFL_FULL_Pos (8U)
17679 #define ETH_MACDBGR_RFFL_FULL_Msk (0x3U << ETH_MACDBGR_RFFL_FULL_Pos) /*!< 0x00000300 */
17680 #define ETH_MACDBGR_RFFL_FULL ETH_MACDBGR_RFFL_FULL_Msk /* RxFIFO full */
17681 #define ETH_MACDBGR_RFFL_ABOVEFCT_Pos (9U)
17682 #define ETH_MACDBGR_RFFL_ABOVEFCT_Msk (0x1U << ETH_MACDBGR_RFFL_ABOVEFCT_Pos) /*!< 0x00000200 */
17683 #define ETH_MACDBGR_RFFL_ABOVEFCT ETH_MACDBGR_RFFL_ABOVEFCT_Msk /* RxFIFO fill-level above flow-control activate threshold */
17684 #define ETH_MACDBGR_RFFL_BELOWFCT_Pos (8U)
17685 #define ETH_MACDBGR_RFFL_BELOWFCT_Msk (0x1U << ETH_MACDBGR_RFFL_BELOWFCT_Pos) /*!< 0x00000100 */
17686 #define ETH_MACDBGR_RFFL_BELOWFCT ETH_MACDBGR_RFFL_BELOWFCT_Msk /* RxFIFO fill-level below flow-control de-activate threshold */
17687 #define ETH_MACDBGR_RFFL_EMPTY 0x00000000U /* RxFIFO empty */
17688 #define ETH_MACDBGR_RFRCS_Pos (5U)
17689 #define ETH_MACDBGR_RFRCS_Msk (0x3U << ETH_MACDBGR_RFRCS_Pos) /*!< 0x00000060 */
17690 #define ETH_MACDBGR_RFRCS ETH_MACDBGR_RFRCS_Msk /* Rx FIFO read controller status mask */
17691 #define ETH_MACDBGR_RFRCS_FLUSHING_Pos (5U)
17692 #define ETH_MACDBGR_RFRCS_FLUSHING_Msk (0x3U << ETH_MACDBGR_RFRCS_FLUSHING_Pos) /*!< 0x00000060 */
17693 #define ETH_MACDBGR_RFRCS_FLUSHING ETH_MACDBGR_RFRCS_FLUSHING_Msk /* Flushing the frame data and status */
17694 #define ETH_MACDBGR_RFRCS_STATUSREADING_Pos (6U)
17695 #define ETH_MACDBGR_RFRCS_STATUSREADING_Msk (0x1U << ETH_MACDBGR_RFRCS_STATUSREADING_Pos) /*!< 0x00000040 */
17696 #define ETH_MACDBGR_RFRCS_STATUSREADING ETH_MACDBGR_RFRCS_STATUSREADING_Msk /* Reading frame status (or time-stamp) */
17697 #define ETH_MACDBGR_RFRCS_DATAREADING_Pos (5U)
17698 #define ETH_MACDBGR_RFRCS_DATAREADING_Msk (0x1U << ETH_MACDBGR_RFRCS_DATAREADING_Pos) /*!< 0x00000020 */
17699 #define ETH_MACDBGR_RFRCS_DATAREADING ETH_MACDBGR_RFRCS_DATAREADING_Msk /* Reading frame data */
17700 #define ETH_MACDBGR_RFRCS_IDLE 0x00000000U /* IDLE state */
17701 #define ETH_MACDBGR_RFWRA_Pos (4U)
17702 #define ETH_MACDBGR_RFWRA_Msk (0x1U << ETH_MACDBGR_RFWRA_Pos) /*!< 0x00000010 */
17703 #define ETH_MACDBGR_RFWRA ETH_MACDBGR_RFWRA_Msk /* Rx FIFO write controller active */
17704 #define ETH_MACDBGR_MSFRWCS_Pos (1U)
17705 #define ETH_MACDBGR_MSFRWCS_Msk (0x3U << ETH_MACDBGR_MSFRWCS_Pos) /*!< 0x00000006 */
17706 #define ETH_MACDBGR_MSFRWCS ETH_MACDBGR_MSFRWCS_Msk /* MAC small FIFO read / write controllers status mask */
17707 #define ETH_MACDBGR_MSFRWCS_1 (0x2U << ETH_MACDBGR_MSFRWCS_Pos) /*!< 0x00000004 */
17708 #define ETH_MACDBGR_MSFRWCS_0 (0x1U << ETH_MACDBGR_MSFRWCS_Pos) /*!< 0x00000002 */
17709 #define ETH_MACDBGR_MMRPEA_Pos (0U)
17710 #define ETH_MACDBGR_MMRPEA_Msk (0x1U << ETH_MACDBGR_MMRPEA_Pos) /*!< 0x00000001 */
17711 #define ETH_MACDBGR_MMRPEA ETH_MACDBGR_MMRPEA_Msk /* MAC MII receive protocol engine active */
17712
17713 /* Bit definition for Ethernet MAC Status Register */
17714 #define ETH_MACSR_TSTS_Pos (9U)
17715 #define ETH_MACSR_TSTS_Msk (0x1U << ETH_MACSR_TSTS_Pos) /*!< 0x00000200 */
17716 #define ETH_MACSR_TSTS ETH_MACSR_TSTS_Msk /* Time stamp trigger status */
17717 #define ETH_MACSR_MMCTS_Pos (6U)
17718 #define ETH_MACSR_MMCTS_Msk (0x1U << ETH_MACSR_MMCTS_Pos) /*!< 0x00000040 */
17719 #define ETH_MACSR_MMCTS ETH_MACSR_MMCTS_Msk /* MMC transmit status */
17720 #define ETH_MACSR_MMMCRS_Pos (5U)
17721 #define ETH_MACSR_MMMCRS_Msk (0x1U << ETH_MACSR_MMMCRS_Pos) /*!< 0x00000020 */
17722 #define ETH_MACSR_MMMCRS ETH_MACSR_MMMCRS_Msk /* MMC receive status */
17723 #define ETH_MACSR_MMCS_Pos (4U)
17724 #define ETH_MACSR_MMCS_Msk (0x1U << ETH_MACSR_MMCS_Pos) /*!< 0x00000010 */
17725 #define ETH_MACSR_MMCS ETH_MACSR_MMCS_Msk /* MMC status */
17726 #define ETH_MACSR_PMTS_Pos (3U)
17727 #define ETH_MACSR_PMTS_Msk (0x1U << ETH_MACSR_PMTS_Pos) /*!< 0x00000008 */
17728 #define ETH_MACSR_PMTS ETH_MACSR_PMTS_Msk /* PMT status */
17729
17730 /* Bit definition for Ethernet MAC Interrupt Mask Register */
17731 #define ETH_MACIMR_TSTIM_Pos (9U)
17732 #define ETH_MACIMR_TSTIM_Msk (0x1U << ETH_MACIMR_TSTIM_Pos) /*!< 0x00000200 */
17733 #define ETH_MACIMR_TSTIM ETH_MACIMR_TSTIM_Msk /* Time stamp trigger interrupt mask */
17734 #define ETH_MACIMR_PMTIM_Pos (3U)
17735 #define ETH_MACIMR_PMTIM_Msk (0x1U << ETH_MACIMR_PMTIM_Pos) /*!< 0x00000008 */
17736 #define ETH_MACIMR_PMTIM ETH_MACIMR_PMTIM_Msk /* PMT interrupt mask */
17737
17738 /* Bit definition for Ethernet MAC Address0 High Register */
17739 #define ETH_MACA0HR_MACA0H_Pos (0U)
17740 #define ETH_MACA0HR_MACA0H_Msk (0xFFFFU << ETH_MACA0HR_MACA0H_Pos) /*!< 0x0000FFFF */
17741 #define ETH_MACA0HR_MACA0H ETH_MACA0HR_MACA0H_Msk /* MAC address0 high */
17742
17743 /* Bit definition for Ethernet MAC Address0 Low Register */
17744 #define ETH_MACA0LR_MACA0L_Pos (0U)
17745 #define ETH_MACA0LR_MACA0L_Msk (0xFFFFFFFFU << ETH_MACA0LR_MACA0L_Pos) /*!< 0xFFFFFFFF */
17746 #define ETH_MACA0LR_MACA0L ETH_MACA0LR_MACA0L_Msk /* MAC address0 low */
17747
17748 /* Bit definition for Ethernet MAC Address1 High Register */
17749 #define ETH_MACA1HR_AE_Pos (31U)
17750 #define ETH_MACA1HR_AE_Msk (0x1U << ETH_MACA1HR_AE_Pos) /*!< 0x80000000 */
17751 #define ETH_MACA1HR_AE ETH_MACA1HR_AE_Msk /* Address enable */
17752 #define ETH_MACA1HR_SA_Pos (30U)
17753 #define ETH_MACA1HR_SA_Msk (0x1U << ETH_MACA1HR_SA_Pos) /*!< 0x40000000 */
17754 #define ETH_MACA1HR_SA ETH_MACA1HR_SA_Msk /* Source address */
17755 #define ETH_MACA1HR_MBC_Pos (24U)
17756 #define ETH_MACA1HR_MBC_Msk (0x3FU << ETH_MACA1HR_MBC_Pos) /*!< 0x3F000000 */
17757 #define ETH_MACA1HR_MBC ETH_MACA1HR_MBC_Msk /* Mask byte control: bits to mask for comparison of the MAC Address bytes */
17758 #define ETH_MACA1HR_MBC_HBits15_8 0x20000000U /* Mask MAC Address high reg bits [15:8] */
17759 #define ETH_MACA1HR_MBC_HBits7_0 0x10000000U /* Mask MAC Address high reg bits [7:0] */
17760 #define ETH_MACA1HR_MBC_LBits31_24 0x08000000U /* Mask MAC Address low reg bits [31:24] */
17761 #define ETH_MACA1HR_MBC_LBits23_16 0x04000000U /* Mask MAC Address low reg bits [23:16] */
17762 #define ETH_MACA1HR_MBC_LBits15_8 0x02000000U /* Mask MAC Address low reg bits [15:8] */
17763 #define ETH_MACA1HR_MBC_LBits7_0 0x01000000U /* Mask MAC Address low reg bits [7:0] */
17764 #define ETH_MACA1HR_MACA1H_Pos (0U)
17765 #define ETH_MACA1HR_MACA1H_Msk (0xFFFFU << ETH_MACA1HR_MACA1H_Pos) /*!< 0x0000FFFF */
17766 #define ETH_MACA1HR_MACA1H ETH_MACA1HR_MACA1H_Msk /* MAC address1 high */
17767
17768 /* Bit definition for Ethernet MAC Address1 Low Register */
17769 #define ETH_MACA1LR_MACA1L_Pos (0U)
17770 #define ETH_MACA1LR_MACA1L_Msk (0xFFFFFFFFU << ETH_MACA1LR_MACA1L_Pos) /*!< 0xFFFFFFFF */
17771 #define ETH_MACA1LR_MACA1L ETH_MACA1LR_MACA1L_Msk /* MAC address1 low */
17772
17773 /* Bit definition for Ethernet MAC Address2 High Register */
17774 #define ETH_MACA2HR_AE_Pos (31U)
17775 #define ETH_MACA2HR_AE_Msk (0x1U << ETH_MACA2HR_AE_Pos) /*!< 0x80000000 */
17776 #define ETH_MACA2HR_AE ETH_MACA2HR_AE_Msk /* Address enable */
17777 #define ETH_MACA2HR_SA_Pos (30U)
17778 #define ETH_MACA2HR_SA_Msk (0x1U << ETH_MACA2HR_SA_Pos) /*!< 0x40000000 */
17779 #define ETH_MACA2HR_SA ETH_MACA2HR_SA_Msk /* Source address */
17780 #define ETH_MACA2HR_MBC_Pos (24U)
17781 #define ETH_MACA2HR_MBC_Msk (0x3FU << ETH_MACA2HR_MBC_Pos) /*!< 0x3F000000 */
17782 #define ETH_MACA2HR_MBC ETH_MACA2HR_MBC_Msk /* Mask byte control */
17783 #define ETH_MACA2HR_MBC_HBits15_8 0x20000000U /* Mask MAC Address high reg bits [15:8] */
17784 #define ETH_MACA2HR_MBC_HBits7_0 0x10000000U /* Mask MAC Address high reg bits [7:0] */
17785 #define ETH_MACA2HR_MBC_LBits31_24 0x08000000U /* Mask MAC Address low reg bits [31:24] */
17786 #define ETH_MACA2HR_MBC_LBits23_16 0x04000000U /* Mask MAC Address low reg bits [23:16] */
17787 #define ETH_MACA2HR_MBC_LBits15_8 0x02000000U /* Mask MAC Address low reg bits [15:8] */
17788 #define ETH_MACA2HR_MBC_LBits7_0 0x01000000U /* Mask MAC Address low reg bits [70] */
17789 #define ETH_MACA2HR_MACA2H_Pos (0U)
17790 #define ETH_MACA2HR_MACA2H_Msk (0xFFFFU << ETH_MACA2HR_MACA2H_Pos) /*!< 0x0000FFFF */
17791 #define ETH_MACA2HR_MACA2H ETH_MACA2HR_MACA2H_Msk /* MAC address1 high */
17792
17793 /* Bit definition for Ethernet MAC Address2 Low Register */
17794 #define ETH_MACA2LR_MACA2L_Pos (0U)
17795 #define ETH_MACA2LR_MACA2L_Msk (0xFFFFFFFFU << ETH_MACA2LR_MACA2L_Pos) /*!< 0xFFFFFFFF */
17796 #define ETH_MACA2LR_MACA2L ETH_MACA2LR_MACA2L_Msk /* MAC address2 low */
17797
17798 /* Bit definition for Ethernet MAC Address3 High Register */
17799 #define ETH_MACA3HR_AE_Pos (31U)
17800 #define ETH_MACA3HR_AE_Msk (0x1U << ETH_MACA3HR_AE_Pos) /*!< 0x80000000 */
17801 #define ETH_MACA3HR_AE ETH_MACA3HR_AE_Msk /* Address enable */
17802 #define ETH_MACA3HR_SA_Pos (30U)
17803 #define ETH_MACA3HR_SA_Msk (0x1U << ETH_MACA3HR_SA_Pos) /*!< 0x40000000 */
17804 #define ETH_MACA3HR_SA ETH_MACA3HR_SA_Msk /* Source address */
17805 #define ETH_MACA3HR_MBC_Pos (24U)
17806 #define ETH_MACA3HR_MBC_Msk (0x3FU << ETH_MACA3HR_MBC_Pos) /*!< 0x3F000000 */
17807 #define ETH_MACA3HR_MBC ETH_MACA3HR_MBC_Msk /* Mask byte control */
17808 #define ETH_MACA3HR_MBC_HBits15_8 0x20000000U /* Mask MAC Address high reg bits [15:8] */
17809 #define ETH_MACA3HR_MBC_HBits7_0 0x10000000U /* Mask MAC Address high reg bits [7:0] */
17810 #define ETH_MACA3HR_MBC_LBits31_24 0x08000000U /* Mask MAC Address low reg bits [31:24] */
17811 #define ETH_MACA3HR_MBC_LBits23_16 0x04000000U /* Mask MAC Address low reg bits [23:16] */
17812 #define ETH_MACA3HR_MBC_LBits15_8 0x02000000U /* Mask MAC Address low reg bits [15:8] */
17813 #define ETH_MACA3HR_MBC_LBits7_0 0x01000000U /* Mask MAC Address low reg bits [70] */
17814 #define ETH_MACA3HR_MACA3H_Pos (0U)
17815 #define ETH_MACA3HR_MACA3H_Msk (0xFFFFU << ETH_MACA3HR_MACA3H_Pos) /*!< 0x0000FFFF */
17816 #define ETH_MACA3HR_MACA3H ETH_MACA3HR_MACA3H_Msk /* MAC address3 high */
17817
17818 /* Bit definition for Ethernet MAC Address3 Low Register */
17819 #define ETH_MACA3LR_MACA3L_Pos (0U)
17820 #define ETH_MACA3LR_MACA3L_Msk (0xFFFFFFFFU << ETH_MACA3LR_MACA3L_Pos) /*!< 0xFFFFFFFF */
17821 #define ETH_MACA3LR_MACA3L ETH_MACA3LR_MACA3L_Msk /* MAC address3 low */
17822
17823 /******************************************************************************/
17824 /* Ethernet MMC Registers bits definition */
17825 /******************************************************************************/
17826
17827 /* Bit definition for Ethernet MMC Contol Register */
17828 #define ETH_MMCCR_MCFHP_Pos (5U)
17829 #define ETH_MMCCR_MCFHP_Msk (0x1U << ETH_MMCCR_MCFHP_Pos) /*!< 0x00000020 */
17830 #define ETH_MMCCR_MCFHP ETH_MMCCR_MCFHP_Msk /* MMC counter Full-Half preset */
17831 #define ETH_MMCCR_MCP_Pos (4U)
17832 #define ETH_MMCCR_MCP_Msk (0x1U << ETH_MMCCR_MCP_Pos) /*!< 0x00000010 */
17833 #define ETH_MMCCR_MCP ETH_MMCCR_MCP_Msk /* MMC counter preset */
17834 #define ETH_MMCCR_MCF_Pos (3U)
17835 #define ETH_MMCCR_MCF_Msk (0x1U << ETH_MMCCR_MCF_Pos) /*!< 0x00000008 */
17836 #define ETH_MMCCR_MCF ETH_MMCCR_MCF_Msk /* MMC Counter Freeze */
17837 #define ETH_MMCCR_ROR_Pos (2U)
17838 #define ETH_MMCCR_ROR_Msk (0x1U << ETH_MMCCR_ROR_Pos) /*!< 0x00000004 */
17839 #define ETH_MMCCR_ROR ETH_MMCCR_ROR_Msk /* Reset on Read */
17840 #define ETH_MMCCR_CSR_Pos (1U)
17841 #define ETH_MMCCR_CSR_Msk (0x1U << ETH_MMCCR_CSR_Pos) /*!< 0x00000002 */
17842 #define ETH_MMCCR_CSR ETH_MMCCR_CSR_Msk /* Counter Stop Rollover */
17843 #define ETH_MMCCR_CR_Pos (0U)
17844 #define ETH_MMCCR_CR_Msk (0x1U << ETH_MMCCR_CR_Pos) /*!< 0x00000001 */
17845 #define ETH_MMCCR_CR ETH_MMCCR_CR_Msk /* Counters Reset */
17846
17847 /* Bit definition for Ethernet MMC Receive Interrupt Register */
17848 #define ETH_MMCRIR_RGUFS_Pos (17U)
17849 #define ETH_MMCRIR_RGUFS_Msk (0x1U << ETH_MMCRIR_RGUFS_Pos) /*!< 0x00020000 */
17850 #define ETH_MMCRIR_RGUFS ETH_MMCRIR_RGUFS_Msk /* Set when Rx good unicast frames counter reaches half the maximum value */
17851 #define ETH_MMCRIR_RFAES_Pos (6U)
17852 #define ETH_MMCRIR_RFAES_Msk (0x1U << ETH_MMCRIR_RFAES_Pos) /*!< 0x00000040 */
17853 #define ETH_MMCRIR_RFAES ETH_MMCRIR_RFAES_Msk /* Set when Rx alignment error counter reaches half the maximum value */
17854 #define ETH_MMCRIR_RFCES_Pos (5U)
17855 #define ETH_MMCRIR_RFCES_Msk (0x1U << ETH_MMCRIR_RFCES_Pos) /*!< 0x00000020 */
17856 #define ETH_MMCRIR_RFCES ETH_MMCRIR_RFCES_Msk /* Set when Rx crc error counter reaches half the maximum value */
17857
17858 /* Bit definition for Ethernet MMC Transmit Interrupt Register */
17859 #define ETH_MMCTIR_TGFS_Pos (21U)
17860 #define ETH_MMCTIR_TGFS_Msk (0x1U << ETH_MMCTIR_TGFS_Pos) /*!< 0x00200000 */
17861 #define ETH_MMCTIR_TGFS ETH_MMCTIR_TGFS_Msk /* Set when Tx good frame count counter reaches half the maximum value */
17862 #define ETH_MMCTIR_TGFMSCS_Pos (15U)
17863 #define ETH_MMCTIR_TGFMSCS_Msk (0x1U << ETH_MMCTIR_TGFMSCS_Pos) /*!< 0x00008000 */
17864 #define ETH_MMCTIR_TGFMSCS ETH_MMCTIR_TGFMSCS_Msk /* Set when Tx good multi col counter reaches half the maximum value */
17865 #define ETH_MMCTIR_TGFSCS_Pos (14U)
17866 #define ETH_MMCTIR_TGFSCS_Msk (0x1U << ETH_MMCTIR_TGFSCS_Pos) /*!< 0x00004000 */
17867 #define ETH_MMCTIR_TGFSCS ETH_MMCTIR_TGFSCS_Msk /* Set when Tx good single col counter reaches half the maximum value */
17868
17869 /* Bit definition for Ethernet MMC Receive Interrupt Mask Register */
17870 #define ETH_MMCRIMR_RGUFM_Pos (17U)
17871 #define ETH_MMCRIMR_RGUFM_Msk (0x1U << ETH_MMCRIMR_RGUFM_Pos) /*!< 0x00020000 */
17872 #define ETH_MMCRIMR_RGUFM ETH_MMCRIMR_RGUFM_Msk /* Mask the interrupt when Rx good unicast frames counter reaches half the maximum value */
17873 #define ETH_MMCRIMR_RFAEM_Pos (6U)
17874 #define ETH_MMCRIMR_RFAEM_Msk (0x1U << ETH_MMCRIMR_RFAEM_Pos) /*!< 0x00000040 */
17875 #define ETH_MMCRIMR_RFAEM ETH_MMCRIMR_RFAEM_Msk /* Mask the interrupt when when Rx alignment error counter reaches half the maximum value */
17876 #define ETH_MMCRIMR_RFCEM_Pos (5U)
17877 #define ETH_MMCRIMR_RFCEM_Msk (0x1U << ETH_MMCRIMR_RFCEM_Pos) /*!< 0x00000020 */
17878 #define ETH_MMCRIMR_RFCEM ETH_MMCRIMR_RFCEM_Msk /* Mask the interrupt when Rx crc error counter reaches half the maximum value */
17879
17880 /* Bit definition for Ethernet MMC Transmit Interrupt Mask Register */
17881 #define ETH_MMCTIMR_TGFM_Pos (21U)
17882 #define ETH_MMCTIMR_TGFM_Msk (0x1U << ETH_MMCTIMR_TGFM_Pos) /*!< 0x00200000 */
17883 #define ETH_MMCTIMR_TGFM ETH_MMCTIMR_TGFM_Msk /* Mask the interrupt when Tx good frame count counter reaches half the maximum value */
17884 #define ETH_MMCTIMR_TGFMSCM_Pos (15U)
17885 #define ETH_MMCTIMR_TGFMSCM_Msk (0x1U << ETH_MMCTIMR_TGFMSCM_Pos) /*!< 0x00008000 */
17886 #define ETH_MMCTIMR_TGFMSCM ETH_MMCTIMR_TGFMSCM_Msk /* Mask the interrupt when Tx good multi col counter reaches half the maximum value */
17887 #define ETH_MMCTIMR_TGFSCM_Pos (14U)
17888 #define ETH_MMCTIMR_TGFSCM_Msk (0x1U << ETH_MMCTIMR_TGFSCM_Pos) /*!< 0x00004000 */
17889 #define ETH_MMCTIMR_TGFSCM ETH_MMCTIMR_TGFSCM_Msk /* Mask the interrupt when Tx good single col counter reaches half the maximum value */
17890
17891 /* Bit definition for Ethernet MMC Transmitted Good Frames after Single Collision Counter Register */
17892 #define ETH_MMCTGFSCCR_TGFSCC_Pos (0U)
17893 #define ETH_MMCTGFSCCR_TGFSCC_Msk (0xFFFFFFFFU << ETH_MMCTGFSCCR_TGFSCC_Pos) /*!< 0xFFFFFFFF */
17894 #define ETH_MMCTGFSCCR_TGFSCC ETH_MMCTGFSCCR_TGFSCC_Msk /* Number of successfully transmitted frames after a single collision in Half-duplex mode. */
17895
17896 /* Bit definition for Ethernet MMC Transmitted Good Frames after More than a Single Collision Counter Register */
17897 #define ETH_MMCTGFMSCCR_TGFMSCC_Pos (0U)
17898 #define ETH_MMCTGFMSCCR_TGFMSCC_Msk (0xFFFFFFFFU << ETH_MMCTGFMSCCR_TGFMSCC_Pos) /*!< 0xFFFFFFFF */
17899 #define ETH_MMCTGFMSCCR_TGFMSCC ETH_MMCTGFMSCCR_TGFMSCC_Msk /* Number of successfully transmitted frames after more than a single collision in Half-duplex mode. */
17900
17901 /* Bit definition for Ethernet MMC Transmitted Good Frames Counter Register */
17902 #define ETH_MMCTGFCR_TGFC_Pos (0U)
17903 #define ETH_MMCTGFCR_TGFC_Msk (0xFFFFFFFFU << ETH_MMCTGFCR_TGFC_Pos) /*!< 0xFFFFFFFF */
17904 #define ETH_MMCTGFCR_TGFC ETH_MMCTGFCR_TGFC_Msk /* Number of good frames transmitted. */
17905
17906 /* Bit definition for Ethernet MMC Received Frames with CRC Error Counter Register */
17907 #define ETH_MMCRFCECR_RFCEC_Pos (0U)
17908 #define ETH_MMCRFCECR_RFCEC_Msk (0xFFFFFFFFU << ETH_MMCRFCECR_RFCEC_Pos) /*!< 0xFFFFFFFF */
17909 #define ETH_MMCRFCECR_RFCEC ETH_MMCRFCECR_RFCEC_Msk /* Number of frames received with CRC error. */
17910
17911 /* Bit definition for Ethernet MMC Received Frames with Alignement Error Counter Register */
17912 #define ETH_MMCRFAECR_RFAEC_Pos (0U)
17913 #define ETH_MMCRFAECR_RFAEC_Msk (0xFFFFFFFFU << ETH_MMCRFAECR_RFAEC_Pos) /*!< 0xFFFFFFFF */
17914 #define ETH_MMCRFAECR_RFAEC ETH_MMCRFAECR_RFAEC_Msk /* Number of frames received with alignment (dribble) error */
17915
17916 /* Bit definition for Ethernet MMC Received Good Unicast Frames Counter Register */
17917 #define ETH_MMCRGUFCR_RGUFC_Pos (0U)
17918 #define ETH_MMCRGUFCR_RGUFC_Msk (0xFFFFFFFFU << ETH_MMCRGUFCR_RGUFC_Pos) /*!< 0xFFFFFFFF */
17919 #define ETH_MMCRGUFCR_RGUFC ETH_MMCRGUFCR_RGUFC_Msk /* Number of good unicast frames received. */
17920
17921 /******************************************************************************/
17922 /* Ethernet PTP Registers bits definition */
17923 /******************************************************************************/
17924
17925 /* Bit definition for Ethernet PTP Time Stamp Contol Register */
17926 #define ETH_PTPTSCR_TSCNT_Pos (16U)
17927 #define ETH_PTPTSCR_TSCNT_Msk (0x3U << ETH_PTPTSCR_TSCNT_Pos) /*!< 0x00030000 */
17928 #define ETH_PTPTSCR_TSCNT ETH_PTPTSCR_TSCNT_Msk /* Time stamp clock node type */
17929 #define ETH_PTPTSSR_TSSMRME_Pos (15U)
17930 #define ETH_PTPTSSR_TSSMRME_Msk (0x1U << ETH_PTPTSSR_TSSMRME_Pos) /*!< 0x00008000 */
17931 #define ETH_PTPTSSR_TSSMRME ETH_PTPTSSR_TSSMRME_Msk /* Time stamp snapshot for message relevant to master enable */
17932 #define ETH_PTPTSSR_TSSEME_Pos (14U)
17933 #define ETH_PTPTSSR_TSSEME_Msk (0x1U << ETH_PTPTSSR_TSSEME_Pos) /*!< 0x00004000 */
17934 #define ETH_PTPTSSR_TSSEME ETH_PTPTSSR_TSSEME_Msk /* Time stamp snapshot for event message enable */
17935 #define ETH_PTPTSSR_TSSIPV4FE_Pos (13U)
17936 #define ETH_PTPTSSR_TSSIPV4FE_Msk (0x1U << ETH_PTPTSSR_TSSIPV4FE_Pos) /*!< 0x00002000 */
17937 #define ETH_PTPTSSR_TSSIPV4FE ETH_PTPTSSR_TSSIPV4FE_Msk /* Time stamp snapshot for IPv4 frames enable */
17938 #define ETH_PTPTSSR_TSSIPV6FE_Pos (12U)
17939 #define ETH_PTPTSSR_TSSIPV6FE_Msk (0x1U << ETH_PTPTSSR_TSSIPV6FE_Pos) /*!< 0x00001000 */
17940 #define ETH_PTPTSSR_TSSIPV6FE ETH_PTPTSSR_TSSIPV6FE_Msk /* Time stamp snapshot for IPv6 frames enable */
17941 #define ETH_PTPTSSR_TSSPTPOEFE_Pos (11U)
17942 #define ETH_PTPTSSR_TSSPTPOEFE_Msk (0x1U << ETH_PTPTSSR_TSSPTPOEFE_Pos) /*!< 0x00000800 */
17943 #define ETH_PTPTSSR_TSSPTPOEFE ETH_PTPTSSR_TSSPTPOEFE_Msk /* Time stamp snapshot for PTP over ethernet frames enable */
17944 #define ETH_PTPTSSR_TSPTPPSV2E_Pos (10U)
17945 #define ETH_PTPTSSR_TSPTPPSV2E_Msk (0x1U << ETH_PTPTSSR_TSPTPPSV2E_Pos) /*!< 0x00000400 */
17946 #define ETH_PTPTSSR_TSPTPPSV2E ETH_PTPTSSR_TSPTPPSV2E_Msk /* Time stamp PTP packet snooping for version2 format enable */
17947 #define ETH_PTPTSSR_TSSSR_Pos (9U)
17948 #define ETH_PTPTSSR_TSSSR_Msk (0x1U << ETH_PTPTSSR_TSSSR_Pos) /*!< 0x00000200 */
17949 #define ETH_PTPTSSR_TSSSR ETH_PTPTSSR_TSSSR_Msk /* Time stamp Sub-seconds rollover */
17950 #define ETH_PTPTSSR_TSSARFE_Pos (8U)
17951 #define ETH_PTPTSSR_TSSARFE_Msk (0x1U << ETH_PTPTSSR_TSSARFE_Pos) /*!< 0x00000100 */
17952 #define ETH_PTPTSSR_TSSARFE ETH_PTPTSSR_TSSARFE_Msk /* Time stamp snapshot for all received frames enable */
17953
17954 #define ETH_PTPTSCR_TSARU_Pos (5U)
17955 #define ETH_PTPTSCR_TSARU_Msk (0x1U << ETH_PTPTSCR_TSARU_Pos) /*!< 0x00000020 */
17956 #define ETH_PTPTSCR_TSARU ETH_PTPTSCR_TSARU_Msk /* Addend register update */
17957 #define ETH_PTPTSCR_TSITE_Pos (4U)
17958 #define ETH_PTPTSCR_TSITE_Msk (0x1U << ETH_PTPTSCR_TSITE_Pos) /*!< 0x00000010 */
17959 #define ETH_PTPTSCR_TSITE ETH_PTPTSCR_TSITE_Msk /* Time stamp interrupt trigger enable */
17960 #define ETH_PTPTSCR_TSSTU_Pos (3U)
17961 #define ETH_PTPTSCR_TSSTU_Msk (0x1U << ETH_PTPTSCR_TSSTU_Pos) /*!< 0x00000008 */
17962 #define ETH_PTPTSCR_TSSTU ETH_PTPTSCR_TSSTU_Msk /* Time stamp update */
17963 #define ETH_PTPTSCR_TSSTI_Pos (2U)
17964 #define ETH_PTPTSCR_TSSTI_Msk (0x1U << ETH_PTPTSCR_TSSTI_Pos) /*!< 0x00000004 */
17965 #define ETH_PTPTSCR_TSSTI ETH_PTPTSCR_TSSTI_Msk /* Time stamp initialize */
17966 #define ETH_PTPTSCR_TSFCU_Pos (1U)
17967 #define ETH_PTPTSCR_TSFCU_Msk (0x1U << ETH_PTPTSCR_TSFCU_Pos) /*!< 0x00000002 */
17968 #define ETH_PTPTSCR_TSFCU ETH_PTPTSCR_TSFCU_Msk /* Time stamp fine or coarse update */
17969 #define ETH_PTPTSCR_TSE_Pos (0U)
17970 #define ETH_PTPTSCR_TSE_Msk (0x1U << ETH_PTPTSCR_TSE_Pos) /*!< 0x00000001 */
17971 #define ETH_PTPTSCR_TSE ETH_PTPTSCR_TSE_Msk /* Time stamp enable */
17972
17973 /* Bit definition for Ethernet PTP Sub-Second Increment Register */
17974 #define ETH_PTPSSIR_STSSI_Pos (0U)
17975 #define ETH_PTPSSIR_STSSI_Msk (0xFFU << ETH_PTPSSIR_STSSI_Pos) /*!< 0x000000FF */
17976 #define ETH_PTPSSIR_STSSI ETH_PTPSSIR_STSSI_Msk /* System time Sub-second increment value */
17977
17978 /* Bit definition for Ethernet PTP Time Stamp High Register */
17979 #define ETH_PTPTSHR_STS_Pos (0U)
17980 #define ETH_PTPTSHR_STS_Msk (0xFFFFFFFFU << ETH_PTPTSHR_STS_Pos) /*!< 0xFFFFFFFF */
17981 #define ETH_PTPTSHR_STS ETH_PTPTSHR_STS_Msk /* System Time second */
17982
17983 /* Bit definition for Ethernet PTP Time Stamp Low Register */
17984 #define ETH_PTPTSLR_STPNS_Pos (31U)
17985 #define ETH_PTPTSLR_STPNS_Msk (0x1U << ETH_PTPTSLR_STPNS_Pos) /*!< 0x80000000 */
17986 #define ETH_PTPTSLR_STPNS ETH_PTPTSLR_STPNS_Msk /* System Time Positive or negative time */
17987 #define ETH_PTPTSLR_STSS_Pos (0U)
17988 #define ETH_PTPTSLR_STSS_Msk (0x7FFFFFFFU << ETH_PTPTSLR_STSS_Pos) /*!< 0x7FFFFFFF */
17989 #define ETH_PTPTSLR_STSS ETH_PTPTSLR_STSS_Msk /* System Time sub-seconds */
17990
17991 /* Bit definition for Ethernet PTP Time Stamp High Update Register */
17992 #define ETH_PTPTSHUR_TSUS_Pos (0U)
17993 #define ETH_PTPTSHUR_TSUS_Msk (0xFFFFFFFFU << ETH_PTPTSHUR_TSUS_Pos) /*!< 0xFFFFFFFF */
17994 #define ETH_PTPTSHUR_TSUS ETH_PTPTSHUR_TSUS_Msk /* Time stamp update seconds */
17995
17996 /* Bit definition for Ethernet PTP Time Stamp Low Update Register */
17997 #define ETH_PTPTSLUR_TSUPNS_Pos (31U)
17998 #define ETH_PTPTSLUR_TSUPNS_Msk (0x1U << ETH_PTPTSLUR_TSUPNS_Pos) /*!< 0x80000000 */
17999 #define ETH_PTPTSLUR_TSUPNS ETH_PTPTSLUR_TSUPNS_Msk /* Time stamp update Positive or negative time */
18000 #define ETH_PTPTSLUR_TSUSS_Pos (0U)
18001 #define ETH_PTPTSLUR_TSUSS_Msk (0x7FFFFFFFU << ETH_PTPTSLUR_TSUSS_Pos) /*!< 0x7FFFFFFF */
18002 #define ETH_PTPTSLUR_TSUSS ETH_PTPTSLUR_TSUSS_Msk /* Time stamp update sub-seconds */
18003
18004 /* Bit definition for Ethernet PTP Time Stamp Addend Register */
18005 #define ETH_PTPTSAR_TSA_Pos (0U)
18006 #define ETH_PTPTSAR_TSA_Msk (0xFFFFFFFFU << ETH_PTPTSAR_TSA_Pos) /*!< 0xFFFFFFFF */
18007 #define ETH_PTPTSAR_TSA ETH_PTPTSAR_TSA_Msk /* Time stamp addend */
18008
18009 /* Bit definition for Ethernet PTP Target Time High Register */
18010 #define ETH_PTPTTHR_TTSH_Pos (0U)
18011 #define ETH_PTPTTHR_TTSH_Msk (0xFFFFFFFFU << ETH_PTPTTHR_TTSH_Pos) /*!< 0xFFFFFFFF */
18012 #define ETH_PTPTTHR_TTSH ETH_PTPTTHR_TTSH_Msk /* Target time stamp high */
18013
18014 /* Bit definition for Ethernet PTP Target Time Low Register */
18015 #define ETH_PTPTTLR_TTSL_Pos (0U)
18016 #define ETH_PTPTTLR_TTSL_Msk (0xFFFFFFFFU << ETH_PTPTTLR_TTSL_Pos) /*!< 0xFFFFFFFF */
18017 #define ETH_PTPTTLR_TTSL ETH_PTPTTLR_TTSL_Msk /* Target time stamp low */
18018
18019 /* Bit definition for Ethernet PTP Time Stamp Status Register */
18020 #define ETH_PTPTSSR_TSTTR_Pos (5U)
18021 #define ETH_PTPTSSR_TSTTR_Msk (0x1U << ETH_PTPTSSR_TSTTR_Pos) /*!< 0x00000020 */
18022 #define ETH_PTPTSSR_TSTTR ETH_PTPTSSR_TSTTR_Msk /* Time stamp target time reached */
18023 #define ETH_PTPTSSR_TSSO_Pos (4U)
18024 #define ETH_PTPTSSR_TSSO_Msk (0x1U << ETH_PTPTSSR_TSSO_Pos) /*!< 0x00000010 */
18025 #define ETH_PTPTSSR_TSSO ETH_PTPTSSR_TSSO_Msk /* Time stamp seconds overflow */
18026
18027 /******************************************************************************/
18028 /* Ethernet DMA Registers bits definition */
18029 /******************************************************************************/
18030
18031 /* Bit definition for Ethernet DMA Bus Mode Register */
18032 #define ETH_DMABMR_AAB_Pos (25U)
18033 #define ETH_DMABMR_AAB_Msk (0x1U << ETH_DMABMR_AAB_Pos) /*!< 0x02000000 */
18034 #define ETH_DMABMR_AAB ETH_DMABMR_AAB_Msk /* Address-Aligned beats */
18035 #define ETH_DMABMR_FPM_Pos (24U)
18036 #define ETH_DMABMR_FPM_Msk (0x1U << ETH_DMABMR_FPM_Pos) /*!< 0x01000000 */
18037 #define ETH_DMABMR_FPM ETH_DMABMR_FPM_Msk /* 4xPBL mode */
18038 #define ETH_DMABMR_USP_Pos (23U)
18039 #define ETH_DMABMR_USP_Msk (0x1U << ETH_DMABMR_USP_Pos) /*!< 0x00800000 */
18040 #define ETH_DMABMR_USP ETH_DMABMR_USP_Msk /* Use separate PBL */
18041 #define ETH_DMABMR_RDP_Pos (17U)
18042 #define ETH_DMABMR_RDP_Msk (0x3FU << ETH_DMABMR_RDP_Pos) /*!< 0x007E0000 */
18043 #define ETH_DMABMR_RDP ETH_DMABMR_RDP_Msk /* RxDMA PBL */
18044 #define ETH_DMABMR_RDP_1Beat 0x00020000U /* maximum number of beats to be transferred in one RxDMA transaction is 1 */
18045 #define ETH_DMABMR_RDP_2Beat 0x00040000U /* maximum number of beats to be transferred in one RxDMA transaction is 2 */
18046 #define ETH_DMABMR_RDP_4Beat 0x00080000U /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
18047 #define ETH_DMABMR_RDP_8Beat 0x00100000U /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
18048 #define ETH_DMABMR_RDP_16Beat 0x00200000U /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
18049 #define ETH_DMABMR_RDP_32Beat 0x00400000U /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
18050 #define ETH_DMABMR_RDP_4xPBL_4Beat 0x01020000U /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
18051 #define ETH_DMABMR_RDP_4xPBL_8Beat 0x01040000U /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
18052 #define ETH_DMABMR_RDP_4xPBL_16Beat 0x01080000U /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
18053 #define ETH_DMABMR_RDP_4xPBL_32Beat 0x01100000U /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
18054 #define ETH_DMABMR_RDP_4xPBL_64Beat 0x01200000U /* maximum number of beats to be transferred in one RxDMA transaction is 64 */
18055 #define ETH_DMABMR_RDP_4xPBL_128Beat 0x01400000U /* maximum number of beats to be transferred in one RxDMA transaction is 128 */
18056 #define ETH_DMABMR_FB_Pos (16U)
18057 #define ETH_DMABMR_FB_Msk (0x1U << ETH_DMABMR_FB_Pos) /*!< 0x00010000 */
18058 #define ETH_DMABMR_FB ETH_DMABMR_FB_Msk /* Fixed Burst */
18059 #define ETH_DMABMR_RTPR_Pos (14U)
18060 #define ETH_DMABMR_RTPR_Msk (0x3U << ETH_DMABMR_RTPR_Pos) /*!< 0x0000C000 */
18061 #define ETH_DMABMR_RTPR ETH_DMABMR_RTPR_Msk /* Rx Tx priority ratio */
18062 #define ETH_DMABMR_RTPR_1_1 0x00000000U /* Rx Tx priority ratio */
18063 #define ETH_DMABMR_RTPR_2_1 0x00004000U /* Rx Tx priority ratio */
18064 #define ETH_DMABMR_RTPR_3_1 0x00008000U /* Rx Tx priority ratio */
18065 #define ETH_DMABMR_RTPR_4_1 0x0000C000U /* Rx Tx priority ratio */
18066 #define ETH_DMABMR_PBL_Pos (8U)
18067 #define ETH_DMABMR_PBL_Msk (0x3FU << ETH_DMABMR_PBL_Pos) /*!< 0x00003F00 */
18068 #define ETH_DMABMR_PBL ETH_DMABMR_PBL_Msk /* Programmable burst length */
18069 #define ETH_DMABMR_PBL_1Beat 0x00000100U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */
18070 #define ETH_DMABMR_PBL_2Beat 0x00000200U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */
18071 #define ETH_DMABMR_PBL_4Beat 0x00000400U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
18072 #define ETH_DMABMR_PBL_8Beat 0x00000800U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
18073 #define ETH_DMABMR_PBL_16Beat 0x00001000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
18074 #define ETH_DMABMR_PBL_32Beat 0x00002000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
18075 #define ETH_DMABMR_PBL_4xPBL_4Beat 0x01000100U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
18076 #define ETH_DMABMR_PBL_4xPBL_8Beat 0x01000200U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
18077 #define ETH_DMABMR_PBL_4xPBL_16Beat 0x01000400U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
18078 #define ETH_DMABMR_PBL_4xPBL_32Beat 0x01000800U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
18079 #define ETH_DMABMR_PBL_4xPBL_64Beat 0x01001000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */
18080 #define ETH_DMABMR_PBL_4xPBL_128Beat 0x01002000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */
18081 #define ETH_DMABMR_EDE_Pos (7U)
18082 #define ETH_DMABMR_EDE_Msk (0x1U << ETH_DMABMR_EDE_Pos) /*!< 0x00000080 */
18083 #define ETH_DMABMR_EDE ETH_DMABMR_EDE_Msk /* Enhanced Descriptor Enable */
18084 #define ETH_DMABMR_DSL_Pos (2U)
18085 #define ETH_DMABMR_DSL_Msk (0x1FU << ETH_DMABMR_DSL_Pos) /*!< 0x0000007C */
18086 #define ETH_DMABMR_DSL ETH_DMABMR_DSL_Msk /* Descriptor Skip Length */
18087 #define ETH_DMABMR_DA_Pos (1U)
18088 #define ETH_DMABMR_DA_Msk (0x1U << ETH_DMABMR_DA_Pos) /*!< 0x00000002 */
18089 #define ETH_DMABMR_DA ETH_DMABMR_DA_Msk /* DMA arbitration scheme */
18090 #define ETH_DMABMR_SR_Pos (0U)
18091 #define ETH_DMABMR_SR_Msk (0x1U << ETH_DMABMR_SR_Pos) /*!< 0x00000001 */
18092 #define ETH_DMABMR_SR ETH_DMABMR_SR_Msk /* Software reset */
18093
18094 /* Bit definition for Ethernet DMA Transmit Poll Demand Register */
18095 #define ETH_DMATPDR_TPD_Pos (0U)
18096 #define ETH_DMATPDR_TPD_Msk (0xFFFFFFFFU << ETH_DMATPDR_TPD_Pos) /*!< 0xFFFFFFFF */
18097 #define ETH_DMATPDR_TPD ETH_DMATPDR_TPD_Msk /* Transmit poll demand */
18098
18099 /* Bit definition for Ethernet DMA Receive Poll Demand Register */
18100 #define ETH_DMARPDR_RPD_Pos (0U)
18101 #define ETH_DMARPDR_RPD_Msk (0xFFFFFFFFU << ETH_DMARPDR_RPD_Pos) /*!< 0xFFFFFFFF */
18102 #define ETH_DMARPDR_RPD ETH_DMARPDR_RPD_Msk /* Receive poll demand */
18103
18104 /* Bit definition for Ethernet DMA Receive Descriptor List Address Register */
18105 #define ETH_DMARDLAR_SRL_Pos (0U)
18106 #define ETH_DMARDLAR_SRL_Msk (0xFFFFFFFFU << ETH_DMARDLAR_SRL_Pos) /*!< 0xFFFFFFFF */
18107 #define ETH_DMARDLAR_SRL ETH_DMARDLAR_SRL_Msk /* Start of receive list */
18108
18109 /* Bit definition for Ethernet DMA Transmit Descriptor List Address Register */
18110 #define ETH_DMATDLAR_STL_Pos (0U)
18111 #define ETH_DMATDLAR_STL_Msk (0xFFFFFFFFU << ETH_DMATDLAR_STL_Pos) /*!< 0xFFFFFFFF */
18112 #define ETH_DMATDLAR_STL ETH_DMATDLAR_STL_Msk /* Start of transmit list */
18113
18114 /* Bit definition for Ethernet DMA Status Register */
18115 #define ETH_DMASR_TSTS_Pos (29U)
18116 #define ETH_DMASR_TSTS_Msk (0x1U << ETH_DMASR_TSTS_Pos) /*!< 0x20000000 */
18117 #define ETH_DMASR_TSTS ETH_DMASR_TSTS_Msk /* Time-stamp trigger status */
18118 #define ETH_DMASR_PMTS_Pos (28U)
18119 #define ETH_DMASR_PMTS_Msk (0x1U << ETH_DMASR_PMTS_Pos) /*!< 0x10000000 */
18120 #define ETH_DMASR_PMTS ETH_DMASR_PMTS_Msk /* PMT status */
18121 #define ETH_DMASR_MMCS_Pos (27U)
18122 #define ETH_DMASR_MMCS_Msk (0x1U << ETH_DMASR_MMCS_Pos) /*!< 0x08000000 */
18123 #define ETH_DMASR_MMCS ETH_DMASR_MMCS_Msk /* MMC status */
18124 #define ETH_DMASR_EBS_Pos (23U)
18125 #define ETH_DMASR_EBS_Msk (0x7U << ETH_DMASR_EBS_Pos) /*!< 0x03800000 */
18126 #define ETH_DMASR_EBS ETH_DMASR_EBS_Msk /* Error bits status */
18127 /* combination with EBS[2:0] for GetFlagStatus function */
18128 #define ETH_DMASR_EBS_DescAccess_Pos (25U)
18129 #define ETH_DMASR_EBS_DescAccess_Msk (0x1U << ETH_DMASR_EBS_DescAccess_Pos) /*!< 0x02000000 */
18130 #define ETH_DMASR_EBS_DescAccess ETH_DMASR_EBS_DescAccess_Msk /* Error bits 0-data buffer, 1-desc. access */
18131 #define ETH_DMASR_EBS_ReadTransf_Pos (24U)
18132 #define ETH_DMASR_EBS_ReadTransf_Msk (0x1U << ETH_DMASR_EBS_ReadTransf_Pos) /*!< 0x01000000 */
18133 #define ETH_DMASR_EBS_ReadTransf ETH_DMASR_EBS_ReadTransf_Msk /* Error bits 0-write trnsf, 1-read transfr */
18134 #define ETH_DMASR_EBS_DataTransfTx_Pos (23U)
18135 #define ETH_DMASR_EBS_DataTransfTx_Msk (0x1U << ETH_DMASR_EBS_DataTransfTx_Pos) /*!< 0x00800000 */
18136 #define ETH_DMASR_EBS_DataTransfTx ETH_DMASR_EBS_DataTransfTx_Msk /* Error bits 0-Rx DMA, 1-Tx DMA */
18137 #define ETH_DMASR_TPS_Pos (20U)
18138 #define ETH_DMASR_TPS_Msk (0x7U << ETH_DMASR_TPS_Pos) /*!< 0x00700000 */
18139 #define ETH_DMASR_TPS ETH_DMASR_TPS_Msk /* Transmit process state */
18140 #define ETH_DMASR_TPS_Stopped 0x00000000U /* Stopped - Reset or Stop Tx Command issued */
18141 #define ETH_DMASR_TPS_Fetching_Pos (20U)
18142 #define ETH_DMASR_TPS_Fetching_Msk (0x1U << ETH_DMASR_TPS_Fetching_Pos) /*!< 0x00100000 */
18143 #define ETH_DMASR_TPS_Fetching ETH_DMASR_TPS_Fetching_Msk /* Running - fetching the Tx descriptor */
18144 #define ETH_DMASR_TPS_Waiting_Pos (21U)
18145 #define ETH_DMASR_TPS_Waiting_Msk (0x1U << ETH_DMASR_TPS_Waiting_Pos) /*!< 0x00200000 */
18146 #define ETH_DMASR_TPS_Waiting ETH_DMASR_TPS_Waiting_Msk /* Running - waiting for status */
18147 #define ETH_DMASR_TPS_Reading_Pos (20U)
18148 #define ETH_DMASR_TPS_Reading_Msk (0x3U << ETH_DMASR_TPS_Reading_Pos) /*!< 0x00300000 */
18149 #define ETH_DMASR_TPS_Reading ETH_DMASR_TPS_Reading_Msk /* Running - reading the data from host memory */
18150 #define ETH_DMASR_TPS_Suspended_Pos (21U)
18151 #define ETH_DMASR_TPS_Suspended_Msk (0x3U << ETH_DMASR_TPS_Suspended_Pos) /*!< 0x00600000 */
18152 #define ETH_DMASR_TPS_Suspended ETH_DMASR_TPS_Suspended_Msk /* Suspended - Tx Descriptor unavailabe */
18153 #define ETH_DMASR_TPS_Closing_Pos (20U)
18154 #define ETH_DMASR_TPS_Closing_Msk (0x7U << ETH_DMASR_TPS_Closing_Pos) /*!< 0x00700000 */
18155 #define ETH_DMASR_TPS_Closing ETH_DMASR_TPS_Closing_Msk /* Running - closing Rx descriptor */
18156 #define ETH_DMASR_RPS_Pos (17U)
18157 #define ETH_DMASR_RPS_Msk (0x7U << ETH_DMASR_RPS_Pos) /*!< 0x000E0000 */
18158 #define ETH_DMASR_RPS ETH_DMASR_RPS_Msk /* Receive process state */
18159 #define ETH_DMASR_RPS_Stopped 0x00000000U /* Stopped - Reset or Stop Rx Command issued */
18160 #define ETH_DMASR_RPS_Fetching_Pos (17U)
18161 #define ETH_DMASR_RPS_Fetching_Msk (0x1U << ETH_DMASR_RPS_Fetching_Pos) /*!< 0x00020000 */
18162 #define ETH_DMASR_RPS_Fetching ETH_DMASR_RPS_Fetching_Msk /* Running - fetching the Rx descriptor */
18163 #define ETH_DMASR_RPS_Waiting_Pos (17U)
18164 #define ETH_DMASR_RPS_Waiting_Msk (0x3U << ETH_DMASR_RPS_Waiting_Pos) /*!< 0x00060000 */
18165 #define ETH_DMASR_RPS_Waiting ETH_DMASR_RPS_Waiting_Msk /* Running - waiting for packet */
18166 #define ETH_DMASR_RPS_Suspended_Pos (19U)
18167 #define ETH_DMASR_RPS_Suspended_Msk (0x1U << ETH_DMASR_RPS_Suspended_Pos) /*!< 0x00080000 */
18168 #define ETH_DMASR_RPS_Suspended ETH_DMASR_RPS_Suspended_Msk /* Suspended - Rx Descriptor unavailable */
18169 #define ETH_DMASR_RPS_Closing_Pos (17U)
18170 #define ETH_DMASR_RPS_Closing_Msk (0x5U << ETH_DMASR_RPS_Closing_Pos) /*!< 0x000A0000 */
18171 #define ETH_DMASR_RPS_Closing ETH_DMASR_RPS_Closing_Msk /* Running - closing descriptor */
18172 #define ETH_DMASR_RPS_Queuing_Pos (17U)
18173 #define ETH_DMASR_RPS_Queuing_Msk (0x7U << ETH_DMASR_RPS_Queuing_Pos) /*!< 0x000E0000 */
18174 #define ETH_DMASR_RPS_Queuing ETH_DMASR_RPS_Queuing_Msk /* Running - queuing the recieve frame into host memory */
18175 #define ETH_DMASR_NIS_Pos (16U)
18176 #define ETH_DMASR_NIS_Msk (0x1U << ETH_DMASR_NIS_Pos) /*!< 0x00010000 */
18177 #define ETH_DMASR_NIS ETH_DMASR_NIS_Msk /* Normal interrupt summary */
18178 #define ETH_DMASR_AIS_Pos (15U)
18179 #define ETH_DMASR_AIS_Msk (0x1U << ETH_DMASR_AIS_Pos) /*!< 0x00008000 */
18180 #define ETH_DMASR_AIS ETH_DMASR_AIS_Msk /* Abnormal interrupt summary */
18181 #define ETH_DMASR_ERS_Pos (14U)
18182 #define ETH_DMASR_ERS_Msk (0x1U << ETH_DMASR_ERS_Pos) /*!< 0x00004000 */
18183 #define ETH_DMASR_ERS ETH_DMASR_ERS_Msk /* Early receive status */
18184 #define ETH_DMASR_FBES_Pos (13U)
18185 #define ETH_DMASR_FBES_Msk (0x1U << ETH_DMASR_FBES_Pos) /*!< 0x00002000 */
18186 #define ETH_DMASR_FBES ETH_DMASR_FBES_Msk /* Fatal bus error status */
18187 #define ETH_DMASR_ETS_Pos (10U)
18188 #define ETH_DMASR_ETS_Msk (0x1U << ETH_DMASR_ETS_Pos) /*!< 0x00000400 */
18189 #define ETH_DMASR_ETS ETH_DMASR_ETS_Msk /* Early transmit status */
18190 #define ETH_DMASR_RWTS_Pos (9U)
18191 #define ETH_DMASR_RWTS_Msk (0x1U << ETH_DMASR_RWTS_Pos) /*!< 0x00000200 */
18192 #define ETH_DMASR_RWTS ETH_DMASR_RWTS_Msk /* Receive watchdog timeout status */
18193 #define ETH_DMASR_RPSS_Pos (8U)
18194 #define ETH_DMASR_RPSS_Msk (0x1U << ETH_DMASR_RPSS_Pos) /*!< 0x00000100 */
18195 #define ETH_DMASR_RPSS ETH_DMASR_RPSS_Msk /* Receive process stopped status */
18196 #define ETH_DMASR_RBUS_Pos (7U)
18197 #define ETH_DMASR_RBUS_Msk (0x1U << ETH_DMASR_RBUS_Pos) /*!< 0x00000080 */
18198 #define ETH_DMASR_RBUS ETH_DMASR_RBUS_Msk /* Receive buffer unavailable status */
18199 #define ETH_DMASR_RS_Pos (6U)
18200 #define ETH_DMASR_RS_Msk (0x1U << ETH_DMASR_RS_Pos) /*!< 0x00000040 */
18201 #define ETH_DMASR_RS ETH_DMASR_RS_Msk /* Receive status */
18202 #define ETH_DMASR_TUS_Pos (5U)
18203 #define ETH_DMASR_TUS_Msk (0x1U << ETH_DMASR_TUS_Pos) /*!< 0x00000020 */
18204 #define ETH_DMASR_TUS ETH_DMASR_TUS_Msk /* Transmit underflow status */
18205 #define ETH_DMASR_ROS_Pos (4U)
18206 #define ETH_DMASR_ROS_Msk (0x1U << ETH_DMASR_ROS_Pos) /*!< 0x00000010 */
18207 #define ETH_DMASR_ROS ETH_DMASR_ROS_Msk /* Receive overflow status */
18208 #define ETH_DMASR_TJTS_Pos (3U)
18209 #define ETH_DMASR_TJTS_Msk (0x1U << ETH_DMASR_TJTS_Pos) /*!< 0x00000008 */
18210 #define ETH_DMASR_TJTS ETH_DMASR_TJTS_Msk /* Transmit jabber timeout status */
18211 #define ETH_DMASR_TBUS_Pos (2U)
18212 #define ETH_DMASR_TBUS_Msk (0x1U << ETH_DMASR_TBUS_Pos) /*!< 0x00000004 */
18213 #define ETH_DMASR_TBUS ETH_DMASR_TBUS_Msk /* Transmit buffer unavailable status */
18214 #define ETH_DMASR_TPSS_Pos (1U)
18215 #define ETH_DMASR_TPSS_Msk (0x1U << ETH_DMASR_TPSS_Pos) /*!< 0x00000002 */
18216 #define ETH_DMASR_TPSS ETH_DMASR_TPSS_Msk /* Transmit process stopped status */
18217 #define ETH_DMASR_TS_Pos (0U)
18218 #define ETH_DMASR_TS_Msk (0x1U << ETH_DMASR_TS_Pos) /*!< 0x00000001 */
18219 #define ETH_DMASR_TS ETH_DMASR_TS_Msk /* Transmit status */
18220
18221 /* Bit definition for Ethernet DMA Operation Mode Register */
18222 #define ETH_DMAOMR_DTCEFD_Pos (26U)
18223 #define ETH_DMAOMR_DTCEFD_Msk (0x1U << ETH_DMAOMR_DTCEFD_Pos) /*!< 0x04000000 */
18224 #define ETH_DMAOMR_DTCEFD ETH_DMAOMR_DTCEFD_Msk /* Disable Dropping of TCP/IP checksum error frames */
18225 #define ETH_DMAOMR_RSF_Pos (25U)
18226 #define ETH_DMAOMR_RSF_Msk (0x1U << ETH_DMAOMR_RSF_Pos) /*!< 0x02000000 */
18227 #define ETH_DMAOMR_RSF ETH_DMAOMR_RSF_Msk /* Receive store and forward */
18228 #define ETH_DMAOMR_DFRF_Pos (24U)
18229 #define ETH_DMAOMR_DFRF_Msk (0x1U << ETH_DMAOMR_DFRF_Pos) /*!< 0x01000000 */
18230 #define ETH_DMAOMR_DFRF ETH_DMAOMR_DFRF_Msk /* Disable flushing of received frames */
18231 #define ETH_DMAOMR_TSF_Pos (21U)
18232 #define ETH_DMAOMR_TSF_Msk (0x1U << ETH_DMAOMR_TSF_Pos) /*!< 0x00200000 */
18233 #define ETH_DMAOMR_TSF ETH_DMAOMR_TSF_Msk /* Transmit store and forward */
18234 #define ETH_DMAOMR_FTF_Pos (20U)
18235 #define ETH_DMAOMR_FTF_Msk (0x1U << ETH_DMAOMR_FTF_Pos) /*!< 0x00100000 */
18236 #define ETH_DMAOMR_FTF ETH_DMAOMR_FTF_Msk /* Flush transmit FIFO */
18237 #define ETH_DMAOMR_TTC_Pos (14U)
18238 #define ETH_DMAOMR_TTC_Msk (0x7U << ETH_DMAOMR_TTC_Pos) /*!< 0x0001C000 */
18239 #define ETH_DMAOMR_TTC ETH_DMAOMR_TTC_Msk /* Transmit threshold control */
18240 #define ETH_DMAOMR_TTC_64Bytes 0x00000000U /* threshold level of the MTL Transmit FIFO is 64 Bytes */
18241 #define ETH_DMAOMR_TTC_128Bytes 0x00004000U /* threshold level of the MTL Transmit FIFO is 128 Bytes */
18242 #define ETH_DMAOMR_TTC_192Bytes 0x00008000U /* threshold level of the MTL Transmit FIFO is 192 Bytes */
18243 #define ETH_DMAOMR_TTC_256Bytes 0x0000C000U /* threshold level of the MTL Transmit FIFO is 256 Bytes */
18244 #define ETH_DMAOMR_TTC_40Bytes 0x00010000U /* threshold level of the MTL Transmit FIFO is 40 Bytes */
18245 #define ETH_DMAOMR_TTC_32Bytes 0x00014000U /* threshold level of the MTL Transmit FIFO is 32 Bytes */
18246 #define ETH_DMAOMR_TTC_24Bytes 0x00018000U /* threshold level of the MTL Transmit FIFO is 24 Bytes */
18247 #define ETH_DMAOMR_TTC_16Bytes 0x0001C000U /* threshold level of the MTL Transmit FIFO is 16 Bytes */
18248 #define ETH_DMAOMR_ST_Pos (13U)
18249 #define ETH_DMAOMR_ST_Msk (0x1U << ETH_DMAOMR_ST_Pos) /*!< 0x00002000 */
18250 #define ETH_DMAOMR_ST ETH_DMAOMR_ST_Msk /* Start/stop transmission command */
18251 #define ETH_DMAOMR_FEF_Pos (7U)
18252 #define ETH_DMAOMR_FEF_Msk (0x1U << ETH_DMAOMR_FEF_Pos) /*!< 0x00000080 */
18253 #define ETH_DMAOMR_FEF ETH_DMAOMR_FEF_Msk /* Forward error frames */
18254 #define ETH_DMAOMR_FUGF_Pos (6U)
18255 #define ETH_DMAOMR_FUGF_Msk (0x1U << ETH_DMAOMR_FUGF_Pos) /*!< 0x00000040 */
18256 #define ETH_DMAOMR_FUGF ETH_DMAOMR_FUGF_Msk /* Forward undersized good frames */
18257 #define ETH_DMAOMR_RTC_Pos (3U)
18258 #define ETH_DMAOMR_RTC_Msk (0x3U << ETH_DMAOMR_RTC_Pos) /*!< 0x00000018 */
18259 #define ETH_DMAOMR_RTC ETH_DMAOMR_RTC_Msk /* receive threshold control */
18260 #define ETH_DMAOMR_RTC_64Bytes 0x00000000U /* threshold level of the MTL Receive FIFO is 64 Bytes */
18261 #define ETH_DMAOMR_RTC_32Bytes 0x00000008U /* threshold level of the MTL Receive FIFO is 32 Bytes */
18262 #define ETH_DMAOMR_RTC_96Bytes 0x00000010U /* threshold level of the MTL Receive FIFO is 96 Bytes */
18263 #define ETH_DMAOMR_RTC_128Bytes 0x00000018U /* threshold level of the MTL Receive FIFO is 128 Bytes */
18264 #define ETH_DMAOMR_OSF_Pos (2U)
18265 #define ETH_DMAOMR_OSF_Msk (0x1U << ETH_DMAOMR_OSF_Pos) /*!< 0x00000004 */
18266 #define ETH_DMAOMR_OSF ETH_DMAOMR_OSF_Msk /* operate on second frame */
18267 #define ETH_DMAOMR_SR_Pos (1U)
18268 #define ETH_DMAOMR_SR_Msk (0x1U << ETH_DMAOMR_SR_Pos) /*!< 0x00000002 */
18269 #define ETH_DMAOMR_SR ETH_DMAOMR_SR_Msk /* Start/stop receive */
18270
18271 /* Bit definition for Ethernet DMA Interrupt Enable Register */
18272 #define ETH_DMAIER_NISE_Pos (16U)
18273 #define ETH_DMAIER_NISE_Msk (0x1U << ETH_DMAIER_NISE_Pos) /*!< 0x00010000 */
18274 #define ETH_DMAIER_NISE ETH_DMAIER_NISE_Msk /* Normal interrupt summary enable */
18275 #define ETH_DMAIER_AISE_Pos (15U)
18276 #define ETH_DMAIER_AISE_Msk (0x1U << ETH_DMAIER_AISE_Pos) /*!< 0x00008000 */
18277 #define ETH_DMAIER_AISE ETH_DMAIER_AISE_Msk /* Abnormal interrupt summary enable */
18278 #define ETH_DMAIER_ERIE_Pos (14U)
18279 #define ETH_DMAIER_ERIE_Msk (0x1U << ETH_DMAIER_ERIE_Pos) /*!< 0x00004000 */
18280 #define ETH_DMAIER_ERIE ETH_DMAIER_ERIE_Msk /* Early receive interrupt enable */
18281 #define ETH_DMAIER_FBEIE_Pos (13U)
18282 #define ETH_DMAIER_FBEIE_Msk (0x1U << ETH_DMAIER_FBEIE_Pos) /*!< 0x00002000 */
18283 #define ETH_DMAIER_FBEIE ETH_DMAIER_FBEIE_Msk /* Fatal bus error interrupt enable */
18284 #define ETH_DMAIER_ETIE_Pos (10U)
18285 #define ETH_DMAIER_ETIE_Msk (0x1U << ETH_DMAIER_ETIE_Pos) /*!< 0x00000400 */
18286 #define ETH_DMAIER_ETIE ETH_DMAIER_ETIE_Msk /* Early transmit interrupt enable */
18287 #define ETH_DMAIER_RWTIE_Pos (9U)
18288 #define ETH_DMAIER_RWTIE_Msk (0x1U << ETH_DMAIER_RWTIE_Pos) /*!< 0x00000200 */
18289 #define ETH_DMAIER_RWTIE ETH_DMAIER_RWTIE_Msk /* Receive watchdog timeout interrupt enable */
18290 #define ETH_DMAIER_RPSIE_Pos (8U)
18291 #define ETH_DMAIER_RPSIE_Msk (0x1U << ETH_DMAIER_RPSIE_Pos) /*!< 0x00000100 */
18292 #define ETH_DMAIER_RPSIE ETH_DMAIER_RPSIE_Msk /* Receive process stopped interrupt enable */
18293 #define ETH_DMAIER_RBUIE_Pos (7U)
18294 #define ETH_DMAIER_RBUIE_Msk (0x1U << ETH_DMAIER_RBUIE_Pos) /*!< 0x00000080 */
18295 #define ETH_DMAIER_RBUIE ETH_DMAIER_RBUIE_Msk /* Receive buffer unavailable interrupt enable */
18296 #define ETH_DMAIER_RIE_Pos (6U)
18297 #define ETH_DMAIER_RIE_Msk (0x1U << ETH_DMAIER_RIE_Pos) /*!< 0x00000040 */
18298 #define ETH_DMAIER_RIE ETH_DMAIER_RIE_Msk /* Receive interrupt enable */
18299 #define ETH_DMAIER_TUIE_Pos (5U)
18300 #define ETH_DMAIER_TUIE_Msk (0x1U << ETH_DMAIER_TUIE_Pos) /*!< 0x00000020 */
18301 #define ETH_DMAIER_TUIE ETH_DMAIER_TUIE_Msk /* Transmit Underflow interrupt enable */
18302 #define ETH_DMAIER_ROIE_Pos (4U)
18303 #define ETH_DMAIER_ROIE_Msk (0x1U << ETH_DMAIER_ROIE_Pos) /*!< 0x00000010 */
18304 #define ETH_DMAIER_ROIE ETH_DMAIER_ROIE_Msk /* Receive Overflow interrupt enable */
18305 #define ETH_DMAIER_TJTIE_Pos (3U)
18306 #define ETH_DMAIER_TJTIE_Msk (0x1U << ETH_DMAIER_TJTIE_Pos) /*!< 0x00000008 */
18307 #define ETH_DMAIER_TJTIE ETH_DMAIER_TJTIE_Msk /* Transmit jabber timeout interrupt enable */
18308 #define ETH_DMAIER_TBUIE_Pos (2U)
18309 #define ETH_DMAIER_TBUIE_Msk (0x1U << ETH_DMAIER_TBUIE_Pos) /*!< 0x00000004 */
18310 #define ETH_DMAIER_TBUIE ETH_DMAIER_TBUIE_Msk /* Transmit buffer unavailable interrupt enable */
18311 #define ETH_DMAIER_TPSIE_Pos (1U)
18312 #define ETH_DMAIER_TPSIE_Msk (0x1U << ETH_DMAIER_TPSIE_Pos) /*!< 0x00000002 */
18313 #define ETH_DMAIER_TPSIE ETH_DMAIER_TPSIE_Msk /* Transmit process stopped interrupt enable */
18314 #define ETH_DMAIER_TIE_Pos (0U)
18315 #define ETH_DMAIER_TIE_Msk (0x1U << ETH_DMAIER_TIE_Pos) /*!< 0x00000001 */
18316 #define ETH_DMAIER_TIE ETH_DMAIER_TIE_Msk /* Transmit interrupt enable */
18317
18318 /* Bit definition for Ethernet DMA Missed Frame and Buffer Overflow Counter Register */
18319 #define ETH_DMAMFBOCR_OFOC_Pos (28U)
18320 #define ETH_DMAMFBOCR_OFOC_Msk (0x1U << ETH_DMAMFBOCR_OFOC_Pos) /*!< 0x10000000 */
18321 #define ETH_DMAMFBOCR_OFOC ETH_DMAMFBOCR_OFOC_Msk /* Overflow bit for FIFO overflow counter */
18322 #define ETH_DMAMFBOCR_MFA_Pos (17U)
18323 #define ETH_DMAMFBOCR_MFA_Msk (0x7FFU << ETH_DMAMFBOCR_MFA_Pos) /*!< 0x0FFE0000 */
18324 #define ETH_DMAMFBOCR_MFA ETH_DMAMFBOCR_MFA_Msk /* Number of frames missed by the application */
18325 #define ETH_DMAMFBOCR_OMFC_Pos (16U)
18326 #define ETH_DMAMFBOCR_OMFC_Msk (0x1U << ETH_DMAMFBOCR_OMFC_Pos) /*!< 0x00010000 */
18327 #define ETH_DMAMFBOCR_OMFC ETH_DMAMFBOCR_OMFC_Msk /* Overflow bit for missed frame counter */
18328 #define ETH_DMAMFBOCR_MFC_Pos (0U)
18329 #define ETH_DMAMFBOCR_MFC_Msk (0xFFFFU << ETH_DMAMFBOCR_MFC_Pos) /*!< 0x0000FFFF */
18330 #define ETH_DMAMFBOCR_MFC ETH_DMAMFBOCR_MFC_Msk /* Number of frames missed by the controller */
18331
18332 /* Bit definition for Ethernet DMA Current Host Transmit Descriptor Register */
18333 #define ETH_DMACHTDR_HTDAP_Pos (0U)
18334 #define ETH_DMACHTDR_HTDAP_Msk (0xFFFFFFFFU << ETH_DMACHTDR_HTDAP_Pos) /*!< 0xFFFFFFFF */
18335 #define ETH_DMACHTDR_HTDAP ETH_DMACHTDR_HTDAP_Msk /* Host transmit descriptor address pointer */
18336
18337 /* Bit definition for Ethernet DMA Current Host Receive Descriptor Register */
18338 #define ETH_DMACHRDR_HRDAP_Pos (0U)
18339 #define ETH_DMACHRDR_HRDAP_Msk (0xFFFFFFFFU << ETH_DMACHRDR_HRDAP_Pos) /*!< 0xFFFFFFFF */
18340 #define ETH_DMACHRDR_HRDAP ETH_DMACHRDR_HRDAP_Msk /* Host receive descriptor address pointer */
18341
18342 /* Bit definition for Ethernet DMA Current Host Transmit Buffer Address Register */
18343 #define ETH_DMACHTBAR_HTBAP_Pos (0U)
18344 #define ETH_DMACHTBAR_HTBAP_Msk (0xFFFFFFFFU << ETH_DMACHTBAR_HTBAP_Pos) /*!< 0xFFFFFFFF */
18345 #define ETH_DMACHTBAR_HTBAP ETH_DMACHTBAR_HTBAP_Msk /* Host transmit buffer address pointer */
18346
18347 /* Bit definition for Ethernet DMA Current Host Receive Buffer Address Register */
18348 #define ETH_DMACHRBAR_HRBAP_Pos (0U)
18349 #define ETH_DMACHRBAR_HRBAP_Msk (0xFFFFFFFFU << ETH_DMACHRBAR_HRBAP_Pos) /*!< 0xFFFFFFFF */
18350 #define ETH_DMACHRBAR_HRBAP ETH_DMACHRBAR_HRBAP_Msk /* Host receive buffer address pointer */
18351
18352 /******************************************************************************/
18353 /* */
18354 /* USB_OTG */
18355 /* */
18356 /******************************************************************************/
18357 /******************** Bit definition for USB_OTG_GOTGCTL register ***********/
18358 #define USB_OTG_GOTGCTL_SRQSCS_Pos (0U)
18359 #define USB_OTG_GOTGCTL_SRQSCS_Msk (0x1U << USB_OTG_GOTGCTL_SRQSCS_Pos) /*!< 0x00000001 */
18360 #define USB_OTG_GOTGCTL_SRQSCS USB_OTG_GOTGCTL_SRQSCS_Msk /*!< Session request success */
18361 #define USB_OTG_GOTGCTL_SRQ_Pos (1U)
18362 #define USB_OTG_GOTGCTL_SRQ_Msk (0x1U << USB_OTG_GOTGCTL_SRQ_Pos) /*!< 0x00000002 */
18363 #define USB_OTG_GOTGCTL_SRQ USB_OTG_GOTGCTL_SRQ_Msk /*!< Session request */
18364 #define USB_OTG_GOTGCTL_VBVALOEN_Pos (2U)
18365 #define USB_OTG_GOTGCTL_VBVALOEN_Msk (0x1U << USB_OTG_GOTGCTL_VBVALOEN_Pos) /*!< 0x00000004 */
18366 #define USB_OTG_GOTGCTL_VBVALOEN USB_OTG_GOTGCTL_VBVALOEN_Msk /*!< VBUS valid override enable */
18367 #define USB_OTG_GOTGCTL_VBVALOVAL_Pos (3U)
18368 #define USB_OTG_GOTGCTL_VBVALOVAL_Msk (0x1U << USB_OTG_GOTGCTL_VBVALOVAL_Pos) /*!< 0x00000008 */
18369 #define USB_OTG_GOTGCTL_VBVALOVAL USB_OTG_GOTGCTL_VBVALOVAL_Msk /*!< VBUS valid override value */
18370 #define USB_OTG_GOTGCTL_AVALOEN_Pos (4U)
18371 #define USB_OTG_GOTGCTL_AVALOEN_Msk (0x1U << USB_OTG_GOTGCTL_AVALOEN_Pos) /*!< 0x00000010 */
18372 #define USB_OTG_GOTGCTL_AVALOEN USB_OTG_GOTGCTL_AVALOEN_Msk /*!< A-peripheral session valid override enable */
18373 #define USB_OTG_GOTGCTL_AVALOVAL_Pos (5U)
18374 #define USB_OTG_GOTGCTL_AVALOVAL_Msk (0x1U << USB_OTG_GOTGCTL_AVALOVAL_Pos) /*!< 0x00000020 */
18375 #define USB_OTG_GOTGCTL_AVALOVAL USB_OTG_GOTGCTL_AVALOVAL_Msk /*!< A-peripheral session valid override value */
18376 #define USB_OTG_GOTGCTL_BVALOEN_Pos (6U)
18377 #define USB_OTG_GOTGCTL_BVALOEN_Msk (0x1U << USB_OTG_GOTGCTL_BVALOEN_Pos) /*!< 0x00000040 */
18378 #define USB_OTG_GOTGCTL_BVALOEN USB_OTG_GOTGCTL_BVALOEN_Msk /*!< B-peripheral session valid override enable */
18379 #define USB_OTG_GOTGCTL_BVALOVAL_Pos (7U)
18380 #define USB_OTG_GOTGCTL_BVALOVAL_Msk (0x1U << USB_OTG_GOTGCTL_BVALOVAL_Pos) /*!< 0x00000080 */
18381 #define USB_OTG_GOTGCTL_BVALOVAL USB_OTG_GOTGCTL_BVALOVAL_Msk /*!< B-peripheral session valid override value */
18382 #define USB_OTG_GOTGCTL_HNGSCS_Pos (8U)
18383 #define USB_OTG_GOTGCTL_HNGSCS_Msk (0x1U << USB_OTG_GOTGCTL_HNGSCS_Pos) /*!< 0x00000100 */
18384 #define USB_OTG_GOTGCTL_HNGSCS USB_OTG_GOTGCTL_HNGSCS_Msk /*!< Host set HNP enable */
18385 #define USB_OTG_GOTGCTL_HNPRQ_Pos (9U)
18386 #define USB_OTG_GOTGCTL_HNPRQ_Msk (0x1U << USB_OTG_GOTGCTL_HNPRQ_Pos) /*!< 0x00000200 */
18387 #define USB_OTG_GOTGCTL_HNPRQ USB_OTG_GOTGCTL_HNPRQ_Msk /*!< HNP request */
18388 #define USB_OTG_GOTGCTL_HSHNPEN_Pos (10U)
18389 #define USB_OTG_GOTGCTL_HSHNPEN_Msk (0x1U << USB_OTG_GOTGCTL_HSHNPEN_Pos) /*!< 0x00000400 */
18390 #define USB_OTG_GOTGCTL_HSHNPEN USB_OTG_GOTGCTL_HSHNPEN_Msk /*!< Host set HNP enable */
18391 #define USB_OTG_GOTGCTL_DHNPEN_Pos (11U)
18392 #define USB_OTG_GOTGCTL_DHNPEN_Msk (0x1U << USB_OTG_GOTGCTL_DHNPEN_Pos) /*!< 0x00000800 */
18393 #define USB_OTG_GOTGCTL_DHNPEN USB_OTG_GOTGCTL_DHNPEN_Msk /*!< Device HNP enabled */
18394 #define USB_OTG_GOTGCTL_EHEN_Pos (12U)
18395 #define USB_OTG_GOTGCTL_EHEN_Msk (0x1U << USB_OTG_GOTGCTL_EHEN_Pos) /*!< 0x00001000 */
18396 #define USB_OTG_GOTGCTL_EHEN USB_OTG_GOTGCTL_EHEN_Msk /*!< Embedded host enable */
18397 #define USB_OTG_GOTGCTL_CIDSTS_Pos (16U)
18398 #define USB_OTG_GOTGCTL_CIDSTS_Msk (0x1U << USB_OTG_GOTGCTL_CIDSTS_Pos) /*!< 0x00010000 */
18399 #define USB_OTG_GOTGCTL_CIDSTS USB_OTG_GOTGCTL_CIDSTS_Msk /*!< Connector ID status */
18400 #define USB_OTG_GOTGCTL_DBCT_Pos (17U)
18401 #define USB_OTG_GOTGCTL_DBCT_Msk (0x1U << USB_OTG_GOTGCTL_DBCT_Pos) /*!< 0x00020000 */
18402 #define USB_OTG_GOTGCTL_DBCT USB_OTG_GOTGCTL_DBCT_Msk /*!< Long/short debounce time */
18403 #define USB_OTG_GOTGCTL_ASVLD_Pos (18U)
18404 #define USB_OTG_GOTGCTL_ASVLD_Msk (0x1U << USB_OTG_GOTGCTL_ASVLD_Pos) /*!< 0x00040000 */
18405 #define USB_OTG_GOTGCTL_ASVLD USB_OTG_GOTGCTL_ASVLD_Msk /*!< A-session valid */
18406 #define USB_OTG_GOTGCTL_BSESVLD_Pos (19U)
18407 #define USB_OTG_GOTGCTL_BSESVLD_Msk (0x1U << USB_OTG_GOTGCTL_BSESVLD_Pos) /*!< 0x00080000 */
18408 #define USB_OTG_GOTGCTL_BSESVLD USB_OTG_GOTGCTL_BSESVLD_Msk /*!< B-session valid */
18409 #define USB_OTG_GOTGCTL_OTGVER_Pos (20U)
18410 #define USB_OTG_GOTGCTL_OTGVER_Msk (0x1U << USB_OTG_GOTGCTL_OTGVER_Pos) /*!< 0x00100000 */
18411 #define USB_OTG_GOTGCTL_OTGVER USB_OTG_GOTGCTL_OTGVER_Msk /*!< OTG version */
18412
18413 /******************** Bit definition forUSB_OTG_HCFG register ********************/
18414
18415 #define USB_OTG_HCFG_FSLSPCS_Pos (0U)
18416 #define USB_OTG_HCFG_FSLSPCS_Msk (0x3U << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000003 */
18417 #define USB_OTG_HCFG_FSLSPCS USB_OTG_HCFG_FSLSPCS_Msk /*!< FS/LS PHY clock select */
18418 #define USB_OTG_HCFG_FSLSPCS_0 (0x1U << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000001 */
18419 #define USB_OTG_HCFG_FSLSPCS_1 (0x2U << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000002 */
18420 #define USB_OTG_HCFG_FSLSS_Pos (2U)
18421 #define USB_OTG_HCFG_FSLSS_Msk (0x1U << USB_OTG_HCFG_FSLSS_Pos) /*!< 0x00000004 */
18422 #define USB_OTG_HCFG_FSLSS USB_OTG_HCFG_FSLSS_Msk /*!< FS- and LS-only support */
18423
18424 /******************** Bit definition for USB_OTG_DCFG register ********************/
18425
18426 #define USB_OTG_DCFG_DSPD_Pos (0U)
18427 #define USB_OTG_DCFG_DSPD_Msk (0x3U << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000003 */
18428 #define USB_OTG_DCFG_DSPD USB_OTG_DCFG_DSPD_Msk /*!< Device speed */
18429 #define USB_OTG_DCFG_DSPD_0 (0x1U << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000001 */
18430 #define USB_OTG_DCFG_DSPD_1 (0x2U << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000002 */
18431 #define USB_OTG_DCFG_NZLSOHSK_Pos (2U)
18432 #define USB_OTG_DCFG_NZLSOHSK_Msk (0x1U << USB_OTG_DCFG_NZLSOHSK_Pos) /*!< 0x00000004 */
18433 #define USB_OTG_DCFG_NZLSOHSK USB_OTG_DCFG_NZLSOHSK_Msk /*!< Nonzero-length status OUT handshake */
18434
18435 #define USB_OTG_DCFG_DAD_Pos (4U)
18436 #define USB_OTG_DCFG_DAD_Msk (0x7FU << USB_OTG_DCFG_DAD_Pos) /*!< 0x000007F0 */
18437 #define USB_OTG_DCFG_DAD USB_OTG_DCFG_DAD_Msk /*!< Device address */
18438 #define USB_OTG_DCFG_DAD_0 (0x01U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000010 */
18439 #define USB_OTG_DCFG_DAD_1 (0x02U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000020 */
18440 #define USB_OTG_DCFG_DAD_2 (0x04U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000040 */
18441 #define USB_OTG_DCFG_DAD_3 (0x08U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000080 */
18442 #define USB_OTG_DCFG_DAD_4 (0x10U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000100 */
18443 #define USB_OTG_DCFG_DAD_5 (0x20U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000200 */
18444 #define USB_OTG_DCFG_DAD_6 (0x40U << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000400 */
18445
18446 #define USB_OTG_DCFG_PFIVL_Pos (11U)
18447 #define USB_OTG_DCFG_PFIVL_Msk (0x3U << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001800 */
18448 #define USB_OTG_DCFG_PFIVL USB_OTG_DCFG_PFIVL_Msk /*!< Periodic (micro)frame interval */
18449 #define USB_OTG_DCFG_PFIVL_0 (0x1U << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00000800 */
18450 #define USB_OTG_DCFG_PFIVL_1 (0x2U << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001000 */
18451
18452 #define USB_OTG_DCFG_PERSCHIVL_Pos (24U)
18453 #define USB_OTG_DCFG_PERSCHIVL_Msk (0x3U << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x03000000 */
18454 #define USB_OTG_DCFG_PERSCHIVL USB_OTG_DCFG_PERSCHIVL_Msk /*!< Periodic scheduling interval */
18455 #define USB_OTG_DCFG_PERSCHIVL_0 (0x1U << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x01000000 */
18456 #define USB_OTG_DCFG_PERSCHIVL_1 (0x2U << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x02000000 */
18457
18458 /******************** Bit definition for USB_OTG_PCGCR register ********************/
18459 #define USB_OTG_PCGCR_STPPCLK_Pos (0U)
18460 #define USB_OTG_PCGCR_STPPCLK_Msk (0x1U << USB_OTG_PCGCR_STPPCLK_Pos) /*!< 0x00000001 */
18461 #define USB_OTG_PCGCR_STPPCLK USB_OTG_PCGCR_STPPCLK_Msk /*!< Stop PHY clock */
18462 #define USB_OTG_PCGCR_GATEHCLK_Pos (1U)
18463 #define USB_OTG_PCGCR_GATEHCLK_Msk (0x1U << USB_OTG_PCGCR_GATEHCLK_Pos) /*!< 0x00000002 */
18464 #define USB_OTG_PCGCR_GATEHCLK USB_OTG_PCGCR_GATEHCLK_Msk /*!< Gate HCLK */
18465 #define USB_OTG_PCGCR_PHYSUSP_Pos (4U)
18466 #define USB_OTG_PCGCR_PHYSUSP_Msk (0x1U << USB_OTG_PCGCR_PHYSUSP_Pos) /*!< 0x00000010 */
18467 #define USB_OTG_PCGCR_PHYSUSP USB_OTG_PCGCR_PHYSUSP_Msk /*!< PHY suspended */
18468
18469 /******************** Bit definition for USB_OTG_GOTGINT register ********************/
18470 #define USB_OTG_GOTGINT_SEDET_Pos (2U)
18471 #define USB_OTG_GOTGINT_SEDET_Msk (0x1U << USB_OTG_GOTGINT_SEDET_Pos) /*!< 0x00000004 */
18472 #define USB_OTG_GOTGINT_SEDET USB_OTG_GOTGINT_SEDET_Msk /*!< Session end detected */
18473 #define USB_OTG_GOTGINT_SRSSCHG_Pos (8U)
18474 #define USB_OTG_GOTGINT_SRSSCHG_Msk (0x1U << USB_OTG_GOTGINT_SRSSCHG_Pos) /*!< 0x00000100 */
18475 #define USB_OTG_GOTGINT_SRSSCHG USB_OTG_GOTGINT_SRSSCHG_Msk /*!< Session request success status change */
18476 #define USB_OTG_GOTGINT_HNSSCHG_Pos (9U)
18477 #define USB_OTG_GOTGINT_HNSSCHG_Msk (0x1U << USB_OTG_GOTGINT_HNSSCHG_Pos) /*!< 0x00000200 */
18478 #define USB_OTG_GOTGINT_HNSSCHG USB_OTG_GOTGINT_HNSSCHG_Msk /*!< Host negotiation success status change */
18479 #define USB_OTG_GOTGINT_HNGDET_Pos (17U)
18480 #define USB_OTG_GOTGINT_HNGDET_Msk (0x1U << USB_OTG_GOTGINT_HNGDET_Pos) /*!< 0x00020000 */
18481 #define USB_OTG_GOTGINT_HNGDET USB_OTG_GOTGINT_HNGDET_Msk /*!< Host negotiation detected */
18482 #define USB_OTG_GOTGINT_ADTOCHG_Pos (18U)
18483 #define USB_OTG_GOTGINT_ADTOCHG_Msk (0x1U << USB_OTG_GOTGINT_ADTOCHG_Pos) /*!< 0x00040000 */
18484 #define USB_OTG_GOTGINT_ADTOCHG USB_OTG_GOTGINT_ADTOCHG_Msk /*!< A-device timeout change */
18485 #define USB_OTG_GOTGINT_DBCDNE_Pos (19U)
18486 #define USB_OTG_GOTGINT_DBCDNE_Msk (0x1U << USB_OTG_GOTGINT_DBCDNE_Pos) /*!< 0x00080000 */
18487 #define USB_OTG_GOTGINT_DBCDNE USB_OTG_GOTGINT_DBCDNE_Msk /*!< Debounce done */
18488 #define USB_OTG_GOTGINT_IDCHNG_Pos (20U)
18489 #define USB_OTG_GOTGINT_IDCHNG_Msk (0x1U << USB_OTG_GOTGINT_IDCHNG_Pos) /*!< 0x00100000 */
18490 #define USB_OTG_GOTGINT_IDCHNG USB_OTG_GOTGINT_IDCHNG_Msk /*!< Change in ID pin input value */
18491
18492 /******************** Bit definition for USB_OTG_DCTL register ********************/
18493 #define USB_OTG_DCTL_RWUSIG_Pos (0U)
18494 #define USB_OTG_DCTL_RWUSIG_Msk (0x1U << USB_OTG_DCTL_RWUSIG_Pos) /*!< 0x00000001 */
18495 #define USB_OTG_DCTL_RWUSIG USB_OTG_DCTL_RWUSIG_Msk /*!< Remote wakeup signaling */
18496 #define USB_OTG_DCTL_SDIS_Pos (1U)
18497 #define USB_OTG_DCTL_SDIS_Msk (0x1U << USB_OTG_DCTL_SDIS_Pos) /*!< 0x00000002 */
18498 #define USB_OTG_DCTL_SDIS USB_OTG_DCTL_SDIS_Msk /*!< Soft disconnect */
18499 #define USB_OTG_DCTL_GINSTS_Pos (2U)
18500 #define USB_OTG_DCTL_GINSTS_Msk (0x1U << USB_OTG_DCTL_GINSTS_Pos) /*!< 0x00000004 */
18501 #define USB_OTG_DCTL_GINSTS USB_OTG_DCTL_GINSTS_Msk /*!< Global IN NAK status */
18502 #define USB_OTG_DCTL_GONSTS_Pos (3U)
18503 #define USB_OTG_DCTL_GONSTS_Msk (0x1U << USB_OTG_DCTL_GONSTS_Pos) /*!< 0x00000008 */
18504 #define USB_OTG_DCTL_GONSTS USB_OTG_DCTL_GONSTS_Msk /*!< Global OUT NAK status */
18505
18506 #define USB_OTG_DCTL_TCTL_Pos (4U)
18507 #define USB_OTG_DCTL_TCTL_Msk (0x7U << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000070 */
18508 #define USB_OTG_DCTL_TCTL USB_OTG_DCTL_TCTL_Msk /*!< Test control */
18509 #define USB_OTG_DCTL_TCTL_0 (0x1U << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000010 */
18510 #define USB_OTG_DCTL_TCTL_1 (0x2U << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000020 */
18511 #define USB_OTG_DCTL_TCTL_2 (0x4U << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000040 */
18512 #define USB_OTG_DCTL_SGINAK_Pos (7U)
18513 #define USB_OTG_DCTL_SGINAK_Msk (0x1U << USB_OTG_DCTL_SGINAK_Pos) /*!< 0x00000080 */
18514 #define USB_OTG_DCTL_SGINAK USB_OTG_DCTL_SGINAK_Msk /*!< Set global IN NAK */
18515 #define USB_OTG_DCTL_CGINAK_Pos (8U)
18516 #define USB_OTG_DCTL_CGINAK_Msk (0x1U << USB_OTG_DCTL_CGINAK_Pos) /*!< 0x00000100 */
18517 #define USB_OTG_DCTL_CGINAK USB_OTG_DCTL_CGINAK_Msk /*!< Clear global IN NAK */
18518 #define USB_OTG_DCTL_SGONAK_Pos (9U)
18519 #define USB_OTG_DCTL_SGONAK_Msk (0x1U << USB_OTG_DCTL_SGONAK_Pos) /*!< 0x00000200 */
18520 #define USB_OTG_DCTL_SGONAK USB_OTG_DCTL_SGONAK_Msk /*!< Set global OUT NAK */
18521 #define USB_OTG_DCTL_CGONAK_Pos (10U)
18522 #define USB_OTG_DCTL_CGONAK_Msk (0x1U << USB_OTG_DCTL_CGONAK_Pos) /*!< 0x00000400 */
18523 #define USB_OTG_DCTL_CGONAK USB_OTG_DCTL_CGONAK_Msk /*!< Clear global OUT NAK */
18524 #define USB_OTG_DCTL_POPRGDNE_Pos (11U)
18525 #define USB_OTG_DCTL_POPRGDNE_Msk (0x1U << USB_OTG_DCTL_POPRGDNE_Pos) /*!< 0x00000800 */
18526 #define USB_OTG_DCTL_POPRGDNE USB_OTG_DCTL_POPRGDNE_Msk /*!< Power-on programming done */
18527
18528 /******************** Bit definition for USB_OTG_HFIR register ********************/
18529 #define USB_OTG_HFIR_FRIVL_Pos (0U)
18530 #define USB_OTG_HFIR_FRIVL_Msk (0xFFFFU << USB_OTG_HFIR_FRIVL_Pos) /*!< 0x0000FFFF */
18531 #define USB_OTG_HFIR_FRIVL USB_OTG_HFIR_FRIVL_Msk /*!< Frame interval */
18532
18533 /******************** Bit definition for USB_OTG_HFNUM register ********************/
18534 #define USB_OTG_HFNUM_FRNUM_Pos (0U)
18535 #define USB_OTG_HFNUM_FRNUM_Msk (0xFFFFU << USB_OTG_HFNUM_FRNUM_Pos) /*!< 0x0000FFFF */
18536 #define USB_OTG_HFNUM_FRNUM USB_OTG_HFNUM_FRNUM_Msk /*!< Frame number */
18537 #define USB_OTG_HFNUM_FTREM_Pos (16U)
18538 #define USB_OTG_HFNUM_FTREM_Msk (0xFFFFU << USB_OTG_HFNUM_FTREM_Pos) /*!< 0xFFFF0000 */
18539 #define USB_OTG_HFNUM_FTREM USB_OTG_HFNUM_FTREM_Msk /*!< Frame time remaining */
18540
18541 /******************** Bit definition for USB_OTG_DSTS register ********************/
18542 #define USB_OTG_DSTS_SUSPSTS_Pos (0U)
18543 #define USB_OTG_DSTS_SUSPSTS_Msk (0x1U << USB_OTG_DSTS_SUSPSTS_Pos) /*!< 0x00000001 */
18544 #define USB_OTG_DSTS_SUSPSTS USB_OTG_DSTS_SUSPSTS_Msk /*!< Suspend status */
18545
18546 #define USB_OTG_DSTS_ENUMSPD_Pos (1U)
18547 #define USB_OTG_DSTS_ENUMSPD_Msk (0x3U << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000006 */
18548 #define USB_OTG_DSTS_ENUMSPD USB_OTG_DSTS_ENUMSPD_Msk /*!< Enumerated speed */
18549 #define USB_OTG_DSTS_ENUMSPD_0 (0x1U << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000002 */
18550 #define USB_OTG_DSTS_ENUMSPD_1 (0x2U << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000004 */
18551 #define USB_OTG_DSTS_EERR_Pos (3U)
18552 #define USB_OTG_DSTS_EERR_Msk (0x1U << USB_OTG_DSTS_EERR_Pos) /*!< 0x00000008 */
18553 #define USB_OTG_DSTS_EERR USB_OTG_DSTS_EERR_Msk /*!< Erratic error */
18554 #define USB_OTG_DSTS_FNSOF_Pos (8U)
18555 #define USB_OTG_DSTS_FNSOF_Msk (0x3FFFU << USB_OTG_DSTS_FNSOF_Pos) /*!< 0x003FFF00 */
18556 #define USB_OTG_DSTS_FNSOF USB_OTG_DSTS_FNSOF_Msk /*!< Frame number of the received SOF */
18557
18558 /******************** Bit definition for USB_OTG_GAHBCFG register ********************/
18559 #define USB_OTG_GAHBCFG_GINT_Pos (0U)
18560 #define USB_OTG_GAHBCFG_GINT_Msk (0x1U << USB_OTG_GAHBCFG_GINT_Pos) /*!< 0x00000001 */
18561 #define USB_OTG_GAHBCFG_GINT USB_OTG_GAHBCFG_GINT_Msk /*!< Global interrupt mask */
18562 #define USB_OTG_GAHBCFG_HBSTLEN_Pos (1U)
18563 #define USB_OTG_GAHBCFG_HBSTLEN_Msk (0xFU << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x0000001E */
18564 #define USB_OTG_GAHBCFG_HBSTLEN USB_OTG_GAHBCFG_HBSTLEN_Msk /*!< Burst length/type */
18565 #define USB_OTG_GAHBCFG_HBSTLEN_0 (0x0U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< Single */
18566 #define USB_OTG_GAHBCFG_HBSTLEN_1 (0x1U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR */
18567 #define USB_OTG_GAHBCFG_HBSTLEN_2 (0x3U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR4 */
18568 #define USB_OTG_GAHBCFG_HBSTLEN_3 (0x5U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR8 */
18569 #define USB_OTG_GAHBCFG_HBSTLEN_4 (0x7U << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR16 */
18570 #define USB_OTG_GAHBCFG_DMAEN_Pos (5U)
18571 #define USB_OTG_GAHBCFG_DMAEN_Msk (0x1U << USB_OTG_GAHBCFG_DMAEN_Pos) /*!< 0x00000020 */
18572 #define USB_OTG_GAHBCFG_DMAEN USB_OTG_GAHBCFG_DMAEN_Msk /*!< DMA enable */
18573 #define USB_OTG_GAHBCFG_TXFELVL_Pos (7U)
18574 #define USB_OTG_GAHBCFG_TXFELVL_Msk (0x1U << USB_OTG_GAHBCFG_TXFELVL_Pos) /*!< 0x00000080 */
18575 #define USB_OTG_GAHBCFG_TXFELVL USB_OTG_GAHBCFG_TXFELVL_Msk /*!< TxFIFO empty level */
18576 #define USB_OTG_GAHBCFG_PTXFELVL_Pos (8U)
18577 #define USB_OTG_GAHBCFG_PTXFELVL_Msk (0x1U << USB_OTG_GAHBCFG_PTXFELVL_Pos) /*!< 0x00000100 */
18578 #define USB_OTG_GAHBCFG_PTXFELVL USB_OTG_GAHBCFG_PTXFELVL_Msk /*!< Periodic TxFIFO empty level */
18579
18580 /******************** Bit definition for USB_OTG_GUSBCFG register ********************/
18581
18582 #define USB_OTG_GUSBCFG_TOCAL_Pos (0U)
18583 #define USB_OTG_GUSBCFG_TOCAL_Msk (0x7U << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000007 */
18584 #define USB_OTG_GUSBCFG_TOCAL USB_OTG_GUSBCFG_TOCAL_Msk /*!< FS timeout calibration */
18585 #define USB_OTG_GUSBCFG_TOCAL_0 (0x1U << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000001 */
18586 #define USB_OTG_GUSBCFG_TOCAL_1 (0x2U << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000002 */
18587 #define USB_OTG_GUSBCFG_TOCAL_2 (0x4U << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000004 */
18588 #define USB_OTG_GUSBCFG_PHYSEL_Pos (6U)
18589 #define USB_OTG_GUSBCFG_PHYSEL_Msk (0x1U << USB_OTG_GUSBCFG_PHYSEL_Pos) /*!< 0x00000040 */
18590 #define USB_OTG_GUSBCFG_PHYSEL USB_OTG_GUSBCFG_PHYSEL_Msk /*!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */
18591 #define USB_OTG_GUSBCFG_SRPCAP_Pos (8U)
18592 #define USB_OTG_GUSBCFG_SRPCAP_Msk (0x1U << USB_OTG_GUSBCFG_SRPCAP_Pos) /*!< 0x00000100 */
18593 #define USB_OTG_GUSBCFG_SRPCAP USB_OTG_GUSBCFG_SRPCAP_Msk /*!< SRP-capable */
18594 #define USB_OTG_GUSBCFG_HNPCAP_Pos (9U)
18595 #define USB_OTG_GUSBCFG_HNPCAP_Msk (0x1U << USB_OTG_GUSBCFG_HNPCAP_Pos) /*!< 0x00000200 */
18596 #define USB_OTG_GUSBCFG_HNPCAP USB_OTG_GUSBCFG_HNPCAP_Msk /*!< HNP-capable */
18597 #define USB_OTG_GUSBCFG_TRDT_Pos (10U)
18598 #define USB_OTG_GUSBCFG_TRDT_Msk (0xFU << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00003C00 */
18599 #define USB_OTG_GUSBCFG_TRDT USB_OTG_GUSBCFG_TRDT_Msk /*!< USB turnaround time */
18600 #define USB_OTG_GUSBCFG_TRDT_0 (0x1U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000400 */
18601 #define USB_OTG_GUSBCFG_TRDT_1 (0x2U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000800 */
18602 #define USB_OTG_GUSBCFG_TRDT_2 (0x4U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00001000 */
18603 #define USB_OTG_GUSBCFG_TRDT_3 (0x8U << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00002000 */
18604 #define USB_OTG_GUSBCFG_PHYLPCS_Pos (15U)
18605 #define USB_OTG_GUSBCFG_PHYLPCS_Msk (0x1U << USB_OTG_GUSBCFG_PHYLPCS_Pos) /*!< 0x00008000 */
18606 #define USB_OTG_GUSBCFG_PHYLPCS USB_OTG_GUSBCFG_PHYLPCS_Msk /*!< PHY Low-power clock select */
18607 #define USB_OTG_GUSBCFG_ULPIFSLS_Pos (17U)
18608 #define USB_OTG_GUSBCFG_ULPIFSLS_Msk (0x1U << USB_OTG_GUSBCFG_ULPIFSLS_Pos) /*!< 0x00020000 */
18609 #define USB_OTG_GUSBCFG_ULPIFSLS USB_OTG_GUSBCFG_ULPIFSLS_Msk /*!< ULPI FS/LS select */
18610 #define USB_OTG_GUSBCFG_ULPIAR_Pos (18U)
18611 #define USB_OTG_GUSBCFG_ULPIAR_Msk (0x1U << USB_OTG_GUSBCFG_ULPIAR_Pos) /*!< 0x00040000 */
18612 #define USB_OTG_GUSBCFG_ULPIAR USB_OTG_GUSBCFG_ULPIAR_Msk /*!< ULPI Auto-resume */
18613 #define USB_OTG_GUSBCFG_ULPICSM_Pos (19U)
18614 #define USB_OTG_GUSBCFG_ULPICSM_Msk (0x1U << USB_OTG_GUSBCFG_ULPICSM_Pos) /*!< 0x00080000 */
18615 #define USB_OTG_GUSBCFG_ULPICSM USB_OTG_GUSBCFG_ULPICSM_Msk /*!< ULPI Clock SuspendM */
18616 #define USB_OTG_GUSBCFG_ULPIEVBUSD_Pos (20U)
18617 #define USB_OTG_GUSBCFG_ULPIEVBUSD_Msk (0x1U << USB_OTG_GUSBCFG_ULPIEVBUSD_Pos) /*!< 0x00100000 */
18618 #define USB_OTG_GUSBCFG_ULPIEVBUSD USB_OTG_GUSBCFG_ULPIEVBUSD_Msk /*!< ULPI External VBUS Drive */
18619 #define USB_OTG_GUSBCFG_ULPIEVBUSI_Pos (21U)
18620 #define USB_OTG_GUSBCFG_ULPIEVBUSI_Msk (0x1U << USB_OTG_GUSBCFG_ULPIEVBUSI_Pos) /*!< 0x00200000 */
18621 #define USB_OTG_GUSBCFG_ULPIEVBUSI USB_OTG_GUSBCFG_ULPIEVBUSI_Msk /*!< ULPI external VBUS indicator */
18622 #define USB_OTG_GUSBCFG_TSDPS_Pos (22U)
18623 #define USB_OTG_GUSBCFG_TSDPS_Msk (0x1U << USB_OTG_GUSBCFG_TSDPS_Pos) /*!< 0x00400000 */
18624 #define USB_OTG_GUSBCFG_TSDPS USB_OTG_GUSBCFG_TSDPS_Msk /*!< TermSel DLine pulsing selection */
18625 #define USB_OTG_GUSBCFG_PCCI_Pos (23U)
18626 #define USB_OTG_GUSBCFG_PCCI_Msk (0x1U << USB_OTG_GUSBCFG_PCCI_Pos) /*!< 0x00800000 */
18627 #define USB_OTG_GUSBCFG_PCCI USB_OTG_GUSBCFG_PCCI_Msk /*!< Indicator complement */
18628 #define USB_OTG_GUSBCFG_PTCI_Pos (24U)
18629 #define USB_OTG_GUSBCFG_PTCI_Msk (0x1U << USB_OTG_GUSBCFG_PTCI_Pos) /*!< 0x01000000 */
18630 #define USB_OTG_GUSBCFG_PTCI USB_OTG_GUSBCFG_PTCI_Msk /*!< Indicator pass through */
18631 #define USB_OTG_GUSBCFG_ULPIIPD_Pos (25U)
18632 #define USB_OTG_GUSBCFG_ULPIIPD_Msk (0x1U << USB_OTG_GUSBCFG_ULPIIPD_Pos) /*!< 0x02000000 */
18633 #define USB_OTG_GUSBCFG_ULPIIPD USB_OTG_GUSBCFG_ULPIIPD_Msk /*!< ULPI interface protect disable */
18634 #define USB_OTG_GUSBCFG_FHMOD_Pos (29U)
18635 #define USB_OTG_GUSBCFG_FHMOD_Msk (0x1U << USB_OTG_GUSBCFG_FHMOD_Pos) /*!< 0x20000000 */
18636 #define USB_OTG_GUSBCFG_FHMOD USB_OTG_GUSBCFG_FHMOD_Msk /*!< Forced host mode */
18637 #define USB_OTG_GUSBCFG_FDMOD_Pos (30U)
18638 #define USB_OTG_GUSBCFG_FDMOD_Msk (0x1U << USB_OTG_GUSBCFG_FDMOD_Pos) /*!< 0x40000000 */
18639 #define USB_OTG_GUSBCFG_FDMOD USB_OTG_GUSBCFG_FDMOD_Msk /*!< Forced peripheral mode */
18640 #define USB_OTG_GUSBCFG_CTXPKT_Pos (31U)
18641 #define USB_OTG_GUSBCFG_CTXPKT_Msk (0x1U << USB_OTG_GUSBCFG_CTXPKT_Pos) /*!< 0x80000000 */
18642 #define USB_OTG_GUSBCFG_CTXPKT USB_OTG_GUSBCFG_CTXPKT_Msk /*!< Corrupt Tx packet */
18643
18644 /******************** Bit definition for USB_OTG_GRSTCTL register ********************/
18645 #define USB_OTG_GRSTCTL_CSRST_Pos (0U)
18646 #define USB_OTG_GRSTCTL_CSRST_Msk (0x1U << USB_OTG_GRSTCTL_CSRST_Pos) /*!< 0x00000001 */
18647 #define USB_OTG_GRSTCTL_CSRST USB_OTG_GRSTCTL_CSRST_Msk /*!< Core soft reset */
18648 #define USB_OTG_GRSTCTL_HSRST_Pos (1U)
18649 #define USB_OTG_GRSTCTL_HSRST_Msk (0x1U << USB_OTG_GRSTCTL_HSRST_Pos) /*!< 0x00000002 */
18650 #define USB_OTG_GRSTCTL_HSRST USB_OTG_GRSTCTL_HSRST_Msk /*!< HCLK soft reset */
18651 #define USB_OTG_GRSTCTL_FCRST_Pos (2U)
18652 #define USB_OTG_GRSTCTL_FCRST_Msk (0x1U << USB_OTG_GRSTCTL_FCRST_Pos) /*!< 0x00000004 */
18653 #define USB_OTG_GRSTCTL_FCRST USB_OTG_GRSTCTL_FCRST_Msk /*!< Host frame counter reset */
18654 #define USB_OTG_GRSTCTL_RXFFLSH_Pos (4U)
18655 #define USB_OTG_GRSTCTL_RXFFLSH_Msk (0x1U << USB_OTG_GRSTCTL_RXFFLSH_Pos) /*!< 0x00000010 */
18656 #define USB_OTG_GRSTCTL_RXFFLSH USB_OTG_GRSTCTL_RXFFLSH_Msk /*!< RxFIFO flush */
18657 #define USB_OTG_GRSTCTL_TXFFLSH_Pos (5U)
18658 #define USB_OTG_GRSTCTL_TXFFLSH_Msk (0x1U << USB_OTG_GRSTCTL_TXFFLSH_Pos) /*!< 0x00000020 */
18659 #define USB_OTG_GRSTCTL_TXFFLSH USB_OTG_GRSTCTL_TXFFLSH_Msk /*!< TxFIFO flush */
18660
18661
18662 #define USB_OTG_GRSTCTL_TXFNUM_Pos (6U)
18663 #define USB_OTG_GRSTCTL_TXFNUM_Msk (0x1FU << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x000007C0 */
18664 #define USB_OTG_GRSTCTL_TXFNUM USB_OTG_GRSTCTL_TXFNUM_Msk /*!< TxFIFO number */
18665 #define USB_OTG_GRSTCTL_TXFNUM_0 (0x01U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000040 */
18666 #define USB_OTG_GRSTCTL_TXFNUM_1 (0x02U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000080 */
18667 #define USB_OTG_GRSTCTL_TXFNUM_2 (0x04U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000100 */
18668 #define USB_OTG_GRSTCTL_TXFNUM_3 (0x08U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000200 */
18669 #define USB_OTG_GRSTCTL_TXFNUM_4 (0x10U << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000400 */
18670 #define USB_OTG_GRSTCTL_DMAREQ_Pos (30U)
18671 #define USB_OTG_GRSTCTL_DMAREQ_Msk (0x1U << USB_OTG_GRSTCTL_DMAREQ_Pos) /*!< 0x40000000 */
18672 #define USB_OTG_GRSTCTL_DMAREQ USB_OTG_GRSTCTL_DMAREQ_Msk /*!< DMA request signal */
18673 #define USB_OTG_GRSTCTL_AHBIDL_Pos (31U)
18674 #define USB_OTG_GRSTCTL_AHBIDL_Msk (0x1U << USB_OTG_GRSTCTL_AHBIDL_Pos) /*!< 0x80000000 */
18675 #define USB_OTG_GRSTCTL_AHBIDL USB_OTG_GRSTCTL_AHBIDL_Msk /*!< AHB master idle */
18676
18677 /******************** Bit definition for USB_OTG_DIEPMSK register ********************/
18678 #define USB_OTG_DIEPMSK_XFRCM_Pos (0U)
18679 #define USB_OTG_DIEPMSK_XFRCM_Msk (0x1U << USB_OTG_DIEPMSK_XFRCM_Pos) /*!< 0x00000001 */
18680 #define USB_OTG_DIEPMSK_XFRCM USB_OTG_DIEPMSK_XFRCM_Msk /*!< Transfer completed interrupt mask */
18681 #define USB_OTG_DIEPMSK_EPDM_Pos (1U)
18682 #define USB_OTG_DIEPMSK_EPDM_Msk (0x1U << USB_OTG_DIEPMSK_EPDM_Pos) /*!< 0x00000002 */
18683 #define USB_OTG_DIEPMSK_EPDM USB_OTG_DIEPMSK_EPDM_Msk /*!< Endpoint disabled interrupt mask */
18684 #define USB_OTG_DIEPMSK_TOM_Pos (3U)
18685 #define USB_OTG_DIEPMSK_TOM_Msk (0x1U << USB_OTG_DIEPMSK_TOM_Pos) /*!< 0x00000008 */
18686 #define USB_OTG_DIEPMSK_TOM USB_OTG_DIEPMSK_TOM_Msk /*!< Timeout condition mask (nonisochronous endpoints) */
18687 #define USB_OTG_DIEPMSK_ITTXFEMSK_Pos (4U)
18688 #define USB_OTG_DIEPMSK_ITTXFEMSK_Msk (0x1U << USB_OTG_DIEPMSK_ITTXFEMSK_Pos) /*!< 0x00000010 */
18689 #define USB_OTG_DIEPMSK_ITTXFEMSK USB_OTG_DIEPMSK_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */
18690 #define USB_OTG_DIEPMSK_INEPNMM_Pos (5U)
18691 #define USB_OTG_DIEPMSK_INEPNMM_Msk (0x1U << USB_OTG_DIEPMSK_INEPNMM_Pos) /*!< 0x00000020 */
18692 #define USB_OTG_DIEPMSK_INEPNMM USB_OTG_DIEPMSK_INEPNMM_Msk /*!< IN token received with EP mismatch mask */
18693 #define USB_OTG_DIEPMSK_INEPNEM_Pos (6U)
18694 #define USB_OTG_DIEPMSK_INEPNEM_Msk (0x1U << USB_OTG_DIEPMSK_INEPNEM_Pos) /*!< 0x00000040 */
18695 #define USB_OTG_DIEPMSK_INEPNEM USB_OTG_DIEPMSK_INEPNEM_Msk /*!< IN endpoint NAK effective mask */
18696 #define USB_OTG_DIEPMSK_TXFURM_Pos (8U)
18697 #define USB_OTG_DIEPMSK_TXFURM_Msk (0x1U << USB_OTG_DIEPMSK_TXFURM_Pos) /*!< 0x00000100 */
18698 #define USB_OTG_DIEPMSK_TXFURM USB_OTG_DIEPMSK_TXFURM_Msk /*!< FIFO underrun mask */
18699 #define USB_OTG_DIEPMSK_BIM_Pos (9U)
18700 #define USB_OTG_DIEPMSK_BIM_Msk (0x1U << USB_OTG_DIEPMSK_BIM_Pos) /*!< 0x00000200 */
18701 #define USB_OTG_DIEPMSK_BIM USB_OTG_DIEPMSK_BIM_Msk /*!< BNA interrupt mask */
18702
18703 /******************** Bit definition for USB_OTG_HPTXSTS register ********************/
18704 #define USB_OTG_HPTXSTS_PTXFSAVL_Pos (0U)
18705 #define USB_OTG_HPTXSTS_PTXFSAVL_Msk (0xFFFFU << USB_OTG_HPTXSTS_PTXFSAVL_Pos) /*!< 0x0000FFFF */
18706 #define USB_OTG_HPTXSTS_PTXFSAVL USB_OTG_HPTXSTS_PTXFSAVL_Msk /*!< Periodic transmit data FIFO space available */
18707 #define USB_OTG_HPTXSTS_PTXQSAV_Pos (16U)
18708 #define USB_OTG_HPTXSTS_PTXQSAV_Msk (0xFFU << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00FF0000 */
18709 #define USB_OTG_HPTXSTS_PTXQSAV USB_OTG_HPTXSTS_PTXQSAV_Msk /*!< Periodic transmit request queue space available */
18710 #define USB_OTG_HPTXSTS_PTXQSAV_0 (0x01U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00010000 */
18711 #define USB_OTG_HPTXSTS_PTXQSAV_1 (0x02U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00020000 */
18712 #define USB_OTG_HPTXSTS_PTXQSAV_2 (0x04U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00040000 */
18713 #define USB_OTG_HPTXSTS_PTXQSAV_3 (0x08U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00080000 */
18714 #define USB_OTG_HPTXSTS_PTXQSAV_4 (0x10U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00100000 */
18715 #define USB_OTG_HPTXSTS_PTXQSAV_5 (0x20U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00200000 */
18716 #define USB_OTG_HPTXSTS_PTXQSAV_6 (0x40U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00400000 */
18717 #define USB_OTG_HPTXSTS_PTXQSAV_7 (0x80U << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00800000 */
18718
18719 #define USB_OTG_HPTXSTS_PTXQTOP_Pos (24U)
18720 #define USB_OTG_HPTXSTS_PTXQTOP_Msk (0xFFU << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0xFF000000 */
18721 #define USB_OTG_HPTXSTS_PTXQTOP USB_OTG_HPTXSTS_PTXQTOP_Msk /*!< Top of the periodic transmit request queue */
18722 #define USB_OTG_HPTXSTS_PTXQTOP_0 (0x01U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x01000000 */
18723 #define USB_OTG_HPTXSTS_PTXQTOP_1 (0x02U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x02000000 */
18724 #define USB_OTG_HPTXSTS_PTXQTOP_2 (0x04U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x04000000 */
18725 #define USB_OTG_HPTXSTS_PTXQTOP_3 (0x08U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x08000000 */
18726 #define USB_OTG_HPTXSTS_PTXQTOP_4 (0x10U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x10000000 */
18727 #define USB_OTG_HPTXSTS_PTXQTOP_5 (0x20U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x20000000 */
18728 #define USB_OTG_HPTXSTS_PTXQTOP_6 (0x40U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x40000000 */
18729 #define USB_OTG_HPTXSTS_PTXQTOP_7 (0x80U << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x80000000 */
18730
18731 /******************** Bit definition for USB_OTG_HAINT register ********************/
18732 #define USB_OTG_HAINT_HAINT_Pos (0U)
18733 #define USB_OTG_HAINT_HAINT_Msk (0xFFFFU << USB_OTG_HAINT_HAINT_Pos) /*!< 0x0000FFFF */
18734 #define USB_OTG_HAINT_HAINT USB_OTG_HAINT_HAINT_Msk /*!< Channel interrupts */
18735
18736 /******************** Bit definition for USB_OTG_DOEPMSK register ********************/
18737 #define USB_OTG_DOEPMSK_XFRCM_Pos (0U)
18738 #define USB_OTG_DOEPMSK_XFRCM_Msk (0x1U << USB_OTG_DOEPMSK_XFRCM_Pos) /*!< 0x00000001 */
18739 #define USB_OTG_DOEPMSK_XFRCM USB_OTG_DOEPMSK_XFRCM_Msk /*!< Transfer completed interrupt mask */
18740 #define USB_OTG_DOEPMSK_EPDM_Pos (1U)
18741 #define USB_OTG_DOEPMSK_EPDM_Msk (0x1U << USB_OTG_DOEPMSK_EPDM_Pos) /*!< 0x00000002 */
18742 #define USB_OTG_DOEPMSK_EPDM USB_OTG_DOEPMSK_EPDM_Msk /*!< Endpoint disabled interrupt mask */
18743 #define USB_OTG_DOEPMSK_STUPM_Pos (3U)
18744 #define USB_OTG_DOEPMSK_STUPM_Msk (0x1U << USB_OTG_DOEPMSK_STUPM_Pos) /*!< 0x00000008 */
18745 #define USB_OTG_DOEPMSK_STUPM USB_OTG_DOEPMSK_STUPM_Msk /*!< SETUP phase done mask */
18746 #define USB_OTG_DOEPMSK_OTEPDM_Pos (4U)
18747 #define USB_OTG_DOEPMSK_OTEPDM_Msk (0x1U << USB_OTG_DOEPMSK_OTEPDM_Pos) /*!< 0x00000010 */
18748 #define USB_OTG_DOEPMSK_OTEPDM USB_OTG_DOEPMSK_OTEPDM_Msk /*!< OUT token received when endpoint disabled mask */
18749 #define USB_OTG_DOEPMSK_OTEPSPRM_Pos (5U)
18750 #define USB_OTG_DOEPMSK_OTEPSPRM_Msk (0x1U << USB_OTG_DOEPMSK_OTEPSPRM_Pos) /*!< 0x00000020 */
18751 #define USB_OTG_DOEPMSK_OTEPSPRM USB_OTG_DOEPMSK_OTEPSPRM_Msk /*!< Status Phase Received mask */
18752 #define USB_OTG_DOEPMSK_B2BSTUP_Pos (6U)
18753 #define USB_OTG_DOEPMSK_B2BSTUP_Msk (0x1U << USB_OTG_DOEPMSK_B2BSTUP_Pos) /*!< 0x00000040 */
18754 #define USB_OTG_DOEPMSK_B2BSTUP USB_OTG_DOEPMSK_B2BSTUP_Msk /*!< Back-to-back SETUP packets received mask */
18755 #define USB_OTG_DOEPMSK_OPEM_Pos (8U)
18756 #define USB_OTG_DOEPMSK_OPEM_Msk (0x1U << USB_OTG_DOEPMSK_OPEM_Pos) /*!< 0x00000100 */
18757 #define USB_OTG_DOEPMSK_OPEM USB_OTG_DOEPMSK_OPEM_Msk /*!< OUT packet error mask */
18758 #define USB_OTG_DOEPMSK_BOIM_Pos (9U)
18759 #define USB_OTG_DOEPMSK_BOIM_Msk (0x1U << USB_OTG_DOEPMSK_BOIM_Pos) /*!< 0x00000200 */
18760 #define USB_OTG_DOEPMSK_BOIM USB_OTG_DOEPMSK_BOIM_Msk /*!< BNA interrupt mask */
18761
18762 /******************** Bit definition for USB_OTG_GINTSTS register ********************/
18763 #define USB_OTG_GINTSTS_CMOD_Pos (0U)
18764 #define USB_OTG_GINTSTS_CMOD_Msk (0x1U << USB_OTG_GINTSTS_CMOD_Pos) /*!< 0x00000001 */
18765 #define USB_OTG_GINTSTS_CMOD USB_OTG_GINTSTS_CMOD_Msk /*!< Current mode of operation */
18766 #define USB_OTG_GINTSTS_MMIS_Pos (1U)
18767 #define USB_OTG_GINTSTS_MMIS_Msk (0x1U << USB_OTG_GINTSTS_MMIS_Pos) /*!< 0x00000002 */
18768 #define USB_OTG_GINTSTS_MMIS USB_OTG_GINTSTS_MMIS_Msk /*!< Mode mismatch interrupt */
18769 #define USB_OTG_GINTSTS_OTGINT_Pos (2U)
18770 #define USB_OTG_GINTSTS_OTGINT_Msk (0x1U << USB_OTG_GINTSTS_OTGINT_Pos) /*!< 0x00000004 */
18771 #define USB_OTG_GINTSTS_OTGINT USB_OTG_GINTSTS_OTGINT_Msk /*!< OTG interrupt */
18772 #define USB_OTG_GINTSTS_SOF_Pos (3U)
18773 #define USB_OTG_GINTSTS_SOF_Msk (0x1U << USB_OTG_GINTSTS_SOF_Pos) /*!< 0x00000008 */
18774 #define USB_OTG_GINTSTS_SOF USB_OTG_GINTSTS_SOF_Msk /*!< Start of frame */
18775 #define USB_OTG_GINTSTS_RXFLVL_Pos (4U)
18776 #define USB_OTG_GINTSTS_RXFLVL_Msk (0x1U << USB_OTG_GINTSTS_RXFLVL_Pos) /*!< 0x00000010 */
18777 #define USB_OTG_GINTSTS_RXFLVL USB_OTG_GINTSTS_RXFLVL_Msk /*!< RxFIFO nonempty */
18778 #define USB_OTG_GINTSTS_NPTXFE_Pos (5U)
18779 #define USB_OTG_GINTSTS_NPTXFE_Msk (0x1U << USB_OTG_GINTSTS_NPTXFE_Pos) /*!< 0x00000020 */
18780 #define USB_OTG_GINTSTS_NPTXFE USB_OTG_GINTSTS_NPTXFE_Msk /*!< Nonperiodic TxFIFO empty */
18781 #define USB_OTG_GINTSTS_GINAKEFF_Pos (6U)
18782 #define USB_OTG_GINTSTS_GINAKEFF_Msk (0x1U << USB_OTG_GINTSTS_GINAKEFF_Pos) /*!< 0x00000040 */
18783 #define USB_OTG_GINTSTS_GINAKEFF USB_OTG_GINTSTS_GINAKEFF_Msk /*!< Global IN nonperiodic NAK effective */
18784 #define USB_OTG_GINTSTS_BOUTNAKEFF_Pos (7U)
18785 #define USB_OTG_GINTSTS_BOUTNAKEFF_Msk (0x1U << USB_OTG_GINTSTS_BOUTNAKEFF_Pos) /*!< 0x00000080 */
18786 #define USB_OTG_GINTSTS_BOUTNAKEFF USB_OTG_GINTSTS_BOUTNAKEFF_Msk /*!< Global OUT NAK effective */
18787 #define USB_OTG_GINTSTS_ESUSP_Pos (10U)
18788 #define USB_OTG_GINTSTS_ESUSP_Msk (0x1U << USB_OTG_GINTSTS_ESUSP_Pos) /*!< 0x00000400 */
18789 #define USB_OTG_GINTSTS_ESUSP USB_OTG_GINTSTS_ESUSP_Msk /*!< Early suspend */
18790 #define USB_OTG_GINTSTS_USBSUSP_Pos (11U)
18791 #define USB_OTG_GINTSTS_USBSUSP_Msk (0x1U << USB_OTG_GINTSTS_USBSUSP_Pos) /*!< 0x00000800 */
18792 #define USB_OTG_GINTSTS_USBSUSP USB_OTG_GINTSTS_USBSUSP_Msk /*!< USB suspend */
18793 #define USB_OTG_GINTSTS_USBRST_Pos (12U)
18794 #define USB_OTG_GINTSTS_USBRST_Msk (0x1U << USB_OTG_GINTSTS_USBRST_Pos) /*!< 0x00001000 */
18795 #define USB_OTG_GINTSTS_USBRST USB_OTG_GINTSTS_USBRST_Msk /*!< USB reset */
18796 #define USB_OTG_GINTSTS_ENUMDNE_Pos (13U)
18797 #define USB_OTG_GINTSTS_ENUMDNE_Msk (0x1U << USB_OTG_GINTSTS_ENUMDNE_Pos) /*!< 0x00002000 */
18798 #define USB_OTG_GINTSTS_ENUMDNE USB_OTG_GINTSTS_ENUMDNE_Msk /*!< Enumeration done */
18799 #define USB_OTG_GINTSTS_ISOODRP_Pos (14U)
18800 #define USB_OTG_GINTSTS_ISOODRP_Msk (0x1U << USB_OTG_GINTSTS_ISOODRP_Pos) /*!< 0x00004000 */
18801 #define USB_OTG_GINTSTS_ISOODRP USB_OTG_GINTSTS_ISOODRP_Msk /*!< Isochronous OUT packet dropped interrupt */
18802 #define USB_OTG_GINTSTS_EOPF_Pos (15U)
18803 #define USB_OTG_GINTSTS_EOPF_Msk (0x1U << USB_OTG_GINTSTS_EOPF_Pos) /*!< 0x00008000 */
18804 #define USB_OTG_GINTSTS_EOPF USB_OTG_GINTSTS_EOPF_Msk /*!< End of periodic frame interrupt */
18805 #define USB_OTG_GINTSTS_IEPINT_Pos (18U)
18806 #define USB_OTG_GINTSTS_IEPINT_Msk (0x1U << USB_OTG_GINTSTS_IEPINT_Pos) /*!< 0x00040000 */
18807 #define USB_OTG_GINTSTS_IEPINT USB_OTG_GINTSTS_IEPINT_Msk /*!< IN endpoint interrupt */
18808 #define USB_OTG_GINTSTS_OEPINT_Pos (19U)
18809 #define USB_OTG_GINTSTS_OEPINT_Msk (0x1U << USB_OTG_GINTSTS_OEPINT_Pos) /*!< 0x00080000 */
18810 #define USB_OTG_GINTSTS_OEPINT USB_OTG_GINTSTS_OEPINT_Msk /*!< OUT endpoint interrupt */
18811 #define USB_OTG_GINTSTS_IISOIXFR_Pos (20U)
18812 #define USB_OTG_GINTSTS_IISOIXFR_Msk (0x1U << USB_OTG_GINTSTS_IISOIXFR_Pos) /*!< 0x00100000 */
18813 #define USB_OTG_GINTSTS_IISOIXFR USB_OTG_GINTSTS_IISOIXFR_Msk /*!< Incomplete isochronous IN transfer */
18814 #define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos (21U)
18815 #define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk (0x1U << USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos) /*!< 0x00200000 */
18816 #define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk /*!< Incomplete periodic transfer */
18817 #define USB_OTG_GINTSTS_DATAFSUSP_Pos (22U)
18818 #define USB_OTG_GINTSTS_DATAFSUSP_Msk (0x1U << USB_OTG_GINTSTS_DATAFSUSP_Pos) /*!< 0x00400000 */
18819 #define USB_OTG_GINTSTS_DATAFSUSP USB_OTG_GINTSTS_DATAFSUSP_Msk /*!< Data fetch suspended */
18820 #define USB_OTG_GINTSTS_RSTDET_Pos (23U)
18821 #define USB_OTG_GINTSTS_RSTDET_Msk (0x1U << USB_OTG_GINTSTS_RSTDET_Pos) /*!< 0x00800000 */
18822 #define USB_OTG_GINTSTS_RSTDET USB_OTG_GINTSTS_RSTDET_Msk /*!< Reset detected interrupt */
18823 #define USB_OTG_GINTSTS_HPRTINT_Pos (24U)
18824 #define USB_OTG_GINTSTS_HPRTINT_Msk (0x1U << USB_OTG_GINTSTS_HPRTINT_Pos) /*!< 0x01000000 */
18825 #define USB_OTG_GINTSTS_HPRTINT USB_OTG_GINTSTS_HPRTINT_Msk /*!< Host port interrupt */
18826 #define USB_OTG_GINTSTS_HCINT_Pos (25U)
18827 #define USB_OTG_GINTSTS_HCINT_Msk (0x1U << USB_OTG_GINTSTS_HCINT_Pos) /*!< 0x02000000 */
18828 #define USB_OTG_GINTSTS_HCINT USB_OTG_GINTSTS_HCINT_Msk /*!< Host channels interrupt */
18829 #define USB_OTG_GINTSTS_PTXFE_Pos (26U)
18830 #define USB_OTG_GINTSTS_PTXFE_Msk (0x1U << USB_OTG_GINTSTS_PTXFE_Pos) /*!< 0x04000000 */
18831 #define USB_OTG_GINTSTS_PTXFE USB_OTG_GINTSTS_PTXFE_Msk /*!< Periodic TxFIFO empty */
18832 #define USB_OTG_GINTSTS_LPMINT_Pos (27U)
18833 #define USB_OTG_GINTSTS_LPMINT_Msk (0x1U << USB_OTG_GINTSTS_LPMINT_Pos) /*!< 0x08000000 */
18834 #define USB_OTG_GINTSTS_LPMINT USB_OTG_GINTSTS_LPMINT_Msk /*!< LPM interrupt */
18835 #define USB_OTG_GINTSTS_CIDSCHG_Pos (28U)
18836 #define USB_OTG_GINTSTS_CIDSCHG_Msk (0x1U << USB_OTG_GINTSTS_CIDSCHG_Pos) /*!< 0x10000000 */
18837 #define USB_OTG_GINTSTS_CIDSCHG USB_OTG_GINTSTS_CIDSCHG_Msk /*!< Connector ID status change */
18838 #define USB_OTG_GINTSTS_DISCINT_Pos (29U)
18839 #define USB_OTG_GINTSTS_DISCINT_Msk (0x1U << USB_OTG_GINTSTS_DISCINT_Pos) /*!< 0x20000000 */
18840 #define USB_OTG_GINTSTS_DISCINT USB_OTG_GINTSTS_DISCINT_Msk /*!< Disconnect detected interrupt */
18841 #define USB_OTG_GINTSTS_SRQINT_Pos (30U)
18842 #define USB_OTG_GINTSTS_SRQINT_Msk (0x1U << USB_OTG_GINTSTS_SRQINT_Pos) /*!< 0x40000000 */
18843 #define USB_OTG_GINTSTS_SRQINT USB_OTG_GINTSTS_SRQINT_Msk /*!< Session request/new session detected interrupt */
18844 #define USB_OTG_GINTSTS_WKUINT_Pos (31U)
18845 #define USB_OTG_GINTSTS_WKUINT_Msk (0x1U << USB_OTG_GINTSTS_WKUINT_Pos) /*!< 0x80000000 */
18846 #define USB_OTG_GINTSTS_WKUINT USB_OTG_GINTSTS_WKUINT_Msk /*!< Resume/remote wakeup detected interrupt */
18847
18848 /******************** Bit definition for USB_OTG_GINTMSK register ********************/
18849 #define USB_OTG_GINTMSK_MMISM_Pos (1U)
18850 #define USB_OTG_GINTMSK_MMISM_Msk (0x1U << USB_OTG_GINTMSK_MMISM_Pos) /*!< 0x00000002 */
18851 #define USB_OTG_GINTMSK_MMISM USB_OTG_GINTMSK_MMISM_Msk /*!< Mode mismatch interrupt mask */
18852 #define USB_OTG_GINTMSK_OTGINT_Pos (2U)
18853 #define USB_OTG_GINTMSK_OTGINT_Msk (0x1U << USB_OTG_GINTMSK_OTGINT_Pos) /*!< 0x00000004 */
18854 #define USB_OTG_GINTMSK_OTGINT USB_OTG_GINTMSK_OTGINT_Msk /*!< OTG interrupt mask */
18855 #define USB_OTG_GINTMSK_SOFM_Pos (3U)
18856 #define USB_OTG_GINTMSK_SOFM_Msk (0x1U << USB_OTG_GINTMSK_SOFM_Pos) /*!< 0x00000008 */
18857 #define USB_OTG_GINTMSK_SOFM USB_OTG_GINTMSK_SOFM_Msk /*!< Start of frame mask */
18858 #define USB_OTG_GINTMSK_RXFLVLM_Pos (4U)
18859 #define USB_OTG_GINTMSK_RXFLVLM_Msk (0x1U << USB_OTG_GINTMSK_RXFLVLM_Pos) /*!< 0x00000010 */
18860 #define USB_OTG_GINTMSK_RXFLVLM USB_OTG_GINTMSK_RXFLVLM_Msk /*!< Receive FIFO nonempty mask */
18861 #define USB_OTG_GINTMSK_NPTXFEM_Pos (5U)
18862 #define USB_OTG_GINTMSK_NPTXFEM_Msk (0x1U << USB_OTG_GINTMSK_NPTXFEM_Pos) /*!< 0x00000020 */
18863 #define USB_OTG_GINTMSK_NPTXFEM USB_OTG_GINTMSK_NPTXFEM_Msk /*!< Nonperiodic TxFIFO empty mask */
18864 #define USB_OTG_GINTMSK_GINAKEFFM_Pos (6U)
18865 #define USB_OTG_GINTMSK_GINAKEFFM_Msk (0x1U << USB_OTG_GINTMSK_GINAKEFFM_Pos) /*!< 0x00000040 */
18866 #define USB_OTG_GINTMSK_GINAKEFFM USB_OTG_GINTMSK_GINAKEFFM_Msk /*!< Global nonperiodic IN NAK effective mask */
18867 #define USB_OTG_GINTMSK_GONAKEFFM_Pos (7U)
18868 #define USB_OTG_GINTMSK_GONAKEFFM_Msk (0x1U << USB_OTG_GINTMSK_GONAKEFFM_Pos) /*!< 0x00000080 */
18869 #define USB_OTG_GINTMSK_GONAKEFFM USB_OTG_GINTMSK_GONAKEFFM_Msk /*!< Global OUT NAK effective mask */
18870 #define USB_OTG_GINTMSK_ESUSPM_Pos (10U)
18871 #define USB_OTG_GINTMSK_ESUSPM_Msk (0x1U << USB_OTG_GINTMSK_ESUSPM_Pos) /*!< 0x00000400 */
18872 #define USB_OTG_GINTMSK_ESUSPM USB_OTG_GINTMSK_ESUSPM_Msk /*!< Early suspend mask */
18873 #define USB_OTG_GINTMSK_USBSUSPM_Pos (11U)
18874 #define USB_OTG_GINTMSK_USBSUSPM_Msk (0x1U << USB_OTG_GINTMSK_USBSUSPM_Pos) /*!< 0x00000800 */
18875 #define USB_OTG_GINTMSK_USBSUSPM USB_OTG_GINTMSK_USBSUSPM_Msk /*!< USB suspend mask */
18876 #define USB_OTG_GINTMSK_USBRST_Pos (12U)
18877 #define USB_OTG_GINTMSK_USBRST_Msk (0x1U << USB_OTG_GINTMSK_USBRST_Pos) /*!< 0x00001000 */
18878 #define USB_OTG_GINTMSK_USBRST USB_OTG_GINTMSK_USBRST_Msk /*!< USB reset mask */
18879 #define USB_OTG_GINTMSK_ENUMDNEM_Pos (13U)
18880 #define USB_OTG_GINTMSK_ENUMDNEM_Msk (0x1U << USB_OTG_GINTMSK_ENUMDNEM_Pos) /*!< 0x00002000 */
18881 #define USB_OTG_GINTMSK_ENUMDNEM USB_OTG_GINTMSK_ENUMDNEM_Msk /*!< Enumeration done mask */
18882 #define USB_OTG_GINTMSK_ISOODRPM_Pos (14U)
18883 #define USB_OTG_GINTMSK_ISOODRPM_Msk (0x1U << USB_OTG_GINTMSK_ISOODRPM_Pos) /*!< 0x00004000 */
18884 #define USB_OTG_GINTMSK_ISOODRPM USB_OTG_GINTMSK_ISOODRPM_Msk /*!< Isochronous OUT packet dropped interrupt mask */
18885 #define USB_OTG_GINTMSK_EOPFM_Pos (15U)
18886 #define USB_OTG_GINTMSK_EOPFM_Msk (0x1U << USB_OTG_GINTMSK_EOPFM_Pos) /*!< 0x00008000 */
18887 #define USB_OTG_GINTMSK_EOPFM USB_OTG_GINTMSK_EOPFM_Msk /*!< End of periodic frame interrupt mask */
18888 #define USB_OTG_GINTMSK_EPMISM_Pos (17U)
18889 #define USB_OTG_GINTMSK_EPMISM_Msk (0x1U << USB_OTG_GINTMSK_EPMISM_Pos) /*!< 0x00020000 */
18890 #define USB_OTG_GINTMSK_EPMISM USB_OTG_GINTMSK_EPMISM_Msk /*!< Endpoint mismatch interrupt mask */
18891 #define USB_OTG_GINTMSK_IEPINT_Pos (18U)
18892 #define USB_OTG_GINTMSK_IEPINT_Msk (0x1U << USB_OTG_GINTMSK_IEPINT_Pos) /*!< 0x00040000 */
18893 #define USB_OTG_GINTMSK_IEPINT USB_OTG_GINTMSK_IEPINT_Msk /*!< IN endpoints interrupt mask */
18894 #define USB_OTG_GINTMSK_OEPINT_Pos (19U)
18895 #define USB_OTG_GINTMSK_OEPINT_Msk (0x1U << USB_OTG_GINTMSK_OEPINT_Pos) /*!< 0x00080000 */
18896 #define USB_OTG_GINTMSK_OEPINT USB_OTG_GINTMSK_OEPINT_Msk /*!< OUT endpoints interrupt mask */
18897 #define USB_OTG_GINTMSK_IISOIXFRM_Pos (20U)
18898 #define USB_OTG_GINTMSK_IISOIXFRM_Msk (0x1U << USB_OTG_GINTMSK_IISOIXFRM_Pos) /*!< 0x00100000 */
18899 #define USB_OTG_GINTMSK_IISOIXFRM USB_OTG_GINTMSK_IISOIXFRM_Msk /*!< Incomplete isochronous IN transfer mask */
18900 #define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos (21U)
18901 #define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk (0x1U << USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos) /*!< 0x00200000 */
18902 #define USB_OTG_GINTMSK_PXFRM_IISOOXFRM USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk /*!< Incomplete periodic transfer mask */
18903 #define USB_OTG_GINTMSK_FSUSPM_Pos (22U)
18904 #define USB_OTG_GINTMSK_FSUSPM_Msk (0x1U << USB_OTG_GINTMSK_FSUSPM_Pos) /*!< 0x00400000 */
18905 #define USB_OTG_GINTMSK_FSUSPM USB_OTG_GINTMSK_FSUSPM_Msk /*!< Data fetch suspended mask */
18906 #define USB_OTG_GINTMSK_RSTDEM_Pos (23U)
18907 #define USB_OTG_GINTMSK_RSTDEM_Msk (0x1U << USB_OTG_GINTMSK_RSTDEM_Pos) /*!< 0x00800000 */
18908 #define USB_OTG_GINTMSK_RSTDEM USB_OTG_GINTMSK_RSTDEM_Msk /*!< Reset detected interrupt mask */
18909 #define USB_OTG_GINTMSK_PRTIM_Pos (24U)
18910 #define USB_OTG_GINTMSK_PRTIM_Msk (0x1U << USB_OTG_GINTMSK_PRTIM_Pos) /*!< 0x01000000 */
18911 #define USB_OTG_GINTMSK_PRTIM USB_OTG_GINTMSK_PRTIM_Msk /*!< Host port interrupt mask */
18912 #define USB_OTG_GINTMSK_HCIM_Pos (25U)
18913 #define USB_OTG_GINTMSK_HCIM_Msk (0x1U << USB_OTG_GINTMSK_HCIM_Pos) /*!< 0x02000000 */
18914 #define USB_OTG_GINTMSK_HCIM USB_OTG_GINTMSK_HCIM_Msk /*!< Host channels interrupt mask */
18915 #define USB_OTG_GINTMSK_PTXFEM_Pos (26U)
18916 #define USB_OTG_GINTMSK_PTXFEM_Msk (0x1U << USB_OTG_GINTMSK_PTXFEM_Pos) /*!< 0x04000000 */
18917 #define USB_OTG_GINTMSK_PTXFEM USB_OTG_GINTMSK_PTXFEM_Msk /*!< Periodic TxFIFO empty mask */
18918 #define USB_OTG_GINTMSK_LPMINTM_Pos (27U)
18919 #define USB_OTG_GINTMSK_LPMINTM_Msk (0x1U << USB_OTG_GINTMSK_LPMINTM_Pos) /*!< 0x08000000 */
18920 #define USB_OTG_GINTMSK_LPMINTM USB_OTG_GINTMSK_LPMINTM_Msk /*!< LPM interrupt Mask */
18921 #define USB_OTG_GINTMSK_CIDSCHGM_Pos (28U)
18922 #define USB_OTG_GINTMSK_CIDSCHGM_Msk (0x1U << USB_OTG_GINTMSK_CIDSCHGM_Pos) /*!< 0x10000000 */
18923 #define USB_OTG_GINTMSK_CIDSCHGM USB_OTG_GINTMSK_CIDSCHGM_Msk /*!< Connector ID status change mask */
18924 #define USB_OTG_GINTMSK_DISCINT_Pos (29U)
18925 #define USB_OTG_GINTMSK_DISCINT_Msk (0x1U << USB_OTG_GINTMSK_DISCINT_Pos) /*!< 0x20000000 */
18926 #define USB_OTG_GINTMSK_DISCINT USB_OTG_GINTMSK_DISCINT_Msk /*!< Disconnect detected interrupt mask */
18927 #define USB_OTG_GINTMSK_SRQIM_Pos (30U)
18928 #define USB_OTG_GINTMSK_SRQIM_Msk (0x1U << USB_OTG_GINTMSK_SRQIM_Pos) /*!< 0x40000000 */
18929 #define USB_OTG_GINTMSK_SRQIM USB_OTG_GINTMSK_SRQIM_Msk /*!< Session request/new session detected interrupt mask */
18930 #define USB_OTG_GINTMSK_WUIM_Pos (31U)
18931 #define USB_OTG_GINTMSK_WUIM_Msk (0x1U << USB_OTG_GINTMSK_WUIM_Pos) /*!< 0x80000000 */
18932 #define USB_OTG_GINTMSK_WUIM USB_OTG_GINTMSK_WUIM_Msk /*!< Resume/remote wakeup detected interrupt mask */
18933
18934 /******************** Bit definition for USB_OTG_DAINT register ********************/
18935 #define USB_OTG_DAINT_IEPINT_Pos (0U)
18936 #define USB_OTG_DAINT_IEPINT_Msk (0xFFFFU << USB_OTG_DAINT_IEPINT_Pos) /*!< 0x0000FFFF */
18937 #define USB_OTG_DAINT_IEPINT USB_OTG_DAINT_IEPINT_Msk /*!< IN endpoint interrupt bits */
18938 #define USB_OTG_DAINT_OEPINT_Pos (16U)
18939 #define USB_OTG_DAINT_OEPINT_Msk (0xFFFFU << USB_OTG_DAINT_OEPINT_Pos) /*!< 0xFFFF0000 */
18940 #define USB_OTG_DAINT_OEPINT USB_OTG_DAINT_OEPINT_Msk /*!< OUT endpoint interrupt bits */
18941
18942 /******************** Bit definition for USB_OTG_HAINTMSK register ********************/
18943 #define USB_OTG_HAINTMSK_HAINTM_Pos (0U)
18944 #define USB_OTG_HAINTMSK_HAINTM_Msk (0xFFFFU << USB_OTG_HAINTMSK_HAINTM_Pos) /*!< 0x0000FFFF */
18945 #define USB_OTG_HAINTMSK_HAINTM USB_OTG_HAINTMSK_HAINTM_Msk /*!< Channel interrupt mask */
18946
18947 /******************** Bit definition for USB_OTG_GRXSTSP register ********************/
18948 #define USB_OTG_GRXSTSP_EPNUM_Pos (0U)
18949 #define USB_OTG_GRXSTSP_EPNUM_Msk (0xFU << USB_OTG_GRXSTSP_EPNUM_Pos) /*!< 0x0000000F */
18950 #define USB_OTG_GRXSTSP_EPNUM USB_OTG_GRXSTSP_EPNUM_Msk /*!< IN EP interrupt mask bits */
18951 #define USB_OTG_GRXSTSP_BCNT_Pos (4U)
18952 #define USB_OTG_GRXSTSP_BCNT_Msk (0x7FFU << USB_OTG_GRXSTSP_BCNT_Pos) /*!< 0x00007FF0 */
18953 #define USB_OTG_GRXSTSP_BCNT USB_OTG_GRXSTSP_BCNT_Msk /*!< OUT EP interrupt mask bits */
18954 #define USB_OTG_GRXSTSP_DPID_Pos (15U)
18955 #define USB_OTG_GRXSTSP_DPID_Msk (0x3U << USB_OTG_GRXSTSP_DPID_Pos) /*!< 0x00018000 */
18956 #define USB_OTG_GRXSTSP_DPID USB_OTG_GRXSTSP_DPID_Msk /*!< OUT EP interrupt mask bits */
18957 #define USB_OTG_GRXSTSP_PKTSTS_Pos (17U)
18958 #define USB_OTG_GRXSTSP_PKTSTS_Msk (0xFU << USB_OTG_GRXSTSP_PKTSTS_Pos) /*!< 0x001E0000 */
18959 #define USB_OTG_GRXSTSP_PKTSTS USB_OTG_GRXSTSP_PKTSTS_Msk /*!< OUT EP interrupt mask bits */
18960
18961 /******************** Bit definition for USB_OTG_DAINTMSK register ********************/
18962 #define USB_OTG_DAINTMSK_IEPM_Pos (0U)
18963 #define USB_OTG_DAINTMSK_IEPM_Msk (0xFFFFU << USB_OTG_DAINTMSK_IEPM_Pos) /*!< 0x0000FFFF */
18964 #define USB_OTG_DAINTMSK_IEPM USB_OTG_DAINTMSK_IEPM_Msk /*!< IN EP interrupt mask bits */
18965 #define USB_OTG_DAINTMSK_OEPM_Pos (16U)
18966 #define USB_OTG_DAINTMSK_OEPM_Msk (0xFFFFU << USB_OTG_DAINTMSK_OEPM_Pos) /*!< 0xFFFF0000 */
18967 #define USB_OTG_DAINTMSK_OEPM USB_OTG_DAINTMSK_OEPM_Msk /*!< OUT EP interrupt mask bits */
18968
18969 /******************** Bit definition for USB_OTG_GRXFSIZ register ********************/
18970 #define USB_OTG_GRXFSIZ_RXFD_Pos (0U)
18971 #define USB_OTG_GRXFSIZ_RXFD_Msk (0xFFFFU << USB_OTG_GRXFSIZ_RXFD_Pos) /*!< 0x0000FFFF */
18972 #define USB_OTG_GRXFSIZ_RXFD USB_OTG_GRXFSIZ_RXFD_Msk /*!< RxFIFO depth */
18973
18974 /******************** Bit definition for USB_OTG_DVBUSDIS register ********************/
18975 #define USB_OTG_DVBUSDIS_VBUSDT_Pos (0U)
18976 #define USB_OTG_DVBUSDIS_VBUSDT_Msk (0xFFFFU << USB_OTG_DVBUSDIS_VBUSDT_Pos) /*!< 0x0000FFFF */
18977 #define USB_OTG_DVBUSDIS_VBUSDT USB_OTG_DVBUSDIS_VBUSDT_Msk /*!< Device VBUS discharge time */
18978
18979 /******************** Bit definition for OTG register ********************/
18980 #define USB_OTG_NPTXFSA_Pos (0U)
18981 #define USB_OTG_NPTXFSA_Msk (0xFFFFU << USB_OTG_NPTXFSA_Pos) /*!< 0x0000FFFF */
18982 #define USB_OTG_NPTXFSA USB_OTG_NPTXFSA_Msk /*!< Nonperiodic transmit RAM start address */
18983 #define USB_OTG_NPTXFD_Pos (16U)
18984 #define USB_OTG_NPTXFD_Msk (0xFFFFU << USB_OTG_NPTXFD_Pos) /*!< 0xFFFF0000 */
18985 #define USB_OTG_NPTXFD USB_OTG_NPTXFD_Msk /*!< Nonperiodic TxFIFO depth */
18986 #define USB_OTG_TX0FSA_Pos (0U)
18987 #define USB_OTG_TX0FSA_Msk (0xFFFFU << USB_OTG_TX0FSA_Pos) /*!< 0x0000FFFF */
18988 #define USB_OTG_TX0FSA USB_OTG_TX0FSA_Msk /*!< Endpoint 0 transmit RAM start address */
18989 #define USB_OTG_TX0FD_Pos (16U)
18990 #define USB_OTG_TX0FD_Msk (0xFFFFU << USB_OTG_TX0FD_Pos) /*!< 0xFFFF0000 */
18991 #define USB_OTG_TX0FD USB_OTG_TX0FD_Msk /*!< Endpoint 0 TxFIFO depth */
18992
18993 /******************** Bit definition forUSB_OTG_DVBUSPULSE register ********************/
18994 #define USB_OTG_DVBUSPULSE_DVBUSP_Pos (0U)
18995 #define USB_OTG_DVBUSPULSE_DVBUSP_Msk (0xFFFU << USB_OTG_DVBUSPULSE_DVBUSP_Pos) /*!< 0x00000FFF */
18996 #define USB_OTG_DVBUSPULSE_DVBUSP USB_OTG_DVBUSPULSE_DVBUSP_Msk /*!< Device VBUS pulsing time */
18997
18998 /******************** Bit definition for USB_OTG_GNPTXSTS register ********************/
18999 #define USB_OTG_GNPTXSTS_NPTXFSAV_Pos (0U)
19000 #define USB_OTG_GNPTXSTS_NPTXFSAV_Msk (0xFFFFU << USB_OTG_GNPTXSTS_NPTXFSAV_Pos) /*!< 0x0000FFFF */
19001 #define USB_OTG_GNPTXSTS_NPTXFSAV USB_OTG_GNPTXSTS_NPTXFSAV_Msk /*!< Nonperiodic TxFIFO space available */
19002
19003 #define USB_OTG_GNPTXSTS_NPTQXSAV_Pos (16U)
19004 #define USB_OTG_GNPTXSTS_NPTQXSAV_Msk (0xFFU << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00FF0000 */
19005 #define USB_OTG_GNPTXSTS_NPTQXSAV USB_OTG_GNPTXSTS_NPTQXSAV_Msk /*!< Nonperiodic transmit request queue space available */
19006 #define USB_OTG_GNPTXSTS_NPTQXSAV_0 (0x01U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00010000 */
19007 #define USB_OTG_GNPTXSTS_NPTQXSAV_1 (0x02U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00020000 */
19008 #define USB_OTG_GNPTXSTS_NPTQXSAV_2 (0x04U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00040000 */
19009 #define USB_OTG_GNPTXSTS_NPTQXSAV_3 (0x08U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00080000 */
19010 #define USB_OTG_GNPTXSTS_NPTQXSAV_4 (0x10U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00100000 */
19011 #define USB_OTG_GNPTXSTS_NPTQXSAV_5 (0x20U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00200000 */
19012 #define USB_OTG_GNPTXSTS_NPTQXSAV_6 (0x40U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00400000 */
19013 #define USB_OTG_GNPTXSTS_NPTQXSAV_7 (0x80U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00800000 */
19014
19015 #define USB_OTG_GNPTXSTS_NPTXQTOP_Pos (24U)
19016 #define USB_OTG_GNPTXSTS_NPTXQTOP_Msk (0x7FU << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x7F000000 */
19017 #define USB_OTG_GNPTXSTS_NPTXQTOP USB_OTG_GNPTXSTS_NPTXQTOP_Msk /*!< Top of the nonperiodic transmit request queue */
19018 #define USB_OTG_GNPTXSTS_NPTXQTOP_0 (0x01U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x01000000 */
19019 #define USB_OTG_GNPTXSTS_NPTXQTOP_1 (0x02U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x02000000 */
19020 #define USB_OTG_GNPTXSTS_NPTXQTOP_2 (0x04U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x04000000 */
19021 #define USB_OTG_GNPTXSTS_NPTXQTOP_3 (0x08U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x08000000 */
19022 #define USB_OTG_GNPTXSTS_NPTXQTOP_4 (0x10U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x10000000 */
19023 #define USB_OTG_GNPTXSTS_NPTXQTOP_5 (0x20U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x20000000 */
19024 #define USB_OTG_GNPTXSTS_NPTXQTOP_6 (0x40U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x40000000 */
19025
19026 /******************** Bit definition for USB_OTG_DTHRCTL register ********************/
19027 #define USB_OTG_DTHRCTL_NONISOTHREN_Pos (0U)
19028 #define USB_OTG_DTHRCTL_NONISOTHREN_Msk (0x1U << USB_OTG_DTHRCTL_NONISOTHREN_Pos) /*!< 0x00000001 */
19029 #define USB_OTG_DTHRCTL_NONISOTHREN USB_OTG_DTHRCTL_NONISOTHREN_Msk /*!< Nonisochronous IN endpoints threshold enable */
19030 #define USB_OTG_DTHRCTL_ISOTHREN_Pos (1U)
19031 #define USB_OTG_DTHRCTL_ISOTHREN_Msk (0x1U << USB_OTG_DTHRCTL_ISOTHREN_Pos) /*!< 0x00000002 */
19032 #define USB_OTG_DTHRCTL_ISOTHREN USB_OTG_DTHRCTL_ISOTHREN_Msk /*!< ISO IN endpoint threshold enable */
19033
19034 #define USB_OTG_DTHRCTL_TXTHRLEN_Pos (2U)
19035 #define USB_OTG_DTHRCTL_TXTHRLEN_Msk (0x1FFU << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x000007FC */
19036 #define USB_OTG_DTHRCTL_TXTHRLEN USB_OTG_DTHRCTL_TXTHRLEN_Msk /*!< Transmit threshold length */
19037 #define USB_OTG_DTHRCTL_TXTHRLEN_0 (0x001U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000004 */
19038 #define USB_OTG_DTHRCTL_TXTHRLEN_1 (0x002U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000008 */
19039 #define USB_OTG_DTHRCTL_TXTHRLEN_2 (0x004U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000010 */
19040 #define USB_OTG_DTHRCTL_TXTHRLEN_3 (0x008U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000020 */
19041 #define USB_OTG_DTHRCTL_TXTHRLEN_4 (0x010U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000040 */
19042 #define USB_OTG_DTHRCTL_TXTHRLEN_5 (0x020U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000080 */
19043 #define USB_OTG_DTHRCTL_TXTHRLEN_6 (0x040U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000100 */
19044 #define USB_OTG_DTHRCTL_TXTHRLEN_7 (0x080U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000200 */
19045 #define USB_OTG_DTHRCTL_TXTHRLEN_8 (0x100U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000400 */
19046 #define USB_OTG_DTHRCTL_RXTHREN_Pos (16U)
19047 #define USB_OTG_DTHRCTL_RXTHREN_Msk (0x1U << USB_OTG_DTHRCTL_RXTHREN_Pos) /*!< 0x00010000 */
19048 #define USB_OTG_DTHRCTL_RXTHREN USB_OTG_DTHRCTL_RXTHREN_Msk /*!< Receive threshold enable */
19049
19050 #define USB_OTG_DTHRCTL_RXTHRLEN_Pos (17U)
19051 #define USB_OTG_DTHRCTL_RXTHRLEN_Msk (0x1FFU << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x03FE0000 */
19052 #define USB_OTG_DTHRCTL_RXTHRLEN USB_OTG_DTHRCTL_RXTHRLEN_Msk /*!< Receive threshold length */
19053 #define USB_OTG_DTHRCTL_RXTHRLEN_0 (0x001U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00020000 */
19054 #define USB_OTG_DTHRCTL_RXTHRLEN_1 (0x002U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00040000 */
19055 #define USB_OTG_DTHRCTL_RXTHRLEN_2 (0x004U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00080000 */
19056 #define USB_OTG_DTHRCTL_RXTHRLEN_3 (0x008U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00100000 */
19057 #define USB_OTG_DTHRCTL_RXTHRLEN_4 (0x010U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00200000 */
19058 #define USB_OTG_DTHRCTL_RXTHRLEN_5 (0x020U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00400000 */
19059 #define USB_OTG_DTHRCTL_RXTHRLEN_6 (0x040U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00800000 */
19060 #define USB_OTG_DTHRCTL_RXTHRLEN_7 (0x080U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x01000000 */
19061 #define USB_OTG_DTHRCTL_RXTHRLEN_8 (0x100U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x02000000 */
19062 #define USB_OTG_DTHRCTL_ARPEN_Pos (27U)
19063 #define USB_OTG_DTHRCTL_ARPEN_Msk (0x1U << USB_OTG_DTHRCTL_ARPEN_Pos) /*!< 0x08000000 */
19064 #define USB_OTG_DTHRCTL_ARPEN USB_OTG_DTHRCTL_ARPEN_Msk /*!< Arbiter parking enable */
19065
19066 /******************** Bit definition for USB_OTG_DIEPEMPMSK register ********************/
19067 #define USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos (0U)
19068 #define USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk (0xFFFFU << USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos) /*!< 0x0000FFFF */
19069 #define USB_OTG_DIEPEMPMSK_INEPTXFEM USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk /*!< IN EP Tx FIFO empty interrupt mask bits */
19070
19071 /******************** Bit definition for USB_OTG_DEACHINT register ********************/
19072 #define USB_OTG_DEACHINT_IEP1INT_Pos (1U)
19073 #define USB_OTG_DEACHINT_IEP1INT_Msk (0x1U << USB_OTG_DEACHINT_IEP1INT_Pos) /*!< 0x00000002 */
19074 #define USB_OTG_DEACHINT_IEP1INT USB_OTG_DEACHINT_IEP1INT_Msk /*!< IN endpoint 1interrupt bit */
19075 #define USB_OTG_DEACHINT_OEP1INT_Pos (17U)
19076 #define USB_OTG_DEACHINT_OEP1INT_Msk (0x1U << USB_OTG_DEACHINT_OEP1INT_Pos) /*!< 0x00020000 */
19077 #define USB_OTG_DEACHINT_OEP1INT USB_OTG_DEACHINT_OEP1INT_Msk /*!< OUT endpoint 1 interrupt bit */
19078
19079 /******************** Bit definition for USB_OTG_GCCFG register ********************/
19080 #define USB_OTG_GCCFG_PWRDWN_Pos (16U)
19081 #define USB_OTG_GCCFG_PWRDWN_Msk (0x1U << USB_OTG_GCCFG_PWRDWN_Pos) /*!< 0x00010000 */
19082 #define USB_OTG_GCCFG_PWRDWN USB_OTG_GCCFG_PWRDWN_Msk /*!< Power down */
19083 #define USB_OTG_GCCFG_VBDEN_Pos (21U)
19084 #define USB_OTG_GCCFG_VBDEN_Msk (0x1U << USB_OTG_GCCFG_VBDEN_Pos) /*!< 0x00200000 */
19085 #define USB_OTG_GCCFG_VBDEN USB_OTG_GCCFG_VBDEN_Msk /*!< USB VBUS Detection Enable */
19086
19087 /******************** Bit definition forUSB_OTG_DEACHINTMSK register ********************/
19088 #define USB_OTG_DEACHINTMSK_IEP1INTM_Pos (1U)
19089 #define USB_OTG_DEACHINTMSK_IEP1INTM_Msk (0x1U << USB_OTG_DEACHINTMSK_IEP1INTM_Pos) /*!< 0x00000002 */
19090 #define USB_OTG_DEACHINTMSK_IEP1INTM USB_OTG_DEACHINTMSK_IEP1INTM_Msk /*!< IN Endpoint 1 interrupt mask bit */
19091 #define USB_OTG_DEACHINTMSK_OEP1INTM_Pos (17U)
19092 #define USB_OTG_DEACHINTMSK_OEP1INTM_Msk (0x1U << USB_OTG_DEACHINTMSK_OEP1INTM_Pos) /*!< 0x00020000 */
19093 #define USB_OTG_DEACHINTMSK_OEP1INTM USB_OTG_DEACHINTMSK_OEP1INTM_Msk /*!< OUT Endpoint 1 interrupt mask bit */
19094
19095 /******************** Bit definition for USB_OTG_CID register ********************/
19096 #define USB_OTG_CID_PRODUCT_ID_Pos (0U)
19097 #define USB_OTG_CID_PRODUCT_ID_Msk (0xFFFFFFFFU << USB_OTG_CID_PRODUCT_ID_Pos) /*!< 0xFFFFFFFF */
19098 #define USB_OTG_CID_PRODUCT_ID USB_OTG_CID_PRODUCT_ID_Msk /*!< Product ID field */
19099
19100 /******************** Bit definition for USB_OTG_GLPMCFG register ********************/
19101 #define USB_OTG_GLPMCFG_LPMEN_Pos (0U)
19102 #define USB_OTG_GLPMCFG_LPMEN_Msk (0x1U << USB_OTG_GLPMCFG_LPMEN_Pos) /*!< 0x00000001 */
19103 #define USB_OTG_GLPMCFG_LPMEN USB_OTG_GLPMCFG_LPMEN_Msk /*!< LPM support enable */
19104 #define USB_OTG_GLPMCFG_LPMACK_Pos (1U)
19105 #define USB_OTG_GLPMCFG_LPMACK_Msk (0x1U << USB_OTG_GLPMCFG_LPMACK_Pos) /*!< 0x00000002 */
19106 #define USB_OTG_GLPMCFG_LPMACK USB_OTG_GLPMCFG_LPMACK_Msk /*!< LPM Token acknowledge enable */
19107 #define USB_OTG_GLPMCFG_BESL_Pos (2U)
19108 #define USB_OTG_GLPMCFG_BESL_Msk (0xFU << USB_OTG_GLPMCFG_BESL_Pos) /*!< 0x0000003C */
19109 #define USB_OTG_GLPMCFG_BESL USB_OTG_GLPMCFG_BESL_Msk /*!< BESL value received with last ACKed LPM Token */
19110 #define USB_OTG_GLPMCFG_REMWAKE_Pos (6U)
19111 #define USB_OTG_GLPMCFG_REMWAKE_Msk (0x1U << USB_OTG_GLPMCFG_REMWAKE_Pos) /*!< 0x00000040 */
19112 #define USB_OTG_GLPMCFG_REMWAKE USB_OTG_GLPMCFG_REMWAKE_Msk /*!< bRemoteWake value received with last ACKed LPM Token */
19113 #define USB_OTG_GLPMCFG_L1SSEN_Pos (7U)
19114 #define USB_OTG_GLPMCFG_L1SSEN_Msk (0x1U << USB_OTG_GLPMCFG_L1SSEN_Pos) /*!< 0x00000080 */
19115 #define USB_OTG_GLPMCFG_L1SSEN USB_OTG_GLPMCFG_L1SSEN_Msk /*!< L1 shallow sleep enable */
19116 #define USB_OTG_GLPMCFG_BESLTHRS_Pos (8U)
19117 #define USB_OTG_GLPMCFG_BESLTHRS_Msk (0xFU << USB_OTG_GLPMCFG_BESLTHRS_Pos) /*!< 0x00000F00 */
19118 #define USB_OTG_GLPMCFG_BESLTHRS USB_OTG_GLPMCFG_BESLTHRS_Msk /*!< BESL threshold */
19119 #define USB_OTG_GLPMCFG_L1DSEN_Pos (12U)
19120 #define USB_OTG_GLPMCFG_L1DSEN_Msk (0x1U << USB_OTG_GLPMCFG_L1DSEN_Pos) /*!< 0x00001000 */
19121 #define USB_OTG_GLPMCFG_L1DSEN USB_OTG_GLPMCFG_L1DSEN_Msk /*!< L1 deep sleep enable */
19122 #define USB_OTG_GLPMCFG_LPMRSP_Pos (13U)
19123 #define USB_OTG_GLPMCFG_LPMRSP_Msk (0x3U << USB_OTG_GLPMCFG_LPMRSP_Pos) /*!< 0x00006000 */
19124 #define USB_OTG_GLPMCFG_LPMRSP USB_OTG_GLPMCFG_LPMRSP_Msk /*!< LPM response */
19125 #define USB_OTG_GLPMCFG_SLPSTS_Pos (15U)
19126 #define USB_OTG_GLPMCFG_SLPSTS_Msk (0x1U << USB_OTG_GLPMCFG_SLPSTS_Pos) /*!< 0x00008000 */
19127 #define USB_OTG_GLPMCFG_SLPSTS USB_OTG_GLPMCFG_SLPSTS_Msk /*!< Port sleep status */
19128 #define USB_OTG_GLPMCFG_L1RSMOK_Pos (16U)
19129 #define USB_OTG_GLPMCFG_L1RSMOK_Msk (0x1U << USB_OTG_GLPMCFG_L1RSMOK_Pos) /*!< 0x00010000 */
19130 #define USB_OTG_GLPMCFG_L1RSMOK USB_OTG_GLPMCFG_L1RSMOK_Msk /*!< Sleep State Resume OK */
19131 #define USB_OTG_GLPMCFG_LPMCHIDX_Pos (17U)
19132 #define USB_OTG_GLPMCFG_LPMCHIDX_Msk (0xFU << USB_OTG_GLPMCFG_LPMCHIDX_Pos) /*!< 0x001E0000 */
19133 #define USB_OTG_GLPMCFG_LPMCHIDX USB_OTG_GLPMCFG_LPMCHIDX_Msk /*!< LPM Channel Index */
19134 #define USB_OTG_GLPMCFG_LPMRCNT_Pos (21U)
19135 #define USB_OTG_GLPMCFG_LPMRCNT_Msk (0x7U << USB_OTG_GLPMCFG_LPMRCNT_Pos) /*!< 0x00E00000 */
19136 #define USB_OTG_GLPMCFG_LPMRCNT USB_OTG_GLPMCFG_LPMRCNT_Msk /*!< LPM retry count */
19137 #define USB_OTG_GLPMCFG_SNDLPM_Pos (24U)
19138 #define USB_OTG_GLPMCFG_SNDLPM_Msk (0x1U << USB_OTG_GLPMCFG_SNDLPM_Pos) /*!< 0x01000000 */
19139 #define USB_OTG_GLPMCFG_SNDLPM USB_OTG_GLPMCFG_SNDLPM_Msk /*!< Send LPM transaction */
19140 #define USB_OTG_GLPMCFG_LPMRCNTSTS_Pos (25U)
19141 #define USB_OTG_GLPMCFG_LPMRCNTSTS_Msk (0x7U << USB_OTG_GLPMCFG_LPMRCNTSTS_Pos) /*!< 0x0E000000 */
19142 #define USB_OTG_GLPMCFG_LPMRCNTSTS USB_OTG_GLPMCFG_LPMRCNTSTS_Msk /*!< LPM retry count status */
19143 #define USB_OTG_GLPMCFG_ENBESL_Pos (28U)
19144 #define USB_OTG_GLPMCFG_ENBESL_Msk (0x1U << USB_OTG_GLPMCFG_ENBESL_Pos) /*!< 0x10000000 */
19145 #define USB_OTG_GLPMCFG_ENBESL USB_OTG_GLPMCFG_ENBESL_Msk /*!< Enable best effort service latency */
19146
19147 /******************** Bit definition for USB_OTG_DIEPEACHMSK1 register ********************/
19148 #define USB_OTG_DIEPEACHMSK1_XFRCM_Pos (0U)
19149 #define USB_OTG_DIEPEACHMSK1_XFRCM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */
19150 #define USB_OTG_DIEPEACHMSK1_XFRCM USB_OTG_DIEPEACHMSK1_XFRCM_Msk /*!< Transfer completed interrupt mask */
19151 #define USB_OTG_DIEPEACHMSK1_EPDM_Pos (1U)
19152 #define USB_OTG_DIEPEACHMSK1_EPDM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_EPDM_Pos) /*!< 0x00000002 */
19153 #define USB_OTG_DIEPEACHMSK1_EPDM USB_OTG_DIEPEACHMSK1_EPDM_Msk /*!< Endpoint disabled interrupt mask */
19154 #define USB_OTG_DIEPEACHMSK1_TOM_Pos (3U)
19155 #define USB_OTG_DIEPEACHMSK1_TOM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_TOM_Pos) /*!< 0x00000008 */
19156 #define USB_OTG_DIEPEACHMSK1_TOM USB_OTG_DIEPEACHMSK1_TOM_Msk /*!< Timeout condition mask (nonisochronous endpoints) */
19157 #define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos (4U)
19158 #define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk (0x1U << USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */
19159 #define USB_OTG_DIEPEACHMSK1_ITTXFEMSK USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */
19160 #define USB_OTG_DIEPEACHMSK1_INEPNMM_Pos (5U)
19161 #define USB_OTG_DIEPEACHMSK1_INEPNMM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */
19162 #define USB_OTG_DIEPEACHMSK1_INEPNMM USB_OTG_DIEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask */
19163 #define USB_OTG_DIEPEACHMSK1_INEPNEM_Pos (6U)
19164 #define USB_OTG_DIEPEACHMSK1_INEPNEM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_INEPNEM_Pos) /*!< 0x00000040 */
19165 #define USB_OTG_DIEPEACHMSK1_INEPNEM USB_OTG_DIEPEACHMSK1_INEPNEM_Msk /*!< IN endpoint NAK effective mask */
19166 #define USB_OTG_DIEPEACHMSK1_TXFURM_Pos (8U)
19167 #define USB_OTG_DIEPEACHMSK1_TXFURM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_TXFURM_Pos) /*!< 0x00000100 */
19168 #define USB_OTG_DIEPEACHMSK1_TXFURM USB_OTG_DIEPEACHMSK1_TXFURM_Msk /*!< FIFO underrun mask */
19169 #define USB_OTG_DIEPEACHMSK1_BIM_Pos (9U)
19170 #define USB_OTG_DIEPEACHMSK1_BIM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_BIM_Pos) /*!< 0x00000200 */
19171 #define USB_OTG_DIEPEACHMSK1_BIM USB_OTG_DIEPEACHMSK1_BIM_Msk /*!< BNA interrupt mask */
19172 #define USB_OTG_DIEPEACHMSK1_NAKM_Pos (13U)
19173 #define USB_OTG_DIEPEACHMSK1_NAKM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */
19174 #define USB_OTG_DIEPEACHMSK1_NAKM USB_OTG_DIEPEACHMSK1_NAKM_Msk /*!< NAK interrupt mask */
19175
19176 /******************** Bit definition for USB_OTG_HPRT register ********************/
19177 #define USB_OTG_HPRT_PCSTS_Pos (0U)
19178 #define USB_OTG_HPRT_PCSTS_Msk (0x1U << USB_OTG_HPRT_PCSTS_Pos) /*!< 0x00000001 */
19179 #define USB_OTG_HPRT_PCSTS USB_OTG_HPRT_PCSTS_Msk /*!< Port connect status */
19180 #define USB_OTG_HPRT_PCDET_Pos (1U)
19181 #define USB_OTG_HPRT_PCDET_Msk (0x1U << USB_OTG_HPRT_PCDET_Pos) /*!< 0x00000002 */
19182 #define USB_OTG_HPRT_PCDET USB_OTG_HPRT_PCDET_Msk /*!< Port connect detected */
19183 #define USB_OTG_HPRT_PENA_Pos (2U)
19184 #define USB_OTG_HPRT_PENA_Msk (0x1U << USB_OTG_HPRT_PENA_Pos) /*!< 0x00000004 */
19185 #define USB_OTG_HPRT_PENA USB_OTG_HPRT_PENA_Msk /*!< Port enable */
19186 #define USB_OTG_HPRT_PENCHNG_Pos (3U)
19187 #define USB_OTG_HPRT_PENCHNG_Msk (0x1U << USB_OTG_HPRT_PENCHNG_Pos) /*!< 0x00000008 */
19188 #define USB_OTG_HPRT_PENCHNG USB_OTG_HPRT_PENCHNG_Msk /*!< Port enable/disable change */
19189 #define USB_OTG_HPRT_POCA_Pos (4U)
19190 #define USB_OTG_HPRT_POCA_Msk (0x1U << USB_OTG_HPRT_POCA_Pos) /*!< 0x00000010 */
19191 #define USB_OTG_HPRT_POCA USB_OTG_HPRT_POCA_Msk /*!< Port overcurrent active */
19192 #define USB_OTG_HPRT_POCCHNG_Pos (5U)
19193 #define USB_OTG_HPRT_POCCHNG_Msk (0x1U << USB_OTG_HPRT_POCCHNG_Pos) /*!< 0x00000020 */
19194 #define USB_OTG_HPRT_POCCHNG USB_OTG_HPRT_POCCHNG_Msk /*!< Port overcurrent change */
19195 #define USB_OTG_HPRT_PRES_Pos (6U)
19196 #define USB_OTG_HPRT_PRES_Msk (0x1U << USB_OTG_HPRT_PRES_Pos) /*!< 0x00000040 */
19197 #define USB_OTG_HPRT_PRES USB_OTG_HPRT_PRES_Msk /*!< Port resume */
19198 #define USB_OTG_HPRT_PSUSP_Pos (7U)
19199 #define USB_OTG_HPRT_PSUSP_Msk (0x1U << USB_OTG_HPRT_PSUSP_Pos) /*!< 0x00000080 */
19200 #define USB_OTG_HPRT_PSUSP USB_OTG_HPRT_PSUSP_Msk /*!< Port suspend */
19201 #define USB_OTG_HPRT_PRST_Pos (8U)
19202 #define USB_OTG_HPRT_PRST_Msk (0x1U << USB_OTG_HPRT_PRST_Pos) /*!< 0x00000100 */
19203 #define USB_OTG_HPRT_PRST USB_OTG_HPRT_PRST_Msk /*!< Port reset */
19204
19205 #define USB_OTG_HPRT_PLSTS_Pos (10U)
19206 #define USB_OTG_HPRT_PLSTS_Msk (0x3U << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000C00 */
19207 #define USB_OTG_HPRT_PLSTS USB_OTG_HPRT_PLSTS_Msk /*!< Port line status */
19208 #define USB_OTG_HPRT_PLSTS_0 (0x1U << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000400 */
19209 #define USB_OTG_HPRT_PLSTS_1 (0x2U << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000800 */
19210 #define USB_OTG_HPRT_PPWR_Pos (12U)
19211 #define USB_OTG_HPRT_PPWR_Msk (0x1U << USB_OTG_HPRT_PPWR_Pos) /*!< 0x00001000 */
19212 #define USB_OTG_HPRT_PPWR USB_OTG_HPRT_PPWR_Msk /*!< Port power */
19213
19214 #define USB_OTG_HPRT_PTCTL_Pos (13U)
19215 #define USB_OTG_HPRT_PTCTL_Msk (0xFU << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x0001E000 */
19216 #define USB_OTG_HPRT_PTCTL USB_OTG_HPRT_PTCTL_Msk /*!< Port test control */
19217 #define USB_OTG_HPRT_PTCTL_0 (0x1U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00002000 */
19218 #define USB_OTG_HPRT_PTCTL_1 (0x2U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00004000 */
19219 #define USB_OTG_HPRT_PTCTL_2 (0x4U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00008000 */
19220 #define USB_OTG_HPRT_PTCTL_3 (0x8U << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00010000 */
19221
19222 #define USB_OTG_HPRT_PSPD_Pos (17U)
19223 #define USB_OTG_HPRT_PSPD_Msk (0x3U << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00060000 */
19224 #define USB_OTG_HPRT_PSPD USB_OTG_HPRT_PSPD_Msk /*!< Port speed */
19225 #define USB_OTG_HPRT_PSPD_0 (0x1U << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00020000 */
19226 #define USB_OTG_HPRT_PSPD_1 (0x2U << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00040000 */
19227
19228 /******************** Bit definition for USB_OTG_DOEPEACHMSK1 register ********************/
19229 #define USB_OTG_DOEPEACHMSK1_XFRCM_Pos (0U)
19230 #define USB_OTG_DOEPEACHMSK1_XFRCM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */
19231 #define USB_OTG_DOEPEACHMSK1_XFRCM USB_OTG_DOEPEACHMSK1_XFRCM_Msk /*!< Transfer completed interrupt mask */
19232 #define USB_OTG_DOEPEACHMSK1_EPDM_Pos (1U)
19233 #define USB_OTG_DOEPEACHMSK1_EPDM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_EPDM_Pos) /*!< 0x00000002 */
19234 #define USB_OTG_DOEPEACHMSK1_EPDM USB_OTG_DOEPEACHMSK1_EPDM_Msk /*!< Endpoint disabled interrupt mask */
19235 #define USB_OTG_DOEPEACHMSK1_TOM_Pos (3U)
19236 #define USB_OTG_DOEPEACHMSK1_TOM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_TOM_Pos) /*!< 0x00000008 */
19237 #define USB_OTG_DOEPEACHMSK1_TOM USB_OTG_DOEPEACHMSK1_TOM_Msk /*!< Timeout condition mask */
19238 #define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos (4U)
19239 #define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk (0x1U << USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */
19240 #define USB_OTG_DOEPEACHMSK1_ITTXFEMSK USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */
19241 #define USB_OTG_DOEPEACHMSK1_INEPNMM_Pos (5U)
19242 #define USB_OTG_DOEPEACHMSK1_INEPNMM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */
19243 #define USB_OTG_DOEPEACHMSK1_INEPNMM USB_OTG_DOEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask */
19244 #define USB_OTG_DOEPEACHMSK1_INEPNEM_Pos (6U)
19245 #define USB_OTG_DOEPEACHMSK1_INEPNEM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_INEPNEM_Pos) /*!< 0x00000040 */
19246 #define USB_OTG_DOEPEACHMSK1_INEPNEM USB_OTG_DOEPEACHMSK1_INEPNEM_Msk /*!< IN endpoint NAK effective mask */
19247 #define USB_OTG_DOEPEACHMSK1_TXFURM_Pos (8U)
19248 #define USB_OTG_DOEPEACHMSK1_TXFURM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_TXFURM_Pos) /*!< 0x00000100 */
19249 #define USB_OTG_DOEPEACHMSK1_TXFURM USB_OTG_DOEPEACHMSK1_TXFURM_Msk /*!< OUT packet error mask */
19250 #define USB_OTG_DOEPEACHMSK1_BIM_Pos (9U)
19251 #define USB_OTG_DOEPEACHMSK1_BIM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_BIM_Pos) /*!< 0x00000200 */
19252 #define USB_OTG_DOEPEACHMSK1_BIM USB_OTG_DOEPEACHMSK1_BIM_Msk /*!< BNA interrupt mask */
19253 #define USB_OTG_DOEPEACHMSK1_BERRM_Pos (12U)
19254 #define USB_OTG_DOEPEACHMSK1_BERRM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_BERRM_Pos) /*!< 0x00001000 */
19255 #define USB_OTG_DOEPEACHMSK1_BERRM USB_OTG_DOEPEACHMSK1_BERRM_Msk /*!< Bubble error interrupt mask */
19256 #define USB_OTG_DOEPEACHMSK1_NAKM_Pos (13U)
19257 #define USB_OTG_DOEPEACHMSK1_NAKM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */
19258 #define USB_OTG_DOEPEACHMSK1_NAKM USB_OTG_DOEPEACHMSK1_NAKM_Msk /*!< NAK interrupt mask */
19259 #define USB_OTG_DOEPEACHMSK1_NYETM_Pos (14U)
19260 #define USB_OTG_DOEPEACHMSK1_NYETM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_NYETM_Pos) /*!< 0x00004000 */
19261 #define USB_OTG_DOEPEACHMSK1_NYETM USB_OTG_DOEPEACHMSK1_NYETM_Msk /*!< NYET interrupt mask */
19262
19263 /******************** Bit definition for USB_OTG_HPTXFSIZ register ********************/
19264 #define USB_OTG_HPTXFSIZ_PTXSA_Pos (0U)
19265 #define USB_OTG_HPTXFSIZ_PTXSA_Msk (0xFFFFU << USB_OTG_HPTXFSIZ_PTXSA_Pos) /*!< 0x0000FFFF */
19266 #define USB_OTG_HPTXFSIZ_PTXSA USB_OTG_HPTXFSIZ_PTXSA_Msk /*!< Host periodic TxFIFO start address */
19267 #define USB_OTG_HPTXFSIZ_PTXFD_Pos (16U)
19268 #define USB_OTG_HPTXFSIZ_PTXFD_Msk (0xFFFFU << USB_OTG_HPTXFSIZ_PTXFD_Pos) /*!< 0xFFFF0000 */
19269 #define USB_OTG_HPTXFSIZ_PTXFD USB_OTG_HPTXFSIZ_PTXFD_Msk /*!< Host periodic TxFIFO depth */
19270
19271 /******************** Bit definition for USB_OTG_DIEPCTL register ********************/
19272 #define USB_OTG_DIEPCTL_MPSIZ_Pos (0U)
19273 #define USB_OTG_DIEPCTL_MPSIZ_Msk (0x7FFU << USB_OTG_DIEPCTL_MPSIZ_Pos) /*!< 0x000007FF */
19274 #define USB_OTG_DIEPCTL_MPSIZ USB_OTG_DIEPCTL_MPSIZ_Msk /*!< Maximum packet size */
19275 #define USB_OTG_DIEPCTL_USBAEP_Pos (15U)
19276 #define USB_OTG_DIEPCTL_USBAEP_Msk (0x1U << USB_OTG_DIEPCTL_USBAEP_Pos) /*!< 0x00008000 */
19277 #define USB_OTG_DIEPCTL_USBAEP USB_OTG_DIEPCTL_USBAEP_Msk /*!< USB active endpoint */
19278 #define USB_OTG_DIEPCTL_EONUM_DPID_Pos (16U)
19279 #define USB_OTG_DIEPCTL_EONUM_DPID_Msk (0x1U << USB_OTG_DIEPCTL_EONUM_DPID_Pos) /*!< 0x00010000 */
19280 #define USB_OTG_DIEPCTL_EONUM_DPID USB_OTG_DIEPCTL_EONUM_DPID_Msk /*!< Even/odd frame */
19281 #define USB_OTG_DIEPCTL_NAKSTS_Pos (17U)
19282 #define USB_OTG_DIEPCTL_NAKSTS_Msk (0x1U << USB_OTG_DIEPCTL_NAKSTS_Pos) /*!< 0x00020000 */
19283 #define USB_OTG_DIEPCTL_NAKSTS USB_OTG_DIEPCTL_NAKSTS_Msk /*!< NAK status */
19284
19285 #define USB_OTG_DIEPCTL_EPTYP_Pos (18U)
19286 #define USB_OTG_DIEPCTL_EPTYP_Msk (0x3U << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x000C0000 */
19287 #define USB_OTG_DIEPCTL_EPTYP USB_OTG_DIEPCTL_EPTYP_Msk /*!< Endpoint type */
19288 #define USB_OTG_DIEPCTL_EPTYP_0 (0x1U << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x00040000 */
19289 #define USB_OTG_DIEPCTL_EPTYP_1 (0x2U << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x00080000 */
19290 #define USB_OTG_DIEPCTL_STALL_Pos (21U)
19291 #define USB_OTG_DIEPCTL_STALL_Msk (0x1U << USB_OTG_DIEPCTL_STALL_Pos) /*!< 0x00200000 */
19292 #define USB_OTG_DIEPCTL_STALL USB_OTG_DIEPCTL_STALL_Msk /*!< STALL handshake */
19293
19294 #define USB_OTG_DIEPCTL_TXFNUM_Pos (22U)
19295 #define USB_OTG_DIEPCTL_TXFNUM_Msk (0xFU << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x03C00000 */
19296 #define USB_OTG_DIEPCTL_TXFNUM USB_OTG_DIEPCTL_TXFNUM_Msk /*!< TxFIFO number */
19297 #define USB_OTG_DIEPCTL_TXFNUM_0 (0x1U << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x00400000 */
19298 #define USB_OTG_DIEPCTL_TXFNUM_1 (0x2U << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x00800000 */
19299 #define USB_OTG_DIEPCTL_TXFNUM_2 (0x4U << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x01000000 */
19300 #define USB_OTG_DIEPCTL_TXFNUM_3 (0x8U << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x02000000 */
19301 #define USB_OTG_DIEPCTL_CNAK_Pos (26U)
19302 #define USB_OTG_DIEPCTL_CNAK_Msk (0x1U << USB_OTG_DIEPCTL_CNAK_Pos) /*!< 0x04000000 */
19303 #define USB_OTG_DIEPCTL_CNAK USB_OTG_DIEPCTL_CNAK_Msk /*!< Clear NAK */
19304 #define USB_OTG_DIEPCTL_SNAK_Pos (27U)
19305 #define USB_OTG_DIEPCTL_SNAK_Msk (0x1U << USB_OTG_DIEPCTL_SNAK_Pos) /*!< 0x08000000 */
19306 #define USB_OTG_DIEPCTL_SNAK USB_OTG_DIEPCTL_SNAK_Msk /*!< Set NAK */
19307 #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos (28U)
19308 #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk (0x1U << USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */
19309 #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */
19310 #define USB_OTG_DIEPCTL_SODDFRM_Pos (29U)
19311 #define USB_OTG_DIEPCTL_SODDFRM_Msk (0x1U << USB_OTG_DIEPCTL_SODDFRM_Pos) /*!< 0x20000000 */
19312 #define USB_OTG_DIEPCTL_SODDFRM USB_OTG_DIEPCTL_SODDFRM_Msk /*!< Set odd frame */
19313 #define USB_OTG_DIEPCTL_EPDIS_Pos (30U)
19314 #define USB_OTG_DIEPCTL_EPDIS_Msk (0x1U << USB_OTG_DIEPCTL_EPDIS_Pos) /*!< 0x40000000 */
19315 #define USB_OTG_DIEPCTL_EPDIS USB_OTG_DIEPCTL_EPDIS_Msk /*!< Endpoint disable */
19316 #define USB_OTG_DIEPCTL_EPENA_Pos (31U)
19317 #define USB_OTG_DIEPCTL_EPENA_Msk (0x1U << USB_OTG_DIEPCTL_EPENA_Pos) /*!< 0x80000000 */
19318 #define USB_OTG_DIEPCTL_EPENA USB_OTG_DIEPCTL_EPENA_Msk /*!< Endpoint enable */
19319
19320 /******************** Bit definition for USB_OTG_HCCHAR register ********************/
19321 #define USB_OTG_HCCHAR_MPSIZ_Pos (0U)
19322 #define USB_OTG_HCCHAR_MPSIZ_Msk (0x7FFU << USB_OTG_HCCHAR_MPSIZ_Pos) /*!< 0x000007FF */
19323 #define USB_OTG_HCCHAR_MPSIZ USB_OTG_HCCHAR_MPSIZ_Msk /*!< Maximum packet size */
19324
19325 #define USB_OTG_HCCHAR_EPNUM_Pos (11U)
19326 #define USB_OTG_HCCHAR_EPNUM_Msk (0xFU << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00007800 */
19327 #define USB_OTG_HCCHAR_EPNUM USB_OTG_HCCHAR_EPNUM_Msk /*!< Endpoint number */
19328 #define USB_OTG_HCCHAR_EPNUM_0 (0x1U << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00000800 */
19329 #define USB_OTG_HCCHAR_EPNUM_1 (0x2U << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00001000 */
19330 #define USB_OTG_HCCHAR_EPNUM_2 (0x4U << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00002000 */
19331 #define USB_OTG_HCCHAR_EPNUM_3 (0x8U << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00004000 */
19332 #define USB_OTG_HCCHAR_EPDIR_Pos (15U)
19333 #define USB_OTG_HCCHAR_EPDIR_Msk (0x1U << USB_OTG_HCCHAR_EPDIR_Pos) /*!< 0x00008000 */
19334 #define USB_OTG_HCCHAR_EPDIR USB_OTG_HCCHAR_EPDIR_Msk /*!< Endpoint direction */
19335 #define USB_OTG_HCCHAR_LSDEV_Pos (17U)
19336 #define USB_OTG_HCCHAR_LSDEV_Msk (0x1U << USB_OTG_HCCHAR_LSDEV_Pos) /*!< 0x00020000 */
19337 #define USB_OTG_HCCHAR_LSDEV USB_OTG_HCCHAR_LSDEV_Msk /*!< Low-speed device */
19338
19339 #define USB_OTG_HCCHAR_EPTYP_Pos (18U)
19340 #define USB_OTG_HCCHAR_EPTYP_Msk (0x3U << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x000C0000 */
19341 #define USB_OTG_HCCHAR_EPTYP USB_OTG_HCCHAR_EPTYP_Msk /*!< Endpoint type */
19342 #define USB_OTG_HCCHAR_EPTYP_0 (0x1U << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00040000 */
19343 #define USB_OTG_HCCHAR_EPTYP_1 (0x2U << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00080000 */
19344
19345 #define USB_OTG_HCCHAR_MC_Pos (20U)
19346 #define USB_OTG_HCCHAR_MC_Msk (0x3U << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00300000 */
19347 #define USB_OTG_HCCHAR_MC USB_OTG_HCCHAR_MC_Msk /*!< Multi Count (MC) / Error Count (EC) */
19348 #define USB_OTG_HCCHAR_MC_0 (0x1U << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00100000 */
19349 #define USB_OTG_HCCHAR_MC_1 (0x2U << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00200000 */
19350
19351 #define USB_OTG_HCCHAR_DAD_Pos (22U)
19352 #define USB_OTG_HCCHAR_DAD_Msk (0x7FU << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x1FC00000 */
19353 #define USB_OTG_HCCHAR_DAD USB_OTG_HCCHAR_DAD_Msk /*!< Device address */
19354 #define USB_OTG_HCCHAR_DAD_0 (0x01U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x00400000 */
19355 #define USB_OTG_HCCHAR_DAD_1 (0x02U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x00800000 */
19356 #define USB_OTG_HCCHAR_DAD_2 (0x04U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x01000000 */
19357 #define USB_OTG_HCCHAR_DAD_3 (0x08U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x02000000 */
19358 #define USB_OTG_HCCHAR_DAD_4 (0x10U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x04000000 */
19359 #define USB_OTG_HCCHAR_DAD_5 (0x20U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x08000000 */
19360 #define USB_OTG_HCCHAR_DAD_6 (0x40U << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x10000000 */
19361 #define USB_OTG_HCCHAR_ODDFRM_Pos (29U)
19362 #define USB_OTG_HCCHAR_ODDFRM_Msk (0x1U << USB_OTG_HCCHAR_ODDFRM_Pos) /*!< 0x20000000 */
19363 #define USB_OTG_HCCHAR_ODDFRM USB_OTG_HCCHAR_ODDFRM_Msk /*!< Odd frame */
19364 #define USB_OTG_HCCHAR_CHDIS_Pos (30U)
19365 #define USB_OTG_HCCHAR_CHDIS_Msk (0x1U << USB_OTG_HCCHAR_CHDIS_Pos) /*!< 0x40000000 */
19366 #define USB_OTG_HCCHAR_CHDIS USB_OTG_HCCHAR_CHDIS_Msk /*!< Channel disable */
19367 #define USB_OTG_HCCHAR_CHENA_Pos (31U)
19368 #define USB_OTG_HCCHAR_CHENA_Msk (0x1U << USB_OTG_HCCHAR_CHENA_Pos) /*!< 0x80000000 */
19369 #define USB_OTG_HCCHAR_CHENA USB_OTG_HCCHAR_CHENA_Msk /*!< Channel enable */
19370
19371 /******************** Bit definition for USB_OTG_HCSPLT register ********************/
19372
19373 #define USB_OTG_HCSPLT_PRTADDR_Pos (0U)
19374 #define USB_OTG_HCSPLT_PRTADDR_Msk (0x7FU << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x0000007F */
19375 #define USB_OTG_HCSPLT_PRTADDR USB_OTG_HCSPLT_PRTADDR_Msk /*!< Port address */
19376 #define USB_OTG_HCSPLT_PRTADDR_0 (0x01U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000001 */
19377 #define USB_OTG_HCSPLT_PRTADDR_1 (0x02U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000002 */
19378 #define USB_OTG_HCSPLT_PRTADDR_2 (0x04U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000004 */
19379 #define USB_OTG_HCSPLT_PRTADDR_3 (0x08U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000008 */
19380 #define USB_OTG_HCSPLT_PRTADDR_4 (0x10U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000010 */
19381 #define USB_OTG_HCSPLT_PRTADDR_5 (0x20U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000020 */
19382 #define USB_OTG_HCSPLT_PRTADDR_6 (0x40U << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000040 */
19383
19384 #define USB_OTG_HCSPLT_HUBADDR_Pos (7U)
19385 #define USB_OTG_HCSPLT_HUBADDR_Msk (0x7FU << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00003F80 */
19386 #define USB_OTG_HCSPLT_HUBADDR USB_OTG_HCSPLT_HUBADDR_Msk /*!< Hub address */
19387 #define USB_OTG_HCSPLT_HUBADDR_0 (0x01U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000080 */
19388 #define USB_OTG_HCSPLT_HUBADDR_1 (0x02U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000100 */
19389 #define USB_OTG_HCSPLT_HUBADDR_2 (0x04U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000200 */
19390 #define USB_OTG_HCSPLT_HUBADDR_3 (0x08U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000400 */
19391 #define USB_OTG_HCSPLT_HUBADDR_4 (0x10U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000800 */
19392 #define USB_OTG_HCSPLT_HUBADDR_5 (0x20U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00001000 */
19393 #define USB_OTG_HCSPLT_HUBADDR_6 (0x40U << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00002000 */
19394
19395 #define USB_OTG_HCSPLT_XACTPOS_Pos (14U)
19396 #define USB_OTG_HCSPLT_XACTPOS_Msk (0x3U << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x0000C000 */
19397 #define USB_OTG_HCSPLT_XACTPOS USB_OTG_HCSPLT_XACTPOS_Msk /*!< XACTPOS */
19398 #define USB_OTG_HCSPLT_XACTPOS_0 (0x1U << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x00004000 */
19399 #define USB_OTG_HCSPLT_XACTPOS_1 (0x2U << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x00008000 */
19400 #define USB_OTG_HCSPLT_COMPLSPLT_Pos (16U)
19401 #define USB_OTG_HCSPLT_COMPLSPLT_Msk (0x1U << USB_OTG_HCSPLT_COMPLSPLT_Pos) /*!< 0x00010000 */
19402 #define USB_OTG_HCSPLT_COMPLSPLT USB_OTG_HCSPLT_COMPLSPLT_Msk /*!< Do complete split */
19403 #define USB_OTG_HCSPLT_SPLITEN_Pos (31U)
19404 #define USB_OTG_HCSPLT_SPLITEN_Msk (0x1U << USB_OTG_HCSPLT_SPLITEN_Pos) /*!< 0x80000000 */
19405 #define USB_OTG_HCSPLT_SPLITEN USB_OTG_HCSPLT_SPLITEN_Msk /*!< Split enable */
19406
19407 /******************** Bit definition for USB_OTG_HCINT register ********************/
19408 #define USB_OTG_HCINT_XFRC_Pos (0U)
19409 #define USB_OTG_HCINT_XFRC_Msk (0x1U << USB_OTG_HCINT_XFRC_Pos) /*!< 0x00000001 */
19410 #define USB_OTG_HCINT_XFRC USB_OTG_HCINT_XFRC_Msk /*!< Transfer completed */
19411 #define USB_OTG_HCINT_CHH_Pos (1U)
19412 #define USB_OTG_HCINT_CHH_Msk (0x1U << USB_OTG_HCINT_CHH_Pos) /*!< 0x00000002 */
19413 #define USB_OTG_HCINT_CHH USB_OTG_HCINT_CHH_Msk /*!< Channel halted */
19414 #define USB_OTG_HCINT_AHBERR_Pos (2U)
19415 #define USB_OTG_HCINT_AHBERR_Msk (0x1U << USB_OTG_HCINT_AHBERR_Pos) /*!< 0x00000004 */
19416 #define USB_OTG_HCINT_AHBERR USB_OTG_HCINT_AHBERR_Msk /*!< AHB error */
19417 #define USB_OTG_HCINT_STALL_Pos (3U)
19418 #define USB_OTG_HCINT_STALL_Msk (0x1U << USB_OTG_HCINT_STALL_Pos) /*!< 0x00000008 */
19419 #define USB_OTG_HCINT_STALL USB_OTG_HCINT_STALL_Msk /*!< STALL response received interrupt */
19420 #define USB_OTG_HCINT_NAK_Pos (4U)
19421 #define USB_OTG_HCINT_NAK_Msk (0x1U << USB_OTG_HCINT_NAK_Pos) /*!< 0x00000010 */
19422 #define USB_OTG_HCINT_NAK USB_OTG_HCINT_NAK_Msk /*!< NAK response received interrupt */
19423 #define USB_OTG_HCINT_ACK_Pos (5U)
19424 #define USB_OTG_HCINT_ACK_Msk (0x1U << USB_OTG_HCINT_ACK_Pos) /*!< 0x00000020 */
19425 #define USB_OTG_HCINT_ACK USB_OTG_HCINT_ACK_Msk /*!< ACK response received/transmitted interrupt */
19426 #define USB_OTG_HCINT_NYET_Pos (6U)
19427 #define USB_OTG_HCINT_NYET_Msk (0x1U << USB_OTG_HCINT_NYET_Pos) /*!< 0x00000040 */
19428 #define USB_OTG_HCINT_NYET USB_OTG_HCINT_NYET_Msk /*!< Response received interrupt */
19429 #define USB_OTG_HCINT_TXERR_Pos (7U)
19430 #define USB_OTG_HCINT_TXERR_Msk (0x1U << USB_OTG_HCINT_TXERR_Pos) /*!< 0x00000080 */
19431 #define USB_OTG_HCINT_TXERR USB_OTG_HCINT_TXERR_Msk /*!< Transaction error */
19432 #define USB_OTG_HCINT_BBERR_Pos (8U)
19433 #define USB_OTG_HCINT_BBERR_Msk (0x1U << USB_OTG_HCINT_BBERR_Pos) /*!< 0x00000100 */
19434 #define USB_OTG_HCINT_BBERR USB_OTG_HCINT_BBERR_Msk /*!< Babble error */
19435 #define USB_OTG_HCINT_FRMOR_Pos (9U)
19436 #define USB_OTG_HCINT_FRMOR_Msk (0x1U << USB_OTG_HCINT_FRMOR_Pos) /*!< 0x00000200 */
19437 #define USB_OTG_HCINT_FRMOR USB_OTG_HCINT_FRMOR_Msk /*!< Frame overrun */
19438 #define USB_OTG_HCINT_DTERR_Pos (10U)
19439 #define USB_OTG_HCINT_DTERR_Msk (0x1U << USB_OTG_HCINT_DTERR_Pos) /*!< 0x00000400 */
19440 #define USB_OTG_HCINT_DTERR USB_OTG_HCINT_DTERR_Msk /*!< Data toggle error */
19441
19442 /******************** Bit definition for USB_OTG_DIEPINT register ********************/
19443 #define USB_OTG_DIEPINT_XFRC_Pos (0U)
19444 #define USB_OTG_DIEPINT_XFRC_Msk (0x1U << USB_OTG_DIEPINT_XFRC_Pos) /*!< 0x00000001 */
19445 #define USB_OTG_DIEPINT_XFRC USB_OTG_DIEPINT_XFRC_Msk /*!< Transfer completed interrupt */
19446 #define USB_OTG_DIEPINT_EPDISD_Pos (1U)
19447 #define USB_OTG_DIEPINT_EPDISD_Msk (0x1U << USB_OTG_DIEPINT_EPDISD_Pos) /*!< 0x00000002 */
19448 #define USB_OTG_DIEPINT_EPDISD USB_OTG_DIEPINT_EPDISD_Msk /*!< Endpoint disabled interrupt */
19449 #define USB_OTG_DIEPINT_TOC_Pos (3U)
19450 #define USB_OTG_DIEPINT_TOC_Msk (0x1U << USB_OTG_DIEPINT_TOC_Pos) /*!< 0x00000008 */
19451 #define USB_OTG_DIEPINT_TOC USB_OTG_DIEPINT_TOC_Msk /*!< Timeout condition */
19452 #define USB_OTG_DIEPINT_ITTXFE_Pos (4U)
19453 #define USB_OTG_DIEPINT_ITTXFE_Msk (0x1U << USB_OTG_DIEPINT_ITTXFE_Pos) /*!< 0x00000010 */
19454 #define USB_OTG_DIEPINT_ITTXFE USB_OTG_DIEPINT_ITTXFE_Msk /*!< IN token received when TxFIFO is empty */
19455 #define USB_OTG_DIEPINT_INEPNE_Pos (6U)
19456 #define USB_OTG_DIEPINT_INEPNE_Msk (0x1U << USB_OTG_DIEPINT_INEPNE_Pos) /*!< 0x00000040 */
19457 #define USB_OTG_DIEPINT_INEPNE USB_OTG_DIEPINT_INEPNE_Msk /*!< IN endpoint NAK effective */
19458 #define USB_OTG_DIEPINT_TXFE_Pos (7U)
19459 #define USB_OTG_DIEPINT_TXFE_Msk (0x1U << USB_OTG_DIEPINT_TXFE_Pos) /*!< 0x00000080 */
19460 #define USB_OTG_DIEPINT_TXFE USB_OTG_DIEPINT_TXFE_Msk /*!< Transmit FIFO empty */
19461 #define USB_OTG_DIEPINT_TXFIFOUDRN_Pos (8U)
19462 #define USB_OTG_DIEPINT_TXFIFOUDRN_Msk (0x1U << USB_OTG_DIEPINT_TXFIFOUDRN_Pos) /*!< 0x00000100 */
19463 #define USB_OTG_DIEPINT_TXFIFOUDRN USB_OTG_DIEPINT_TXFIFOUDRN_Msk /*!< Transmit Fifo Underrun */
19464 #define USB_OTG_DIEPINT_BNA_Pos (9U)
19465 #define USB_OTG_DIEPINT_BNA_Msk (0x1U << USB_OTG_DIEPINT_BNA_Pos) /*!< 0x00000200 */
19466 #define USB_OTG_DIEPINT_BNA USB_OTG_DIEPINT_BNA_Msk /*!< Buffer not available interrupt */
19467 #define USB_OTG_DIEPINT_PKTDRPSTS_Pos (11U)
19468 #define USB_OTG_DIEPINT_PKTDRPSTS_Msk (0x1U << USB_OTG_DIEPINT_PKTDRPSTS_Pos) /*!< 0x00000800 */
19469 #define USB_OTG_DIEPINT_PKTDRPSTS USB_OTG_DIEPINT_PKTDRPSTS_Msk /*!< Packet dropped status */
19470 #define USB_OTG_DIEPINT_BERR_Pos (12U)
19471 #define USB_OTG_DIEPINT_BERR_Msk (0x1U << USB_OTG_DIEPINT_BERR_Pos) /*!< 0x00001000 */
19472 #define USB_OTG_DIEPINT_BERR USB_OTG_DIEPINT_BERR_Msk /*!< Babble error interrupt */
19473 #define USB_OTG_DIEPINT_NAK_Pos (13U)
19474 #define USB_OTG_DIEPINT_NAK_Msk (0x1U << USB_OTG_DIEPINT_NAK_Pos) /*!< 0x00002000 */
19475 #define USB_OTG_DIEPINT_NAK USB_OTG_DIEPINT_NAK_Msk /*!< NAK interrupt */
19476
19477 /******************** Bit definition forUSB_OTG_HCINTMSK register ********************/
19478 #define USB_OTG_HCINTMSK_XFRCM_Pos (0U)
19479 #define USB_OTG_HCINTMSK_XFRCM_Msk (0x1U << USB_OTG_HCINTMSK_XFRCM_Pos) /*!< 0x00000001 */
19480 #define USB_OTG_HCINTMSK_XFRCM USB_OTG_HCINTMSK_XFRCM_Msk /*!< Transfer completed mask */
19481 #define USB_OTG_HCINTMSK_CHHM_Pos (1U)
19482 #define USB_OTG_HCINTMSK_CHHM_Msk (0x1U << USB_OTG_HCINTMSK_CHHM_Pos) /*!< 0x00000002 */
19483 #define USB_OTG_HCINTMSK_CHHM USB_OTG_HCINTMSK_CHHM_Msk /*!< Channel halted mask */
19484 #define USB_OTG_HCINTMSK_AHBERR_Pos (2U)
19485 #define USB_OTG_HCINTMSK_AHBERR_Msk (0x1U << USB_OTG_HCINTMSK_AHBERR_Pos) /*!< 0x00000004 */
19486 #define USB_OTG_HCINTMSK_AHBERR USB_OTG_HCINTMSK_AHBERR_Msk /*!< AHB error */
19487 #define USB_OTG_HCINTMSK_STALLM_Pos (3U)
19488 #define USB_OTG_HCINTMSK_STALLM_Msk (0x1U << USB_OTG_HCINTMSK_STALLM_Pos) /*!< 0x00000008 */
19489 #define USB_OTG_HCINTMSK_STALLM USB_OTG_HCINTMSK_STALLM_Msk /*!< STALL response received interrupt mask */
19490 #define USB_OTG_HCINTMSK_NAKM_Pos (4U)
19491 #define USB_OTG_HCINTMSK_NAKM_Msk (0x1U << USB_OTG_HCINTMSK_NAKM_Pos) /*!< 0x00000010 */
19492 #define USB_OTG_HCINTMSK_NAKM USB_OTG_HCINTMSK_NAKM_Msk /*!< NAK response received interrupt mask */
19493 #define USB_OTG_HCINTMSK_ACKM_Pos (5U)
19494 #define USB_OTG_HCINTMSK_ACKM_Msk (0x1U << USB_OTG_HCINTMSK_ACKM_Pos) /*!< 0x00000020 */
19495 #define USB_OTG_HCINTMSK_ACKM USB_OTG_HCINTMSK_ACKM_Msk /*!< ACK response received/transmitted interrupt mask */
19496 #define USB_OTG_HCINTMSK_NYET_Pos (6U)
19497 #define USB_OTG_HCINTMSK_NYET_Msk (0x1U << USB_OTG_HCINTMSK_NYET_Pos) /*!< 0x00000040 */
19498 #define USB_OTG_HCINTMSK_NYET USB_OTG_HCINTMSK_NYET_Msk /*!< response received interrupt mask */
19499 #define USB_OTG_HCINTMSK_TXERRM_Pos (7U)
19500 #define USB_OTG_HCINTMSK_TXERRM_Msk (0x1U << USB_OTG_HCINTMSK_TXERRM_Pos) /*!< 0x00000080 */
19501 #define USB_OTG_HCINTMSK_TXERRM USB_OTG_HCINTMSK_TXERRM_Msk /*!< Transaction error mask */
19502 #define USB_OTG_HCINTMSK_BBERRM_Pos (8U)
19503 #define USB_OTG_HCINTMSK_BBERRM_Msk (0x1U << USB_OTG_HCINTMSK_BBERRM_Pos) /*!< 0x00000100 */
19504 #define USB_OTG_HCINTMSK_BBERRM USB_OTG_HCINTMSK_BBERRM_Msk /*!< Babble error mask */
19505 #define USB_OTG_HCINTMSK_FRMORM_Pos (9U)
19506 #define USB_OTG_HCINTMSK_FRMORM_Msk (0x1U << USB_OTG_HCINTMSK_FRMORM_Pos) /*!< 0x00000200 */
19507 #define USB_OTG_HCINTMSK_FRMORM USB_OTG_HCINTMSK_FRMORM_Msk /*!< Frame overrun mask */
19508 #define USB_OTG_HCINTMSK_DTERRM_Pos (10U)
19509 #define USB_OTG_HCINTMSK_DTERRM_Msk (0x1U << USB_OTG_HCINTMSK_DTERRM_Pos) /*!< 0x00000400 */
19510 #define USB_OTG_HCINTMSK_DTERRM USB_OTG_HCINTMSK_DTERRM_Msk /*!< Data toggle error mask */
19511
19512 /******************** Bit definition for USB_OTG_DIEPTSIZ register ********************/
19513
19514 #define USB_OTG_DIEPTSIZ_XFRSIZ_Pos (0U)
19515 #define USB_OTG_DIEPTSIZ_XFRSIZ_Msk (0x7FFFFU << USB_OTG_DIEPTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */
19516 #define USB_OTG_DIEPTSIZ_XFRSIZ USB_OTG_DIEPTSIZ_XFRSIZ_Msk /*!< Transfer size */
19517 #define USB_OTG_DIEPTSIZ_PKTCNT_Pos (19U)
19518 #define USB_OTG_DIEPTSIZ_PKTCNT_Msk (0x3FFU << USB_OTG_DIEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */
19519 #define USB_OTG_DIEPTSIZ_PKTCNT USB_OTG_DIEPTSIZ_PKTCNT_Msk /*!< Packet count */
19520 #define USB_OTG_DIEPTSIZ_MULCNT_Pos (29U)
19521 #define USB_OTG_DIEPTSIZ_MULCNT_Msk (0x3U << USB_OTG_DIEPTSIZ_MULCNT_Pos) /*!< 0x60000000 */
19522 #define USB_OTG_DIEPTSIZ_MULCNT USB_OTG_DIEPTSIZ_MULCNT_Msk /*!< Packet count */
19523 /******************** Bit definition for USB_OTG_HCTSIZ register ********************/
19524 #define USB_OTG_HCTSIZ_XFRSIZ_Pos (0U)
19525 #define USB_OTG_HCTSIZ_XFRSIZ_Msk (0x7FFFFU << USB_OTG_HCTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */
19526 #define USB_OTG_HCTSIZ_XFRSIZ USB_OTG_HCTSIZ_XFRSIZ_Msk /*!< Transfer size */
19527 #define USB_OTG_HCTSIZ_PKTCNT_Pos (19U)
19528 #define USB_OTG_HCTSIZ_PKTCNT_Msk (0x3FFU << USB_OTG_HCTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */
19529 #define USB_OTG_HCTSIZ_PKTCNT USB_OTG_HCTSIZ_PKTCNT_Msk /*!< Packet count */
19530 #define USB_OTG_HCTSIZ_DOPING_Pos (31U)
19531 #define USB_OTG_HCTSIZ_DOPING_Msk (0x1U << USB_OTG_HCTSIZ_DOPING_Pos) /*!< 0x80000000 */
19532 #define USB_OTG_HCTSIZ_DOPING USB_OTG_HCTSIZ_DOPING_Msk /*!< Do PING */
19533 #define USB_OTG_HCTSIZ_DPID_Pos (29U)
19534 #define USB_OTG_HCTSIZ_DPID_Msk (0x3U << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x60000000 */
19535 #define USB_OTG_HCTSIZ_DPID USB_OTG_HCTSIZ_DPID_Msk /*!< Data PID */
19536 #define USB_OTG_HCTSIZ_DPID_0 (0x1U << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x20000000 */
19537 #define USB_OTG_HCTSIZ_DPID_1 (0x2U << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x40000000 */
19538
19539 /******************** Bit definition for USB_OTG_DIEPDMA register ********************/
19540 #define USB_OTG_DIEPDMA_DMAADDR_Pos (0U)
19541 #define USB_OTG_DIEPDMA_DMAADDR_Msk (0xFFFFFFFFU << USB_OTG_DIEPDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */
19542 #define USB_OTG_DIEPDMA_DMAADDR USB_OTG_DIEPDMA_DMAADDR_Msk /*!< DMA address */
19543
19544 /******************** Bit definition for USB_OTG_HCDMA register ********************/
19545 #define USB_OTG_HCDMA_DMAADDR_Pos (0U)
19546 #define USB_OTG_HCDMA_DMAADDR_Msk (0xFFFFFFFFU << USB_OTG_HCDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */
19547 #define USB_OTG_HCDMA_DMAADDR USB_OTG_HCDMA_DMAADDR_Msk /*!< DMA address */
19548
19549 /******************** Bit definition for USB_OTG_DTXFSTS register ********************/
19550 #define USB_OTG_DTXFSTS_INEPTFSAV_Pos (0U)
19551 #define USB_OTG_DTXFSTS_INEPTFSAV_Msk (0xFFFFU << USB_OTG_DTXFSTS_INEPTFSAV_Pos) /*!< 0x0000FFFF */
19552 #define USB_OTG_DTXFSTS_INEPTFSAV USB_OTG_DTXFSTS_INEPTFSAV_Msk /*!< IN endpoint TxFIFO space available */
19553
19554 /******************** Bit definition for USB_OTG_DIEPTXF register ********************/
19555 #define USB_OTG_DIEPTXF_INEPTXSA_Pos (0U)
19556 #define USB_OTG_DIEPTXF_INEPTXSA_Msk (0xFFFFU << USB_OTG_DIEPTXF_INEPTXSA_Pos) /*!< 0x0000FFFF */
19557 #define USB_OTG_DIEPTXF_INEPTXSA USB_OTG_DIEPTXF_INEPTXSA_Msk /*!< IN endpoint FIFOx transmit RAM start address */
19558 #define USB_OTG_DIEPTXF_INEPTXFD_Pos (16U)
19559 #define USB_OTG_DIEPTXF_INEPTXFD_Msk (0xFFFFU << USB_OTG_DIEPTXF_INEPTXFD_Pos) /*!< 0xFFFF0000 */
19560 #define USB_OTG_DIEPTXF_INEPTXFD USB_OTG_DIEPTXF_INEPTXFD_Msk /*!< IN endpoint TxFIFO depth */
19561
19562 /******************** Bit definition for USB_OTG_DOEPCTL register ********************/
19563
19564 #define USB_OTG_DOEPCTL_MPSIZ_Pos (0U)
19565 #define USB_OTG_DOEPCTL_MPSIZ_Msk (0x7FFU << USB_OTG_DOEPCTL_MPSIZ_Pos) /*!< 0x000007FF */
19566 #define USB_OTG_DOEPCTL_MPSIZ USB_OTG_DOEPCTL_MPSIZ_Msk /*!< Maximum packet size */ /*!<Bit 1 */
19567 #define USB_OTG_DOEPCTL_USBAEP_Pos (15U)
19568 #define USB_OTG_DOEPCTL_USBAEP_Msk (0x1U << USB_OTG_DOEPCTL_USBAEP_Pos) /*!< 0x00008000 */
19569 #define USB_OTG_DOEPCTL_USBAEP USB_OTG_DOEPCTL_USBAEP_Msk /*!< USB active endpoint */
19570 #define USB_OTG_DOEPCTL_NAKSTS_Pos (17U)
19571 #define USB_OTG_DOEPCTL_NAKSTS_Msk (0x1U << USB_OTG_DOEPCTL_NAKSTS_Pos) /*!< 0x00020000 */
19572 #define USB_OTG_DOEPCTL_NAKSTS USB_OTG_DOEPCTL_NAKSTS_Msk /*!< NAK status */
19573 #define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos (28U)
19574 #define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk (0x1U << USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */
19575 #define USB_OTG_DOEPCTL_SD0PID_SEVNFRM USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */
19576 #define USB_OTG_DOEPCTL_SODDFRM_Pos (29U)
19577 #define USB_OTG_DOEPCTL_SODDFRM_Msk (0x1U << USB_OTG_DOEPCTL_SODDFRM_Pos) /*!< 0x20000000 */
19578 #define USB_OTG_DOEPCTL_SODDFRM USB_OTG_DOEPCTL_SODDFRM_Msk /*!< Set odd frame */
19579 #define USB_OTG_DOEPCTL_EPTYP_Pos (18U)
19580 #define USB_OTG_DOEPCTL_EPTYP_Msk (0x3U << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x000C0000 */
19581 #define USB_OTG_DOEPCTL_EPTYP USB_OTG_DOEPCTL_EPTYP_Msk /*!< Endpoint type */
19582 #define USB_OTG_DOEPCTL_EPTYP_0 (0x1U << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x00040000 */
19583 #define USB_OTG_DOEPCTL_EPTYP_1 (0x2U << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x00080000 */
19584 #define USB_OTG_DOEPCTL_SNPM_Pos (20U)
19585 #define USB_OTG_DOEPCTL_SNPM_Msk (0x1U << USB_OTG_DOEPCTL_SNPM_Pos) /*!< 0x00100000 */
19586 #define USB_OTG_DOEPCTL_SNPM USB_OTG_DOEPCTL_SNPM_Msk /*!< Snoop mode */
19587 #define USB_OTG_DOEPCTL_STALL_Pos (21U)
19588 #define USB_OTG_DOEPCTL_STALL_Msk (0x1U << USB_OTG_DOEPCTL_STALL_Pos) /*!< 0x00200000 */
19589 #define USB_OTG_DOEPCTL_STALL USB_OTG_DOEPCTL_STALL_Msk /*!< STALL handshake */
19590 #define USB_OTG_DOEPCTL_CNAK_Pos (26U)
19591 #define USB_OTG_DOEPCTL_CNAK_Msk (0x1U << USB_OTG_DOEPCTL_CNAK_Pos) /*!< 0x04000000 */
19592 #define USB_OTG_DOEPCTL_CNAK USB_OTG_DOEPCTL_CNAK_Msk /*!< Clear NAK */
19593 #define USB_OTG_DOEPCTL_SNAK_Pos (27U)
19594 #define USB_OTG_DOEPCTL_SNAK_Msk (0x1U << USB_OTG_DOEPCTL_SNAK_Pos) /*!< 0x08000000 */
19595 #define USB_OTG_DOEPCTL_SNAK USB_OTG_DOEPCTL_SNAK_Msk /*!< Set NAK */
19596 #define USB_OTG_DOEPCTL_EPDIS_Pos (30U)
19597 #define USB_OTG_DOEPCTL_EPDIS_Msk (0x1U << USB_OTG_DOEPCTL_EPDIS_Pos) /*!< 0x40000000 */
19598 #define USB_OTG_DOEPCTL_EPDIS USB_OTG_DOEPCTL_EPDIS_Msk /*!< Endpoint disable */
19599 #define USB_OTG_DOEPCTL_EPENA_Pos (31U)
19600 #define USB_OTG_DOEPCTL_EPENA_Msk (0x1U << USB_OTG_DOEPCTL_EPENA_Pos) /*!< 0x80000000 */
19601 #define USB_OTG_DOEPCTL_EPENA USB_OTG_DOEPCTL_EPENA_Msk /*!< Endpoint enable */
19602
19603 /******************** Bit definition for USB_OTG_DOEPINT register ********************/
19604 #define USB_OTG_DOEPINT_XFRC_Pos (0U)
19605 #define USB_OTG_DOEPINT_XFRC_Msk (0x1U << USB_OTG_DOEPINT_XFRC_Pos) /*!< 0x00000001 */
19606 #define USB_OTG_DOEPINT_XFRC USB_OTG_DOEPINT_XFRC_Msk /*!< Transfer completed interrupt */
19607 #define USB_OTG_DOEPINT_EPDISD_Pos (1U)
19608 #define USB_OTG_DOEPINT_EPDISD_Msk (0x1U << USB_OTG_DOEPINT_EPDISD_Pos) /*!< 0x00000002 */
19609 #define USB_OTG_DOEPINT_EPDISD USB_OTG_DOEPINT_EPDISD_Msk /*!< Endpoint disabled interrupt */
19610 #define USB_OTG_DOEPINT_STUP_Pos (3U)
19611 #define USB_OTG_DOEPINT_STUP_Msk (0x1U << USB_OTG_DOEPINT_STUP_Pos) /*!< 0x00000008 */
19612 #define USB_OTG_DOEPINT_STUP USB_OTG_DOEPINT_STUP_Msk /*!< SETUP phase done */
19613 #define USB_OTG_DOEPINT_OTEPDIS_Pos (4U)
19614 #define USB_OTG_DOEPINT_OTEPDIS_Msk (0x1U << USB_OTG_DOEPINT_OTEPDIS_Pos) /*!< 0x00000010 */
19615 #define USB_OTG_DOEPINT_OTEPDIS USB_OTG_DOEPINT_OTEPDIS_Msk /*!< OUT token received when endpoint disabled */
19616 #define USB_OTG_DOEPINT_OTEPSPR_Pos (5U)
19617 #define USB_OTG_DOEPINT_OTEPSPR_Msk (0x1U << USB_OTG_DOEPINT_OTEPSPR_Pos) /*!< 0x00000020 */
19618 #define USB_OTG_DOEPINT_OTEPSPR USB_OTG_DOEPINT_OTEPSPR_Msk /*!< Status Phase Received For Control Write */
19619 #define USB_OTG_DOEPINT_B2BSTUP_Pos (6U)
19620 #define USB_OTG_DOEPINT_B2BSTUP_Msk (0x1U << USB_OTG_DOEPINT_B2BSTUP_Pos) /*!< 0x00000040 */
19621 #define USB_OTG_DOEPINT_B2BSTUP USB_OTG_DOEPINT_B2BSTUP_Msk /*!< Back-to-back SETUP packets received */
19622 #define USB_OTG_DOEPINT_NYET_Pos (14U)
19623 #define USB_OTG_DOEPINT_NYET_Msk (0x1U << USB_OTG_DOEPINT_NYET_Pos) /*!< 0x00004000 */
19624 #define USB_OTG_DOEPINT_NYET USB_OTG_DOEPINT_NYET_Msk /*!< NYET interrupt */
19625
19626 /******************** Bit definition for USB_OTG_DOEPTSIZ register ********************/
19627
19628 #define USB_OTG_DOEPTSIZ_XFRSIZ_Pos (0U)
19629 #define USB_OTG_DOEPTSIZ_XFRSIZ_Msk (0x7FFFFU << USB_OTG_DOEPTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */
19630 #define USB_OTG_DOEPTSIZ_XFRSIZ USB_OTG_DOEPTSIZ_XFRSIZ_Msk /*!< Transfer size */
19631 #define USB_OTG_DOEPTSIZ_PKTCNT_Pos (19U)
19632 #define USB_OTG_DOEPTSIZ_PKTCNT_Msk (0x3FFU << USB_OTG_DOEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */
19633 #define USB_OTG_DOEPTSIZ_PKTCNT USB_OTG_DOEPTSIZ_PKTCNT_Msk /*!< Packet count */
19634
19635 #define USB_OTG_DOEPTSIZ_STUPCNT_Pos (29U)
19636 #define USB_OTG_DOEPTSIZ_STUPCNT_Msk (0x3U << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x60000000 */
19637 #define USB_OTG_DOEPTSIZ_STUPCNT USB_OTG_DOEPTSIZ_STUPCNT_Msk /*!< SETUP packet count */
19638 #define USB_OTG_DOEPTSIZ_STUPCNT_0 (0x1U << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x20000000 */
19639 #define USB_OTG_DOEPTSIZ_STUPCNT_1 (0x2U << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x40000000 */
19640
19641 /******************** Bit definition for PCGCCTL register ********************/
19642 #define USB_OTG_PCGCCTL_STOPCLK_Pos (0U)
19643 #define USB_OTG_PCGCCTL_STOPCLK_Msk (0x1U << USB_OTG_PCGCCTL_STOPCLK_Pos) /*!< 0x00000001 */
19644 #define USB_OTG_PCGCCTL_STOPCLK USB_OTG_PCGCCTL_STOPCLK_Msk /*!< SETUP packet count */
19645 #define USB_OTG_PCGCCTL_GATECLK_Pos (1U)
19646 #define USB_OTG_PCGCCTL_GATECLK_Msk (0x1U << USB_OTG_PCGCCTL_GATECLK_Pos) /*!< 0x00000002 */
19647 #define USB_OTG_PCGCCTL_GATECLK USB_OTG_PCGCCTL_GATECLK_Msk /*!<Bit 0 */
19648 #define USB_OTG_PCGCCTL_PHYSUSP_Pos (4U)
19649 #define USB_OTG_PCGCCTL_PHYSUSP_Msk (0x1U << USB_OTG_PCGCCTL_PHYSUSP_Pos) /*!< 0x00000010 */
19650 #define USB_OTG_PCGCCTL_PHYSUSP USB_OTG_PCGCCTL_PHYSUSP_Msk /*!<Bit 1 */
19651
19652 /* Legacy define */
19653 /******************** Bit definition for OTG register ********************/
19654 #define USB_OTG_CHNUM_Pos (0U)
19655 #define USB_OTG_CHNUM_Msk (0xFU << USB_OTG_CHNUM_Pos) /*!< 0x0000000F */
19656 #define USB_OTG_CHNUM USB_OTG_CHNUM_Msk /*!< Channel number */
19657 #define USB_OTG_CHNUM_0 (0x1U << USB_OTG_CHNUM_Pos) /*!< 0x00000001 */
19658 #define USB_OTG_CHNUM_1 (0x2U << USB_OTG_CHNUM_Pos) /*!< 0x00000002 */
19659 #define USB_OTG_CHNUM_2 (0x4U << USB_OTG_CHNUM_Pos) /*!< 0x00000004 */
19660 #define USB_OTG_CHNUM_3 (0x8U << USB_OTG_CHNUM_Pos) /*!< 0x00000008 */
19661 #define USB_OTG_BCNT_Pos (4U)
19662 #define USB_OTG_BCNT_Msk (0x7FFU << USB_OTG_BCNT_Pos) /*!< 0x00007FF0 */
19663 #define USB_OTG_BCNT USB_OTG_BCNT_Msk /*!< Byte count */
19664
19665 #define USB_OTG_DPID_Pos (15U)
19666 #define USB_OTG_DPID_Msk (0x3U << USB_OTG_DPID_Pos) /*!< 0x00018000 */
19667 #define USB_OTG_DPID USB_OTG_DPID_Msk /*!< Data PID */
19668 #define USB_OTG_DPID_0 (0x1U << USB_OTG_DPID_Pos) /*!< 0x00008000 */
19669 #define USB_OTG_DPID_1 (0x2U << USB_OTG_DPID_Pos) /*!< 0x00010000 */
19670
19671 #define USB_OTG_PKTSTS_Pos (17U)
19672 #define USB_OTG_PKTSTS_Msk (0xFU << USB_OTG_PKTSTS_Pos) /*!< 0x001E0000 */
19673 #define USB_OTG_PKTSTS USB_OTG_PKTSTS_Msk /*!< Packet status */
19674 #define USB_OTG_PKTSTS_0 (0x1U << USB_OTG_PKTSTS_Pos) /*!< 0x00020000 */
19675 #define USB_OTG_PKTSTS_1 (0x2U << USB_OTG_PKTSTS_Pos) /*!< 0x00040000 */
19676 #define USB_OTG_PKTSTS_2 (0x4U << USB_OTG_PKTSTS_Pos) /*!< 0x00080000 */
19677 #define USB_OTG_PKTSTS_3 (0x8U << USB_OTG_PKTSTS_Pos) /*!< 0x00100000 */
19678
19679 #define USB_OTG_EPNUM_Pos (0U)
19680 #define USB_OTG_EPNUM_Msk (0xFU << USB_OTG_EPNUM_Pos) /*!< 0x0000000F */
19681 #define USB_OTG_EPNUM USB_OTG_EPNUM_Msk /*!< Endpoint number */
19682 #define USB_OTG_EPNUM_0 (0x1U << USB_OTG_EPNUM_Pos) /*!< 0x00000001 */
19683 #define USB_OTG_EPNUM_1 (0x2U << USB_OTG_EPNUM_Pos) /*!< 0x00000002 */
19684 #define USB_OTG_EPNUM_2 (0x4U << USB_OTG_EPNUM_Pos) /*!< 0x00000004 */
19685 #define USB_OTG_EPNUM_3 (0x8U << USB_OTG_EPNUM_Pos) /*!< 0x00000008 */
19686
19687 #define USB_OTG_FRMNUM_Pos (21U)
19688 #define USB_OTG_FRMNUM_Msk (0xFU << USB_OTG_FRMNUM_Pos) /*!< 0x01E00000 */
19689 #define USB_OTG_FRMNUM USB_OTG_FRMNUM_Msk /*!< Frame number */
19690 #define USB_OTG_FRMNUM_0 (0x1U << USB_OTG_FRMNUM_Pos) /*!< 0x00200000 */
19691 #define USB_OTG_FRMNUM_1 (0x2U << USB_OTG_FRMNUM_Pos) /*!< 0x00400000 */
19692 #define USB_OTG_FRMNUM_2 (0x4U << USB_OTG_FRMNUM_Pos) /*!< 0x00800000 */
19693 #define USB_OTG_FRMNUM_3 (0x8U << USB_OTG_FRMNUM_Pos) /*!< 0x01000000 */
19694 /**
19695 * @}
19696 */
19697
19698 /**
19699 * @}
19700 */
19701
19702 /** @addtogroup Exported_macros
19703 * @{
19704 */
19705
19706 /******************************* ADC Instances ********************************/
19707 #define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1) || \
19708 ((INSTANCE) == ADC2) || \
19709 ((INSTANCE) == ADC3))
19710
19711 #define IS_ADC_MULTIMODE_MASTER_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
19712
19713 #define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC123_COMMON)
19714
19715 /******************************* CAN Instances ********************************/
19716 #define IS_CAN_ALL_INSTANCE(INSTANCE) (((INSTANCE) == CAN1) || \
19717 ((INSTANCE) == CAN2))
19718 /******************************* CRC Instances ********************************/
19719 #define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
19720
19721 /******************************* DAC Instances ********************************/
19722 #define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC1)
19723
19724 /******************************* DCMI Instances *******************************/
19725 #define IS_DCMI_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DCMI)
19726
19727 /******************************* DMA2D Instances *******************************/
19728 #define IS_DMA2D_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DMA2D)
19729
19730 /******************************** DMA Instances *******************************/
19731 #define IS_DMA_STREAM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0) || \
19732 ((INSTANCE) == DMA1_Stream1) || \
19733 ((INSTANCE) == DMA1_Stream2) || \
19734 ((INSTANCE) == DMA1_Stream3) || \
19735 ((INSTANCE) == DMA1_Stream4) || \
19736 ((INSTANCE) == DMA1_Stream5) || \
19737 ((INSTANCE) == DMA1_Stream6) || \
19738 ((INSTANCE) == DMA1_Stream7) || \
19739 ((INSTANCE) == DMA2_Stream0) || \
19740 ((INSTANCE) == DMA2_Stream1) || \
19741 ((INSTANCE) == DMA2_Stream2) || \
19742 ((INSTANCE) == DMA2_Stream3) || \
19743 ((INSTANCE) == DMA2_Stream4) || \
19744 ((INSTANCE) == DMA2_Stream5) || \
19745 ((INSTANCE) == DMA2_Stream6) || \
19746 ((INSTANCE) == DMA2_Stream7))
19747
19748 /******************************* GPIO Instances *******************************/
19749 #define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
19750 ((INSTANCE) == GPIOB) || \
19751 ((INSTANCE) == GPIOC) || \
19752 ((INSTANCE) == GPIOD) || \
19753 ((INSTANCE) == GPIOE) || \
19754 ((INSTANCE) == GPIOF) || \
19755 ((INSTANCE) == GPIOG) || \
19756 ((INSTANCE) == GPIOH) || \
19757 ((INSTANCE) == GPIOI) || \
19758 ((INSTANCE) == GPIOJ) || \
19759 ((INSTANCE) == GPIOK))
19760
19761 /******************************** I2C Instances *******************************/
19762 #define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
19763 ((INSTANCE) == I2C2) || \
19764 ((INSTANCE) == I2C3))
19765
19766 /******************************* SMBUS Instances ******************************/
19767 #define IS_SMBUS_ALL_INSTANCE IS_I2C_ALL_INSTANCE
19768
19769 /******************************** I2S Instances *******************************/
19770
19771 #define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI2) || \
19772 ((INSTANCE) == SPI3))
19773
19774 /*************************** I2S Extended Instances ***************************/
19775 #define IS_I2S_EXT_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2S2ext)|| \
19776 ((INSTANCE) == I2S3ext))
19777 /* Legacy Defines */
19778 #define IS_I2S_ALL_INSTANCE_EXT IS_I2S_EXT_ALL_INSTANCE
19779
19780 /****************************** LTDC Instances ********************************/
19781 #define IS_LTDC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == LTDC)
19782 /******************************* RNG Instances ********************************/
19783 #define IS_RNG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RNG)
19784
19785 /****************************** RTC Instances *********************************/
19786 #define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
19787
19788 /******************************* SAI Instances ********************************/
19789 #define IS_SAI_ALL_INSTANCE(PERIPH) (((PERIPH) == SAI1_Block_A) || \
19790 ((PERIPH) == SAI1_Block_B))
19791 /* Legacy define */
19792
19793 #define IS_SAI_BLOCK_PERIPH IS_SAI_ALL_INSTANCE
19794
19795 /******************************** SPI Instances *******************************/
19796 #define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
19797 ((INSTANCE) == SPI2) || \
19798 ((INSTANCE) == SPI3) || \
19799 ((INSTANCE) == SPI4) || \
19800 ((INSTANCE) == SPI5) || \
19801 ((INSTANCE) == SPI6))
19802
19803
19804 /****************** TIM Instances : All supported instances *******************/
19805 #define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
19806 ((INSTANCE) == TIM2) || \
19807 ((INSTANCE) == TIM3) || \
19808 ((INSTANCE) == TIM4) || \
19809 ((INSTANCE) == TIM5) || \
19810 ((INSTANCE) == TIM6) || \
19811 ((INSTANCE) == TIM7) || \
19812 ((INSTANCE) == TIM8) || \
19813 ((INSTANCE) == TIM9) || \
19814 ((INSTANCE) == TIM10)|| \
19815 ((INSTANCE) == TIM11)|| \
19816 ((INSTANCE) == TIM12)|| \
19817 ((INSTANCE) == TIM13)|| \
19818 ((INSTANCE) == TIM14))
19819
19820 /************* TIM Instances : at least 1 capture/compare channel *************/
19821 #define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
19822 ((INSTANCE) == TIM2) || \
19823 ((INSTANCE) == TIM3) || \
19824 ((INSTANCE) == TIM4) || \
19825 ((INSTANCE) == TIM5) || \
19826 ((INSTANCE) == TIM8) || \
19827 ((INSTANCE) == TIM9) || \
19828 ((INSTANCE) == TIM10) || \
19829 ((INSTANCE) == TIM11) || \
19830 ((INSTANCE) == TIM12) || \
19831 ((INSTANCE) == TIM13) || \
19832 ((INSTANCE) == TIM14))
19833
19834 /************ TIM Instances : at least 2 capture/compare channels *************/
19835 #define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
19836 ((INSTANCE) == TIM2) || \
19837 ((INSTANCE) == TIM3) || \
19838 ((INSTANCE) == TIM4) || \
19839 ((INSTANCE) == TIM5) || \
19840 ((INSTANCE) == TIM8) || \
19841 ((INSTANCE) == TIM9) || \
19842 ((INSTANCE) == TIM12))
19843
19844 /************ TIM Instances : at least 3 capture/compare channels *************/
19845 #define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
19846 ((INSTANCE) == TIM2) || \
19847 ((INSTANCE) == TIM3) || \
19848 ((INSTANCE) == TIM4) || \
19849 ((INSTANCE) == TIM5) || \
19850 ((INSTANCE) == TIM8))
19851
19852 /************ TIM Instances : at least 4 capture/compare channels *************/
19853 #define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
19854 ((INSTANCE) == TIM2) || \
19855 ((INSTANCE) == TIM3) || \
19856 ((INSTANCE) == TIM4) || \
19857 ((INSTANCE) == TIM5) || \
19858 ((INSTANCE) == TIM8))
19859
19860 /******************** TIM Instances : Advanced-control timers *****************/
19861 #define IS_TIM_ADVANCED_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
19862 ((INSTANCE) == TIM8))
19863
19864 /******************* TIM Instances : Timer input XOR function *****************/
19865 #define IS_TIM_XOR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
19866 ((INSTANCE) == TIM2) || \
19867 ((INSTANCE) == TIM3) || \
19868 ((INSTANCE) == TIM4) || \
19869 ((INSTANCE) == TIM5) || \
19870 ((INSTANCE) == TIM8))
19871
19872 /****************** TIM Instances : DMA requests generation (UDE) *************/
19873 #define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
19874 ((INSTANCE) == TIM2) || \
19875 ((INSTANCE) == TIM3) || \
19876 ((INSTANCE) == TIM4) || \
19877 ((INSTANCE) == TIM5) || \
19878 ((INSTANCE) == TIM6) || \
19879 ((INSTANCE) == TIM7) || \
19880 ((INSTANCE) == TIM8))
19881
19882 /************ TIM Instances : DMA requests generation (CCxDE) *****************/
19883 #define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
19884 ((INSTANCE) == TIM2) || \
19885 ((INSTANCE) == TIM3) || \
19886 ((INSTANCE) == TIM4) || \
19887 ((INSTANCE) == TIM5) || \
19888 ((INSTANCE) == TIM8))
19889
19890 /************ TIM Instances : DMA requests generation (COMDE) *****************/
19891 #define IS_TIM_CCDMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
19892 ((INSTANCE) == TIM2) || \
19893 ((INSTANCE) == TIM3) || \
19894 ((INSTANCE) == TIM4) || \
19895 ((INSTANCE) == TIM5) || \
19896 ((INSTANCE) == TIM8))
19897
19898 /******************** TIM Instances : DMA burst feature ***********************/
19899 #define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
19900 ((INSTANCE) == TIM2) || \
19901 ((INSTANCE) == TIM3) || \
19902 ((INSTANCE) == TIM4) || \
19903 ((INSTANCE) == TIM5) || \
19904 ((INSTANCE) == TIM8))
19905
19906 /****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/
19907 #define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
19908 ((INSTANCE) == TIM2) || \
19909 ((INSTANCE) == TIM3) || \
19910 ((INSTANCE) == TIM4) || \
19911 ((INSTANCE) == TIM5) || \
19912 ((INSTANCE) == TIM6) || \
19913 ((INSTANCE) == TIM7) || \
19914 ((INSTANCE) == TIM8))
19915
19916 /*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
19917 #define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
19918 ((INSTANCE) == TIM2) || \
19919 ((INSTANCE) == TIM3) || \
19920 ((INSTANCE) == TIM4) || \
19921 ((INSTANCE) == TIM5) || \
19922 ((INSTANCE) == TIM8) || \
19923 ((INSTANCE) == TIM9) || \
19924 ((INSTANCE) == TIM12))
19925
19926 /********************** TIM Instances : 32 bit Counter ************************/
19927 #define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)(((INSTANCE) == TIM2) || \
19928 ((INSTANCE) == TIM5))
19929
19930 /***************** TIM Instances : external trigger input availabe ************/
19931 #define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
19932 ((INSTANCE) == TIM2) || \
19933 ((INSTANCE) == TIM3) || \
19934 ((INSTANCE) == TIM4) || \
19935 ((INSTANCE) == TIM5) || \
19936 ((INSTANCE) == TIM8))
19937
19938 /****************** TIM Instances : remapping capability **********************/
19939 #define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
19940 ((INSTANCE) == TIM5) || \
19941 ((INSTANCE) == TIM11))
19942
19943 /******************* TIM Instances : output(s) available **********************/
19944 #define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
19945 ((((INSTANCE) == TIM1) && \
19946 (((CHANNEL) == TIM_CHANNEL_1) || \
19947 ((CHANNEL) == TIM_CHANNEL_2) || \
19948 ((CHANNEL) == TIM_CHANNEL_3) || \
19949 ((CHANNEL) == TIM_CHANNEL_4))) \
19950 || \
19951 (((INSTANCE) == TIM2) && \
19952 (((CHANNEL) == TIM_CHANNEL_1) || \
19953 ((CHANNEL) == TIM_CHANNEL_2) || \
19954 ((CHANNEL) == TIM_CHANNEL_3) || \
19955 ((CHANNEL) == TIM_CHANNEL_4))) \
19956 || \
19957 (((INSTANCE) == TIM3) && \
19958 (((CHANNEL) == TIM_CHANNEL_1) || \
19959 ((CHANNEL) == TIM_CHANNEL_2) || \
19960 ((CHANNEL) == TIM_CHANNEL_3) || \
19961 ((CHANNEL) == TIM_CHANNEL_4))) \
19962 || \
19963 (((INSTANCE) == TIM4) && \
19964 (((CHANNEL) == TIM_CHANNEL_1) || \
19965 ((CHANNEL) == TIM_CHANNEL_2) || \
19966 ((CHANNEL) == TIM_CHANNEL_3) || \
19967 ((CHANNEL) == TIM_CHANNEL_4))) \
19968 || \
19969 (((INSTANCE) == TIM5) && \
19970 (((CHANNEL) == TIM_CHANNEL_1) || \
19971 ((CHANNEL) == TIM_CHANNEL_2) || \
19972 ((CHANNEL) == TIM_CHANNEL_3) || \
19973 ((CHANNEL) == TIM_CHANNEL_4))) \
19974 || \
19975 (((INSTANCE) == TIM8) && \
19976 (((CHANNEL) == TIM_CHANNEL_1) || \
19977 ((CHANNEL) == TIM_CHANNEL_2) || \
19978 ((CHANNEL) == TIM_CHANNEL_3) || \
19979 ((CHANNEL) == TIM_CHANNEL_4))) \
19980 || \
19981 (((INSTANCE) == TIM9) && \
19982 (((CHANNEL) == TIM_CHANNEL_1) || \
19983 ((CHANNEL) == TIM_CHANNEL_2))) \
19984 || \
19985 (((INSTANCE) == TIM10) && \
19986 (((CHANNEL) == TIM_CHANNEL_1))) \
19987 || \
19988 (((INSTANCE) == TIM11) && \
19989 (((CHANNEL) == TIM_CHANNEL_1))) \
19990 || \
19991 (((INSTANCE) == TIM12) && \
19992 (((CHANNEL) == TIM_CHANNEL_1) || \
19993 ((CHANNEL) == TIM_CHANNEL_2))) \
19994 || \
19995 (((INSTANCE) == TIM13) && \
19996 (((CHANNEL) == TIM_CHANNEL_1))) \
19997 || \
19998 (((INSTANCE) == TIM14) && \
19999 (((CHANNEL) == TIM_CHANNEL_1))))
20000
20001 /************ TIM Instances : complementary output(s) available ***************/
20002 #define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
20003 ((((INSTANCE) == TIM1) && \
20004 (((CHANNEL) == TIM_CHANNEL_1) || \
20005 ((CHANNEL) == TIM_CHANNEL_2) || \
20006 ((CHANNEL) == TIM_CHANNEL_3))) \
20007 || \
20008 (((INSTANCE) == TIM8) && \
20009 (((CHANNEL) == TIM_CHANNEL_1) || \
20010 ((CHANNEL) == TIM_CHANNEL_2) || \
20011 ((CHANNEL) == TIM_CHANNEL_3))))
20012
20013 /****************** TIM Instances : supporting counting mode selection ********/
20014 #define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
20015 ((INSTANCE) == TIM2) || \
20016 ((INSTANCE) == TIM3) || \
20017 ((INSTANCE) == TIM4) || \
20018 ((INSTANCE) == TIM5) || \
20019 ((INSTANCE) == TIM8))
20020
20021 /****************** TIM Instances : supporting clock division *****************/
20022 #define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
20023 ((INSTANCE) == TIM2) || \
20024 ((INSTANCE) == TIM3) || \
20025 ((INSTANCE) == TIM4) || \
20026 ((INSTANCE) == TIM5) || \
20027 ((INSTANCE) == TIM8) || \
20028 ((INSTANCE) == TIM9) || \
20029 ((INSTANCE) == TIM10)|| \
20030 ((INSTANCE) == TIM11)|| \
20031 ((INSTANCE) == TIM12)|| \
20032 ((INSTANCE) == TIM13)|| \
20033 ((INSTANCE) == TIM14))
20034
20035 /****************** TIM Instances : supporting commutation event generation ***/
20036 #define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)|| \
20037 ((INSTANCE) == TIM8))
20038
20039
20040 /****************** TIM Instances : supporting OCxREF clear *******************/
20041 #define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
20042 ((INSTANCE) == TIM2) || \
20043 ((INSTANCE) == TIM3) || \
20044 ((INSTANCE) == TIM4) || \
20045 ((INSTANCE) == TIM5) || \
20046 ((INSTANCE) == TIM8))
20047
20048 /****** TIM Instances : supporting external clock mode 1 for ETRF input *******/
20049 #define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
20050 ((INSTANCE) == TIM2) || \
20051 ((INSTANCE) == TIM3) || \
20052 ((INSTANCE) == TIM4) || \
20053 ((INSTANCE) == TIM5) || \
20054 ((INSTANCE) == TIM8) || \
20055 ((INSTANCE) == TIM9) || \
20056 ((INSTANCE) == TIM12))
20057
20058 /****** TIM Instances : supporting external clock mode 2 for ETRF input *******/
20059 #define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
20060 ((INSTANCE) == TIM2) || \
20061 ((INSTANCE) == TIM3) || \
20062 ((INSTANCE) == TIM4) || \
20063 ((INSTANCE) == TIM5) || \
20064 ((INSTANCE) == TIM8))
20065
20066 /****************** TIM Instances : supporting repetition counter *************/
20067 #define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
20068 ((INSTANCE) == TIM8))
20069
20070 /****************** TIM Instances : supporting encoder interface **************/
20071 #define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
20072 ((INSTANCE) == TIM2) || \
20073 ((INSTANCE) == TIM3) || \
20074 ((INSTANCE) == TIM4) || \
20075 ((INSTANCE) == TIM5) || \
20076 ((INSTANCE) == TIM8) || \
20077 ((INSTANCE) == TIM9) || \
20078 ((INSTANCE) == TIM12))
20079 /****************** TIM Instances : supporting Hall sensor interface **********/
20080 #define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
20081 ((INSTANCE) == TIM2) || \
20082 ((INSTANCE) == TIM3) || \
20083 ((INSTANCE) == TIM4) || \
20084 ((INSTANCE) == TIM5) || \
20085 ((INSTANCE) == TIM8))
20086 /****************** TIM Instances : supporting the break function *************/
20087 #define IS_TIM_BREAK_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
20088 ((INSTANCE) == TIM8))
20089
20090 /******************** USART Instances : Synchronous mode **********************/
20091 #define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
20092 ((INSTANCE) == USART2) || \
20093 ((INSTANCE) == USART3) || \
20094 ((INSTANCE) == USART6))
20095
20096 /******************** UART Instances : Half-Duplex mode **********************/
20097 #define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
20098 ((INSTANCE) == USART2) || \
20099 ((INSTANCE) == USART3) || \
20100 ((INSTANCE) == UART4) || \
20101 ((INSTANCE) == UART5) || \
20102 ((INSTANCE) == USART6) || \
20103 ((INSTANCE) == UART7) || \
20104 ((INSTANCE) == UART8))
20105
20106 /* Legacy defines */
20107 #define IS_UART_INSTANCE IS_UART_HALFDUPLEX_INSTANCE
20108
20109 /****************** UART Instances : Hardware Flow control ********************/
20110 #define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
20111 ((INSTANCE) == USART2) || \
20112 ((INSTANCE) == USART3) || \
20113 ((INSTANCE) == USART6))
20114 /******************** UART Instances : LIN mode **********************/
20115 #define IS_UART_LIN_INSTANCE IS_UART_HALFDUPLEX_INSTANCE
20116
20117 /********************* UART Instances : Smart card mode ***********************/
20118 #define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
20119 ((INSTANCE) == USART2) || \
20120 ((INSTANCE) == USART3) || \
20121 ((INSTANCE) == USART6))
20122
20123 /*********************** UART Instances : IRDA mode ***************************/
20124 #define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
20125 ((INSTANCE) == USART2) || \
20126 ((INSTANCE) == USART3) || \
20127 ((INSTANCE) == UART4) || \
20128 ((INSTANCE) == UART5) || \
20129 ((INSTANCE) == USART6) || \
20130 ((INSTANCE) == UART7) || \
20131 ((INSTANCE) == UART8))
20132
20133 /*********************** PCD Instances ****************************************/
20134 #define IS_PCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS) || \
20135 ((INSTANCE) == USB_OTG_HS))
20136
20137 /*********************** HCD Instances ****************************************/
20138 #define IS_HCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS) || \
20139 ((INSTANCE) == USB_OTG_HS))
20140
20141 /****************************** SDIO Instances ********************************/
20142 #define IS_SDIO_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SDIO)
20143
20144 /****************************** IWDG Instances ********************************/
20145 #define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
20146
20147 /****************************** WWDG Instances ********************************/
20148 #define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
20149
20150
20151 /****************************** QSPI Instances ********************************/
20152 #define IS_QSPI_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == QUADSPI)
20153 /****************************** USB Exported Constants ************************/
20154 #define USB_OTG_FS_HOST_MAX_CHANNEL_NBR 12U
20155 #define USB_OTG_FS_MAX_IN_ENDPOINTS 6U /* Including EP0 */
20156 #define USB_OTG_FS_MAX_OUT_ENDPOINTS 6U /* Including EP0 */
20157 #define USB_OTG_FS_TOTAL_FIFO_SIZE 1280U /* in Bytes */
20158 #define USB_OTG_HS_HOST_MAX_CHANNEL_NBR 16U
20159 #define USB_OTG_HS_MAX_IN_ENDPOINTS 8U /* Including EP0 */
20160 #define USB_OTG_HS_MAX_OUT_ENDPOINTS 8U /* Including EP0 */
20161 #define USB_OTG_HS_TOTAL_FIFO_SIZE 4096U /* in Bytes */
20162
20163 /*
20164 * @brief Specific devices reset values definitions
20165 */
20166 #define RCC_PLLCFGR_RST_VALUE 0x24003010U
20167 #define RCC_PLLI2SCFGR_RST_VALUE 0x24003000U
20168 #define RCC_PLLSAICFGR_RST_VALUE 0x24003000U
20169
20170 #define RCC_MAX_FREQUENCY 180000000U /*!< Max frequency of family in Hz*/
20171 #define RCC_MAX_FREQUENCY_SCALE1 RCC_MAX_FREQUENCY /*!< Maximum frequency for system clock at power scale1, in Hz */
20172 #define RCC_MAX_FREQUENCY_SCALE2 168000000U /*!< Maximum frequency for system clock at power scale2, in Hz */
20173 #define RCC_MAX_FREQUENCY_SCALE3 120000000U /*!< Maximum frequency for system clock at power scale3, in Hz */
20174 #define RCC_PLLVCO_OUTPUT_MIN 192000000U /*!< Frequency min for PLLVCO output, in Hz */
20175 #define RCC_PLLVCO_INPUT_MIN 950000U /*!< Frequency min for PLLVCO input, in Hz */
20176 #define RCC_PLLVCO_INPUT_MAX 2100000U /*!< Frequency max for PLLVCO input, in Hz */
20177 #define RCC_PLLVCO_OUTPUT_MAX 432000000U /*!< Frequency max for PLLVCO output, in Hz */
20178
20179 #define RCC_PLLN_MIN_VALUE 50U
20180 #define RCC_PLLN_MAX_VALUE 432U
20181
20182 #define FLASH_SCALE1_LATENCY1_FREQ 30000000U /*!< HCLK frequency to set FLASH latency 1 in power scale 1 */
20183 #define FLASH_SCALE1_LATENCY2_FREQ 60000000U /*!< HCLK frequency to set FLASH latency 2 in power scale 1 */
20184 #define FLASH_SCALE1_LATENCY3_FREQ 90000000U /*!< HCLK frequency to set FLASH latency 3 in power scale 1 */
20185 #define FLASH_SCALE1_LATENCY4_FREQ 120000000U /*!< HCLK frequency to set FLASH latency 4 in power scale 1 */
20186 #define FLASH_SCALE1_LATENCY5_FREQ 150000000U /*!< HCLK frequency to set FLASH latency 5 in power scale 1 */
20187
20188 #define FLASH_SCALE2_LATENCY1_FREQ 30000000U /*!< HCLK frequency to set FLASH latency 1 in power scale 2 */
20189 #define FLASH_SCALE2_LATENCY2_FREQ 60000000U /*!< HCLK frequency to set FLASH latency 2 in power scale 2 */
20190 #define FLASH_SCALE2_LATENCY3_FREQ 90000000U /*!< HCLK frequency to set FLASH latency 3 in power scale 2 */
20191 #define FLASH_SCALE2_LATENCY4_FREQ 12000000U /*!< HCLK frequency to set FLASH latency 4 in power scale 2 */
20192 #define FLASH_SCALE2_LATENCY5_FREQ 150000000U /*!< HCLK frequency to set FLASH latency 5 in power scale 2 */
20193
20194 #define FLASH_SCALE3_LATENCY1_FREQ 30000000U /*!< HCLK frequency to set FLASH latency 1 in power scale 3 */
20195 #define FLASH_SCALE3_LATENCY2_FREQ 60000000U /*!< HCLK frequency to set FLASH latency 2 in power scale 3 */
20196 #define FLASH_SCALE3_LATENCY3_FREQ 90000000U /*!< HCLK frequency to set FLASH latency 3 in power scale 3 */
20197
20198 /******************************************************************************/
20199 /* For a painless codes migration between the STM32F4xx device product */
20200 /* lines, the aliases defined below are put in place to overcome the */
20201 /* differences in the interrupt handlers and IRQn definitions. */
20202 /* No need to update developed interrupt code when moving across */
20203 /* product lines within the same STM32F4 Family */
20204 /******************************************************************************/
20205 /* Aliases for __IRQn */
20206 #define FSMC_IRQn FMC_IRQn
20207
20208 /* Aliases for __IRQHandler */
20209 #define FSMC_IRQHandler FMC_IRQHandler
20210
20211 /**
20212 * @}
20213 */
20214
20215 /**
20216 * @}
20217 */
20218
20219 /**
20220 * @}
20221 */
20222
20223 #ifdef __cplusplus
20224 }
20225 #endif /* __cplusplus */
20226
20227 #endif /* __STM32F469xx_H */
20228
20229
20230
20231 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/