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Added current STM32 standandard libraries in version independend folder structure
author Ideenmodellierer
date Sun, 17 Feb 2019 21:12:22 +0100
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127:1369f8660eaa 128:c78bcbd5deda
1 /**
2 ******************************************************************************
3 * @file stm32f4xx_ll_usart.c
4 * @author MCD Application Team
5 * @brief USART LL module driver.
6 ******************************************************************************
7 * @attention
8 *
9 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
10 *
11 * Redistribution and use in source and binary forms, with or without modification,
12 * are permitted provided that the following conditions are met:
13 * 1. Redistributions of source code must retain the above copyright notice,
14 * this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright notice,
16 * this list of conditions and the following disclaimer in the documentation
17 * and/or other materials provided with the distribution.
18 * 3. Neither the name of STMicroelectronics nor the names of its contributors
19 * may be used to endorse or promote products derived from this software
20 * without specific prior written permission.
21 *
22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
23 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
25 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
29 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32 *
33 ******************************************************************************
34 */
35 #if defined(USE_FULL_LL_DRIVER)
36
37 /* Includes ------------------------------------------------------------------*/
38 #include "stm32f4xx_ll_usart.h"
39 #include "stm32f4xx_ll_rcc.h"
40 #include "stm32f4xx_ll_bus.h"
41 #ifdef USE_FULL_ASSERT
42 #include "stm32_assert.h"
43 #else
44 #define assert_param(expr) ((void)0U)
45 #endif
46
47 /** @addtogroup STM32F4xx_LL_Driver
48 * @{
49 */
50
51 #if defined (USART1) || defined (USART2) || defined (USART3) || defined (USART6) || defined (UART4) || defined (UART5) || defined (UART7) || defined (UART8) || defined (UART9) || defined (UART10)
52
53 /** @addtogroup USART_LL
54 * @{
55 */
56
57 /* Private types -------------------------------------------------------------*/
58 /* Private variables ---------------------------------------------------------*/
59 /* Private constants ---------------------------------------------------------*/
60 /** @addtogroup USART_LL_Private_Constants
61 * @{
62 */
63
64 /**
65 * @}
66 */
67
68
69 /* Private macros ------------------------------------------------------------*/
70 /** @addtogroup USART_LL_Private_Macros
71 * @{
72 */
73
74 /* __BAUDRATE__ The maximum Baud Rate is derived from the maximum clock available
75 * divided by the smallest oversampling used on the USART (i.e. 8) */
76 #define IS_LL_USART_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) <= 12500000U)
77
78 /* __VALUE__ In case of oversampling by 16 and 8, BRR content must be greater than or equal to 16d. */
79 #define IS_LL_USART_BRR_MIN(__VALUE__) ((__VALUE__) >= 16U)
80
81 /* __VALUE__ BRR content must be lower than or equal to 0xFFFF. */
82 #define IS_LL_USART_BRR_MAX(__VALUE__) ((__VALUE__) <= 0x0000FFFFU)
83
84 #define IS_LL_USART_DIRECTION(__VALUE__) (((__VALUE__) == LL_USART_DIRECTION_NONE) \
85 || ((__VALUE__) == LL_USART_DIRECTION_RX) \
86 || ((__VALUE__) == LL_USART_DIRECTION_TX) \
87 || ((__VALUE__) == LL_USART_DIRECTION_TX_RX))
88
89 #define IS_LL_USART_PARITY(__VALUE__) (((__VALUE__) == LL_USART_PARITY_NONE) \
90 || ((__VALUE__) == LL_USART_PARITY_EVEN) \
91 || ((__VALUE__) == LL_USART_PARITY_ODD))
92
93 #define IS_LL_USART_DATAWIDTH(__VALUE__) (((__VALUE__) == LL_USART_DATAWIDTH_8B) \
94 || ((__VALUE__) == LL_USART_DATAWIDTH_9B))
95
96 #define IS_LL_USART_OVERSAMPLING(__VALUE__) (((__VALUE__) == LL_USART_OVERSAMPLING_16) \
97 || ((__VALUE__) == LL_USART_OVERSAMPLING_8))
98
99 #define IS_LL_USART_LASTBITCLKOUTPUT(__VALUE__) (((__VALUE__) == LL_USART_LASTCLKPULSE_NO_OUTPUT) \
100 || ((__VALUE__) == LL_USART_LASTCLKPULSE_OUTPUT))
101
102 #define IS_LL_USART_CLOCKPHASE(__VALUE__) (((__VALUE__) == LL_USART_PHASE_1EDGE) \
103 || ((__VALUE__) == LL_USART_PHASE_2EDGE))
104
105 #define IS_LL_USART_CLOCKPOLARITY(__VALUE__) (((__VALUE__) == LL_USART_POLARITY_LOW) \
106 || ((__VALUE__) == LL_USART_POLARITY_HIGH))
107
108 #define IS_LL_USART_CLOCKOUTPUT(__VALUE__) (((__VALUE__) == LL_USART_CLOCK_DISABLE) \
109 || ((__VALUE__) == LL_USART_CLOCK_ENABLE))
110
111 #define IS_LL_USART_STOPBITS(__VALUE__) (((__VALUE__) == LL_USART_STOPBITS_0_5) \
112 || ((__VALUE__) == LL_USART_STOPBITS_1) \
113 || ((__VALUE__) == LL_USART_STOPBITS_1_5) \
114 || ((__VALUE__) == LL_USART_STOPBITS_2))
115
116 #define IS_LL_USART_HWCONTROL(__VALUE__) (((__VALUE__) == LL_USART_HWCONTROL_NONE) \
117 || ((__VALUE__) == LL_USART_HWCONTROL_RTS) \
118 || ((__VALUE__) == LL_USART_HWCONTROL_CTS) \
119 || ((__VALUE__) == LL_USART_HWCONTROL_RTS_CTS))
120
121 /**
122 * @}
123 */
124
125 /* Private function prototypes -----------------------------------------------*/
126
127 /* Exported functions --------------------------------------------------------*/
128 /** @addtogroup USART_LL_Exported_Functions
129 * @{
130 */
131
132 /** @addtogroup USART_LL_EF_Init
133 * @{
134 */
135
136 /**
137 * @brief De-initialize USART registers (Registers restored to their default values).
138 * @param USARTx USART Instance
139 * @retval An ErrorStatus enumeration value:
140 * - SUCCESS: USART registers are de-initialized
141 * - ERROR: USART registers are not de-initialized
142 */
143 ErrorStatus LL_USART_DeInit(USART_TypeDef *USARTx)
144 {
145 ErrorStatus status = SUCCESS;
146
147 /* Check the parameters */
148 assert_param(IS_UART_INSTANCE(USARTx));
149
150 if (USARTx == USART1)
151 {
152 /* Force reset of USART clock */
153 LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_USART1);
154
155 /* Release reset of USART clock */
156 LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_USART1);
157 }
158 else if (USARTx == USART2)
159 {
160 /* Force reset of USART clock */
161 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_USART2);
162
163 /* Release reset of USART clock */
164 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_USART2);
165 }
166 #if defined(USART3)
167 else if (USARTx == USART3)
168 {
169 /* Force reset of USART clock */
170 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_USART3);
171
172 /* Release reset of USART clock */
173 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_USART3);
174 }
175 #endif /* USART3 */
176 #if defined(USART6)
177 else if (USARTx == USART6)
178 {
179 /* Force reset of USART clock */
180 LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_USART6);
181
182 /* Release reset of USART clock */
183 LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_USART6);
184 }
185 #endif /* USART6 */
186 #if defined(UART4)
187 else if (USARTx == UART4)
188 {
189 /* Force reset of UART clock */
190 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_UART4);
191
192 /* Release reset of UART clock */
193 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_UART4);
194 }
195 #endif /* UART4 */
196 #if defined(UART5)
197 else if (USARTx == UART5)
198 {
199 /* Force reset of UART clock */
200 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_UART5);
201
202 /* Release reset of UART clock */
203 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_UART5);
204 }
205 #endif /* UART5 */
206 #if defined(UART7)
207 else if (USARTx == UART7)
208 {
209 /* Force reset of UART clock */
210 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_UART7);
211
212 /* Release reset of UART clock */
213 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_UART7);
214 }
215 #endif /* UART7 */
216 #if defined(UART8)
217 else if (USARTx == UART8)
218 {
219 /* Force reset of UART clock */
220 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_UART8);
221
222 /* Release reset of UART clock */
223 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_UART8);
224 }
225 #endif /* UART8 */
226 #if defined(UART9)
227 else if (USARTx == UART9)
228 {
229 /* Force reset of UART clock */
230 LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_UART9);
231
232 /* Release reset of UART clock */
233 LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_UART9);
234 }
235 #endif /* UART9 */
236 #if defined(UART10)
237 else if (USARTx == UART10)
238 {
239 /* Force reset of UART clock */
240 LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_UART10);
241
242 /* Release reset of UART clock */
243 LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_UART10);
244 }
245 #endif /* UART10 */
246 else
247 {
248 status = ERROR;
249 }
250
251 return (status);
252 }
253
254 /**
255 * @brief Initialize USART registers according to the specified
256 * parameters in USART_InitStruct.
257 * @note As some bits in USART configuration registers can only be written when the USART is disabled (USART_CR1_UE bit =0),
258 * USART IP should be in disabled state prior calling this function. Otherwise, ERROR result will be returned.
259 * @note Baud rate value stored in USART_InitStruct BaudRate field, should be valid (different from 0).
260 * @param USARTx USART Instance
261 * @param USART_InitStruct pointer to a LL_USART_InitTypeDef structure
262 * that contains the configuration information for the specified USART peripheral.
263 * @retval An ErrorStatus enumeration value:
264 * - SUCCESS: USART registers are initialized according to USART_InitStruct content
265 * - ERROR: Problem occurred during USART Registers initialization
266 */
267 ErrorStatus LL_USART_Init(USART_TypeDef *USARTx, LL_USART_InitTypeDef *USART_InitStruct)
268 {
269 ErrorStatus status = ERROR;
270 uint32_t periphclk = LL_RCC_PERIPH_FREQUENCY_NO;
271 LL_RCC_ClocksTypeDef rcc_clocks;
272
273 /* Check the parameters */
274 assert_param(IS_UART_INSTANCE(USARTx));
275 assert_param(IS_LL_USART_BAUDRATE(USART_InitStruct->BaudRate));
276 assert_param(IS_LL_USART_DATAWIDTH(USART_InitStruct->DataWidth));
277 assert_param(IS_LL_USART_STOPBITS(USART_InitStruct->StopBits));
278 assert_param(IS_LL_USART_PARITY(USART_InitStruct->Parity));
279 assert_param(IS_LL_USART_DIRECTION(USART_InitStruct->TransferDirection));
280 assert_param(IS_LL_USART_HWCONTROL(USART_InitStruct->HardwareFlowControl));
281 assert_param(IS_LL_USART_OVERSAMPLING(USART_InitStruct->OverSampling));
282
283 /* USART needs to be in disabled state, in order to be able to configure some bits in
284 CRx registers */
285 if (LL_USART_IsEnabled(USARTx) == 0U)
286 {
287 /*---------------------------- USART CR1 Configuration -----------------------
288 * Configure USARTx CR1 (USART Word Length, Parity, Mode and Oversampling bits) with parameters:
289 * - DataWidth: USART_CR1_M bits according to USART_InitStruct->DataWidth value
290 * - Parity: USART_CR1_PCE, USART_CR1_PS bits according to USART_InitStruct->Parity value
291 * - TransferDirection: USART_CR1_TE, USART_CR1_RE bits according to USART_InitStruct->TransferDirection value
292 * - Oversampling: USART_CR1_OVER8 bit according to USART_InitStruct->OverSampling value.
293 */
294 MODIFY_REG(USARTx->CR1,
295 (USART_CR1_M | USART_CR1_PCE | USART_CR1_PS |
296 USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8),
297 (USART_InitStruct->DataWidth | USART_InitStruct->Parity |
298 USART_InitStruct->TransferDirection | USART_InitStruct->OverSampling));
299
300 /*---------------------------- USART CR2 Configuration -----------------------
301 * Configure USARTx CR2 (Stop bits) with parameters:
302 * - Stop Bits: USART_CR2_STOP bits according to USART_InitStruct->StopBits value.
303 * - CLKEN, CPOL, CPHA and LBCL bits are to be configured using LL_USART_ClockInit().
304 */
305 LL_USART_SetStopBitsLength(USARTx, USART_InitStruct->StopBits);
306
307 /*---------------------------- USART CR3 Configuration -----------------------
308 * Configure USARTx CR3 (Hardware Flow Control) with parameters:
309 * - HardwareFlowControl: USART_CR3_RTSE, USART_CR3_CTSE bits according to USART_InitStruct->HardwareFlowControl value.
310 */
311 LL_USART_SetHWFlowCtrl(USARTx, USART_InitStruct->HardwareFlowControl);
312
313 /*---------------------------- USART BRR Configuration -----------------------
314 * Retrieve Clock frequency used for USART Peripheral
315 */
316 LL_RCC_GetSystemClocksFreq(&rcc_clocks);
317 if (USARTx == USART1)
318 {
319 periphclk = rcc_clocks.PCLK2_Frequency;
320 }
321 else if (USARTx == USART2)
322 {
323 periphclk = rcc_clocks.PCLK1_Frequency;
324 }
325 #if defined(USART3)
326 else if (USARTx == USART3)
327 {
328 periphclk = rcc_clocks.PCLK1_Frequency;
329 }
330 #endif /* USART3 */
331 #if defined(USART6)
332 else if (USARTx == USART6)
333 {
334 periphclk = rcc_clocks.PCLK2_Frequency;
335 }
336 #endif /* USART6 */
337 #if defined(UART4)
338 else if (USARTx == UART4)
339 {
340 periphclk = rcc_clocks.PCLK1_Frequency;
341 }
342 #endif /* UART4 */
343 #if defined(UART5)
344 else if (USARTx == UART5)
345 {
346 periphclk = rcc_clocks.PCLK1_Frequency;
347 }
348 #endif /* UART5 */
349 #if defined(UART7)
350 else if (USARTx == UART7)
351 {
352 periphclk = rcc_clocks.PCLK1_Frequency;
353 }
354 #endif /* UART7 */
355 #if defined(UART8)
356 else if (USARTx == UART8)
357 {
358 periphclk = rcc_clocks.PCLK1_Frequency;
359 }
360 #endif /* UART8 */
361 #if defined(UART9)
362 else if (USARTx == UART9)
363 {
364 periphclk = rcc_clocks.PCLK1_Frequency;
365 }
366 #endif /* UART9 */
367 #if defined(UART10)
368 else if (USARTx == UART10)
369 {
370 periphclk = rcc_clocks.PCLK1_Frequency;
371 }
372 #endif /* UART10 */
373 else
374 {
375 /* Nothing to do, as error code is already assigned to ERROR value */
376 }
377
378 /* Configure the USART Baud Rate :
379 - valid baud rate value (different from 0) is required
380 - Peripheral clock as returned by RCC service, should be valid (different from 0).
381 */
382 if ((periphclk != LL_RCC_PERIPH_FREQUENCY_NO)
383 && (USART_InitStruct->BaudRate != 0U))
384 {
385 status = SUCCESS;
386 LL_USART_SetBaudRate(USARTx,
387 periphclk,
388 USART_InitStruct->OverSampling,
389 USART_InitStruct->BaudRate);
390
391 /* Check BRR is greater than or equal to 16d */
392 assert_param(IS_LL_USART_BRR_MIN(USARTx->BRR));
393
394 /* Check BRR is greater than or equal to 16d */
395 assert_param(IS_LL_USART_BRR_MAX(USARTx->BRR));
396 }
397 }
398 /* Endif (=> USART not in Disabled state => return ERROR) */
399
400 return (status);
401 }
402
403 /**
404 * @brief Set each @ref LL_USART_InitTypeDef field to default value.
405 * @param USART_InitStruct pointer to a @ref LL_USART_InitTypeDef structure
406 * whose fields will be set to default values.
407 * @retval None
408 */
409
410 void LL_USART_StructInit(LL_USART_InitTypeDef *USART_InitStruct)
411 {
412 /* Set USART_InitStruct fields to default values */
413 USART_InitStruct->BaudRate = 9600U;
414 USART_InitStruct->DataWidth = LL_USART_DATAWIDTH_8B;
415 USART_InitStruct->StopBits = LL_USART_STOPBITS_1;
416 USART_InitStruct->Parity = LL_USART_PARITY_NONE ;
417 USART_InitStruct->TransferDirection = LL_USART_DIRECTION_TX_RX;
418 USART_InitStruct->HardwareFlowControl = LL_USART_HWCONTROL_NONE;
419 USART_InitStruct->OverSampling = LL_USART_OVERSAMPLING_16;
420 }
421
422 /**
423 * @brief Initialize USART Clock related settings according to the
424 * specified parameters in the USART_ClockInitStruct.
425 * @note As some bits in USART configuration registers can only be written when the USART is disabled (USART_CR1_UE bit =0),
426 * USART IP should be in disabled state prior calling this function. Otherwise, ERROR result will be returned.
427 * @param USARTx USART Instance
428 * @param USART_ClockInitStruct pointer to a @ref LL_USART_ClockInitTypeDef structure
429 * that contains the Clock configuration information for the specified USART peripheral.
430 * @retval An ErrorStatus enumeration value:
431 * - SUCCESS: USART registers related to Clock settings are initialized according to USART_ClockInitStruct content
432 * - ERROR: Problem occurred during USART Registers initialization
433 */
434 ErrorStatus LL_USART_ClockInit(USART_TypeDef *USARTx, LL_USART_ClockInitTypeDef *USART_ClockInitStruct)
435 {
436 ErrorStatus status = SUCCESS;
437
438 /* Check USART Instance and Clock signal output parameters */
439 assert_param(IS_UART_INSTANCE(USARTx));
440 assert_param(IS_LL_USART_CLOCKOUTPUT(USART_ClockInitStruct->ClockOutput));
441
442 /* USART needs to be in disabled state, in order to be able to configure some bits in
443 CRx registers */
444 if (LL_USART_IsEnabled(USARTx) == 0U)
445 {
446 /*---------------------------- USART CR2 Configuration -----------------------*/
447 /* If Clock signal has to be output */
448 if (USART_ClockInitStruct->ClockOutput == LL_USART_CLOCK_DISABLE)
449 {
450 /* Deactivate Clock signal delivery :
451 * - Disable Clock Output: USART_CR2_CLKEN cleared
452 */
453 LL_USART_DisableSCLKOutput(USARTx);
454 }
455 else
456 {
457 /* Ensure USART instance is USART capable */
458 assert_param(IS_USART_INSTANCE(USARTx));
459
460 /* Check clock related parameters */
461 assert_param(IS_LL_USART_CLOCKPOLARITY(USART_ClockInitStruct->ClockPolarity));
462 assert_param(IS_LL_USART_CLOCKPHASE(USART_ClockInitStruct->ClockPhase));
463 assert_param(IS_LL_USART_LASTBITCLKOUTPUT(USART_ClockInitStruct->LastBitClockPulse));
464
465 /*---------------------------- USART CR2 Configuration -----------------------
466 * Configure USARTx CR2 (Clock signal related bits) with parameters:
467 * - Enable Clock Output: USART_CR2_CLKEN set
468 * - Clock Polarity: USART_CR2_CPOL bit according to USART_ClockInitStruct->ClockPolarity value
469 * - Clock Phase: USART_CR2_CPHA bit according to USART_ClockInitStruct->ClockPhase value
470 * - Last Bit Clock Pulse Output: USART_CR2_LBCL bit according to USART_ClockInitStruct->LastBitClockPulse value.
471 */
472 MODIFY_REG(USARTx->CR2,
473 USART_CR2_CLKEN | USART_CR2_CPHA | USART_CR2_CPOL | USART_CR2_LBCL,
474 USART_CR2_CLKEN | USART_ClockInitStruct->ClockPolarity |
475 USART_ClockInitStruct->ClockPhase | USART_ClockInitStruct->LastBitClockPulse);
476 }
477 }
478 /* Else (USART not in Disabled state => return ERROR */
479 else
480 {
481 status = ERROR;
482 }
483
484 return (status);
485 }
486
487 /**
488 * @brief Set each field of a @ref LL_USART_ClockInitTypeDef type structure to default value.
489 * @param USART_ClockInitStruct pointer to a @ref LL_USART_ClockInitTypeDef structure
490 * whose fields will be set to default values.
491 * @retval None
492 */
493 void LL_USART_ClockStructInit(LL_USART_ClockInitTypeDef *USART_ClockInitStruct)
494 {
495 /* Set LL_USART_ClockInitStruct fields with default values */
496 USART_ClockInitStruct->ClockOutput = LL_USART_CLOCK_DISABLE;
497 USART_ClockInitStruct->ClockPolarity = LL_USART_POLARITY_LOW; /* Not relevant when ClockOutput = LL_USART_CLOCK_DISABLE */
498 USART_ClockInitStruct->ClockPhase = LL_USART_PHASE_1EDGE; /* Not relevant when ClockOutput = LL_USART_CLOCK_DISABLE */
499 USART_ClockInitStruct->LastBitClockPulse = LL_USART_LASTCLKPULSE_NO_OUTPUT; /* Not relevant when ClockOutput = LL_USART_CLOCK_DISABLE */
500 }
501
502 /**
503 * @}
504 */
505
506 /**
507 * @}
508 */
509
510 /**
511 * @}
512 */
513
514 #endif /* USART1 || USART2 || USART3 || USART6 || UART4 || UART5 || UART7 || UART8 || UART9 || UART10 */
515
516 /**
517 * @}
518 */
519
520 #endif /* USE_FULL_LL_DRIVER */
521
522 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
523