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Added current STM32 standandard libraries in version independend folder structure
author Ideenmodellierer
date Sun, 17 Feb 2019 21:12:22 +0100
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127:1369f8660eaa 128:c78bcbd5deda
1 /**
2 ******************************************************************************
3 * @file stm32f4xx_ll_tim.c
4 * @author MCD Application Team
5 * @brief TIM LL module driver.
6 ******************************************************************************
7 * @attention
8 *
9 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
10 *
11 * Redistribution and use in source and binary forms, with or without modification,
12 * are permitted provided that the following conditions are met:
13 * 1. Redistributions of source code must retain the above copyright notice,
14 * this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright notice,
16 * this list of conditions and the following disclaimer in the documentation
17 * and/or other materials provided with the distribution.
18 * 3. Neither the name of STMicroelectronics nor the names of its contributors
19 * may be used to endorse or promote products derived from this software
20 * without specific prior written permission.
21 *
22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
23 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
25 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
29 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32 *
33 ******************************************************************************
34 */
35 #if defined(USE_FULL_LL_DRIVER)
36
37 /* Includes ------------------------------------------------------------------*/
38 #include "stm32f4xx_ll_tim.h"
39 #include "stm32f4xx_ll_bus.h"
40
41 #ifdef USE_FULL_ASSERT
42 #include "stm32_assert.h"
43 #else
44 #define assert_param(expr) ((void)0U)
45 #endif
46
47 /** @addtogroup STM32F4xx_LL_Driver
48 * @{
49 */
50
51 #if defined (TIM1) || defined (TIM2) || defined (TIM3) || defined (TIM4) || defined (TIM5) || defined (TIM6) || defined (TIM7) || defined (TIM8) || defined (TIM9) || defined (TIM10) || defined (TIM11) || defined (TIM12) || defined (TIM13) || defined (TIM14)
52
53 /** @addtogroup TIM_LL
54 * @{
55 */
56
57 /* Private types -------------------------------------------------------------*/
58 /* Private variables ---------------------------------------------------------*/
59 /* Private constants ---------------------------------------------------------*/
60 /* Private macros ------------------------------------------------------------*/
61 /** @addtogroup TIM_LL_Private_Macros
62 * @{
63 */
64 #define IS_LL_TIM_COUNTERMODE(__VALUE__) (((__VALUE__) == LL_TIM_COUNTERMODE_UP) \
65 || ((__VALUE__) == LL_TIM_COUNTERMODE_DOWN) \
66 || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_UP) \
67 || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_DOWN) \
68 || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_UP_DOWN))
69
70 #define IS_LL_TIM_CLOCKDIVISION(__VALUE__) (((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV1) \
71 || ((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV2) \
72 || ((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV4))
73
74 #define IS_LL_TIM_OCMODE(__VALUE__) (((__VALUE__) == LL_TIM_OCMODE_FROZEN) \
75 || ((__VALUE__) == LL_TIM_OCMODE_ACTIVE) \
76 || ((__VALUE__) == LL_TIM_OCMODE_INACTIVE) \
77 || ((__VALUE__) == LL_TIM_OCMODE_TOGGLE) \
78 || ((__VALUE__) == LL_TIM_OCMODE_FORCED_INACTIVE) \
79 || ((__VALUE__) == LL_TIM_OCMODE_FORCED_ACTIVE) \
80 || ((__VALUE__) == LL_TIM_OCMODE_PWM1) \
81 || ((__VALUE__) == LL_TIM_OCMODE_PWM2))
82
83 #define IS_LL_TIM_OCSTATE(__VALUE__) (((__VALUE__) == LL_TIM_OCSTATE_DISABLE) \
84 || ((__VALUE__) == LL_TIM_OCSTATE_ENABLE))
85
86 #define IS_LL_TIM_OCPOLARITY(__VALUE__) (((__VALUE__) == LL_TIM_OCPOLARITY_HIGH) \
87 || ((__VALUE__) == LL_TIM_OCPOLARITY_LOW))
88
89 #define IS_LL_TIM_OCIDLESTATE(__VALUE__) (((__VALUE__) == LL_TIM_OCIDLESTATE_LOW) \
90 || ((__VALUE__) == LL_TIM_OCIDLESTATE_HIGH))
91
92 #define IS_LL_TIM_ACTIVEINPUT(__VALUE__) (((__VALUE__) == LL_TIM_ACTIVEINPUT_DIRECTTI) \
93 || ((__VALUE__) == LL_TIM_ACTIVEINPUT_INDIRECTTI) \
94 || ((__VALUE__) == LL_TIM_ACTIVEINPUT_TRC))
95
96 #define IS_LL_TIM_ICPSC(__VALUE__) (((__VALUE__) == LL_TIM_ICPSC_DIV1) \
97 || ((__VALUE__) == LL_TIM_ICPSC_DIV2) \
98 || ((__VALUE__) == LL_TIM_ICPSC_DIV4) \
99 || ((__VALUE__) == LL_TIM_ICPSC_DIV8))
100
101 #define IS_LL_TIM_IC_FILTER(__VALUE__) (((__VALUE__) == LL_TIM_IC_FILTER_FDIV1) \
102 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N2) \
103 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N4) \
104 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N8) \
105 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV2_N6) \
106 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV2_N8) \
107 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV4_N6) \
108 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV4_N8) \
109 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV8_N6) \
110 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV8_N8) \
111 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N5) \
112 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N6) \
113 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N8) \
114 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N5) \
115 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N6) \
116 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N8))
117
118 #define IS_LL_TIM_IC_POLARITY(__VALUE__) (((__VALUE__) == LL_TIM_IC_POLARITY_RISING) \
119 || ((__VALUE__) == LL_TIM_IC_POLARITY_FALLING) \
120 || ((__VALUE__) == LL_TIM_IC_POLARITY_BOTHEDGE))
121
122 #define IS_LL_TIM_ENCODERMODE(__VALUE__) (((__VALUE__) == LL_TIM_ENCODERMODE_X2_TI1) \
123 || ((__VALUE__) == LL_TIM_ENCODERMODE_X2_TI2) \
124 || ((__VALUE__) == LL_TIM_ENCODERMODE_X4_TI12))
125
126 #define IS_LL_TIM_IC_POLARITY_ENCODER(__VALUE__) (((__VALUE__) == LL_TIM_IC_POLARITY_RISING) \
127 || ((__VALUE__) == LL_TIM_IC_POLARITY_FALLING))
128
129 #define IS_LL_TIM_OSSR_STATE(__VALUE__) (((__VALUE__) == LL_TIM_OSSR_DISABLE) \
130 || ((__VALUE__) == LL_TIM_OSSR_ENABLE))
131
132 #define IS_LL_TIM_OSSI_STATE(__VALUE__) (((__VALUE__) == LL_TIM_OSSI_DISABLE) \
133 || ((__VALUE__) == LL_TIM_OSSI_ENABLE))
134
135 #define IS_LL_TIM_LOCK_LEVEL(__VALUE__) (((__VALUE__) == LL_TIM_LOCKLEVEL_OFF) \
136 || ((__VALUE__) == LL_TIM_LOCKLEVEL_1) \
137 || ((__VALUE__) == LL_TIM_LOCKLEVEL_2) \
138 || ((__VALUE__) == LL_TIM_LOCKLEVEL_3))
139
140 #define IS_LL_TIM_BREAK_STATE(__VALUE__) (((__VALUE__) == LL_TIM_BREAK_DISABLE) \
141 || ((__VALUE__) == LL_TIM_BREAK_ENABLE))
142
143 #define IS_LL_TIM_BREAK_POLARITY(__VALUE__) (((__VALUE__) == LL_TIM_BREAK_POLARITY_LOW) \
144 || ((__VALUE__) == LL_TIM_BREAK_POLARITY_HIGH))
145
146 #define IS_LL_TIM_AUTOMATIC_OUTPUT_STATE(__VALUE__) (((__VALUE__) == LL_TIM_AUTOMATICOUTPUT_DISABLE) \
147 || ((__VALUE__) == LL_TIM_AUTOMATICOUTPUT_ENABLE))
148 /**
149 * @}
150 */
151
152
153 /* Private function prototypes -----------------------------------------------*/
154 /** @defgroup TIM_LL_Private_Functions TIM Private Functions
155 * @{
156 */
157 static ErrorStatus OC1Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
158 static ErrorStatus OC2Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
159 static ErrorStatus OC3Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
160 static ErrorStatus OC4Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
161 static ErrorStatus IC1Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
162 static ErrorStatus IC2Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
163 static ErrorStatus IC3Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
164 static ErrorStatus IC4Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
165 /**
166 * @}
167 */
168
169 /* Exported functions --------------------------------------------------------*/
170 /** @addtogroup TIM_LL_Exported_Functions
171 * @{
172 */
173
174 /** @addtogroup TIM_LL_EF_Init
175 * @{
176 */
177
178 /**
179 * @brief Set TIMx registers to their reset values.
180 * @param TIMx Timer instance
181 * @retval An ErrorStatus enumeration value:
182 * - SUCCESS: TIMx registers are de-initialized
183 * - ERROR: invalid TIMx instance
184 */
185 ErrorStatus LL_TIM_DeInit(TIM_TypeDef *TIMx)
186 {
187 ErrorStatus result = SUCCESS;
188
189 /* Check the parameters */
190 assert_param(IS_TIM_INSTANCE(TIMx));
191
192 if (TIMx == TIM1)
193 {
194 LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM1);
195 LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM1);
196 }
197 #if defined(TIM2)
198 else if (TIMx == TIM2)
199 {
200 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM2);
201 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM2);
202 }
203 #endif
204 #if defined(TIM3)
205 else if (TIMx == TIM3)
206 {
207 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM3);
208 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM3);
209 }
210 #endif
211 #if defined(TIM4)
212 else if (TIMx == TIM4)
213 {
214 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM4);
215 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM4);
216 }
217 #endif
218 #if defined(TIM5)
219 else if (TIMx == TIM5)
220 {
221 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM5);
222 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM5);
223 }
224 #endif
225 #if defined(TIM6)
226 else if (TIMx == TIM6)
227 {
228 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM6);
229 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM6);
230 }
231 #endif
232 #if defined (TIM7)
233 else if (TIMx == TIM7)
234 {
235 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM7);
236 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM7);
237 }
238 #endif
239 #if defined(TIM8)
240 else if (TIMx == TIM8)
241 {
242 LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM8);
243 LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM8);
244 }
245 #endif
246 #if defined(TIM9)
247 else if (TIMx == TIM9)
248 {
249 LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM9);
250 LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM9);
251 }
252 #endif
253 #if defined(TIM10)
254 else if (TIMx == TIM10)
255 {
256 LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM10);
257 LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM10);
258 }
259 #endif
260 #if defined(TIM11)
261 else if (TIMx == TIM11)
262 {
263 LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM11);
264 LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM11);
265 }
266 #endif
267 #if defined(TIM12)
268 else if (TIMx == TIM12)
269 {
270 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM12);
271 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM12);
272 }
273 #endif
274 #if defined(TIM13)
275 else if (TIMx == TIM13)
276 {
277 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM13);
278 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM13);
279 }
280 #endif
281 #if defined(TIM14)
282 else if (TIMx == TIM14)
283 {
284 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM14);
285 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM14);
286 }
287 #endif
288 else
289 {
290 result = ERROR;
291 }
292
293 return result;
294 }
295
296 /**
297 * @brief Set the fields of the time base unit configuration data structure
298 * to their default values.
299 * @param TIM_InitStruct pointer to a @ref LL_TIM_InitTypeDef structure (time base unit configuration data structure)
300 * @retval None
301 */
302 void LL_TIM_StructInit(LL_TIM_InitTypeDef *TIM_InitStruct)
303 {
304 /* Set the default configuration */
305 TIM_InitStruct->Prescaler = (uint16_t)0x0000U;
306 TIM_InitStruct->CounterMode = LL_TIM_COUNTERMODE_UP;
307 TIM_InitStruct->Autoreload = 0xFFFFFFFFU;
308 TIM_InitStruct->ClockDivision = LL_TIM_CLOCKDIVISION_DIV1;
309 TIM_InitStruct->RepetitionCounter = (uint8_t)0x00U;
310 }
311
312 /**
313 * @brief Configure the TIMx time base unit.
314 * @param TIMx Timer Instance
315 * @param TIM_InitStruct pointer to a @ref LL_TIM_InitTypeDef structure (TIMx time base unit configuration data structure)
316 * @retval An ErrorStatus enumeration value:
317 * - SUCCESS: TIMx registers are de-initialized
318 * - ERROR: not applicable
319 */
320 ErrorStatus LL_TIM_Init(TIM_TypeDef *TIMx, LL_TIM_InitTypeDef *TIM_InitStruct)
321 {
322 uint32_t tmpcr1 = 0U;
323
324 /* Check the parameters */
325 assert_param(IS_TIM_INSTANCE(TIMx));
326 assert_param(IS_LL_TIM_COUNTERMODE(TIM_InitStruct->CounterMode));
327 assert_param(IS_LL_TIM_CLOCKDIVISION(TIM_InitStruct->ClockDivision));
328
329 tmpcr1 = LL_TIM_ReadReg(TIMx, CR1);
330
331 if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
332 {
333 /* Select the Counter Mode */
334 MODIFY_REG(tmpcr1, (TIM_CR1_DIR | TIM_CR1_CMS), TIM_InitStruct->CounterMode);
335 }
336
337 if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx))
338 {
339 /* Set the clock division */
340 MODIFY_REG(tmpcr1, TIM_CR1_CKD, TIM_InitStruct->ClockDivision);
341 }
342
343 /* Write to TIMx CR1 */
344 LL_TIM_WriteReg(TIMx, CR1, tmpcr1);
345
346 /* Set the Autoreload value */
347 LL_TIM_SetAutoReload(TIMx, TIM_InitStruct->Autoreload);
348
349 /* Set the Prescaler value */
350 LL_TIM_SetPrescaler(TIMx, TIM_InitStruct->Prescaler);
351
352 if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx))
353 {
354 /* Set the Repetition Counter value */
355 LL_TIM_SetRepetitionCounter(TIMx, TIM_InitStruct->RepetitionCounter);
356 }
357
358 /* Generate an update event to reload the Prescaler
359 and the repetition counter value (if applicable) immediately */
360 LL_TIM_GenerateEvent_UPDATE(TIMx);
361
362 return SUCCESS;
363 }
364
365 /**
366 * @brief Set the fields of the TIMx output channel configuration data
367 * structure to their default values.
368 * @param TIM_OC_InitStruct pointer to a @ref LL_TIM_OC_InitTypeDef structure (the output channel configuration data structure)
369 * @retval None
370 */
371 void LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct)
372 {
373 /* Set the default configuration */
374 TIM_OC_InitStruct->OCMode = LL_TIM_OCMODE_FROZEN;
375 TIM_OC_InitStruct->OCState = LL_TIM_OCSTATE_DISABLE;
376 TIM_OC_InitStruct->OCNState = LL_TIM_OCSTATE_DISABLE;
377 TIM_OC_InitStruct->CompareValue = 0x00000000U;
378 TIM_OC_InitStruct->OCPolarity = LL_TIM_OCPOLARITY_HIGH;
379 TIM_OC_InitStruct->OCNPolarity = LL_TIM_OCPOLARITY_HIGH;
380 TIM_OC_InitStruct->OCIdleState = LL_TIM_OCIDLESTATE_LOW;
381 TIM_OC_InitStruct->OCNIdleState = LL_TIM_OCIDLESTATE_LOW;
382 }
383
384 /**
385 * @brief Configure the TIMx output channel.
386 * @param TIMx Timer Instance
387 * @param Channel This parameter can be one of the following values:
388 * @arg @ref LL_TIM_CHANNEL_CH1
389 * @arg @ref LL_TIM_CHANNEL_CH2
390 * @arg @ref LL_TIM_CHANNEL_CH3
391 * @arg @ref LL_TIM_CHANNEL_CH4
392 * @param TIM_OC_InitStruct pointer to a @ref LL_TIM_OC_InitTypeDef structure (TIMx output channel configuration data structure)
393 * @retval An ErrorStatus enumeration value:
394 * - SUCCESS: TIMx output channel is initialized
395 * - ERROR: TIMx output channel is not initialized
396 */
397 ErrorStatus LL_TIM_OC_Init(TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct)
398 {
399 ErrorStatus result = ERROR;
400
401 switch (Channel)
402 {
403 case LL_TIM_CHANNEL_CH1:
404 result = OC1Config(TIMx, TIM_OC_InitStruct);
405 break;
406 case LL_TIM_CHANNEL_CH2:
407 result = OC2Config(TIMx, TIM_OC_InitStruct);
408 break;
409 case LL_TIM_CHANNEL_CH3:
410 result = OC3Config(TIMx, TIM_OC_InitStruct);
411 break;
412 case LL_TIM_CHANNEL_CH4:
413 result = OC4Config(TIMx, TIM_OC_InitStruct);
414 break;
415 default:
416 break;
417 }
418
419 return result;
420 }
421
422 /**
423 * @brief Set the fields of the TIMx input channel configuration data
424 * structure to their default values.
425 * @param TIM_ICInitStruct pointer to a @ref LL_TIM_IC_InitTypeDef structure (the input channel configuration data structure)
426 * @retval None
427 */
428 void LL_TIM_IC_StructInit(LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
429 {
430 /* Set the default configuration */
431 TIM_ICInitStruct->ICPolarity = LL_TIM_IC_POLARITY_RISING;
432 TIM_ICInitStruct->ICActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI;
433 TIM_ICInitStruct->ICPrescaler = LL_TIM_ICPSC_DIV1;
434 TIM_ICInitStruct->ICFilter = LL_TIM_IC_FILTER_FDIV1;
435 }
436
437 /**
438 * @brief Configure the TIMx input channel.
439 * @param TIMx Timer Instance
440 * @param Channel This parameter can be one of the following values:
441 * @arg @ref LL_TIM_CHANNEL_CH1
442 * @arg @ref LL_TIM_CHANNEL_CH2
443 * @arg @ref LL_TIM_CHANNEL_CH3
444 * @arg @ref LL_TIM_CHANNEL_CH4
445 * @param TIM_IC_InitStruct pointer to a @ref LL_TIM_IC_InitTypeDef structure (TIMx input channel configuration data structure)
446 * @retval An ErrorStatus enumeration value:
447 * - SUCCESS: TIMx output channel is initialized
448 * - ERROR: TIMx output channel is not initialized
449 */
450 ErrorStatus LL_TIM_IC_Init(TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_IC_InitTypeDef *TIM_IC_InitStruct)
451 {
452 ErrorStatus result = ERROR;
453
454 switch (Channel)
455 {
456 case LL_TIM_CHANNEL_CH1:
457 result = IC1Config(TIMx, TIM_IC_InitStruct);
458 break;
459 case LL_TIM_CHANNEL_CH2:
460 result = IC2Config(TIMx, TIM_IC_InitStruct);
461 break;
462 case LL_TIM_CHANNEL_CH3:
463 result = IC3Config(TIMx, TIM_IC_InitStruct);
464 break;
465 case LL_TIM_CHANNEL_CH4:
466 result = IC4Config(TIMx, TIM_IC_InitStruct);
467 break;
468 default:
469 break;
470 }
471
472 return result;
473 }
474
475 /**
476 * @brief Fills each TIM_EncoderInitStruct field with its default value
477 * @param TIM_EncoderInitStruct pointer to a @ref LL_TIM_ENCODER_InitTypeDef structure (encoder interface configuration data structure)
478 * @retval None
479 */
480 void LL_TIM_ENCODER_StructInit(LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct)
481 {
482 /* Set the default configuration */
483 TIM_EncoderInitStruct->EncoderMode = LL_TIM_ENCODERMODE_X2_TI1;
484 TIM_EncoderInitStruct->IC1Polarity = LL_TIM_IC_POLARITY_RISING;
485 TIM_EncoderInitStruct->IC1ActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI;
486 TIM_EncoderInitStruct->IC1Prescaler = LL_TIM_ICPSC_DIV1;
487 TIM_EncoderInitStruct->IC1Filter = LL_TIM_IC_FILTER_FDIV1;
488 TIM_EncoderInitStruct->IC2Polarity = LL_TIM_IC_POLARITY_RISING;
489 TIM_EncoderInitStruct->IC2ActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI;
490 TIM_EncoderInitStruct->IC2Prescaler = LL_TIM_ICPSC_DIV1;
491 TIM_EncoderInitStruct->IC2Filter = LL_TIM_IC_FILTER_FDIV1;
492 }
493
494 /**
495 * @brief Configure the encoder interface of the timer instance.
496 * @param TIMx Timer Instance
497 * @param TIM_EncoderInitStruct pointer to a @ref LL_TIM_ENCODER_InitTypeDef structure (TIMx encoder interface configuration data structure)
498 * @retval An ErrorStatus enumeration value:
499 * - SUCCESS: TIMx registers are de-initialized
500 * - ERROR: not applicable
501 */
502 ErrorStatus LL_TIM_ENCODER_Init(TIM_TypeDef *TIMx, LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct)
503 {
504 uint32_t tmpccmr1 = 0U;
505 uint32_t tmpccer = 0U;
506
507 /* Check the parameters */
508 assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(TIMx));
509 assert_param(IS_LL_TIM_ENCODERMODE(TIM_EncoderInitStruct->EncoderMode));
510 assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_EncoderInitStruct->IC1Polarity));
511 assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_EncoderInitStruct->IC1ActiveInput));
512 assert_param(IS_LL_TIM_ICPSC(TIM_EncoderInitStruct->IC1Prescaler));
513 assert_param(IS_LL_TIM_IC_FILTER(TIM_EncoderInitStruct->IC1Filter));
514 assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_EncoderInitStruct->IC2Polarity));
515 assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_EncoderInitStruct->IC2ActiveInput));
516 assert_param(IS_LL_TIM_ICPSC(TIM_EncoderInitStruct->IC2Prescaler));
517 assert_param(IS_LL_TIM_IC_FILTER(TIM_EncoderInitStruct->IC2Filter));
518
519 /* Disable the CC1 and CC2: Reset the CC1E and CC2E Bits */
520 TIMx->CCER &= (uint32_t)~(TIM_CCER_CC1E | TIM_CCER_CC2E);
521
522 /* Get the TIMx CCMR1 register value */
523 tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
524
525 /* Get the TIMx CCER register value */
526 tmpccer = LL_TIM_ReadReg(TIMx, CCER);
527
528 /* Configure TI1 */
529 tmpccmr1 &= (uint32_t)~(TIM_CCMR1_CC1S | TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC);
530 tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1ActiveInput >> 16U);
531 tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1Filter >> 16U);
532 tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1Prescaler >> 16U);
533
534 /* Configure TI2 */
535 tmpccmr1 &= (uint32_t)~(TIM_CCMR1_CC2S | TIM_CCMR1_IC2F | TIM_CCMR1_IC2PSC);
536 tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2ActiveInput >> 8U);
537 tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2Filter >> 8U);
538 tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2Prescaler >> 8U);
539
540 /* Set TI1 and TI2 polarity and enable TI1 and TI2 */
541 tmpccer &= (uint32_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP | TIM_CCER_CC2P | TIM_CCER_CC2NP);
542 tmpccer |= (uint32_t)(TIM_EncoderInitStruct->IC1Polarity);
543 tmpccer |= (uint32_t)(TIM_EncoderInitStruct->IC2Polarity << 4U);
544 tmpccer |= (uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E);
545
546 /* Set encoder mode */
547 LL_TIM_SetEncoderMode(TIMx, TIM_EncoderInitStruct->EncoderMode);
548
549 /* Write to TIMx CCMR1 */
550 LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
551
552 /* Write to TIMx CCER */
553 LL_TIM_WriteReg(TIMx, CCER, tmpccer);
554
555 return SUCCESS;
556 }
557
558 /**
559 * @brief Set the fields of the TIMx Hall sensor interface configuration data
560 * structure to their default values.
561 * @param TIM_HallSensorInitStruct pointer to a @ref LL_TIM_HALLSENSOR_InitTypeDef structure (HALL sensor interface configuration data structure)
562 * @retval None
563 */
564 void LL_TIM_HALLSENSOR_StructInit(LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct)
565 {
566 /* Set the default configuration */
567 TIM_HallSensorInitStruct->IC1Polarity = LL_TIM_IC_POLARITY_RISING;
568 TIM_HallSensorInitStruct->IC1Prescaler = LL_TIM_ICPSC_DIV1;
569 TIM_HallSensorInitStruct->IC1Filter = LL_TIM_IC_FILTER_FDIV1;
570 TIM_HallSensorInitStruct->CommutationDelay = 0U;
571 }
572
573 /**
574 * @brief Configure the Hall sensor interface of the timer instance.
575 * @note TIMx CH1, CH2 and CH3 inputs connected through a XOR
576 * to the TI1 input channel
577 * @note TIMx slave mode controller is configured in reset mode.
578 Selected internal trigger is TI1F_ED.
579 * @note Channel 1 is configured as input, IC1 is mapped on TRC.
580 * @note Captured value stored in TIMx_CCR1 correspond to the time elapsed
581 * between 2 changes on the inputs. It gives information about motor speed.
582 * @note Channel 2 is configured in output PWM 2 mode.
583 * @note Compare value stored in TIMx_CCR2 corresponds to the commutation delay.
584 * @note OC2REF is selected as trigger output on TRGO.
585 * @note LL_TIM_IC_POLARITY_BOTHEDGE must not be used for TI1 when it is used
586 * when TIMx operates in Hall sensor interface mode.
587 * @param TIMx Timer Instance
588 * @param TIM_HallSensorInitStruct pointer to a @ref LL_TIM_HALLSENSOR_InitTypeDef structure (TIMx HALL sensor interface configuration data structure)
589 * @retval An ErrorStatus enumeration value:
590 * - SUCCESS: TIMx registers are de-initialized
591 * - ERROR: not applicable
592 */
593 ErrorStatus LL_TIM_HALLSENSOR_Init(TIM_TypeDef *TIMx, LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct)
594 {
595 uint32_t tmpcr2 = 0U;
596 uint32_t tmpccmr1 = 0U;
597 uint32_t tmpccer = 0U;
598 uint32_t tmpsmcr = 0U;
599
600 /* Check the parameters */
601 assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(TIMx));
602 assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_HallSensorInitStruct->IC1Polarity));
603 assert_param(IS_LL_TIM_ICPSC(TIM_HallSensorInitStruct->IC1Prescaler));
604 assert_param(IS_LL_TIM_IC_FILTER(TIM_HallSensorInitStruct->IC1Filter));
605
606 /* Disable the CC1 and CC2: Reset the CC1E and CC2E Bits */
607 TIMx->CCER &= (uint32_t)~(TIM_CCER_CC1E | TIM_CCER_CC2E);
608
609 /* Get the TIMx CR2 register value */
610 tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
611
612 /* Get the TIMx CCMR1 register value */
613 tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
614
615 /* Get the TIMx CCER register value */
616 tmpccer = LL_TIM_ReadReg(TIMx, CCER);
617
618 /* Get the TIMx SMCR register value */
619 tmpsmcr = LL_TIM_ReadReg(TIMx, SMCR);
620
621 /* Connect TIMx_CH1, CH2 and CH3 pins to the TI1 input */
622 tmpcr2 |= TIM_CR2_TI1S;
623
624 /* OC2REF signal is used as trigger output (TRGO) */
625 tmpcr2 |= LL_TIM_TRGO_OC2REF;
626
627 /* Configure the slave mode controller */
628 tmpsmcr &= (uint32_t)~(TIM_SMCR_TS | TIM_SMCR_SMS);
629 tmpsmcr |= LL_TIM_TS_TI1F_ED;
630 tmpsmcr |= LL_TIM_SLAVEMODE_RESET;
631
632 /* Configure input channel 1 */
633 tmpccmr1 &= (uint32_t)~(TIM_CCMR1_CC1S | TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC);
634 tmpccmr1 |= (uint32_t)(LL_TIM_ACTIVEINPUT_TRC >> 16U);
635 tmpccmr1 |= (uint32_t)(TIM_HallSensorInitStruct->IC1Filter >> 16U);
636 tmpccmr1 |= (uint32_t)(TIM_HallSensorInitStruct->IC1Prescaler >> 16U);
637
638 /* Configure input channel 2 */
639 tmpccmr1 &= (uint32_t)~(TIM_CCMR1_OC2M | TIM_CCMR1_OC2FE | TIM_CCMR1_OC2PE | TIM_CCMR1_OC2CE);
640 tmpccmr1 |= (uint32_t)(LL_TIM_OCMODE_PWM2 << 8U);
641
642 /* Set Channel 1 polarity and enable Channel 1 and Channel2 */
643 tmpccer &= (uint32_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP | TIM_CCER_CC2P | TIM_CCER_CC2NP);
644 tmpccer |= (uint32_t)(TIM_HallSensorInitStruct->IC1Polarity);
645 tmpccer |= (uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E);
646
647 /* Write to TIMx CR2 */
648 LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
649
650 /* Write to TIMx SMCR */
651 LL_TIM_WriteReg(TIMx, SMCR, tmpsmcr);
652
653 /* Write to TIMx CCMR1 */
654 LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
655
656 /* Write to TIMx CCER */
657 LL_TIM_WriteReg(TIMx, CCER, tmpccer);
658
659 /* Write to TIMx CCR2 */
660 LL_TIM_OC_SetCompareCH2(TIMx, TIM_HallSensorInitStruct->CommutationDelay);
661
662 return SUCCESS;
663 }
664
665 /**
666 * @brief Set the fields of the Break and Dead Time configuration data structure
667 * to their default values.
668 * @param TIM_BDTRInitStruct pointer to a @ref LL_TIM_BDTR_InitTypeDef structure (Break and Dead Time configuration data structure)
669 * @retval None
670 */
671 void LL_TIM_BDTR_StructInit(LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct)
672 {
673 /* Set the default configuration */
674 TIM_BDTRInitStruct->OSSRState = LL_TIM_OSSR_DISABLE;
675 TIM_BDTRInitStruct->OSSIState = LL_TIM_OSSI_DISABLE;
676 TIM_BDTRInitStruct->LockLevel = LL_TIM_LOCKLEVEL_OFF;
677 TIM_BDTRInitStruct->DeadTime = (uint8_t)0x00U;
678 TIM_BDTRInitStruct->BreakState = LL_TIM_BREAK_DISABLE;
679 TIM_BDTRInitStruct->BreakPolarity = LL_TIM_BREAK_POLARITY_LOW;
680 TIM_BDTRInitStruct->AutomaticOutput = LL_TIM_AUTOMATICOUTPUT_DISABLE;
681 }
682
683 /**
684 * @brief Configure the Break and Dead Time feature of the timer instance.
685 * @note As the bits AOE, BKP, BKE, OSSR, OSSI and DTG[7:0] can be write-locked
686 * depending on the LOCK configuration, it can be necessary to configure all of
687 * them during the first write access to the TIMx_BDTR register.
688 * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
689 * a timer instance provides a break input.
690 * @param TIMx Timer Instance
691 * @param TIM_BDTRInitStruct pointer to a @ref LL_TIM_BDTR_InitTypeDef structure(Break and Dead Time configuration data structure)
692 * @retval An ErrorStatus enumeration value:
693 * - SUCCESS: Break and Dead Time is initialized
694 * - ERROR: not applicable
695 */
696 ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef *TIMx, LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct)
697 {
698 uint32_t tmpbdtr = 0;
699
700 /* Check the parameters */
701 assert_param(IS_TIM_BREAK_INSTANCE(TIMx));
702 assert_param(IS_LL_TIM_OSSR_STATE(TIM_BDTRInitStruct->OSSRState));
703 assert_param(IS_LL_TIM_OSSI_STATE(TIM_BDTRInitStruct->OSSIState));
704 assert_param(IS_LL_TIM_LOCK_LEVEL(TIM_BDTRInitStruct->LockLevel));
705 assert_param(IS_LL_TIM_BREAK_STATE(TIM_BDTRInitStruct->BreakState));
706 assert_param(IS_LL_TIM_BREAK_POLARITY(TIM_BDTRInitStruct->BreakPolarity));
707 assert_param(IS_LL_TIM_AUTOMATIC_OUTPUT_STATE(TIM_BDTRInitStruct->AutomaticOutput));
708
709 /* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State,
710 the OSSI State, the dead time value and the Automatic Output Enable Bit */
711
712 /* Set the BDTR bits */
713 MODIFY_REG(tmpbdtr, TIM_BDTR_DTG, TIM_BDTRInitStruct->DeadTime);
714 MODIFY_REG(tmpbdtr, TIM_BDTR_LOCK, TIM_BDTRInitStruct->LockLevel);
715 MODIFY_REG(tmpbdtr, TIM_BDTR_OSSI, TIM_BDTRInitStruct->OSSIState);
716 MODIFY_REG(tmpbdtr, TIM_BDTR_OSSR, TIM_BDTRInitStruct->OSSRState);
717 MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, TIM_BDTRInitStruct->BreakState);
718 MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, TIM_BDTRInitStruct->BreakPolarity);
719 MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, TIM_BDTRInitStruct->AutomaticOutput);
720 MODIFY_REG(tmpbdtr, TIM_BDTR_MOE, TIM_BDTRInitStruct->AutomaticOutput);
721
722 /* Set TIMx_BDTR */
723 LL_TIM_WriteReg(TIMx, BDTR, tmpbdtr);
724
725 return SUCCESS;
726 }
727 /**
728 * @}
729 */
730
731 /**
732 * @}
733 */
734
735 /** @addtogroup TIM_LL_Private_Functions TIM Private Functions
736 * @brief Private functions
737 * @{
738 */
739 /**
740 * @brief Configure the TIMx output channel 1.
741 * @param TIMx Timer Instance
742 * @param TIM_OCInitStruct pointer to the the TIMx output channel 1 configuration data structure
743 * @retval An ErrorStatus enumeration value:
744 * - SUCCESS: TIMx registers are de-initialized
745 * - ERROR: not applicable
746 */
747 static ErrorStatus OC1Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
748 {
749 uint32_t tmpccmr1 = 0U;
750 uint32_t tmpccer = 0U;
751 uint32_t tmpcr2 = 0U;
752
753 /* Check the parameters */
754 assert_param(IS_TIM_CC1_INSTANCE(TIMx));
755 assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
756 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
757 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
758 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
759 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
760
761 /* Disable the Channel 1: Reset the CC1E Bit */
762 CLEAR_BIT(TIMx->CCER, TIM_CCER_CC1E);
763
764 /* Get the TIMx CCER register value */
765 tmpccer = LL_TIM_ReadReg(TIMx, CCER);
766
767 /* Get the TIMx CR2 register value */
768 tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
769
770 /* Get the TIMx CCMR1 register value */
771 tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
772
773 /* Reset Capture/Compare selection Bits */
774 CLEAR_BIT(tmpccmr1, TIM_CCMR1_CC1S);
775
776 /* Set the Output Compare Mode */
777 MODIFY_REG(tmpccmr1, TIM_CCMR1_OC1M, TIM_OCInitStruct->OCMode);
778
779 /* Set the Output Compare Polarity */
780 MODIFY_REG(tmpccer, TIM_CCER_CC1P, TIM_OCInitStruct->OCPolarity);
781
782 /* Set the Output State */
783 MODIFY_REG(tmpccer, TIM_CCER_CC1E, TIM_OCInitStruct->OCState);
784
785 if (IS_TIM_BREAK_INSTANCE(TIMx))
786 {
787 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
788 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
789
790 /* Set the complementary output Polarity */
791 MODIFY_REG(tmpccer, TIM_CCER_CC1NP, TIM_OCInitStruct->OCNPolarity << 2U);
792
793 /* Set the complementary output State */
794 MODIFY_REG(tmpccer, TIM_CCER_CC1NE, TIM_OCInitStruct->OCNState << 2U);
795
796 /* Set the Output Idle state */
797 MODIFY_REG(tmpcr2, TIM_CR2_OIS1, TIM_OCInitStruct->OCIdleState);
798
799 /* Set the complementary output Idle state */
800 MODIFY_REG(tmpcr2, TIM_CR2_OIS1N, TIM_OCInitStruct->OCNIdleState << 1U);
801 }
802
803 /* Write to TIMx CR2 */
804 LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
805
806 /* Write to TIMx CCMR1 */
807 LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
808
809 /* Set the Capture Compare Register value */
810 LL_TIM_OC_SetCompareCH1(TIMx, TIM_OCInitStruct->CompareValue);
811
812 /* Write to TIMx CCER */
813 LL_TIM_WriteReg(TIMx, CCER, tmpccer);
814
815 return SUCCESS;
816 }
817
818 /**
819 * @brief Configure the TIMx output channel 2.
820 * @param TIMx Timer Instance
821 * @param TIM_OCInitStruct pointer to the the TIMx output channel 2 configuration data structure
822 * @retval An ErrorStatus enumeration value:
823 * - SUCCESS: TIMx registers are de-initialized
824 * - ERROR: not applicable
825 */
826 static ErrorStatus OC2Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
827 {
828 uint32_t tmpccmr1 = 0U;
829 uint32_t tmpccer = 0U;
830 uint32_t tmpcr2 = 0U;
831
832 /* Check the parameters */
833 assert_param(IS_TIM_CC2_INSTANCE(TIMx));
834 assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
835 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
836 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
837 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
838 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
839
840 /* Disable the Channel 2: Reset the CC2E Bit */
841 CLEAR_BIT(TIMx->CCER, TIM_CCER_CC2E);
842
843 /* Get the TIMx CCER register value */
844 tmpccer = LL_TIM_ReadReg(TIMx, CCER);
845
846 /* Get the TIMx CR2 register value */
847 tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
848
849 /* Get the TIMx CCMR1 register value */
850 tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
851
852 /* Reset Capture/Compare selection Bits */
853 CLEAR_BIT(tmpccmr1, TIM_CCMR1_CC2S);
854
855 /* Select the Output Compare Mode */
856 MODIFY_REG(tmpccmr1, TIM_CCMR1_OC2M, TIM_OCInitStruct->OCMode << 8U);
857
858 /* Set the Output Compare Polarity */
859 MODIFY_REG(tmpccer, TIM_CCER_CC2P, TIM_OCInitStruct->OCPolarity << 4U);
860
861 /* Set the Output State */
862 MODIFY_REG(tmpccer, TIM_CCER_CC2E, TIM_OCInitStruct->OCState << 4U);
863
864 if (IS_TIM_BREAK_INSTANCE(TIMx))
865 {
866 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
867 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
868
869 /* Set the complementary output Polarity */
870 MODIFY_REG(tmpccer, TIM_CCER_CC2NP, TIM_OCInitStruct->OCNPolarity << 6U);
871
872 /* Set the complementary output State */
873 MODIFY_REG(tmpccer, TIM_CCER_CC2NE, TIM_OCInitStruct->OCNState << 6U);
874
875 /* Set the Output Idle state */
876 MODIFY_REG(tmpcr2, TIM_CR2_OIS2, TIM_OCInitStruct->OCIdleState << 2U);
877
878 /* Set the complementary output Idle state */
879 MODIFY_REG(tmpcr2, TIM_CR2_OIS2N, TIM_OCInitStruct->OCNIdleState << 3U);
880 }
881
882 /* Write to TIMx CR2 */
883 LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
884
885 /* Write to TIMx CCMR1 */
886 LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
887
888 /* Set the Capture Compare Register value */
889 LL_TIM_OC_SetCompareCH2(TIMx, TIM_OCInitStruct->CompareValue);
890
891 /* Write to TIMx CCER */
892 LL_TIM_WriteReg(TIMx, CCER, tmpccer);
893
894 return SUCCESS;
895 }
896
897 /**
898 * @brief Configure the TIMx output channel 3.
899 * @param TIMx Timer Instance
900 * @param TIM_OCInitStruct pointer to the the TIMx output channel 3 configuration data structure
901 * @retval An ErrorStatus enumeration value:
902 * - SUCCESS: TIMx registers are de-initialized
903 * - ERROR: not applicable
904 */
905 static ErrorStatus OC3Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
906 {
907 uint32_t tmpccmr2 = 0U;
908 uint32_t tmpccer = 0U;
909 uint32_t tmpcr2 = 0U;
910
911 /* Check the parameters */
912 assert_param(IS_TIM_CC3_INSTANCE(TIMx));
913 assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
914 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
915 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
916 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
917 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
918
919 /* Disable the Channel 3: Reset the CC3E Bit */
920 CLEAR_BIT(TIMx->CCER, TIM_CCER_CC3E);
921
922 /* Get the TIMx CCER register value */
923 tmpccer = LL_TIM_ReadReg(TIMx, CCER);
924
925 /* Get the TIMx CR2 register value */
926 tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
927
928 /* Get the TIMx CCMR2 register value */
929 tmpccmr2 = LL_TIM_ReadReg(TIMx, CCMR2);
930
931 /* Reset Capture/Compare selection Bits */
932 CLEAR_BIT(tmpccmr2, TIM_CCMR2_CC3S);
933
934 /* Select the Output Compare Mode */
935 MODIFY_REG(tmpccmr2, TIM_CCMR2_OC3M, TIM_OCInitStruct->OCMode);
936
937 /* Set the Output Compare Polarity */
938 MODIFY_REG(tmpccer, TIM_CCER_CC3P, TIM_OCInitStruct->OCPolarity << 8U);
939
940 /* Set the Output State */
941 MODIFY_REG(tmpccer, TIM_CCER_CC3E, TIM_OCInitStruct->OCState << 8U);
942
943 if (IS_TIM_BREAK_INSTANCE(TIMx))
944 {
945 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
946 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
947
948 /* Set the complementary output Polarity */
949 MODIFY_REG(tmpccer, TIM_CCER_CC3NP, TIM_OCInitStruct->OCNPolarity << 10U);
950
951 /* Set the complementary output State */
952 MODIFY_REG(tmpccer, TIM_CCER_CC3NE, TIM_OCInitStruct->OCNState << 10U);
953
954 /* Set the Output Idle state */
955 MODIFY_REG(tmpcr2, TIM_CR2_OIS3, TIM_OCInitStruct->OCIdleState << 4U);
956
957 /* Set the complementary output Idle state */
958 MODIFY_REG(tmpcr2, TIM_CR2_OIS3N, TIM_OCInitStruct->OCNIdleState << 5U);
959 }
960
961 /* Write to TIMx CR2 */
962 LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
963
964 /* Write to TIMx CCMR2 */
965 LL_TIM_WriteReg(TIMx, CCMR2, tmpccmr2);
966
967 /* Set the Capture Compare Register value */
968 LL_TIM_OC_SetCompareCH3(TIMx, TIM_OCInitStruct->CompareValue);
969
970 /* Write to TIMx CCER */
971 LL_TIM_WriteReg(TIMx, CCER, tmpccer);
972
973 return SUCCESS;
974 }
975
976 /**
977 * @brief Configure the TIMx output channel 4.
978 * @param TIMx Timer Instance
979 * @param TIM_OCInitStruct pointer to the the TIMx output channel 4 configuration data structure
980 * @retval An ErrorStatus enumeration value:
981 * - SUCCESS: TIMx registers are de-initialized
982 * - ERROR: not applicable
983 */
984 static ErrorStatus OC4Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
985 {
986 uint32_t tmpccmr2 = 0U;
987 uint32_t tmpccer = 0U;
988 uint32_t tmpcr2 = 0U;
989
990 /* Check the parameters */
991 assert_param(IS_TIM_CC4_INSTANCE(TIMx));
992 assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
993 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
994 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
995 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
996 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
997
998 /* Disable the Channel 4: Reset the CC4E Bit */
999 CLEAR_BIT(TIMx->CCER, TIM_CCER_CC4E);
1000
1001 /* Get the TIMx CCER register value */
1002 tmpccer = LL_TIM_ReadReg(TIMx, CCER);
1003
1004 /* Get the TIMx CR2 register value */
1005 tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
1006
1007 /* Get the TIMx CCMR2 register value */
1008 tmpccmr2 = LL_TIM_ReadReg(TIMx, CCMR2);
1009
1010 /* Reset Capture/Compare selection Bits */
1011 CLEAR_BIT(tmpccmr2, TIM_CCMR2_CC4S);
1012
1013 /* Select the Output Compare Mode */
1014 MODIFY_REG(tmpccmr2, TIM_CCMR2_OC4M, TIM_OCInitStruct->OCMode << 8U);
1015
1016 /* Set the Output Compare Polarity */
1017 MODIFY_REG(tmpccer, TIM_CCER_CC4P, TIM_OCInitStruct->OCPolarity << 12U);
1018
1019 /* Set the Output State */
1020 MODIFY_REG(tmpccer, TIM_CCER_CC4E, TIM_OCInitStruct->OCState << 12U);
1021
1022 if (IS_TIM_BREAK_INSTANCE(TIMx))
1023 {
1024 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
1025 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
1026
1027 /* Set the Output Idle state */
1028 MODIFY_REG(tmpcr2, TIM_CR2_OIS4, TIM_OCInitStruct->OCIdleState << 6U);
1029 }
1030
1031 /* Write to TIMx CR2 */
1032 LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
1033
1034 /* Write to TIMx CCMR2 */
1035 LL_TIM_WriteReg(TIMx, CCMR2, tmpccmr2);
1036
1037 /* Set the Capture Compare Register value */
1038 LL_TIM_OC_SetCompareCH4(TIMx, TIM_OCInitStruct->CompareValue);
1039
1040 /* Write to TIMx CCER */
1041 LL_TIM_WriteReg(TIMx, CCER, tmpccer);
1042
1043 return SUCCESS;
1044 }
1045
1046
1047 /**
1048 * @brief Configure the TIMx input channel 1.
1049 * @param TIMx Timer Instance
1050 * @param TIM_ICInitStruct pointer to the the TIMx input channel 1 configuration data structure
1051 * @retval An ErrorStatus enumeration value:
1052 * - SUCCESS: TIMx registers are de-initialized
1053 * - ERROR: not applicable
1054 */
1055 static ErrorStatus IC1Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
1056 {
1057 /* Check the parameters */
1058 assert_param(IS_TIM_CC1_INSTANCE(TIMx));
1059 assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
1060 assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
1061 assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
1062 assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
1063
1064 /* Disable the Channel 1: Reset the CC1E Bit */
1065 TIMx->CCER &= (uint32_t)~TIM_CCER_CC1E;
1066
1067 /* Select the Input and set the filter and the prescaler value */
1068 MODIFY_REG(TIMx->CCMR1,
1069 (TIM_CCMR1_CC1S | TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC),
1070 (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 16U);
1071
1072 /* Select the Polarity and set the CC1E Bit */
1073 MODIFY_REG(TIMx->CCER,
1074 (TIM_CCER_CC1P | TIM_CCER_CC1NP),
1075 (TIM_ICInitStruct->ICPolarity | TIM_CCER_CC1E));
1076
1077 return SUCCESS;
1078 }
1079
1080 /**
1081 * @brief Configure the TIMx input channel 2.
1082 * @param TIMx Timer Instance
1083 * @param TIM_ICInitStruct pointer to the the TIMx input channel 2 configuration data structure
1084 * @retval An ErrorStatus enumeration value:
1085 * - SUCCESS: TIMx registers are de-initialized
1086 * - ERROR: not applicable
1087 */
1088 static ErrorStatus IC2Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
1089 {
1090 /* Check the parameters */
1091 assert_param(IS_TIM_CC2_INSTANCE(TIMx));
1092 assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
1093 assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
1094 assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
1095 assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
1096
1097 /* Disable the Channel 2: Reset the CC2E Bit */
1098 TIMx->CCER &= (uint32_t)~TIM_CCER_CC2E;
1099
1100 /* Select the Input and set the filter and the prescaler value */
1101 MODIFY_REG(TIMx->CCMR1,
1102 (TIM_CCMR1_CC2S | TIM_CCMR1_IC2F | TIM_CCMR1_IC2PSC),
1103 (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 8U);
1104
1105 /* Select the Polarity and set the CC2E Bit */
1106 MODIFY_REG(TIMx->CCER,
1107 (TIM_CCER_CC2P | TIM_CCER_CC2NP),
1108 ((TIM_ICInitStruct->ICPolarity << 4U) | TIM_CCER_CC2E));
1109
1110 return SUCCESS;
1111 }
1112
1113 /**
1114 * @brief Configure the TIMx input channel 3.
1115 * @param TIMx Timer Instance
1116 * @param TIM_ICInitStruct pointer to the the TIMx input channel 3 configuration data structure
1117 * @retval An ErrorStatus enumeration value:
1118 * - SUCCESS: TIMx registers are de-initialized
1119 * - ERROR: not applicable
1120 */
1121 static ErrorStatus IC3Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
1122 {
1123 /* Check the parameters */
1124 assert_param(IS_TIM_CC3_INSTANCE(TIMx));
1125 assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
1126 assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
1127 assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
1128 assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
1129
1130 /* Disable the Channel 3: Reset the CC3E Bit */
1131 TIMx->CCER &= (uint32_t)~TIM_CCER_CC3E;
1132
1133 /* Select the Input and set the filter and the prescaler value */
1134 MODIFY_REG(TIMx->CCMR2,
1135 (TIM_CCMR2_CC3S | TIM_CCMR2_IC3F | TIM_CCMR2_IC3PSC),
1136 (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 16U);
1137
1138 /* Select the Polarity and set the CC3E Bit */
1139 MODIFY_REG(TIMx->CCER,
1140 (TIM_CCER_CC3P | TIM_CCER_CC3NP),
1141 ((TIM_ICInitStruct->ICPolarity << 8U) | TIM_CCER_CC3E));
1142
1143 return SUCCESS;
1144 }
1145
1146 /**
1147 * @brief Configure the TIMx input channel 4.
1148 * @param TIMx Timer Instance
1149 * @param TIM_ICInitStruct pointer to the the TIMx input channel 4 configuration data structure
1150 * @retval An ErrorStatus enumeration value:
1151 * - SUCCESS: TIMx registers are de-initialized
1152 * - ERROR: not applicable
1153 */
1154 static ErrorStatus IC4Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
1155 {
1156 /* Check the parameters */
1157 assert_param(IS_TIM_CC4_INSTANCE(TIMx));
1158 assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
1159 assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
1160 assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
1161 assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
1162
1163 /* Disable the Channel 4: Reset the CC4E Bit */
1164 TIMx->CCER &= (uint32_t)~TIM_CCER_CC4E;
1165
1166 /* Select the Input and set the filter and the prescaler value */
1167 MODIFY_REG(TIMx->CCMR2,
1168 (TIM_CCMR2_CC4S | TIM_CCMR2_IC4F | TIM_CCMR2_IC4PSC),
1169 (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 8U);
1170
1171 /* Select the Polarity and set the CC2E Bit */
1172 MODIFY_REG(TIMx->CCER,
1173 (TIM_CCER_CC4P | TIM_CCER_CC4NP),
1174 ((TIM_ICInitStruct->ICPolarity << 12U) | TIM_CCER_CC4E));
1175
1176 return SUCCESS;
1177 }
1178
1179
1180 /**
1181 * @}
1182 */
1183
1184 /**
1185 * @}
1186 */
1187
1188 #endif /* TIM1 || TIM2 || TIM3 || TIM4 || TIM5 || TIM6 || TIM7 || TIM8 || TIM9 || TIM10 || TIM11 || TIM12 || TIM13 || TIM14 */
1189
1190 /**
1191 * @}
1192 */
1193
1194 #endif /* USE_FULL_LL_DRIVER */
1195
1196 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/