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comparison Common/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_spi.c @ 128:c78bcbd5deda FlipDisplay
Added current STM32 standandard libraries in version independend folder structure
author | Ideenmodellierer |
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date | Sun, 17 Feb 2019 21:12:22 +0100 |
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1 /** | |
2 ****************************************************************************** | |
3 * @file stm32f4xx_ll_spi.c | |
4 * @author MCD Application Team | |
5 * @brief SPI LL module driver. | |
6 ****************************************************************************** | |
7 * @attention | |
8 * | |
9 * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2> | |
10 * | |
11 * Redistribution and use in source and binary forms, with or without modification, | |
12 * are permitted provided that the following conditions are met: | |
13 * 1. Redistributions of source code must retain the above copyright notice, | |
14 * this list of conditions and the following disclaimer. | |
15 * 2. Redistributions in binary form must reproduce the above copyright notice, | |
16 * this list of conditions and the following disclaimer in the documentation | |
17 * and/or other materials provided with the distribution. | |
18 * 3. Neither the name of STMicroelectronics nor the names of its contributors | |
19 * may be used to endorse or promote products derived from this software | |
20 * without specific prior written permission. | |
21 * | |
22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" | |
23 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE | |
24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE | |
25 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE | |
26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL | |
27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR | |
28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER | |
29 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, | |
30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE | |
31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | |
32 * | |
33 ****************************************************************************** | |
34 */ | |
35 #if defined(USE_FULL_LL_DRIVER) | |
36 | |
37 /* Includes ------------------------------------------------------------------*/ | |
38 #include "stm32f4xx_ll_spi.h" | |
39 #include "stm32f4xx_ll_bus.h" | |
40 #include "stm32f4xx_ll_rcc.h" | |
41 | |
42 #ifdef USE_FULL_ASSERT | |
43 #include "stm32_assert.h" | |
44 #else | |
45 #define assert_param(expr) ((void)0U) | |
46 #endif | |
47 | |
48 /** @addtogroup STM32F4xx_LL_Driver | |
49 * @{ | |
50 */ | |
51 | |
52 #if defined (SPI1) || defined (SPI2) || defined (SPI3) || defined (SPI4) || defined (SPI5) || defined(SPI6) | |
53 | |
54 /** @addtogroup SPI_LL | |
55 * @{ | |
56 */ | |
57 | |
58 /* Private types -------------------------------------------------------------*/ | |
59 /* Private variables ---------------------------------------------------------*/ | |
60 | |
61 /* Private constants ---------------------------------------------------------*/ | |
62 /** @defgroup SPI_LL_Private_Constants SPI Private Constants | |
63 * @{ | |
64 */ | |
65 /* SPI registers Masks */ | |
66 #define SPI_CR1_CLEAR_MASK (SPI_CR1_CPHA | SPI_CR1_CPOL | SPI_CR1_MSTR | \ | |
67 SPI_CR1_BR | SPI_CR1_LSBFIRST | SPI_CR1_SSI | \ | |
68 SPI_CR1_SSM | SPI_CR1_RXONLY | SPI_CR1_DFF | \ | |
69 SPI_CR1_CRCNEXT | SPI_CR1_CRCEN | SPI_CR1_BIDIOE | \ | |
70 SPI_CR1_BIDIMODE) | |
71 /** | |
72 * @} | |
73 */ | |
74 | |
75 /* Private macros ------------------------------------------------------------*/ | |
76 /** @defgroup SPI_LL_Private_Macros SPI Private Macros | |
77 * @{ | |
78 */ | |
79 #define IS_LL_SPI_TRANSFER_DIRECTION(__VALUE__) (((__VALUE__) == LL_SPI_FULL_DUPLEX) \ | |
80 || ((__VALUE__) == LL_SPI_SIMPLEX_RX) \ | |
81 || ((__VALUE__) == LL_SPI_HALF_DUPLEX_RX) \ | |
82 || ((__VALUE__) == LL_SPI_HALF_DUPLEX_TX)) | |
83 | |
84 #define IS_LL_SPI_MODE(__VALUE__) (((__VALUE__) == LL_SPI_MODE_MASTER) \ | |
85 || ((__VALUE__) == LL_SPI_MODE_SLAVE)) | |
86 | |
87 #define IS_LL_SPI_DATAWIDTH(__VALUE__) (((__VALUE__) == LL_SPI_DATAWIDTH_8BIT) \ | |
88 || ((__VALUE__) == LL_SPI_DATAWIDTH_16BIT)) | |
89 | |
90 #define IS_LL_SPI_POLARITY(__VALUE__) (((__VALUE__) == LL_SPI_POLARITY_LOW) \ | |
91 || ((__VALUE__) == LL_SPI_POLARITY_HIGH)) | |
92 | |
93 #define IS_LL_SPI_PHASE(__VALUE__) (((__VALUE__) == LL_SPI_PHASE_1EDGE) \ | |
94 || ((__VALUE__) == LL_SPI_PHASE_2EDGE)) | |
95 | |
96 #define IS_LL_SPI_NSS(__VALUE__) (((__VALUE__) == LL_SPI_NSS_SOFT) \ | |
97 || ((__VALUE__) == LL_SPI_NSS_HARD_INPUT) \ | |
98 || ((__VALUE__) == LL_SPI_NSS_HARD_OUTPUT)) | |
99 | |
100 #define IS_LL_SPI_BAUDRATE(__VALUE__) (((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV2) \ | |
101 || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV4) \ | |
102 || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV8) \ | |
103 || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV16) \ | |
104 || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV32) \ | |
105 || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV64) \ | |
106 || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV128) \ | |
107 || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV256)) | |
108 | |
109 #define IS_LL_SPI_BITORDER(__VALUE__) (((__VALUE__) == LL_SPI_LSB_FIRST) \ | |
110 || ((__VALUE__) == LL_SPI_MSB_FIRST)) | |
111 | |
112 #define IS_LL_SPI_CRCCALCULATION(__VALUE__) (((__VALUE__) == LL_SPI_CRCCALCULATION_ENABLE) \ | |
113 || ((__VALUE__) == LL_SPI_CRCCALCULATION_DISABLE)) | |
114 | |
115 #define IS_LL_SPI_CRC_POLYNOMIAL(__VALUE__) ((__VALUE__) >= 0x1U) | |
116 | |
117 /** | |
118 * @} | |
119 */ | |
120 | |
121 /* Private function prototypes -----------------------------------------------*/ | |
122 | |
123 /* Exported functions --------------------------------------------------------*/ | |
124 /** @addtogroup SPI_LL_Exported_Functions | |
125 * @{ | |
126 */ | |
127 | |
128 /** @addtogroup SPI_LL_EF_Init | |
129 * @{ | |
130 */ | |
131 | |
132 /** | |
133 * @brief De-initialize the SPI registers to their default reset values. | |
134 * @param SPIx SPI Instance | |
135 * @retval An ErrorStatus enumeration value: | |
136 * - SUCCESS: SPI registers are de-initialized | |
137 * - ERROR: SPI registers are not de-initialized | |
138 */ | |
139 ErrorStatus LL_SPI_DeInit(SPI_TypeDef *SPIx) | |
140 { | |
141 ErrorStatus status = ERROR; | |
142 | |
143 /* Check the parameters */ | |
144 assert_param(IS_SPI_ALL_INSTANCE(SPIx)); | |
145 | |
146 #if defined(SPI1) | |
147 if (SPIx == SPI1) | |
148 { | |
149 /* Force reset of SPI clock */ | |
150 LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_SPI1); | |
151 | |
152 /* Release reset of SPI clock */ | |
153 LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_SPI1); | |
154 | |
155 status = SUCCESS; | |
156 } | |
157 #endif /* SPI1 */ | |
158 #if defined(SPI2) | |
159 if (SPIx == SPI2) | |
160 { | |
161 /* Force reset of SPI clock */ | |
162 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_SPI2); | |
163 | |
164 /* Release reset of SPI clock */ | |
165 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_SPI2); | |
166 | |
167 status = SUCCESS; | |
168 } | |
169 #endif /* SPI2 */ | |
170 #if defined(SPI3) | |
171 if (SPIx == SPI3) | |
172 { | |
173 /* Force reset of SPI clock */ | |
174 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_SPI3); | |
175 | |
176 /* Release reset of SPI clock */ | |
177 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_SPI3); | |
178 | |
179 status = SUCCESS; | |
180 } | |
181 #endif /* SPI3 */ | |
182 #if defined(SPI4) | |
183 if (SPIx == SPI4) | |
184 { | |
185 /* Force reset of SPI clock */ | |
186 LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_SPI4); | |
187 | |
188 /* Release reset of SPI clock */ | |
189 LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_SPI4); | |
190 | |
191 status = SUCCESS; | |
192 } | |
193 #endif /* SPI4 */ | |
194 #if defined(SPI5) | |
195 if (SPIx == SPI5) | |
196 { | |
197 /* Force reset of SPI clock */ | |
198 LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_SPI5); | |
199 | |
200 /* Release reset of SPI clock */ | |
201 LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_SPI5); | |
202 | |
203 status = SUCCESS; | |
204 } | |
205 #endif /* SPI5 */ | |
206 #if defined(SPI6) | |
207 if (SPIx == SPI6) | |
208 { | |
209 /* Force reset of SPI clock */ | |
210 LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_SPI6); | |
211 | |
212 /* Release reset of SPI clock */ | |
213 LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_SPI6); | |
214 | |
215 status = SUCCESS; | |
216 } | |
217 #endif /* SPI6 */ | |
218 | |
219 return status; | |
220 } | |
221 | |
222 /** | |
223 * @brief Initialize the SPI registers according to the specified parameters in SPI_InitStruct. | |
224 * @note As some bits in SPI configuration registers can only be written when the SPI is disabled (SPI_CR1_SPE bit =0), | |
225 * SPI IP should be in disabled state prior calling this function. Otherwise, ERROR result will be returned. | |
226 * @param SPIx SPI Instance | |
227 * @param SPI_InitStruct pointer to a @ref LL_SPI_InitTypeDef structure | |
228 * @retval An ErrorStatus enumeration value. (Return always SUCCESS) | |
229 */ | |
230 ErrorStatus LL_SPI_Init(SPI_TypeDef *SPIx, LL_SPI_InitTypeDef *SPI_InitStruct) | |
231 { | |
232 ErrorStatus status = ERROR; | |
233 | |
234 /* Check the SPI Instance SPIx*/ | |
235 assert_param(IS_SPI_ALL_INSTANCE(SPIx)); | |
236 | |
237 /* Check the SPI parameters from SPI_InitStruct*/ | |
238 assert_param(IS_LL_SPI_TRANSFER_DIRECTION(SPI_InitStruct->TransferDirection)); | |
239 assert_param(IS_LL_SPI_MODE(SPI_InitStruct->Mode)); | |
240 assert_param(IS_LL_SPI_DATAWIDTH(SPI_InitStruct->DataWidth)); | |
241 assert_param(IS_LL_SPI_POLARITY(SPI_InitStruct->ClockPolarity)); | |
242 assert_param(IS_LL_SPI_PHASE(SPI_InitStruct->ClockPhase)); | |
243 assert_param(IS_LL_SPI_NSS(SPI_InitStruct->NSS)); | |
244 assert_param(IS_LL_SPI_BAUDRATE(SPI_InitStruct->BaudRate)); | |
245 assert_param(IS_LL_SPI_BITORDER(SPI_InitStruct->BitOrder)); | |
246 assert_param(IS_LL_SPI_CRCCALCULATION(SPI_InitStruct->CRCCalculation)); | |
247 | |
248 if (LL_SPI_IsEnabled(SPIx) == 0x00000000U) | |
249 { | |
250 /*---------------------------- SPIx CR1 Configuration ------------------------ | |
251 * Configure SPIx CR1 with parameters: | |
252 * - TransferDirection: SPI_CR1_BIDIMODE, SPI_CR1_BIDIOE and SPI_CR1_RXONLY bits | |
253 * - Master/Slave Mode: SPI_CR1_MSTR bit | |
254 * - DataWidth: SPI_CR1_DFF bit | |
255 * - ClockPolarity: SPI_CR1_CPOL bit | |
256 * - ClockPhase: SPI_CR1_CPHA bit | |
257 * - NSS management: SPI_CR1_SSM bit | |
258 * - BaudRate prescaler: SPI_CR1_BR[2:0] bits | |
259 * - BitOrder: SPI_CR1_LSBFIRST bit | |
260 * - CRCCalculation: SPI_CR1_CRCEN bit | |
261 */ | |
262 MODIFY_REG(SPIx->CR1, | |
263 SPI_CR1_CLEAR_MASK, | |
264 SPI_InitStruct->TransferDirection | SPI_InitStruct->Mode | SPI_InitStruct->DataWidth | | |
265 SPI_InitStruct->ClockPolarity | SPI_InitStruct->ClockPhase | | |
266 SPI_InitStruct->NSS | SPI_InitStruct->BaudRate | | |
267 SPI_InitStruct->BitOrder | SPI_InitStruct->CRCCalculation); | |
268 | |
269 /*---------------------------- SPIx CR2 Configuration ------------------------ | |
270 * Configure SPIx CR2 with parameters: | |
271 * - NSS management: SSOE bit | |
272 */ | |
273 MODIFY_REG(SPIx->CR2, SPI_CR2_SSOE, (SPI_InitStruct->NSS >> 16U)); | |
274 | |
275 /*---------------------------- SPIx CRCPR Configuration ---------------------- | |
276 * Configure SPIx CRCPR with parameters: | |
277 * - CRCPoly: CRCPOLY[15:0] bits | |
278 */ | |
279 if (SPI_InitStruct->CRCCalculation == LL_SPI_CRCCALCULATION_ENABLE) | |
280 { | |
281 assert_param(IS_LL_SPI_CRC_POLYNOMIAL(SPI_InitStruct->CRCPoly)); | |
282 LL_SPI_SetCRCPolynomial(SPIx, SPI_InitStruct->CRCPoly); | |
283 } | |
284 status = SUCCESS; | |
285 } | |
286 | |
287 /* Activate the SPI mode (Reset I2SMOD bit in I2SCFGR register) */ | |
288 CLEAR_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SMOD); | |
289 return status; | |
290 } | |
291 | |
292 /** | |
293 * @brief Set each @ref LL_SPI_InitTypeDef field to default value. | |
294 * @param SPI_InitStruct pointer to a @ref LL_SPI_InitTypeDef structure | |
295 * whose fields will be set to default values. | |
296 * @retval None | |
297 */ | |
298 void LL_SPI_StructInit(LL_SPI_InitTypeDef *SPI_InitStruct) | |
299 { | |
300 /* Set SPI_InitStruct fields to default values */ | |
301 SPI_InitStruct->TransferDirection = LL_SPI_FULL_DUPLEX; | |
302 SPI_InitStruct->Mode = LL_SPI_MODE_SLAVE; | |
303 SPI_InitStruct->DataWidth = LL_SPI_DATAWIDTH_8BIT; | |
304 SPI_InitStruct->ClockPolarity = LL_SPI_POLARITY_LOW; | |
305 SPI_InitStruct->ClockPhase = LL_SPI_PHASE_1EDGE; | |
306 SPI_InitStruct->NSS = LL_SPI_NSS_HARD_INPUT; | |
307 SPI_InitStruct->BaudRate = LL_SPI_BAUDRATEPRESCALER_DIV2; | |
308 SPI_InitStruct->BitOrder = LL_SPI_MSB_FIRST; | |
309 SPI_InitStruct->CRCCalculation = LL_SPI_CRCCALCULATION_DISABLE; | |
310 SPI_InitStruct->CRCPoly = 7U; | |
311 } | |
312 | |
313 /** | |
314 * @} | |
315 */ | |
316 | |
317 /** | |
318 * @} | |
319 */ | |
320 | |
321 /** | |
322 * @} | |
323 */ | |
324 | |
325 /** @addtogroup I2S_LL | |
326 * @{ | |
327 */ | |
328 | |
329 /* Private types -------------------------------------------------------------*/ | |
330 /* Private variables ---------------------------------------------------------*/ | |
331 /* Private constants ---------------------------------------------------------*/ | |
332 /** @defgroup I2S_LL_Private_Constants I2S Private Constants | |
333 * @{ | |
334 */ | |
335 /* I2S registers Masks */ | |
336 #define I2S_I2SCFGR_CLEAR_MASK (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN | \ | |
337 SPI_I2SCFGR_CKPOL | SPI_I2SCFGR_I2SSTD | \ | |
338 SPI_I2SCFGR_I2SCFG | SPI_I2SCFGR_I2SMOD ) | |
339 | |
340 #define I2S_I2SPR_CLEAR_MASK 0x0002U | |
341 /** | |
342 * @} | |
343 */ | |
344 /* Private macros ------------------------------------------------------------*/ | |
345 /** @defgroup I2S_LL_Private_Macros I2S Private Macros | |
346 * @{ | |
347 */ | |
348 | |
349 #define IS_LL_I2S_DATAFORMAT(__VALUE__) (((__VALUE__) == LL_I2S_DATAFORMAT_16B) \ | |
350 || ((__VALUE__) == LL_I2S_DATAFORMAT_16B_EXTENDED) \ | |
351 || ((__VALUE__) == LL_I2S_DATAFORMAT_24B) \ | |
352 || ((__VALUE__) == LL_I2S_DATAFORMAT_32B)) | |
353 | |
354 #define IS_LL_I2S_CPOL(__VALUE__) (((__VALUE__) == LL_I2S_POLARITY_LOW) \ | |
355 || ((__VALUE__) == LL_I2S_POLARITY_HIGH)) | |
356 | |
357 #define IS_LL_I2S_STANDARD(__VALUE__) (((__VALUE__) == LL_I2S_STANDARD_PHILIPS) \ | |
358 || ((__VALUE__) == LL_I2S_STANDARD_MSB) \ | |
359 || ((__VALUE__) == LL_I2S_STANDARD_LSB) \ | |
360 || ((__VALUE__) == LL_I2S_STANDARD_PCM_SHORT) \ | |
361 || ((__VALUE__) == LL_I2S_STANDARD_PCM_LONG)) | |
362 | |
363 #define IS_LL_I2S_MODE(__VALUE__) (((__VALUE__) == LL_I2S_MODE_SLAVE_TX) \ | |
364 || ((__VALUE__) == LL_I2S_MODE_SLAVE_RX) \ | |
365 || ((__VALUE__) == LL_I2S_MODE_MASTER_TX) \ | |
366 || ((__VALUE__) == LL_I2S_MODE_MASTER_RX)) | |
367 | |
368 #define IS_LL_I2S_MCLK_OUTPUT(__VALUE__) (((__VALUE__) == LL_I2S_MCLK_OUTPUT_ENABLE) \ | |
369 || ((__VALUE__) == LL_I2S_MCLK_OUTPUT_DISABLE)) | |
370 | |
371 #define IS_LL_I2S_AUDIO_FREQ(__VALUE__) ((((__VALUE__) >= LL_I2S_AUDIOFREQ_8K) \ | |
372 && ((__VALUE__) <= LL_I2S_AUDIOFREQ_192K)) \ | |
373 || ((__VALUE__) == LL_I2S_AUDIOFREQ_DEFAULT)) | |
374 | |
375 #define IS_LL_I2S_PRESCALER_LINEAR(__VALUE__) ((__VALUE__) >= 0x2U) | |
376 | |
377 #define IS_LL_I2S_PRESCALER_PARITY(__VALUE__) (((__VALUE__) == LL_I2S_PRESCALER_PARITY_EVEN) \ | |
378 || ((__VALUE__) == LL_I2S_PRESCALER_PARITY_ODD)) | |
379 /** | |
380 * @} | |
381 */ | |
382 | |
383 /* Private function prototypes -----------------------------------------------*/ | |
384 | |
385 /* Exported functions --------------------------------------------------------*/ | |
386 /** @addtogroup I2S_LL_Exported_Functions | |
387 * @{ | |
388 */ | |
389 | |
390 /** @addtogroup I2S_LL_EF_Init | |
391 * @{ | |
392 */ | |
393 | |
394 /** | |
395 * @brief De-initialize the SPI/I2S registers to their default reset values. | |
396 * @param SPIx SPI Instance | |
397 * @retval An ErrorStatus enumeration value: | |
398 * - SUCCESS: SPI registers are de-initialized | |
399 * - ERROR: SPI registers are not de-initialized | |
400 */ | |
401 ErrorStatus LL_I2S_DeInit(SPI_TypeDef *SPIx) | |
402 { | |
403 return LL_SPI_DeInit(SPIx); | |
404 } | |
405 | |
406 /** | |
407 * @brief Initializes the SPI/I2S registers according to the specified parameters in I2S_InitStruct. | |
408 * @note As some bits in SPI configuration registers can only be written when the SPI is disabled (SPI_CR1_SPE bit =0), | |
409 * SPI IP should be in disabled state prior calling this function. Otherwise, ERROR result will be returned. | |
410 * @param SPIx SPI Instance | |
411 * @param I2S_InitStruct pointer to a @ref LL_I2S_InitTypeDef structure | |
412 * @retval An ErrorStatus enumeration value: | |
413 * - SUCCESS: SPI registers are Initialized | |
414 * - ERROR: SPI registers are not Initialized | |
415 */ | |
416 ErrorStatus LL_I2S_Init(SPI_TypeDef *SPIx, LL_I2S_InitTypeDef *I2S_InitStruct) | |
417 { | |
418 uint16_t i2sdiv = 2U, i2sodd = 0U, packetlength = 1U; | |
419 uint32_t tmp = 0U; | |
420 uint32_t sourceclock = 0U; | |
421 ErrorStatus status = ERROR; | |
422 | |
423 /* Check the I2S parameters */ | |
424 assert_param(IS_I2S_ALL_INSTANCE(SPIx)); | |
425 assert_param(IS_LL_I2S_MODE(I2S_InitStruct->Mode)); | |
426 assert_param(IS_LL_I2S_STANDARD(I2S_InitStruct->Standard)); | |
427 assert_param(IS_LL_I2S_DATAFORMAT(I2S_InitStruct->DataFormat)); | |
428 assert_param(IS_LL_I2S_MCLK_OUTPUT(I2S_InitStruct->MCLKOutput)); | |
429 assert_param(IS_LL_I2S_AUDIO_FREQ(I2S_InitStruct->AudioFreq)); | |
430 assert_param(IS_LL_I2S_CPOL(I2S_InitStruct->ClockPolarity)); | |
431 | |
432 if (LL_I2S_IsEnabled(SPIx) == 0x00000000U) | |
433 { | |
434 /*---------------------------- SPIx I2SCFGR Configuration -------------------- | |
435 * Configure SPIx I2SCFGR with parameters: | |
436 * - Mode: SPI_I2SCFGR_I2SCFG[1:0] bit | |
437 * - Standard: SPI_I2SCFGR_I2SSTD[1:0] and SPI_I2SCFGR_PCMSYNC bits | |
438 * - DataFormat: SPI_I2SCFGR_CHLEN and SPI_I2SCFGR_DATLEN bits | |
439 * - ClockPolarity: SPI_I2SCFGR_CKPOL bit | |
440 */ | |
441 | |
442 /* Write to SPIx I2SCFGR */ | |
443 MODIFY_REG(SPIx->I2SCFGR, | |
444 I2S_I2SCFGR_CLEAR_MASK, | |
445 I2S_InitStruct->Mode | I2S_InitStruct->Standard | | |
446 I2S_InitStruct->DataFormat | I2S_InitStruct->ClockPolarity | | |
447 SPI_I2SCFGR_I2SMOD); | |
448 | |
449 /*---------------------------- SPIx I2SPR Configuration ---------------------- | |
450 * Configure SPIx I2SPR with parameters: | |
451 * - MCLKOutput: SPI_I2SPR_MCKOE bit | |
452 * - AudioFreq: SPI_I2SPR_I2SDIV[7:0] and SPI_I2SPR_ODD bits | |
453 */ | |
454 | |
455 /* If the requested audio frequency is not the default, compute the prescaler (i2sodd, i2sdiv) | |
456 * else, default values are used: i2sodd = 0U, i2sdiv = 2U. | |
457 */ | |
458 if (I2S_InitStruct->AudioFreq != LL_I2S_AUDIOFREQ_DEFAULT) | |
459 { | |
460 /* Check the frame length (For the Prescaler computing) | |
461 * Default value: LL_I2S_DATAFORMAT_16B (packetlength = 1U). | |
462 */ | |
463 if (I2S_InitStruct->DataFormat != LL_I2S_DATAFORMAT_16B) | |
464 { | |
465 /* Packet length is 32 bits */ | |
466 packetlength = 2U; | |
467 } | |
468 | |
469 /* If an external I2S clock has to be used, the specific define should be set | |
470 in the project configuration or in the stm32f4xx_ll_rcc.h file */ | |
471 /* Get the I2S source clock value */ | |
472 sourceclock = LL_RCC_GetI2SClockFreq(LL_RCC_I2S1_CLKSOURCE); | |
473 | |
474 /* Compute the Real divider depending on the MCLK output state with a floating point */ | |
475 if (I2S_InitStruct->MCLKOutput == LL_I2S_MCLK_OUTPUT_ENABLE) | |
476 { | |
477 /* MCLK output is enabled */ | |
478 tmp = (uint16_t)(((((sourceclock / 256U) * 10U) / I2S_InitStruct->AudioFreq)) + 5U); | |
479 } | |
480 else | |
481 { | |
482 /* MCLK output is disabled */ | |
483 tmp = (uint16_t)(((((sourceclock / (32U * packetlength)) * 10U) / I2S_InitStruct->AudioFreq)) + 5U); | |
484 } | |
485 | |
486 /* Remove the floating point */ | |
487 tmp = tmp / 10U; | |
488 | |
489 /* Check the parity of the divider */ | |
490 i2sodd = (uint16_t)(tmp & (uint16_t)0x0001U); | |
491 | |
492 /* Compute the i2sdiv prescaler */ | |
493 i2sdiv = (uint16_t)((tmp - i2sodd) / 2U); | |
494 | |
495 /* Get the Mask for the Odd bit (SPI_I2SPR[8]) register */ | |
496 i2sodd = (uint16_t)(i2sodd << 8U); | |
497 } | |
498 | |
499 /* Test if the divider is 1 or 0 or greater than 0xFF */ | |
500 if ((i2sdiv < 2U) || (i2sdiv > 0xFFU)) | |
501 { | |
502 /* Set the default values */ | |
503 i2sdiv = 2U; | |
504 i2sodd = 0U; | |
505 } | |
506 | |
507 /* Write to SPIx I2SPR register the computed value */ | |
508 WRITE_REG(SPIx->I2SPR, i2sdiv | i2sodd | I2S_InitStruct->MCLKOutput); | |
509 | |
510 status = SUCCESS; | |
511 } | |
512 return status; | |
513 } | |
514 | |
515 /** | |
516 * @brief Set each @ref LL_I2S_InitTypeDef field to default value. | |
517 * @param I2S_InitStruct pointer to a @ref LL_I2S_InitTypeDef structure | |
518 * whose fields will be set to default values. | |
519 * @retval None | |
520 */ | |
521 void LL_I2S_StructInit(LL_I2S_InitTypeDef *I2S_InitStruct) | |
522 { | |
523 /*--------------- Reset I2S init structure parameters values -----------------*/ | |
524 I2S_InitStruct->Mode = LL_I2S_MODE_SLAVE_TX; | |
525 I2S_InitStruct->Standard = LL_I2S_STANDARD_PHILIPS; | |
526 I2S_InitStruct->DataFormat = LL_I2S_DATAFORMAT_16B; | |
527 I2S_InitStruct->MCLKOutput = LL_I2S_MCLK_OUTPUT_DISABLE; | |
528 I2S_InitStruct->AudioFreq = LL_I2S_AUDIOFREQ_DEFAULT; | |
529 I2S_InitStruct->ClockPolarity = LL_I2S_POLARITY_LOW; | |
530 } | |
531 | |
532 /** | |
533 * @brief Set linear and parity prescaler. | |
534 * @note To calculate value of PrescalerLinear(I2SDIV[7:0] bits) and PrescalerParity(ODD bit)\n | |
535 * Check Audio frequency table and formulas inside Reference Manual (SPI/I2S). | |
536 * @param SPIx SPI Instance | |
537 * @param PrescalerLinear value Min_Data=0x02 and Max_Data=0xFF. | |
538 * @param PrescalerParity This parameter can be one of the following values: | |
539 * @arg @ref LL_I2S_PRESCALER_PARITY_EVEN | |
540 * @arg @ref LL_I2S_PRESCALER_PARITY_ODD | |
541 * @retval None | |
542 */ | |
543 void LL_I2S_ConfigPrescaler(SPI_TypeDef *SPIx, uint32_t PrescalerLinear, uint32_t PrescalerParity) | |
544 { | |
545 /* Check the I2S parameters */ | |
546 assert_param(IS_I2S_ALL_INSTANCE(SPIx)); | |
547 assert_param(IS_LL_I2S_PRESCALER_LINEAR(PrescalerLinear)); | |
548 assert_param(IS_LL_I2S_PRESCALER_PARITY(PrescalerParity)); | |
549 | |
550 /* Write to SPIx I2SPR */ | |
551 MODIFY_REG(SPIx->I2SPR, SPI_I2SPR_I2SDIV | SPI_I2SPR_ODD, PrescalerLinear | (PrescalerParity << 8U)); | |
552 } | |
553 | |
554 #if defined (SPI_I2S_FULLDUPLEX_SUPPORT) | |
555 /** | |
556 * @brief Configures the full duplex mode for the I2Sx peripheral using its extension | |
557 * I2Sxext according to the specified parameters in the I2S_InitStruct. | |
558 * @note The structure pointed by I2S_InitStruct parameter should be the same | |
559 * used for the master I2S peripheral. In this case, if the master is | |
560 * configured as transmitter, the slave will be receiver and vice versa. | |
561 * Or you can force a different mode by modifying the field I2S_Mode to the | |
562 * value I2S_SlaveRx or I2S_SlaveTx independently of the master configuration. | |
563 * @param I2Sxext SPI Instance | |
564 * @param I2S_InitStruct pointer to a @ref LL_I2S_InitTypeDef structure | |
565 * @retval An ErrorStatus enumeration value: | |
566 * - SUCCESS: I2Sxext registers are Initialized | |
567 * - ERROR: I2Sxext registers are not Initialized | |
568 */ | |
569 ErrorStatus LL_I2S_InitFullDuplex(SPI_TypeDef *I2Sxext, LL_I2S_InitTypeDef *I2S_InitStruct) | |
570 { | |
571 uint16_t mode = 0U; | |
572 ErrorStatus status = ERROR; | |
573 | |
574 /* Check the I2S parameters */ | |
575 assert_param(IS_I2S_EXT_ALL_INSTANCE(I2Sxext)); | |
576 assert_param(IS_LL_I2S_MODE(I2S_InitStruct->Mode)); | |
577 assert_param(IS_LL_I2S_STANDARD(I2S_InitStruct->Standard)); | |
578 assert_param(IS_LL_I2S_DATAFORMAT(I2S_InitStruct->DataFormat)); | |
579 assert_param(IS_LL_I2S_CPOL(I2S_InitStruct->ClockPolarity)); | |
580 | |
581 if (LL_I2S_IsEnabled(I2Sxext) == 0x00000000U) | |
582 { | |
583 /*---------------------------- SPIx I2SCFGR Configuration -------------------- | |
584 * Configure SPIx I2SCFGR with parameters: | |
585 * - Mode: SPI_I2SCFGR_I2SCFG[1:0] bit | |
586 * - Standard: SPI_I2SCFGR_I2SSTD[1:0] and SPI_I2SCFGR_PCMSYNC bits | |
587 * - DataFormat: SPI_I2SCFGR_CHLEN and SPI_I2SCFGR_DATLEN bits | |
588 * - ClockPolarity: SPI_I2SCFGR_CKPOL bit | |
589 */ | |
590 | |
591 /* Reset I2SPR registers */ | |
592 WRITE_REG(I2Sxext->I2SPR, I2S_I2SPR_CLEAR_MASK); | |
593 | |
594 /* Get the mode to be configured for the extended I2S */ | |
595 if ((I2S_InitStruct->Mode == LL_I2S_MODE_MASTER_TX) || (I2S_InitStruct->Mode == LL_I2S_MODE_SLAVE_TX)) | |
596 { | |
597 mode = LL_I2S_MODE_SLAVE_RX; | |
598 } | |
599 else | |
600 { | |
601 if ((I2S_InitStruct->Mode == LL_I2S_MODE_MASTER_RX) || (I2S_InitStruct->Mode == LL_I2S_MODE_SLAVE_RX)) | |
602 { | |
603 mode = LL_I2S_MODE_SLAVE_TX; | |
604 } | |
605 } | |
606 | |
607 /* Write to SPIx I2SCFGR */ | |
608 MODIFY_REG(I2Sxext->I2SCFGR, | |
609 I2S_I2SCFGR_CLEAR_MASK, | |
610 I2S_InitStruct->Standard | | |
611 I2S_InitStruct->DataFormat | I2S_InitStruct->ClockPolarity | | |
612 SPI_I2SCFGR_I2SMOD | mode); | |
613 | |
614 status = SUCCESS; | |
615 } | |
616 return status; | |
617 } | |
618 #endif /* SPI_I2S_FULLDUPLEX_SUPPORT */ | |
619 | |
620 /** | |
621 * @} | |
622 */ | |
623 | |
624 /** | |
625 * @} | |
626 */ | |
627 | |
628 /** | |
629 * @} | |
630 */ | |
631 | |
632 #endif /* defined (SPI1) || defined (SPI2) || defined (SPI3) || defined (SPI4) || defined (SPI5) || defined(SPI6) */ | |
633 | |
634 /** | |
635 * @} | |
636 */ | |
637 | |
638 #endif /* USE_FULL_LL_DRIVER */ | |
639 | |
640 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |