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comparison Common/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_rcc.c @ 128:c78bcbd5deda FlipDisplay

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Added current STM32 standandard libraries in version independend folder structure
author Ideenmodellierer
date Sun, 17 Feb 2019 21:12:22 +0100
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127:1369f8660eaa 128:c78bcbd5deda
1 /**
2 ******************************************************************************
3 * @file stm32f4xx_ll_rcc.c
4 * @author MCD Application Team
5 * @brief RCC LL module driver.
6 ******************************************************************************
7 * @attention
8 *
9 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
10 *
11 * Redistribution and use in source and binary forms, with or without modification,
12 * are permitted provided that the following conditions are met:
13 * 1. Redistributions of source code must retain the above copyright notice,
14 * this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright notice,
16 * this list of conditions and the following disclaimer in the documentation
17 * and/or other materials provided with the distribution.
18 * 3. Neither the name of STMicroelectronics nor the names of its contributors
19 * may be used to endorse or promote products derived from this software
20 * without specific prior written permission.
21 *
22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
23 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
25 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
29 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32 *
33 ******************************************************************************
34 */
35 #if defined(USE_FULL_LL_DRIVER)
36
37 /* Includes ------------------------------------------------------------------*/
38 #include "stm32f4xx_ll_rcc.h"
39 #ifdef USE_FULL_ASSERT
40 #include "stm32_assert.h"
41 #else
42 #define assert_param(expr) ((void)0U)
43 #endif
44 /** @addtogroup STM32F4xx_LL_Driver
45 * @{
46 */
47
48 #if defined(RCC)
49
50 /** @addtogroup RCC_LL
51 * @{
52 */
53
54 /* Private types -------------------------------------------------------------*/
55 /* Private variables ---------------------------------------------------------*/
56 /* Private constants ---------------------------------------------------------*/
57 /* Private macros ------------------------------------------------------------*/
58 /** @addtogroup RCC_LL_Private_Macros
59 * @{
60 */
61 #if defined(FMPI2C1)
62 #define IS_LL_RCC_FMPI2C_CLKSOURCE(__VALUE__) ((__VALUE__) == LL_RCC_FMPI2C1_CLKSOURCE)
63 #endif /* FMPI2C1 */
64
65 #if defined(LPTIM1)
66 #define IS_LL_RCC_LPTIM_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_LPTIM1_CLKSOURCE))
67 #endif /* LPTIM1 */
68
69 #if defined(SAI1)
70 #if defined(RCC_DCKCFGR_SAI1SRC)
71 #define IS_LL_RCC_SAI_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_SAI1_CLKSOURCE) \
72 || ((__VALUE__) == LL_RCC_SAI2_CLKSOURCE))
73 #elif defined(RCC_DCKCFGR_SAI1ASRC)
74 #define IS_LL_RCC_SAI_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_SAI1_A_CLKSOURCE) \
75 || ((__VALUE__) == LL_RCC_SAI1_B_CLKSOURCE))
76 #endif /* RCC_DCKCFGR_SAI1SRC */
77 #endif /* SAI1 */
78
79 #if defined(SDIO)
80 #define IS_LL_RCC_SDIO_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_SDIO_CLKSOURCE))
81 #endif /* SDIO */
82
83 #if defined(RNG)
84 #define IS_LL_RCC_RNG_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_RNG_CLKSOURCE))
85 #endif /* RNG */
86
87 #if defined(USB_OTG_FS) || defined(USB_OTG_HS)
88 #define IS_LL_RCC_USB_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_USB_CLKSOURCE))
89 #endif /* USB_OTG_FS || USB_OTG_HS */
90
91 #if defined(DFSDM2_Channel0)
92 #define IS_LL_RCC_DFSDM_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_DFSDM1_CLKSOURCE))
93
94 #define IS_LL_RCC_DFSDM_AUDIO_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_DFSDM1_AUDIO_CLKSOURCE) \
95 || ((__VALUE__) == LL_RCC_DFSDM2_AUDIO_CLKSOURCE))
96 #elif defined(DFSDM1_Channel0)
97 #define IS_LL_RCC_DFSDM_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_DFSDM1_CLKSOURCE))
98
99 #define IS_LL_RCC_DFSDM_AUDIO_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_DFSDM1_AUDIO_CLKSOURCE))
100 #endif /* DFSDM2_Channel0 */
101
102 #if defined(RCC_DCKCFGR_I2S2SRC)
103 #define IS_LL_RCC_I2S_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_I2S1_CLKSOURCE) \
104 || ((__VALUE__) == LL_RCC_I2S2_CLKSOURCE))
105 #else
106 #define IS_LL_RCC_I2S_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_I2S1_CLKSOURCE))
107 #endif /* RCC_DCKCFGR_I2S2SRC */
108
109 #if defined(CEC)
110 #define IS_LL_RCC_CEC_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_CEC_CLKSOURCE))
111 #endif /* CEC */
112
113 #if defined(DSI)
114 #define IS_LL_RCC_DSI_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_DSI_CLKSOURCE))
115 #endif /* DSI */
116
117 #if defined(LTDC)
118 #define IS_LL_RCC_LTDC_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_LTDC_CLKSOURCE))
119 #endif /* LTDC */
120
121 #if defined(SPDIFRX)
122 #define IS_LL_RCC_SPDIFRX_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_SPDIFRX1_CLKSOURCE))
123 #endif /* SPDIFRX */
124 /**
125 * @}
126 */
127
128 /* Private function prototypes -----------------------------------------------*/
129 /** @defgroup RCC_LL_Private_Functions RCC Private functions
130 * @{
131 */
132 uint32_t RCC_GetSystemClockFreq(void);
133 uint32_t RCC_GetHCLKClockFreq(uint32_t SYSCLK_Frequency);
134 uint32_t RCC_GetPCLK1ClockFreq(uint32_t HCLK_Frequency);
135 uint32_t RCC_GetPCLK2ClockFreq(uint32_t HCLK_Frequency);
136 uint32_t RCC_PLL_GetFreqDomain_SYS(uint32_t SYSCLK_Source);
137 uint32_t RCC_PLL_GetFreqDomain_48M(void);
138 #if defined(RCC_DCKCFGR_I2SSRC) || defined(RCC_DCKCFGR_I2S1SRC)
139 uint32_t RCC_PLL_GetFreqDomain_I2S(void);
140 #endif /* RCC_DCKCFGR_I2SSRC || RCC_DCKCFGR_I2S1SRC */
141 #if defined(SPDIFRX)
142 uint32_t RCC_PLL_GetFreqDomain_SPDIFRX(void);
143 #endif /* SPDIFRX */
144 #if defined(RCC_PLLCFGR_PLLR)
145 #if defined(SAI1)
146 uint32_t RCC_PLL_GetFreqDomain_SAI(void);
147 #endif /* SAI1 */
148 #endif /* RCC_PLLCFGR_PLLR */
149 #if defined(DSI)
150 uint32_t RCC_PLL_GetFreqDomain_DSI(void);
151 #endif /* DSI */
152 #if defined(RCC_PLLSAI_SUPPORT)
153 uint32_t RCC_PLLSAI_GetFreqDomain_SAI(void);
154 #if defined(RCC_PLLSAICFGR_PLLSAIP)
155 uint32_t RCC_PLLSAI_GetFreqDomain_48M(void);
156 #endif /* RCC_PLLSAICFGR_PLLSAIP */
157 #if defined(LTDC)
158 uint32_t RCC_PLLSAI_GetFreqDomain_LTDC(void);
159 #endif /* LTDC */
160 #endif /* RCC_PLLSAI_SUPPORT */
161 #if defined(RCC_PLLI2S_SUPPORT)
162 uint32_t RCC_PLLI2S_GetFreqDomain_I2S(void);
163 #if defined(RCC_PLLI2SCFGR_PLLI2SQ) && !defined(RCC_DCKCFGR_PLLI2SDIVQ)
164 uint32_t RCC_PLLI2S_GetFreqDomain_48M(void);
165 #endif /* RCC_PLLI2SCFGR_PLLI2SQ && !RCC_DCKCFGR_PLLI2SDIVQ */
166 #if defined(SAI1)
167 uint32_t RCC_PLLI2S_GetFreqDomain_SAI(void);
168 #endif /* SAI1 */
169 #if defined(SPDIFRX)
170 uint32_t RCC_PLLI2S_GetFreqDomain_SPDIFRX(void);
171 #endif /* SPDIFRX */
172 #endif /* RCC_PLLI2S_SUPPORT */
173 /**
174 * @}
175 */
176
177
178 /* Exported functions --------------------------------------------------------*/
179 /** @addtogroup RCC_LL_Exported_Functions
180 * @{
181 */
182
183 /** @addtogroup RCC_LL_EF_Init
184 * @{
185 */
186
187 /**
188 * @brief Reset the RCC clock configuration to the default reset state.
189 * @note The default reset state of the clock configuration is given below:
190 * - HSI ON and used as system clock source
191 * - HSE and PLL OFF
192 * - AHB, APB1 and APB2 prescaler set to 1.
193 * - CSS, MCO OFF
194 * - All interrupts disabled
195 * @note This function doesn't modify the configuration of the
196 * - Peripheral clocks
197 * - LSI, LSE and RTC clocks
198 * @retval An ErrorStatus enumeration value:
199 * - SUCCESS: RCC registers are de-initialized
200 * - ERROR: not applicable
201 */
202 ErrorStatus LL_RCC_DeInit(void)
203 {
204 uint32_t vl_mask = 0U;
205
206 /* Set HSION bit */
207 LL_RCC_HSI_Enable();
208
209 /* Wait for HSI READY bit */
210 while(LL_RCC_HSI_IsReady() != 1U)
211 {}
212
213 /* Reset CFGR register */
214 LL_RCC_WriteReg(CFGR, 0x00000000U);
215
216 vl_mask = 0xFFFFFFFFU;
217
218 /* Reset HSEON, PLLSYSON bits */
219 CLEAR_BIT(vl_mask, (RCC_CR_HSEON | RCC_CR_HSEBYP | RCC_CR_PLLON | RCC_CR_CSSON));
220
221 #if defined(RCC_PLLSAI_SUPPORT)
222 /* Reset PLLSAION bit */
223 CLEAR_BIT(vl_mask, RCC_CR_PLLSAION);
224 #endif /* RCC_PLLSAI_SUPPORT */
225
226 #if defined(RCC_PLLI2S_SUPPORT)
227 /* Reset PLLI2SON bit */
228 CLEAR_BIT(vl_mask, RCC_CR_PLLI2SON);
229 #endif /* RCC_PLLI2S_SUPPORT */
230
231 /* Write new mask in CR register */
232 LL_RCC_WriteReg(CR, vl_mask);
233
234 /* Set HSITRIM bits to the reset value*/
235 LL_RCC_HSI_SetCalibTrimming(0x10U);
236
237 /* Wait for PLL READY bit to be reset */
238 while(LL_RCC_PLL_IsReady() != 0U)
239 {}
240
241 /* Reset PLLCFGR register */
242 LL_RCC_WriteReg(PLLCFGR, RCC_PLLCFGR_RST_VALUE);
243
244 #if defined(RCC_PLLI2S_SUPPORT)
245 /* Reset PLLI2SCFGR register */
246 LL_RCC_WriteReg(PLLI2SCFGR, RCC_PLLI2SCFGR_RST_VALUE);
247 #endif /* RCC_PLLI2S_SUPPORT */
248
249 #if defined(RCC_PLLSAI_SUPPORT)
250 /* Reset PLLSAICFGR register */
251 LL_RCC_WriteReg(PLLSAICFGR, RCC_PLLSAICFGR_RST_VALUE);
252 #endif /* RCC_PLLSAI_SUPPORT */
253
254 /* Disable all interrupts */
255 CLEAR_BIT(RCC->CIR, RCC_CIR_LSIRDYIE | RCC_CIR_LSERDYIE | RCC_CIR_HSIRDYIE | RCC_CIR_HSERDYIE | RCC_CIR_PLLRDYIE);
256
257 #if defined(RCC_CIR_PLLI2SRDYIE)
258 CLEAR_BIT(RCC->CIR, RCC_CIR_PLLI2SRDYIE);
259 #endif /* RCC_CIR_PLLI2SRDYIE */
260
261 #if defined(RCC_CIR_PLLSAIRDYIE)
262 CLEAR_BIT(RCC->CIR, RCC_CIR_PLLSAIRDYIE);
263 #endif /* RCC_CIR_PLLSAIRDYIE */
264
265 /* Clear all interrupt flags */
266 SET_BIT(RCC->CIR, RCC_CIR_LSIRDYC | RCC_CIR_LSERDYC | RCC_CIR_HSIRDYC | RCC_CIR_HSERDYC | RCC_CIR_PLLRDYC | RCC_CIR_CSSC);
267
268 #if defined(RCC_CIR_PLLI2SRDYC)
269 SET_BIT(RCC->CIR, RCC_CIR_PLLI2SRDYC);
270 #endif /* RCC_CIR_PLLI2SRDYC */
271
272 #if defined(RCC_CIR_PLLSAIRDYC)
273 SET_BIT(RCC->CIR, RCC_CIR_PLLSAIRDYC);
274 #endif /* RCC_CIR_PLLSAIRDYC */
275
276 /* Clear LSION bit */
277 CLEAR_BIT(RCC->CSR, RCC_CSR_LSION);
278
279 /* Reset all CSR flags */
280 SET_BIT(RCC->CSR, RCC_CSR_RMVF);
281
282 return SUCCESS;
283 }
284
285 /**
286 * @}
287 */
288
289 /** @addtogroup RCC_LL_EF_Get_Freq
290 * @brief Return the frequencies of different on chip clocks; System, AHB, APB1 and APB2 buses clocks
291 * and different peripheral clocks available on the device.
292 * @note If SYSCLK source is HSI, function returns values based on HSI_VALUE(**)
293 * @note If SYSCLK source is HSE, function returns values based on HSE_VALUE(***)
294 * @note If SYSCLK source is PLL, function returns values based on HSE_VALUE(***)
295 * or HSI_VALUE(**) multiplied/divided by the PLL factors.
296 * @note (**) HSI_VALUE is a constant defined in this file (default value
297 * 16 MHz) but the real value may vary depending on the variations
298 * in voltage and temperature.
299 * @note (***) HSE_VALUE is a constant defined in this file (default value
300 * 25 MHz), user has to ensure that HSE_VALUE is same as the real
301 * frequency of the crystal used. Otherwise, this function may
302 * have wrong result.
303 * @note The result of this function could be incorrect when using fractional
304 * value for HSE crystal.
305 * @note This function can be used by the user application to compute the
306 * baud-rate for the communication peripherals or configure other parameters.
307 * @{
308 */
309
310 /**
311 * @brief Return the frequencies of different on chip clocks; System, AHB, APB1 and APB2 buses clocks
312 * @note Each time SYSCLK, HCLK, PCLK1 and/or PCLK2 clock changes, this function
313 * must be called to update structure fields. Otherwise, any
314 * configuration based on this function will be incorrect.
315 * @param RCC_Clocks pointer to a @ref LL_RCC_ClocksTypeDef structure which will hold the clocks frequencies
316 * @retval None
317 */
318 void LL_RCC_GetSystemClocksFreq(LL_RCC_ClocksTypeDef *RCC_Clocks)
319 {
320 /* Get SYSCLK frequency */
321 RCC_Clocks->SYSCLK_Frequency = RCC_GetSystemClockFreq();
322
323 /* HCLK clock frequency */
324 RCC_Clocks->HCLK_Frequency = RCC_GetHCLKClockFreq(RCC_Clocks->SYSCLK_Frequency);
325
326 /* PCLK1 clock frequency */
327 RCC_Clocks->PCLK1_Frequency = RCC_GetPCLK1ClockFreq(RCC_Clocks->HCLK_Frequency);
328
329 /* PCLK2 clock frequency */
330 RCC_Clocks->PCLK2_Frequency = RCC_GetPCLK2ClockFreq(RCC_Clocks->HCLK_Frequency);
331 }
332
333 #if defined(FMPI2C1)
334 /**
335 * @brief Return FMPI2Cx clock frequency
336 * @param FMPI2CxSource This parameter can be one of the following values:
337 * @arg @ref LL_RCC_FMPI2C1_CLKSOURCE
338 * @retval FMPI2C clock frequency (in Hz)
339 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that HSI oscillator is not ready
340 */
341 uint32_t LL_RCC_GetFMPI2CClockFreq(uint32_t FMPI2CxSource)
342 {
343 uint32_t FMPI2C_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
344
345 /* Check parameter */
346 assert_param(IS_LL_RCC_FMPI2C_CLKSOURCE(FMPI2CxSource));
347
348 if (FMPI2CxSource == LL_RCC_FMPI2C1_CLKSOURCE)
349 {
350 /* FMPI2C1 CLK clock frequency */
351 switch (LL_RCC_GetFMPI2CClockSource(FMPI2CxSource))
352 {
353 case LL_RCC_FMPI2C1_CLKSOURCE_SYSCLK: /* FMPI2C1 Clock is System Clock */
354 FMPI2C_frequency = RCC_GetSystemClockFreq();
355 break;
356
357 case LL_RCC_FMPI2C1_CLKSOURCE_HSI: /* FMPI2C1 Clock is HSI Osc. */
358 if (LL_RCC_HSI_IsReady())
359 {
360 FMPI2C_frequency = HSI_VALUE;
361 }
362 break;
363
364 case LL_RCC_FMPI2C1_CLKSOURCE_PCLK1: /* FMPI2C1 Clock is PCLK1 */
365 default:
366 FMPI2C_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
367 break;
368 }
369 }
370
371 return FMPI2C_frequency;
372 }
373 #endif /* FMPI2C1 */
374
375 /**
376 * @brief Return I2Sx clock frequency
377 * @param I2SxSource This parameter can be one of the following values:
378 * @arg @ref LL_RCC_I2S1_CLKSOURCE
379 * @arg @ref LL_RCC_I2S2_CLKSOURCE (*)
380 *
381 * (*) value not defined in all devices.
382 * @retval I2S clock frequency (in Hz)
383 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
384 */
385 uint32_t LL_RCC_GetI2SClockFreq(uint32_t I2SxSource)
386 {
387 uint32_t i2s_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
388
389 /* Check parameter */
390 assert_param(IS_LL_RCC_I2S_CLKSOURCE(I2SxSource));
391
392 if (I2SxSource == LL_RCC_I2S1_CLKSOURCE)
393 {
394 /* I2S1 CLK clock frequency */
395 switch (LL_RCC_GetI2SClockSource(I2SxSource))
396 {
397 #if defined(RCC_PLLI2S_SUPPORT)
398 case LL_RCC_I2S1_CLKSOURCE_PLLI2S: /* I2S1 Clock is PLLI2S */
399 if (LL_RCC_PLLI2S_IsReady())
400 {
401 i2s_frequency = RCC_PLLI2S_GetFreqDomain_I2S();
402 }
403 break;
404 #endif /* RCC_PLLI2S_SUPPORT */
405
406 #if defined(RCC_DCKCFGR_I2SSRC) || defined(RCC_DCKCFGR_I2S1SRC)
407 case LL_RCC_I2S1_CLKSOURCE_PLL: /* I2S1 Clock is PLL */
408 if (LL_RCC_PLL_IsReady())
409 {
410 i2s_frequency = RCC_PLL_GetFreqDomain_I2S();
411 }
412 break;
413
414 case LL_RCC_I2S1_CLKSOURCE_PLLSRC: /* I2S1 Clock is PLL Main source */
415 switch (LL_RCC_PLL_GetMainSource())
416 {
417 case LL_RCC_PLLSOURCE_HSE: /* I2S1 Clock is HSE Osc. */
418 if (LL_RCC_HSE_IsReady())
419 {
420 i2s_frequency = HSE_VALUE;
421 }
422 break;
423
424 case LL_RCC_PLLSOURCE_HSI: /* I2S1 Clock is HSI Osc. */
425 default:
426 if (LL_RCC_HSI_IsReady())
427 {
428 i2s_frequency = HSI_VALUE;
429 }
430 break;
431 }
432 break;
433 #endif /* RCC_DCKCFGR_I2SSRC || RCC_DCKCFGR_I2S1SRC */
434
435 case LL_RCC_I2S1_CLKSOURCE_PIN: /* I2S1 Clock is External clock */
436 default:
437 i2s_frequency = EXTERNAL_CLOCK_VALUE;
438 break;
439 }
440 }
441 #if defined(RCC_DCKCFGR_I2S2SRC)
442 else
443 {
444 /* I2S2 CLK clock frequency */
445 switch (LL_RCC_GetI2SClockSource(I2SxSource))
446 {
447 case LL_RCC_I2S2_CLKSOURCE_PLLI2S: /* I2S2 Clock is PLLI2S */
448 if (LL_RCC_PLLI2S_IsReady())
449 {
450 i2s_frequency = RCC_PLLI2S_GetFreqDomain_I2S();
451 }
452 break;
453
454 case LL_RCC_I2S2_CLKSOURCE_PLL: /* I2S2 Clock is PLL */
455 if (LL_RCC_PLL_IsReady())
456 {
457 i2s_frequency = RCC_PLL_GetFreqDomain_I2S();
458 }
459 break;
460
461 case LL_RCC_I2S2_CLKSOURCE_PLLSRC: /* I2S2 Clock is PLL Main source */
462 switch (LL_RCC_PLL_GetMainSource())
463 {
464 case LL_RCC_PLLSOURCE_HSE: /* I2S2 Clock is HSE Osc. */
465 if (LL_RCC_HSE_IsReady())
466 {
467 i2s_frequency = HSE_VALUE;
468 }
469 break;
470
471 case LL_RCC_PLLSOURCE_HSI: /* I2S2 Clock is HSI Osc. */
472 default:
473 if (LL_RCC_HSI_IsReady())
474 {
475 i2s_frequency = HSI_VALUE;
476 }
477 break;
478 }
479 break;
480
481 case LL_RCC_I2S2_CLKSOURCE_PIN: /* I2S2 Clock is External clock */
482 default:
483 i2s_frequency = EXTERNAL_CLOCK_VALUE;
484 break;
485 }
486 }
487 #endif /* RCC_DCKCFGR_I2S2SRC */
488
489 return i2s_frequency;
490 }
491
492 #if defined(LPTIM1)
493 /**
494 * @brief Return LPTIMx clock frequency
495 * @param LPTIMxSource This parameter can be one of the following values:
496 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE
497 * @retval LPTIM clock frequency (in Hz)
498 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI, LSI or LSE) is not ready
499 */
500 uint32_t LL_RCC_GetLPTIMClockFreq(uint32_t LPTIMxSource)
501 {
502 uint32_t lptim_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
503
504 /* Check parameter */
505 assert_param(IS_LL_RCC_LPTIM_CLKSOURCE(LPTIMxSource));
506
507 if (LPTIMxSource == LL_RCC_LPTIM1_CLKSOURCE)
508 {
509 /* LPTIM1CLK clock frequency */
510 switch (LL_RCC_GetLPTIMClockSource(LPTIMxSource))
511 {
512 case LL_RCC_LPTIM1_CLKSOURCE_LSI: /* LPTIM1 Clock is LSI Osc. */
513 if (LL_RCC_LSI_IsReady())
514 {
515 lptim_frequency = LSI_VALUE;
516 }
517 break;
518
519 case LL_RCC_LPTIM1_CLKSOURCE_HSI: /* LPTIM1 Clock is HSI Osc. */
520 if (LL_RCC_HSI_IsReady())
521 {
522 lptim_frequency = HSI_VALUE;
523 }
524 break;
525
526 case LL_RCC_LPTIM1_CLKSOURCE_LSE: /* LPTIM1 Clock is LSE Osc. */
527 if (LL_RCC_LSE_IsReady())
528 {
529 lptim_frequency = LSE_VALUE;
530 }
531 break;
532
533 case LL_RCC_LPTIM1_CLKSOURCE_PCLK1: /* LPTIM1 Clock is PCLK1 */
534 default:
535 lptim_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
536 break;
537 }
538 }
539
540 return lptim_frequency;
541 }
542 #endif /* LPTIM1 */
543
544 #if defined(SAI1)
545 /**
546 * @brief Return SAIx clock frequency
547 * @param SAIxSource This parameter can be one of the following values:
548 * @arg @ref LL_RCC_SAI1_CLKSOURCE (*)
549 * @arg @ref LL_RCC_SAI2_CLKSOURCE (*)
550 * @arg @ref LL_RCC_SAI1_A_CLKSOURCE (*)
551 * @arg @ref LL_RCC_SAI1_B_CLKSOURCE (*)
552 *
553 * (*) value not defined in all devices.
554 * @retval SAI clock frequency (in Hz)
555 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
556 */
557 uint32_t LL_RCC_GetSAIClockFreq(uint32_t SAIxSource)
558 {
559 uint32_t sai_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
560
561 /* Check parameter */
562 assert_param(IS_LL_RCC_SAI_CLKSOURCE(SAIxSource));
563
564 #if defined(RCC_DCKCFGR_SAI1SRC)
565 if ((SAIxSource == LL_RCC_SAI1_CLKSOURCE) || (SAIxSource == LL_RCC_SAI2_CLKSOURCE))
566 {
567 /* SAI1CLK clock frequency */
568 switch (LL_RCC_GetSAIClockSource(SAIxSource))
569 {
570 case LL_RCC_SAI1_CLKSOURCE_PLLSAI: /* PLLSAI clock used as SAI1 clock source */
571 case LL_RCC_SAI2_CLKSOURCE_PLLSAI: /* PLLSAI clock used as SAI2 clock source */
572 if (LL_RCC_PLLSAI_IsReady())
573 {
574 sai_frequency = RCC_PLLSAI_GetFreqDomain_SAI();
575 }
576 break;
577
578 case LL_RCC_SAI1_CLKSOURCE_PLLI2S: /* PLLI2S clock used as SAI1 clock source */
579 case LL_RCC_SAI2_CLKSOURCE_PLLI2S: /* PLLI2S clock used as SAI2 clock source */
580 if (LL_RCC_PLLI2S_IsReady())
581 {
582 sai_frequency = RCC_PLLI2S_GetFreqDomain_SAI();
583 }
584 break;
585
586 case LL_RCC_SAI1_CLKSOURCE_PLL: /* PLL clock used as SAI1 clock source */
587 case LL_RCC_SAI2_CLKSOURCE_PLL: /* PLL clock used as SAI2 clock source */
588 if (LL_RCC_PLL_IsReady())
589 {
590 sai_frequency = RCC_PLL_GetFreqDomain_SAI();
591 }
592 break;
593
594 case LL_RCC_SAI2_CLKSOURCE_PLLSRC:
595 switch (LL_RCC_PLL_GetMainSource())
596 {
597 case LL_RCC_PLLSOURCE_HSE: /* HSE clock used as SAI2 clock source */
598 if (LL_RCC_HSE_IsReady())
599 {
600 sai_frequency = HSE_VALUE;
601 }
602 break;
603
604 case LL_RCC_PLLSOURCE_HSI: /* HSI clock used as SAI2 clock source */
605 default:
606 if (LL_RCC_HSI_IsReady())
607 {
608 sai_frequency = HSI_VALUE;
609 }
610 break;
611 }
612 break;
613
614 case LL_RCC_SAI1_CLKSOURCE_PIN: /* External input clock used as SAI1 clock source */
615 default:
616 sai_frequency = EXTERNAL_CLOCK_VALUE;
617 break;
618 }
619 }
620 #endif /* RCC_DCKCFGR_SAI1SRC */
621 #if defined(RCC_DCKCFGR_SAI1ASRC)
622 if ((SAIxSource == LL_RCC_SAI1_A_CLKSOURCE) || (SAIxSource == LL_RCC_SAI1_B_CLKSOURCE))
623 {
624 /* SAI1CLK clock frequency */
625 switch (LL_RCC_GetSAIClockSource(SAIxSource))
626 {
627 #if defined(RCC_PLLSAI_SUPPORT)
628 case LL_RCC_SAI1_A_CLKSOURCE_PLLSAI: /* PLLSAI clock used as SAI1 Block A clock source */
629 case LL_RCC_SAI1_B_CLKSOURCE_PLLSAI: /* PLLSAI clock used as SAI1 Block B clock source */
630 if (LL_RCC_PLLSAI_IsReady())
631 {
632 sai_frequency = RCC_PLLSAI_GetFreqDomain_SAI();
633 }
634 break;
635 #endif /* RCC_PLLSAI_SUPPORT */
636
637 case LL_RCC_SAI1_A_CLKSOURCE_PLLI2S: /* PLLI2S clock used as SAI1 Block A clock source */
638 case LL_RCC_SAI1_B_CLKSOURCE_PLLI2S: /* PLLI2S clock used as SAI1 Block B clock source */
639 if (LL_RCC_PLLI2S_IsReady())
640 {
641 sai_frequency = RCC_PLLI2S_GetFreqDomain_SAI();
642 }
643 break;
644
645 #if defined(RCC_SAI1A_PLLSOURCE_SUPPORT)
646 case LL_RCC_SAI1_A_CLKSOURCE_PLL: /* PLL clock used as SAI1 Block A clock source */
647 case LL_RCC_SAI1_B_CLKSOURCE_PLL: /* PLL clock used as SAI1 Block B clock source */
648 if (LL_RCC_PLL_IsReady())
649 {
650 sai_frequency = RCC_PLL_GetFreqDomain_SAI();
651 }
652 break;
653
654 case LL_RCC_SAI1_A_CLKSOURCE_PLLSRC:
655 case LL_RCC_SAI1_B_CLKSOURCE_PLLSRC:
656 switch (LL_RCC_PLL_GetMainSource())
657 {
658 case LL_RCC_PLLSOURCE_HSE: /* HSE clock used as SAI1 Block A or B clock source */
659 if (LL_RCC_HSE_IsReady())
660 {
661 sai_frequency = HSE_VALUE;
662 }
663 break;
664
665 case LL_RCC_PLLSOURCE_HSI: /* HSI clock used as SAI1 Block A or B clock source */
666 default:
667 if (LL_RCC_HSI_IsReady())
668 {
669 sai_frequency = HSI_VALUE;
670 }
671 break;
672 }
673 break;
674 #endif /* RCC_SAI1A_PLLSOURCE_SUPPORT */
675
676 case LL_RCC_SAI1_A_CLKSOURCE_PIN: /* External input clock used as SAI1 Block A clock source */
677 case LL_RCC_SAI1_B_CLKSOURCE_PIN: /* External input clock used as SAI1 Block B clock source */
678 default:
679 sai_frequency = EXTERNAL_CLOCK_VALUE;
680 break;
681 }
682 }
683 #endif /* RCC_DCKCFGR_SAI1ASRC */
684
685 return sai_frequency;
686 }
687 #endif /* SAI1 */
688
689 #if defined(SDIO)
690 /**
691 * @brief Return SDIOx clock frequency
692 * @param SDIOxSource This parameter can be one of the following values:
693 * @arg @ref LL_RCC_SDIO_CLKSOURCE
694 * @retval SDIO clock frequency (in Hz)
695 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
696 */
697 uint32_t LL_RCC_GetSDIOClockFreq(uint32_t SDIOxSource)
698 {
699 uint32_t SDIO_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
700
701 /* Check parameter */
702 assert_param(IS_LL_RCC_SDIO_CLKSOURCE(SDIOxSource));
703
704 if (SDIOxSource == LL_RCC_SDIO_CLKSOURCE)
705 {
706 #if defined(RCC_DCKCFGR_SDIOSEL) || defined(RCC_DCKCFGR2_SDIOSEL)
707 /* SDIOCLK clock frequency */
708 switch (LL_RCC_GetSDIOClockSource(SDIOxSource))
709 {
710 case LL_RCC_SDIO_CLKSOURCE_PLL48CLK: /* PLL48M clock used as SDIO clock source */
711 switch (LL_RCC_GetCK48MClockSource(LL_RCC_CK48M_CLKSOURCE))
712 {
713 case LL_RCC_CK48M_CLKSOURCE_PLL: /* PLL clock used as 48Mhz domain clock */
714 if (LL_RCC_PLL_IsReady())
715 {
716 SDIO_frequency = RCC_PLL_GetFreqDomain_48M();
717 }
718 break;
719
720 #if defined(RCC_PLLSAI_SUPPORT)
721 case LL_RCC_CK48M_CLKSOURCE_PLLSAI: /* PLLSAI clock used as 48Mhz domain clock */
722 default:
723 if (LL_RCC_PLLSAI_IsReady())
724 {
725 SDIO_frequency = RCC_PLLSAI_GetFreqDomain_48M();
726 }
727 break;
728 #endif /* RCC_PLLSAI_SUPPORT */
729
730 #if defined(RCC_PLLI2SCFGR_PLLI2SQ) && !defined(RCC_DCKCFGR_PLLI2SDIVQ)
731 case LL_RCC_CK48M_CLKSOURCE_PLLI2S: /* PLLI2S clock used as 48Mhz domain clock */
732 default:
733 if (LL_RCC_PLLI2S_IsReady())
734 {
735 SDIO_frequency = RCC_PLLI2S_GetFreqDomain_48M();
736 }
737 break;
738 #endif /* RCC_PLLI2SCFGR_PLLI2SQ && !RCC_DCKCFGR_PLLI2SDIVQ */
739 }
740 break;
741
742 case LL_RCC_SDIO_CLKSOURCE_SYSCLK: /* PLL clock used as SDIO clock source */
743 default:
744 SDIO_frequency = RCC_GetSystemClockFreq();
745 break;
746 }
747 #else
748 /* PLL clock used as 48Mhz domain clock */
749 if (LL_RCC_PLL_IsReady())
750 {
751 SDIO_frequency = RCC_PLL_GetFreqDomain_48M();
752 }
753 #endif /* RCC_DCKCFGR_SDIOSEL || RCC_DCKCFGR2_SDIOSEL */
754 }
755
756 return SDIO_frequency;
757 }
758 #endif /* SDIO */
759
760 #if defined(RNG)
761 /**
762 * @brief Return RNGx clock frequency
763 * @param RNGxSource This parameter can be one of the following values:
764 * @arg @ref LL_RCC_RNG_CLKSOURCE
765 * @retval RNG clock frequency (in Hz)
766 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
767 */
768 uint32_t LL_RCC_GetRNGClockFreq(uint32_t RNGxSource)
769 {
770 uint32_t rng_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
771
772 /* Check parameter */
773 assert_param(IS_LL_RCC_RNG_CLKSOURCE(RNGxSource));
774
775 #if defined(RCC_DCKCFGR_CK48MSEL) || defined(RCC_DCKCFGR2_CK48MSEL)
776 /* RNGCLK clock frequency */
777 switch (LL_RCC_GetRNGClockSource(RNGxSource))
778 {
779 #if defined(RCC_PLLI2SCFGR_PLLI2SQ) && !defined(RCC_DCKCFGR_PLLI2SDIVQ)
780 case LL_RCC_RNG_CLKSOURCE_PLLI2S: /* PLLI2S clock used as RNG clock source */
781 if (LL_RCC_PLLI2S_IsReady())
782 {
783 rng_frequency = RCC_PLLI2S_GetFreqDomain_48M();
784 }
785 break;
786 #endif /* RCC_PLLI2SCFGR_PLLI2SQ && !RCC_DCKCFGR_PLLI2SDIVQ */
787
788 #if defined(RCC_PLLSAI_SUPPORT)
789 case LL_RCC_RNG_CLKSOURCE_PLLSAI: /* PLLSAI clock used as RNG clock source */
790 if (LL_RCC_PLLSAI_IsReady())
791 {
792 rng_frequency = RCC_PLLSAI_GetFreqDomain_48M();
793 }
794 break;
795 #endif /* RCC_PLLSAI_SUPPORT */
796
797 case LL_RCC_RNG_CLKSOURCE_PLL: /* PLL clock used as RNG clock source */
798 default:
799 if (LL_RCC_PLL_IsReady())
800 {
801 rng_frequency = RCC_PLL_GetFreqDomain_48M();
802 }
803 break;
804 }
805 #else
806 /* PLL clock used as RNG clock source */
807 if (LL_RCC_PLL_IsReady())
808 {
809 rng_frequency = RCC_PLL_GetFreqDomain_48M();
810 }
811 #endif /* RCC_DCKCFGR_CK48MSEL || RCC_DCKCFGR2_CK48MSEL */
812
813 return rng_frequency;
814 }
815 #endif /* RNG */
816
817 #if defined(CEC)
818 /**
819 * @brief Return CEC clock frequency
820 * @param CECxSource This parameter can be one of the following values:
821 * @arg @ref LL_RCC_CEC_CLKSOURCE
822 * @retval CEC clock frequency (in Hz)
823 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI or LSE) is not ready
824 */
825 uint32_t LL_RCC_GetCECClockFreq(uint32_t CECxSource)
826 {
827 uint32_t cec_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
828
829 /* Check parameter */
830 assert_param(IS_LL_RCC_CEC_CLKSOURCE(CECxSource));
831
832 /* CECCLK clock frequency */
833 switch (LL_RCC_GetCECClockSource(CECxSource))
834 {
835 case LL_RCC_CEC_CLKSOURCE_LSE: /* CEC Clock is LSE Osc. */
836 if (LL_RCC_LSE_IsReady())
837 {
838 cec_frequency = LSE_VALUE;
839 }
840 break;
841
842 case LL_RCC_CEC_CLKSOURCE_HSI_DIV488: /* CEC Clock is HSI Osc. */
843 default:
844 if (LL_RCC_HSI_IsReady())
845 {
846 cec_frequency = HSI_VALUE/488U;
847 }
848 break;
849 }
850
851 return cec_frequency;
852 }
853 #endif /* CEC */
854
855 #if defined(USB_OTG_FS) || defined(USB_OTG_HS)
856 /**
857 * @brief Return USBx clock frequency
858 * @param USBxSource This parameter can be one of the following values:
859 * @arg @ref LL_RCC_USB_CLKSOURCE
860 * @retval USB clock frequency (in Hz)
861 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
862 */
863 uint32_t LL_RCC_GetUSBClockFreq(uint32_t USBxSource)
864 {
865 uint32_t usb_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
866
867 /* Check parameter */
868 assert_param(IS_LL_RCC_USB_CLKSOURCE(USBxSource));
869
870 #if defined(RCC_DCKCFGR_CK48MSEL) || defined(RCC_DCKCFGR2_CK48MSEL)
871 /* USBCLK clock frequency */
872 switch (LL_RCC_GetUSBClockSource(USBxSource))
873 {
874 #if defined(RCC_PLLI2SCFGR_PLLI2SQ) && !defined(RCC_DCKCFGR_PLLI2SDIVQ)
875 case LL_RCC_USB_CLKSOURCE_PLLI2S: /* PLLI2S clock used as USB clock source */
876 if (LL_RCC_PLLI2S_IsReady())
877 {
878 usb_frequency = RCC_PLLI2S_GetFreqDomain_48M();
879 }
880 break;
881
882 #endif /* RCC_PLLI2SCFGR_PLLI2SQ && !RCC_DCKCFGR_PLLI2SDIVQ */
883
884 #if defined(RCC_PLLSAI_SUPPORT)
885 case LL_RCC_USB_CLKSOURCE_PLLSAI: /* PLLSAI clock used as USB clock source */
886 if (LL_RCC_PLLSAI_IsReady())
887 {
888 usb_frequency = RCC_PLLSAI_GetFreqDomain_48M();
889 }
890 break;
891 #endif /* RCC_PLLSAI_SUPPORT */
892
893 case LL_RCC_USB_CLKSOURCE_PLL: /* PLL clock used as USB clock source */
894 default:
895 if (LL_RCC_PLL_IsReady())
896 {
897 usb_frequency = RCC_PLL_GetFreqDomain_48M();
898 }
899 break;
900 }
901 #else
902 /* PLL clock used as USB clock source */
903 if (LL_RCC_PLL_IsReady())
904 {
905 usb_frequency = RCC_PLL_GetFreqDomain_48M();
906 }
907 #endif /* RCC_DCKCFGR_CK48MSEL || RCC_DCKCFGR2_CK48MSEL */
908
909 return usb_frequency;
910 }
911 #endif /* USB_OTG_FS || USB_OTG_HS */
912
913 #if defined(DFSDM1_Channel0)
914 /**
915 * @brief Return DFSDMx clock frequency
916 * @param DFSDMxSource This parameter can be one of the following values:
917 * @arg @ref LL_RCC_DFSDM1_CLKSOURCE
918 * @arg @ref LL_RCC_DFSDM2_CLKSOURCE (*)
919 *
920 * (*) value not defined in all devices.
921 * @retval DFSDM clock frequency (in Hz)
922 */
923 uint32_t LL_RCC_GetDFSDMClockFreq(uint32_t DFSDMxSource)
924 {
925 uint32_t dfsdm_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
926
927 /* Check parameter */
928 assert_param(IS_LL_RCC_DFSDM_CLKSOURCE(DFSDMxSource));
929
930 if (DFSDMxSource == LL_RCC_DFSDM1_CLKSOURCE)
931 {
932 /* DFSDM1CLK clock frequency */
933 switch (LL_RCC_GetDFSDMClockSource(DFSDMxSource))
934 {
935 case LL_RCC_DFSDM1_CLKSOURCE_SYSCLK: /* DFSDM1 Clock is SYSCLK */
936 dfsdm_frequency = RCC_GetSystemClockFreq();
937 break;
938
939 case LL_RCC_DFSDM1_CLKSOURCE_PCLK2: /* DFSDM1 Clock is PCLK2 */
940 default:
941 dfsdm_frequency = RCC_GetPCLK2ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
942 break;
943 }
944 }
945 #if defined(DFSDM2_Channel0)
946 else
947 {
948 /* DFSDM2CLK clock frequency */
949 switch (LL_RCC_GetDFSDMClockSource(DFSDMxSource))
950 {
951 case LL_RCC_DFSDM2_CLKSOURCE_SYSCLK: /* DFSDM2 Clock is SYSCLK */
952 dfsdm_frequency = RCC_GetSystemClockFreq();
953 break;
954
955 case LL_RCC_DFSDM2_CLKSOURCE_PCLK2: /* DFSDM2 Clock is PCLK2 */
956 default:
957 dfsdm_frequency = RCC_GetPCLK2ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
958 break;
959 }
960 }
961 #endif /* DFSDM2_Channel0 */
962
963 return dfsdm_frequency;
964 }
965
966 /**
967 * @brief Return DFSDMx Audio clock frequency
968 * @param DFSDMxSource This parameter can be one of the following values:
969 * @arg @ref LL_RCC_DFSDM1_AUDIO_CLKSOURCE
970 * @arg @ref LL_RCC_DFSDM2_AUDIO_CLKSOURCE (*)
971 *
972 * (*) value not defined in all devices.
973 * @retval DFSDM clock frequency (in Hz)
974 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
975 */
976 uint32_t LL_RCC_GetDFSDMAudioClockFreq(uint32_t DFSDMxSource)
977 {
978 uint32_t dfsdm_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
979
980 /* Check parameter */
981 assert_param(IS_LL_RCC_DFSDM_AUDIO_CLKSOURCE(DFSDMxSource));
982
983 if (DFSDMxSource == LL_RCC_DFSDM1_AUDIO_CLKSOURCE)
984 {
985 /* DFSDM1CLK clock frequency */
986 switch (LL_RCC_GetDFSDMAudioClockSource(DFSDMxSource))
987 {
988 case LL_RCC_DFSDM1_AUDIO_CLKSOURCE_I2S1: /* I2S1 clock used as DFSDM1 clock */
989 dfsdm_frequency = LL_RCC_GetI2SClockFreq(LL_RCC_I2S1_CLKSOURCE);
990 break;
991
992 case LL_RCC_DFSDM1_AUDIO_CLKSOURCE_I2S2: /* I2S2 clock used as DFSDM1 clock */
993 default:
994 dfsdm_frequency = LL_RCC_GetI2SClockFreq(LL_RCC_I2S2_CLKSOURCE);
995 break;
996 }
997 }
998 #if defined(DFSDM2_Channel0)
999 else
1000 {
1001 /* DFSDM2CLK clock frequency */
1002 switch (LL_RCC_GetDFSDMAudioClockSource(DFSDMxSource))
1003 {
1004 case LL_RCC_DFSDM2_AUDIO_CLKSOURCE_I2S1: /* I2S1 clock used as DFSDM2 clock */
1005 dfsdm_frequency = LL_RCC_GetI2SClockFreq(LL_RCC_I2S1_CLKSOURCE);
1006 break;
1007
1008 case LL_RCC_DFSDM2_AUDIO_CLKSOURCE_I2S2: /* I2S2 clock used as DFSDM2 clock */
1009 default:
1010 dfsdm_frequency = LL_RCC_GetI2SClockFreq(LL_RCC_I2S2_CLKSOURCE);
1011 break;
1012 }
1013 }
1014 #endif /* DFSDM2_Channel0 */
1015
1016 return dfsdm_frequency;
1017 }
1018 #endif /* DFSDM1_Channel0 */
1019
1020 #if defined(DSI)
1021 /**
1022 * @brief Return DSI clock frequency
1023 * @param DSIxSource This parameter can be one of the following values:
1024 * @arg @ref LL_RCC_DSI_CLKSOURCE
1025 * @retval DSI clock frequency (in Hz)
1026 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
1027 * - @ref LL_RCC_PERIPH_FREQUENCY_NA indicates that external clock is used
1028 */
1029 uint32_t LL_RCC_GetDSIClockFreq(uint32_t DSIxSource)
1030 {
1031 uint32_t dsi_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
1032
1033 /* Check parameter */
1034 assert_param(IS_LL_RCC_DSI_CLKSOURCE(DSIxSource));
1035
1036 /* DSICLK clock frequency */
1037 switch (LL_RCC_GetDSIClockSource(DSIxSource))
1038 {
1039 case LL_RCC_DSI_CLKSOURCE_PLL: /* DSI Clock is PLL Osc. */
1040 if (LL_RCC_PLL_IsReady())
1041 {
1042 dsi_frequency = RCC_PLL_GetFreqDomain_DSI();
1043 }
1044 break;
1045
1046 case LL_RCC_DSI_CLKSOURCE_PHY: /* DSI Clock is DSI physical clock. */
1047 default:
1048 dsi_frequency = LL_RCC_PERIPH_FREQUENCY_NA;
1049 break;
1050 }
1051
1052 return dsi_frequency;
1053 }
1054 #endif /* DSI */
1055
1056 #if defined(LTDC)
1057 /**
1058 * @brief Return LTDC clock frequency
1059 * @param LTDCxSource This parameter can be one of the following values:
1060 * @arg @ref LL_RCC_LTDC_CLKSOURCE
1061 * @retval LTDC clock frequency (in Hz)
1062 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator PLLSAI is not ready
1063 */
1064 uint32_t LL_RCC_GetLTDCClockFreq(uint32_t LTDCxSource)
1065 {
1066 uint32_t ltdc_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
1067
1068 /* Check parameter */
1069 assert_param(IS_LL_RCC_LTDC_CLKSOURCE(LTDCxSource));
1070
1071 if (LL_RCC_PLLSAI_IsReady())
1072 {
1073 ltdc_frequency = RCC_PLLSAI_GetFreqDomain_LTDC();
1074 }
1075
1076 return ltdc_frequency;
1077 }
1078 #endif /* LTDC */
1079
1080 #if defined(SPDIFRX)
1081 /**
1082 * @brief Return SPDIFRX clock frequency
1083 * @param SPDIFRXxSource This parameter can be one of the following values:
1084 * @arg @ref LL_RCC_SPDIFRX1_CLKSOURCE
1085 * @retval SPDIFRX clock frequency (in Hz)
1086 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
1087 */
1088 uint32_t LL_RCC_GetSPDIFRXClockFreq(uint32_t SPDIFRXxSource)
1089 {
1090 uint32_t spdifrx_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
1091
1092 /* Check parameter */
1093 assert_param(IS_LL_RCC_SPDIFRX_CLKSOURCE(SPDIFRXxSource));
1094
1095 /* SPDIFRX1CLK clock frequency */
1096 switch (LL_RCC_GetSPDIFRXClockSource(SPDIFRXxSource))
1097 {
1098 case LL_RCC_SPDIFRX1_CLKSOURCE_PLLI2S: /* SPDIFRX Clock is PLLI2S Osc. */
1099 if (LL_RCC_PLLI2S_IsReady())
1100 {
1101 spdifrx_frequency = RCC_PLLI2S_GetFreqDomain_SPDIFRX();
1102 }
1103 break;
1104
1105 case LL_RCC_SPDIFRX1_CLKSOURCE_PLL: /* SPDIFRX Clock is PLL Osc. */
1106 default:
1107 if (LL_RCC_PLL_IsReady())
1108 {
1109 spdifrx_frequency = RCC_PLL_GetFreqDomain_SPDIFRX();
1110 }
1111 break;
1112 }
1113
1114 return spdifrx_frequency;
1115 }
1116 #endif /* SPDIFRX */
1117
1118 /**
1119 * @}
1120 */
1121
1122 /**
1123 * @}
1124 */
1125
1126 /** @addtogroup RCC_LL_Private_Functions
1127 * @{
1128 */
1129
1130 /**
1131 * @brief Return SYSTEM clock frequency
1132 * @retval SYSTEM clock frequency (in Hz)
1133 */
1134 uint32_t RCC_GetSystemClockFreq(void)
1135 {
1136 uint32_t frequency = 0U;
1137
1138 /* Get SYSCLK source -------------------------------------------------------*/
1139 switch (LL_RCC_GetSysClkSource())
1140 {
1141 case LL_RCC_SYS_CLKSOURCE_STATUS_HSI: /* HSI used as system clock source */
1142 frequency = HSI_VALUE;
1143 break;
1144
1145 case LL_RCC_SYS_CLKSOURCE_STATUS_HSE: /* HSE used as system clock source */
1146 frequency = HSE_VALUE;
1147 break;
1148
1149 case LL_RCC_SYS_CLKSOURCE_STATUS_PLL: /* PLL used as system clock source */
1150 frequency = RCC_PLL_GetFreqDomain_SYS(LL_RCC_SYS_CLKSOURCE_STATUS_PLL);
1151 break;
1152
1153 #if defined(RCC_PLLR_SYSCLK_SUPPORT)
1154 case LL_RCC_SYS_CLKSOURCE_STATUS_PLLR: /* PLLR used as system clock source */
1155 frequency = RCC_PLL_GetFreqDomain_SYS(LL_RCC_SYS_CLKSOURCE_STATUS_PLLR);
1156 break;
1157 #endif /* RCC_PLLR_SYSCLK_SUPPORT */
1158
1159 default:
1160 frequency = HSI_VALUE;
1161 break;
1162 }
1163
1164 return frequency;
1165 }
1166
1167 /**
1168 * @brief Return HCLK clock frequency
1169 * @param SYSCLK_Frequency SYSCLK clock frequency
1170 * @retval HCLK clock frequency (in Hz)
1171 */
1172 uint32_t RCC_GetHCLKClockFreq(uint32_t SYSCLK_Frequency)
1173 {
1174 /* HCLK clock frequency */
1175 return __LL_RCC_CALC_HCLK_FREQ(SYSCLK_Frequency, LL_RCC_GetAHBPrescaler());
1176 }
1177
1178 /**
1179 * @brief Return PCLK1 clock frequency
1180 * @param HCLK_Frequency HCLK clock frequency
1181 * @retval PCLK1 clock frequency (in Hz)
1182 */
1183 uint32_t RCC_GetPCLK1ClockFreq(uint32_t HCLK_Frequency)
1184 {
1185 /* PCLK1 clock frequency */
1186 return __LL_RCC_CALC_PCLK1_FREQ(HCLK_Frequency, LL_RCC_GetAPB1Prescaler());
1187 }
1188
1189 /**
1190 * @brief Return PCLK2 clock frequency
1191 * @param HCLK_Frequency HCLK clock frequency
1192 * @retval PCLK2 clock frequency (in Hz)
1193 */
1194 uint32_t RCC_GetPCLK2ClockFreq(uint32_t HCLK_Frequency)
1195 {
1196 /* PCLK2 clock frequency */
1197 return __LL_RCC_CALC_PCLK2_FREQ(HCLK_Frequency, LL_RCC_GetAPB2Prescaler());
1198 }
1199
1200 /**
1201 * @brief Return PLL clock frequency used for system domain
1202 * @param SYSCLK_Source System clock source
1203 * @retval PLL clock frequency (in Hz)
1204 */
1205 uint32_t RCC_PLL_GetFreqDomain_SYS(uint32_t SYSCLK_Source)
1206 {
1207 uint32_t pllinputfreq = 0U, pllsource = 0U, plloutputfreq = 0U;
1208
1209 /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN
1210 SYSCLK = PLL_VCO / (PLLP or PLLR)
1211 */
1212 pllsource = LL_RCC_PLL_GetMainSource();
1213
1214 switch (pllsource)
1215 {
1216 case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */
1217 pllinputfreq = HSI_VALUE;
1218 break;
1219
1220 case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */
1221 pllinputfreq = HSE_VALUE;
1222 break;
1223
1224 default:
1225 pllinputfreq = HSI_VALUE;
1226 break;
1227 }
1228
1229 if (SYSCLK_Source == LL_RCC_SYS_CLKSOURCE_STATUS_PLL)
1230 {
1231 plloutputfreq = __LL_RCC_CALC_PLLCLK_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(),
1232 LL_RCC_PLL_GetN(), LL_RCC_PLL_GetP());
1233 }
1234 #if defined(RCC_PLLR_SYSCLK_SUPPORT)
1235 else
1236 {
1237 plloutputfreq = __LL_RCC_CALC_PLLRCLK_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(),
1238 LL_RCC_PLL_GetN(), LL_RCC_PLL_GetR());
1239 }
1240 #endif /* RCC_PLLR_SYSCLK_SUPPORT */
1241
1242 return plloutputfreq;
1243 }
1244
1245 /**
1246 * @brief Return PLL clock frequency used for 48 MHz domain
1247 * @retval PLL clock frequency (in Hz)
1248 */
1249 uint32_t RCC_PLL_GetFreqDomain_48M(void)
1250 {
1251 uint32_t pllinputfreq = 0U, pllsource = 0U;
1252
1253 /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM ) * PLLN
1254 48M Domain clock = PLL_VCO / PLLQ
1255 */
1256 pllsource = LL_RCC_PLL_GetMainSource();
1257
1258 switch (pllsource)
1259 {
1260 case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */
1261 pllinputfreq = HSI_VALUE;
1262 break;
1263
1264 case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */
1265 pllinputfreq = HSE_VALUE;
1266 break;
1267
1268 default:
1269 pllinputfreq = HSI_VALUE;
1270 break;
1271 }
1272 return __LL_RCC_CALC_PLLCLK_48M_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(),
1273 LL_RCC_PLL_GetN(), LL_RCC_PLL_GetQ());
1274 }
1275
1276 #if defined(DSI)
1277 /**
1278 * @brief Return PLL clock frequency used for DSI clock
1279 * @retval PLL clock frequency (in Hz)
1280 */
1281 uint32_t RCC_PLL_GetFreqDomain_DSI(void)
1282 {
1283 uint32_t pllinputfreq = 0U, pllsource = 0U;
1284
1285 /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN
1286 DSICLK = PLL_VCO / PLLR
1287 */
1288 pllsource = LL_RCC_PLL_GetMainSource();
1289
1290 switch (pllsource)
1291 {
1292 case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */
1293 pllinputfreq = HSE_VALUE;
1294 break;
1295
1296 case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */
1297 default:
1298 pllinputfreq = HSI_VALUE;
1299 break;
1300 }
1301 return __LL_RCC_CALC_PLLCLK_DSI_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(),
1302 LL_RCC_PLL_GetN(), LL_RCC_PLL_GetR());
1303 }
1304 #endif /* DSI */
1305
1306 #if defined(RCC_DCKCFGR_I2SSRC) || defined(RCC_DCKCFGR_I2S1SRC)
1307 /**
1308 * @brief Return PLL clock frequency used for I2S clock
1309 * @retval PLL clock frequency (in Hz)
1310 */
1311 uint32_t RCC_PLL_GetFreqDomain_I2S(void)
1312 {
1313 uint32_t pllinputfreq = 0U, pllsource = 0U;
1314
1315 /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN
1316 I2SCLK = PLL_VCO / PLLR
1317 */
1318 pllsource = LL_RCC_PLL_GetMainSource();
1319
1320 switch (pllsource)
1321 {
1322 case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */
1323 pllinputfreq = HSE_VALUE;
1324 break;
1325
1326 case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */
1327 default:
1328 pllinputfreq = HSI_VALUE;
1329 break;
1330 }
1331 return __LL_RCC_CALC_PLLCLK_I2S_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(),
1332 LL_RCC_PLL_GetN(), LL_RCC_PLL_GetR());
1333 }
1334 #endif /* RCC_DCKCFGR_I2SSRC || RCC_DCKCFGR_I2S1SRC */
1335
1336 #if defined(SPDIFRX)
1337 /**
1338 * @brief Return PLL clock frequency used for SPDIFRX clock
1339 * @retval PLL clock frequency (in Hz)
1340 */
1341 uint32_t RCC_PLL_GetFreqDomain_SPDIFRX(void)
1342 {
1343 uint32_t pllinputfreq = 0U, pllsource = 0U;
1344
1345 /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN
1346 SPDIFRXCLK = PLL_VCO / PLLR
1347 */
1348 pllsource = LL_RCC_PLL_GetMainSource();
1349
1350 switch (pllsource)
1351 {
1352 case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */
1353 pllinputfreq = HSE_VALUE;
1354 break;
1355
1356 case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */
1357 default:
1358 pllinputfreq = HSI_VALUE;
1359 break;
1360 }
1361 return __LL_RCC_CALC_PLLCLK_SPDIFRX_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(),
1362 LL_RCC_PLL_GetN(), LL_RCC_PLL_GetR());
1363 }
1364 #endif /* SPDIFRX */
1365
1366 #if defined(RCC_PLLCFGR_PLLR)
1367 #if defined(SAI1)
1368 /**
1369 * @brief Return PLL clock frequency used for SAI clock
1370 * @retval PLL clock frequency (in Hz)
1371 */
1372 uint32_t RCC_PLL_GetFreqDomain_SAI(void)
1373 {
1374 uint32_t pllinputfreq = 0U, pllsource = 0U, plloutputfreq = 0U;
1375
1376 /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN
1377 SAICLK = (PLL_VCO / PLLR) / PLLDIVR
1378 or
1379 SAICLK = PLL_VCO / PLLR
1380 */
1381 pllsource = LL_RCC_PLL_GetMainSource();
1382
1383 switch (pllsource)
1384 {
1385 case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */
1386 pllinputfreq = HSE_VALUE;
1387 break;
1388
1389 case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */
1390 default:
1391 pllinputfreq = HSI_VALUE;
1392 break;
1393 }
1394
1395 #if defined(RCC_DCKCFGR_PLLDIVR)
1396 plloutputfreq = __LL_RCC_CALC_PLLCLK_SAI_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(),
1397 LL_RCC_PLL_GetN(), LL_RCC_PLL_GetR(), LL_RCC_PLL_GetDIVR());
1398 #else
1399 plloutputfreq = __LL_RCC_CALC_PLLCLK_SAI_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(),
1400 LL_RCC_PLL_GetN(), LL_RCC_PLL_GetR());
1401 #endif /* RCC_DCKCFGR_PLLDIVR */
1402
1403 return plloutputfreq;
1404 }
1405 #endif /* SAI1 */
1406 #endif /* RCC_PLLCFGR_PLLR */
1407
1408 #if defined(RCC_PLLSAI_SUPPORT)
1409 /**
1410 * @brief Return PLLSAI clock frequency used for SAI domain
1411 * @retval PLLSAI clock frequency (in Hz)
1412 */
1413 uint32_t RCC_PLLSAI_GetFreqDomain_SAI(void)
1414 {
1415 uint32_t pllinputfreq = 0U, pllsource = 0U;
1416
1417 /* PLLSAI_VCO = (HSE_VALUE or HSI_VALUE / PLLSAIM) * PLLSAIN
1418 SAI domain clock = (PLLSAI_VCO / PLLSAIQ) / PLLSAIDIVQ
1419 */
1420 pllsource = LL_RCC_PLL_GetMainSource();
1421
1422 switch (pllsource)
1423 {
1424 case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLLSAI clock source */
1425 pllinputfreq = HSI_VALUE;
1426 break;
1427
1428 case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLLSAI clock source */
1429 pllinputfreq = HSE_VALUE;
1430 break;
1431
1432 default:
1433 pllinputfreq = HSI_VALUE;
1434 break;
1435 }
1436 return __LL_RCC_CALC_PLLSAI_SAI_FREQ(pllinputfreq, LL_RCC_PLLSAI_GetDivider(),
1437 LL_RCC_PLLSAI_GetN(), LL_RCC_PLLSAI_GetQ(), LL_RCC_PLLSAI_GetDIVQ());
1438 }
1439
1440 #if defined(RCC_PLLSAICFGR_PLLSAIP)
1441 /**
1442 * @brief Return PLLSAI clock frequency used for 48Mhz domain
1443 * @retval PLLSAI clock frequency (in Hz)
1444 */
1445 uint32_t RCC_PLLSAI_GetFreqDomain_48M(void)
1446 {
1447 uint32_t pllinputfreq = 0U, pllsource = 0U;
1448
1449 /* PLLSAI_VCO = (HSE_VALUE or HSI_VALUE / PLLSAIM) * PLLSAIN
1450 48M Domain clock = PLLSAI_VCO / PLLSAIP
1451 */
1452 pllsource = LL_RCC_PLL_GetMainSource();
1453
1454 switch (pllsource)
1455 {
1456 case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLLSAI clock source */
1457 pllinputfreq = HSI_VALUE;
1458 break;
1459
1460 case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLLSAI clock source */
1461 pllinputfreq = HSE_VALUE;
1462 break;
1463
1464 default:
1465 pllinputfreq = HSI_VALUE;
1466 break;
1467 }
1468 return __LL_RCC_CALC_PLLSAI_48M_FREQ(pllinputfreq, LL_RCC_PLLSAI_GetDivider(),
1469 LL_RCC_PLLSAI_GetN(), LL_RCC_PLLSAI_GetP());
1470 }
1471 #endif /* RCC_PLLSAICFGR_PLLSAIP */
1472
1473 #if defined(LTDC)
1474 /**
1475 * @brief Return PLLSAI clock frequency used for LTDC domain
1476 * @retval PLLSAI clock frequency (in Hz)
1477 */
1478 uint32_t RCC_PLLSAI_GetFreqDomain_LTDC(void)
1479 {
1480 uint32_t pllinputfreq = 0U, pllsource = 0U;
1481
1482 /* PLLSAI_VCO = (HSE_VALUE or HSI_VALUE / PLLSAIM) * PLLSAIN
1483 LTDC Domain clock = (PLLSAI_VCO / PLLSAIR) / PLLSAIDIVR
1484 */
1485 pllsource = LL_RCC_PLL_GetMainSource();
1486
1487 switch (pllsource)
1488 {
1489 case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLLSAI clock source */
1490 pllinputfreq = HSI_VALUE;
1491 break;
1492
1493 case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLLSAI clock source */
1494 pllinputfreq = HSE_VALUE;
1495 break;
1496
1497 default:
1498 pllinputfreq = HSI_VALUE;
1499 break;
1500 }
1501 return __LL_RCC_CALC_PLLSAI_LTDC_FREQ(pllinputfreq, LL_RCC_PLLSAI_GetDivider(),
1502 LL_RCC_PLLSAI_GetN(), LL_RCC_PLLSAI_GetR(), LL_RCC_PLLSAI_GetDIVR());
1503 }
1504 #endif /* LTDC */
1505 #endif /* RCC_PLLSAI_SUPPORT */
1506
1507 #if defined(RCC_PLLI2S_SUPPORT)
1508 #if defined(SAI1)
1509 /**
1510 * @brief Return PLLI2S clock frequency used for SAI domains
1511 * @retval PLLI2S clock frequency (in Hz)
1512 */
1513 uint32_t RCC_PLLI2S_GetFreqDomain_SAI(void)
1514 {
1515 uint32_t plli2sinputfreq = 0U, plli2ssource = 0U, plli2soutputfreq = 0U;
1516
1517 /* PLLI2S_VCO = (HSE_VALUE or HSI_VALUE / PLLI2SM) * PLLI2SN
1518 SAI domain clock = (PLLI2S_VCO / PLLI2SQ) / PLLI2SDIVQ
1519 or
1520 SAI domain clock = (PLLI2S_VCO / PLLI2SR) / PLLI2SDIVR
1521 */
1522 plli2ssource = LL_RCC_PLLI2S_GetMainSource();
1523
1524 switch (plli2ssource)
1525 {
1526 case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLLI2S clock source */
1527 plli2sinputfreq = HSE_VALUE;
1528 break;
1529
1530 #if defined(RCC_PLLI2SCFGR_PLLI2SSRC)
1531 case LL_RCC_PLLI2SSOURCE_PIN: /* External pin input clock used as PLLI2S clock source */
1532 plli2sinputfreq = EXTERNAL_CLOCK_VALUE;
1533 break;
1534 #endif /* RCC_PLLI2SCFGR_PLLI2SSRC */
1535
1536 case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLLI2S clock source */
1537 default:
1538 plli2sinputfreq = HSI_VALUE;
1539 break;
1540 }
1541
1542 #if defined(RCC_DCKCFGR_PLLI2SDIVQ)
1543 plli2soutputfreq = __LL_RCC_CALC_PLLI2S_SAI_FREQ(plli2sinputfreq, LL_RCC_PLLI2S_GetDivider(),
1544 LL_RCC_PLLI2S_GetN(), LL_RCC_PLLI2S_GetQ(), LL_RCC_PLLI2S_GetDIVQ());
1545 #else
1546 plli2soutputfreq = __LL_RCC_CALC_PLLI2S_SAI_FREQ(plli2sinputfreq, LL_RCC_PLLI2S_GetDivider(),
1547 LL_RCC_PLLI2S_GetN(), LL_RCC_PLLI2S_GetR(), LL_RCC_PLLI2S_GetDIVR());
1548 #endif /* RCC_DCKCFGR_PLLI2SDIVQ */
1549
1550 return plli2soutputfreq;
1551 }
1552 #endif /* SAI1 */
1553
1554 #if defined(SPDIFRX)
1555 /**
1556 * @brief Return PLLI2S clock frequency used for SPDIFRX domain
1557 * @retval PLLI2S clock frequency (in Hz)
1558 */
1559 uint32_t RCC_PLLI2S_GetFreqDomain_SPDIFRX(void)
1560 {
1561 uint32_t pllinputfreq = 0U, pllsource = 0U;
1562
1563 /* PLLI2S_VCO = (HSE_VALUE or HSI_VALUE / PLLI2SM) * PLLI2SN
1564 SPDIFRX Domain clock = PLLI2S_VCO / PLLI2SP
1565 */
1566 pllsource = LL_RCC_PLLI2S_GetMainSource();
1567
1568 switch (pllsource)
1569 {
1570 case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLLI2S clock source */
1571 pllinputfreq = HSE_VALUE;
1572 break;
1573
1574 case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLLI2S clock source */
1575 default:
1576 pllinputfreq = HSI_VALUE;
1577 break;
1578 }
1579
1580 return __LL_RCC_CALC_PLLI2S_SPDIFRX_FREQ(pllinputfreq, LL_RCC_PLLI2S_GetDivider(),
1581 LL_RCC_PLLI2S_GetN(), LL_RCC_PLLI2S_GetP());
1582 }
1583 #endif /* SPDIFRX */
1584
1585 /**
1586 * @brief Return PLLI2S clock frequency used for I2S domain
1587 * @retval PLLI2S clock frequency (in Hz)
1588 */
1589 uint32_t RCC_PLLI2S_GetFreqDomain_I2S(void)
1590 {
1591 uint32_t plli2sinputfreq = 0U, plli2ssource = 0U, plli2soutputfreq = 0U;
1592
1593 /* PLLI2S_VCO = (HSE_VALUE or HSI_VALUE / PLLI2SM) * PLLI2SN
1594 I2S Domain clock = PLLI2S_VCO / PLLI2SR
1595 */
1596 plli2ssource = LL_RCC_PLLI2S_GetMainSource();
1597
1598 switch (plli2ssource)
1599 {
1600 case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLLI2S clock source */
1601 plli2sinputfreq = HSE_VALUE;
1602 break;
1603
1604 #if defined(RCC_PLLI2SCFGR_PLLI2SSRC)
1605 case LL_RCC_PLLI2SSOURCE_PIN: /* External pin input clock used as PLLI2S clock source */
1606 plli2sinputfreq = EXTERNAL_CLOCK_VALUE;
1607 break;
1608 #endif /* RCC_PLLI2SCFGR_PLLI2SSRC */
1609
1610 case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLLI2S clock source */
1611 default:
1612 plli2sinputfreq = HSI_VALUE;
1613 break;
1614 }
1615
1616 plli2soutputfreq = __LL_RCC_CALC_PLLI2S_I2S_FREQ(plli2sinputfreq, LL_RCC_PLLI2S_GetDivider(),
1617 LL_RCC_PLLI2S_GetN(), LL_RCC_PLLI2S_GetR());
1618
1619 return plli2soutputfreq;
1620 }
1621
1622 #if defined(RCC_PLLI2SCFGR_PLLI2SQ) && !defined(RCC_DCKCFGR_PLLI2SDIVQ)
1623 /**
1624 * @brief Return PLLI2S clock frequency used for 48Mhz domain
1625 * @retval PLLI2S clock frequency (in Hz)
1626 */
1627 uint32_t RCC_PLLI2S_GetFreqDomain_48M(void)
1628 {
1629 uint32_t plli2sinputfreq = 0U, plli2ssource = 0U, plli2soutputfreq = 0U;
1630
1631 /* PLL48M_VCO = (HSE_VALUE or HSI_VALUE / PLLI2SM) * PLLI2SN
1632 48M Domain clock = PLLI2S_VCO / PLLI2SQ
1633 */
1634 plli2ssource = LL_RCC_PLLI2S_GetMainSource();
1635
1636 switch (plli2ssource)
1637 {
1638 case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLLI2S clock source */
1639 plli2sinputfreq = HSE_VALUE;
1640 break;
1641
1642 #if defined(RCC_PLLI2SCFGR_PLLI2SSRC)
1643 case LL_RCC_PLLI2SSOURCE_PIN: /* External pin input clock used as PLLI2S clock source */
1644 plli2sinputfreq = EXTERNAL_CLOCK_VALUE;
1645 break;
1646 #endif /* RCC_PLLI2SCFGR_PLLI2SSRC */
1647
1648 case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLLI2S clock source */
1649 default:
1650 plli2sinputfreq = HSI_VALUE;
1651 break;
1652 }
1653
1654 plli2soutputfreq = __LL_RCC_CALC_PLLI2S_48M_FREQ(plli2sinputfreq, LL_RCC_PLLI2S_GetDivider(),
1655 LL_RCC_PLLI2S_GetN(), LL_RCC_PLLI2S_GetQ());
1656
1657 return plli2soutputfreq;
1658 }
1659 #endif /* RCC_PLLI2SCFGR_PLLI2SQ && !RCC_DCKCFGR_PLLI2SDIVQ */
1660 #endif /* RCC_PLLI2S_SUPPORT */
1661 /**
1662 * @}
1663 */
1664
1665 /**
1666 * @}
1667 */
1668
1669 #endif /* defined(RCC) */
1670
1671 /**
1672 * @}
1673 */
1674
1675 #endif /* USE_FULL_LL_DRIVER */
1676
1677 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/