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comparison Common/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_fsmc.c @ 128:c78bcbd5deda FlipDisplay
Added current STM32 standandard libraries in version independend folder structure
author | Ideenmodellierer |
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date | Sun, 17 Feb 2019 21:12:22 +0100 |
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1 /** | |
2 ****************************************************************************** | |
3 * @file stm32f4xx_ll_fsmc.c | |
4 * @author MCD Application Team | |
5 * @brief FSMC Low Layer HAL module driver. | |
6 * | |
7 * This file provides firmware functions to manage the following | |
8 * functionalities of the Flexible Static Memory Controller (FSMC) peripheral memories: | |
9 * + Initialization/de-initialization functions | |
10 * + Peripheral Control functions | |
11 * + Peripheral State functions | |
12 * | |
13 @verbatim | |
14 ============================================================================== | |
15 ##### FSMC peripheral features ##### | |
16 ============================================================================== | |
17 [..] The Flexible static memory controller (FSMC) includes two memory controllers: | |
18 (+) The NOR/PSRAM memory controller | |
19 (+) The NAND/PC Card memory controller | |
20 | |
21 [..] The FSMC functional block makes the interface with synchronous and asynchronous static | |
22 memories, SDRAM memories, and 16-bit PC memory cards. Its main purposes are: | |
23 (+) to translate AHB transactions into the appropriate external device protocol. | |
24 (+) to meet the access time requirements of the external memory devices. | |
25 | |
26 [..] All external memories share the addresses, data and control signals with the controller. | |
27 Each external device is accessed by means of a unique Chip Select. The FSMC performs | |
28 only one access at a time to an external device. | |
29 The main features of the FSMC controller are the following: | |
30 (+) Interface with static-memory mapped devices including: | |
31 (++) Static random access memory (SRAM). | |
32 (++) Read-only memory (ROM). | |
33 (++) NOR Flash memory/OneNAND Flash memory. | |
34 (++) PSRAM (4 memory banks). | |
35 (++) 16-bit PC Card compatible devices. | |
36 (++) Two banks of NAND Flash memory with ECC hardware to check up to 8 Kbytes of | |
37 data. | |
38 (+) Independent Chip Select control for each memory bank. | |
39 (+) Independent configuration for each memory bank. | |
40 | |
41 @endverbatim | |
42 ****************************************************************************** | |
43 * @attention | |
44 * | |
45 * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2> | |
46 * | |
47 * Redistribution and use in source and binary forms, with or without modification, | |
48 * are permitted provided that the following conditions are met: | |
49 * 1. Redistributions of source code must retain the above copyright notice, | |
50 * this list of conditions and the following disclaimer. | |
51 * 2. Redistributions in binary form must reproduce the above copyright notice, | |
52 * this list of conditions and the following disclaimer in the documentation | |
53 * and/or other materials provided with the distribution. | |
54 * 3. Neither the name of STMicroelectronics nor the names of its contributors | |
55 * may be used to endorse or promote products derived from this software | |
56 * without specific prior written permission. | |
57 * | |
58 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" | |
59 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE | |
60 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE | |
61 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE | |
62 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL | |
63 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR | |
64 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER | |
65 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, | |
66 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE | |
67 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | |
68 * | |
69 ****************************************************************************** | |
70 */ | |
71 | |
72 /* Includes ------------------------------------------------------------------*/ | |
73 #include "stm32f4xx_hal.h" | |
74 | |
75 /** @addtogroup STM32F4xx_HAL_Driver | |
76 * @{ | |
77 */ | |
78 | |
79 /** @defgroup FSMC_LL FSMC Low Layer | |
80 * @brief FSMC driver modules | |
81 * @{ | |
82 */ | |
83 | |
84 #if defined (HAL_SRAM_MODULE_ENABLED) || defined(HAL_NOR_MODULE_ENABLED) || defined(HAL_NAND_MODULE_ENABLED) || defined(HAL_PCCARD_MODULE_ENABLED) | |
85 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F412Zx) ||\ | |
86 defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F413xx) || defined(STM32F423xx) | |
87 /* Private typedef -----------------------------------------------------------*/ | |
88 /* Private define ------------------------------------------------------------*/ | |
89 /* Private macro -------------------------------------------------------------*/ | |
90 /* Private variables ---------------------------------------------------------*/ | |
91 /* Private function prototypes -----------------------------------------------*/ | |
92 /* Private functions ---------------------------------------------------------*/ | |
93 /** @addtogroup FSMC_LL_Private_Functions | |
94 * @{ | |
95 */ | |
96 | |
97 /** @addtogroup FSMC_LL_NORSRAM | |
98 * @brief NORSRAM Controller functions | |
99 * | |
100 @verbatim | |
101 ============================================================================== | |
102 ##### How to use NORSRAM device driver ##### | |
103 ============================================================================== | |
104 | |
105 [..] | |
106 This driver contains a set of APIs to interface with the FSMC NORSRAM banks in order | |
107 to run the NORSRAM external devices. | |
108 | |
109 (+) FSMC NORSRAM bank reset using the function FSMC_NORSRAM_DeInit() | |
110 (+) FSMC NORSRAM bank control configuration using the function FSMC_NORSRAM_Init() | |
111 (+) FSMC NORSRAM bank timing configuration using the function FSMC_NORSRAM_Timing_Init() | |
112 (+) FSMC NORSRAM bank extended timing configuration using the function | |
113 FSMC_NORSRAM_Extended_Timing_Init() | |
114 (+) FSMC NORSRAM bank enable/disable write operation using the functions | |
115 FSMC_NORSRAM_WriteOperation_Enable()/FSMC_NORSRAM_WriteOperation_Disable() | |
116 | |
117 @endverbatim | |
118 * @{ | |
119 */ | |
120 | |
121 /** @addtogroup FSMC_LL_NORSRAM_Private_Functions_Group1 | |
122 * @brief Initialization and Configuration functions | |
123 * | |
124 @verbatim | |
125 ============================================================================== | |
126 ##### Initialization and de_initialization functions ##### | |
127 ============================================================================== | |
128 [..] | |
129 This section provides functions allowing to: | |
130 (+) Initialize and configure the FSMC NORSRAM interface | |
131 (+) De-initialize the FSMC NORSRAM interface | |
132 (+) Configure the FSMC clock and associated GPIOs | |
133 | |
134 @endverbatim | |
135 * @{ | |
136 */ | |
137 | |
138 /** | |
139 * @brief Initialize the FSMC_NORSRAM device according to the specified | |
140 * control parameters in the FSMC_NORSRAM_InitTypeDef | |
141 * @param Device Pointer to NORSRAM device instance | |
142 * @param Init Pointer to NORSRAM Initialization structure | |
143 * @retval HAL status | |
144 */ | |
145 HAL_StatusTypeDef FSMC_NORSRAM_Init(FSMC_NORSRAM_TypeDef *Device, FSMC_NORSRAM_InitTypeDef* Init) | |
146 { | |
147 uint32_t tmpr = 0U; | |
148 | |
149 /* Check the parameters */ | |
150 assert_param(IS_FSMC_NORSRAM_DEVICE(Device)); | |
151 assert_param(IS_FSMC_NORSRAM_BANK(Init->NSBank)); | |
152 assert_param(IS_FSMC_MUX(Init->DataAddressMux)); | |
153 assert_param(IS_FSMC_MEMORY(Init->MemoryType)); | |
154 assert_param(IS_FSMC_NORSRAM_MEMORY_WIDTH(Init->MemoryDataWidth)); | |
155 assert_param(IS_FSMC_BURSTMODE(Init->BurstAccessMode)); | |
156 assert_param(IS_FSMC_WAIT_POLARITY(Init->WaitSignalPolarity)); | |
157 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) | |
158 assert_param(IS_FSMC_WRAP_MODE(Init->WrapMode)); | |
159 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */ | |
160 assert_param(IS_FSMC_WAIT_SIGNAL_ACTIVE(Init->WaitSignalActive)); | |
161 assert_param(IS_FSMC_WRITE_OPERATION(Init->WriteOperation)); | |
162 assert_param(IS_FSMC_WAITE_SIGNAL(Init->WaitSignal)); | |
163 assert_param(IS_FSMC_EXTENDED_MODE(Init->ExtendedMode)); | |
164 assert_param(IS_FSMC_ASYNWAIT(Init->AsynchronousWait)); | |
165 assert_param(IS_FSMC_WRITE_BURST(Init->WriteBurst)); | |
166 assert_param(IS_FSMC_PAGESIZE(Init->PageSize)); | |
167 #if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F413xx) || defined(STM32F423xx) | |
168 assert_param(IS_FSMC_WRITE_FIFO(Init->WriteFifo)); | |
169 assert_param(IS_FSMC_CONTINOUS_CLOCK(Init->ContinuousClock)); | |
170 #endif /* STM32F412Zx || STM32F412Vx || STM32F413xx || STM32F423xx */ | |
171 | |
172 /* Get the BTCR register value */ | |
173 tmpr = Device->BTCR[Init->NSBank]; | |
174 | |
175 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) | |
176 /* Clear MBKEN, MUXEN, MTYP, MWID, FACCEN, BURSTEN, WAITPOL, WRAPMOD, WAITCFG, WREN, | |
177 WAITEN, EXTMOD, ASYNCWAIT, CPSIZE and CBURSTRW bits */ | |
178 tmpr &= ((uint32_t)~(FSMC_BCR1_MBKEN | FSMC_BCR1_MUXEN | FSMC_BCR1_MTYP | \ | |
179 FSMC_BCR1_MWID | FSMC_BCR1_FACCEN | FSMC_BCR1_BURSTEN | \ | |
180 FSMC_BCR1_WAITPOL | FSMC_BCR1_WRAPMOD | FSMC_BCR1_WAITCFG | \ | |
181 FSMC_BCR1_WREN | FSMC_BCR1_WAITEN | FSMC_BCR1_EXTMOD | \ | |
182 FSMC_BCR1_ASYNCWAIT | FSMC_BCR1_CPSIZE | FSMC_BCR1_CBURSTRW)); | |
183 /* Set NORSRAM device control parameters */ | |
184 tmpr |= (uint32_t)(Init->DataAddressMux |\ | |
185 Init->MemoryType |\ | |
186 Init->MemoryDataWidth |\ | |
187 Init->BurstAccessMode |\ | |
188 Init->WaitSignalPolarity |\ | |
189 Init->WrapMode |\ | |
190 Init->WaitSignalActive |\ | |
191 Init->WriteOperation |\ | |
192 Init->WaitSignal |\ | |
193 Init->ExtendedMode |\ | |
194 Init->AsynchronousWait |\ | |
195 Init->PageSize |\ | |
196 Init->WriteBurst | |
197 ); | |
198 #else /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F413xx || STM32F423xx */ | |
199 /* Clear MBKEN, MUXEN, MTYP, MWID, FACCEN, BURSTEN, WAITPOL, WAITCFG, WREN, | |
200 WAITEN, EXTMOD, ASYNCWAIT,CPSIZE, CBURSTRW, CCLKEN and WFDIS bits */ | |
201 tmpr &= ((uint32_t)~(FSMC_BCR1_MBKEN | FSMC_BCR1_MUXEN | FSMC_BCR1_MTYP | \ | |
202 FSMC_BCR1_MWID | FSMC_BCR1_FACCEN | FSMC_BCR1_BURSTEN | \ | |
203 FSMC_BCR1_WAITPOL | FSMC_BCR1_WAITCFG | FSMC_BCR1_WREN | \ | |
204 FSMC_BCR1_WAITEN | FSMC_BCR1_EXTMOD | FSMC_BCR1_ASYNCWAIT | \ | |
205 FSMC_BCR1_CPSIZE | FSMC_BCR1_CBURSTRW | FSMC_BCR1_CCLKEN | \ | |
206 FSMC_BCR1_WFDIS)); | |
207 /* Set NORSRAM device control parameters */ | |
208 tmpr |= (uint32_t)(Init->DataAddressMux |\ | |
209 Init->MemoryType |\ | |
210 Init->MemoryDataWidth |\ | |
211 Init->BurstAccessMode |\ | |
212 Init->WaitSignalPolarity |\ | |
213 Init->WaitSignalActive |\ | |
214 Init->WriteOperation |\ | |
215 Init->WaitSignal |\ | |
216 Init->ExtendedMode |\ | |
217 Init->AsynchronousWait |\ | |
218 Init->WriteBurst |\ | |
219 Init->ContinuousClock |\ | |
220 Init->PageSize |\ | |
221 Init->WriteFifo); | |
222 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */ | |
223 | |
224 if(Init->MemoryType == FSMC_MEMORY_TYPE_NOR) | |
225 { | |
226 tmpr |= (uint32_t)FSMC_NORSRAM_FLASH_ACCESS_ENABLE; | |
227 } | |
228 | |
229 Device->BTCR[Init->NSBank] = tmpr; | |
230 | |
231 #if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F413xx) || defined(STM32F423xx) | |
232 /* Configure synchronous mode when Continuous clock is enabled for bank2..4 */ | |
233 if((Init->ContinuousClock == FSMC_CONTINUOUS_CLOCK_SYNC_ASYNC) && (Init->NSBank != FSMC_NORSRAM_BANK1)) | |
234 { | |
235 Device->BTCR[FSMC_NORSRAM_BANK1] |= (uint32_t)(Init->ContinuousClock); | |
236 } | |
237 | |
238 if(Init->NSBank != FSMC_NORSRAM_BANK1) | |
239 { | |
240 Device->BTCR[FSMC_NORSRAM_BANK1] |= (uint32_t)(Init->WriteFifo); | |
241 } | |
242 #endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F413xx || STM32F423xx */ | |
243 | |
244 return HAL_OK; | |
245 } | |
246 | |
247 /** | |
248 * @brief DeInitialize the FSMC_NORSRAM peripheral | |
249 * @param Device Pointer to NORSRAM device instance | |
250 * @param ExDevice Pointer to NORSRAM extended mode device instance | |
251 * @param Bank NORSRAM bank number | |
252 * @retval HAL status | |
253 */ | |
254 HAL_StatusTypeDef FSMC_NORSRAM_DeInit(FSMC_NORSRAM_TypeDef *Device, FSMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank) | |
255 { | |
256 /* Check the parameters */ | |
257 assert_param(IS_FSMC_NORSRAM_DEVICE(Device)); | |
258 assert_param(IS_FSMC_NORSRAM_EXTENDED_DEVICE(ExDevice)); | |
259 assert_param(IS_FSMC_NORSRAM_BANK(Bank)); | |
260 | |
261 /* Disable the FSMC_NORSRAM device */ | |
262 __FSMC_NORSRAM_DISABLE(Device, Bank); | |
263 | |
264 /* De-initialize the FSMC_NORSRAM device */ | |
265 /* FSMC_NORSRAM_BANK1 */ | |
266 if(Bank == FSMC_NORSRAM_BANK1) | |
267 { | |
268 Device->BTCR[Bank] = 0x000030DBU; | |
269 } | |
270 /* FSMC_NORSRAM_BANK2, FSMC_NORSRAM_BANK3 or FSMC_NORSRAM_BANK4 */ | |
271 else | |
272 { | |
273 Device->BTCR[Bank] = 0x000030D2U; | |
274 } | |
275 | |
276 Device->BTCR[Bank + 1U] = 0x0FFFFFFFU; | |
277 ExDevice->BWTR[Bank] = 0x0FFFFFFFU; | |
278 | |
279 return HAL_OK; | |
280 } | |
281 | |
282 | |
283 /** | |
284 * @brief Initialize the FSMC_NORSRAM Timing according to the specified | |
285 * parameters in the FSMC_NORSRAM_TimingTypeDef | |
286 * @param Device Pointer to NORSRAM device instance | |
287 * @param Timing Pointer to NORSRAM Timing structure | |
288 * @param Bank NORSRAM bank number | |
289 * @retval HAL status | |
290 */ | |
291 HAL_StatusTypeDef FSMC_NORSRAM_Timing_Init(FSMC_NORSRAM_TypeDef *Device, FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank) | |
292 { | |
293 uint32_t tmpr = 0U; | |
294 | |
295 /* Check the parameters */ | |
296 assert_param(IS_FSMC_NORSRAM_DEVICE(Device)); | |
297 assert_param(IS_FSMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime)); | |
298 assert_param(IS_FSMC_ADDRESS_HOLD_TIME(Timing->AddressHoldTime)); | |
299 assert_param(IS_FSMC_DATASETUP_TIME(Timing->DataSetupTime)); | |
300 assert_param(IS_FSMC_TURNAROUND_TIME(Timing->BusTurnAroundDuration)); | |
301 assert_param(IS_FSMC_CLK_DIV(Timing->CLKDivision)); | |
302 assert_param(IS_FSMC_DATA_LATENCY(Timing->DataLatency)); | |
303 assert_param(IS_FSMC_ACCESS_MODE(Timing->AccessMode)); | |
304 assert_param(IS_FSMC_NORSRAM_BANK(Bank)); | |
305 | |
306 /* Get the BTCR register value */ | |
307 tmpr = Device->BTCR[Bank + 1U]; | |
308 | |
309 /* Clear ADDSET, ADDHLD, DATAST, BUSTURN, CLKDIV, DATLAT and ACCMOD bits */ | |
310 tmpr &= ((uint32_t)~(FSMC_BTR1_ADDSET | FSMC_BTR1_ADDHLD | FSMC_BTR1_DATAST | \ | |
311 FSMC_BTR1_BUSTURN | FSMC_BTR1_CLKDIV | FSMC_BTR1_DATLAT | \ | |
312 FSMC_BTR1_ACCMOD)); | |
313 | |
314 /* Set FSMC_NORSRAM device timing parameters */ | |
315 tmpr |= (uint32_t)(Timing->AddressSetupTime |\ | |
316 ((Timing->AddressHoldTime) << 4U) |\ | |
317 ((Timing->DataSetupTime) << 8U) |\ | |
318 ((Timing->BusTurnAroundDuration) << 16U) |\ | |
319 (((Timing->CLKDivision)-1U) << 20U) |\ | |
320 (((Timing->DataLatency)-2U) << 24U) |\ | |
321 (Timing->AccessMode)); | |
322 | |
323 Device->BTCR[Bank + 1] = tmpr; | |
324 | |
325 #if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F413xx) || defined(STM32F423xx) | |
326 /* Configure Clock division value (in NORSRAM bank 1) when continuous clock is enabled */ | |
327 if(HAL_IS_BIT_SET(Device->BTCR[FSMC_NORSRAM_BANK1], FSMC_BCR1_CCLKEN)) | |
328 { | |
329 tmpr = (uint32_t)(Device->BTCR[FSMC_NORSRAM_BANK1 + 1U] & ~(0x0FU << 20U)); | |
330 tmpr |= (uint32_t)(((Timing->CLKDivision)-1U) << 20U); | |
331 Device->BTCR[FSMC_NORSRAM_BANK1 + 1U] = tmpr; | |
332 } | |
333 #endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F413xx || STM32F423xx */ | |
334 | |
335 return HAL_OK; | |
336 } | |
337 | |
338 /** | |
339 * @brief Initialize the FSMC_NORSRAM Extended mode Timing according to the specified | |
340 * parameters in the FSMC_NORSRAM_TimingTypeDef | |
341 * @param Device Pointer to NORSRAM device instance | |
342 * @param Timing Pointer to NORSRAM Timing structure | |
343 * @param Bank NORSRAM bank number | |
344 * @retval HAL status | |
345 */ | |
346 HAL_StatusTypeDef FSMC_NORSRAM_Extended_Timing_Init(FSMC_NORSRAM_EXTENDED_TypeDef *Device, FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, uint32_t ExtendedMode) | |
347 { | |
348 uint32_t tmpr = 0U; | |
349 | |
350 /* Check the parameters */ | |
351 assert_param(IS_FSMC_EXTENDED_MODE(ExtendedMode)); | |
352 | |
353 /* Set NORSRAM device timing register for write configuration, if extended mode is used */ | |
354 if(ExtendedMode == FSMC_EXTENDED_MODE_ENABLE) | |
355 { | |
356 /* Check the parameters */ | |
357 assert_param(IS_FSMC_NORSRAM_EXTENDED_DEVICE(Device)); | |
358 assert_param(IS_FSMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime)); | |
359 assert_param(IS_FSMC_ADDRESS_HOLD_TIME(Timing->AddressHoldTime)); | |
360 assert_param(IS_FSMC_DATASETUP_TIME(Timing->DataSetupTime)); | |
361 assert_param(IS_FSMC_TURNAROUND_TIME(Timing->BusTurnAroundDuration)); | |
362 assert_param(IS_FSMC_ACCESS_MODE(Timing->AccessMode)); | |
363 assert_param(IS_FSMC_NORSRAM_BANK(Bank)); | |
364 | |
365 /* Get the BWTR register value */ | |
366 tmpr = Device->BWTR[Bank]; | |
367 | |
368 /* Clear ADDSET, ADDHLD, DATAST, BUSTURN and ACCMOD bits */ | |
369 tmpr &= ((uint32_t)~(FSMC_BWTR1_ADDSET | FSMC_BWTR1_ADDHLD | FSMC_BWTR1_DATAST | \ | |
370 FSMC_BWTR1_BUSTURN | FSMC_BWTR1_ACCMOD)); | |
371 | |
372 tmpr |= (uint32_t)(Timing->AddressSetupTime |\ | |
373 ((Timing->AddressHoldTime) << 4U) |\ | |
374 ((Timing->DataSetupTime) << 8U) |\ | |
375 ((Timing->BusTurnAroundDuration) << 16U) |\ | |
376 (Timing->AccessMode)); | |
377 | |
378 Device->BWTR[Bank] = tmpr; | |
379 } | |
380 else | |
381 { | |
382 Device->BWTR[Bank] = 0x0FFFFFFFU; | |
383 } | |
384 | |
385 return HAL_OK; | |
386 } | |
387 /** | |
388 * @} | |
389 */ | |
390 | |
391 /** @addtogroup FSMC_LL_NORSRAM_Private_Functions_Group2 | |
392 * @brief management functions | |
393 * | |
394 @verbatim | |
395 ============================================================================== | |
396 ##### FSMC_NORSRAM Control functions ##### | |
397 ============================================================================== | |
398 [..] | |
399 This subsection provides a set of functions allowing to control dynamically | |
400 the FSMC NORSRAM interface. | |
401 | |
402 @endverbatim | |
403 * @{ | |
404 */ | |
405 | |
406 /** | |
407 * @brief Enables dynamically FSMC_NORSRAM write operation. | |
408 * @param Device Pointer to NORSRAM device instance | |
409 * @param Bank NORSRAM bank number | |
410 * @retval HAL status | |
411 */ | |
412 HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Enable(FSMC_NORSRAM_TypeDef *Device, uint32_t Bank) | |
413 { | |
414 /* Check the parameters */ | |
415 assert_param(IS_FSMC_NORSRAM_DEVICE(Device)); | |
416 assert_param(IS_FSMC_NORSRAM_BANK(Bank)); | |
417 | |
418 /* Enable write operation */ | |
419 Device->BTCR[Bank] |= FSMC_WRITE_OPERATION_ENABLE; | |
420 | |
421 return HAL_OK; | |
422 } | |
423 | |
424 /** | |
425 * @brief Disables dynamically FSMC_NORSRAM write operation. | |
426 * @param Device Pointer to NORSRAM device instance | |
427 * @param Bank NORSRAM bank number | |
428 * @retval HAL status | |
429 */ | |
430 HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Disable(FSMC_NORSRAM_TypeDef *Device, uint32_t Bank) | |
431 { | |
432 /* Check the parameters */ | |
433 assert_param(IS_FSMC_NORSRAM_DEVICE(Device)); | |
434 assert_param(IS_FSMC_NORSRAM_BANK(Bank)); | |
435 | |
436 /* Disable write operation */ | |
437 Device->BTCR[Bank] &= ~FSMC_WRITE_OPERATION_ENABLE; | |
438 | |
439 return HAL_OK; | |
440 } | |
441 /** | |
442 * @} | |
443 */ | |
444 | |
445 /** | |
446 * @} | |
447 */ | |
448 | |
449 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) | |
450 /** @addtogroup FSMC_LL_NAND | |
451 * @brief NAND Controller functions | |
452 * | |
453 @verbatim | |
454 ============================================================================== | |
455 ##### How to use NAND device driver ##### | |
456 ============================================================================== | |
457 [..] | |
458 This driver contains a set of APIs to interface with the FSMC NAND banks in order | |
459 to run the NAND external devices. | |
460 | |
461 (+) FSMC NAND bank reset using the function FSMC_NAND_DeInit() | |
462 (+) FSMC NAND bank control configuration using the function FSMC_NAND_Init() | |
463 (+) FSMC NAND bank common space timing configuration using the function | |
464 FSMC_NAND_CommonSpace_Timing_Init() | |
465 (+) FSMC NAND bank attribute space timing configuration using the function | |
466 FSMC_NAND_AttributeSpace_Timing_Init() | |
467 (+) FSMC NAND bank enable/disable ECC correction feature using the functions | |
468 FSMC_NAND_ECC_Enable()/FSMC_NAND_ECC_Disable() | |
469 (+) FSMC NAND bank get ECC correction code using the function FSMC_NAND_GetECC() | |
470 | |
471 @endverbatim | |
472 * @{ | |
473 */ | |
474 | |
475 /** @addtogroup FSMC_LL_NAND_Private_Functions_Group1 | |
476 * @brief Initialization and Configuration functions | |
477 * | |
478 @verbatim | |
479 ============================================================================== | |
480 ##### Initialization and de_initialization functions ##### | |
481 ============================================================================== | |
482 [..] | |
483 This section provides functions allowing to: | |
484 (+) Initialize and configure the FSMC NAND interface | |
485 (+) De-initialize the FSMC NAND interface | |
486 (+) Configure the FSMC clock and associated GPIOs | |
487 | |
488 @endverbatim | |
489 * @{ | |
490 */ | |
491 | |
492 /** | |
493 * @brief Initializes the FSMC_NAND device according to the specified | |
494 * control parameters in the FSMC_NAND_HandleTypeDef | |
495 * @param Device Pointer to NAND device instance | |
496 * @param Init Pointer to NAND Initialization structure | |
497 * @retval HAL status | |
498 */ | |
499 HAL_StatusTypeDef FSMC_NAND_Init(FSMC_NAND_TypeDef *Device, FSMC_NAND_InitTypeDef *Init) | |
500 { | |
501 uint32_t tmpr = 0U; | |
502 | |
503 /* Check the parameters */ | |
504 assert_param(IS_FSMC_NAND_BANK(Init->NandBank)); | |
505 assert_param(IS_FSMC_WAIT_FEATURE(Init->Waitfeature)); | |
506 assert_param(IS_FSMC_NAND_MEMORY_WIDTH(Init->MemoryDataWidth)); | |
507 assert_param(IS_FSMC_ECC_STATE(Init->EccComputation)); | |
508 assert_param(IS_FSMC_ECCPAGE_SIZE(Init->ECCPageSize)); | |
509 assert_param(IS_FSMC_TCLR_TIME(Init->TCLRSetupTime)); | |
510 assert_param(IS_FSMC_TAR_TIME(Init->TARSetupTime)); | |
511 | |
512 if(Init->NandBank == FSMC_NAND_BANK2) | |
513 { | |
514 /* Get the NAND bank 2 register value */ | |
515 tmpr = Device->PCR2; | |
516 } | |
517 else | |
518 { | |
519 /* Get the NAND bank 3 register value */ | |
520 tmpr = Device->PCR3; | |
521 } | |
522 | |
523 /* Clear PWAITEN, PBKEN, PTYP, PWID, ECCEN, TCLR, TAR and ECCPS bits */ | |
524 tmpr &= ((uint32_t)~(FSMC_PCR2_PWAITEN | FSMC_PCR2_PBKEN | FSMC_PCR2_PTYP | \ | |
525 FSMC_PCR2_PWID | FSMC_PCR2_ECCEN | FSMC_PCR2_TCLR | \ | |
526 FSMC_PCR2_TAR | FSMC_PCR2_ECCPS)); | |
527 | |
528 /* Set NAND device control parameters */ | |
529 tmpr |= (uint32_t)(Init->Waitfeature |\ | |
530 FSMC_PCR_MEMORY_TYPE_NAND |\ | |
531 Init->MemoryDataWidth |\ | |
532 Init->EccComputation |\ | |
533 Init->ECCPageSize |\ | |
534 ((Init->TCLRSetupTime) << 9U) |\ | |
535 ((Init->TARSetupTime) << 13U)); | |
536 | |
537 if(Init->NandBank == FSMC_NAND_BANK2) | |
538 { | |
539 /* NAND bank 2 registers configuration */ | |
540 Device->PCR2 = tmpr; | |
541 } | |
542 else | |
543 { | |
544 /* NAND bank 3 registers configuration */ | |
545 Device->PCR3 = tmpr; | |
546 } | |
547 | |
548 return HAL_OK; | |
549 } | |
550 | |
551 /** | |
552 * @brief Initializes the FSMC_NAND Common space Timing according to the specified | |
553 * parameters in the FSMC_NAND_PCC_TimingTypeDef | |
554 * @param Device Pointer to NAND device instance | |
555 * @param Timing Pointer to NAND timing structure | |
556 * @param Bank NAND bank number | |
557 * @retval HAL status | |
558 */ | |
559 HAL_StatusTypeDef FSMC_NAND_CommonSpace_Timing_Init(FSMC_NAND_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank) | |
560 { | |
561 uint32_t tmpr = 0U; | |
562 | |
563 /* Check the parameters */ | |
564 assert_param(IS_FSMC_SETUP_TIME(Timing->SetupTime)); | |
565 assert_param(IS_FSMC_WAIT_TIME(Timing->WaitSetupTime)); | |
566 assert_param(IS_FSMC_HOLD_TIME(Timing->HoldSetupTime)); | |
567 assert_param(IS_FSMC_HIZ_TIME(Timing->HiZSetupTime)); | |
568 | |
569 if(Bank == FSMC_NAND_BANK2) | |
570 { | |
571 /* Get the NAND bank 2 register value */ | |
572 tmpr = Device->PMEM2; | |
573 } | |
574 else | |
575 { | |
576 /* Get the NAND bank 3 register value */ | |
577 tmpr = Device->PMEM3; | |
578 } | |
579 | |
580 /* Clear MEMSETx, MEMWAITx, MEMHOLDx and MEMHIZx bits */ | |
581 tmpr &= ((uint32_t)~(FSMC_PMEM2_MEMSET2 | FSMC_PMEM2_MEMWAIT2 | FSMC_PMEM2_MEMHOLD2 | \ | |
582 FSMC_PMEM2_MEMHIZ2)); | |
583 | |
584 /* Set FSMC_NAND device timing parameters */ | |
585 tmpr |= (uint32_t)(Timing->SetupTime |\ | |
586 ((Timing->WaitSetupTime) << 8U) |\ | |
587 ((Timing->HoldSetupTime) << 16U) |\ | |
588 ((Timing->HiZSetupTime) << 24U) | |
589 ); | |
590 | |
591 if(Bank == FSMC_NAND_BANK2) | |
592 { | |
593 /* NAND bank 2 registers configuration */ | |
594 Device->PMEM2 = tmpr; | |
595 } | |
596 else | |
597 { | |
598 /* NAND bank 3 registers configuration */ | |
599 Device->PMEM3 = tmpr; | |
600 } | |
601 | |
602 return HAL_OK; | |
603 } | |
604 | |
605 /** | |
606 * @brief Initializes the FSMC_NAND Attribute space Timing according to the specified | |
607 * parameters in the FSMC_NAND_PCC_TimingTypeDef | |
608 * @param Device Pointer to NAND device instance | |
609 * @param Timing Pointer to NAND timing structure | |
610 * @param Bank NAND bank number | |
611 * @retval HAL status | |
612 */ | |
613 HAL_StatusTypeDef FSMC_NAND_AttributeSpace_Timing_Init(FSMC_NAND_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank) | |
614 { | |
615 uint32_t tmpr = 0U; | |
616 | |
617 /* Check the parameters */ | |
618 assert_param(IS_FSMC_SETUP_TIME(Timing->SetupTime)); | |
619 assert_param(IS_FSMC_WAIT_TIME(Timing->WaitSetupTime)); | |
620 assert_param(IS_FSMC_HOLD_TIME(Timing->HoldSetupTime)); | |
621 assert_param(IS_FSMC_HIZ_TIME(Timing->HiZSetupTime)); | |
622 | |
623 if(Bank == FSMC_NAND_BANK2) | |
624 { | |
625 /* Get the NAND bank 2 register value */ | |
626 tmpr = Device->PATT2; | |
627 } | |
628 else | |
629 { | |
630 /* Get the NAND bank 3 register value */ | |
631 tmpr = Device->PATT3; | |
632 } | |
633 | |
634 /* Clear ATTSETx, ATTWAITx, ATTHOLDx and ATTHIZx bits */ | |
635 tmpr &= ((uint32_t)~(FSMC_PATT2_ATTSET2 | FSMC_PATT2_ATTWAIT2 | FSMC_PATT2_ATTHOLD2 | \ | |
636 FSMC_PATT2_ATTHIZ2)); | |
637 | |
638 /* Set FSMC_NAND device timing parameters */ | |
639 tmpr |= (uint32_t)(Timing->SetupTime |\ | |
640 ((Timing->WaitSetupTime) << 8U) |\ | |
641 ((Timing->HoldSetupTime) << 16U) |\ | |
642 ((Timing->HiZSetupTime) << 24U) | |
643 ); | |
644 | |
645 if(Bank == FSMC_NAND_BANK2) | |
646 { | |
647 /* NAND bank 2 registers configuration */ | |
648 Device->PATT2 = tmpr; | |
649 } | |
650 else | |
651 { | |
652 /* NAND bank 3 registers configuration */ | |
653 Device->PATT3 = tmpr; | |
654 } | |
655 | |
656 return HAL_OK; | |
657 } | |
658 | |
659 /** | |
660 * @brief DeInitializes the FSMC_NAND device | |
661 * @param Device Pointer to NAND device instance | |
662 * @param Bank NAND bank number | |
663 * @retval HAL status | |
664 */ | |
665 HAL_StatusTypeDef FSMC_NAND_DeInit(FSMC_NAND_TypeDef *Device, uint32_t Bank) | |
666 { | |
667 /* Disable the NAND Bank */ | |
668 __FSMC_NAND_DISABLE(Device, Bank); | |
669 | |
670 /* De-initialize the NAND Bank */ | |
671 if(Bank == FSMC_NAND_BANK2) | |
672 { | |
673 /* Set the FSMC_NAND_BANK2 registers to their reset values */ | |
674 Device->PCR2 = 0x00000018U; | |
675 Device->SR2 = 0x00000040U; | |
676 Device->PMEM2 = 0xFCFCFCFCU; | |
677 Device->PATT2 = 0xFCFCFCFCU; | |
678 } | |
679 /* FSMC_Bank3_NAND */ | |
680 else | |
681 { | |
682 /* Set the FSMC_NAND_BANK3 registers to their reset values */ | |
683 Device->PCR3 = 0x00000018U; | |
684 Device->SR3 = 0x00000040U; | |
685 Device->PMEM3 = 0xFCFCFCFCU; | |
686 Device->PATT3 = 0xFCFCFCFCU; | |
687 } | |
688 | |
689 return HAL_OK; | |
690 } | |
691 /** | |
692 * @} | |
693 */ | |
694 | |
695 /** @addtogroup FSMC_LL_NAND_Private_Functions_Group2 | |
696 * @brief management functions | |
697 * | |
698 @verbatim | |
699 ============================================================================== | |
700 ##### FSMC_NAND Control functions ##### | |
701 ============================================================================== | |
702 [..] | |
703 This subsection provides a set of functions allowing to control dynamically | |
704 the FSMC NAND interface. | |
705 | |
706 @endverbatim | |
707 * @{ | |
708 */ | |
709 | |
710 /** | |
711 * @brief Enables dynamically FSMC_NAND ECC feature. | |
712 * @param Device Pointer to NAND device instance | |
713 * @param Bank NAND bank number | |
714 * @retval HAL status | |
715 */ | |
716 HAL_StatusTypeDef FSMC_NAND_ECC_Enable(FSMC_NAND_TypeDef *Device, uint32_t Bank) | |
717 { | |
718 /* Enable ECC feature */ | |
719 if(Bank == FSMC_NAND_BANK2) | |
720 { | |
721 Device->PCR2 |= FSMC_PCR2_ECCEN; | |
722 } | |
723 else | |
724 { | |
725 Device->PCR3 |= FSMC_PCR3_ECCEN; | |
726 } | |
727 | |
728 return HAL_OK; | |
729 } | |
730 | |
731 /** | |
732 * @brief Disables dynamically FSMC_NAND ECC feature. | |
733 * @param Device Pointer to NAND device instance | |
734 * @param Bank NAND bank number | |
735 * @retval HAL status | |
736 */ | |
737 HAL_StatusTypeDef FSMC_NAND_ECC_Disable(FSMC_NAND_TypeDef *Device, uint32_t Bank) | |
738 { | |
739 /* Disable ECC feature */ | |
740 if(Bank == FSMC_NAND_BANK2) | |
741 { | |
742 Device->PCR2 &= ~FSMC_PCR2_ECCEN; | |
743 } | |
744 else | |
745 { | |
746 Device->PCR3 &= ~FSMC_PCR3_ECCEN; | |
747 } | |
748 | |
749 return HAL_OK; | |
750 } | |
751 | |
752 /** | |
753 * @brief Disables dynamically FSMC_NAND ECC feature. | |
754 * @param Device Pointer to NAND device instance | |
755 * @param ECCval Pointer to ECC value | |
756 * @param Bank NAND bank number | |
757 * @param Timeout Timeout wait value | |
758 * @retval HAL status | |
759 */ | |
760 HAL_StatusTypeDef FSMC_NAND_GetECC(FSMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, uint32_t Timeout) | |
761 { | |
762 uint32_t tickstart = 0U; | |
763 | |
764 /* Check the parameters */ | |
765 assert_param(IS_FSMC_NAND_DEVICE(Device)); | |
766 assert_param(IS_FSMC_NAND_BANK(Bank)); | |
767 | |
768 /* Get tick */ | |
769 tickstart = HAL_GetTick(); | |
770 | |
771 /* Wait until FIFO is empty */ | |
772 while(__FSMC_NAND_GET_FLAG(Device, Bank, FSMC_FLAG_FEMPT) == RESET) | |
773 { | |
774 /* Check for the Timeout */ | |
775 if(Timeout != HAL_MAX_DELAY) | |
776 { | |
777 if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout)) | |
778 { | |
779 return HAL_TIMEOUT; | |
780 } | |
781 } | |
782 } | |
783 | |
784 if(Bank == FSMC_NAND_BANK2) | |
785 { | |
786 /* Get the ECCR2 register value */ | |
787 *ECCval = (uint32_t)Device->ECCR2; | |
788 } | |
789 else | |
790 { | |
791 /* Get the ECCR3 register value */ | |
792 *ECCval = (uint32_t)Device->ECCR3; | |
793 } | |
794 | |
795 return HAL_OK; | |
796 } | |
797 | |
798 /** | |
799 * @} | |
800 */ | |
801 | |
802 /** | |
803 * @} | |
804 */ | |
805 | |
806 /** @addtogroup FSMC_LL_PCCARD | |
807 * @brief PCCARD Controller functions | |
808 * | |
809 @verbatim | |
810 ============================================================================== | |
811 ##### How to use PCCARD device driver ##### | |
812 ============================================================================== | |
813 [..] | |
814 This driver contains a set of APIs to interface with the FSMC PCCARD bank in order | |
815 to run the PCCARD/compact flash external devices. | |
816 | |
817 (+) FSMC PCCARD bank reset using the function FSMC_PCCARD_DeInit() | |
818 (+) FSMC PCCARD bank control configuration using the function FSMC_PCCARD_Init() | |
819 (+) FSMC PCCARD bank common space timing configuration using the function | |
820 FSMC_PCCARD_CommonSpace_Timing_Init() | |
821 (+) FSMC PCCARD bank attribute space timing configuration using the function | |
822 FSMC_PCCARD_AttributeSpace_Timing_Init() | |
823 (+) FSMC PCCARD bank IO space timing configuration using the function | |
824 FSMC_PCCARD_IOSpace_Timing_Init() | |
825 | |
826 @endverbatim | |
827 * @{ | |
828 */ | |
829 | |
830 /** @addtogroup FSMC_LL_PCCARD_Private_Functions_Group1 | |
831 * @brief Initialization and Configuration functions | |
832 * | |
833 @verbatim | |
834 ============================================================================== | |
835 ##### Initialization and de_initialization functions ##### | |
836 ============================================================================== | |
837 [..] | |
838 This section provides functions allowing to: | |
839 (+) Initialize and configure the FSMC PCCARD interface | |
840 (+) De-initialize the FSMC PCCARD interface | |
841 (+) Configure the FSMC clock and associated GPIOs | |
842 | |
843 @endverbatim | |
844 * @{ | |
845 */ | |
846 | |
847 /** | |
848 * @brief Initializes the FSMC_PCCARD device according to the specified | |
849 * control parameters in the FSMC_PCCARD_HandleTypeDef | |
850 * @param Device Pointer to PCCARD device instance | |
851 * @param Init Pointer to PCCARD Initialization structure | |
852 * @retval HAL status | |
853 */ | |
854 HAL_StatusTypeDef FSMC_PCCARD_Init(FSMC_PCCARD_TypeDef *Device, FSMC_PCCARD_InitTypeDef *Init) | |
855 { | |
856 uint32_t tmpr = 0U; | |
857 | |
858 /* Check the parameters */ | |
859 assert_param(IS_FSMC_WAIT_FEATURE(Init->Waitfeature)); | |
860 assert_param(IS_FSMC_TCLR_TIME(Init->TCLRSetupTime)); | |
861 assert_param(IS_FSMC_TAR_TIME(Init->TARSetupTime)); | |
862 | |
863 /* Get PCCARD control register value */ | |
864 tmpr = Device->PCR4; | |
865 | |
866 /* Clear TAR, TCLR, PWAITEN and PWID bits */ | |
867 tmpr &= ((uint32_t)~(FSMC_PCR4_TAR | FSMC_PCR4_TCLR | FSMC_PCR4_PWAITEN | \ | |
868 FSMC_PCR4_PWID | FSMC_PCR4_PTYP)); | |
869 | |
870 /* Set FSMC_PCCARD device control parameters */ | |
871 tmpr |= (uint32_t)(Init->Waitfeature |\ | |
872 FSMC_NAND_PCC_MEM_BUS_WIDTH_16 |\ | |
873 (Init->TCLRSetupTime << 9U) |\ | |
874 (Init->TARSetupTime << 13U)); | |
875 | |
876 Device->PCR4 = tmpr; | |
877 | |
878 return HAL_OK; | |
879 } | |
880 | |
881 /** | |
882 * @brief Initializes the FSMC_PCCARD Common space Timing according to the specified | |
883 * parameters in the FSMC_NAND_PCC_TimingTypeDef | |
884 * @param Device Pointer to PCCARD device instance | |
885 * @param Timing Pointer to PCCARD timing structure | |
886 * @retval HAL status | |
887 */ | |
888 HAL_StatusTypeDef FSMC_PCCARD_CommonSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing) | |
889 { | |
890 uint32_t tmpr = 0U; | |
891 | |
892 /* Check the parameters */ | |
893 assert_param(IS_FSMC_SETUP_TIME(Timing->SetupTime)); | |
894 assert_param(IS_FSMC_WAIT_TIME(Timing->WaitSetupTime)); | |
895 assert_param(IS_FSMC_HOLD_TIME(Timing->HoldSetupTime)); | |
896 assert_param(IS_FSMC_HIZ_TIME(Timing->HiZSetupTime)); | |
897 | |
898 /* Get PCCARD common space timing register value */ | |
899 tmpr = Device->PMEM4; | |
900 | |
901 /* Clear MEMSETx, MEMWAITx, MEMHOLDx and MEMHIZx bits */ | |
902 tmpr &= ((uint32_t)~(FSMC_PMEM4_MEMSET4 | FSMC_PMEM4_MEMWAIT4 | FSMC_PMEM4_MEMHOLD4 | \ | |
903 FSMC_PMEM4_MEMHIZ4)); | |
904 /* Set PCCARD timing parameters */ | |
905 tmpr |= (uint32_t)((Timing->SetupTime |\ | |
906 ((Timing->WaitSetupTime) << 8U) |\ | |
907 (Timing->HoldSetupTime) << 16U) |\ | |
908 ((Timing->HiZSetupTime) << 24U)); | |
909 | |
910 Device->PMEM4 = tmpr; | |
911 | |
912 return HAL_OK; | |
913 } | |
914 | |
915 /** | |
916 * @brief Initializes the FSMC_PCCARD Attribute space Timing according to the specified | |
917 * parameters in the FSMC_NAND_PCC_TimingTypeDef | |
918 * @param Device Pointer to PCCARD device instance | |
919 * @param Timing Pointer to PCCARD timing structure | |
920 * @retval HAL status | |
921 */ | |
922 HAL_StatusTypeDef FSMC_PCCARD_AttributeSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing) | |
923 { | |
924 uint32_t tmpr = 0U; | |
925 | |
926 /* Check the parameters */ | |
927 assert_param(IS_FSMC_SETUP_TIME(Timing->SetupTime)); | |
928 assert_param(IS_FSMC_WAIT_TIME(Timing->WaitSetupTime)); | |
929 assert_param(IS_FSMC_HOLD_TIME(Timing->HoldSetupTime)); | |
930 assert_param(IS_FSMC_HIZ_TIME(Timing->HiZSetupTime)); | |
931 | |
932 /* Get PCCARD timing parameters */ | |
933 tmpr = Device->PATT4; | |
934 | |
935 /* Clear ATTSETx, ATTWAITx, ATTHOLDx and ATTHIZx bits */ | |
936 tmpr &= ((uint32_t)~(FSMC_PATT4_ATTSET4 | FSMC_PATT4_ATTWAIT4 | FSMC_PATT4_ATTHOLD4 | \ | |
937 FSMC_PATT4_ATTHIZ4)); | |
938 | |
939 /* Set PCCARD timing parameters */ | |
940 tmpr |= (uint32_t)(Timing->SetupTime |\ | |
941 ((Timing->WaitSetupTime) << 8U) |\ | |
942 ((Timing->HoldSetupTime) << 16U) |\ | |
943 ((Timing->HiZSetupTime) << 24U)); | |
944 Device->PATT4 = tmpr; | |
945 | |
946 return HAL_OK; | |
947 } | |
948 | |
949 /** | |
950 * @brief Initializes the FSMC_PCCARD IO space Timing according to the specified | |
951 * parameters in the FSMC_NAND_PCC_TimingTypeDef | |
952 * @param Device Pointer to PCCARD device instance | |
953 * @param Timing Pointer to PCCARD timing structure | |
954 * @retval HAL status | |
955 */ | |
956 HAL_StatusTypeDef FSMC_PCCARD_IOSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing) | |
957 { | |
958 uint32_t tmpr = 0U; | |
959 | |
960 /* Check the parameters */ | |
961 assert_param(IS_FSMC_SETUP_TIME(Timing->SetupTime)); | |
962 assert_param(IS_FSMC_WAIT_TIME(Timing->WaitSetupTime)); | |
963 assert_param(IS_FSMC_HOLD_TIME(Timing->HoldSetupTime)); | |
964 assert_param(IS_FSMC_HIZ_TIME(Timing->HiZSetupTime)); | |
965 | |
966 /* Get FSMC_PCCARD device timing parameters */ | |
967 tmpr = Device->PIO4; | |
968 | |
969 /* Clear IOSET4, IOWAIT4, IOHOLD4 and IOHIZ4 bits */ | |
970 tmpr &= ((uint32_t)~(FSMC_PIO4_IOSET4 | FSMC_PIO4_IOWAIT4 | FSMC_PIO4_IOHOLD4 | \ | |
971 FSMC_PIO4_IOHIZ4)); | |
972 | |
973 /* Set FSMC_PCCARD device timing parameters */ | |
974 tmpr |= (uint32_t)(Timing->SetupTime |\ | |
975 ((Timing->WaitSetupTime) << 8U) |\ | |
976 ((Timing->HoldSetupTime) << 16U) |\ | |
977 ((Timing->HiZSetupTime) << 24U)); | |
978 | |
979 Device->PIO4 = tmpr; | |
980 | |
981 return HAL_OK; | |
982 } | |
983 | |
984 /** | |
985 * @brief DeInitializes the FSMC_PCCARD device | |
986 * @param Device Pointer to PCCARD device instance | |
987 * @retval HAL status | |
988 */ | |
989 HAL_StatusTypeDef FSMC_PCCARD_DeInit(FSMC_PCCARD_TypeDef *Device) | |
990 { | |
991 /* Disable the FSMC_PCCARD device */ | |
992 __FSMC_PCCARD_DISABLE(Device); | |
993 | |
994 /* De-initialize the FSMC_PCCARD device */ | |
995 Device->PCR4 = 0x00000018U; | |
996 Device->SR4 = 0x00000000U; | |
997 Device->PMEM4 = 0xFCFCFCFCU; | |
998 Device->PATT4 = 0xFCFCFCFCU; | |
999 Device->PIO4 = 0xFCFCFCFCU; | |
1000 | |
1001 return HAL_OK; | |
1002 } | |
1003 /** | |
1004 * @} | |
1005 */ | |
1006 | |
1007 /** | |
1008 * @} | |
1009 */ | |
1010 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */ | |
1011 | |
1012 /** | |
1013 * @} | |
1014 */ | |
1015 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F412Zx || STM32F412Vx || STM32F413xx || STM32F423xx */ | |
1016 #endif /* HAL_SRAM_MODULE_ENABLED || HAL_NOR_MODULE_ENABLED || HAL_NAND_MODULE_ENABLED || HAL_PCCARD_MODULE_ENABLED */ | |
1017 | |
1018 /** | |
1019 * @} | |
1020 */ | |
1021 | |
1022 /** | |
1023 * @} | |
1024 */ | |
1025 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |