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Added current STM32 standandard libraries in version independend folder structure
author Ideenmodellierer
date Sun, 17 Feb 2019 21:12:22 +0100
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127:1369f8660eaa 128:c78bcbd5deda
1 /**
2 ******************************************************************************
3 * @file stm32f4xx_ll_dma.c
4 * @author MCD Application Team
5 * @brief DMA LL module driver.
6 ******************************************************************************
7 * @attention
8 *
9 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
10 *
11 * Redistribution and use in source and binary forms, with or without modification,
12 * are permitted provided that the following conditions are met:
13 * 1. Redistributions of source code must retain the above copyright notice,
14 * this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright notice,
16 * this list of conditions and the following disclaimer in the documentation
17 * and/or other materials provided with the distribution.
18 * 3. Neither the name of STMicroelectronics nor the names of its contributors
19 * may be used to endorse or promote products derived from this software
20 * without specific prior written permission.
21 *
22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
23 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
25 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
29 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32 *
33 ******************************************************************************
34 */
35 #if defined(USE_FULL_LL_DRIVER)
36
37 /* Includes ------------------------------------------------------------------*/
38 #include "stm32f4xx_ll_dma.h"
39 #include "stm32f4xx_ll_bus.h"
40 #ifdef USE_FULL_ASSERT
41 #include "stm32_assert.h"
42 #else
43 #define assert_param(expr) ((void)0U)
44 #endif
45
46 /** @addtogroup STM32F4xx_LL_Driver
47 * @{
48 */
49
50 #if defined (DMA1) || defined (DMA2)
51
52 /** @defgroup DMA_LL DMA
53 * @{
54 */
55
56 /* Private types -------------------------------------------------------------*/
57 /* Private variables ---------------------------------------------------------*/
58 /* Private constants ---------------------------------------------------------*/
59 /* Private macros ------------------------------------------------------------*/
60 /** @addtogroup DMA_LL_Private_Macros
61 * @{
62 */
63 #define IS_LL_DMA_DIRECTION(__VALUE__) (((__VALUE__) == LL_DMA_DIRECTION_PERIPH_TO_MEMORY) || \
64 ((__VALUE__) == LL_DMA_DIRECTION_MEMORY_TO_PERIPH) || \
65 ((__VALUE__) == LL_DMA_DIRECTION_MEMORY_TO_MEMORY))
66
67 #define IS_LL_DMA_MODE(__VALUE__) (((__VALUE__) == LL_DMA_MODE_NORMAL) || \
68 ((__VALUE__) == LL_DMA_MODE_CIRCULAR) || \
69 ((__VALUE__) == LL_DMA_MODE_PFCTRL))
70
71 #define IS_LL_DMA_PERIPHINCMODE(__VALUE__) (((__VALUE__) == LL_DMA_PERIPH_INCREMENT) || \
72 ((__VALUE__) == LL_DMA_PERIPH_NOINCREMENT))
73
74 #define IS_LL_DMA_MEMORYINCMODE(__VALUE__) (((__VALUE__) == LL_DMA_MEMORY_INCREMENT) || \
75 ((__VALUE__) == LL_DMA_MEMORY_NOINCREMENT))
76
77 #define IS_LL_DMA_PERIPHDATASIZE(__VALUE__) (((__VALUE__) == LL_DMA_PDATAALIGN_BYTE) || \
78 ((__VALUE__) == LL_DMA_PDATAALIGN_HALFWORD) || \
79 ((__VALUE__) == LL_DMA_PDATAALIGN_WORD))
80
81 #define IS_LL_DMA_MEMORYDATASIZE(__VALUE__) (((__VALUE__) == LL_DMA_MDATAALIGN_BYTE) || \
82 ((__VALUE__) == LL_DMA_MDATAALIGN_HALFWORD) || \
83 ((__VALUE__) == LL_DMA_MDATAALIGN_WORD))
84
85 #define IS_LL_DMA_NBDATA(__VALUE__) ((__VALUE__) <= 0x0000FFFFU)
86
87 #define IS_LL_DMA_CHANNEL(__VALUE__) (((__VALUE__) == LL_DMA_CHANNEL_0) || \
88 ((__VALUE__) == LL_DMA_CHANNEL_1) || \
89 ((__VALUE__) == LL_DMA_CHANNEL_2) || \
90 ((__VALUE__) == LL_DMA_CHANNEL_3) || \
91 ((__VALUE__) == LL_DMA_CHANNEL_4) || \
92 ((__VALUE__) == LL_DMA_CHANNEL_5) || \
93 ((__VALUE__) == LL_DMA_CHANNEL_6) || \
94 ((__VALUE__) == LL_DMA_CHANNEL_7))
95
96 #define IS_LL_DMA_PRIORITY(__VALUE__) (((__VALUE__) == LL_DMA_PRIORITY_LOW) || \
97 ((__VALUE__) == LL_DMA_PRIORITY_MEDIUM) || \
98 ((__VALUE__) == LL_DMA_PRIORITY_HIGH) || \
99 ((__VALUE__) == LL_DMA_PRIORITY_VERYHIGH))
100
101 #define IS_LL_DMA_ALL_STREAM_INSTANCE(INSTANCE, STREAM) ((((INSTANCE) == DMA1) && \
102 (((STREAM) == LL_DMA_STREAM_0) || \
103 ((STREAM) == LL_DMA_STREAM_1) || \
104 ((STREAM) == LL_DMA_STREAM_2) || \
105 ((STREAM) == LL_DMA_STREAM_3) || \
106 ((STREAM) == LL_DMA_STREAM_4) || \
107 ((STREAM) == LL_DMA_STREAM_5) || \
108 ((STREAM) == LL_DMA_STREAM_6) || \
109 ((STREAM) == LL_DMA_STREAM_7) || \
110 ((STREAM) == LL_DMA_STREAM_ALL))) ||\
111 (((INSTANCE) == DMA2) && \
112 (((STREAM) == LL_DMA_STREAM_0) || \
113 ((STREAM) == LL_DMA_STREAM_1) || \
114 ((STREAM) == LL_DMA_STREAM_2) || \
115 ((STREAM) == LL_DMA_STREAM_3) || \
116 ((STREAM) == LL_DMA_STREAM_4) || \
117 ((STREAM) == LL_DMA_STREAM_5) || \
118 ((STREAM) == LL_DMA_STREAM_6) || \
119 ((STREAM) == LL_DMA_STREAM_7) || \
120 ((STREAM) == LL_DMA_STREAM_ALL))))
121
122 #define IS_LL_DMA_FIFO_MODE_STATE(STATE) (((STATE) == LL_DMA_FIFOMODE_DISABLE ) || \
123 ((STATE) == LL_DMA_FIFOMODE_ENABLE))
124
125 #define IS_LL_DMA_FIFO_THRESHOLD(THRESHOLD) (((THRESHOLD) == LL_DMA_FIFOTHRESHOLD_1_4) || \
126 ((THRESHOLD) == LL_DMA_FIFOTHRESHOLD_1_2) || \
127 ((THRESHOLD) == LL_DMA_FIFOTHRESHOLD_3_4) || \
128 ((THRESHOLD) == LL_DMA_FIFOTHRESHOLD_FULL))
129
130 #define IS_LL_DMA_MEMORY_BURST(BURST) (((BURST) == LL_DMA_MBURST_SINGLE) || \
131 ((BURST) == LL_DMA_MBURST_INC4) || \
132 ((BURST) == LL_DMA_MBURST_INC8) || \
133 ((BURST) == LL_DMA_MBURST_INC16))
134
135 #define IS_LL_DMA_PERIPHERAL_BURST(BURST) (((BURST) == LL_DMA_PBURST_SINGLE) || \
136 ((BURST) == LL_DMA_PBURST_INC4) || \
137 ((BURST) == LL_DMA_PBURST_INC8) || \
138 ((BURST) == LL_DMA_PBURST_INC16))
139
140 /**
141 * @}
142 */
143
144 /* Private function prototypes -----------------------------------------------*/
145
146 /* Exported functions --------------------------------------------------------*/
147 /** @addtogroup DMA_LL_Exported_Functions
148 * @{
149 */
150
151 /** @addtogroup DMA_LL_EF_Init
152 * @{
153 */
154
155 /**
156 * @brief De-initialize the DMA registers to their default reset values.
157 * @param DMAx DMAx Instance
158 * @param Stream This parameter can be one of the following values:
159 * @arg @ref LL_DMA_STREAM_0
160 * @arg @ref LL_DMA_STREAM_1
161 * @arg @ref LL_DMA_STREAM_2
162 * @arg @ref LL_DMA_STREAM_3
163 * @arg @ref LL_DMA_STREAM_4
164 * @arg @ref LL_DMA_STREAM_5
165 * @arg @ref LL_DMA_STREAM_6
166 * @arg @ref LL_DMA_STREAM_7
167 * @arg @ref LL_DMA_STREAM_ALL
168 * @retval An ErrorStatus enumeration value:
169 * - SUCCESS: DMA registers are de-initialized
170 * - ERROR: DMA registers are not de-initialized
171 */
172 uint32_t LL_DMA_DeInit(DMA_TypeDef *DMAx, uint32_t Stream)
173 {
174 DMA_Stream_TypeDef *tmp = (DMA_Stream_TypeDef *)DMA1_Stream0;
175 ErrorStatus status = SUCCESS;
176
177 /* Check the DMA Instance DMAx and Stream parameters*/
178 assert_param(IS_LL_DMA_ALL_STREAM_INSTANCE(DMAx, Stream));
179
180 if (Stream == LL_DMA_STREAM_ALL)
181 {
182 if (DMAx == DMA1)
183 {
184 /* Force reset of DMA clock */
185 LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_DMA1);
186
187 /* Release reset of DMA clock */
188 LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_DMA1);
189 }
190 else if (DMAx == DMA2)
191 {
192 /* Force reset of DMA clock */
193 LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_DMA2);
194
195 /* Release reset of DMA clock */
196 LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_DMA2);
197 }
198 else
199 {
200 status = ERROR;
201 }
202 }
203 else
204 {
205 /* Disable the selected Stream */
206 LL_DMA_DisableStream(DMAx,Stream);
207
208 /* Get the DMA Stream Instance */
209 tmp = (DMA_Stream_TypeDef *)(__LL_DMA_GET_STREAM_INSTANCE(DMAx, Stream));
210
211 /* Reset DMAx_Streamy configuration register */
212 LL_DMA_WriteReg(tmp, CR, 0U);
213
214 /* Reset DMAx_Streamy remaining bytes register */
215 LL_DMA_WriteReg(tmp, NDTR, 0U);
216
217 /* Reset DMAx_Streamy peripheral address register */
218 LL_DMA_WriteReg(tmp, PAR, 0U);
219
220 /* Reset DMAx_Streamy memory address register */
221 LL_DMA_WriteReg(tmp, M0AR, 0U);
222
223 /* Reset DMAx_Streamy memory address register */
224 LL_DMA_WriteReg(tmp, M1AR, 0U);
225
226 /* Reset DMAx_Streamy FIFO control register */
227 LL_DMA_WriteReg(tmp, FCR, 0x00000021U);
228
229 /* Reset Channel register field for DMAx Stream*/
230 LL_DMA_SetChannelSelection(DMAx, Stream, LL_DMA_CHANNEL_0);
231
232 if(Stream == LL_DMA_STREAM_0)
233 {
234 /* Reset the Stream0 pending flags */
235 DMAx->LIFCR = 0x0000003FU;
236 }
237 else if(Stream == LL_DMA_STREAM_1)
238 {
239 /* Reset the Stream1 pending flags */
240 DMAx->LIFCR = 0x00000F40U;
241 }
242 else if(Stream == LL_DMA_STREAM_2)
243 {
244 /* Reset the Stream2 pending flags */
245 DMAx->LIFCR = 0x003F0000U;
246 }
247 else if(Stream == LL_DMA_STREAM_3)
248 {
249 /* Reset the Stream3 pending flags */
250 DMAx->LIFCR = 0x0F400000U;
251 }
252 else if(Stream == LL_DMA_STREAM_4)
253 {
254 /* Reset the Stream4 pending flags */
255 DMAx->HIFCR = 0x0000003FU;
256 }
257 else if(Stream == LL_DMA_STREAM_5)
258 {
259 /* Reset the Stream5 pending flags */
260 DMAx->HIFCR = 0x00000F40U;
261 }
262 else if(Stream == LL_DMA_STREAM_6)
263 {
264 /* Reset the Stream6 pending flags */
265 DMAx->HIFCR = 0x003F0000U;
266 }
267 else if(Stream == LL_DMA_STREAM_7)
268 {
269 /* Reset the Stream7 pending flags */
270 DMAx->HIFCR = 0x0F400000U;
271 }
272 else
273 {
274 status = ERROR;
275 }
276 }
277
278 return status;
279 }
280
281 /**
282 * @brief Initialize the DMA registers according to the specified parameters in DMA_InitStruct.
283 * @note To convert DMAx_Streamy Instance to DMAx Instance and Streamy, use helper macros :
284 * @arg @ref __LL_DMA_GET_INSTANCE
285 * @arg @ref __LL_DMA_GET_STREAM
286 * @param DMAx DMAx Instance
287 * @param Stream This parameter can be one of the following values:
288 * @arg @ref LL_DMA_STREAM_0
289 * @arg @ref LL_DMA_STREAM_1
290 * @arg @ref LL_DMA_STREAM_2
291 * @arg @ref LL_DMA_STREAM_3
292 * @arg @ref LL_DMA_STREAM_4
293 * @arg @ref LL_DMA_STREAM_5
294 * @arg @ref LL_DMA_STREAM_6
295 * @arg @ref LL_DMA_STREAM_7
296 * @param DMA_InitStruct pointer to a @ref LL_DMA_InitTypeDef structure.
297 * @retval An ErrorStatus enumeration value:
298 * - SUCCESS: DMA registers are initialized
299 * - ERROR: Not applicable
300 */
301 uint32_t LL_DMA_Init(DMA_TypeDef *DMAx, uint32_t Stream, LL_DMA_InitTypeDef *DMA_InitStruct)
302 {
303 /* Check the DMA Instance DMAx and Stream parameters*/
304 assert_param(IS_LL_DMA_ALL_STREAM_INSTANCE(DMAx, Stream));
305
306 /* Check the DMA parameters from DMA_InitStruct */
307 assert_param(IS_LL_DMA_DIRECTION(DMA_InitStruct->Direction));
308 assert_param(IS_LL_DMA_MODE(DMA_InitStruct->Mode));
309 assert_param(IS_LL_DMA_PERIPHINCMODE(DMA_InitStruct->PeriphOrM2MSrcIncMode));
310 assert_param(IS_LL_DMA_MEMORYINCMODE(DMA_InitStruct->MemoryOrM2MDstIncMode));
311 assert_param(IS_LL_DMA_PERIPHDATASIZE(DMA_InitStruct->PeriphOrM2MSrcDataSize));
312 assert_param(IS_LL_DMA_MEMORYDATASIZE(DMA_InitStruct->MemoryOrM2MDstDataSize));
313 assert_param(IS_LL_DMA_NBDATA(DMA_InitStruct->NbData));
314 assert_param(IS_LL_DMA_CHANNEL(DMA_InitStruct->Channel));
315 assert_param(IS_LL_DMA_PRIORITY(DMA_InitStruct->Priority));
316 assert_param(IS_LL_DMA_FIFO_MODE_STATE(DMA_InitStruct->FIFOMode));
317 /* Check the memory burst, peripheral burst and FIFO threshold parameters only
318 when FIFO mode is enabled */
319 if(DMA_InitStruct->FIFOMode != LL_DMA_FIFOMODE_DISABLE)
320 {
321 assert_param(IS_LL_DMA_FIFO_THRESHOLD(DMA_InitStruct->FIFOThreshold));
322 assert_param(IS_LL_DMA_MEMORY_BURST(DMA_InitStruct->MemBurst));
323 assert_param(IS_LL_DMA_PERIPHERAL_BURST(DMA_InitStruct->PeriphBurst));
324 }
325
326 /*---------------------------- DMAx SxCR Configuration ------------------------
327 * Configure DMAx_Streamy: data transfer direction, data transfer mode,
328 * peripheral and memory increment mode,
329 * data size alignment and priority level with parameters :
330 * - Direction: DMA_SxCR_DIR[1:0] bits
331 * - Mode: DMA_SxCR_CIRC bit
332 * - PeriphOrM2MSrcIncMode: DMA_SxCR_PINC bit
333 * - MemoryOrM2MDstIncMode: DMA_SxCR_MINC bit
334 * - PeriphOrM2MSrcDataSize: DMA_SxCR_PSIZE[1:0] bits
335 * - MemoryOrM2MDstDataSize: DMA_SxCR_MSIZE[1:0] bits
336 * - Priority: DMA_SxCR_PL[1:0] bits
337 */
338 LL_DMA_ConfigTransfer(DMAx, Stream, DMA_InitStruct->Direction | \
339 DMA_InitStruct->Mode | \
340 DMA_InitStruct->PeriphOrM2MSrcIncMode | \
341 DMA_InitStruct->MemoryOrM2MDstIncMode | \
342 DMA_InitStruct->PeriphOrM2MSrcDataSize | \
343 DMA_InitStruct->MemoryOrM2MDstDataSize | \
344 DMA_InitStruct->Priority
345 );
346
347 if(DMA_InitStruct->FIFOMode != LL_DMA_FIFOMODE_DISABLE)
348 {
349 /*---------------------------- DMAx SxFCR Configuration ------------------------
350 * Configure DMAx_Streamy: fifo mode and fifo threshold with parameters :
351 * - FIFOMode: DMA_SxFCR_DMDIS bit
352 * - FIFOThreshold: DMA_SxFCR_FTH[1:0] bits
353 */
354 LL_DMA_ConfigFifo(DMAx, Stream, DMA_InitStruct->FIFOMode, DMA_InitStruct->FIFOThreshold);
355
356 /*---------------------------- DMAx SxCR Configuration --------------------------
357 * Configure DMAx_Streamy: memory burst transfer with parameters :
358 * - MemBurst: DMA_SxCR_MBURST[1:0] bits
359 */
360 LL_DMA_SetMemoryBurstxfer(DMAx,Stream,DMA_InitStruct->MemBurst);
361
362 /*---------------------------- DMAx SxCR Configuration --------------------------
363 * Configure DMAx_Streamy: peripheral burst transfer with parameters :
364 * - PeriphBurst: DMA_SxCR_PBURST[1:0] bits
365 */
366 LL_DMA_SetPeriphBurstxfer(DMAx,Stream,DMA_InitStruct->PeriphBurst);
367 }
368
369 /*-------------------------- DMAx SxM0AR Configuration --------------------------
370 * Configure the memory or destination base address with parameter :
371 * - MemoryOrM2MDstAddress: DMA_SxM0AR_M0A[31:0] bits
372 */
373 LL_DMA_SetMemoryAddress(DMAx, Stream, DMA_InitStruct->MemoryOrM2MDstAddress);
374
375 /*-------------------------- DMAx SxPAR Configuration ---------------------------
376 * Configure the peripheral or source base address with parameter :
377 * - PeriphOrM2MSrcAddress: DMA_SxPAR_PA[31:0] bits
378 */
379 LL_DMA_SetPeriphAddress(DMAx, Stream, DMA_InitStruct->PeriphOrM2MSrcAddress);
380
381 /*--------------------------- DMAx SxNDTR Configuration -------------------------
382 * Configure the peripheral base address with parameter :
383 * - NbData: DMA_SxNDT[15:0] bits
384 */
385 LL_DMA_SetDataLength(DMAx, Stream, DMA_InitStruct->NbData);
386
387 /*--------------------------- DMA SxCR_CHSEL Configuration ----------------------
388 * Configure the peripheral base address with parameter :
389 * - PeriphRequest: DMA_SxCR_CHSEL[2:0] bits
390 */
391 LL_DMA_SetChannelSelection(DMAx, Stream, DMA_InitStruct->Channel);
392
393 return SUCCESS;
394 }
395
396 /**
397 * @brief Set each @ref LL_DMA_InitTypeDef field to default value.
398 * @param DMA_InitStruct Pointer to a @ref LL_DMA_InitTypeDef structure.
399 * @retval None
400 */
401 void LL_DMA_StructInit(LL_DMA_InitTypeDef *DMA_InitStruct)
402 {
403 /* Set DMA_InitStruct fields to default values */
404 DMA_InitStruct->PeriphOrM2MSrcAddress = 0x00000000U;
405 DMA_InitStruct->MemoryOrM2MDstAddress = 0x00000000U;
406 DMA_InitStruct->Direction = LL_DMA_DIRECTION_PERIPH_TO_MEMORY;
407 DMA_InitStruct->Mode = LL_DMA_MODE_NORMAL;
408 DMA_InitStruct->PeriphOrM2MSrcIncMode = LL_DMA_PERIPH_NOINCREMENT;
409 DMA_InitStruct->MemoryOrM2MDstIncMode = LL_DMA_MEMORY_NOINCREMENT;
410 DMA_InitStruct->PeriphOrM2MSrcDataSize = LL_DMA_PDATAALIGN_BYTE;
411 DMA_InitStruct->MemoryOrM2MDstDataSize = LL_DMA_MDATAALIGN_BYTE;
412 DMA_InitStruct->NbData = 0x00000000U;
413 DMA_InitStruct->Channel = LL_DMA_CHANNEL_0;
414 DMA_InitStruct->Priority = LL_DMA_PRIORITY_LOW;
415 DMA_InitStruct->FIFOMode = LL_DMA_FIFOMODE_DISABLE;
416 DMA_InitStruct->FIFOThreshold = LL_DMA_FIFOTHRESHOLD_1_4;
417 DMA_InitStruct->MemBurst = LL_DMA_MBURST_SINGLE;
418 DMA_InitStruct->PeriphBurst = LL_DMA_PBURST_SINGLE;
419 }
420
421 /**
422 * @}
423 */
424
425 /**
426 * @}
427 */
428
429 /**
430 * @}
431 */
432
433 #endif /* DMA1 || DMA2 */
434
435 /**
436 * @}
437 */
438
439 #endif /* USE_FULL_LL_DRIVER */
440
441 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/