Mercurial > public > ostc4

comparison Common/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_adc.c @ 128:c78bcbd5deda FlipDisplay

Find changesets by keywords (author, files, the commit message), revision number or hash, or revset expression.
Added current STM32 standandard libraries in version independend folder structure
author Ideenmodellierer
date Sun, 17 Feb 2019 21:12:22 +0100
parents
children
comparison
equal deleted inserted replaced
127:1369f8660eaa 128:c78bcbd5deda
1 /**
2 ******************************************************************************
3 * @file stm32f4xx_ll_adc.c
4 * @author MCD Application Team
5 * @brief ADC LL module driver
6 ******************************************************************************
7 * @attention
8 *
9 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
10 *
11 * Redistribution and use in source and binary forms, with or without modification,
12 * are permitted provided that the following conditions are met:
13 * 1. Redistributions of source code must retain the above copyright notice,
14 * this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright notice,
16 * this list of conditions and the following disclaimer in the documentation
17 * and/or other materials provided with the distribution.
18 * 3. Neither the name of STMicroelectronics nor the names of its contributors
19 * may be used to endorse or promote products derived from this software
20 * without specific prior written permission.
21 *
22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
23 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
25 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
29 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32 *
33 ******************************************************************************
34 */
35 #if defined(USE_FULL_LL_DRIVER)
36
37 /* Includes ------------------------------------------------------------------*/
38 #include "stm32f4xx_ll_adc.h"
39 #include "stm32f4xx_ll_bus.h"
40
41 #ifdef USE_FULL_ASSERT
42 #include "stm32_assert.h"
43 #else
44 #define assert_param(expr) ((void)0U)
45 #endif
46
47 /** @addtogroup STM32F4xx_LL_Driver
48 * @{
49 */
50
51 #if defined (ADC1) || defined (ADC2) || defined (ADC3)
52
53 /** @addtogroup ADC_LL ADC
54 * @{
55 */
56
57 /* Private types -------------------------------------------------------------*/
58 /* Private variables ---------------------------------------------------------*/
59 /* Private constants ---------------------------------------------------------*/
60 /* Private macros ------------------------------------------------------------*/
61
62 /** @addtogroup ADC_LL_Private_Macros
63 * @{
64 */
65
66 /* Check of parameters for configuration of ADC hierarchical scope: */
67 /* common to several ADC instances. */
68 #define IS_LL_ADC_COMMON_CLOCK(__CLOCK__) \
69 ( ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV2) \
70 || ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV4) \
71 || ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV6) \
72 || ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV8) \
73 )
74
75 /* Check of parameters for configuration of ADC hierarchical scope: */
76 /* ADC instance. */
77 #define IS_LL_ADC_RESOLUTION(__RESOLUTION__) \
78 ( ((__RESOLUTION__) == LL_ADC_RESOLUTION_12B) \
79 || ((__RESOLUTION__) == LL_ADC_RESOLUTION_10B) \
80 || ((__RESOLUTION__) == LL_ADC_RESOLUTION_8B) \
81 || ((__RESOLUTION__) == LL_ADC_RESOLUTION_6B) \
82 )
83
84 #define IS_LL_ADC_DATA_ALIGN(__DATA_ALIGN__) \
85 ( ((__DATA_ALIGN__) == LL_ADC_DATA_ALIGN_RIGHT) \
86 || ((__DATA_ALIGN__) == LL_ADC_DATA_ALIGN_LEFT) \
87 )
88
89 #define IS_LL_ADC_SCAN_SELECTION(__SCAN_SELECTION__) \
90 ( ((__SCAN_SELECTION__) == LL_ADC_SEQ_SCAN_DISABLE) \
91 || ((__SCAN_SELECTION__) == LL_ADC_SEQ_SCAN_ENABLE) \
92 )
93
94 #define IS_LL_ADC_SEQ_SCAN_MODE(__SEQ_SCAN_MODE__) \
95 ( ((__SCAN_MODE__) == LL_ADC_SEQ_SCAN_DISABLE) \
96 || ((__SCAN_MODE__) == LL_ADC_SEQ_SCAN_ENABLE) \
97 )
98
99 /* Check of parameters for configuration of ADC hierarchical scope: */
100 /* ADC group regular */
101 #define IS_LL_ADC_REG_TRIG_SOURCE(__REG_TRIG_SOURCE__) \
102 ( ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE) \
103 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH1) \
104 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH2) \
105 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH3) \
106 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH2) \
107 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH3) \
108 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH4) \
109 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_TRGO) \
110 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_CH1) \
111 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_TRGO) \
112 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_CH4) \
113 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM5_CH1) \
114 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM5_CH2) \
115 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM5_CH3) \
116 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_CH1) \
117 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_TRGO) \
118 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_EXTI_LINE11) \
119 )
120 #define IS_LL_ADC_REG_CONTINUOUS_MODE(__REG_CONTINUOUS_MODE__) \
121 ( ((__REG_CONTINUOUS_MODE__) == LL_ADC_REG_CONV_SINGLE) \
122 || ((__REG_CONTINUOUS_MODE__) == LL_ADC_REG_CONV_CONTINUOUS) \
123 )
124
125 #define IS_LL_ADC_REG_DMA_TRANSFER(__REG_DMA_TRANSFER__) \
126 ( ((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_NONE) \
127 || ((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_LIMITED) \
128 || ((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_UNLIMITED) \
129 )
130
131 #define IS_LL_ADC_REG_FLAG_EOC_SELECTION(__REG_FLAG_EOC_SELECTION__) \
132 ( ((__REG_FLAG_EOC_SELECTION__) == LL_ADC_REG_FLAG_EOC_SEQUENCE_CONV) \
133 || ((__REG_FLAG_EOC_SELECTION__) == LL_ADC_REG_FLAG_EOC_UNITARY_CONV) \
134 )
135
136 #define IS_LL_ADC_REG_SEQ_SCAN_LENGTH(__REG_SEQ_SCAN_LENGTH__) \
137 ( ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_DISABLE) \
138 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS) \
139 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS) \
140 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS) \
141 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS) \
142 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS) \
143 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS) \
144 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS) \
145 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS) \
146 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS) \
147 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS) \
148 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS) \
149 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS) \
150 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS) \
151 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS) \
152 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS) \
153 )
154
155 #define IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE(__REG_SEQ_DISCONT_MODE__) \
156 ( ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_DISABLE) \
157 || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_1RANK) \
158 || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_2RANKS) \
159 || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_3RANKS) \
160 || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_4RANKS) \
161 || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_5RANKS) \
162 || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_6RANKS) \
163 || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_7RANKS) \
164 || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_8RANKS) \
165 )
166
167 /* Check of parameters for configuration of ADC hierarchical scope: */
168 /* ADC group injected */
169 #define IS_LL_ADC_INJ_TRIG_SOURCE(__INJ_TRIG_SOURCE__) \
170 ( ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_SOFTWARE) \
171 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_CH4) \
172 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO) \
173 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_CH1) \
174 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_TRGO) \
175 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH2) \
176 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH4) \
177 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_CH1) \
178 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_CH2) \
179 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_CH3) \
180 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_TRGO) \
181 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM5_CH4) \
182 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM5_TRGO) \
183 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_CH2) \
184 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_CH3) \
185 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_CH4) \
186 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_EXTI_LINE15) \
187 )
188
189 #define IS_LL_ADC_INJ_TRIG_EXT_EDGE(__INJ_TRIG_EXT_EDGE__) \
190 ( ((__INJ_TRIG_EXT_EDGE__) == LL_ADC_INJ_TRIG_EXT_RISING) \
191 || ((__INJ_TRIG_EXT_EDGE__) == LL_ADC_INJ_TRIG_EXT_FALLING) \
192 || ((__INJ_TRIG_EXT_EDGE__) == LL_ADC_INJ_TRIG_EXT_RISINGFALLING) \
193 )
194
195 #define IS_LL_ADC_INJ_TRIG_AUTO(__INJ_TRIG_AUTO__) \
196 ( ((__INJ_TRIG_AUTO__) == LL_ADC_INJ_TRIG_INDEPENDENT) \
197 || ((__INJ_TRIG_AUTO__) == LL_ADC_INJ_TRIG_FROM_GRP_REGULAR) \
198 )
199
200 #define IS_LL_ADC_INJ_SEQ_SCAN_LENGTH(__INJ_SEQ_SCAN_LENGTH__) \
201 ( ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_DISABLE) \
202 || ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS) \
203 || ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS) \
204 || ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS) \
205 )
206
207 #define IS_LL_ADC_INJ_SEQ_SCAN_DISCONT_MODE(__INJ_SEQ_DISCONT_MODE__) \
208 ( ((__INJ_SEQ_DISCONT_MODE__) == LL_ADC_INJ_SEQ_DISCONT_DISABLE) \
209 || ((__INJ_SEQ_DISCONT_MODE__) == LL_ADC_INJ_SEQ_DISCONT_1RANK) \
210 )
211
212 #if defined(ADC_MULTIMODE_SUPPORT)
213 /* Check of parameters for configuration of ADC hierarchical scope: */
214 /* multimode. */
215 #if defined(ADC3)
216 #define IS_LL_ADC_MULTI_MODE(__MULTI_MODE__) \
217 ( ((__MULTI_MODE__) == LL_ADC_MULTI_INDEPENDENT) \
218 || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_SIMULT) \
219 || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_INTERL) \
220 || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_INJ_SIMULT) \
221 || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_INJ_ALTERN) \
222 || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM) \
223 || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT) \
224 || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM) \
225 || ((__MULTI_MODE__) == LL_ADC_MULTI_TRIPLE_REG_SIM_INJ_SIM) \
226 || ((__MULTI_MODE__) == LL_ADC_MULTI_TRIPLE_REG_SIM_INJ_ALT) \
227 || ((__MULTI_MODE__) == LL_ADC_MULTI_TRIPLE_INJ_SIMULT) \
228 || ((__MULTI_MODE__) == LL_ADC_MULTI_TRIPLE_REG_SIMULT) \
229 || ((__MULTI_MODE__) == LL_ADC_MULTI_TRIPLE_REG_INTERL) \
230 || ((__MULTI_MODE__) == LL_ADC_MULTI_TRIPLE_INJ_ALTERN) \
231 )
232 #else
233 #define IS_LL_ADC_MULTI_MODE(__MULTI_MODE__) \
234 ( ((__MULTI_MODE__) == LL_ADC_MULTI_INDEPENDENT) \
235 || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_SIMULT) \
236 || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_INTERL) \
237 || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_INJ_SIMULT) \
238 || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_INJ_ALTERN) \
239 || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM) \
240 || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT) \
241 || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM) \
242 )
243 #endif
244
245 #define IS_LL_ADC_MULTI_DMA_TRANSFER(__MULTI_DMA_TRANSFER__) \
246 ( ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_EACH_ADC) \
247 || ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_LIMIT_1) \
248 || ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_LIMIT_2) \
249 || ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_LIMIT_3) \
250 || ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_UNLMT_1) \
251 || ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_UNLMT_2) \
252 || ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_UNLMT_3) \
253 )
254
255 #define IS_LL_ADC_MULTI_TWOSMP_DELAY(__MULTI_TWOSMP_DELAY__) \
256 ( ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES) \
257 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES) \
258 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES) \
259 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES) \
260 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES) \
261 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_10CYCLES) \
262 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_11CYCLES) \
263 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_12CYCLES) \
264 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_13CYCLES) \
265 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_14CYCLES) \
266 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_15CYCLES) \
267 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_16CYCLES) \
268 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_17CYCLES) \
269 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_18CYCLES) \
270 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_19CYCLES) \
271 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_20CYCLES) \
272 )
273
274 #define IS_LL_ADC_MULTI_MASTER_SLAVE(__MULTI_MASTER_SLAVE__) \
275 ( ((__MULTI_MASTER_SLAVE__) == LL_ADC_MULTI_MASTER) \
276 || ((__MULTI_MASTER_SLAVE__) == LL_ADC_MULTI_SLAVE) \
277 || ((__MULTI_MASTER_SLAVE__) == LL_ADC_MULTI_MASTER_SLAVE) \
278 )
279
280 #endif /* ADC_MULTIMODE_SUPPORT */
281 /**
282 * @}
283 */
284
285
286 /* Private function prototypes -----------------------------------------------*/
287
288 /* Exported functions --------------------------------------------------------*/
289 /** @addtogroup ADC_LL_Exported_Functions
290 * @{
291 */
292
293 /** @addtogroup ADC_LL_EF_Init
294 * @{
295 */
296
297 /**
298 * @brief De-initialize registers of all ADC instances belonging to
299 * the same ADC common instance to their default reset values.
300 * @param ADCxy_COMMON ADC common instance
301 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
302 * @retval An ErrorStatus enumeration value:
303 * - SUCCESS: ADC common registers are de-initialized
304 * - ERROR: not applicable
305 */
306 ErrorStatus LL_ADC_CommonDeInit(ADC_Common_TypeDef *ADCxy_COMMON)
307 {
308 /* Check the parameters */
309 assert_param(IS_ADC_COMMON_INSTANCE(ADCxy_COMMON));
310
311
312 /* Force reset of ADC clock (core clock) */
313 LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_ADC);
314
315 /* Release reset of ADC clock (core clock) */
316 LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_ADC);
317
318 return SUCCESS;
319 }
320
321 /**
322 * @brief Initialize some features of ADC common parameters
323 * (all ADC instances belonging to the same ADC common instance)
324 * and multimode (for devices with several ADC instances available).
325 * @note The setting of ADC common parameters is conditioned to
326 * ADC instances state:
327 * All ADC instances belonging to the same ADC common instance
328 * must be disabled.
329 * @param ADCxy_COMMON ADC common instance
330 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
331 * @param ADC_CommonInitStruct Pointer to a @ref LL_ADC_CommonInitTypeDef structure
332 * @retval An ErrorStatus enumeration value:
333 * - SUCCESS: ADC common registers are initialized
334 * - ERROR: ADC common registers are not initialized
335 */
336 ErrorStatus LL_ADC_CommonInit(ADC_Common_TypeDef *ADCxy_COMMON, LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct)
337 {
338 ErrorStatus status = SUCCESS;
339
340 /* Check the parameters */
341 assert_param(IS_ADC_COMMON_INSTANCE(ADCxy_COMMON));
342 assert_param(IS_LL_ADC_COMMON_CLOCK(ADC_CommonInitStruct->CommonClock));
343
344 #if defined(ADC_MULTIMODE_SUPPORT)
345 assert_param(IS_LL_ADC_MULTI_MODE(ADC_CommonInitStruct->Multimode));
346 if(ADC_CommonInitStruct->Multimode != LL_ADC_MULTI_INDEPENDENT)
347 {
348 assert_param(IS_LL_ADC_MULTI_DMA_TRANSFER(ADC_CommonInitStruct->MultiDMATransfer));
349 assert_param(IS_LL_ADC_MULTI_TWOSMP_DELAY(ADC_CommonInitStruct->MultiTwoSamplingDelay));
350 }
351 #endif /* ADC_MULTIMODE_SUPPORT */
352
353 /* Note: Hardware constraint (refer to description of functions */
354 /* "LL_ADC_SetCommonXXX()" and "LL_ADC_SetMultiXXX()"): */
355 /* On this STM32 serie, setting of these features is conditioned to */
356 /* ADC state: */
357 /* All ADC instances of the ADC common group must be disabled. */
358 if(__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(ADCxy_COMMON) == 0U)
359 {
360 /* Configuration of ADC hierarchical scope: */
361 /* - common to several ADC */
362 /* (all ADC instances belonging to the same ADC common instance) */
363 /* - Set ADC clock (conversion clock) */
364 /* - multimode (if several ADC instances available on the */
365 /* selected device) */
366 /* - Set ADC multimode configuration */
367 /* - Set ADC multimode DMA transfer */
368 /* - Set ADC multimode: delay between 2 sampling phases */
369 #if defined(ADC_MULTIMODE_SUPPORT)
370 if(ADC_CommonInitStruct->Multimode != LL_ADC_MULTI_INDEPENDENT)
371 {
372 MODIFY_REG(ADCxy_COMMON->CCR,
373 ADC_CCR_ADCPRE
374 | ADC_CCR_MULTI
375 | ADC_CCR_DMA
376 | ADC_CCR_DDS
377 | ADC_CCR_DELAY
378 ,
379 ADC_CommonInitStruct->CommonClock
380 | ADC_CommonInitStruct->Multimode
381 | ADC_CommonInitStruct->MultiDMATransfer
382 | ADC_CommonInitStruct->MultiTwoSamplingDelay
383 );
384 }
385 else
386 {
387 MODIFY_REG(ADCxy_COMMON->CCR,
388 ADC_CCR_ADCPRE
389 | ADC_CCR_MULTI
390 | ADC_CCR_DMA
391 | ADC_CCR_DDS
392 | ADC_CCR_DELAY
393 ,
394 ADC_CommonInitStruct->CommonClock
395 | LL_ADC_MULTI_INDEPENDENT
396 );
397 }
398 #else
399 LL_ADC_SetCommonClock(ADCxy_COMMON, ADC_CommonInitStruct->CommonClock);
400 #endif
401 }
402 else
403 {
404 /* Initialization error: One or several ADC instances belonging to */
405 /* the same ADC common instance are not disabled. */
406 status = ERROR;
407 }
408
409 return status;
410 }
411
412 /**
413 * @brief Set each @ref LL_ADC_CommonInitTypeDef field to default value.
414 * @param ADC_CommonInitStruct Pointer to a @ref LL_ADC_CommonInitTypeDef structure
415 * whose fields will be set to default values.
416 * @retval None
417 */
418 void LL_ADC_CommonStructInit(LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct)
419 {
420 /* Set ADC_CommonInitStruct fields to default values */
421 /* Set fields of ADC common */
422 /* (all ADC instances belonging to the same ADC common instance) */
423 ADC_CommonInitStruct->CommonClock = LL_ADC_CLOCK_SYNC_PCLK_DIV2;
424
425 #if defined(ADC_MULTIMODE_SUPPORT)
426 /* Set fields of ADC multimode */
427 ADC_CommonInitStruct->Multimode = LL_ADC_MULTI_INDEPENDENT;
428 ADC_CommonInitStruct->MultiDMATransfer = LL_ADC_MULTI_REG_DMA_EACH_ADC;
429 ADC_CommonInitStruct->MultiTwoSamplingDelay = LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES;
430 #endif /* ADC_MULTIMODE_SUPPORT */
431 }
432
433 /**
434 * @brief De-initialize registers of the selected ADC instance
435 * to their default reset values.
436 * @note To reset all ADC instances quickly (perform a hard reset),
437 * use function @ref LL_ADC_CommonDeInit().
438 * @param ADCx ADC instance
439 * @retval An ErrorStatus enumeration value:
440 * - SUCCESS: ADC registers are de-initialized
441 * - ERROR: ADC registers are not de-initialized
442 */
443 ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx)
444 {
445 ErrorStatus status = SUCCESS;
446
447 /* Check the parameters */
448 assert_param(IS_ADC_ALL_INSTANCE(ADCx));
449
450 /* Disable ADC instance if not already disabled. */
451 if(LL_ADC_IsEnabled(ADCx) == 1U)
452 {
453 /* Set ADC group regular trigger source to SW start to ensure to not */
454 /* have an external trigger event occurring during the conversion stop */
455 /* ADC disable process. */
456 LL_ADC_REG_SetTriggerSource(ADCx, LL_ADC_REG_TRIG_SOFTWARE);
457
458 /* Set ADC group injected trigger source to SW start to ensure to not */
459 /* have an external trigger event occurring during the conversion stop */
460 /* ADC disable process. */
461 LL_ADC_INJ_SetTriggerSource(ADCx, LL_ADC_INJ_TRIG_SOFTWARE);
462
463 /* Disable the ADC instance */
464 LL_ADC_Disable(ADCx);
465 }
466
467 /* Check whether ADC state is compliant with expected state */
468 /* (hardware requirements of bits state to reset registers below) */
469 if(READ_BIT(ADCx->CR2, ADC_CR2_ADON) == 0U)
470 {
471 /* ========== Reset ADC registers ========== */
472 /* Reset register SR */
473 CLEAR_BIT(ADCx->SR,
474 ( LL_ADC_FLAG_STRT
475 | LL_ADC_FLAG_JSTRT
476 | LL_ADC_FLAG_EOCS
477 | LL_ADC_FLAG_OVR
478 | LL_ADC_FLAG_JEOS
479 | LL_ADC_FLAG_AWD1 )
480 );
481
482 /* Reset register CR1 */
483 CLEAR_BIT(ADCx->CR1,
484 ( ADC_CR1_OVRIE | ADC_CR1_RES | ADC_CR1_AWDEN
485 | ADC_CR1_JAWDEN
486 | ADC_CR1_DISCNUM | ADC_CR1_JDISCEN | ADC_CR1_DISCEN
487 | ADC_CR1_JAUTO | ADC_CR1_AWDSGL | ADC_CR1_SCAN
488 | ADC_CR1_JEOCIE | ADC_CR1_AWDIE | ADC_CR1_EOCIE
489 | ADC_CR1_AWDCH )
490 );
491
492 /* Reset register CR2 */
493 CLEAR_BIT(ADCx->CR2,
494 ( ADC_CR2_SWSTART | ADC_CR2_EXTEN | ADC_CR2_EXTSEL
495 | ADC_CR2_JSWSTART | ADC_CR2_JEXTEN | ADC_CR2_JEXTSEL
496 | ADC_CR2_ALIGN | ADC_CR2_EOCS
497 | ADC_CR2_DDS | ADC_CR2_DMA
498 | ADC_CR2_CONT | ADC_CR2_ADON )
499 );
500
501 /* Reset register SMPR1 */
502 CLEAR_BIT(ADCx->SMPR1,
503 ( ADC_SMPR1_SMP18 | ADC_SMPR1_SMP17 | ADC_SMPR1_SMP16
504 | ADC_SMPR1_SMP15 | ADC_SMPR1_SMP14 | ADC_SMPR1_SMP13
505 | ADC_SMPR1_SMP12 | ADC_SMPR1_SMP11 | ADC_SMPR1_SMP10)
506 );
507
508 /* Reset register SMPR2 */
509 CLEAR_BIT(ADCx->SMPR2,
510 ( ADC_SMPR2_SMP9
511 | ADC_SMPR2_SMP8 | ADC_SMPR2_SMP7 | ADC_SMPR2_SMP6
512 | ADC_SMPR2_SMP5 | ADC_SMPR2_SMP4 | ADC_SMPR2_SMP3
513 | ADC_SMPR2_SMP2 | ADC_SMPR2_SMP1 | ADC_SMPR2_SMP0)
514 );
515
516 /* Reset register JOFR1 */
517 CLEAR_BIT(ADCx->JOFR1, ADC_JOFR1_JOFFSET1);
518 /* Reset register JOFR2 */
519 CLEAR_BIT(ADCx->JOFR2, ADC_JOFR2_JOFFSET2);
520 /* Reset register JOFR3 */
521 CLEAR_BIT(ADCx->JOFR3, ADC_JOFR3_JOFFSET3);
522 /* Reset register JOFR4 */
523 CLEAR_BIT(ADCx->JOFR4, ADC_JOFR4_JOFFSET4);
524
525 /* Reset register HTR */
526 SET_BIT(ADCx->HTR, ADC_HTR_HT);
527 /* Reset register LTR */
528 CLEAR_BIT(ADCx->LTR, ADC_LTR_LT);
529
530 /* Reset register SQR1 */
531 CLEAR_BIT(ADCx->SQR1,
532 ( ADC_SQR1_L
533 | ADC_SQR1_SQ16
534 | ADC_SQR1_SQ15 | ADC_SQR1_SQ14 | ADC_SQR1_SQ13)
535 );
536
537 /* Reset register SQR2 */
538 CLEAR_BIT(ADCx->SQR2,
539 ( ADC_SQR2_SQ12 | ADC_SQR2_SQ11 | ADC_SQR2_SQ10
540 | ADC_SQR2_SQ9 | ADC_SQR2_SQ8 | ADC_SQR2_SQ7)
541 );
542
543
544 /* Reset register JSQR */
545 CLEAR_BIT(ADCx->JSQR,
546 ( ADC_JSQR_JL
547 | ADC_JSQR_JSQ4 | ADC_JSQR_JSQ3
548 | ADC_JSQR_JSQ2 | ADC_JSQR_JSQ1 )
549 );
550
551 /* Reset register DR */
552 /* bits in access mode read only, no direct reset applicable */
553
554 /* Reset registers JDR1, JDR2, JDR3, JDR4 */
555 /* bits in access mode read only, no direct reset applicable */
556
557 /* Reset register CCR */
558 CLEAR_BIT(ADC->CCR, ADC_CCR_TSVREFE | ADC_CCR_ADCPRE);
559 }
560
561 return status;
562 }
563
564 /**
565 * @brief Initialize some features of ADC instance.
566 * @note These parameters have an impact on ADC scope: ADC instance.
567 * Affects both group regular and group injected (availability
568 * of ADC group injected depends on STM32 families).
569 * Refer to corresponding unitary functions into
570 * @ref ADC_LL_EF_Configuration_ADC_Instance .
571 * @note The setting of these parameters by function @ref LL_ADC_Init()
572 * is conditioned to ADC state:
573 * ADC instance must be disabled.
574 * This condition is applied to all ADC features, for efficiency
575 * and compatibility over all STM32 families. However, the different
576 * features can be set under different ADC state conditions
577 * (setting possible with ADC enabled without conversion on going,
578 * ADC enabled with conversion on going, ...)
579 * Each feature can be updated afterwards with a unitary function
580 * and potentially with ADC in a different state than disabled,
581 * refer to description of each function for setting
582 * conditioned to ADC state.
583 * @note After using this function, some other features must be configured
584 * using LL unitary functions.
585 * The minimum configuration remaining to be done is:
586 * - Set ADC group regular or group injected sequencer:
587 * map channel on the selected sequencer rank.
588 * Refer to function @ref LL_ADC_REG_SetSequencerRanks().
589 * - Set ADC channel sampling time
590 * Refer to function LL_ADC_SetChannelSamplingTime();
591 * @param ADCx ADC instance
592 * @param ADC_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure
593 * @retval An ErrorStatus enumeration value:
594 * - SUCCESS: ADC registers are initialized
595 * - ERROR: ADC registers are not initialized
596 */
597 ErrorStatus LL_ADC_Init(ADC_TypeDef *ADCx, LL_ADC_InitTypeDef *ADC_InitStruct)
598 {
599 ErrorStatus status = SUCCESS;
600
601 /* Check the parameters */
602 assert_param(IS_ADC_ALL_INSTANCE(ADCx));
603
604 assert_param(IS_LL_ADC_RESOLUTION(ADC_InitStruct->Resolution));
605 assert_param(IS_LL_ADC_DATA_ALIGN(ADC_InitStruct->DataAlignment));
606 assert_param(IS_LL_ADC_SCAN_SELECTION(ADC_InitStruct->SequencersScanMode));
607
608 /* Note: Hardware constraint (refer to description of this function): */
609 /* ADC instance must be disabled. */
610 if(LL_ADC_IsEnabled(ADCx) == 0U)
611 {
612 /* Configuration of ADC hierarchical scope: */
613 /* - ADC instance */
614 /* - Set ADC data resolution */
615 /* - Set ADC conversion data alignment */
616 MODIFY_REG(ADCx->CR1,
617 ADC_CR1_RES
618 | ADC_CR1_SCAN
619 ,
620 ADC_InitStruct->Resolution
621 | ADC_InitStruct->SequencersScanMode
622 );
623
624 MODIFY_REG(ADCx->CR2,
625 ADC_CR2_ALIGN
626 ,
627 ADC_InitStruct->DataAlignment
628 );
629
630 }
631 else
632 {
633 /* Initialization error: ADC instance is not disabled. */
634 status = ERROR;
635 }
636 return status;
637 }
638
639 /**
640 * @brief Set each @ref LL_ADC_InitTypeDef field to default value.
641 * @param ADC_InitStruct Pointer to a @ref LL_ADC_InitTypeDef structure
642 * whose fields will be set to default values.
643 * @retval None
644 */
645 void LL_ADC_StructInit(LL_ADC_InitTypeDef *ADC_InitStruct)
646 {
647 /* Set ADC_InitStruct fields to default values */
648 /* Set fields of ADC instance */
649 ADC_InitStruct->Resolution = LL_ADC_RESOLUTION_12B;
650 ADC_InitStruct->DataAlignment = LL_ADC_DATA_ALIGN_RIGHT;
651
652 /* Enable scan mode to have a generic behavior with ADC of other */
653 /* STM32 families, without this setting available: */
654 /* ADC group regular sequencer and ADC group injected sequencer depend */
655 /* only of their own configuration. */
656 ADC_InitStruct->SequencersScanMode = LL_ADC_SEQ_SCAN_ENABLE;
657
658 }
659
660 /**
661 * @brief Initialize some features of ADC group regular.
662 * @note These parameters have an impact on ADC scope: ADC group regular.
663 * Refer to corresponding unitary functions into
664 * @ref ADC_LL_EF_Configuration_ADC_Group_Regular
665 * (functions with prefix "REG").
666 * @note The setting of these parameters by function @ref LL_ADC_Init()
667 * is conditioned to ADC state:
668 * ADC instance must be disabled.
669 * This condition is applied to all ADC features, for efficiency
670 * and compatibility over all STM32 families. However, the different
671 * features can be set under different ADC state conditions
672 * (setting possible with ADC enabled without conversion on going,
673 * ADC enabled with conversion on going, ...)
674 * Each feature can be updated afterwards with a unitary function
675 * and potentially with ADC in a different state than disabled,
676 * refer to description of each function for setting
677 * conditioned to ADC state.
678 * @note After using this function, other features must be configured
679 * using LL unitary functions.
680 * The minimum configuration remaining to be done is:
681 * - Set ADC group regular or group injected sequencer:
682 * map channel on the selected sequencer rank.
683 * Refer to function @ref LL_ADC_REG_SetSequencerRanks().
684 * - Set ADC channel sampling time
685 * Refer to function LL_ADC_SetChannelSamplingTime();
686 * @param ADCx ADC instance
687 * @param ADC_REG_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure
688 * @retval An ErrorStatus enumeration value:
689 * - SUCCESS: ADC registers are initialized
690 * - ERROR: ADC registers are not initialized
691 */
692 ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *ADCx, LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct)
693 {
694 ErrorStatus status = SUCCESS;
695
696 /* Check the parameters */
697 assert_param(IS_ADC_ALL_INSTANCE(ADCx));
698 assert_param(IS_LL_ADC_REG_TRIG_SOURCE(ADC_REG_InitStruct->TriggerSource));
699 assert_param(IS_LL_ADC_REG_SEQ_SCAN_LENGTH(ADC_REG_InitStruct->SequencerLength));
700 if(ADC_REG_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE)
701 {
702 assert_param(IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE(ADC_REG_InitStruct->SequencerDiscont));
703 }
704 assert_param(IS_LL_ADC_REG_CONTINUOUS_MODE(ADC_REG_InitStruct->ContinuousMode));
705 assert_param(IS_LL_ADC_REG_DMA_TRANSFER(ADC_REG_InitStruct->DMATransfer));
706
707 /* Note: Hardware constraint (refer to description of this function): */
708 /* ADC instance must be disabled. */
709 if(LL_ADC_IsEnabled(ADCx) == 0U)
710 {
711 /* Configuration of ADC hierarchical scope: */
712 /* - ADC group regular */
713 /* - Set ADC group regular trigger source */
714 /* - Set ADC group regular sequencer length */
715 /* - Set ADC group regular sequencer discontinuous mode */
716 /* - Set ADC group regular continuous mode */
717 /* - Set ADC group regular conversion data transfer: no transfer or */
718 /* transfer by DMA, and DMA requests mode */
719 /* Note: On this STM32 serie, ADC trigger edge is set when starting */
720 /* ADC conversion. */
721 /* Refer to function @ref LL_ADC_REG_StartConversionExtTrig(). */
722 if(ADC_REG_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE)
723 {
724 MODIFY_REG(ADCx->CR1,
725 ADC_CR1_DISCEN
726 | ADC_CR1_DISCNUM
727 ,
728 ADC_REG_InitStruct->SequencerLength
729 | ADC_REG_InitStruct->SequencerDiscont
730 );
731 }
732 else
733 {
734 MODIFY_REG(ADCx->CR1,
735 ADC_CR1_DISCEN
736 | ADC_CR1_DISCNUM
737 ,
738 ADC_REG_InitStruct->SequencerLength
739 | LL_ADC_REG_SEQ_DISCONT_DISABLE
740 );
741 }
742
743 MODIFY_REG(ADCx->CR2,
744 ADC_CR2_EXTSEL
745 | ADC_CR2_EXTEN
746 | ADC_CR2_CONT
747 | ADC_CR2_DMA
748 | ADC_CR2_DDS
749 ,
750 (ADC_REG_InitStruct->TriggerSource & ADC_CR2_EXTSEL)
751 | ADC_REG_InitStruct->ContinuousMode
752 | ADC_REG_InitStruct->DMATransfer
753 );
754
755 /* Set ADC group regular sequencer length and scan direction */
756 /* Note: Hardware constraint (refer to description of this function): */
757 /* Note: If ADC instance feature scan mode is disabled */
758 /* (refer to ADC instance initialization structure */
759 /* parameter @ref SequencersScanMode */
760 /* or function @ref LL_ADC_SetSequencersScanMode() ), */
761 /* this parameter is discarded. */
762 LL_ADC_REG_SetSequencerLength(ADCx, ADC_REG_InitStruct->SequencerLength);
763 }
764 else
765 {
766 /* Initialization error: ADC instance is not disabled. */
767 status = ERROR;
768 }
769 return status;
770 }
771
772 /**
773 * @brief Set each @ref LL_ADC_REG_InitTypeDef field to default value.
774 * @param ADC_REG_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure
775 * whose fields will be set to default values.
776 * @retval None
777 */
778 void LL_ADC_REG_StructInit(LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct)
779 {
780 /* Set ADC_REG_InitStruct fields to default values */
781 /* Set fields of ADC group regular */
782 /* Note: On this STM32 serie, ADC trigger edge is set when starting */
783 /* ADC conversion. */
784 /* Refer to function @ref LL_ADC_REG_StartConversionExtTrig(). */
785 ADC_REG_InitStruct->TriggerSource = LL_ADC_REG_TRIG_SOFTWARE;
786 ADC_REG_InitStruct->SequencerLength = LL_ADC_REG_SEQ_SCAN_DISABLE;
787 ADC_REG_InitStruct->SequencerDiscont = LL_ADC_REG_SEQ_DISCONT_DISABLE;
788 ADC_REG_InitStruct->ContinuousMode = LL_ADC_REG_CONV_SINGLE;
789 ADC_REG_InitStruct->DMATransfer = LL_ADC_REG_DMA_TRANSFER_NONE;
790 }
791
792 /**
793 * @brief Initialize some features of ADC group injected.
794 * @note These parameters have an impact on ADC scope: ADC group injected.
795 * Refer to corresponding unitary functions into
796 * @ref ADC_LL_EF_Configuration_ADC_Group_Regular
797 * (functions with prefix "INJ").
798 * @note The setting of these parameters by function @ref LL_ADC_Init()
799 * is conditioned to ADC state:
800 * ADC instance must be disabled.
801 * This condition is applied to all ADC features, for efficiency
802 * and compatibility over all STM32 families. However, the different
803 * features can be set under different ADC state conditions
804 * (setting possible with ADC enabled without conversion on going,
805 * ADC enabled with conversion on going, ...)
806 * Each feature can be updated afterwards with a unitary function
807 * and potentially with ADC in a different state than disabled,
808 * refer to description of each function for setting
809 * conditioned to ADC state.
810 * @note After using this function, other features must be configured
811 * using LL unitary functions.
812 * The minimum configuration remaining to be done is:
813 * - Set ADC group injected sequencer:
814 * map channel on the selected sequencer rank.
815 * Refer to function @ref LL_ADC_INJ_SetSequencerRanks().
816 * - Set ADC channel sampling time
817 * Refer to function LL_ADC_SetChannelSamplingTime();
818 * @param ADCx ADC instance
819 * @param ADC_INJ_InitStruct Pointer to a @ref LL_ADC_INJ_InitTypeDef structure
820 * @retval An ErrorStatus enumeration value:
821 * - SUCCESS: ADC registers are initialized
822 * - ERROR: ADC registers are not initialized
823 */
824 ErrorStatus LL_ADC_INJ_Init(ADC_TypeDef *ADCx, LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct)
825 {
826 ErrorStatus status = SUCCESS;
827
828 /* Check the parameters */
829 assert_param(IS_ADC_ALL_INSTANCE(ADCx));
830 assert_param(IS_LL_ADC_INJ_TRIG_SOURCE(ADC_INJ_InitStruct->TriggerSource));
831 assert_param(IS_LL_ADC_INJ_SEQ_SCAN_LENGTH(ADC_INJ_InitStruct->SequencerLength));
832 if(ADC_INJ_InitStruct->SequencerLength != LL_ADC_INJ_SEQ_SCAN_DISABLE)
833 {
834 assert_param(IS_LL_ADC_INJ_SEQ_SCAN_DISCONT_MODE(ADC_INJ_InitStruct->SequencerDiscont));
835 }
836 assert_param(IS_LL_ADC_INJ_TRIG_AUTO(ADC_INJ_InitStruct->TrigAuto));
837
838 /* Note: Hardware constraint (refer to description of this function): */
839 /* ADC instance must be disabled. */
840 if(LL_ADC_IsEnabled(ADCx) == 0U)
841 {
842 /* Configuration of ADC hierarchical scope: */
843 /* - ADC group injected */
844 /* - Set ADC group injected trigger source */
845 /* - Set ADC group injected sequencer length */
846 /* - Set ADC group injected sequencer discontinuous mode */
847 /* - Set ADC group injected conversion trigger: independent or */
848 /* from ADC group regular */
849 /* Note: On this STM32 serie, ADC trigger edge is set when starting */
850 /* ADC conversion. */
851 /* Refer to function @ref LL_ADC_INJ_StartConversionExtTrig(). */
852 if(ADC_INJ_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE)
853 {
854 MODIFY_REG(ADCx->CR1,
855 ADC_CR1_JDISCEN
856 | ADC_CR1_JAUTO
857 ,
858 ADC_INJ_InitStruct->SequencerDiscont
859 | ADC_INJ_InitStruct->TrigAuto
860 );
861 }
862 else
863 {
864 MODIFY_REG(ADCx->CR1,
865 ADC_CR1_JDISCEN
866 | ADC_CR1_JAUTO
867 ,
868 LL_ADC_REG_SEQ_DISCONT_DISABLE
869 | ADC_INJ_InitStruct->TrigAuto
870 );
871 }
872
873 MODIFY_REG(ADCx->CR2,
874 ADC_CR2_JEXTSEL
875 | ADC_CR2_JEXTEN
876 ,
877 (ADC_INJ_InitStruct->TriggerSource & ADC_CR2_JEXTSEL)
878 );
879
880 /* Note: Hardware constraint (refer to description of this function): */
881 /* Note: If ADC instance feature scan mode is disabled */
882 /* (refer to ADC instance initialization structure */
883 /* parameter @ref SequencersScanMode */
884 /* or function @ref LL_ADC_SetSequencersScanMode() ), */
885 /* this parameter is discarded. */
886 LL_ADC_INJ_SetSequencerLength(ADCx, ADC_INJ_InitStruct->SequencerLength);
887 }
888 else
889 {
890 /* Initialization error: ADC instance is not disabled. */
891 status = ERROR;
892 }
893 return status;
894 }
895
896 /**
897 * @brief Set each @ref LL_ADC_INJ_InitTypeDef field to default value.
898 * @param ADC_INJ_InitStruct Pointer to a @ref LL_ADC_INJ_InitTypeDef structure
899 * whose fields will be set to default values.
900 * @retval None
901 */
902 void LL_ADC_INJ_StructInit(LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct)
903 {
904 /* Set ADC_INJ_InitStruct fields to default values */
905 /* Set fields of ADC group injected */
906 ADC_INJ_InitStruct->TriggerSource = LL_ADC_INJ_TRIG_SOFTWARE;
907 ADC_INJ_InitStruct->SequencerLength = LL_ADC_INJ_SEQ_SCAN_DISABLE;
908 ADC_INJ_InitStruct->SequencerDiscont = LL_ADC_INJ_SEQ_DISCONT_DISABLE;
909 ADC_INJ_InitStruct->TrigAuto = LL_ADC_INJ_TRIG_INDEPENDENT;
910 }
911
912 /**
913 * @}
914 */
915
916 /**
917 * @}
918 */
919
920 /**
921 * @}
922 */
923
924 #endif /* ADC1 || ADC2 || ADC3 */
925
926 /**
927 * @}
928 */
929
930 #endif /* USE_FULL_LL_DRIVER */
931
932 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/